Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2814	1		T1	3		T2	4		T3	2
all_pins[1]	2814	1		T1	3		T2	4		T3	2
all_pins[2]	2814	1		T1	3		T2	4		T3	2
all_pins[3]	2814	1		T1	3		T2	4		T3	2
all_pins[4]	2814	1		T1	3		T2	4		T3	2
all_pins[5]	2814	1		T1	3		T2	4		T3	2
all_pins[6]	2814	1		T1	3		T2	4		T3	2
all_pins[7]	2814	1		T1	3		T2	4		T3	2
all_pins[8]	2814	1		T1	3		T2	4		T3	2
all_pins[9]	2814	1		T1	3		T2	4		T3	2
all_pins[10]	2814	1		T1	3		T2	4		T3	2
all_pins[11]	2814	1		T1	3		T2	4		T3	2
all_pins[12]	2814	1		T1	3		T2	4		T3	2
all_pins[13]	2814	1		T1	3		T2	4		T3	2
all_pins[14]	2814	1		T1	3		T2	4		T3	2
all_pins[15]	2814	1		T1	3		T2	4		T3	2
all_pins[16]	2814	1		T1	3		T2	4		T3	2
all_pins[17]	2814	1		T1	3		T2	4		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	49796	1		T1	53		T2	72		T3	36
values[0x1]	856	1		T1	1		T7	1		T27	1
transitions[0x0=>0x1]	692	1		T1	1		T7	1		T27	1
transitions[0x1=>0x0]	698	1		T1	1		T7	1		T27	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2688	1		T1	3		T2	4		T3	2
all_pins[0]	values[0x1]	126	1		T7	1		T27	1		T45	1
all_pins[0]	transitions[0x0=>0x1]	121	1		T7	1		T27	1		T45	1
all_pins[0]	transitions[0x1=>0x0]	121	1		T1	1		T22	1		T23	1
all_pins[1]	values[0x0]	2688	1		T1	2		T2	4		T3	2
all_pins[1]	values[0x1]	126	1		T1	1		T22	1		T23	1
all_pins[1]	transitions[0x0=>0x1]	121	1		T1	1		T22	1		T23	1
all_pins[1]	transitions[0x1=>0x0]	25	1		T66	1		T64	4		T65	1
all_pins[2]	values[0x0]	2784	1		T1	3		T2	4		T3	2
all_pins[2]	values[0x1]	30	1		T66	1		T64	6		T65	2
all_pins[2]	transitions[0x0=>0x1]	23	1		T66	1		T64	2		T65	2
all_pins[2]	transitions[0x1=>0x0]	33	1		T63	2		T64	1		T245	3
all_pins[3]	values[0x0]	2774	1		T1	3		T2	4		T3	2
all_pins[3]	values[0x1]	40	1		T63	2		T64	5		T245	3
all_pins[3]	transitions[0x0=>0x1]	28	1		T63	2		T64	3		T245	3
all_pins[3]	transitions[0x1=>0x0]	37	1		T66	1		T63	2		T65	1
all_pins[4]	values[0x0]	2765	1		T1	3		T2	4		T3	2
all_pins[4]	values[0x1]	49	1		T66	1		T63	2		T64	2
all_pins[4]	transitions[0x0=>0x1]	31	1		T63	2		T64	1		T65	1
all_pins[4]	transitions[0x1=>0x0]	19	1		T64	1		T240	3		T239	2
all_pins[5]	values[0x0]	2777	1		T1	3		T2	4		T3	2
all_pins[5]	values[0x1]	37	1		T66	1		T64	2		T240	4
all_pins[5]	transitions[0x0=>0x1]	29	1		T66	1		T240	4		T239	3
all_pins[5]	transitions[0x1=>0x0]	25	1		T63	1		T239	2		T250	1
all_pins[6]	values[0x0]	2781	1		T1	3		T2	4		T3	2
all_pins[6]	values[0x1]	33	1		T63	1		T64	2		T239	2
all_pins[6]	transitions[0x0=>0x1]	26	1		T63	1		T64	1		T239	2
all_pins[6]	transitions[0x1=>0x0]	28	1		T64	3		T65	2		T245	1
all_pins[7]	values[0x0]	2779	1		T1	3		T2	4		T3	2
all_pins[7]	values[0x1]	35	1		T64	4		T65	2		T245	1
all_pins[7]	transitions[0x0=>0x1]	31	1		T64	4		T245	1		T241	1
all_pins[7]	transitions[0x1=>0x0]	23	1		T66	1		T64	1		T65	1
all_pins[8]	values[0x0]	2787	1		T1	3		T2	4		T3	2
all_pins[8]	values[0x1]	27	1		T66	1		T64	1		T65	3
all_pins[8]	transitions[0x0=>0x1]	21	1		T66	1		T64	1		T65	3
all_pins[8]	transitions[0x1=>0x0]	44	1		T66	1		T63	1		T64	1
all_pins[9]	values[0x0]	2764	1		T1	3		T2	4		T3	2
all_pins[9]	values[0x1]	50	1		T66	1		T63	1		T64	1
all_pins[9]	transitions[0x0=>0x1]	36	1		T66	1		T63	1		T64	1
all_pins[9]	transitions[0x1=>0x0]	35	1		T63	2		T64	3		T240	3
all_pins[10]	values[0x0]	2765	1		T1	3		T2	4		T3	2
all_pins[10]	values[0x1]	49	1		T63	2		T64	3		T240	3
all_pins[10]	transitions[0x0=>0x1]	37	1		T240	1		T241	3		T239	1
all_pins[10]	transitions[0x1=>0x0]	19	1		T64	1		T245	1		T241	1
all_pins[11]	values[0x0]	2783	1		T1	3		T2	4		T3	2
all_pins[11]	values[0x1]	31	1		T63	2		T64	4		T240	2
all_pins[11]	transitions[0x0=>0x1]	24	1		T63	2		T64	4		T245	1
all_pins[11]	transitions[0x1=>0x0]	40	1		T66	3		T64	1		T245	2
all_pins[12]	values[0x0]	2767	1		T1	3		T2	4		T3	2
all_pins[12]	values[0x1]	47	1		T66	3		T64	1		T240	2
all_pins[12]	transitions[0x0=>0x1]	41	1		T66	3		T64	1		T240	2
all_pins[12]	transitions[0x1=>0x0]	33	1		T64	3		T65	1		T245	1
all_pins[13]	values[0x0]	2775	1		T1	3		T2	4		T3	2
all_pins[13]	values[0x1]	39	1		T64	3		T65	1		T245	1
all_pins[13]	transitions[0x0=>0x1]	25	1		T64	3		T65	1		T245	1
all_pins[13]	transitions[0x1=>0x0]	26	1		T63	1		T64	1		T240	1
all_pins[14]	values[0x0]	2774	1		T1	3		T2	4		T3	2
all_pins[14]	values[0x1]	40	1		T63	1		T64	1		T240	1
all_pins[14]	transitions[0x0=>0x1]	28	1		T240	1		T239	1		T246	3
all_pins[14]	transitions[0x1=>0x0]	25	1		T64	2		T239	3		T250	1
all_pins[15]	values[0x0]	2777	1		T1	3		T2	4		T3	2
all_pins[15]	values[0x1]	37	1		T63	1		T64	3		T239	3
all_pins[15]	transitions[0x0=>0x1]	23	1		T63	1		T64	2		T239	3
all_pins[15]	transitions[0x1=>0x0]	22	1		T66	2		T63	1		T65	1
all_pins[16]	values[0x0]	2778	1		T1	3		T2	4		T3	2
all_pins[16]	values[0x1]	36	1		T66	2		T63	1		T64	1
all_pins[16]	transitions[0x0=>0x1]	33	1		T66	2		T63	1		T64	1
all_pins[16]	transitions[0x1=>0x0]	21	1		T66	2		T63	1		T64	1
all_pins[17]	values[0x0]	2790	1		T1	3		T2	4		T3	2
all_pins[17]	values[0x1]	24	1		T66	2		T63	1		T64	1
all_pins[17]	transitions[0x0=>0x1]	14	1		T66	1		T65	2		T245	1
all_pins[17]	transitions[0x1=>0x0]	122	1		T7	1		T27	1		T45	1