Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	154	1		T66	4		T63	4		T64	7
all_values[1]	154	1		T66	4		T63	4		T64	7
all_values[2]	154	1		T66	4		T63	4		T64	7
all_values[3]	154	1		T66	4		T63	4		T64	7
all_values[4]	154	1		T66	4		T63	4		T64	7
all_values[5]	154	1		T66	4		T63	4		T64	7
all_values[6]	154	1		T66	4		T63	4		T64	7
all_values[7]	154	1		T66	4		T63	4		T64	7
all_values[8]	154	1		T66	4		T63	4		T64	7
all_values[9]	154	1		T66	4		T63	4		T64	7
all_values[10]	154	1		T66	4		T63	4		T64	7
all_values[11]	154	1		T66	4		T63	4		T64	7
all_values[12]	154	1		T66	4		T63	4		T64	7
all_values[13]	154	1		T66	4		T63	4		T64	7
all_values[14]	154	1		T66	4		T63	4		T64	7
all_values[15]	154	1		T66	4		T63	4		T64	7
all_values[16]	154	1		T66	4		T63	4		T64	7
all_values[17]	154	1		T66	4		T63	4		T64	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1489	1		T66	41		T63	43		T64	63
auto[1]	1283	1		T66	31		T63	29		T64	63

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	467	1		T66	13		T63	15		T64	13
auto[1]	2305	1		T66	59		T63	57		T64	113

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1635	1		T66	41		T63	45		T64	76
auto[1]	1137	1		T66	31		T63	27		T64	50

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	25	1		T64	3		T240	2		T245	2
all_values[0]	auto[0]	auto[0]	auto[1]	30	1		T63	2		T65	1		T240	1
all_values[0]	auto[0]	auto[1]	auto[0]	11	1		T64	2		T245	2		T241	2
all_values[0]	auto[0]	auto[1]	auto[1]	28	1		T66	2		T64	1		T65	2
all_values[0]	auto[1]	auto[0]	auto[1]	32	1		T66	1		T65	1		T250	1
all_values[0]	auto[1]	auto[1]	auto[1]	28	1		T66	1		T63	2		T64	1
all_values[1]	auto[0]	auto[0]	auto[0]	21	1		T63	2		T64	1		T240	1
all_values[1]	auto[0]	auto[0]	auto[1]	31	1		T66	2		T63	1		T245	1
all_values[1]	auto[0]	auto[1]	auto[0]	8	1		T240	1		T253	1		T249	2
all_values[1]	auto[0]	auto[1]	auto[1]	31	1		T66	1		T64	3		T65	1
all_values[1]	auto[1]	auto[0]	auto[1]	42	1		T66	1		T63	1		T64	1
all_values[1]	auto[1]	auto[1]	auto[1]	21	1		T64	2		T65	2		T240	1
all_values[2]	auto[0]	auto[0]	auto[0]	23	1		T63	1		T64	1		T65	1
all_values[2]	auto[0]	auto[0]	auto[1]	37	1		T66	2		T63	2		T65	1
all_values[2]	auto[0]	auto[1]	auto[0]	9	1		T239	1		T246	2		T253	1
all_values[2]	auto[0]	auto[1]	auto[1]	21	1		T64	2		T240	1		T250	1
all_values[2]	auto[1]	auto[0]	auto[1]	34	1		T66	2		T63	1		T65	1
all_values[2]	auto[1]	auto[1]	auto[1]	30	1		T64	4		T65	1		T241	1
all_values[3]	auto[0]	auto[0]	auto[0]	21	1		T66	1		T63	1		T64	1
all_values[3]	auto[0]	auto[0]	auto[1]	24	1		T66	2		T64	1		T245	1
all_values[3]	auto[0]	auto[1]	auto[0]	10	1		T240	1		T241	1		T250	1
all_values[3]	auto[0]	auto[1]	auto[1]	48	1		T63	1		T64	3		T65	1
all_values[3]	auto[1]	auto[0]	auto[1]	26	1		T66	1		T63	1		T65	1
all_values[3]	auto[1]	auto[1]	auto[1]	25	1		T63	1		T64	2		T65	1
all_values[4]	auto[0]	auto[0]	auto[0]	7	1		T66	1		T64	1		T65	1
all_values[4]	auto[0]	auto[0]	auto[1]	25	1		T66	1		T63	1		T245	2
all_values[4]	auto[0]	auto[1]	auto[0]	3	1		T244	1		T254	2		-	-
all_values[4]	auto[0]	auto[1]	auto[1]	44	1		T63	1		T64	4		T65	1
all_values[4]	auto[1]	auto[0]	auto[1]	42	1		T64	2		T65	1		T240	1
all_values[4]	auto[1]	auto[1]	auto[1]	33	1		T66	2		T63	2		T65	1
all_values[5]	auto[0]	auto[0]	auto[0]	13	1		T63	1		T242	2		T246	1
all_values[5]	auto[0]	auto[0]	auto[1]	35	1		T66	1		T63	1		T64	3
all_values[5]	auto[0]	auto[1]	auto[0]	11	1		T245	1		T241	2		T247	1
all_values[5]	auto[0]	auto[1]	auto[1]	32	1		T64	1		T65	1		T240	2
all_values[5]	auto[1]	auto[0]	auto[1]	30	1		T66	1		T63	1		T64	2
all_values[5]	auto[1]	auto[1]	auto[1]	33	1		T66	2		T63	1		T64	1
all_values[6]	auto[0]	auto[0]	auto[0]	18	1		T66	1		T64	1		T240	4
all_values[6]	auto[0]	auto[0]	auto[1]	38	1		T63	1		T64	3		T65	1
all_values[6]	auto[0]	auto[1]	auto[0]	6	1		T242	3		T255	2		T244	1
all_values[6]	auto[0]	auto[1]	auto[1]	30	1		T66	1		T63	1		T64	1
all_values[6]	auto[1]	auto[0]	auto[1]	37	1		T66	2		T64	2		T65	1
all_values[6]	auto[1]	auto[1]	auto[1]	25	1		T63	2		T65	1		T239	1
all_values[7]	auto[0]	auto[0]	auto[0]	16	1		T63	1		T65	1		T242	3
all_values[7]	auto[0]	auto[0]	auto[1]	36	1		T66	1		T63	1		T64	1
all_values[7]	auto[0]	auto[1]	auto[0]	5	1		T245	1		T256	2		T244	1
all_values[7]	auto[0]	auto[1]	auto[1]	36	1		T66	1		T63	1		T64	1
all_values[7]	auto[1]	auto[0]	auto[1]	29	1		T66	1		T63	1		T64	1
all_values[7]	auto[1]	auto[1]	auto[1]	32	1		T66	1		T64	4		T65	1
all_values[8]	auto[0]	auto[0]	auto[0]	30	1		T66	1		T240	1		T241	1
all_values[8]	auto[0]	auto[0]	auto[1]	33	1		T66	1		T63	2		T64	1
all_values[8]	auto[0]	auto[1]	auto[0]	9	1		T63	1		T246	1		T247	2
all_values[8]	auto[0]	auto[1]	auto[1]	24	1		T64	2		T65	1		T241	1
all_values[8]	auto[1]	auto[0]	auto[1]	29	1		T64	3		T65	1		T240	2
all_values[8]	auto[1]	auto[1]	auto[1]	29	1		T66	2		T63	1		T64	1
all_values[9]	auto[0]	auto[0]	auto[0]	11	1		T240	1		T241	1		T248	1
all_values[9]	auto[0]	auto[0]	auto[1]	27	1		T66	1		T63	1		T64	3
all_values[9]	auto[0]	auto[1]	auto[0]	7	1		T240	1		T248	2		T251	1
all_values[9]	auto[0]	auto[1]	auto[1]	37	1		T66	1		T63	1		T64	1
all_values[9]	auto[1]	auto[0]	auto[1]	41	1		T66	2		T63	1		T64	1
all_values[9]	auto[1]	auto[1]	auto[1]	31	1		T63	1		T64	2		T245	3
all_values[10]	auto[0]	auto[0]	auto[0]	16	1		T66	1		T63	2		T65	1
all_values[10]	auto[0]	auto[0]	auto[1]	30	1		T66	1		T64	1		T245	3
all_values[10]	auto[0]	auto[1]	auto[0]	6	1		T66	1		T247	1		T255	2
all_values[10]	auto[0]	auto[1]	auto[1]	40	1		T63	1		T64	4		T65	1
all_values[10]	auto[1]	auto[0]	auto[1]	29	1		T63	1		T64	1		T65	1
all_values[10]	auto[1]	auto[1]	auto[1]	33	1		T66	1		T64	1		T65	1
all_values[11]	auto[0]	auto[0]	auto[0]	16	1		T240	1		T239	1		T242	1
all_values[11]	auto[0]	auto[0]	auto[1]	32	1		T63	1		T64	2		T65	3
all_values[11]	auto[0]	auto[1]	auto[0]	6	1		T239	1		T246	2		T255	1
all_values[11]	auto[0]	auto[1]	auto[1]	35	1		T66	3		T63	1		T64	3
all_values[11]	auto[1]	auto[0]	auto[1]	30	1		T66	1		T63	2		T64	2
all_values[11]	auto[1]	auto[1]	auto[1]	35	1		T240	1		T245	1		T241	2
all_values[12]	auto[0]	auto[0]	auto[0]	15	1		T66	1		T63	1		T240	1
all_values[12]	auto[0]	auto[0]	auto[1]	35	1		T63	1		T64	3		T65	3
all_values[12]	auto[0]	auto[1]	auto[0]	6	1		T240	1		T256	3		T254	2
all_values[12]	auto[0]	auto[1]	auto[1]	32	1		T66	1		T63	1		T64	1
all_values[12]	auto[1]	auto[0]	auto[1]	33	1		T63	1		T64	2		T65	1
all_values[12]	auto[1]	auto[1]	auto[1]	33	1		T66	2		T64	1		T241	1
all_values[13]	auto[0]	auto[0]	auto[0]	15	1		T66	1		T63	4		T64	3
all_values[13]	auto[0]	auto[0]	auto[1]	39	1		T66	1		T65	3		T240	2
all_values[13]	auto[0]	auto[1]	auto[0]	8	1		T66	1		T241	1		T250	2
all_values[13]	auto[0]	auto[1]	auto[1]	28	1		T64	2		T250	1		T242	1
all_values[13]	auto[1]	auto[0]	auto[1]	37	1		T64	1		T65	1		T240	2
all_values[13]	auto[1]	auto[1]	auto[1]	27	1		T66	1		T64	1		T245	1
all_values[14]	auto[0]	auto[0]	auto[0]	15	1		T65	1		T240	1		T241	2
all_values[14]	auto[0]	auto[0]	auto[1]	24	1		T66	1		T63	2		T64	4
all_values[14]	auto[0]	auto[1]	auto[0]	9	1		T242	1		T253	1		T247	1
all_values[14]	auto[0]	auto[1]	auto[1]	41	1		T66	1		T63	1		T240	2
all_values[14]	auto[1]	auto[0]	auto[1]	33	1		T66	1		T64	1		T240	1
all_values[14]	auto[1]	auto[1]	auto[1]	32	1		T66	1		T63	1		T64	2
all_values[15]	auto[0]	auto[0]	auto[0]	15	1		T66	4		T65	2		T245	3
all_values[15]	auto[0]	auto[0]	auto[1]	30	1		T63	1		T64	2		T65	1
all_values[15]	auto[0]	auto[1]	auto[0]	7	1		T245	1		T255	2		T243	2
all_values[15]	auto[0]	auto[1]	auto[1]	34	1		T63	1		T64	2		T240	2
all_values[15]	auto[1]	auto[0]	auto[1]	34	1		T64	1		T65	1		T240	1
all_values[15]	auto[1]	auto[1]	auto[1]	34	1		T63	2		T64	2		T240	1
all_values[16]	auto[0]	auto[0]	auto[0]	15	1		T63	1		T240	1		T245	1
all_values[16]	auto[0]	auto[0]	auto[1]	26	1		T64	3		T65	2		T241	1
all_values[16]	auto[0]	auto[1]	auto[0]	12	1		T240	1		T245	1		T241	1
all_values[16]	auto[0]	auto[1]	auto[1]	29	1		T66	2		T63	1		T240	1
all_values[16]	auto[1]	auto[0]	auto[1]	38	1		T66	1		T63	1		T64	2
all_values[16]	auto[1]	auto[1]	auto[1]	34	1		T66	1		T63	1		T64	2
all_values[17]	auto[0]	auto[0]	auto[0]	25	1		T240	3		T245	1		T239	2
all_values[17]	auto[0]	auto[0]	auto[1]	39	1		T66	1		T63	1		T64	2
all_values[17]	auto[0]	auto[1]	auto[0]	17	1		T240	1		T241	2		T250	4
all_values[17]	auto[0]	auto[1]	auto[1]	27	1		T63	1		T64	3		T65	1
all_values[17]	auto[1]	auto[0]	auto[1]	25	1		T66	1		T64	1		T65	2
all_values[17]	auto[1]	auto[1]	auto[1]	21	1		T66	2		T63	2		T64	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal