Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.86 96.13 87.57 97.19 46.88 93.35 97.36 96.58


Total test records in report: 950
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T837 /workspace/coverage/default/48.usbdev_fifo_rst.2733650229 Mar 26 02:54:02 PM PDT 24 Mar 26 02:54:04 PM PDT 24 175901611 ps
T838 /workspace/coverage/default/12.usbdev_phy_pins_sense.3000999841 Mar 26 02:53:00 PM PDT 24 Mar 26 02:53:01 PM PDT 24 28450294 ps
T839 /workspace/coverage/default/21.usbdev_out_stall.3991867919 Mar 26 02:53:03 PM PDT 24 Mar 26 02:53:11 PM PDT 24 8397839333 ps
T840 /workspace/coverage/default/15.usbdev_av_buffer.635125120 Mar 26 02:53:02 PM PDT 24 Mar 26 02:53:12 PM PDT 24 8367587762 ps
T224 /workspace/coverage/default/47.usbdev_fifo_rst.126471458 Mar 26 02:54:03 PM PDT 24 Mar 26 02:54:05 PM PDT 24 65253159 ps
T841 /workspace/coverage/default/33.usbdev_fifo_rst.3425859597 Mar 26 02:53:18 PM PDT 24 Mar 26 02:53:20 PM PDT 24 59940426 ps
T842 /workspace/coverage/default/39.usbdev_out_stall.3084748913 Mar 26 02:53:50 PM PDT 24 Mar 26 02:53:57 PM PDT 24 8375184696 ps
T843 /workspace/coverage/default/5.usbdev_setup_trans_ignored.1840500328 Mar 26 02:52:15 PM PDT 24 Mar 26 02:52:23 PM PDT 24 8356079051 ps
T844 /workspace/coverage/default/2.usbdev_pkt_received.2969292956 Mar 26 02:52:11 PM PDT 24 Mar 26 02:52:19 PM PDT 24 8380951081 ps
T845 /workspace/coverage/default/10.usbdev_enable.3417639358 Mar 26 02:52:25 PM PDT 24 Mar 26 02:52:32 PM PDT 24 8365859285 ps
T846 /workspace/coverage/default/4.usbdev_random_length_out_trans.3742411683 Mar 26 02:52:41 PM PDT 24 Mar 26 02:52:49 PM PDT 24 8376956236 ps
T158 /workspace/coverage/default/5.usbdev_in_stall.3117034096 Mar 26 02:52:26 PM PDT 24 Mar 26 02:52:33 PM PDT 24 8356966475 ps
T847 /workspace/coverage/default/7.usbdev_out_trans_nak.1250318521 Mar 26 02:52:20 PM PDT 24 Mar 26 02:52:27 PM PDT 24 8386927438 ps
T848 /workspace/coverage/default/25.usbdev_enable.2113107652 Mar 26 02:53:07 PM PDT 24 Mar 26 02:53:14 PM PDT 24 8364817869 ps
T849 /workspace/coverage/default/35.usbdev_fifo_rst.44019084 Mar 26 02:53:41 PM PDT 24 Mar 26 02:53:43 PM PDT 24 58592397 ps
T850 /workspace/coverage/default/23.usbdev_setup_trans_ignored.640896477 Mar 26 02:53:04 PM PDT 24 Mar 26 02:53:12 PM PDT 24 8362234556 ps
T851 /workspace/coverage/default/14.usbdev_out_trans_nak.3506822335 Mar 26 02:52:45 PM PDT 24 Mar 26 02:52:53 PM PDT 24 8368170047 ps
T852 /workspace/coverage/default/42.usbdev_in_trans.1849945834 Mar 26 02:54:51 PM PDT 24 Mar 26 02:54:58 PM PDT 24 8444588549 ps
T853 /workspace/coverage/default/1.usbdev_fifo_rst.3108921054 Mar 26 02:52:09 PM PDT 24 Mar 26 02:52:11 PM PDT 24 37775639 ps
T854 /workspace/coverage/default/21.usbdev_pkt_sent.3893425340 Mar 26 02:53:04 PM PDT 24 Mar 26 02:53:12 PM PDT 24 8409520907 ps
T855 /workspace/coverage/default/26.usbdev_out_stall.228869691 Mar 26 02:53:34 PM PDT 24 Mar 26 02:53:41 PM PDT 24 8370085698 ps
T856 /workspace/coverage/default/44.usbdev_max_length_out_transaction.1265016175 Mar 26 02:54:28 PM PDT 24 Mar 26 02:54:35 PM PDT 24 8404349727 ps
T857 /workspace/coverage/default/39.usbdev_phy_pins_sense.3640860802 Mar 26 02:53:52 PM PDT 24 Mar 26 02:53:52 PM PDT 24 28252683 ps
T858 /workspace/coverage/default/33.usbdev_random_length_out_trans.4097332255 Mar 26 02:53:47 PM PDT 24 Mar 26 02:53:57 PM PDT 24 8383100266 ps
T859 /workspace/coverage/default/19.usbdev_pkt_received.2574748131 Mar 26 02:53:02 PM PDT 24 Mar 26 02:53:11 PM PDT 24 8379987755 ps
T860 /workspace/coverage/default/44.usbdev_random_length_out_trans.2746479646 Mar 26 02:54:03 PM PDT 24 Mar 26 02:54:11 PM PDT 24 8378271906 ps
T861 /workspace/coverage/default/26.usbdev_smoke.3436951556 Mar 26 02:53:13 PM PDT 24 Mar 26 02:53:20 PM PDT 24 8475892963 ps
T862 /workspace/coverage/default/33.usbdev_max_length_out_transaction.2802102837 Mar 26 02:53:16 PM PDT 24 Mar 26 02:53:26 PM PDT 24 8411673973 ps
T863 /workspace/coverage/default/7.usbdev_phy_pins_sense.2726876668 Mar 26 02:52:12 PM PDT 24 Mar 26 02:52:13 PM PDT 24 27135266 ps
T864 /workspace/coverage/default/39.usbdev_pkt_sent.3348975524 Mar 26 02:53:57 PM PDT 24 Mar 26 02:54:05 PM PDT 24 8437488018 ps
T865 /workspace/coverage/default/13.usbdev_smoke.2213242759 Mar 26 02:52:44 PM PDT 24 Mar 26 02:52:52 PM PDT 24 8469816994 ps
T866 /workspace/coverage/default/49.usbdev_av_buffer.2508612939 Mar 26 02:54:02 PM PDT 24 Mar 26 02:54:10 PM PDT 24 8370413127 ps
T867 /workspace/coverage/default/4.usbdev_pkt_sent.2194256579 Mar 26 02:52:21 PM PDT 24 Mar 26 02:52:28 PM PDT 24 8400866931 ps
T868 /workspace/coverage/default/11.usbdev_setup_trans_ignored.3075173061 Mar 26 02:52:41 PM PDT 24 Mar 26 02:52:49 PM PDT 24 8360023719 ps
T869 /workspace/coverage/default/44.usbdev_out_trans_nak.1743140506 Mar 26 02:53:55 PM PDT 24 Mar 26 02:54:03 PM PDT 24 8394403222 ps
T69 /workspace/coverage/default/2.usbdev_sec_cm.2698130585 Mar 26 02:52:11 PM PDT 24 Mar 26 02:52:12 PM PDT 24 238887666 ps
T870 /workspace/coverage/default/23.usbdev_av_buffer.804964549 Mar 26 02:52:59 PM PDT 24 Mar 26 02:53:07 PM PDT 24 8374600897 ps
T871 /workspace/coverage/default/36.usbdev_pkt_received.2377118117 Mar 26 02:53:36 PM PDT 24 Mar 26 02:53:44 PM PDT 24 8405916369 ps
T872 /workspace/coverage/default/43.usbdev_random_length_out_trans.1596397509 Mar 26 02:53:55 PM PDT 24 Mar 26 02:54:04 PM PDT 24 8399549171 ps
T873 /workspace/coverage/default/38.usbdev_setup_trans_ignored.2194228697 Mar 26 02:54:00 PM PDT 24 Mar 26 02:54:10 PM PDT 24 8358836628 ps
T874 /workspace/coverage/default/35.usbdev_in_trans.2264804542 Mar 26 02:53:49 PM PDT 24 Mar 26 02:53:58 PM PDT 24 8380550537 ps
T875 /workspace/coverage/default/24.usbdev_min_length_out_transaction.4278411633 Mar 26 02:53:04 PM PDT 24 Mar 26 02:53:13 PM PDT 24 8366171512 ps
T876 /workspace/coverage/default/27.usbdev_pkt_received.3275445745 Mar 26 02:53:50 PM PDT 24 Mar 26 02:53:58 PM PDT 24 8380865706 ps
T877 /workspace/coverage/default/21.usbdev_phy_pins_sense.1894267586 Mar 26 02:53:09 PM PDT 24 Mar 26 02:53:10 PM PDT 24 28279996 ps
T878 /workspace/coverage/default/15.usbdev_pkt_sent.64138730 Mar 26 02:52:51 PM PDT 24 Mar 26 02:52:59 PM PDT 24 8392158653 ps
T879 /workspace/coverage/default/37.usbdev_max_length_out_transaction.438326166 Mar 26 02:53:54 PM PDT 24 Mar 26 02:54:02 PM PDT 24 8406174423 ps
T880 /workspace/coverage/default/13.usbdev_random_length_out_trans.1361150490 Mar 26 02:53:03 PM PDT 24 Mar 26 02:53:10 PM PDT 24 8377879510 ps
T881 /workspace/coverage/default/6.usbdev_out_trans_nak.3527577507 Mar 26 02:52:33 PM PDT 24 Mar 26 02:52:41 PM PDT 24 8383937243 ps
T882 /workspace/coverage/default/26.usbdev_pkt_sent.4037530477 Mar 26 02:53:10 PM PDT 24 Mar 26 02:53:19 PM PDT 24 8376015160 ps
T883 /workspace/coverage/default/41.usbdev_out_trans_nak.3597892843 Mar 26 02:53:54 PM PDT 24 Mar 26 02:54:01 PM PDT 24 8376108350 ps
T884 /workspace/coverage/default/5.usbdev_out_trans_nak.2203653153 Mar 26 02:52:43 PM PDT 24 Mar 26 02:52:53 PM PDT 24 8393408309 ps
T885 /workspace/coverage/default/27.usbdev_out_stall.1878177793 Mar 26 02:53:09 PM PDT 24 Mar 26 02:53:17 PM PDT 24 8399224281 ps
T886 /workspace/coverage/default/33.usbdev_out_trans_nak.3339378092 Mar 26 02:53:14 PM PDT 24 Mar 26 02:53:22 PM PDT 24 8398393021 ps
T234 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.720996684 Mar 26 01:22:09 PM PDT 24 Mar 26 01:22:13 PM PDT 24 475626209 ps
T51 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1918958227 Mar 26 01:22:10 PM PDT 24 Mar 26 01:22:13 PM PDT 24 230033200 ps
T52 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3003062022 Mar 26 01:22:21 PM PDT 24 Mar 26 01:22:23 PM PDT 24 72247055 ps
T62 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.464071147 Mar 26 01:22:18 PM PDT 24 Mar 26 01:22:19 PM PDT 24 65750677 ps
T53 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1692578265 Mar 26 01:22:22 PM PDT 24 Mar 26 01:22:24 PM PDT 24 70541960 ps
T58 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3386282218 Mar 26 01:22:23 PM PDT 24 Mar 26 01:22:26 PM PDT 24 116564590 ps
T59 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2845914098 Mar 26 01:22:20 PM PDT 24 Mar 26 01:22:21 PM PDT 24 64368618 ps
T83 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1369885747 Mar 26 01:22:19 PM PDT 24 Mar 26 01:22:20 PM PDT 24 45529202 ps
T84 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2381359260 Mar 26 01:22:13 PM PDT 24 Mar 26 01:22:14 PM PDT 24 38758189 ps
T85 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1646998757 Mar 26 01:22:17 PM PDT 24 Mar 26 01:22:18 PM PDT 24 84532119 ps
T887 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.936149223 Mar 26 01:22:12 PM PDT 24 Mar 26 01:22:14 PM PDT 24 251924097 ps
T86 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.474334545 Mar 26 01:22:26 PM PDT 24 Mar 26 01:22:28 PM PDT 24 114242244 ps
T66 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.736685982 Mar 26 01:22:22 PM PDT 24 Mar 26 01:22:23 PM PDT 24 19092090 ps
T67 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2092057665 Mar 26 01:22:07 PM PDT 24 Mar 26 01:22:08 PM PDT 24 31687606 ps
T63 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3168244229 Mar 26 01:22:31 PM PDT 24 Mar 26 01:22:32 PM PDT 24 23361005 ps
T185 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3482821582 Mar 26 01:22:18 PM PDT 24 Mar 26 01:22:19 PM PDT 24 64545935 ps
T64 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2798268095 Mar 26 01:22:10 PM PDT 24 Mar 26 01:22:11 PM PDT 24 30238309 ps
T177 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1680938773 Mar 26 01:22:20 PM PDT 24 Mar 26 01:22:22 PM PDT 24 132146072 ps
T186 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.801671044 Mar 26 01:22:08 PM PDT 24 Mar 26 01:22:09 PM PDT 24 70236705 ps
T187 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3648331898 Mar 26 01:22:05 PM PDT 24 Mar 26 01:22:08 PM PDT 24 88448859 ps
T188 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1771084687 Mar 26 01:22:19 PM PDT 24 Mar 26 01:22:20 PM PDT 24 52011551 ps
T183 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.4075706681 Mar 26 01:22:18 PM PDT 24 Mar 26 01:22:23 PM PDT 24 456739207 ps
T200 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2458908063 Mar 26 01:22:20 PM PDT 24 Mar 26 01:22:22 PM PDT 24 68984150 ps
T178 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.395685879 Mar 26 01:22:13 PM PDT 24 Mar 26 01:22:14 PM PDT 24 36254477 ps
T179 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2643098759 Mar 26 01:22:17 PM PDT 24 Mar 26 01:22:19 PM PDT 24 47653042 ps
T180 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2448623060 Mar 26 01:22:15 PM PDT 24 Mar 26 01:22:17 PM PDT 24 109516531 ps
T181 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1456793116 Mar 26 01:22:11 PM PDT 24 Mar 26 01:22:12 PM PDT 24 39587851 ps
T65 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2150653543 Mar 26 01:22:31 PM PDT 24 Mar 26 01:22:32 PM PDT 24 28943880 ps
T189 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3933420394 Mar 26 01:22:18 PM PDT 24 Mar 26 01:22:20 PM PDT 24 116455843 ps
T182 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.40031293 Mar 26 01:22:19 PM PDT 24 Mar 26 01:22:21 PM PDT 24 102194616 ps
T184 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3275637228 Mar 26 01:22:01 PM PDT 24 Mar 26 01:22:04 PM PDT 24 236715833 ps
T201 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3536298717 Mar 26 01:22:17 PM PDT 24 Mar 26 01:22:18 PM PDT 24 52301767 ps
T60 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.750837234 Mar 26 01:22:18 PM PDT 24 Mar 26 01:22:19 PM PDT 24 33108472 ps
T190 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2041174703 Mar 26 01:22:20 PM PDT 24 Mar 26 01:22:21 PM PDT 24 61316063 ps
T191 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3060061536 Mar 26 01:22:05 PM PDT 24 Mar 26 01:22:08 PM PDT 24 99506201 ps
T235 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1662902072 Mar 26 01:22:20 PM PDT 24 Mar 26 01:22:21 PM PDT 24 146613905 ps
T257 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3805138247 Mar 26 01:22:20 PM PDT 24 Mar 26 01:22:26 PM PDT 24 464481578 ps
T236 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1546996785 Mar 26 01:22:21 PM PDT 24 Mar 26 01:22:23 PM PDT 24 130466708 ps
T237 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.694847726 Mar 26 01:22:14 PM PDT 24 Mar 26 01:22:16 PM PDT 24 160475063 ps
T192 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3345406878 Mar 26 01:22:13 PM PDT 24 Mar 26 01:22:14 PM PDT 24 35599622 ps
T888 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2725285903 Mar 26 01:22:17 PM PDT 24 Mar 26 01:22:19 PM PDT 24 42319203 ps
T238 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1695947010 Mar 26 01:22:17 PM PDT 24 Mar 26 01:22:18 PM PDT 24 86835403 ps
T229 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1250684160 Mar 26 01:22:18 PM PDT 24 Mar 26 01:22:23 PM PDT 24 416145630 ps
T889 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.23674399 Mar 26 01:22:18 PM PDT 24 Mar 26 01:22:19 PM PDT 24 118995180 ps
T231 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1468454766 Mar 26 01:22:26 PM PDT 24 Mar 26 01:22:29 PM PDT 24 86296155 ps
T890 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1114653149 Mar 26 01:22:22 PM PDT 24 Mar 26 01:22:24 PM PDT 24 118118438 ps
T230 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.854026462 Mar 26 01:22:17 PM PDT 24 Mar 26 01:22:21 PM PDT 24 95638319 ps
T891 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2317606367 Mar 26 01:22:04 PM PDT 24 Mar 26 01:22:07 PM PDT 24 56132805 ps
T892 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2519733638 Mar 26 01:22:18 PM PDT 24 Mar 26 01:22:19 PM PDT 24 77203753 ps
T240 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.147096459 Mar 26 01:22:08 PM PDT 24 Mar 26 01:22:09 PM PDT 24 25877605 ps
T232 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.259783207 Mar 26 01:22:23 PM PDT 24 Mar 26 01:22:26 PM PDT 24 86034126 ps
T893 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3300708197 Mar 26 01:22:22 PM PDT 24 Mar 26 01:22:24 PM PDT 24 55775073 ps
T245 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2946083689 Mar 26 01:22:29 PM PDT 24 Mar 26 01:22:30 PM PDT 24 21723424 ps
T894 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1608648410 Mar 26 01:22:19 PM PDT 24 Mar 26 01:22:21 PM PDT 24 89906527 ps
T241 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2691877441 Mar 26 01:22:22 PM PDT 24 Mar 26 01:22:23 PM PDT 24 19612103 ps
T265 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1928990499 Mar 26 01:22:17 PM PDT 24 Mar 26 01:22:20 PM PDT 24 258924315 ps
T239 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1011284124 Mar 26 01:22:29 PM PDT 24 Mar 26 01:22:30 PM PDT 24 30941193 ps
T193 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1138601137 Mar 26 01:22:18 PM PDT 24 Mar 26 01:22:18 PM PDT 24 40406829 ps
T233 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3026918735 Mar 26 01:22:22 PM PDT 24 Mar 26 01:22:24 PM PDT 24 84857249 ps
T250 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2240470488 Mar 26 01:22:18 PM PDT 24 Mar 26 01:22:19 PM PDT 24 26602178 ps
T895 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.999846893 Mar 26 01:22:23 PM PDT 24 Mar 26 01:22:25 PM PDT 24 123628148 ps
T266 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1160420960 Mar 26 01:22:20 PM PDT 24 Mar 26 01:22:23 PM PDT 24 293262041 ps
T242 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2130553440 Mar 26 01:22:35 PM PDT 24 Mar 26 01:22:36 PM PDT 24 29590199 ps
T195 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3674060946 Mar 26 01:22:17 PM PDT 24 Mar 26 01:22:18 PM PDT 24 29844576 ps
T246 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2951016955 Mar 26 01:22:19 PM PDT 24 Mar 26 01:22:20 PM PDT 24 24175186 ps
T253 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2104482516 Mar 26 01:22:37 PM PDT 24 Mar 26 01:22:38 PM PDT 24 28065959 ps
T260 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3995076947 Mar 26 01:22:16 PM PDT 24 Mar 26 01:22:21 PM PDT 24 437803875 ps
T262 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3246557277 Mar 26 01:22:13 PM PDT 24 Mar 26 01:22:16 PM PDT 24 202205798 ps
T896 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3729938682 Mar 26 01:22:23 PM PDT 24 Mar 26 01:22:26 PM PDT 24 77151694 ps
T202 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2889810422 Mar 26 01:22:23 PM PDT 24 Mar 26 01:22:28 PM PDT 24 472185464 ps
T263 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3334737360 Mar 26 01:22:19 PM PDT 24 Mar 26 01:22:22 PM PDT 24 264103633 ps
T196 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2919348433 Mar 26 01:22:19 PM PDT 24 Mar 26 01:22:20 PM PDT 24 83937870 ps
T897 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3810989686 Mar 26 01:22:07 PM PDT 24 Mar 26 01:22:09 PM PDT 24 191947521 ps
T247 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.288813130 Mar 26 01:22:20 PM PDT 24 Mar 26 01:22:21 PM PDT 24 30891835 ps
T248 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1111944728 Mar 26 01:22:08 PM PDT 24 Mar 26 01:22:09 PM PDT 24 30172873 ps
T898 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.688261511 Mar 26 01:22:10 PM PDT 24 Mar 26 01:22:12 PM PDT 24 126116930 ps
T899 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3254937862 Mar 26 01:22:21 PM PDT 24 Mar 26 01:22:23 PM PDT 24 66037803 ps
T252 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1737960310 Mar 26 01:22:09 PM PDT 24 Mar 26 01:22:10 PM PDT 24 30126964 ps
T197 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3271032619 Mar 26 01:22:04 PM PDT 24 Mar 26 01:22:05 PM PDT 24 90599382 ps
T900 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1401427841 Mar 26 01:22:13 PM PDT 24 Mar 26 01:22:15 PM PDT 24 127420385 ps
T255 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1733928523 Mar 26 01:22:20 PM PDT 24 Mar 26 01:22:21 PM PDT 24 28761516 ps
T243 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1208631525 Mar 26 01:22:35 PM PDT 24 Mar 26 01:22:36 PM PDT 24 26172692 ps
T901 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1144300057 Mar 26 01:22:03 PM PDT 24 Mar 26 01:22:05 PM PDT 24 50020094 ps
T61 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2339520360 Mar 26 01:22:08 PM PDT 24 Mar 26 01:22:09 PM PDT 24 33446018 ps
T902 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.836434571 Mar 26 01:22:22 PM PDT 24 Mar 26 01:22:22 PM PDT 24 37509858 ps
T258 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1400808063 Mar 26 01:22:05 PM PDT 24 Mar 26 01:22:09 PM PDT 24 448241173 ps
T903 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1636079789 Mar 26 01:22:11 PM PDT 24 Mar 26 01:22:18 PM PDT 24 287529648 ps
T198 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3641896327 Mar 26 01:22:03 PM PDT 24 Mar 26 01:22:03 PM PDT 24 28116171 ps
T904 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1367671242 Mar 26 01:22:07 PM PDT 24 Mar 26 01:22:10 PM PDT 24 358926055 ps
T199 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1069360112 Mar 26 01:22:22 PM PDT 24 Mar 26 01:22:23 PM PDT 24 29802188 ps
T905 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3685459343 Mar 26 01:22:17 PM PDT 24 Mar 26 01:22:21 PM PDT 24 261452961 ps
T906 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.501012528 Mar 26 01:22:21 PM PDT 24 Mar 26 01:22:22 PM PDT 24 71290435 ps
T57 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1599218638 Mar 26 01:22:09 PM PDT 24 Mar 26 01:22:10 PM PDT 24 39134355 ps
T259 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.4011929748 Mar 26 01:22:11 PM PDT 24 Mar 26 01:22:16 PM PDT 24 464772274 ps
T249 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1613197966 Mar 26 01:22:30 PM PDT 24 Mar 26 01:22:30 PM PDT 24 27625334 ps
T907 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2707051144 Mar 26 01:22:20 PM PDT 24 Mar 26 01:22:21 PM PDT 24 37138009 ps
T908 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3111631003 Mar 26 01:22:19 PM PDT 24 Mar 26 01:22:22 PM PDT 24 82033083 ps
T909 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3449421632 Mar 26 01:22:06 PM PDT 24 Mar 26 01:22:09 PM PDT 24 83832207 ps
T910 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.668624169 Mar 26 01:22:21 PM PDT 24 Mar 26 01:22:23 PM PDT 24 56649332 ps
T911 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3237890504 Mar 26 01:22:18 PM PDT 24 Mar 26 01:22:20 PM PDT 24 126888122 ps
T912 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3343026515 Mar 26 01:22:21 PM PDT 24 Mar 26 01:22:23 PM PDT 24 103498642 ps
T251 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1520423293 Mar 26 01:22:28 PM PDT 24 Mar 26 01:22:29 PM PDT 24 19062920 ps
T913 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.649251176 Mar 26 01:22:08 PM PDT 24 Mar 26 01:22:09 PM PDT 24 26772562 ps
T914 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4232888923 Mar 26 01:22:18 PM PDT 24 Mar 26 01:22:19 PM PDT 24 57992647 ps
T915 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3283222535 Mar 26 01:22:21 PM PDT 24 Mar 26 01:22:23 PM PDT 24 60766591 ps
T916 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2160912343 Mar 26 01:22:29 PM PDT 24 Mar 26 01:22:30 PM PDT 24 23546819 ps
T917 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1561094977 Mar 26 01:22:18 PM PDT 24 Mar 26 01:22:18 PM PDT 24 28054642 ps
T918 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.658162075 Mar 26 01:22:13 PM PDT 24 Mar 26 01:22:15 PM PDT 24 43588176 ps
T919 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1783024927 Mar 26 01:22:08 PM PDT 24 Mar 26 01:22:10 PM PDT 24 44960371 ps
T264 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.865502187 Mar 26 01:22:15 PM PDT 24 Mar 26 01:22:18 PM PDT 24 239635618 ps
T256 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2043270916 Mar 26 01:22:30 PM PDT 24 Mar 26 01:22:30 PM PDT 24 28659541 ps
T920 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.473685159 Mar 26 01:22:22 PM PDT 24 Mar 26 01:22:24 PM PDT 24 65948500 ps
T921 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2954580966 Mar 26 01:22:04 PM PDT 24 Mar 26 01:22:05 PM PDT 24 87235248 ps
T922 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1597946279 Mar 26 01:22:21 PM PDT 24 Mar 26 01:22:26 PM PDT 24 477795210 ps
T923 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.4181891505 Mar 26 01:22:12 PM PDT 24 Mar 26 01:22:15 PM PDT 24 108120187 ps
T924 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1763659222 Mar 26 01:22:19 PM PDT 24 Mar 26 01:22:20 PM PDT 24 35416295 ps
T925 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3288061857 Mar 26 01:22:19 PM PDT 24 Mar 26 01:22:22 PM PDT 24 54610190 ps
T267 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3486385607 Mar 26 01:22:26 PM PDT 24 Mar 26 01:22:29 PM PDT 24 263192163 ps
T926 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.4080468730 Mar 26 01:22:22 PM PDT 24 Mar 26 01:22:24 PM PDT 24 87382754 ps
T194 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4135731404 Mar 26 01:22:26 PM PDT 24 Mar 26 01:22:26 PM PDT 24 36551066 ps
T927 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2789648307 Mar 26 01:22:18 PM PDT 24 Mar 26 01:22:19 PM PDT 24 35876370 ps
T928 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.827763345 Mar 26 01:22:12 PM PDT 24 Mar 26 01:22:16 PM PDT 24 151030262 ps
T929 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2935229434 Mar 26 01:22:19 PM PDT 24 Mar 26 01:22:21 PM PDT 24 67362373 ps
T930 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.303766013 Mar 26 01:22:10 PM PDT 24 Mar 26 01:22:13 PM PDT 24 259733061 ps
T931 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1791202191 Mar 26 01:22:14 PM PDT 24 Mar 26 01:22:15 PM PDT 24 143872911 ps
T244 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3152834910 Mar 26 01:22:21 PM PDT 24 Mar 26 01:22:22 PM PDT 24 18919118 ps
T932 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3488560712 Mar 26 01:22:30 PM PDT 24 Mar 26 01:22:31 PM PDT 24 22476733 ps
T933 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.488061472 Mar 26 01:22:19 PM PDT 24 Mar 26 01:22:21 PM PDT 24 111685998 ps
T934 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3490167779 Mar 26 01:22:13 PM PDT 24 Mar 26 01:22:14 PM PDT 24 64584108 ps
T254 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1670701314 Mar 26 01:22:31 PM PDT 24 Mar 26 01:22:31 PM PDT 24 26921082 ps
T935 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2197687135 Mar 26 01:22:08 PM PDT 24 Mar 26 01:22:09 PM PDT 24 68454107 ps
T936 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1805893094 Mar 26 01:22:18 PM PDT 24 Mar 26 01:22:20 PM PDT 24 58614145 ps
T937 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1106327290 Mar 26 01:22:16 PM PDT 24 Mar 26 01:22:18 PM PDT 24 33905804 ps
T938 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2949374626 Mar 26 01:22:27 PM PDT 24 Mar 26 01:22:28 PM PDT 24 29817972 ps
T939 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2690729219 Mar 26 01:22:03 PM PDT 24 Mar 26 01:22:06 PM PDT 24 167359031 ps
T940 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3224366769 Mar 26 01:22:07 PM PDT 24 Mar 26 01:22:08 PM PDT 24 37152561 ps
T941 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.629449691 Mar 26 01:22:05 PM PDT 24 Mar 26 01:22:09 PM PDT 24 468324620 ps
T942 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1195316807 Mar 26 01:22:26 PM PDT 24 Mar 26 01:22:28 PM PDT 24 121979314 ps
T943 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.266143708 Mar 26 01:22:37 PM PDT 24 Mar 26 01:22:38 PM PDT 24 22276466 ps
T944 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2576647198 Mar 26 01:22:17 PM PDT 24 Mar 26 01:22:18 PM PDT 24 79313045 ps
T945 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2544247218 Mar 26 01:22:21 PM PDT 24 Mar 26 01:22:23 PM PDT 24 44671784 ps
T946 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1249524661 Mar 26 01:22:17 PM PDT 24 Mar 26 01:22:20 PM PDT 24 313613831 ps
T947 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3402081556 Mar 26 01:22:03 PM PDT 24 Mar 26 01:22:06 PM PDT 24 271995168 ps
T261 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1800524201 Mar 26 01:22:15 PM PDT 24 Mar 26 01:22:18 PM PDT 24 279471202 ps
T948 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.103300166 Mar 26 01:22:19 PM PDT 24 Mar 26 01:22:22 PM PDT 24 153479163 ps
T949 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1945421055 Mar 26 01:22:22 PM PDT 24 Mar 26 01:22:24 PM PDT 24 77659447 ps
T950 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2808259933 Mar 26 01:22:19 PM PDT 24 Mar 26 01:22:23 PM PDT 24 285218369 ps

Test location /workspace/coverage/default/16.usbdev_in_trans.2694683540
Short name T1
Test name
Test status
Simulation time 8389641445 ps
CPU time 7.12 seconds
Started Mar 26 02:52:49 PM PDT 24
Finished Mar 26 02:52:57 PM PDT 24
Peak memory 203436 kb
Host smart-32433d8f-5365-4927-8ff3-697f96826468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26946
83540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.2694683540
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2798268095
Short name T64
Test name
Test status
Simulation time 30238309 ps
CPU time 0.68 seconds
Started Mar 26 01:22:10 PM PDT 24
Finished Mar 26 01:22:11 PM PDT 24
Peak memory 203060 kb
Host smart-7500dc93-e98e-469e-9fc6-3f4661e482a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2798268095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.2798268095
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.726393239
Short name T3
Test name
Test status
Simulation time 91120934 ps
CPU time 1.15 seconds
Started Mar 26 02:54:14 PM PDT 24
Finished Mar 26 02:54:16 PM PDT 24
Peak memory 203564 kb
Host smart-2e54c30a-0bd9-4b16-bf0b-1ff0c13c5ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72639
3239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.726393239
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3003062022
Short name T52
Test name
Test status
Simulation time 72247055 ps
CPU time 1.09 seconds
Started Mar 26 01:22:21 PM PDT 24
Finished Mar 26 01:22:23 PM PDT 24
Peak memory 211380 kb
Host smart-9f79babc-24a2-4df9-9972-0b0fa2ad1d6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003062022 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.3003062022
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.873938424
Short name T8
Test name
Test status
Simulation time 8371014568 ps
CPU time 9.17 seconds
Started Mar 26 02:53:28 PM PDT 24
Finished Mar 26 02:53:37 PM PDT 24
Peak memory 203436 kb
Host smart-ab2aabe1-443d-401b-a5f2-7ab339ac09c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87393
8424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.873938424
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.2854451888
Short name T81
Test name
Test status
Simulation time 155523117 ps
CPU time 1.78 seconds
Started Mar 26 02:53:52 PM PDT 24
Finished Mar 26 02:53:54 PM PDT 24
Peak memory 203488 kb
Host smart-99c57990-62ac-4df3-9d13-370751503a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28544
51888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.2854451888
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2711941333
Short name T54
Test name
Test status
Simulation time 102132328 ps
CPU time 0.95 seconds
Started Mar 26 02:52:10 PM PDT 24
Finished Mar 26 02:52:11 PM PDT 24
Peak memory 219200 kb
Host smart-313ce017-5ba5-4bf5-87fb-b6fecc973e99
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2711941333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2711941333
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/19.usbdev_smoke.2195763830
Short name T16
Test name
Test status
Simulation time 8469989324 ps
CPU time 7.56 seconds
Started Mar 26 02:53:08 PM PDT 24
Finished Mar 26 02:53:15 PM PDT 24
Peak memory 203480 kb
Host smart-cdc8b5a4-8776-4584-8478-fbe39b8876ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21957
63830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.2195763830
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.147096459
Short name T240
Test name
Test status
Simulation time 25877605 ps
CPU time 0.64 seconds
Started Mar 26 01:22:08 PM PDT 24
Finished Mar 26 01:22:09 PM PDT 24
Peak memory 202964 kb
Host smart-3eb3d989-8c70-435a-8e92-25fb39de96de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=147096459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.147096459
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.1111543178
Short name T4
Test name
Test status
Simulation time 8361986016 ps
CPU time 6.86 seconds
Started Mar 26 02:53:08 PM PDT 24
Finished Mar 26 02:53:16 PM PDT 24
Peak memory 203460 kb
Host smart-7ac3d803-8fd2-4ae4-997d-327cc405576d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11115
43178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1111543178
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.3238316405
Short name T28
Test name
Test status
Simulation time 8440503726 ps
CPU time 7.42 seconds
Started Mar 26 02:54:02 PM PDT 24
Finished Mar 26 02:54:10 PM PDT 24
Peak memory 203680 kb
Host smart-a3fe53c6-5ccc-4f06-bc38-1b132434e9ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32383
16405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.3238316405
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.4075706681
Short name T183
Test name
Test status
Simulation time 456739207 ps
CPU time 4.65 seconds
Started Mar 26 01:22:18 PM PDT 24
Finished Mar 26 01:22:23 PM PDT 24
Peak memory 203444 kb
Host smart-d03b4ede-784f-4e37-a0c6-528542b97c2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4075706681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.4075706681
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.450358650
Short name T25
Test name
Test status
Simulation time 22447933 ps
CPU time 0.63 seconds
Started Mar 26 02:53:06 PM PDT 24
Finished Mar 26 02:53:07 PM PDT 24
Peak memory 203336 kb
Host smart-23bda766-cfba-4b3a-b1a2-d257c1dce154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45035
8650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.450358650
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.2637235223
Short name T214
Test name
Test status
Simulation time 8402514335 ps
CPU time 7.08 seconds
Started Mar 26 02:52:11 PM PDT 24
Finished Mar 26 02:52:18 PM PDT 24
Peak memory 203476 kb
Host smart-f0a7fb04-a559-406c-957f-c817f247a95c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26372
35223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.2637235223
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2092057665
Short name T67
Test name
Test status
Simulation time 31687606 ps
CPU time 0.73 seconds
Started Mar 26 01:22:07 PM PDT 24
Finished Mar 26 01:22:08 PM PDT 24
Peak memory 203136 kb
Host smart-6d5d2a33-be47-4485-92bc-3abfca7849ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092057665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2092057665
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3152834910
Short name T244
Test name
Test status
Simulation time 18919118 ps
CPU time 0.61 seconds
Started Mar 26 01:22:21 PM PDT 24
Finished Mar 26 01:22:22 PM PDT 24
Peak memory 203064 kb
Host smart-cf5e93b4-7426-4865-b018-ee2b0b777775
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3152834910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.3152834910
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2951016955
Short name T246
Test name
Test status
Simulation time 24175186 ps
CPU time 0.64 seconds
Started Mar 26 01:22:19 PM PDT 24
Finished Mar 26 01:22:20 PM PDT 24
Peak memory 203076 kb
Host smart-7565b635-26d2-48f9-82be-c3690e1365e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2951016955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2951016955
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/default/10.usbdev_smoke.752612765
Short name T18
Test name
Test status
Simulation time 8481080083 ps
CPU time 7.33 seconds
Started Mar 26 02:52:20 PM PDT 24
Finished Mar 26 02:52:28 PM PDT 24
Peak memory 203348 kb
Host smart-2f2030ab-5350-4840-92d4-d08d3b59f0ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75261
2765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.752612765
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.976246372
Short name T87
Test name
Test status
Simulation time 8443141220 ps
CPU time 7.57 seconds
Started Mar 26 02:53:52 PM PDT 24
Finished Mar 26 02:54:00 PM PDT 24
Peak memory 203448 kb
Host smart-94080816-c1e6-4a92-9144-380c94b9d570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97624
6372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.976246372
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_smoke.3805148220
Short name T148
Test name
Test status
Simulation time 8481046044 ps
CPU time 7.75 seconds
Started Mar 26 02:53:13 PM PDT 24
Finished Mar 26 02:53:20 PM PDT 24
Peak memory 203504 kb
Host smart-e4c00c25-e086-4377-9acb-c0755452e2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38051
48220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3805148220
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_smoke.482594416
Short name T79
Test name
Test status
Simulation time 8476491055 ps
CPU time 8.41 seconds
Started Mar 26 02:53:28 PM PDT 24
Finished Mar 26 02:53:36 PM PDT 24
Peak memory 203500 kb
Host smart-6c25aa53-9a18-47d1-93fa-0a4d946db188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48259
4416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.482594416
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_smoke.646907303
Short name T401
Test name
Test status
Simulation time 8479047876 ps
CPU time 8.6 seconds
Started Mar 26 02:53:57 PM PDT 24
Finished Mar 26 02:54:06 PM PDT 24
Peak memory 203480 kb
Host smart-760d40a2-da4e-4376-82a2-10f7f401d5b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64690
7303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.646907303
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1161108842
Short name T485
Test name
Test status
Simulation time 8475107599 ps
CPU time 7.32 seconds
Started Mar 26 02:53:58 PM PDT 24
Finished Mar 26 02:54:11 PM PDT 24
Peak memory 203484 kb
Host smart-a13e343e-33a6-456e-aa5d-d2145d8e0c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11611
08842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1161108842
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_smoke.2160581278
Short name T141
Test name
Test status
Simulation time 8469535241 ps
CPU time 8.79 seconds
Started Mar 26 02:52:23 PM PDT 24
Finished Mar 26 02:52:32 PM PDT 24
Peak memory 201876 kb
Host smart-d7e6f5dd-2fc0-43c3-a6ea-1602e79a7bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21605
81278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.2160581278
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_smoke.3602238263
Short name T145
Test name
Test status
Simulation time 8481270667 ps
CPU time 7.49 seconds
Started Mar 26 02:53:00 PM PDT 24
Finished Mar 26 02:53:08 PM PDT 24
Peak memory 203440 kb
Host smart-296b9709-c2a0-400b-8265-961fc5ae97fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36022
38263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.3602238263
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1468454766
Short name T231
Test name
Test status
Simulation time 86296155 ps
CPU time 2.61 seconds
Started Mar 26 01:22:26 PM PDT 24
Finished Mar 26 01:22:29 PM PDT 24
Peak memory 203220 kb
Host smart-2dda3f9b-4296-4a28-9f4b-729a2f24dfb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1468454766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1468454766
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.736685982
Short name T66
Test name
Test status
Simulation time 19092090 ps
CPU time 0.62 seconds
Started Mar 26 01:22:22 PM PDT 24
Finished Mar 26 01:22:23 PM PDT 24
Peak memory 202888 kb
Host smart-ae4b00d9-13cd-43b6-9777-c4246f23d43a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=736685982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.736685982
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.2717229445
Short name T7
Test name
Test status
Simulation time 8371405101 ps
CPU time 7.2 seconds
Started Mar 26 02:52:40 PM PDT 24
Finished Mar 26 02:52:48 PM PDT 24
Peak memory 203456 kb
Host smart-cb3e0363-1faf-4877-aab6-b7d67dca40ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27172
29445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2717229445
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.464071147
Short name T62
Test name
Test status
Simulation time 65750677 ps
CPU time 0.97 seconds
Started Mar 26 01:22:18 PM PDT 24
Finished Mar 26 01:22:19 PM PDT 24
Peak memory 203204 kb
Host smart-9f76ef2d-d5ac-4d0e-a965-51d9ad7f8adc
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464071147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.464071147
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.4011929748
Short name T259
Test name
Test status
Simulation time 464772274 ps
CPU time 4.69 seconds
Started Mar 26 01:22:11 PM PDT 24
Finished Mar 26 01:22:16 PM PDT 24
Peak memory 203160 kb
Host smart-38408fab-221d-45d9-8641-a47c219428e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4011929748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.4011929748
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1599218638
Short name T57
Test name
Test status
Simulation time 39134355 ps
CPU time 0.83 seconds
Started Mar 26 01:22:09 PM PDT 24
Finished Mar 26 01:22:10 PM PDT 24
Peak memory 202968 kb
Host smart-a5db17c0-823d-4a38-a4cf-38cf8a1471ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599218638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.1599218638
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.876023759
Short name T205
Test name
Test status
Simulation time 206687635 ps
CPU time 2.28 seconds
Started Mar 26 02:52:51 PM PDT 24
Finished Mar 26 02:52:54 PM PDT 24
Peak memory 203572 kb
Host smart-4d536cce-bc76-4c0d-96f1-78d1ee1e645d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87602
3759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.876023759
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2889810422
Short name T202
Test name
Test status
Simulation time 472185464 ps
CPU time 4.08 seconds
Started Mar 26 01:22:23 PM PDT 24
Finished Mar 26 01:22:28 PM PDT 24
Peak memory 203124 kb
Host smart-e6579752-4eca-478c-9eae-fdc93d7022b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2889810422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2889810422
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1733928523
Short name T255
Test name
Test status
Simulation time 28761516 ps
CPU time 0.64 seconds
Started Mar 26 01:22:20 PM PDT 24
Finished Mar 26 01:22:21 PM PDT 24
Peak memory 203072 kb
Host smart-5687cd9a-85d5-4ab2-87f7-193808584c8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1733928523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1733928523
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3486385607
Short name T267
Test name
Test status
Simulation time 263192163 ps
CPU time 2.61 seconds
Started Mar 26 01:22:26 PM PDT 24
Finished Mar 26 01:22:29 PM PDT 24
Peak memory 203156 kb
Host smart-a45c4de0-78cf-4d6b-a6ab-8c2787d3a5e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3486385607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3486385607
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/16.usbdev_smoke.843896873
Short name T135
Test name
Test status
Simulation time 8479493154 ps
CPU time 8.58 seconds
Started Mar 26 02:52:58 PM PDT 24
Finished Mar 26 02:53:07 PM PDT 24
Peak memory 203412 kb
Host smart-51d8e33b-2613-42d5-82da-41ef5b07e41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84389
6873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.843896873
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_smoke.2780271991
Short name T138
Test name
Test status
Simulation time 8475616400 ps
CPU time 7.87 seconds
Started Mar 26 02:52:10 PM PDT 24
Finished Mar 26 02:52:18 PM PDT 24
Peak memory 203436 kb
Host smart-94f590f8-bc24-4576-9260-0cba6497df9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27802
71991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.2780271991
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.854026462
Short name T230
Test name
Test status
Simulation time 95638319 ps
CPU time 3.02 seconds
Started Mar 26 01:22:17 PM PDT 24
Finished Mar 26 01:22:21 PM PDT 24
Peak memory 203328 kb
Host smart-38c7741d-ec08-445c-88fd-99a717032796
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=854026462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.854026462
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.2343585971
Short name T492
Test name
Test status
Simulation time 28642122 ps
CPU time 0.66 seconds
Started Mar 26 02:53:04 PM PDT 24
Finished Mar 26 02:53:05 PM PDT 24
Peak memory 203356 kb
Host smart-ba3b74d3-dee6-4471-8818-cbfa5cbc5cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23435
85971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.2343585971
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.3880695519
Short name T215
Test name
Test status
Simulation time 63953003 ps
CPU time 1.79 seconds
Started Mar 26 02:53:31 PM PDT 24
Finished Mar 26 02:53:33 PM PDT 24
Peak memory 203584 kb
Host smart-dc76f4d2-7abc-4a85-a84e-a9a9e0160181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38806
95519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.3880695519
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3275637228
Short name T184
Test name
Test status
Simulation time 236715833 ps
CPU time 2.93 seconds
Started Mar 26 01:22:01 PM PDT 24
Finished Mar 26 01:22:04 PM PDT 24
Peak memory 203216 kb
Host smart-ca4be5f7-275f-4471-ab66-2fea6e690292
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3275637228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3275637228
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.3165243137
Short name T13
Test name
Test status
Simulation time 8354875823 ps
CPU time 7.3 seconds
Started Mar 26 02:52:47 PM PDT 24
Finished Mar 26 02:52:54 PM PDT 24
Peak memory 203484 kb
Host smart-807df015-1d88-4d1b-b704-a2c55fe58d73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31652
43137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.3165243137
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.1309074741
Short name T137
Test name
Test status
Simulation time 8474641418 ps
CPU time 9.52 seconds
Started Mar 26 02:53:02 PM PDT 24
Finished Mar 26 02:53:12 PM PDT 24
Peak memory 203372 kb
Host smart-221cff91-d71e-422c-90fd-77736422cfb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13090
74741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.1309074741
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.23674399
Short name T889
Test name
Test status
Simulation time 118995180 ps
CPU time 1.49 seconds
Started Mar 26 01:22:18 PM PDT 24
Finished Mar 26 01:22:19 PM PDT 24
Peak memory 203232 kb
Host smart-561bc901-407f-442c-b0b1-d3161a60e795
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23674399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_cs
r_outstanding.23674399
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.649251176
Short name T913
Test name
Test status
Simulation time 26772562 ps
CPU time 0.73 seconds
Started Mar 26 01:22:08 PM PDT 24
Finished Mar 26 01:22:09 PM PDT 24
Peak memory 202932 kb
Host smart-81bbdb0f-540b-4f68-b269-4f2eef531bdd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649251176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.649251176
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.3022181103
Short name T97
Test name
Test status
Simulation time 8406560697 ps
CPU time 8.04 seconds
Started Mar 26 02:52:10 PM PDT 24
Finished Mar 26 02:52:19 PM PDT 24
Peak memory 203472 kb
Host smart-9859b1bf-6473-4496-9585-a3087e7b3a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30221
81103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.3022181103
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.933081460
Short name T153
Test name
Test status
Simulation time 8360274872 ps
CPU time 7.51 seconds
Started Mar 26 02:52:08 PM PDT 24
Finished Mar 26 02:52:16 PM PDT 24
Peak memory 203440 kb
Host smart-d011c1e8-d3f2-4f9f-b7a7-d35588cb2fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93308
1460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.933081460
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.4174983790
Short name T101
Test name
Test status
Simulation time 8409689810 ps
CPU time 7.29 seconds
Started Mar 26 02:52:07 PM PDT 24
Finished Mar 26 02:52:14 PM PDT 24
Peak memory 203364 kb
Host smart-6dbc1894-ab93-43ed-b23e-4299d41ee126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41749
83790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.4174983790
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3343643661
Short name T786
Test name
Test status
Simulation time 8437824767 ps
CPU time 6.95 seconds
Started Mar 26 02:52:41 PM PDT 24
Finished Mar 26 02:52:48 PM PDT 24
Peak memory 203432 kb
Host smart-a387995d-1d06-41bc-acf2-99553c31e9a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33436
43661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3343643661
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.1251726526
Short name T166
Test name
Test status
Simulation time 8364088016 ps
CPU time 7.66 seconds
Started Mar 26 02:53:02 PM PDT 24
Finished Mar 26 02:53:10 PM PDT 24
Peak memory 203472 kb
Host smart-ef4e96c7-ea3e-4dc0-96eb-fa1503340cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12517
26526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.1251726526
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3326127195
Short name T104
Test name
Test status
Simulation time 8417919333 ps
CPU time 8.41 seconds
Started Mar 26 02:53:00 PM PDT 24
Finished Mar 26 02:53:09 PM PDT 24
Peak memory 203500 kb
Host smart-b4dae17e-07f8-47e6-96dd-ea08e756613e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33261
27195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3326127195
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.1911724236
Short name T558
Test name
Test status
Simulation time 8418041055 ps
CPU time 9.59 seconds
Started Mar 26 02:53:28 PM PDT 24
Finished Mar 26 02:53:38 PM PDT 24
Peak memory 203336 kb
Host smart-ba889b40-4081-4f36-8fde-a9a2c4aad191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19117
24236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.1911724236
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2051808929
Short name T99
Test name
Test status
Simulation time 8423087415 ps
CPU time 7 seconds
Started Mar 26 02:53:04 PM PDT 24
Finished Mar 26 02:53:11 PM PDT 24
Peak memory 203336 kb
Host smart-e77328c8-63e0-4391-8dc9-b0b24757c887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20518
08929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2051808929
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.1990252295
Short name T812
Test name
Test status
Simulation time 8357308603 ps
CPU time 7.43 seconds
Started Mar 26 02:52:09 PM PDT 24
Finished Mar 26 02:52:17 PM PDT 24
Peak memory 203464 kb
Host smart-1efc22a8-d39a-47ee-89c1-e4ce61a8a44e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19902
52295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.1990252295
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.3352106831
Short name T488
Test name
Test status
Simulation time 8416124709 ps
CPU time 7.23 seconds
Started Mar 26 02:53:05 PM PDT 24
Finished Mar 26 02:53:12 PM PDT 24
Peak memory 203384 kb
Host smart-6503253b-28b8-437e-bf83-7a27800e792b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33521
06831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.3352106831
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.1909137942
Short name T163
Test name
Test status
Simulation time 8358875769 ps
CPU time 9.18 seconds
Started Mar 26 02:52:56 PM PDT 24
Finished Mar 26 02:53:06 PM PDT 24
Peak memory 203436 kb
Host smart-aaf2c6a6-3f58-47f5-b764-eba4cb48dbda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19091
37942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.1909137942
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.821026595
Short name T106
Test name
Test status
Simulation time 8409163945 ps
CPU time 9.31 seconds
Started Mar 26 02:53:07 PM PDT 24
Finished Mar 26 02:53:16 PM PDT 24
Peak memory 203452 kb
Host smart-19ba9695-405a-4780-a1f7-d2def095baec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82102
6595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.821026595
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.173848493
Short name T109
Test name
Test status
Simulation time 8433116527 ps
CPU time 7.68 seconds
Started Mar 26 02:53:03 PM PDT 24
Finished Mar 26 02:53:11 PM PDT 24
Peak memory 203448 kb
Host smart-6e0415cb-5f0a-4ede-ab89-7f259fc5fa87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17384
8493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.173848493
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.3104785974
Short name T687
Test name
Test status
Simulation time 8403164904 ps
CPU time 8.85 seconds
Started Mar 26 02:53:02 PM PDT 24
Finished Mar 26 02:53:11 PM PDT 24
Peak memory 203368 kb
Host smart-aa9334ea-288a-49ca-ba63-23c34725f7f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31047
85974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.3104785974
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.3085393534
Short name T150
Test name
Test status
Simulation time 8360519787 ps
CPU time 7.64 seconds
Started Mar 26 02:53:04 PM PDT 24
Finished Mar 26 02:53:12 PM PDT 24
Peak memory 203452 kb
Host smart-df0e6fe3-2998-41ac-8220-626d0c843aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30853
93534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.3085393534
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.992121746
Short name T173
Test name
Test status
Simulation time 8359458754 ps
CPU time 9.49 seconds
Started Mar 26 02:53:11 PM PDT 24
Finished Mar 26 02:53:20 PM PDT 24
Peak memory 203464 kb
Host smart-20f6e6b0-fb92-4020-ae76-45767666cf3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99212
1746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.992121746
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3830813039
Short name T89
Test name
Test status
Simulation time 8401266541 ps
CPU time 7.77 seconds
Started Mar 26 02:52:45 PM PDT 24
Finished Mar 26 02:52:53 PM PDT 24
Peak memory 203408 kb
Host smart-f66d028f-bc0d-4c39-9076-5500f3351bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38308
13039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3830813039
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2690729219
Short name T939
Test name
Test status
Simulation time 167359031 ps
CPU time 2.05 seconds
Started Mar 26 01:22:03 PM PDT 24
Finished Mar 26 01:22:06 PM PDT 24
Peak memory 203156 kb
Host smart-b8099576-aadd-4f58-9f7d-047004fe6dfe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690729219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2690729219
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1636079789
Short name T903
Test name
Test status
Simulation time 287529648 ps
CPU time 7.02 seconds
Started Mar 26 01:22:11 PM PDT 24
Finished Mar 26 01:22:18 PM PDT 24
Peak memory 203088 kb
Host smart-eb2c189c-8ba5-4024-8a9f-a943fac40a3b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636079789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1636079789
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1456793116
Short name T181
Test name
Test status
Simulation time 39587851 ps
CPU time 1.09 seconds
Started Mar 26 01:22:11 PM PDT 24
Finished Mar 26 01:22:12 PM PDT 24
Peak memory 211436 kb
Host smart-bf2ae64f-0de5-468c-8465-d90222796a6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456793116 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.1456793116
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3224366769
Short name T940
Test name
Test status
Simulation time 37152561 ps
CPU time 0.78 seconds
Started Mar 26 01:22:07 PM PDT 24
Finished Mar 26 01:22:08 PM PDT 24
Peak memory 203040 kb
Host smart-776328fb-305e-407c-8290-37016b121093
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224366769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.3224366769
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3060061536
Short name T191
Test name
Test status
Simulation time 99506201 ps
CPU time 1.53 seconds
Started Mar 26 01:22:05 PM PDT 24
Finished Mar 26 01:22:08 PM PDT 24
Peak memory 203216 kb
Host smart-168b52fb-56cc-4f0f-aecb-9ca865190b32
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3060061536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3060061536
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.629449691
Short name T941
Test name
Test status
Simulation time 468324620 ps
CPU time 4.4 seconds
Started Mar 26 01:22:05 PM PDT 24
Finished Mar 26 01:22:09 PM PDT 24
Peak memory 203196 kb
Host smart-d1a10f06-ea5e-4f4a-8f07-9ae36eba9a4f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=629449691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.629449691
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1144300057
Short name T901
Test name
Test status
Simulation time 50020094 ps
CPU time 1.49 seconds
Started Mar 26 01:22:03 PM PDT 24
Finished Mar 26 01:22:05 PM PDT 24
Peak memory 203320 kb
Host smart-a2a3712f-25cc-48db-ad63-75b3bd501f9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144300057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_c
sr_outstanding.1144300057
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3449421632
Short name T909
Test name
Test status
Simulation time 83832207 ps
CPU time 2.72 seconds
Started Mar 26 01:22:06 PM PDT 24
Finished Mar 26 01:22:09 PM PDT 24
Peak memory 203208 kb
Host smart-74b126de-6925-45ca-831a-de18d42335e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3449421632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3449421632
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1918958227
Short name T51
Test name
Test status
Simulation time 230033200 ps
CPU time 2.71 seconds
Started Mar 26 01:22:10 PM PDT 24
Finished Mar 26 01:22:13 PM PDT 24
Peak memory 203184 kb
Host smart-057272c9-c2f6-4a90-9969-322cd48a38ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1918958227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.1918958227
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1367671242
Short name T904
Test name
Test status
Simulation time 358926055 ps
CPU time 3.58 seconds
Started Mar 26 01:22:07 PM PDT 24
Finished Mar 26 01:22:10 PM PDT 24
Peak memory 203088 kb
Host smart-d7295ea6-7b12-49c3-8375-04327d858aae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367671242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1367671242
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2317606367
Short name T891
Test name
Test status
Simulation time 56132805 ps
CPU time 1.88 seconds
Started Mar 26 01:22:04 PM PDT 24
Finished Mar 26 01:22:07 PM PDT 24
Peak memory 211532 kb
Host smart-791349e2-ae6c-4a82-b1e6-e5e8a4161f2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317606367 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.2317606367
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3641896327
Short name T198
Test name
Test status
Simulation time 28116171 ps
CPU time 0.75 seconds
Started Mar 26 01:22:03 PM PDT 24
Finished Mar 26 01:22:03 PM PDT 24
Peak memory 203060 kb
Host smart-c38499b6-b2e8-42de-9c97-69bb20fe3041
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641896327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.3641896327
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3648331898
Short name T187
Test name
Test status
Simulation time 88448859 ps
CPU time 1.54 seconds
Started Mar 26 01:22:05 PM PDT 24
Finished Mar 26 01:22:08 PM PDT 24
Peak memory 203160 kb
Host smart-e7db2b32-3254-40a0-aa0f-5f17fe45a89b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3648331898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.3648331898
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2954580966
Short name T921
Test name
Test status
Simulation time 87235248 ps
CPU time 1.15 seconds
Started Mar 26 01:22:04 PM PDT 24
Finished Mar 26 01:22:05 PM PDT 24
Peak memory 203272 kb
Host smart-40cf19e9-29c2-465a-afa4-11facc4cf1e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954580966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_c
sr_outstanding.2954580966
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3402081556
Short name T947
Test name
Test status
Simulation time 271995168 ps
CPU time 2.86 seconds
Started Mar 26 01:22:03 PM PDT 24
Finished Mar 26 01:22:06 PM PDT 24
Peak memory 203296 kb
Host smart-4d3d5203-db9d-4fe8-9d59-5485e33203d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3402081556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3402081556
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1791202191
Short name T931
Test name
Test status
Simulation time 143872911 ps
CPU time 1.75 seconds
Started Mar 26 01:22:14 PM PDT 24
Finished Mar 26 01:22:15 PM PDT 24
Peak memory 211448 kb
Host smart-79ec84c4-c385-4ec1-b609-6b9824004e50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791202191 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.1791202191
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1771084687
Short name T188
Test name
Test status
Simulation time 52011551 ps
CPU time 0.96 seconds
Started Mar 26 01:22:19 PM PDT 24
Finished Mar 26 01:22:20 PM PDT 24
Peak memory 203092 kb
Host smart-675e5aa3-9c86-4ce0-8a66-9c0aa32154b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771084687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.1771084687
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2725285903
Short name T888
Test name
Test status
Simulation time 42319203 ps
CPU time 1.1 seconds
Started Mar 26 01:22:17 PM PDT 24
Finished Mar 26 01:22:19 PM PDT 24
Peak memory 203228 kb
Host smart-feaa9135-af62-4440-90d6-ced0008385f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725285903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_
csr_outstanding.2725285903
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3805138247
Short name T257
Test name
Test status
Simulation time 464481578 ps
CPU time 5.01 seconds
Started Mar 26 01:22:20 PM PDT 24
Finished Mar 26 01:22:26 PM PDT 24
Peak memory 203284 kb
Host smart-ff445f10-fee4-494f-a503-28fdc66a0c13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3805138247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.3805138247
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2519733638
Short name T892
Test name
Test status
Simulation time 77203753 ps
CPU time 1.36 seconds
Started Mar 26 01:22:18 PM PDT 24
Finished Mar 26 01:22:19 PM PDT 24
Peak memory 211464 kb
Host smart-36453020-d303-442b-8f99-76fc19d11eed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519733638 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.2519733638
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1561094977
Short name T917
Test name
Test status
Simulation time 28054642 ps
CPU time 0.65 seconds
Started Mar 26 01:22:18 PM PDT 24
Finished Mar 26 01:22:18 PM PDT 24
Peak memory 202996 kb
Host smart-e26123eb-b749-4ec0-8000-0b0b74726da4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1561094977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1561094977
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1250684160
Short name T229
Test name
Test status
Simulation time 416145630 ps
CPU time 4.3 seconds
Started Mar 26 01:22:18 PM PDT 24
Finished Mar 26 01:22:23 PM PDT 24
Peak memory 203224 kb
Host smart-81146a54-bcac-4aaa-a83a-fd88add8f245
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1250684160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1250684160
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3995076947
Short name T260
Test name
Test status
Simulation time 437803875 ps
CPU time 4.37 seconds
Started Mar 26 01:22:16 PM PDT 24
Finished Mar 26 01:22:21 PM PDT 24
Peak memory 203220 kb
Host smart-1f139c58-ef0b-4843-afa0-5c7e44f3483b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3995076947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.3995076947
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1646998757
Short name T85
Test name
Test status
Simulation time 84532119 ps
CPU time 1.3 seconds
Started Mar 26 01:22:17 PM PDT 24
Finished Mar 26 01:22:18 PM PDT 24
Peak memory 211416 kb
Host smart-f7294b3e-8663-4df5-93bf-c518f4dc8a96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646998757 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.1646998757
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3536298717
Short name T201
Test name
Test status
Simulation time 52301767 ps
CPU time 0.92 seconds
Started Mar 26 01:22:17 PM PDT 24
Finished Mar 26 01:22:18 PM PDT 24
Peak memory 203116 kb
Host smart-cd4a2b81-dfe5-4e6e-8a23-69bdc70efc14
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536298717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3536298717
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3933420394
Short name T189
Test name
Test status
Simulation time 116455843 ps
CPU time 1.52 seconds
Started Mar 26 01:22:18 PM PDT 24
Finished Mar 26 01:22:20 PM PDT 24
Peak memory 203224 kb
Host smart-819a1b7f-9688-48cb-9ad5-38c96cf48920
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933420394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_
csr_outstanding.3933420394
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1249524661
Short name T946
Test name
Test status
Simulation time 313613831 ps
CPU time 3.41 seconds
Started Mar 26 01:22:17 PM PDT 24
Finished Mar 26 01:22:20 PM PDT 24
Peak memory 203304 kb
Host smart-cc60e1d0-56a5-4a0a-8cf5-3c4608c40f1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1249524661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1249524661
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1546996785
Short name T236
Test name
Test status
Simulation time 130466708 ps
CPU time 1.55 seconds
Started Mar 26 01:22:21 PM PDT 24
Finished Mar 26 01:22:23 PM PDT 24
Peak memory 211528 kb
Host smart-fd9ca91a-c305-475a-b67f-102475aa34a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546996785 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.1546996785
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2041174703
Short name T190
Test name
Test status
Simulation time 61316063 ps
CPU time 0.98 seconds
Started Mar 26 01:22:20 PM PDT 24
Finished Mar 26 01:22:21 PM PDT 24
Peak memory 203220 kb
Host smart-13d886fb-17da-4894-a650-235633b6f386
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041174703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2041174703
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1763659222
Short name T924
Test name
Test status
Simulation time 35416295 ps
CPU time 0.65 seconds
Started Mar 26 01:22:19 PM PDT 24
Finished Mar 26 01:22:20 PM PDT 24
Peak memory 203088 kb
Host smart-c4b95e9f-f5fe-41eb-ba8f-9eed10419b9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1763659222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1763659222
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1695947010
Short name T238
Test name
Test status
Simulation time 86835403 ps
CPU time 1.08 seconds
Started Mar 26 01:22:17 PM PDT 24
Finished Mar 26 01:22:18 PM PDT 24
Peak memory 203280 kb
Host smart-56e0ea79-00e6-4d44-af0c-84a9cc9fa5fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695947010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_
csr_outstanding.1695947010
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3288061857
Short name T925
Test name
Test status
Simulation time 54610190 ps
CPU time 1.73 seconds
Started Mar 26 01:22:19 PM PDT 24
Finished Mar 26 01:22:22 PM PDT 24
Peak memory 203248 kb
Host smart-f1e5f878-ab28-4d10-ad52-2cfc8d9c7b24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3288061857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3288061857
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.103300166
Short name T948
Test name
Test status
Simulation time 153479163 ps
CPU time 2.18 seconds
Started Mar 26 01:22:19 PM PDT 24
Finished Mar 26 01:22:22 PM PDT 24
Peak memory 203212 kb
Host smart-4996225a-2d31-43c0-9a7e-4f94a9625d6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=103300166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.103300166
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2544247218
Short name T945
Test name
Test status
Simulation time 44671784 ps
CPU time 1.27 seconds
Started Mar 26 01:22:21 PM PDT 24
Finished Mar 26 01:22:23 PM PDT 24
Peak memory 212716 kb
Host smart-fe4b1b83-44d7-4653-8828-afbce5346e6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544247218 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.2544247218
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2707051144
Short name T907
Test name
Test status
Simulation time 37138009 ps
CPU time 0.99 seconds
Started Mar 26 01:22:20 PM PDT 24
Finished Mar 26 01:22:21 PM PDT 24
Peak memory 203240 kb
Host smart-7d67a8b0-b4bd-4f58-b770-2d50b17f5a14
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707051144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.2707051144
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1805893094
Short name T936
Test name
Test status
Simulation time 58614145 ps
CPU time 1.36 seconds
Started Mar 26 01:22:18 PM PDT 24
Finished Mar 26 01:22:20 PM PDT 24
Peak memory 203196 kb
Host smart-39d62851-8c03-428d-9f47-aa50c189a104
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805893094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_
csr_outstanding.1805893094
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3685459343
Short name T905
Test name
Test status
Simulation time 261452961 ps
CPU time 3.07 seconds
Started Mar 26 01:22:17 PM PDT 24
Finished Mar 26 01:22:21 PM PDT 24
Peak memory 203248 kb
Host smart-ff4d5ec3-40bd-4356-a05e-fd736d46dade
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3685459343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3685459343
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3334737360
Short name T263
Test name
Test status
Simulation time 264103633 ps
CPU time 2.58 seconds
Started Mar 26 01:22:19 PM PDT 24
Finished Mar 26 01:22:22 PM PDT 24
Peak memory 203256 kb
Host smart-09edff63-da11-4a75-8cd2-d57e37e39583
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3334737360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3334737360
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1692578265
Short name T53
Test name
Test status
Simulation time 70541960 ps
CPU time 1.13 seconds
Started Mar 26 01:22:22 PM PDT 24
Finished Mar 26 01:22:24 PM PDT 24
Peak memory 219636 kb
Host smart-d36c1553-757a-4f36-9e30-fee79aab7133
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692578265 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.1692578265
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.473685159
Short name T920
Test name
Test status
Simulation time 65948500 ps
CPU time 0.95 seconds
Started Mar 26 01:22:22 PM PDT 24
Finished Mar 26 01:22:24 PM PDT 24
Peak memory 203248 kb
Host smart-541cd42c-79bf-4407-a033-42602c806f35
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473685159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.473685159
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3254937862
Short name T899
Test name
Test status
Simulation time 66037803 ps
CPU time 1.01 seconds
Started Mar 26 01:22:21 PM PDT 24
Finished Mar 26 01:22:23 PM PDT 24
Peak memory 203348 kb
Host smart-0c725c5e-f79f-44d6-b750-94af899ddb3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254937862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_
csr_outstanding.3254937862
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3111631003
Short name T908
Test name
Test status
Simulation time 82033083 ps
CPU time 2.62 seconds
Started Mar 26 01:22:19 PM PDT 24
Finished Mar 26 01:22:22 PM PDT 24
Peak memory 203332 kb
Host smart-720ce281-f90d-4fc5-9656-aa5e67097f84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3111631003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3111631003
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1597946279
Short name T922
Test name
Test status
Simulation time 477795210 ps
CPU time 4.32 seconds
Started Mar 26 01:22:21 PM PDT 24
Finished Mar 26 01:22:26 PM PDT 24
Peak memory 203080 kb
Host smart-0bcb97f9-c256-4816-b5fa-729766d02660
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1597946279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1597946279
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3283222535
Short name T915
Test name
Test status
Simulation time 60766591 ps
CPU time 1.11 seconds
Started Mar 26 01:22:21 PM PDT 24
Finished Mar 26 01:22:23 PM PDT 24
Peak memory 212548 kb
Host smart-b69dd81c-218e-4bd4-af97-4e9bc5609f81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283222535 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.3283222535
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.668624169
Short name T910
Test name
Test status
Simulation time 56649332 ps
CPU time 0.94 seconds
Started Mar 26 01:22:21 PM PDT 24
Finished Mar 26 01:22:23 PM PDT 24
Peak memory 203260 kb
Host smart-39cabe39-346b-4d00-9b66-98627fe35033
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668624169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.668624169
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.501012528
Short name T906
Test name
Test status
Simulation time 71290435 ps
CPU time 1.01 seconds
Started Mar 26 01:22:21 PM PDT 24
Finished Mar 26 01:22:22 PM PDT 24
Peak memory 203280 kb
Host smart-dd44f414-b774-4d83-a2e5-6465ad9587eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501012528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_c
sr_outstanding.501012528
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.4080468730
Short name T926
Test name
Test status
Simulation time 87382754 ps
CPU time 1.4 seconds
Started Mar 26 01:22:22 PM PDT 24
Finished Mar 26 01:22:24 PM PDT 24
Peak memory 203380 kb
Host smart-4629af74-97ff-43bd-b06f-b74f5f9b570e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4080468730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.4080468730
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3386282218
Short name T58
Test name
Test status
Simulation time 116564590 ps
CPU time 2.32 seconds
Started Mar 26 01:22:23 PM PDT 24
Finished Mar 26 01:22:26 PM PDT 24
Peak memory 203240 kb
Host smart-36c93aa4-83e1-4708-9446-2c0d20e9306c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3386282218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3386282218
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1195316807
Short name T942
Test name
Test status
Simulation time 121979314 ps
CPU time 1.87 seconds
Started Mar 26 01:22:26 PM PDT 24
Finished Mar 26 01:22:28 PM PDT 24
Peak memory 214084 kb
Host smart-1efef556-31dd-4e9b-a98d-960d8374bc91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195316807 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.1195316807
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.836434571
Short name T902
Test name
Test status
Simulation time 37509858 ps
CPU time 0.73 seconds
Started Mar 26 01:22:22 PM PDT 24
Finished Mar 26 01:22:22 PM PDT 24
Peak memory 203096 kb
Host smart-a4e0b511-8999-479f-b13f-1ce74975fec1
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836434571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.836434571
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3300708197
Short name T893
Test name
Test status
Simulation time 55775073 ps
CPU time 1.42 seconds
Started Mar 26 01:22:22 PM PDT 24
Finished Mar 26 01:22:24 PM PDT 24
Peak memory 203276 kb
Host smart-fcc5396d-d105-413a-803d-ea727072835d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300708197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_
csr_outstanding.3300708197
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3026918735
Short name T233
Test name
Test status
Simulation time 84857249 ps
CPU time 2.61 seconds
Started Mar 26 01:22:22 PM PDT 24
Finished Mar 26 01:22:24 PM PDT 24
Peak memory 203324 kb
Host smart-227b2414-8cd6-44b3-bfcf-43ec7d99fb7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3026918735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3026918735
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4135731404
Short name T194
Test name
Test status
Simulation time 36551066 ps
CPU time 0.77 seconds
Started Mar 26 01:22:26 PM PDT 24
Finished Mar 26 01:22:26 PM PDT 24
Peak memory 203040 kb
Host smart-1d4eb921-e786-4d56-bad4-4a6e44f42616
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135731404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.4135731404
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2691877441
Short name T241
Test name
Test status
Simulation time 19612103 ps
CPU time 0.69 seconds
Started Mar 26 01:22:22 PM PDT 24
Finished Mar 26 01:22:23 PM PDT 24
Peak memory 202956 kb
Host smart-00c354ed-02b4-408a-b64f-8a7dab41797b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2691877441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.2691877441
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1114653149
Short name T890
Test name
Test status
Simulation time 118118438 ps
CPU time 1.55 seconds
Started Mar 26 01:22:22 PM PDT 24
Finished Mar 26 01:22:24 PM PDT 24
Peak memory 203296 kb
Host smart-8949a12b-a180-4d11-8274-add4bb9a5d64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114653149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_
csr_outstanding.1114653149
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3343026515
Short name T912
Test name
Test status
Simulation time 103498642 ps
CPU time 1.57 seconds
Started Mar 26 01:22:21 PM PDT 24
Finished Mar 26 01:22:23 PM PDT 24
Peak memory 203292 kb
Host smart-baa18319-7257-4622-a0f7-4648ff342842
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3343026515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3343026515
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3729938682
Short name T896
Test name
Test status
Simulation time 77151694 ps
CPU time 2.36 seconds
Started Mar 26 01:22:23 PM PDT 24
Finished Mar 26 01:22:26 PM PDT 24
Peak memory 211488 kb
Host smart-f2ba6a8e-cbab-40cf-adc4-80e13e7fce5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729938682 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.3729938682
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1069360112
Short name T199
Test name
Test status
Simulation time 29802188 ps
CPU time 0.93 seconds
Started Mar 26 01:22:22 PM PDT 24
Finished Mar 26 01:22:23 PM PDT 24
Peak memory 203156 kb
Host smart-5d3a2a0f-33ff-4b5b-875a-24181c0cc2bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069360112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1069360112
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.999846893
Short name T895
Test name
Test status
Simulation time 123628148 ps
CPU time 1.5 seconds
Started Mar 26 01:22:23 PM PDT 24
Finished Mar 26 01:22:25 PM PDT 24
Peak memory 203280 kb
Host smart-ab6868b5-6263-4881-87f7-ec8b80ea20ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999846893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_c
sr_outstanding.999846893
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.474334545
Short name T86
Test name
Test status
Simulation time 114242244 ps
CPU time 2.17 seconds
Started Mar 26 01:22:26 PM PDT 24
Finished Mar 26 01:22:28 PM PDT 24
Peak memory 203184 kb
Host smart-5466af64-f535-4abd-aed7-b217c2c9c8a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=474334545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.474334545
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.4181891505
Short name T923
Test name
Test status
Simulation time 108120187 ps
CPU time 3.26 seconds
Started Mar 26 01:22:12 PM PDT 24
Finished Mar 26 01:22:15 PM PDT 24
Peak memory 203188 kb
Host smart-dbc7ee0a-23b0-459a-b1be-74404e536287
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181891505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.4181891505
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.827763345
Short name T928
Test name
Test status
Simulation time 151030262 ps
CPU time 3.67 seconds
Started Mar 26 01:22:12 PM PDT 24
Finished Mar 26 01:22:16 PM PDT 24
Peak memory 203160 kb
Host smart-a8d4941c-280a-4acc-816f-27c1d9e07e29
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827763345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.827763345
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2339520360
Short name T61
Test name
Test status
Simulation time 33446018 ps
CPU time 0.76 seconds
Started Mar 26 01:22:08 PM PDT 24
Finished Mar 26 01:22:09 PM PDT 24
Peak memory 203012 kb
Host smart-0e451f9e-1a34-49ca-a307-63d3bd278619
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339520360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2339520360
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.688261511
Short name T898
Test name
Test status
Simulation time 126116930 ps
CPU time 1.79 seconds
Started Mar 26 01:22:10 PM PDT 24
Finished Mar 26 01:22:12 PM PDT 24
Peak memory 211444 kb
Host smart-24438a32-6afd-4f17-8cec-374bf2ba0d8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688261511 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.688261511
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.801671044
Short name T186
Test name
Test status
Simulation time 70236705 ps
CPU time 1 seconds
Started Mar 26 01:22:08 PM PDT 24
Finished Mar 26 01:22:09 PM PDT 24
Peak memory 203120 kb
Host smart-67b1938e-5619-4b77-af4c-ca3cec8458b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801671044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.801671044
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1111944728
Short name T248
Test name
Test status
Simulation time 30172873 ps
CPU time 0.72 seconds
Started Mar 26 01:22:08 PM PDT 24
Finished Mar 26 01:22:09 PM PDT 24
Peak memory 202936 kb
Host smart-6f0bec20-b7f3-4d9a-88a1-806c43f30b68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1111944728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.1111944728
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3271032619
Short name T197
Test name
Test status
Simulation time 90599382 ps
CPU time 1.44 seconds
Started Mar 26 01:22:04 PM PDT 24
Finished Mar 26 01:22:05 PM PDT 24
Peak memory 203208 kb
Host smart-fc0f928c-bdd9-4f7a-a123-7fbf578c5688
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3271032619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3271032619
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.936149223
Short name T887
Test name
Test status
Simulation time 251924097 ps
CPU time 2.44 seconds
Started Mar 26 01:22:12 PM PDT 24
Finished Mar 26 01:22:14 PM PDT 24
Peak memory 203088 kb
Host smart-9cbe7f41-b0e3-49c5-9c70-74a5fd2b259c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=936149223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.936149223
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2197687135
Short name T935
Test name
Test status
Simulation time 68454107 ps
CPU time 1.12 seconds
Started Mar 26 01:22:08 PM PDT 24
Finished Mar 26 01:22:09 PM PDT 24
Peak memory 203132 kb
Host smart-d2c6a418-c20d-4f84-bbd4-d12e91432f35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197687135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c
sr_outstanding.2197687135
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3490167779
Short name T934
Test name
Test status
Simulation time 64584108 ps
CPU time 1.1 seconds
Started Mar 26 01:22:13 PM PDT 24
Finished Mar 26 01:22:14 PM PDT 24
Peak memory 203168 kb
Host smart-327f5628-d82b-479f-84fc-1b44aa5f7d4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3490167779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.3490167779
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1400808063
Short name T258
Test name
Test status
Simulation time 448241173 ps
CPU time 4.29 seconds
Started Mar 26 01:22:05 PM PDT 24
Finished Mar 26 01:22:09 PM PDT 24
Peak memory 203204 kb
Host smart-64e77d4a-a308-4c4f-a862-f7b231b0eab3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1400808063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1400808063
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2150653543
Short name T65
Test name
Test status
Simulation time 28943880 ps
CPU time 0.68 seconds
Started Mar 26 01:22:31 PM PDT 24
Finished Mar 26 01:22:32 PM PDT 24
Peak memory 203028 kb
Host smart-29b5a593-2df8-4d2d-aec5-888f8f5540f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2150653543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.2150653543
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.266143708
Short name T943
Test name
Test status
Simulation time 22276466 ps
CPU time 0.62 seconds
Started Mar 26 01:22:37 PM PDT 24
Finished Mar 26 01:22:38 PM PDT 24
Peak memory 203080 kb
Host smart-5374b8d4-17e2-4ab6-83e6-76c4c6aefb80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=266143708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.266143708
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1520423293
Short name T251
Test name
Test status
Simulation time 19062920 ps
CPU time 0.63 seconds
Started Mar 26 01:22:28 PM PDT 24
Finished Mar 26 01:22:29 PM PDT 24
Peak memory 203072 kb
Host smart-c7049f00-beac-4e69-8fcd-7062246eeba8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1520423293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1520423293
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3810989686
Short name T897
Test name
Test status
Simulation time 191947521 ps
CPU time 2.06 seconds
Started Mar 26 01:22:07 PM PDT 24
Finished Mar 26 01:22:09 PM PDT 24
Peak memory 203216 kb
Host smart-39273107-2076-418d-b48c-066a215fb8be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810989686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3810989686
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.395685879
Short name T178
Test name
Test status
Simulation time 36254477 ps
CPU time 1.15 seconds
Started Mar 26 01:22:13 PM PDT 24
Finished Mar 26 01:22:14 PM PDT 24
Peak memory 211484 kb
Host smart-b1344ceb-490f-44ab-b0b1-550360b3ede9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395685879 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.395685879
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3345406878
Short name T192
Test name
Test status
Simulation time 35599622 ps
CPU time 0.96 seconds
Started Mar 26 01:22:13 PM PDT 24
Finished Mar 26 01:22:14 PM PDT 24
Peak memory 203156 kb
Host smart-ad7f74a8-c236-40fd-a492-b4375e77524c
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345406878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3345406878
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1737960310
Short name T252
Test name
Test status
Simulation time 30126964 ps
CPU time 0.64 seconds
Started Mar 26 01:22:09 PM PDT 24
Finished Mar 26 01:22:10 PM PDT 24
Peak memory 202984 kb
Host smart-2015a53c-43fa-417a-95d0-f7b60567778f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1737960310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1737960310
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1783024927
Short name T919
Test name
Test status
Simulation time 44960371 ps
CPU time 1.43 seconds
Started Mar 26 01:22:08 PM PDT 24
Finished Mar 26 01:22:10 PM PDT 24
Peak memory 203268 kb
Host smart-e3139596-58fc-47a5-a3c2-63860d8cfae8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1783024927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1783024927
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.720996684
Short name T234
Test name
Test status
Simulation time 475626209 ps
CPU time 4.42 seconds
Started Mar 26 01:22:09 PM PDT 24
Finished Mar 26 01:22:13 PM PDT 24
Peak memory 203096 kb
Host smart-dcd9d6e2-ef33-461d-ab19-880f15263935
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=720996684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.720996684
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2381359260
Short name T84
Test name
Test status
Simulation time 38758189 ps
CPU time 1.05 seconds
Started Mar 26 01:22:13 PM PDT 24
Finished Mar 26 01:22:14 PM PDT 24
Peak memory 203184 kb
Host smart-dae89d55-937b-4399-b0a2-8d06d5fe1ed0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381359260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_c
sr_outstanding.2381359260
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.303766013
Short name T930
Test name
Test status
Simulation time 259733061 ps
CPU time 2.78 seconds
Started Mar 26 01:22:10 PM PDT 24
Finished Mar 26 01:22:13 PM PDT 24
Peak memory 203252 kb
Host smart-5b152dd6-b5fc-46d7-983f-9ba880d6b6eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=303766013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.303766013
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2949374626
Short name T938
Test name
Test status
Simulation time 29817972 ps
CPU time 0.64 seconds
Started Mar 26 01:22:27 PM PDT 24
Finished Mar 26 01:22:28 PM PDT 24
Peak memory 202980 kb
Host smart-78be2458-2e43-4131-920f-db3cf5e3d633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2949374626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2949374626
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3168244229
Short name T63
Test name
Test status
Simulation time 23361005 ps
CPU time 0.64 seconds
Started Mar 26 01:22:31 PM PDT 24
Finished Mar 26 01:22:32 PM PDT 24
Peak memory 203068 kb
Host smart-092b11a8-6353-419d-b2af-a937752ad0bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3168244229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3168244229
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2043270916
Short name T256
Test name
Test status
Simulation time 28659541 ps
CPU time 0.65 seconds
Started Mar 26 01:22:30 PM PDT 24
Finished Mar 26 01:22:30 PM PDT 24
Peak memory 202968 kb
Host smart-87bd0318-c314-46c3-b445-b5603146243d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2043270916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.2043270916
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1613197966
Short name T249
Test name
Test status
Simulation time 27625334 ps
CPU time 0.67 seconds
Started Mar 26 01:22:30 PM PDT 24
Finished Mar 26 01:22:30 PM PDT 24
Peak memory 202996 kb
Host smart-ce654b34-40af-486a-8a43-4bb3acd997eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1613197966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1613197966
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2935229434
Short name T929
Test name
Test status
Simulation time 67362373 ps
CPU time 2.04 seconds
Started Mar 26 01:22:19 PM PDT 24
Finished Mar 26 01:22:21 PM PDT 24
Peak memory 203196 kb
Host smart-fbbb7091-0db9-49c8-864f-f2bfcc2f7eb1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935229434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2935229434
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.750837234
Short name T60
Test name
Test status
Simulation time 33108472 ps
CPU time 0.74 seconds
Started Mar 26 01:22:18 PM PDT 24
Finished Mar 26 01:22:19 PM PDT 24
Peak memory 202988 kb
Host smart-138abedd-b437-4c06-83b6-ab481b523299
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750837234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.750837234
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2643098759
Short name T179
Test name
Test status
Simulation time 47653042 ps
CPU time 1.65 seconds
Started Mar 26 01:22:17 PM PDT 24
Finished Mar 26 01:22:19 PM PDT 24
Peak memory 211536 kb
Host smart-b754a02b-1271-482f-bcec-bb47e4238080
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643098759 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.2643098759
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3482821582
Short name T185
Test name
Test status
Simulation time 64545935 ps
CPU time 0.97 seconds
Started Mar 26 01:22:18 PM PDT 24
Finished Mar 26 01:22:19 PM PDT 24
Peak memory 203096 kb
Host smart-5664c3e4-8dcc-4e90-8ed8-2e17d88f6a12
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482821582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3482821582
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2240470488
Short name T250
Test name
Test status
Simulation time 26602178 ps
CPU time 0.62 seconds
Started Mar 26 01:22:18 PM PDT 24
Finished Mar 26 01:22:19 PM PDT 24
Peak memory 202932 kb
Host smart-ffb11633-ed89-4ad0-b4f1-3b82ea4e529a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2240470488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.2240470488
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2919348433
Short name T196
Test name
Test status
Simulation time 83937870 ps
CPU time 1.47 seconds
Started Mar 26 01:22:19 PM PDT 24
Finished Mar 26 01:22:20 PM PDT 24
Peak memory 203236 kb
Host smart-c51c49c9-def3-4c0c-9c10-bad7e1cb7fd8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2919348433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2919348433
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2845914098
Short name T59
Test name
Test status
Simulation time 64368618 ps
CPU time 0.96 seconds
Started Mar 26 01:22:20 PM PDT 24
Finished Mar 26 01:22:21 PM PDT 24
Peak memory 203172 kb
Host smart-057dfc66-7369-4a3d-8981-a722e17fba2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845914098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_c
sr_outstanding.2845914098
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.658162075
Short name T918
Test name
Test status
Simulation time 43588176 ps
CPU time 1.4 seconds
Started Mar 26 01:22:13 PM PDT 24
Finished Mar 26 01:22:15 PM PDT 24
Peak memory 203376 kb
Host smart-8ec05247-f346-4b1b-a289-69a61034ff1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=658162075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.658162075
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3246557277
Short name T262
Test name
Test status
Simulation time 202205798 ps
CPU time 2.33 seconds
Started Mar 26 01:22:13 PM PDT 24
Finished Mar 26 01:22:16 PM PDT 24
Peak memory 203316 kb
Host smart-869bb471-e542-433b-962b-b6dfc2386cde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3246557277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3246557277
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1670701314
Short name T254
Test name
Test status
Simulation time 26921082 ps
CPU time 0.68 seconds
Started Mar 26 01:22:31 PM PDT 24
Finished Mar 26 01:22:31 PM PDT 24
Peak memory 203088 kb
Host smart-4570e060-0858-48d2-ab13-02deb149f9ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1670701314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.1670701314
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2160912343
Short name T916
Test name
Test status
Simulation time 23546819 ps
CPU time 0.62 seconds
Started Mar 26 01:22:29 PM PDT 24
Finished Mar 26 01:22:30 PM PDT 24
Peak memory 202936 kb
Host smart-37c6b5c9-c1d8-436e-b170-dfcc51804dd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2160912343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2160912343
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1011284124
Short name T239
Test name
Test status
Simulation time 30941193 ps
CPU time 0.68 seconds
Started Mar 26 01:22:29 PM PDT 24
Finished Mar 26 01:22:30 PM PDT 24
Peak memory 202944 kb
Host smart-da8fc20b-b764-4887-b14c-edb0af42bb7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1011284124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1011284124
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2130553440
Short name T242
Test name
Test status
Simulation time 29590199 ps
CPU time 0.67 seconds
Started Mar 26 01:22:35 PM PDT 24
Finished Mar 26 01:22:36 PM PDT 24
Peak memory 202868 kb
Host smart-725aa43b-8a90-4345-8012-b79d298b4ac9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2130553440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2130553440
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2946083689
Short name T245
Test name
Test status
Simulation time 21723424 ps
CPU time 0.64 seconds
Started Mar 26 01:22:29 PM PDT 24
Finished Mar 26 01:22:30 PM PDT 24
Peak memory 203088 kb
Host smart-f1b4d492-c671-43d9-86ff-481e658f341e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2946083689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2946083689
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2104482516
Short name T253
Test name
Test status
Simulation time 28065959 ps
CPU time 0.66 seconds
Started Mar 26 01:22:37 PM PDT 24
Finished Mar 26 01:22:38 PM PDT 24
Peak memory 203088 kb
Host smart-512c8a15-0946-4662-b1f7-3100fd581e5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2104482516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2104482516
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3488560712
Short name T932
Test name
Test status
Simulation time 22476733 ps
CPU time 0.69 seconds
Started Mar 26 01:22:30 PM PDT 24
Finished Mar 26 01:22:31 PM PDT 24
Peak memory 203044 kb
Host smart-9261919d-9407-4fb6-b11b-a0694a9dd0d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3488560712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3488560712
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1208631525
Short name T243
Test name
Test status
Simulation time 26172692 ps
CPU time 0.61 seconds
Started Mar 26 01:22:35 PM PDT 24
Finished Mar 26 01:22:36 PM PDT 24
Peak memory 203016 kb
Host smart-54ac5c69-c5e6-4251-972b-c9e15aecd8ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1208631525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.1208631525
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1680938773
Short name T177
Test name
Test status
Simulation time 132146072 ps
CPU time 1.81 seconds
Started Mar 26 01:22:20 PM PDT 24
Finished Mar 26 01:22:22 PM PDT 24
Peak memory 219660 kb
Host smart-dbcf2054-0b02-415e-9309-90d4aae7094b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680938773 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.1680938773
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1138601137
Short name T193
Test name
Test status
Simulation time 40406829 ps
CPU time 0.78 seconds
Started Mar 26 01:22:18 PM PDT 24
Finished Mar 26 01:22:18 PM PDT 24
Peak memory 203020 kb
Host smart-34be9377-1a1d-436f-98dc-b237f55a4a92
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138601137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1138601137
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.694847726
Short name T237
Test name
Test status
Simulation time 160475063 ps
CPU time 1.64 seconds
Started Mar 26 01:22:14 PM PDT 24
Finished Mar 26 01:22:16 PM PDT 24
Peak memory 203248 kb
Host smart-81d757e0-8edc-4cf3-b9db-1f8e62a5c630
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694847726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_cs
r_outstanding.694847726
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2448623060
Short name T180
Test name
Test status
Simulation time 109516531 ps
CPU time 1.65 seconds
Started Mar 26 01:22:15 PM PDT 24
Finished Mar 26 01:22:17 PM PDT 24
Peak memory 203184 kb
Host smart-13bcfeac-e201-47c3-89cb-6b4740674d60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2448623060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2448623060
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1800524201
Short name T261
Test name
Test status
Simulation time 279471202 ps
CPU time 2.71 seconds
Started Mar 26 01:22:15 PM PDT 24
Finished Mar 26 01:22:18 PM PDT 24
Peak memory 203172 kb
Host smart-198ef764-909a-4986-899f-9c35971c4566
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1800524201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1800524201
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.488061472
Short name T933
Test name
Test status
Simulation time 111685998 ps
CPU time 1.73 seconds
Started Mar 26 01:22:19 PM PDT 24
Finished Mar 26 01:22:21 PM PDT 24
Peak memory 211420 kb
Host smart-118fdb42-a671-426d-aa2f-bb19b85579ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488061472 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.488061472
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3674060946
Short name T195
Test name
Test status
Simulation time 29844576 ps
CPU time 0.77 seconds
Started Mar 26 01:22:17 PM PDT 24
Finished Mar 26 01:22:18 PM PDT 24
Peak memory 203008 kb
Host smart-af85593a-7143-4339-98c4-8e232ead810c
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674060946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3674060946
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1401427841
Short name T900
Test name
Test status
Simulation time 127420385 ps
CPU time 1.41 seconds
Started Mar 26 01:22:13 PM PDT 24
Finished Mar 26 01:22:15 PM PDT 24
Peak memory 203176 kb
Host smart-f39822da-2deb-425a-96f7-d8d0404074be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401427841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c
sr_outstanding.1401427841
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.40031293
Short name T182
Test name
Test status
Simulation time 102194616 ps
CPU time 1.37 seconds
Started Mar 26 01:22:19 PM PDT 24
Finished Mar 26 01:22:21 PM PDT 24
Peak memory 203184 kb
Host smart-51bc5247-5875-41bc-88a0-c28f49ece5d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=40031293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.40031293
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.865502187
Short name T264
Test name
Test status
Simulation time 239635618 ps
CPU time 2.58 seconds
Started Mar 26 01:22:15 PM PDT 24
Finished Mar 26 01:22:18 PM PDT 24
Peak memory 203332 kb
Host smart-f213a539-7944-45d4-8a96-98578335e051
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=865502187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.865502187
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1608648410
Short name T894
Test name
Test status
Simulation time 89906527 ps
CPU time 1.23 seconds
Started Mar 26 01:22:19 PM PDT 24
Finished Mar 26 01:22:21 PM PDT 24
Peak memory 212668 kb
Host smart-5cc294a7-fbb9-4faf-a5ba-98e978d3090f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608648410 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.1608648410
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2789648307
Short name T927
Test name
Test status
Simulation time 35876370 ps
CPU time 0.76 seconds
Started Mar 26 01:22:18 PM PDT 24
Finished Mar 26 01:22:19 PM PDT 24
Peak memory 203080 kb
Host smart-833596ae-c088-4405-9fa8-aaaf29297d2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789648307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2789648307
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.288813130
Short name T247
Test name
Test status
Simulation time 30891835 ps
CPU time 0.72 seconds
Started Mar 26 01:22:20 PM PDT 24
Finished Mar 26 01:22:21 PM PDT 24
Peak memory 203040 kb
Host smart-678f243c-c7e0-433e-9933-ebcd96e777a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=288813130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.288813130
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2458908063
Short name T200
Test name
Test status
Simulation time 68984150 ps
CPU time 1.05 seconds
Started Mar 26 01:22:20 PM PDT 24
Finished Mar 26 01:22:22 PM PDT 24
Peak memory 203204 kb
Host smart-e62b67da-c644-4d5d-8ebe-94e09eb4d0aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458908063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_c
sr_outstanding.2458908063
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2808259933
Short name T950
Test name
Test status
Simulation time 285218369 ps
CPU time 3.15 seconds
Started Mar 26 01:22:19 PM PDT 24
Finished Mar 26 01:22:23 PM PDT 24
Peak memory 203216 kb
Host smart-57e73335-1cdf-4e5f-8d18-1521556239bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2808259933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2808259933
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1928990499
Short name T265
Test name
Test status
Simulation time 258924315 ps
CPU time 2.84 seconds
Started Mar 26 01:22:17 PM PDT 24
Finished Mar 26 01:22:20 PM PDT 24
Peak memory 203208 kb
Host smart-d358c117-2546-4b7f-87b3-2983e78b68ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1928990499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1928990499
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2576647198
Short name T944
Test name
Test status
Simulation time 79313045 ps
CPU time 1.39 seconds
Started Mar 26 01:22:17 PM PDT 24
Finished Mar 26 01:22:18 PM PDT 24
Peak memory 211692 kb
Host smart-c3f4988e-9870-4930-a21a-046858cdb573
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576647198 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.2576647198
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1369885747
Short name T83
Test name
Test status
Simulation time 45529202 ps
CPU time 0.81 seconds
Started Mar 26 01:22:19 PM PDT 24
Finished Mar 26 01:22:20 PM PDT 24
Peak memory 203080 kb
Host smart-a46fd7a5-9d74-4903-b68f-25424467dc16
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369885747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1369885747
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4232888923
Short name T914
Test name
Test status
Simulation time 57992647 ps
CPU time 1.33 seconds
Started Mar 26 01:22:18 PM PDT 24
Finished Mar 26 01:22:19 PM PDT 24
Peak memory 203228 kb
Host smart-08fea098-6c30-4985-987b-f0d85e879fa7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232888923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_c
sr_outstanding.4232888923
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.259783207
Short name T232
Test name
Test status
Simulation time 86034126 ps
CPU time 2.54 seconds
Started Mar 26 01:22:23 PM PDT 24
Finished Mar 26 01:22:26 PM PDT 24
Peak memory 203184 kb
Host smart-c64c3ca5-c312-44df-9123-d17c99aef097
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=259783207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.259783207
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1160420960
Short name T266
Test name
Test status
Simulation time 293262041 ps
CPU time 2.68 seconds
Started Mar 26 01:22:20 PM PDT 24
Finished Mar 26 01:22:23 PM PDT 24
Peak memory 203068 kb
Host smart-64128aa1-c677-4ff4-ad3d-b7d111a5fbb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1160420960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.1160420960
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1945421055
Short name T949
Test name
Test status
Simulation time 77659447 ps
CPU time 1.28 seconds
Started Mar 26 01:22:22 PM PDT 24
Finished Mar 26 01:22:24 PM PDT 24
Peak memory 211400 kb
Host smart-3be30c39-3c6d-4635-92b5-d2c699866d1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945421055 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.1945421055
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1106327290
Short name T937
Test name
Test status
Simulation time 33905804 ps
CPU time 0.89 seconds
Started Mar 26 01:22:16 PM PDT 24
Finished Mar 26 01:22:18 PM PDT 24
Peak memory 203156 kb
Host smart-263be58a-80fe-4698-bb46-9037072b575a
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106327290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1106327290
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1662902072
Short name T235
Test name
Test status
Simulation time 146613905 ps
CPU time 1.41 seconds
Started Mar 26 01:22:20 PM PDT 24
Finished Mar 26 01:22:21 PM PDT 24
Peak memory 203232 kb
Host smart-54c7fc0c-7bf8-4b7b-92a4-0740990249e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662902072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_c
sr_outstanding.1662902072
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3237890504
Short name T911
Test name
Test status
Simulation time 126888122 ps
CPU time 1.67 seconds
Started Mar 26 01:22:18 PM PDT 24
Finished Mar 26 01:22:20 PM PDT 24
Peak memory 203264 kb
Host smart-a9ae2699-35e8-4330-8407-feb064e4648d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3237890504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3237890504
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.817710589
Short name T761
Test name
Test status
Simulation time 8368136398 ps
CPU time 7.15 seconds
Started Mar 26 02:52:07 PM PDT 24
Finished Mar 26 02:52:14 PM PDT 24
Peak memory 203476 kb
Host smart-23c4815b-c1a7-41bc-8429-5eeef2a6a706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81771
0589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.817710589
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_enable.367273939
Short name T502
Test name
Test status
Simulation time 8369961879 ps
CPU time 8.27 seconds
Started Mar 26 02:52:06 PM PDT 24
Finished Mar 26 02:52:14 PM PDT 24
Peak memory 203460 kb
Host smart-64f88b14-5252-47a7-b251-b453970f50e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36727
3939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.367273939
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.306828530
Short name T317
Test name
Test status
Simulation time 152730144 ps
CPU time 1.44 seconds
Started Mar 26 02:52:04 PM PDT 24
Finished Mar 26 02:52:05 PM PDT 24
Peak memory 203596 kb
Host smart-fe48200a-f4e8-4bd8-8dcf-bb2d0dbc66da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30682
8530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.306828530
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2323279146
Short name T816
Test name
Test status
Simulation time 8363055481 ps
CPU time 7.48 seconds
Started Mar 26 02:52:09 PM PDT 24
Finished Mar 26 02:52:17 PM PDT 24
Peak memory 203476 kb
Host smart-45dd788a-33c3-4365-9c33-ba4bd080f541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23232
79146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2323279146
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.636260702
Short name T550
Test name
Test status
Simulation time 8421752635 ps
CPU time 9.38 seconds
Started Mar 26 02:52:05 PM PDT 24
Finished Mar 26 02:52:15 PM PDT 24
Peak memory 203456 kb
Host smart-03615308-0252-4868-9a1a-b7aa27dd1326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63626
0702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.636260702
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.951592895
Short name T227
Test name
Test status
Simulation time 8408084976 ps
CPU time 8.51 seconds
Started Mar 26 02:52:05 PM PDT 24
Finished Mar 26 02:52:13 PM PDT 24
Peak memory 203464 kb
Host smart-232efec8-1bf9-4ac8-844c-c16c9bd417ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95159
2895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.951592895
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.3228382671
Short name T613
Test name
Test status
Simulation time 8364852018 ps
CPU time 7.72 seconds
Started Mar 26 02:52:04 PM PDT 24
Finished Mar 26 02:52:12 PM PDT 24
Peak memory 203508 kb
Host smart-dd8d2b3a-3597-4354-8340-e05e6b6c24af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32283
82671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.3228382671
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.404622124
Short name T565
Test name
Test status
Simulation time 8368486946 ps
CPU time 8 seconds
Started Mar 26 02:52:06 PM PDT 24
Finished Mar 26 02:52:14 PM PDT 24
Peak memory 203476 kb
Host smart-afe78c8f-f3c6-4b55-a3c8-5a7d04dca96f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40462
2124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.404622124
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1707408056
Short name T396
Test name
Test status
Simulation time 21477594 ps
CPU time 0.63 seconds
Started Mar 26 02:52:14 PM PDT 24
Finished Mar 26 02:52:15 PM PDT 24
Peak memory 203332 kb
Host smart-4e693ae0-9239-480f-a38e-a8ac79533c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17074
08056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1707408056
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.1058990269
Short name T594
Test name
Test status
Simulation time 8370971255 ps
CPU time 8.5 seconds
Started Mar 26 02:51:58 PM PDT 24
Finished Mar 26 02:52:07 PM PDT 24
Peak memory 203484 kb
Host smart-f0982361-9a50-46dc-adec-aae400076a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10589
90269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.1058990269
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1996755540
Short name T780
Test name
Test status
Simulation time 8456211301 ps
CPU time 8.8 seconds
Started Mar 26 02:52:08 PM PDT 24
Finished Mar 26 02:52:17 PM PDT 24
Peak memory 203404 kb
Host smart-60bd7c4d-36c0-46ea-a4cd-217f8718815a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19967
55540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1996755540
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.1232195705
Short name T361
Test name
Test status
Simulation time 8390728846 ps
CPU time 7.31 seconds
Started Mar 26 02:52:12 PM PDT 24
Finished Mar 26 02:52:19 PM PDT 24
Peak memory 203468 kb
Host smart-fbbed0ec-03fd-45dd-9862-6026ffe9094e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12321
95705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.1232195705
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.4039152676
Short name T68
Test name
Test status
Simulation time 162578645 ps
CPU time 1.07 seconds
Started Mar 26 02:52:09 PM PDT 24
Finished Mar 26 02:52:10 PM PDT 24
Peak memory 220432 kb
Host smart-bf92cf6c-ad49-476b-9cdb-43194711ff19
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4039152676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.4039152676
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.3650336685
Short name T607
Test name
Test status
Simulation time 8356998395 ps
CPU time 7.33 seconds
Started Mar 26 02:52:07 PM PDT 24
Finished Mar 26 02:52:14 PM PDT 24
Peak memory 203332 kb
Host smart-2a19b336-238c-4190-818f-943aba76b4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36503
36685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.3650336685
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1379421839
Short name T328
Test name
Test status
Simulation time 8369452352 ps
CPU time 6.96 seconds
Started Mar 26 02:52:11 PM PDT 24
Finished Mar 26 02:52:18 PM PDT 24
Peak memory 203448 kb
Host smart-bf03aa4b-8bfb-4b41-81f3-70b026b36379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13794
21839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1379421839
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_enable.394632837
Short name T46
Test name
Test status
Simulation time 8374150828 ps
CPU time 9.46 seconds
Started Mar 26 02:52:12 PM PDT 24
Finished Mar 26 02:52:21 PM PDT 24
Peak memory 203496 kb
Host smart-7f972bbb-ced1-46a0-b86f-ac04e1c1cf6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39463
2837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.394632837
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.3108921054
Short name T853
Test name
Test status
Simulation time 37775639 ps
CPU time 1.01 seconds
Started Mar 26 02:52:09 PM PDT 24
Finished Mar 26 02:52:11 PM PDT 24
Peak memory 203564 kb
Host smart-b971e3c4-8f20-4ce8-94a2-75b01ee55c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31089
21054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.3108921054
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.3168968238
Short name T411
Test name
Test status
Simulation time 8395580294 ps
CPU time 7.81 seconds
Started Mar 26 02:51:57 PM PDT 24
Finished Mar 26 02:52:05 PM PDT 24
Peak memory 203396 kb
Host smart-330527a8-7510-43d4-b37a-852d4bd5c8a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31689
68238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.3168968238
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2506785507
Short name T275
Test name
Test status
Simulation time 8413206990 ps
CPU time 7.07 seconds
Started Mar 26 02:52:10 PM PDT 24
Finished Mar 26 02:52:17 PM PDT 24
Peak memory 203436 kb
Host smart-543eed4a-7db5-49e1-b0bb-9434c64744a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25067
85507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2506785507
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.1956063296
Short name T493
Test name
Test status
Simulation time 8359787069 ps
CPU time 7.53 seconds
Started Mar 26 02:52:09 PM PDT 24
Finished Mar 26 02:52:16 PM PDT 24
Peak memory 203484 kb
Host smart-3fac3f3d-7f57-42bd-bfa5-463f8f866d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19560
63296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.1956063296
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.1806717556
Short name T732
Test name
Test status
Simulation time 8358997671 ps
CPU time 7.27 seconds
Started Mar 26 02:52:09 PM PDT 24
Finished Mar 26 02:52:17 PM PDT 24
Peak memory 203464 kb
Host smart-5201a733-73bb-4da1-ae83-7b8df14e4ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18067
17556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.1806717556
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.547078874
Short name T433
Test name
Test status
Simulation time 8373637894 ps
CPU time 7.38 seconds
Started Mar 26 02:52:04 PM PDT 24
Finished Mar 26 02:52:11 PM PDT 24
Peak memory 203456 kb
Host smart-f95b1e97-765f-4bb2-bcc4-fc3fb669c985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54707
8874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.547078874
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3008714493
Short name T766
Test name
Test status
Simulation time 23529944 ps
CPU time 0.66 seconds
Started Mar 26 02:52:07 PM PDT 24
Finished Mar 26 02:52:08 PM PDT 24
Peak memory 203272 kb
Host smart-9ac13a2e-aec2-458d-adb0-81ede045d17b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30087
14493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3008714493
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.2983157121
Short name T532
Test name
Test status
Simulation time 8411171164 ps
CPU time 7.99 seconds
Started Mar 26 02:52:08 PM PDT 24
Finished Mar 26 02:52:17 PM PDT 24
Peak memory 203472 kb
Host smart-1b503c37-a3e0-4e7c-8899-e5cd0d10e5e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29831
57121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.2983157121
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.1793710708
Short name T604
Test name
Test status
Simulation time 8417228932 ps
CPU time 7.75 seconds
Started Mar 26 02:52:04 PM PDT 24
Finished Mar 26 02:52:12 PM PDT 24
Peak memory 203472 kb
Host smart-16f75215-b796-4fda-a5bd-d47d7d7d1959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17937
10708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.1793710708
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.652429416
Short name T663
Test name
Test status
Simulation time 8394734953 ps
CPU time 8 seconds
Started Mar 26 02:52:18 PM PDT 24
Finished Mar 26 02:52:27 PM PDT 24
Peak memory 203456 kb
Host smart-64ebc5e5-0b24-4f8c-b6ad-ac995ce0a04c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65242
9416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.652429416
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.2684058714
Short name T56
Test name
Test status
Simulation time 191557471 ps
CPU time 1.06 seconds
Started Mar 26 02:52:06 PM PDT 24
Finished Mar 26 02:52:07 PM PDT 24
Peak memory 220304 kb
Host smart-ba80b73a-9c10-4020-8deb-c147121bb708
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2684058714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2684058714
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.4049751281
Short name T814
Test name
Test status
Simulation time 8359560270 ps
CPU time 6.94 seconds
Started Mar 26 02:52:07 PM PDT 24
Finished Mar 26 02:52:14 PM PDT 24
Peak memory 203396 kb
Host smart-51059576-c52f-4f33-88a5-6b3cac23b9c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40497
51281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.4049751281
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.198855919
Short name T78
Test name
Test status
Simulation time 8474457047 ps
CPU time 8.67 seconds
Started Mar 26 02:52:06 PM PDT 24
Finished Mar 26 02:52:15 PM PDT 24
Peak memory 203516 kb
Host smart-88e86a13-bb29-4328-b8de-bfccf3143e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19885
5919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.198855919
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.3432608066
Short name T531
Test name
Test status
Simulation time 8370782869 ps
CPU time 8 seconds
Started Mar 26 02:52:21 PM PDT 24
Finished Mar 26 02:52:29 PM PDT 24
Peak memory 203448 kb
Host smart-f479471e-a235-42a3-8a33-7b63e2884b0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34326
08066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3432608066
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_enable.3417639358
Short name T845
Test name
Test status
Simulation time 8365859285 ps
CPU time 7.64 seconds
Started Mar 26 02:52:25 PM PDT 24
Finished Mar 26 02:52:32 PM PDT 24
Peak memory 203508 kb
Host smart-a380e189-0255-465c-b0d0-625972aa1ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34176
39358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.3417639358
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.2454745967
Short name T222
Test name
Test status
Simulation time 184211260 ps
CPU time 2.17 seconds
Started Mar 26 02:52:40 PM PDT 24
Finished Mar 26 02:52:42 PM PDT 24
Peak memory 203564 kb
Host smart-dac8007e-9d8b-4888-be9a-19c60a24d6c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24547
45967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.2454745967
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.3246361326
Short name T376
Test name
Test status
Simulation time 8360488952 ps
CPU time 7.92 seconds
Started Mar 26 02:52:19 PM PDT 24
Finished Mar 26 02:52:27 PM PDT 24
Peak memory 203468 kb
Host smart-228e5881-79b6-4bcc-a4da-24d257bd6a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32463
61326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.3246361326
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.944325804
Short name T130
Test name
Test status
Simulation time 8406505852 ps
CPU time 8.02 seconds
Started Mar 26 02:52:22 PM PDT 24
Finished Mar 26 02:52:30 PM PDT 24
Peak memory 203452 kb
Host smart-b67eb05c-2c32-477b-b876-4d0f86e00c73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94432
5804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.944325804
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.1573904293
Short name T454
Test name
Test status
Simulation time 8410956702 ps
CPU time 7.32 seconds
Started Mar 26 02:52:39 PM PDT 24
Finished Mar 26 02:52:47 PM PDT 24
Peak memory 203336 kb
Host smart-0ab2dee0-ba6b-4d83-91f5-a6a5b57b5aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15739
04293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.1573904293
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.3649581418
Short name T294
Test name
Test status
Simulation time 8365469708 ps
CPU time 7.69 seconds
Started Mar 26 02:52:20 PM PDT 24
Finished Mar 26 02:52:28 PM PDT 24
Peak memory 203316 kb
Host smart-72ce0c19-aa88-470c-b930-405c142c0501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36495
81418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.3649581418
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.23145540
Short name T836
Test name
Test status
Simulation time 8422892399 ps
CPU time 7.51 seconds
Started Mar 26 02:52:44 PM PDT 24
Finished Mar 26 02:52:52 PM PDT 24
Peak memory 203452 kb
Host smart-1d298d62-b534-436f-9017-0758710f3b95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23145
540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.23145540
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.3109982878
Short name T313
Test name
Test status
Simulation time 8405267802 ps
CPU time 7.21 seconds
Started Mar 26 02:52:25 PM PDT 24
Finished Mar 26 02:52:32 PM PDT 24
Peak memory 203512 kb
Host smart-8385048d-5e77-4f25-b0f8-974d44b60580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31099
82878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.3109982878
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2523528750
Short name T772
Test name
Test status
Simulation time 8367007489 ps
CPU time 6.94 seconds
Started Mar 26 02:52:23 PM PDT 24
Finished Mar 26 02:52:30 PM PDT 24
Peak memory 203368 kb
Host smart-1e90aa83-3d3d-45e2-ad03-bfa1fceff5b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25235
28750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2523528750
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.687863306
Short name T794
Test name
Test status
Simulation time 25843177 ps
CPU time 0.67 seconds
Started Mar 26 02:52:22 PM PDT 24
Finished Mar 26 02:52:23 PM PDT 24
Peak memory 203356 kb
Host smart-8f3e78a8-41fd-4406-aa56-789f8b77e8ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68786
3306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.687863306
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.3313669046
Short name T290
Test name
Test status
Simulation time 8365084119 ps
CPU time 8.9 seconds
Started Mar 26 02:52:31 PM PDT 24
Finished Mar 26 02:52:40 PM PDT 24
Peak memory 203448 kb
Host smart-26fc6f28-9ceb-497b-aa5e-91011c341238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33136
69046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.3313669046
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.869944936
Short name T647
Test name
Test status
Simulation time 8440813242 ps
CPU time 9.29 seconds
Started Mar 26 02:52:24 PM PDT 24
Finished Mar 26 02:52:34 PM PDT 24
Peak memory 203472 kb
Host smart-45460b8a-6284-4ac9-b503-4593c6a87175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86994
4936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.869944936
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.766521313
Short name T699
Test name
Test status
Simulation time 8386094997 ps
CPU time 9.1 seconds
Started Mar 26 02:52:16 PM PDT 24
Finished Mar 26 02:52:25 PM PDT 24
Peak memory 203436 kb
Host smart-094d9c57-4a69-4d21-991d-dcb9fe977b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76652
1313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.766521313
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.3067764938
Short name T779
Test name
Test status
Simulation time 8354118376 ps
CPU time 8.03 seconds
Started Mar 26 02:52:31 PM PDT 24
Finished Mar 26 02:52:39 PM PDT 24
Peak memory 203472 kb
Host smart-23991180-8309-4e6f-9982-548fc8e8dfe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30677
64938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.3067764938
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.2215526800
Short name T343
Test name
Test status
Simulation time 8366607788 ps
CPU time 6.8 seconds
Started Mar 26 02:52:33 PM PDT 24
Finished Mar 26 02:52:40 PM PDT 24
Peak memory 203436 kb
Host smart-78106d66-ce37-4079-89d3-4c0adbb73c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22155
26800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.2215526800
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_enable.783429301
Short name T344
Test name
Test status
Simulation time 8368943546 ps
CPU time 7.08 seconds
Started Mar 26 02:52:23 PM PDT 24
Finished Mar 26 02:52:30 PM PDT 24
Peak memory 203484 kb
Host smart-bda2fe9b-5095-41ae-bfb3-a8d72a245351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78342
9301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.783429301
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.3962922944
Short name T715
Test name
Test status
Simulation time 56991080 ps
CPU time 1.62 seconds
Started Mar 26 02:52:20 PM PDT 24
Finished Mar 26 02:52:22 PM PDT 24
Peak memory 203572 kb
Host smart-f9a874de-21d8-4074-905e-fd0275e9581d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39629
22944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3962922944
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.504021046
Short name T643
Test name
Test status
Simulation time 8362540256 ps
CPU time 6.91 seconds
Started Mar 26 02:52:29 PM PDT 24
Finished Mar 26 02:52:36 PM PDT 24
Peak memory 203408 kb
Host smart-9952c44c-0983-44cf-aca6-c75feb0466e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50402
1046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.504021046
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.389523050
Short name T792
Test name
Test status
Simulation time 8416327775 ps
CPU time 8.07 seconds
Started Mar 26 02:52:24 PM PDT 24
Finished Mar 26 02:52:32 PM PDT 24
Peak memory 203036 kb
Host smart-d975ebc1-8239-456d-9f10-c6f31f2acc02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38952
3050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.389523050
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.3383210685
Short name T813
Test name
Test status
Simulation time 8409690128 ps
CPU time 7.1 seconds
Started Mar 26 02:53:03 PM PDT 24
Finished Mar 26 02:53:11 PM PDT 24
Peak memory 203456 kb
Host smart-0e548c37-0d17-48fd-83df-98d32750bb11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33832
10685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.3383210685
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.649955956
Short name T636
Test name
Test status
Simulation time 8365906820 ps
CPU time 9.12 seconds
Started Mar 26 02:52:39 PM PDT 24
Finished Mar 26 02:52:49 PM PDT 24
Peak memory 203344 kb
Host smart-71cb798a-5363-4a4c-86c6-ddefc8b5a181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64995
5956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.649955956
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.1127617453
Short name T103
Test name
Test status
Simulation time 8413910372 ps
CPU time 8.71 seconds
Started Mar 26 02:52:25 PM PDT 24
Finished Mar 26 02:52:34 PM PDT 24
Peak memory 203464 kb
Host smart-3c5936a3-0351-4bbd-b00b-0f0a838a0fe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11276
17453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.1127617453
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.3636302052
Short name T204
Test name
Test status
Simulation time 8364595696 ps
CPU time 9.31 seconds
Started Mar 26 02:52:49 PM PDT 24
Finished Mar 26 02:52:59 PM PDT 24
Peak memory 203492 kb
Host smart-554abbb3-4294-462e-853c-f621b439d852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36363
02052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.3636302052
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1819210319
Short name T590
Test name
Test status
Simulation time 8366726056 ps
CPU time 9.04 seconds
Started Mar 26 02:52:27 PM PDT 24
Finished Mar 26 02:52:36 PM PDT 24
Peak memory 203484 kb
Host smart-f387b798-1d83-4122-b108-fdcef4c0b4d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18192
10319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1819210319
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1144789399
Short name T387
Test name
Test status
Simulation time 23878640 ps
CPU time 0.63 seconds
Started Mar 26 02:52:42 PM PDT 24
Finished Mar 26 02:52:43 PM PDT 24
Peak memory 203360 kb
Host smart-0346a60f-2a03-4f82-b3f6-477c23cfa567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11447
89399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1144789399
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.2692941909
Short name T593
Test name
Test status
Simulation time 8402644339 ps
CPU time 7.18 seconds
Started Mar 26 02:52:45 PM PDT 24
Finished Mar 26 02:52:52 PM PDT 24
Peak memory 203468 kb
Host smart-ae112c50-e541-493f-b69a-378f45a41aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26929
41909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.2692941909
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.2282968150
Short name T120
Test name
Test status
Simulation time 8378150799 ps
CPU time 7.63 seconds
Started Mar 26 02:52:24 PM PDT 24
Finished Mar 26 02:52:31 PM PDT 24
Peak memory 203456 kb
Host smart-93e25a21-b742-4b7c-84f9-c6441a4fa5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22829
68150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.2282968150
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.3260402205
Short name T423
Test name
Test status
Simulation time 8362635770 ps
CPU time 8.51 seconds
Started Mar 26 02:52:37 PM PDT 24
Finished Mar 26 02:52:46 PM PDT 24
Peak memory 203484 kb
Host smart-4e3ce1d4-9d01-4825-aef2-2ae26ca8bbe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32604
02205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.3260402205
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.3075173061
Short name T868
Test name
Test status
Simulation time 8360023719 ps
CPU time 7.28 seconds
Started Mar 26 02:52:41 PM PDT 24
Finished Mar 26 02:52:49 PM PDT 24
Peak memory 203480 kb
Host smart-ab080dc6-c79e-46f7-8b28-368ce6bfc97c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30751
73061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.3075173061
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.1700625808
Short name T621
Test name
Test status
Simulation time 8373852684 ps
CPU time 9.4 seconds
Started Mar 26 02:52:46 PM PDT 24
Finished Mar 26 02:52:56 PM PDT 24
Peak memory 203448 kb
Host smart-81171ae2-f0b0-4f0b-9a53-1ef2cfa9e461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17006
25808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.1700625808
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_enable.85229717
Short name T526
Test name
Test status
Simulation time 8370026706 ps
CPU time 7.68 seconds
Started Mar 26 02:52:24 PM PDT 24
Finished Mar 26 02:52:37 PM PDT 24
Peak memory 203452 kb
Host smart-bcfe4f15-0f66-4fdc-9a6c-ca408c0e875c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85229
717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.85229717
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.551482915
Short name T50
Test name
Test status
Simulation time 92574210 ps
CPU time 1.28 seconds
Started Mar 26 02:52:41 PM PDT 24
Finished Mar 26 02:52:42 PM PDT 24
Peak memory 203556 kb
Host smart-3fccb69c-3b1b-4376-b942-365e14e5417c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55148
2915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.551482915
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.727235362
Short name T767
Test name
Test status
Simulation time 8362826626 ps
CPU time 9.61 seconds
Started Mar 26 02:52:48 PM PDT 24
Finished Mar 26 02:52:58 PM PDT 24
Peak memory 203460 kb
Host smart-6a97147e-8dd3-496f-8ad4-354591997fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72723
5362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.727235362
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.1594186014
Short name T75
Test name
Test status
Simulation time 8405878654 ps
CPU time 8.22 seconds
Started Mar 26 02:52:47 PM PDT 24
Finished Mar 26 02:52:55 PM PDT 24
Peak memory 203464 kb
Host smart-5f9e66c0-eefa-4f75-b25b-a6a2dcfc7240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15941
86014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.1594186014
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.3796257302
Short name T753
Test name
Test status
Simulation time 8411583937 ps
CPU time 9.1 seconds
Started Mar 26 02:52:35 PM PDT 24
Finished Mar 26 02:52:45 PM PDT 24
Peak memory 203416 kb
Host smart-58f58516-4866-4c3b-8f9a-49e7b01e401b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37962
57302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.3796257302
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.769042763
Short name T332
Test name
Test status
Simulation time 8366318256 ps
CPU time 7.63 seconds
Started Mar 26 02:52:25 PM PDT 24
Finished Mar 26 02:52:33 PM PDT 24
Peak memory 203472 kb
Host smart-5db05a4c-0af2-43bf-9b37-69ce338f29af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76904
2763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.769042763
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.3222507462
Short name T403
Test name
Test status
Simulation time 8403775061 ps
CPU time 8.21 seconds
Started Mar 26 02:52:24 PM PDT 24
Finished Mar 26 02:52:37 PM PDT 24
Peak memory 202916 kb
Host smart-d40a8b5a-7113-4f97-a851-3f32c1f6409f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32225
07462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.3222507462
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.359577589
Short name T718
Test name
Test status
Simulation time 8395420488 ps
CPU time 7.25 seconds
Started Mar 26 02:52:25 PM PDT 24
Finished Mar 26 02:52:32 PM PDT 24
Peak memory 203488 kb
Host smart-30ae2f95-b62d-46e0-8a13-f675ecb46246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35957
7589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.359577589
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.3000999841
Short name T838
Test name
Test status
Simulation time 28450294 ps
CPU time 0.62 seconds
Started Mar 26 02:53:00 PM PDT 24
Finished Mar 26 02:53:01 PM PDT 24
Peak memory 203212 kb
Host smart-1b71d890-bd92-4b29-808b-5a4a59468c03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30009
99841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.3000999841
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.463293862
Short name T830
Test name
Test status
Simulation time 8377505846 ps
CPU time 7.32 seconds
Started Mar 26 02:52:26 PM PDT 24
Finished Mar 26 02:52:34 PM PDT 24
Peak memory 203456 kb
Host smart-100291a1-8e63-4ffa-ab88-9c8f8b76141b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46329
3862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.463293862
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2701890408
Short name T210
Test name
Test status
Simulation time 8409330639 ps
CPU time 8.95 seconds
Started Mar 26 02:52:56 PM PDT 24
Finished Mar 26 02:53:05 PM PDT 24
Peak memory 203364 kb
Host smart-8208afe8-b158-438c-b729-a5a292855584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27018
90408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2701890408
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.2622136174
Short name T326
Test name
Test status
Simulation time 8391202838 ps
CPU time 7.11 seconds
Started Mar 26 02:52:57 PM PDT 24
Finished Mar 26 02:53:04 PM PDT 24
Peak memory 203412 kb
Host smart-af71fe65-b296-4d17-b585-edf97d092607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26221
36174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.2622136174
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.879771774
Short name T528
Test name
Test status
Simulation time 8361810707 ps
CPU time 7.72 seconds
Started Mar 26 02:53:06 PM PDT 24
Finished Mar 26 02:53:14 PM PDT 24
Peak memory 203484 kb
Host smart-a967924a-61a1-4595-897d-2baccd5d4741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87977
1774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.879771774
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.1508866149
Short name T365
Test name
Test status
Simulation time 8475060170 ps
CPU time 8.42 seconds
Started Mar 26 02:52:28 PM PDT 24
Finished Mar 26 02:52:37 PM PDT 24
Peak memory 203504 kb
Host smart-7766f9e0-85be-4c02-bd0a-22c0969d3102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15088
66149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.1508866149
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.1411728599
Short name T731
Test name
Test status
Simulation time 8367315528 ps
CPU time 7.28 seconds
Started Mar 26 02:52:45 PM PDT 24
Finished Mar 26 02:52:52 PM PDT 24
Peak memory 203340 kb
Host smart-9b5a1974-1b8f-484b-a248-19ae6dd50539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14117
28599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.1411728599
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_enable.1643776578
Short name T706
Test name
Test status
Simulation time 8370864624 ps
CPU time 7.76 seconds
Started Mar 26 02:52:38 PM PDT 24
Finished Mar 26 02:52:46 PM PDT 24
Peak memory 203480 kb
Host smart-5f52fa61-9988-41db-9676-84f52bfae392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16437
76578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.1643776578
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.4043728585
Short name T539
Test name
Test status
Simulation time 108913105 ps
CPU time 1.46 seconds
Started Mar 26 02:53:01 PM PDT 24
Finished Mar 26 02:53:03 PM PDT 24
Peak memory 203524 kb
Host smart-be4038d8-e500-4735-a888-69d2f09f9a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40437
28585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.4043728585
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.3884186740
Short name T155
Test name
Test status
Simulation time 8358144271 ps
CPU time 8.71 seconds
Started Mar 26 02:53:02 PM PDT 24
Finished Mar 26 02:53:11 PM PDT 24
Peak memory 203436 kb
Host smart-4916b3f8-7099-4a0e-b6ea-ed00d38a1dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38841
86740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.3884186740
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.1877683785
Short name T671
Test name
Test status
Simulation time 8377641130 ps
CPU time 8.55 seconds
Started Mar 26 02:52:49 PM PDT 24
Finished Mar 26 02:52:58 PM PDT 24
Peak memory 203348 kb
Host smart-d744fe45-3af4-4866-8fbe-8f730381353e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18776
83785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1877683785
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.1438351683
Short name T358
Test name
Test status
Simulation time 8411408339 ps
CPU time 7.44 seconds
Started Mar 26 02:52:46 PM PDT 24
Finished Mar 26 02:52:53 PM PDT 24
Peak memory 203408 kb
Host smart-c427c044-dcd4-4849-a19b-d94bac7adada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14383
51683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.1438351683
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.2983261863
Short name T746
Test name
Test status
Simulation time 8366206941 ps
CPU time 7.06 seconds
Started Mar 26 02:52:43 PM PDT 24
Finished Mar 26 02:52:50 PM PDT 24
Peak memory 203484 kb
Host smart-5f168f33-de49-42a2-a485-516a89506556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29832
61863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.2983261863
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.1868092584
Short name T102
Test name
Test status
Simulation time 8400567714 ps
CPU time 7.09 seconds
Started Mar 26 02:52:49 PM PDT 24
Finished Mar 26 02:52:57 PM PDT 24
Peak memory 203476 kb
Host smart-90c7a32d-d1ff-46ba-a0e1-7a187d0351b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18680
92584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.1868092584
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.3292879786
Short name T300
Test name
Test status
Simulation time 8379224180 ps
CPU time 8.97 seconds
Started Mar 26 02:52:57 PM PDT 24
Finished Mar 26 02:53:07 PM PDT 24
Peak memory 203468 kb
Host smart-389da9b0-ce81-488d-b52e-b1218e5420b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32928
79786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3292879786
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.3061509273
Short name T71
Test name
Test status
Simulation time 8401441534 ps
CPU time 7.72 seconds
Started Mar 26 02:52:49 PM PDT 24
Finished Mar 26 02:52:57 PM PDT 24
Peak memory 203472 kb
Host smart-851038b7-f727-4bc3-af61-0947399d62ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30615
09273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.3061509273
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.19533267
Short name T37
Test name
Test status
Simulation time 28307700 ps
CPU time 0.64 seconds
Started Mar 26 02:52:48 PM PDT 24
Finished Mar 26 02:52:49 PM PDT 24
Peak memory 203388 kb
Host smart-9f1b4115-4b5d-463b-aeb5-6a72cb15eded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19533
267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.19533267
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.3055015150
Short name T784
Test name
Test status
Simulation time 8438070725 ps
CPU time 9.34 seconds
Started Mar 26 02:52:55 PM PDT 24
Finished Mar 26 02:53:05 PM PDT 24
Peak memory 203500 kb
Host smart-d31947d7-e661-4c3b-b7b9-6b5dd20c03eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30550
15150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.3055015150
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.1361150490
Short name T880
Test name
Test status
Simulation time 8377879510 ps
CPU time 7.39 seconds
Started Mar 26 02:53:03 PM PDT 24
Finished Mar 26 02:53:10 PM PDT 24
Peak memory 203504 kb
Host smart-009fc95e-92a9-4279-bd14-bbeabec49949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13611
50490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.1361150490
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_smoke.2213242759
Short name T865
Test name
Test status
Simulation time 8469816994 ps
CPU time 7.15 seconds
Started Mar 26 02:52:44 PM PDT 24
Finished Mar 26 02:52:52 PM PDT 24
Peak memory 203472 kb
Host smart-30840905-769f-4a5e-b44f-68866815443c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22132
42759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.2213242759
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.53730235
Short name T378
Test name
Test status
Simulation time 8369409974 ps
CPU time 8.03 seconds
Started Mar 26 02:52:46 PM PDT 24
Finished Mar 26 02:52:55 PM PDT 24
Peak memory 203472 kb
Host smart-421e36d2-7517-4bd3-b461-5ca361bad347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53730
235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.53730235
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_enable.2848281875
Short name T207
Test name
Test status
Simulation time 8366799697 ps
CPU time 9.53 seconds
Started Mar 26 02:52:50 PM PDT 24
Finished Mar 26 02:53:00 PM PDT 24
Peak memory 203464 kb
Host smart-52fcb5f5-2591-44b2-914b-a46594d57dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28482
81875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.2848281875
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.3469728035
Short name T6
Test name
Test status
Simulation time 8357364485 ps
CPU time 7.87 seconds
Started Mar 26 02:52:50 PM PDT 24
Finished Mar 26 02:52:58 PM PDT 24
Peak memory 203440 kb
Host smart-33d6c057-e20e-4409-aa52-fac76e1feac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34697
28035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3469728035
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.3137995574
Short name T540
Test name
Test status
Simulation time 8454517575 ps
CPU time 7.41 seconds
Started Mar 26 02:52:56 PM PDT 24
Finished Mar 26 02:53:04 PM PDT 24
Peak memory 203488 kb
Host smart-25acc7e2-5dc2-4973-9796-60c243203416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31379
95574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.3137995574
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.2063137285
Short name T360
Test name
Test status
Simulation time 8404988412 ps
CPU time 8.43 seconds
Started Mar 26 02:53:02 PM PDT 24
Finished Mar 26 02:53:16 PM PDT 24
Peak memory 203480 kb
Host smart-10fe7fb8-b8d8-4751-83ee-7d0fc9cf8de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20631
37285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.2063137285
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.2889841403
Short name T611
Test name
Test status
Simulation time 8363256872 ps
CPU time 9.22 seconds
Started Mar 26 02:52:49 PM PDT 24
Finished Mar 26 02:52:59 PM PDT 24
Peak memory 203476 kb
Host smart-6fd4e917-87a7-44c9-924e-f1954f1493cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28898
41403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.2889841403
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.4159146628
Short name T96
Test name
Test status
Simulation time 8398816120 ps
CPU time 7.08 seconds
Started Mar 26 02:52:48 PM PDT 24
Finished Mar 26 02:52:56 PM PDT 24
Peak memory 203464 kb
Host smart-c6c237e4-e430-4ba9-b0bc-6a0914e1c06e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41591
46628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.4159146628
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.3551718348
Short name T796
Test name
Test status
Simulation time 8399840261 ps
CPU time 9.38 seconds
Started Mar 26 02:52:39 PM PDT 24
Finished Mar 26 02:52:49 PM PDT 24
Peak memory 203476 kb
Host smart-3229994a-20b1-42b4-ace1-b74e2d10efee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35517
18348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.3551718348
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.3506822335
Short name T851
Test name
Test status
Simulation time 8368170047 ps
CPU time 7.23 seconds
Started Mar 26 02:52:45 PM PDT 24
Finished Mar 26 02:52:53 PM PDT 24
Peak memory 203480 kb
Host smart-e25ebb89-474e-47fd-9454-be74cba20e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35068
22335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.3506822335
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2898117211
Short name T585
Test name
Test status
Simulation time 32335492 ps
CPU time 0.66 seconds
Started Mar 26 02:52:41 PM PDT 24
Finished Mar 26 02:52:42 PM PDT 24
Peak memory 203368 kb
Host smart-a6bf53b7-b24d-4c62-bc7d-bd7119429e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28981
17211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2898117211
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.3907553669
Short name T306
Test name
Test status
Simulation time 8372873193 ps
CPU time 8.02 seconds
Started Mar 26 02:52:42 PM PDT 24
Finished Mar 26 02:52:50 PM PDT 24
Peak memory 203460 kb
Host smart-79636f59-44ce-4e4c-82d0-4c4054a0301e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39075
53669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.3907553669
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.3214667266
Short name T694
Test name
Test status
Simulation time 8402072659 ps
CPU time 7.13 seconds
Started Mar 26 02:52:49 PM PDT 24
Finished Mar 26 02:52:57 PM PDT 24
Peak memory 203476 kb
Host smart-e5290ba3-5163-4114-8710-712d6a9d3512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32146
67266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.3214667266
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.3664486614
Short name T452
Test name
Test status
Simulation time 8396993901 ps
CPU time 7.23 seconds
Started Mar 26 02:52:46 PM PDT 24
Finished Mar 26 02:52:53 PM PDT 24
Peak memory 203468 kb
Host smart-3c00c821-2c03-4495-bb9f-cd76e1f23816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36644
86614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.3664486614
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.3582332885
Short name T14
Test name
Test status
Simulation time 8358316803 ps
CPU time 7.88 seconds
Started Mar 26 02:52:54 PM PDT 24
Finished Mar 26 02:53:02 PM PDT 24
Peak memory 203504 kb
Host smart-650e4c88-4805-4dff-875b-492df8b0da82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35823
32885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.3582332885
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.354420957
Short name T627
Test name
Test status
Simulation time 8473702136 ps
CPU time 7.53 seconds
Started Mar 26 02:52:58 PM PDT 24
Finished Mar 26 02:53:06 PM PDT 24
Peak memory 203456 kb
Host smart-48437428-79ff-4891-b1ad-ecd9cfe42bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35442
0957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.354420957
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.635125120
Short name T840
Test name
Test status
Simulation time 8367587762 ps
CPU time 10.05 seconds
Started Mar 26 02:53:02 PM PDT 24
Finished Mar 26 02:53:12 PM PDT 24
Peak memory 203468 kb
Host smart-318066f3-1337-48a7-873c-f8fc248f2309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63512
5120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.635125120
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_enable.2642280109
Short name T692
Test name
Test status
Simulation time 8366754286 ps
CPU time 7.73 seconds
Started Mar 26 02:52:50 PM PDT 24
Finished Mar 26 02:52:58 PM PDT 24
Peak memory 203392 kb
Host smart-8dccfa3c-359a-4c80-b1d2-8dcf6de21bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26422
80109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.2642280109
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2018219904
Short name T314
Test name
Test status
Simulation time 72458167 ps
CPU time 1.88 seconds
Started Mar 26 02:52:40 PM PDT 24
Finished Mar 26 02:52:42 PM PDT 24
Peak memory 203576 kb
Host smart-05ba73de-d911-4358-990d-9ca008527dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20182
19904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2018219904
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.3978850198
Short name T719
Test name
Test status
Simulation time 8358775795 ps
CPU time 9.06 seconds
Started Mar 26 02:52:42 PM PDT 24
Finished Mar 26 02:52:51 PM PDT 24
Peak memory 203452 kb
Host smart-9cea58d6-1e2a-493f-817a-285550eb2121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39788
50198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.3978850198
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.275696967
Short name T776
Test name
Test status
Simulation time 8449653727 ps
CPU time 9.87 seconds
Started Mar 26 02:53:02 PM PDT 24
Finished Mar 26 02:53:12 PM PDT 24
Peak memory 203468 kb
Host smart-b58adfc3-35d7-4c8d-8d76-63575f6ddd45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27569
6967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.275696967
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.1945379038
Short name T417
Test name
Test status
Simulation time 8402469416 ps
CPU time 7.35 seconds
Started Mar 26 02:52:45 PM PDT 24
Finished Mar 26 02:52:53 PM PDT 24
Peak memory 203484 kb
Host smart-82af335b-bb76-4d38-b666-0de9e2fec108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19453
79038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.1945379038
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.1754157539
Short name T355
Test name
Test status
Simulation time 8369819792 ps
CPU time 8.87 seconds
Started Mar 26 02:52:36 PM PDT 24
Finished Mar 26 02:52:45 PM PDT 24
Peak memory 203504 kb
Host smart-8f7de678-d91d-4632-969f-597580a4e8a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17541
57539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.1754157539
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3745145223
Short name T111
Test name
Test status
Simulation time 8450669418 ps
CPU time 9.6 seconds
Started Mar 26 02:52:52 PM PDT 24
Finished Mar 26 02:53:01 PM PDT 24
Peak memory 203464 kb
Host smart-94aee5d7-aed5-41f3-9e2d-6fb3ad0ea5da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37451
45223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3745145223
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.4144130015
Short name T755
Test name
Test status
Simulation time 8375328722 ps
CPU time 7.18 seconds
Started Mar 26 02:52:45 PM PDT 24
Finished Mar 26 02:52:53 PM PDT 24
Peak memory 203488 kb
Host smart-46d82833-3ec4-4879-8dce-88651ba6dcb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41441
30015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.4144130015
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.2160520116
Short name T226
Test name
Test status
Simulation time 8372900756 ps
CPU time 9.09 seconds
Started Mar 26 02:52:59 PM PDT 24
Finished Mar 26 02:53:09 PM PDT 24
Peak memory 203516 kb
Host smart-d3237d6e-3ad2-4523-8d45-c5f6273a581e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21605
20116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.2160520116
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3857597110
Short name T514
Test name
Test status
Simulation time 26367202 ps
CPU time 0.65 seconds
Started Mar 26 02:52:40 PM PDT 24
Finished Mar 26 02:52:41 PM PDT 24
Peak memory 203360 kb
Host smart-801cfe27-1998-49c3-a990-30ea95c2ab58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38575
97110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3857597110
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.1591021047
Short name T578
Test name
Test status
Simulation time 8382481229 ps
CPU time 7.71 seconds
Started Mar 26 02:52:45 PM PDT 24
Finished Mar 26 02:52:53 PM PDT 24
Peak memory 203480 kb
Host smart-50b5df83-201a-43c4-8722-aa888abe2c0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15910
21047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.1591021047
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.64138730
Short name T878
Test name
Test status
Simulation time 8392158653 ps
CPU time 7.84 seconds
Started Mar 26 02:52:51 PM PDT 24
Finished Mar 26 02:52:59 PM PDT 24
Peak memory 203472 kb
Host smart-b2ba1529-d4f0-4157-9b08-a2483a4d06f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64138
730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.64138730
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.3011319890
Short name T298
Test name
Test status
Simulation time 8393262372 ps
CPU time 9.28 seconds
Started Mar 26 02:52:57 PM PDT 24
Finished Mar 26 02:53:07 PM PDT 24
Peak memory 203468 kb
Host smart-58d4446b-6737-4cf9-8e14-a4435d4b15e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30113
19890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.3011319890
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.4289117900
Short name T291
Test name
Test status
Simulation time 8358132417 ps
CPU time 6.86 seconds
Started Mar 26 02:52:53 PM PDT 24
Finished Mar 26 02:53:00 PM PDT 24
Peak memory 203504 kb
Host smart-7f0374c1-0fa4-490c-9008-a0c6c0758a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42891
17900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.4289117900
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.1119631796
Short name T557
Test name
Test status
Simulation time 8475490829 ps
CPU time 7.52 seconds
Started Mar 26 02:52:53 PM PDT 24
Finished Mar 26 02:53:02 PM PDT 24
Peak memory 203484 kb
Host smart-a7714c81-3b12-4475-8214-1693d19b898c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11196
31796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.1119631796
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.22660834
Short name T474
Test name
Test status
Simulation time 8366147831 ps
CPU time 8.16 seconds
Started Mar 26 02:52:41 PM PDT 24
Finished Mar 26 02:52:50 PM PDT 24
Peak memory 203412 kb
Host smart-225147b0-a1d7-44de-ab18-5fd32dc97d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22660
834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.22660834
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_enable.2307866353
Short name T649
Test name
Test status
Simulation time 8366371214 ps
CPU time 7.73 seconds
Started Mar 26 02:52:40 PM PDT 24
Finished Mar 26 02:52:48 PM PDT 24
Peak memory 203484 kb
Host smart-51c9dd28-92cf-4a3f-9a26-9f731accbbd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23078
66353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.2307866353
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.1802064787
Short name T445
Test name
Test status
Simulation time 133339777 ps
CPU time 1.31 seconds
Started Mar 26 02:52:47 PM PDT 24
Finished Mar 26 02:52:48 PM PDT 24
Peak memory 203572 kb
Host smart-95ccd1f7-8a95-4f0b-bb3b-0417237c3dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18020
64787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.1802064787
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.3596696830
Short name T487
Test name
Test status
Simulation time 8405361102 ps
CPU time 7.53 seconds
Started Mar 26 02:52:45 PM PDT 24
Finished Mar 26 02:52:52 PM PDT 24
Peak memory 203500 kb
Host smart-4cbfbb15-2042-4e64-aebd-5fbbd9c322ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35966
96830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.3596696830
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.1958328447
Short name T297
Test name
Test status
Simulation time 8362901770 ps
CPU time 7.76 seconds
Started Mar 26 02:52:54 PM PDT 24
Finished Mar 26 02:53:02 PM PDT 24
Peak memory 203484 kb
Host smart-aef5bc45-8d45-4bc5-90c2-9822b1b04456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19583
28447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1958328447
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.1840370027
Short name T762
Test name
Test status
Simulation time 8398933906 ps
CPU time 7.89 seconds
Started Mar 26 02:53:01 PM PDT 24
Finished Mar 26 02:53:09 PM PDT 24
Peak memory 203468 kb
Host smart-4f69364d-457d-49e9-9ab2-2e81657b8d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18403
70027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.1840370027
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.1946362734
Short name T684
Test name
Test status
Simulation time 8392141443 ps
CPU time 8.17 seconds
Started Mar 26 02:52:57 PM PDT 24
Finished Mar 26 02:53:06 PM PDT 24
Peak memory 203512 kb
Host smart-245ef452-a9d6-46c3-a2ee-ae557ad38272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19463
62734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.1946362734
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.749080125
Short name T653
Test name
Test status
Simulation time 25513083 ps
CPU time 0.61 seconds
Started Mar 26 02:52:52 PM PDT 24
Finished Mar 26 02:52:53 PM PDT 24
Peak memory 203388 kb
Host smart-14d6118f-f931-43fa-9867-6a9123b81c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74908
0125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.749080125
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.949338206
Short name T211
Test name
Test status
Simulation time 8398651126 ps
CPU time 8.38 seconds
Started Mar 26 02:52:59 PM PDT 24
Finished Mar 26 02:53:07 PM PDT 24
Peak memory 203468 kb
Host smart-545acf37-8240-41ad-ac8b-5ebb83129f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94933
8206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.949338206
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.1541215834
Short name T392
Test name
Test status
Simulation time 8453044948 ps
CPU time 8.1 seconds
Started Mar 26 02:52:52 PM PDT 24
Finished Mar 26 02:53:01 PM PDT 24
Peak memory 203480 kb
Host smart-296b2699-29b9-41f5-8191-9e240b166a58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15412
15834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.1541215834
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.444324026
Short name T353
Test name
Test status
Simulation time 8363214858 ps
CPU time 7.63 seconds
Started Mar 26 02:52:47 PM PDT 24
Finished Mar 26 02:52:55 PM PDT 24
Peak memory 203512 kb
Host smart-0c0b24c5-d165-44ed-9c16-ac9159b47e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44432
4026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.444324026
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.4225922315
Short name T635
Test name
Test status
Simulation time 8356238424 ps
CPU time 7.9 seconds
Started Mar 26 02:52:59 PM PDT 24
Finished Mar 26 02:53:07 PM PDT 24
Peak memory 203516 kb
Host smart-f2881fad-106b-4edb-93df-221520e4ed47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42259
22315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.4225922315
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.672700377
Short name T666
Test name
Test status
Simulation time 8371649588 ps
CPU time 8.35 seconds
Started Mar 26 02:52:53 PM PDT 24
Finished Mar 26 02:53:02 PM PDT 24
Peak memory 203452 kb
Host smart-fc950906-bb70-4513-82fb-a84310c1c5b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67270
0377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.672700377
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_enable.4038529495
Short name T758
Test name
Test status
Simulation time 8369634767 ps
CPU time 8.15 seconds
Started Mar 26 02:52:52 PM PDT 24
Finished Mar 26 02:53:00 PM PDT 24
Peak memory 203420 kb
Host smart-8e5a517b-e73e-49eb-8ee1-d60baf5cf40f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40385
29495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.4038529495
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.4280286058
Short name T617
Test name
Test status
Simulation time 79285698 ps
CPU time 1.17 seconds
Started Mar 26 02:53:00 PM PDT 24
Finished Mar 26 02:53:02 PM PDT 24
Peak memory 203460 kb
Host smart-08cf8548-49a7-4d3b-9776-e208575a75dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42802
86058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.4280286058
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.291740530
Short name T176
Test name
Test status
Simulation time 8362331676 ps
CPU time 7.57 seconds
Started Mar 26 02:52:56 PM PDT 24
Finished Mar 26 02:53:04 PM PDT 24
Peak memory 203488 kb
Host smart-207d8a14-9b79-464c-abc8-59e4b6aaa509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29174
0530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.291740530
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1496045771
Short name T134
Test name
Test status
Simulation time 8411713217 ps
CPU time 7.63 seconds
Started Mar 26 02:53:01 PM PDT 24
Finished Mar 26 02:53:09 PM PDT 24
Peak memory 203384 kb
Host smart-756330e8-e8c9-4d1a-8baf-985162f25800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14960
45771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1496045771
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.4273590672
Short name T693
Test name
Test status
Simulation time 8409787960 ps
CPU time 7.78 seconds
Started Mar 26 02:52:59 PM PDT 24
Finished Mar 26 02:53:08 PM PDT 24
Peak memory 203684 kb
Host smart-ff1cbe59-2b55-493a-a917-84c6d3800680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42735
90672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.4273590672
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.583663895
Short name T797
Test name
Test status
Simulation time 8367228482 ps
CPU time 6.94 seconds
Started Mar 26 02:52:53 PM PDT 24
Finished Mar 26 02:53:00 PM PDT 24
Peak memory 203488 kb
Host smart-1d9d22bc-3970-4eb5-90f4-f6509164bb52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58366
3895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.583663895
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.278333220
Short name T409
Test name
Test status
Simulation time 8406108147 ps
CPU time 7.52 seconds
Started Mar 26 02:53:09 PM PDT 24
Finished Mar 26 02:53:17 PM PDT 24
Peak memory 203472 kb
Host smart-3979916c-9030-4848-99a8-6b3cf7660428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27833
3220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.278333220
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.1350226760
Short name T395
Test name
Test status
Simulation time 8402766489 ps
CPU time 6.94 seconds
Started Mar 26 02:53:46 PM PDT 24
Finished Mar 26 02:53:53 PM PDT 24
Peak memory 203472 kb
Host smart-9afd89b9-1b9a-4008-afc4-62f72a19c7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13502
26760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.1350226760
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.642858625
Short name T632
Test name
Test status
Simulation time 8387315580 ps
CPU time 7.05 seconds
Started Mar 26 02:53:03 PM PDT 24
Finished Mar 26 02:53:10 PM PDT 24
Peak memory 203480 kb
Host smart-cf543db2-6990-46d4-b225-75ff5a03b9f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64285
8625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.642858625
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.1170407219
Short name T586
Test name
Test status
Simulation time 28157859 ps
CPU time 0.63 seconds
Started Mar 26 02:53:02 PM PDT 24
Finished Mar 26 02:53:03 PM PDT 24
Peak memory 203308 kb
Host smart-b46e7da3-385d-43c3-abe8-918c99d9bf2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11704
07219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.1170407219
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.889689439
Short name T325
Test name
Test status
Simulation time 8363529622 ps
CPU time 6.84 seconds
Started Mar 26 02:52:56 PM PDT 24
Finished Mar 26 02:53:03 PM PDT 24
Peak memory 203472 kb
Host smart-2593b2c1-35e9-4dca-bbc8-4d18226e814a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88968
9439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.889689439
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.2715822795
Short name T683
Test name
Test status
Simulation time 8376912192 ps
CPU time 7.93 seconds
Started Mar 26 02:53:07 PM PDT 24
Finished Mar 26 02:53:15 PM PDT 24
Peak memory 203332 kb
Host smart-7bb98912-05a3-4d64-b6a1-ece0a34f0255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27158
22795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2715822795
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.1112145963
Short name T783
Test name
Test status
Simulation time 8381745876 ps
CPU time 7.92 seconds
Started Mar 26 02:52:47 PM PDT 24
Finished Mar 26 02:52:56 PM PDT 24
Peak memory 203368 kb
Host smart-6ae7963d-fc14-4cda-8817-d49e29b807a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11121
45963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.1112145963
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.1520663630
Short name T549
Test name
Test status
Simulation time 8362627131 ps
CPU time 8.13 seconds
Started Mar 26 02:53:08 PM PDT 24
Finished Mar 26 02:53:16 PM PDT 24
Peak memory 203476 kb
Host smart-1637e05f-be90-459e-82b1-b752b0ab73d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15206
63630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.1520663630
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.998050442
Short name T80
Test name
Test status
Simulation time 8475318576 ps
CPU time 9.78 seconds
Started Mar 26 02:53:04 PM PDT 24
Finished Mar 26 02:53:14 PM PDT 24
Peak memory 203480 kb
Host smart-58320b2d-b106-469b-a362-cc977adc07ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99805
0442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.998050442
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.1349500298
Short name T735
Test name
Test status
Simulation time 8370678739 ps
CPU time 7.61 seconds
Started Mar 26 02:53:33 PM PDT 24
Finished Mar 26 02:53:41 PM PDT 24
Peak memory 203472 kb
Host smart-09090404-4a87-4b26-9171-52ff7a4caaff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13495
00298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.1349500298
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_enable.1775396483
Short name T828
Test name
Test status
Simulation time 8368802961 ps
CPU time 7.14 seconds
Started Mar 26 02:52:54 PM PDT 24
Finished Mar 26 02:53:01 PM PDT 24
Peak memory 203464 kb
Host smart-a709ac1b-137b-4f36-a41d-f7019c8b55a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17753
96483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.1775396483
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2055779979
Short name T677
Test name
Test status
Simulation time 208930406 ps
CPU time 1.82 seconds
Started Mar 26 02:53:09 PM PDT 24
Finished Mar 26 02:53:11 PM PDT 24
Peak memory 203424 kb
Host smart-03cfb787-fafe-422c-aac3-dcb3ad2ec9bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20557
79979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2055779979
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.930710707
Short name T575
Test name
Test status
Simulation time 8357596386 ps
CPU time 6.8 seconds
Started Mar 26 02:52:53 PM PDT 24
Finished Mar 26 02:53:00 PM PDT 24
Peak memory 203496 kb
Host smart-f4eff714-5496-439e-9693-3d9becc7e74d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93071
0707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.930710707
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.3906223739
Short name T535
Test name
Test status
Simulation time 8387240603 ps
CPU time 8.16 seconds
Started Mar 26 02:52:56 PM PDT 24
Finished Mar 26 02:53:05 PM PDT 24
Peak memory 203464 kb
Host smart-b59f9708-8350-49a5-9ebc-557c9b693176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39062
23739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3906223739
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.2137470788
Short name T340
Test name
Test status
Simulation time 8406637742 ps
CPU time 8.43 seconds
Started Mar 26 02:53:00 PM PDT 24
Finished Mar 26 02:53:09 PM PDT 24
Peak memory 203520 kb
Host smart-2cb21077-5276-400b-923a-3c2e09f71283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21374
70788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.2137470788
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.3165960044
Short name T393
Test name
Test status
Simulation time 8365638371 ps
CPU time 7.44 seconds
Started Mar 26 02:53:19 PM PDT 24
Finished Mar 26 02:53:27 PM PDT 24
Peak memory 203688 kb
Host smart-b6b15916-2767-44cc-a1a0-7e613b3bd74a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31659
60044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.3165960044
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1319485206
Short name T429
Test name
Test status
Simulation time 8374599571 ps
CPU time 7.45 seconds
Started Mar 26 02:52:57 PM PDT 24
Finished Mar 26 02:53:05 PM PDT 24
Peak memory 203472 kb
Host smart-d26c831b-c71e-40bd-9992-db4bbc32a85a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13194
85206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1319485206
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1505124634
Short name T554
Test name
Test status
Simulation time 8377764255 ps
CPU time 8.49 seconds
Started Mar 26 02:53:05 PM PDT 24
Finished Mar 26 02:53:14 PM PDT 24
Peak memory 203500 kb
Host smart-397af0eb-ccc9-404d-900b-e61881b4dcec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15051
24634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1505124634
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.1211405626
Short name T803
Test name
Test status
Simulation time 28959540 ps
CPU time 0.63 seconds
Started Mar 26 02:52:52 PM PDT 24
Finished Mar 26 02:52:53 PM PDT 24
Peak memory 203372 kb
Host smart-b981d803-677e-4775-a8b0-43025bc6f3a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12114
05626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.1211405626
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.1178950726
Short name T832
Test name
Test status
Simulation time 8372215472 ps
CPU time 8.08 seconds
Started Mar 26 02:53:01 PM PDT 24
Finished Mar 26 02:53:10 PM PDT 24
Peak memory 203476 kb
Host smart-bf5184d1-9baa-47eb-bef9-835bc74a8f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11789
50726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.1178950726
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.4268168622
Short name T22
Test name
Test status
Simulation time 8417241330 ps
CPU time 7.64 seconds
Started Mar 26 02:52:59 PM PDT 24
Finished Mar 26 02:53:07 PM PDT 24
Peak memory 203436 kb
Host smart-ed0586c7-08d5-40f7-9d48-9fb2052d6643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42681
68622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.4268168622
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.615604161
Short name T379
Test name
Test status
Simulation time 8389107600 ps
CPU time 7.52 seconds
Started Mar 26 02:52:45 PM PDT 24
Finished Mar 26 02:52:53 PM PDT 24
Peak memory 203476 kb
Host smart-ff346514-4fe4-4c1b-8eed-e1810275c876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61560
4161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.615604161
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.998933737
Short name T537
Test name
Test status
Simulation time 8359241405 ps
CPU time 7.54 seconds
Started Mar 26 02:52:51 PM PDT 24
Finished Mar 26 02:52:59 PM PDT 24
Peak memory 203484 kb
Host smart-ce50ab8f-a18d-4c0e-91aa-8c14a4dd60f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99893
3737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.998933737
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.3977597449
Short name T143
Test name
Test status
Simulation time 8471785542 ps
CPU time 8.77 seconds
Started Mar 26 02:53:02 PM PDT 24
Finished Mar 26 02:53:11 PM PDT 24
Peak memory 203500 kb
Host smart-ebaddc6a-0ff3-4ef4-b167-d96a43591b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39775
97449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.3977597449
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.672709983
Short name T438
Test name
Test status
Simulation time 8369358595 ps
CPU time 8.01 seconds
Started Mar 26 02:52:58 PM PDT 24
Finished Mar 26 02:53:06 PM PDT 24
Peak memory 203468 kb
Host smart-39ebe921-94f8-46e2-9bda-aafabb9c334d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67270
9983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.672709983
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_enable.220642038
Short name T456
Test name
Test status
Simulation time 8372632281 ps
CPU time 7.17 seconds
Started Mar 26 02:52:53 PM PDT 24
Finished Mar 26 02:53:01 PM PDT 24
Peak memory 203504 kb
Host smart-5d7f7840-d378-48f5-ac85-eeba1101b8c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22064
2038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.220642038
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.3388692355
Short name T382
Test name
Test status
Simulation time 72107244 ps
CPU time 1.14 seconds
Started Mar 26 02:53:18 PM PDT 24
Finished Mar 26 02:53:20 PM PDT 24
Peak memory 203540 kb
Host smart-b23bd363-d5fe-4f3c-b7bc-c8805417dea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33886
92355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.3388692355
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.3328427165
Short name T170
Test name
Test status
Simulation time 8357586233 ps
CPU time 7.57 seconds
Started Mar 26 02:53:00 PM PDT 24
Finished Mar 26 02:53:08 PM PDT 24
Peak memory 203464 kb
Host smart-cd607d93-75da-4fac-afe3-389b9dbea823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33284
27165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.3328427165
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.2947188450
Short name T460
Test name
Test status
Simulation time 8379858529 ps
CPU time 7.48 seconds
Started Mar 26 02:52:59 PM PDT 24
Finished Mar 26 02:53:07 PM PDT 24
Peak memory 203468 kb
Host smart-79323f33-e37e-4e0f-9266-f2f43776f37b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29471
88450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.2947188450
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1162023113
Short name T670
Test name
Test status
Simulation time 8407645702 ps
CPU time 7.34 seconds
Started Mar 26 02:53:00 PM PDT 24
Finished Mar 26 02:53:07 PM PDT 24
Peak memory 203480 kb
Host smart-d902c2e3-2d28-4664-9c94-684d8b4ecdab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11620
23113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1162023113
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.535020350
Short name T576
Test name
Test status
Simulation time 8361369828 ps
CPU time 7.23 seconds
Started Mar 26 02:52:58 PM PDT 24
Finished Mar 26 02:53:06 PM PDT 24
Peak memory 203512 kb
Host smart-5ef0052f-8c39-4b3b-a071-eb1c7a3f7856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53502
0350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.535020350
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.577926962
Short name T327
Test name
Test status
Simulation time 8397429635 ps
CPU time 7.93 seconds
Started Mar 26 02:52:51 PM PDT 24
Finished Mar 26 02:52:59 PM PDT 24
Peak memory 203444 kb
Host smart-e23b0b16-61f0-4b4c-bc18-35fad3c197a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57792
6962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.577926962
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2763901989
Short name T305
Test name
Test status
Simulation time 8380319809 ps
CPU time 7.81 seconds
Started Mar 26 02:53:04 PM PDT 24
Finished Mar 26 02:53:12 PM PDT 24
Peak memory 203484 kb
Host smart-85430701-b51b-47cd-8ae8-77c16acfbb7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27639
01989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2763901989
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.3916048740
Short name T35
Test name
Test status
Simulation time 22820524 ps
CPU time 0.63 seconds
Started Mar 26 02:52:58 PM PDT 24
Finished Mar 26 02:52:59 PM PDT 24
Peak memory 203380 kb
Host smart-e9679ef0-43c4-4743-881b-99db71ce6df8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39160
48740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.3916048740
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.2574748131
Short name T859
Test name
Test status
Simulation time 8379987755 ps
CPU time 8.73 seconds
Started Mar 26 02:53:02 PM PDT 24
Finished Mar 26 02:53:11 PM PDT 24
Peak memory 203468 kb
Host smart-d69623d0-b4aa-4125-8c55-b83bb5f67fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25747
48131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.2574748131
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.731887284
Short name T714
Test name
Test status
Simulation time 8386753583 ps
CPU time 8.37 seconds
Started Mar 26 02:53:02 PM PDT 24
Finished Mar 26 02:53:11 PM PDT 24
Peak memory 203420 kb
Host smart-5b92a3f9-0013-46b5-a253-2bba3eade1b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73188
7284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.731887284
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.3237093495
Short name T44
Test name
Test status
Simulation time 8391555862 ps
CPU time 7.12 seconds
Started Mar 26 02:52:59 PM PDT 24
Finished Mar 26 02:53:06 PM PDT 24
Peak memory 203508 kb
Host smart-f2c9734b-0023-4781-b7b8-fa4db2334313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32370
93495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.3237093495
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.1966114099
Short name T289
Test name
Test status
Simulation time 8358675632 ps
CPU time 7.94 seconds
Started Mar 26 02:53:07 PM PDT 24
Finished Mar 26 02:53:15 PM PDT 24
Peak memory 203472 kb
Host smart-fe31e01c-8a1d-46c6-8b1c-200a0cbee005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19661
14099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.1966114099
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.1322966425
Short name T538
Test name
Test status
Simulation time 8374608511 ps
CPU time 7.73 seconds
Started Mar 26 02:52:10 PM PDT 24
Finished Mar 26 02:52:23 PM PDT 24
Peak memory 203480 kb
Host smart-3e98c60b-dbee-4e64-a78c-06414cb3416f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13229
66425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.1322966425
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_enable.4263995918
Short name T547
Test name
Test status
Simulation time 8367122757 ps
CPU time 7.26 seconds
Started Mar 26 02:52:07 PM PDT 24
Finished Mar 26 02:52:15 PM PDT 24
Peak memory 203504 kb
Host smart-2a4cc3a3-e684-406c-ac7b-498e4968c6af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42639
95918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.4263995918
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.56302568
Short name T740
Test name
Test status
Simulation time 106537106 ps
CPU time 1.16 seconds
Started Mar 26 02:52:04 PM PDT 24
Finished Mar 26 02:52:06 PM PDT 24
Peak memory 203564 kb
Host smart-334a295d-9b9e-4d6c-a276-ee2a532700ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56302
568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.56302568
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.2900646906
Short name T835
Test name
Test status
Simulation time 8413382100 ps
CPU time 7.37 seconds
Started Mar 26 02:52:03 PM PDT 24
Finished Mar 26 02:52:11 PM PDT 24
Peak memory 203480 kb
Host smart-26d7c078-3a5c-41fe-885b-c7b495f723cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29006
46906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.2900646906
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.1055232921
Short name T552
Test name
Test status
Simulation time 8411866356 ps
CPU time 7.29 seconds
Started Mar 26 02:52:09 PM PDT 24
Finished Mar 26 02:52:17 PM PDT 24
Peak memory 203412 kb
Host smart-8c5fdc91-9e58-444a-9240-de3471e18b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10552
32921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.1055232921
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.489494274
Short name T760
Test name
Test status
Simulation time 8368525891 ps
CPU time 7.16 seconds
Started Mar 26 02:52:10 PM PDT 24
Finished Mar 26 02:52:18 PM PDT 24
Peak memory 203472 kb
Host smart-4acf7892-278d-4d04-9fb3-2ae2e3cfbad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48949
4274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.489494274
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.3031222249
Short name T100
Test name
Test status
Simulation time 8394490082 ps
CPU time 6.96 seconds
Started Mar 26 02:52:05 PM PDT 24
Finished Mar 26 02:52:12 PM PDT 24
Peak memory 203452 kb
Host smart-4d8590b7-2da0-48eb-8f98-c8944beb9f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30312
22249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.3031222249
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.3362738405
Short name T339
Test name
Test status
Simulation time 8406436248 ps
CPU time 8.33 seconds
Started Mar 26 02:52:05 PM PDT 24
Finished Mar 26 02:52:13 PM PDT 24
Peak memory 203456 kb
Host smart-83bfc936-ef1f-4e67-bcf3-13970b6e4585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33627
38405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3362738405
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2350368451
Short name T703
Test name
Test status
Simulation time 8366020121 ps
CPU time 7.92 seconds
Started Mar 26 02:52:05 PM PDT 24
Finished Mar 26 02:52:13 PM PDT 24
Peak memory 203484 kb
Host smart-380bf9e0-8768-4c46-b4dd-6819314025cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23503
68451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2350368451
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2841096878
Short name T508
Test name
Test status
Simulation time 27212230 ps
CPU time 0.63 seconds
Started Mar 26 02:52:08 PM PDT 24
Finished Mar 26 02:52:08 PM PDT 24
Peak memory 203356 kb
Host smart-bc8df49e-d287-444b-a7f2-09278a3834b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28410
96878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2841096878
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.2969292956
Short name T844
Test name
Test status
Simulation time 8380951081 ps
CPU time 8.23 seconds
Started Mar 26 02:52:11 PM PDT 24
Finished Mar 26 02:52:19 PM PDT 24
Peak memory 203472 kb
Host smart-2ca1a7b0-5e13-49e1-96bf-26ff7aa9ef4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29692
92956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.2969292956
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.2522901093
Short name T674
Test name
Test status
Simulation time 8450379214 ps
CPU time 7.18 seconds
Started Mar 26 02:52:12 PM PDT 24
Finished Mar 26 02:52:20 PM PDT 24
Peak memory 203468 kb
Host smart-fc96f9e7-bce8-4596-a832-df2e61c535f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25229
01093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2522901093
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.1032901816
Short name T47
Test name
Test status
Simulation time 8389212323 ps
CPU time 7.88 seconds
Started Mar 26 02:52:05 PM PDT 24
Finished Mar 26 02:52:13 PM PDT 24
Peak memory 203488 kb
Host smart-7f5d8856-abb6-4985-b784-74bbd97580f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10329
01816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.1032901816
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.2698130585
Short name T69
Test name
Test status
Simulation time 238887666 ps
CPU time 1.08 seconds
Started Mar 26 02:52:11 PM PDT 24
Finished Mar 26 02:52:12 PM PDT 24
Peak memory 220304 kb
Host smart-4751f900-c965-4d38-8005-761050bef731
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2698130585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2698130585
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3032043968
Short name T331
Test name
Test status
Simulation time 8359915516 ps
CPU time 7.91 seconds
Started Mar 26 02:52:07 PM PDT 24
Finished Mar 26 02:52:15 PM PDT 24
Peak memory 203508 kb
Host smart-fccf95a7-4308-42f7-ace0-c146edb1d565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30320
43968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3032043968
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.2825242559
Short name T115
Test name
Test status
Simulation time 8476744453 ps
CPU time 7.77 seconds
Started Mar 26 02:52:02 PM PDT 24
Finished Mar 26 02:52:10 PM PDT 24
Peak memory 203496 kb
Host smart-d27523de-87b5-4501-ab69-ad039fe2c225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28252
42559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.2825242559
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.1103341684
Short name T371
Test name
Test status
Simulation time 8369580399 ps
CPU time 8.49 seconds
Started Mar 26 02:53:00 PM PDT 24
Finished Mar 26 02:53:09 PM PDT 24
Peak memory 203452 kb
Host smart-34417ffa-0892-41dd-9369-8a318a05d35f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11033
41684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.1103341684
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_enable.206065063
Short name T520
Test name
Test status
Simulation time 8369211553 ps
CPU time 8.58 seconds
Started Mar 26 02:52:57 PM PDT 24
Finished Mar 26 02:53:05 PM PDT 24
Peak memory 203504 kb
Host smart-1e9381fb-2aea-47d3-8d29-925c5ba1c572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20606
5063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.206065063
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.2379524462
Short name T285
Test name
Test status
Simulation time 230489658 ps
CPU time 1.91 seconds
Started Mar 26 02:53:00 PM PDT 24
Finished Mar 26 02:53:03 PM PDT 24
Peak memory 203536 kb
Host smart-044399a9-5894-48fc-9f47-d96fab95be87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23795
24462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2379524462
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.171968499
Short name T791
Test name
Test status
Simulation time 8363659264 ps
CPU time 7.32 seconds
Started Mar 26 02:53:01 PM PDT 24
Finished Mar 26 02:53:08 PM PDT 24
Peak memory 203452 kb
Host smart-09a97c28-0736-4e3e-bcb1-df315cc63eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17196
8499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.171968499
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.3847105186
Short name T477
Test name
Test status
Simulation time 8385660639 ps
CPU time 9.18 seconds
Started Mar 26 02:53:01 PM PDT 24
Finished Mar 26 02:53:11 PM PDT 24
Peak memory 203448 kb
Host smart-d905deb0-d082-4c90-a7be-15438b19c989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38471
05186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.3847105186
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1379466244
Short name T562
Test name
Test status
Simulation time 8410841086 ps
CPU time 7.86 seconds
Started Mar 26 02:53:08 PM PDT 24
Finished Mar 26 02:53:17 PM PDT 24
Peak memory 203428 kb
Host smart-1394961c-b0e8-4d58-9f85-b163d583293a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13794
66244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1379466244
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.4194028129
Short name T292
Test name
Test status
Simulation time 8368072011 ps
CPU time 8.93 seconds
Started Mar 26 02:53:03 PM PDT 24
Finished Mar 26 02:53:12 PM PDT 24
Peak memory 203484 kb
Host smart-bbbeb17a-1078-441e-9607-0746ed3ff0f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41940
28129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.4194028129
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.3570895703
Short name T612
Test name
Test status
Simulation time 8387695011 ps
CPU time 7.42 seconds
Started Mar 26 02:53:01 PM PDT 24
Finished Mar 26 02:53:09 PM PDT 24
Peak memory 203408 kb
Host smart-530dc146-da34-410f-8deb-ea7e43016713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35708
95703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.3570895703
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.1993644872
Short name T318
Test name
Test status
Simulation time 8367758865 ps
CPU time 9.03 seconds
Started Mar 26 02:53:00 PM PDT 24
Finished Mar 26 02:53:10 PM PDT 24
Peak memory 203484 kb
Host smart-24325ed5-82f0-4a71-9708-7bd8103a2d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19936
44872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.1993644872
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.474202571
Short name T737
Test name
Test status
Simulation time 8378092039 ps
CPU time 9.88 seconds
Started Mar 26 02:53:01 PM PDT 24
Finished Mar 26 02:53:11 PM PDT 24
Peak memory 203484 kb
Host smart-1250b97f-ee1b-4a8d-82de-a70b7bcf1c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47420
2571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.474202571
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.3834225180
Short name T595
Test name
Test status
Simulation time 8402738861 ps
CPU time 7.07 seconds
Started Mar 26 02:52:59 PM PDT 24
Finished Mar 26 02:53:06 PM PDT 24
Peak memory 203676 kb
Host smart-33a1d1c6-7034-470a-86eb-14fb7ee3c281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38342
25180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.3834225180
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.3716113150
Short name T271
Test name
Test status
Simulation time 8401053748 ps
CPU time 6.97 seconds
Started Mar 26 02:53:02 PM PDT 24
Finished Mar 26 02:53:09 PM PDT 24
Peak memory 203404 kb
Host smart-d247d67b-656c-46e3-95d9-e7c4844b9a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37161
13150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.3716113150
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.2077229240
Short name T341
Test name
Test status
Simulation time 8362801854 ps
CPU time 9.12 seconds
Started Mar 26 02:53:06 PM PDT 24
Finished Mar 26 02:53:16 PM PDT 24
Peak memory 203480 kb
Host smart-525ed3ab-7e91-4564-8b4f-f8b53b2dee1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20772
29240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.2077229240
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2908193409
Short name T808
Test name
Test status
Simulation time 8368828168 ps
CPU time 7.09 seconds
Started Mar 26 02:53:03 PM PDT 24
Finished Mar 26 02:53:10 PM PDT 24
Peak memory 203444 kb
Host smart-3dae7c27-35df-457e-bd80-a9071c01efb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29081
93409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2908193409
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_enable.3038500273
Short name T689
Test name
Test status
Simulation time 8366562949 ps
CPU time 9.24 seconds
Started Mar 26 02:53:01 PM PDT 24
Finished Mar 26 02:53:11 PM PDT 24
Peak memory 203484 kb
Host smart-5762c722-ff3b-4a61-b701-80fa8eb6e306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30385
00273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.3038500273
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.2139664633
Short name T286
Test name
Test status
Simulation time 57589739 ps
CPU time 1.66 seconds
Started Mar 26 02:53:06 PM PDT 24
Finished Mar 26 02:53:07 PM PDT 24
Peak memory 203356 kb
Host smart-5b45b256-6236-4f7b-a20d-ea0bd2989a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21396
64633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.2139664633
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.2767585554
Short name T154
Test name
Test status
Simulation time 8361983936 ps
CPU time 7.21 seconds
Started Mar 26 02:53:02 PM PDT 24
Finished Mar 26 02:53:10 PM PDT 24
Peak memory 203484 kb
Host smart-77d82655-ef23-4043-adb0-e2659931f0f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27675
85554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.2767585554
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.3786273402
Short name T626
Test name
Test status
Simulation time 8448488379 ps
CPU time 9.29 seconds
Started Mar 26 02:53:10 PM PDT 24
Finished Mar 26 02:53:19 PM PDT 24
Peak memory 203476 kb
Host smart-af67c8d1-00db-4d74-8f64-b85374e965af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37862
73402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.3786273402
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.1901946131
Short name T206
Test name
Test status
Simulation time 8412343483 ps
CPU time 8.15 seconds
Started Mar 26 02:53:04 PM PDT 24
Finished Mar 26 02:53:13 PM PDT 24
Peak memory 203508 kb
Host smart-a9c134c9-f084-4d2e-9019-1e772fbde438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19019
46131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.1901946131
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.616359138
Short name T581
Test name
Test status
Simulation time 8361849350 ps
CPU time 8.61 seconds
Started Mar 26 02:53:07 PM PDT 24
Finished Mar 26 02:53:15 PM PDT 24
Peak memory 203500 kb
Host smart-f0093171-5ba6-40fc-880f-e3a017ef1a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61635
9138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.616359138
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1848034298
Short name T688
Test name
Test status
Simulation time 8421460144 ps
CPU time 7.33 seconds
Started Mar 26 02:53:02 PM PDT 24
Finished Mar 26 02:53:10 PM PDT 24
Peak memory 203488 kb
Host smart-d41eefa5-8230-479f-ad4a-82d608574477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18480
34298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1848034298
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.3991867919
Short name T839
Test name
Test status
Simulation time 8397839333 ps
CPU time 7.46 seconds
Started Mar 26 02:53:03 PM PDT 24
Finished Mar 26 02:53:11 PM PDT 24
Peak memory 203452 kb
Host smart-91cad177-c354-4aae-b21b-30b34261edc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39918
67919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.3991867919
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.545232499
Short name T288
Test name
Test status
Simulation time 8407037977 ps
CPU time 7.14 seconds
Started Mar 26 02:53:03 PM PDT 24
Finished Mar 26 02:53:10 PM PDT 24
Peak memory 203504 kb
Host smart-1903dc7a-c76f-49db-be71-fcaf08aa253b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54523
2499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.545232499
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.1894267586
Short name T877
Test name
Test status
Simulation time 28279996 ps
CPU time 0.63 seconds
Started Mar 26 02:53:09 PM PDT 24
Finished Mar 26 02:53:10 PM PDT 24
Peak memory 203344 kb
Host smart-20495006-d08a-4d4f-9e0f-5de51c25c3d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18942
67586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.1894267586
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.849929759
Short name T49
Test name
Test status
Simulation time 8371625281 ps
CPU time 7.92 seconds
Started Mar 26 02:52:56 PM PDT 24
Finished Mar 26 02:53:04 PM PDT 24
Peak memory 203448 kb
Host smart-3524b6ee-22e9-4be7-bd71-a976572ee964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84992
9759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.849929759
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.3893425340
Short name T854
Test name
Test status
Simulation time 8409520907 ps
CPU time 7.58 seconds
Started Mar 26 02:53:04 PM PDT 24
Finished Mar 26 02:53:12 PM PDT 24
Peak memory 203440 kb
Host smart-d18624b7-cf75-4b19-97f6-a1b2b7a3179b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38934
25340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3893425340
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.762129660
Short name T284
Test name
Test status
Simulation time 8391675382 ps
CPU time 7.41 seconds
Started Mar 26 02:53:05 PM PDT 24
Finished Mar 26 02:53:13 PM PDT 24
Peak memory 203500 kb
Host smart-a6684c10-6ee3-4a87-9397-5cbf2d42ce03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76212
9660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.762129660
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1635843537
Short name T826
Test name
Test status
Simulation time 8357902723 ps
CPU time 8.95 seconds
Started Mar 26 02:53:07 PM PDT 24
Finished Mar 26 02:53:16 PM PDT 24
Peak memory 203496 kb
Host smart-1ed8b092-dce2-4dd2-96bd-4e8f11cb8037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16358
43537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1635843537
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.2572502406
Short name T139
Test name
Test status
Simulation time 8469628291 ps
CPU time 7.7 seconds
Started Mar 26 02:53:00 PM PDT 24
Finished Mar 26 02:53:08 PM PDT 24
Peak memory 203460 kb
Host smart-86bd9172-e3d8-4c3b-940d-757fc9c8a64b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25725
02406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.2572502406
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.2732083775
Short name T620
Test name
Test status
Simulation time 8371015870 ps
CPU time 7.85 seconds
Started Mar 26 02:53:03 PM PDT 24
Finished Mar 26 02:53:11 PM PDT 24
Peak memory 203492 kb
Host smart-e61e75c8-d327-4060-8b79-1f0783ad167e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27320
83775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.2732083775
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_enable.3145898729
Short name T507
Test name
Test status
Simulation time 8371321510 ps
CPU time 7.86 seconds
Started Mar 26 02:53:04 PM PDT 24
Finished Mar 26 02:53:12 PM PDT 24
Peak memory 203472 kb
Host smart-acf5c789-229d-4687-99f2-e11c698b8e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31458
98729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.3145898729
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.3494598426
Short name T697
Test name
Test status
Simulation time 138922469 ps
CPU time 1.38 seconds
Started Mar 26 02:53:06 PM PDT 24
Finished Mar 26 02:53:07 PM PDT 24
Peak memory 203568 kb
Host smart-a4c76f2b-3175-48ac-9022-e4a86a951013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34945
98426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.3494598426
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.604080472
Short name T114
Test name
Test status
Simulation time 8457416635 ps
CPU time 7.68 seconds
Started Mar 26 02:53:11 PM PDT 24
Finished Mar 26 02:53:19 PM PDT 24
Peak memory 203448 kb
Host smart-858b1e4e-65e6-4b2c-8d8c-3541d82cffb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60408
0472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.604080472
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.3145579891
Short name T673
Test name
Test status
Simulation time 8414082002 ps
CPU time 8.35 seconds
Started Mar 26 02:53:07 PM PDT 24
Finished Mar 26 02:53:15 PM PDT 24
Peak memory 203476 kb
Host smart-46937bc7-9fd4-4dc9-8449-2a50207ce28f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31455
79891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.3145579891
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3980626829
Short name T11
Test name
Test status
Simulation time 8363683820 ps
CPU time 7.47 seconds
Started Mar 26 02:53:07 PM PDT 24
Finished Mar 26 02:53:14 PM PDT 24
Peak memory 203484 kb
Host smart-ac161d05-8f41-49b6-94ae-7b1851cffe57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39806
26829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3980626829
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2440207071
Short name T580
Test name
Test status
Simulation time 8400912588 ps
CPU time 7.63 seconds
Started Mar 26 02:53:02 PM PDT 24
Finished Mar 26 02:53:10 PM PDT 24
Peak memory 203408 kb
Host smart-11918bc8-5ea1-443a-9cc4-5b04eeda19be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24402
07071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2440207071
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.3276234135
Short name T583
Test name
Test status
Simulation time 8374422799 ps
CPU time 9.17 seconds
Started Mar 26 02:53:04 PM PDT 24
Finished Mar 26 02:53:13 PM PDT 24
Peak memory 203496 kb
Host smart-3e06c946-7aaa-497c-8e9e-e6e32e622d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32762
34135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.3276234135
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.3649596057
Short name T559
Test name
Test status
Simulation time 31377810 ps
CPU time 0.66 seconds
Started Mar 26 02:53:07 PM PDT 24
Finished Mar 26 02:53:08 PM PDT 24
Peak memory 203356 kb
Host smart-8a329944-7e8b-4ade-a434-000fa44d5fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36495
96057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.3649596057
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.3617366329
Short name T723
Test name
Test status
Simulation time 8383624852 ps
CPU time 8.62 seconds
Started Mar 26 02:52:58 PM PDT 24
Finished Mar 26 02:53:07 PM PDT 24
Peak memory 203432 kb
Host smart-83ae13ed-a22b-48d2-a4ee-0a27f8153ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36173
66329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.3617366329
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.1056304617
Short name T479
Test name
Test status
Simulation time 8456525447 ps
CPU time 7.64 seconds
Started Mar 26 02:53:16 PM PDT 24
Finished Mar 26 02:53:24 PM PDT 24
Peak memory 203476 kb
Host smart-71733e11-b6ef-4d56-a827-6b724d1cfa3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10563
04617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1056304617
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.3460478162
Short name T637
Test name
Test status
Simulation time 8368291830 ps
CPU time 7.84 seconds
Started Mar 26 02:53:07 PM PDT 24
Finished Mar 26 02:53:15 PM PDT 24
Peak memory 203472 kb
Host smart-8b02791e-9325-4b36-948c-e1376aab3a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34604
78162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.3460478162
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1351858893
Short name T311
Test name
Test status
Simulation time 8357947938 ps
CPU time 9.45 seconds
Started Mar 26 02:53:06 PM PDT 24
Finished Mar 26 02:53:16 PM PDT 24
Peak memory 203476 kb
Host smart-5641a49d-188f-4fbc-9ed5-ba7ba3d86c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13518
58893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1351858893
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.804964549
Short name T870
Test name
Test status
Simulation time 8374600897 ps
CPU time 7.13 seconds
Started Mar 26 02:52:59 PM PDT 24
Finished Mar 26 02:53:07 PM PDT 24
Peak memory 203444 kb
Host smart-b33fd7ee-a4dd-404c-9b64-fd1b3df7adc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80496
4549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.804964549
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_enable.2126652714
Short name T430
Test name
Test status
Simulation time 8368244575 ps
CPU time 7.46 seconds
Started Mar 26 02:52:55 PM PDT 24
Finished Mar 26 02:53:03 PM PDT 24
Peak memory 203484 kb
Host smart-d597b18f-454c-4949-a1a9-041d71c3e8fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21266
52714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2126652714
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3718868533
Short name T397
Test name
Test status
Simulation time 37910119 ps
CPU time 0.96 seconds
Started Mar 26 02:53:00 PM PDT 24
Finished Mar 26 02:53:02 PM PDT 24
Peak memory 203596 kb
Host smart-6d18e897-9f0a-4014-8710-288279d439e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37188
68533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3718868533
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.2161196490
Short name T169
Test name
Test status
Simulation time 8357773779 ps
CPU time 7.42 seconds
Started Mar 26 02:53:09 PM PDT 24
Finished Mar 26 02:53:17 PM PDT 24
Peak memory 203452 kb
Host smart-dd65b5aa-7fb7-4ef6-92ee-dd8ff16b4171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21611
96490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.2161196490
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.3906231800
Short name T122
Test name
Test status
Simulation time 8389588068 ps
CPU time 10.03 seconds
Started Mar 26 02:53:02 PM PDT 24
Finished Mar 26 02:53:12 PM PDT 24
Peak memory 203484 kb
Host smart-5676e55c-bb10-4f5b-b1ff-0a1cded137d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39062
31800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.3906231800
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.2840020787
Short name T272
Test name
Test status
Simulation time 8413319841 ps
CPU time 7.6 seconds
Started Mar 26 02:53:00 PM PDT 24
Finished Mar 26 02:53:08 PM PDT 24
Peak memory 203508 kb
Host smart-f7dff203-d512-416d-8244-5f5f2e0509c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28400
20787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.2840020787
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.2334033355
Short name T335
Test name
Test status
Simulation time 8362615978 ps
CPU time 7.53 seconds
Started Mar 26 02:53:03 PM PDT 24
Finished Mar 26 02:53:11 PM PDT 24
Peak memory 203488 kb
Host smart-42734b64-ff4e-4580-a470-4f2087ffc9a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23340
33355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.2334033355
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.1531953804
Short name T366
Test name
Test status
Simulation time 8365217307 ps
CPU time 8.63 seconds
Started Mar 26 02:52:59 PM PDT 24
Finished Mar 26 02:53:08 PM PDT 24
Peak memory 203456 kb
Host smart-cf4c311b-0bbd-4d7a-982c-c223b3e62bc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15319
53804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.1531953804
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.3973574008
Short name T736
Test name
Test status
Simulation time 8406174135 ps
CPU time 7.37 seconds
Started Mar 26 02:53:03 PM PDT 24
Finished Mar 26 02:53:11 PM PDT 24
Peak memory 203472 kb
Host smart-0988aab0-f3ed-4fb8-9d5c-74b4ed31edc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39735
74008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.3973574008
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.3075845160
Short name T654
Test name
Test status
Simulation time 29731053 ps
CPU time 0.61 seconds
Started Mar 26 02:53:02 PM PDT 24
Finished Mar 26 02:53:03 PM PDT 24
Peak memory 203360 kb
Host smart-fb07f735-30bd-407b-b39a-8f5a37a077ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30758
45160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.3075845160
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.3207999310
Short name T375
Test name
Test status
Simulation time 8408134724 ps
CPU time 9.04 seconds
Started Mar 26 02:53:22 PM PDT 24
Finished Mar 26 02:53:31 PM PDT 24
Peak memory 203472 kb
Host smart-ec57c2b0-8ee3-4d1d-b9bb-7f532b7f5405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32079
99310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.3207999310
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.962873555
Short name T486
Test name
Test status
Simulation time 8414049511 ps
CPU time 7.49 seconds
Started Mar 26 02:53:10 PM PDT 24
Finished Mar 26 02:53:18 PM PDT 24
Peak memory 203484 kb
Host smart-9a3da63c-5c1a-4d4f-adae-707491ece4b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96287
3555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.962873555
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.3574110520
Short name T270
Test name
Test status
Simulation time 8389654941 ps
CPU time 7.32 seconds
Started Mar 26 02:53:03 PM PDT 24
Finished Mar 26 02:53:11 PM PDT 24
Peak memory 203484 kb
Host smart-0bfdebc6-6e52-460b-9ddb-f8a5ce65739c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35741
10520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.3574110520
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.640896477
Short name T850
Test name
Test status
Simulation time 8362234556 ps
CPU time 7.45 seconds
Started Mar 26 02:53:04 PM PDT 24
Finished Mar 26 02:53:12 PM PDT 24
Peak memory 203492 kb
Host smart-9f3e834c-4257-455c-8394-fcaa11eec4ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64089
6477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.640896477
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3483004385
Short name T144
Test name
Test status
Simulation time 8472662551 ps
CPU time 7.4 seconds
Started Mar 26 02:53:06 PM PDT 24
Finished Mar 26 02:53:13 PM PDT 24
Peak memory 203284 kb
Host smart-38e2698f-4272-4a93-8daf-f21185f0d5e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34830
04385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3483004385
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3558934115
Short name T338
Test name
Test status
Simulation time 8369505477 ps
CPU time 7.53 seconds
Started Mar 26 02:53:03 PM PDT 24
Finished Mar 26 02:53:11 PM PDT 24
Peak memory 203480 kb
Host smart-ac7e1b8c-54ef-443d-a42e-7eef36b39bda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35589
34115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3558934115
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_enable.3647690013
Short name T308
Test name
Test status
Simulation time 8373246315 ps
CPU time 7.79 seconds
Started Mar 26 02:53:02 PM PDT 24
Finished Mar 26 02:53:10 PM PDT 24
Peak memory 203476 kb
Host smart-445e63dc-ed3e-4b74-9f4d-600468f053dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36476
90013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.3647690013
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2374284304
Short name T219
Test name
Test status
Simulation time 70046422 ps
CPU time 1.2 seconds
Started Mar 26 02:53:01 PM PDT 24
Finished Mar 26 02:53:03 PM PDT 24
Peak memory 203428 kb
Host smart-ad12e8c1-235d-4573-b18a-f5848ec49855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23742
84304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2374284304
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.409112721
Short name T161
Test name
Test status
Simulation time 8359085977 ps
CPU time 7.55 seconds
Started Mar 26 02:53:04 PM PDT 24
Finished Mar 26 02:53:12 PM PDT 24
Peak memory 203440 kb
Host smart-01159f05-9615-4d2c-a6b6-70c5ccb6dbea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40911
2721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.409112721
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.4159107630
Short name T23
Test name
Test status
Simulation time 8409451950 ps
CPU time 7.64 seconds
Started Mar 26 02:53:11 PM PDT 24
Finished Mar 26 02:53:20 PM PDT 24
Peak memory 203476 kb
Host smart-f9701c77-f7a8-4d40-92dd-d797dffe6dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41591
07630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.4159107630
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2056159213
Short name T777
Test name
Test status
Simulation time 8406091879 ps
CPU time 9.71 seconds
Started Mar 26 02:53:03 PM PDT 24
Finished Mar 26 02:53:13 PM PDT 24
Peak memory 203400 kb
Host smart-1efb9e57-b018-480a-b83f-f4d65c0ff00d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20561
59213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2056159213
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.4278411633
Short name T875
Test name
Test status
Simulation time 8366171512 ps
CPU time 8.63 seconds
Started Mar 26 02:53:04 PM PDT 24
Finished Mar 26 02:53:13 PM PDT 24
Peak memory 203400 kb
Host smart-7b84b1a5-3ec5-48b5-aa18-0d85dbfa8690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42784
11633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.4278411633
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.2421229800
Short name T427
Test name
Test status
Simulation time 8399737339 ps
CPU time 7.37 seconds
Started Mar 26 02:53:08 PM PDT 24
Finished Mar 26 02:53:15 PM PDT 24
Peak memory 203464 kb
Host smart-c0391d31-0abf-48e3-936b-4a9799f15eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24212
29800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.2421229800
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2665542764
Short name T616
Test name
Test status
Simulation time 8392346702 ps
CPU time 7.12 seconds
Started Mar 26 02:53:03 PM PDT 24
Finished Mar 26 02:53:10 PM PDT 24
Peak memory 203488 kb
Host smart-68624be0-e41d-46e3-b32c-bce280d9457f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26655
42764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2665542764
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.4285679932
Short name T641
Test name
Test status
Simulation time 24435819 ps
CPU time 0.64 seconds
Started Mar 26 02:53:02 PM PDT 24
Finished Mar 26 02:53:03 PM PDT 24
Peak memory 203380 kb
Host smart-6bd302c8-be63-44dc-bcb8-7aaa53e461d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42856
79932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.4285679932
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.4117090180
Short name T661
Test name
Test status
Simulation time 8407503487 ps
CPU time 7.44 seconds
Started Mar 26 02:53:04 PM PDT 24
Finished Mar 26 02:53:11 PM PDT 24
Peak memory 203456 kb
Host smart-ec6eca48-8272-42f4-b72b-1fcfb7053275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41170
90180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.4117090180
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.1724452
Short name T679
Test name
Test status
Simulation time 8425763125 ps
CPU time 7.78 seconds
Started Mar 26 02:53:10 PM PDT 24
Finished Mar 26 02:53:18 PM PDT 24
Peak memory 203480 kb
Host smart-cccf61f8-e379-496d-8eb0-afcf2a127867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17244
52 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.1724452
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.2212233987
Short name T42
Test name
Test status
Simulation time 8367305521 ps
CPU time 7.52 seconds
Started Mar 26 02:53:08 PM PDT 24
Finished Mar 26 02:53:16 PM PDT 24
Peak memory 203468 kb
Host smart-653fb355-761f-47a0-958a-1dbe01bad772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22122
33987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.2212233987
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2579782856
Short name T518
Test name
Test status
Simulation time 8361948119 ps
CPU time 7.05 seconds
Started Mar 26 02:53:03 PM PDT 24
Finished Mar 26 02:53:10 PM PDT 24
Peak memory 203508 kb
Host smart-1e047d1e-fb85-4746-9dff-def07df4e533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25797
82856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2579782856
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.94924724
Short name T147
Test name
Test status
Simulation time 8475174750 ps
CPU time 8.45 seconds
Started Mar 26 02:53:08 PM PDT 24
Finished Mar 26 02:53:17 PM PDT 24
Peak memory 203476 kb
Host smart-3ea951a4-4bed-4c3d-8325-aaf2e6c011ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94924
724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.94924724
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.159920790
Short name T495
Test name
Test status
Simulation time 8375202526 ps
CPU time 7.12 seconds
Started Mar 26 02:53:16 PM PDT 24
Finished Mar 26 02:53:23 PM PDT 24
Peak memory 203336 kb
Host smart-93bf5fab-0475-437a-8958-f7736e1827e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15992
0790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.159920790
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_enable.2113107652
Short name T848
Test name
Test status
Simulation time 8364817869 ps
CPU time 7.1 seconds
Started Mar 26 02:53:07 PM PDT 24
Finished Mar 26 02:53:14 PM PDT 24
Peak memory 203464 kb
Host smart-025ceac9-8ed3-4589-951a-2ec22317a802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21131
07652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.2113107652
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1710441613
Short name T302
Test name
Test status
Simulation time 232592911 ps
CPU time 1.94 seconds
Started Mar 26 02:53:09 PM PDT 24
Finished Mar 26 02:53:11 PM PDT 24
Peak memory 203464 kb
Host smart-85b4c93f-73ce-4d19-968b-80e0d52795e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17104
41613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1710441613
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.292663123
Short name T342
Test name
Test status
Simulation time 8441525107 ps
CPU time 7.82 seconds
Started Mar 26 02:53:11 PM PDT 24
Finished Mar 26 02:53:18 PM PDT 24
Peak memory 203472 kb
Host smart-f8a670d1-a8fd-4e25-9909-89b2823ed022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29266
3123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.292663123
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.3645487455
Short name T800
Test name
Test status
Simulation time 8415310101 ps
CPU time 8.23 seconds
Started Mar 26 02:53:04 PM PDT 24
Finished Mar 26 02:53:13 PM PDT 24
Peak memory 203524 kb
Host smart-f6e44409-5f13-4faa-b193-bc76e93f9aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36454
87455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.3645487455
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.1543786661
Short name T541
Test name
Test status
Simulation time 8361028394 ps
CPU time 8.21 seconds
Started Mar 26 02:53:05 PM PDT 24
Finished Mar 26 02:53:13 PM PDT 24
Peak memory 203508 kb
Host smart-1ce7a2e5-3714-4f47-a845-8bcdd750b895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15437
86661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.1543786661
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.3556863052
Short name T90
Test name
Test status
Simulation time 8439326700 ps
CPU time 8.87 seconds
Started Mar 26 02:53:35 PM PDT 24
Finished Mar 26 02:53:44 PM PDT 24
Peak memory 203472 kb
Host smart-c50697ce-a1b2-45e8-92ed-2672eb90e0b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35568
63052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.3556863052
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.2286102056
Short name T20
Test name
Test status
Simulation time 8386856885 ps
CPU time 7.87 seconds
Started Mar 26 02:53:58 PM PDT 24
Finished Mar 26 02:54:06 PM PDT 24
Peak memory 203472 kb
Host smart-eb8fdde8-2a92-46f7-8912-e5217f95bcf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22861
02056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2286102056
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3853649057
Short name T73
Test name
Test status
Simulation time 8397729157 ps
CPU time 9.88 seconds
Started Mar 26 02:53:05 PM PDT 24
Finished Mar 26 02:53:15 PM PDT 24
Peak memory 203508 kb
Host smart-56aa7eeb-fbf6-49c9-aa47-3364bb3bec39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38536
49057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3853649057
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.1116549486
Short name T33
Test name
Test status
Simulation time 29405716 ps
CPU time 0.65 seconds
Started Mar 26 02:53:05 PM PDT 24
Finished Mar 26 02:53:06 PM PDT 24
Peak memory 203336 kb
Host smart-2f402cb5-42d3-4c17-a721-d8d1789453a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11165
49486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.1116549486
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.1117013328
Short name T530
Test name
Test status
Simulation time 8399603469 ps
CPU time 7.49 seconds
Started Mar 26 02:53:10 PM PDT 24
Finished Mar 26 02:53:23 PM PDT 24
Peak memory 203472 kb
Host smart-f3433c5c-42cc-4c77-9813-b4ca08c8d711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11170
13328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.1117013328
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.2146912610
Short name T527
Test name
Test status
Simulation time 8423109998 ps
CPU time 7.64 seconds
Started Mar 26 02:53:08 PM PDT 24
Finished Mar 26 02:53:16 PM PDT 24
Peak memory 203476 kb
Host smart-aee6da4d-ba38-4067-9c7f-fd20d09548b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21469
12610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.2146912610
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.1123466414
Short name T274
Test name
Test status
Simulation time 8385769987 ps
CPU time 6.8 seconds
Started Mar 26 02:53:19 PM PDT 24
Finished Mar 26 02:53:27 PM PDT 24
Peak memory 203484 kb
Host smart-e0423f1b-bcfe-4562-bd52-35191c60ac1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11234
66414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.1123466414
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.276607125
Short name T307
Test name
Test status
Simulation time 8362566782 ps
CPU time 9.5 seconds
Started Mar 26 02:53:07 PM PDT 24
Finished Mar 26 02:53:16 PM PDT 24
Peak memory 203508 kb
Host smart-d3dca086-4923-438f-a88d-175436d08745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27660
7125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.276607125
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2128684423
Short name T136
Test name
Test status
Simulation time 8471684218 ps
CPU time 7.82 seconds
Started Mar 26 02:53:07 PM PDT 24
Finished Mar 26 02:53:15 PM PDT 24
Peak memory 203508 kb
Host smart-5782d2ed-7e02-47fa-a045-fa41030267e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21286
84423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2128684423
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.16490045
Short name T650
Test name
Test status
Simulation time 8371557490 ps
CPU time 7.22 seconds
Started Mar 26 02:53:04 PM PDT 24
Finished Mar 26 02:53:11 PM PDT 24
Peak memory 203672 kb
Host smart-21f7ba4a-96e0-474c-af9a-08b5cd58b82a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16490
045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.16490045
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_enable.258808098
Short name T598
Test name
Test status
Simulation time 8377698376 ps
CPU time 6.74 seconds
Started Mar 26 02:53:13 PM PDT 24
Finished Mar 26 02:53:25 PM PDT 24
Peak memory 203472 kb
Host smart-bf669f55-a033-4e8c-8ca7-af739b3fae99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25880
8098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.258808098
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3101683634
Short name T117
Test name
Test status
Simulation time 8427904385 ps
CPU time 6.85 seconds
Started Mar 26 02:53:05 PM PDT 24
Finished Mar 26 02:53:12 PM PDT 24
Peak memory 203400 kb
Host smart-01219b61-8c2b-4ee5-8aaf-5d3f4990867d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31016
83634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3101683634
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.215718126
Short name T614
Test name
Test status
Simulation time 8410252053 ps
CPU time 7.32 seconds
Started Mar 26 02:53:30 PM PDT 24
Finished Mar 26 02:53:37 PM PDT 24
Peak memory 203448 kb
Host smart-cda624fa-941d-42d3-9b03-9153e7242d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21571
8126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.215718126
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.3990036283
Short name T408
Test name
Test status
Simulation time 8362046804 ps
CPU time 6.88 seconds
Started Mar 26 02:53:11 PM PDT 24
Finished Mar 26 02:53:18 PM PDT 24
Peak memory 203512 kb
Host smart-c0516841-f64b-4387-b7d1-7795aff4cace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39900
36283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.3990036283
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.492453803
Short name T110
Test name
Test status
Simulation time 8433431081 ps
CPU time 8.92 seconds
Started Mar 26 02:53:13 PM PDT 24
Finished Mar 26 02:53:22 PM PDT 24
Peak memory 203472 kb
Host smart-179ad445-92d8-4ea9-b76d-70fc596f0dd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49245
3803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.492453803
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.228869691
Short name T855
Test name
Test status
Simulation time 8370085698 ps
CPU time 7.6 seconds
Started Mar 26 02:53:34 PM PDT 24
Finished Mar 26 02:53:41 PM PDT 24
Peak memory 203492 kb
Host smart-2952ad30-8fc4-4be8-862e-a04dc7e614b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22886
9691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.228869691
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1600102087
Short name T555
Test name
Test status
Simulation time 8399627001 ps
CPU time 8.36 seconds
Started Mar 26 02:53:18 PM PDT 24
Finished Mar 26 02:53:26 PM PDT 24
Peak memory 203472 kb
Host smart-116684f8-bcf5-4ffe-8799-1b6dcb3f0cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16001
02087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1600102087
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3164167064
Short name T482
Test name
Test status
Simulation time 30322422 ps
CPU time 0.63 seconds
Started Mar 26 02:53:56 PM PDT 24
Finished Mar 26 02:53:57 PM PDT 24
Peak memory 203288 kb
Host smart-b2c96725-7a6d-46e9-9cfd-75a9e588d348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31641
67064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3164167064
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.2400982721
Short name T825
Test name
Test status
Simulation time 8388065512 ps
CPU time 7 seconds
Started Mar 26 02:53:05 PM PDT 24
Finished Mar 26 02:53:12 PM PDT 24
Peak memory 203472 kb
Host smart-3467003b-e522-428d-917b-b6f1a7ff1bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24009
82721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.2400982721
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.4037530477
Short name T882
Test name
Test status
Simulation time 8376015160 ps
CPU time 8.53 seconds
Started Mar 26 02:53:10 PM PDT 24
Finished Mar 26 02:53:19 PM PDT 24
Peak memory 203468 kb
Host smart-5383c3d6-908a-4b18-985a-de2a7ae9a9f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40375
30477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.4037530477
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.4232151776
Short name T685
Test name
Test status
Simulation time 8367699588 ps
CPU time 7.38 seconds
Started Mar 26 02:53:07 PM PDT 24
Finished Mar 26 02:53:15 PM PDT 24
Peak memory 203336 kb
Host smart-8d6d9114-66a1-42a8-82d7-a548d3fd8eab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42321
51776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.4232151776
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.742699090
Short name T708
Test name
Test status
Simulation time 8360588604 ps
CPU time 9.74 seconds
Started Mar 26 02:53:06 PM PDT 24
Finished Mar 26 02:53:16 PM PDT 24
Peak memory 203472 kb
Host smart-d64bd838-d6db-4a1c-8f97-9027e7475328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74269
9090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.742699090
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.3436951556
Short name T861
Test name
Test status
Simulation time 8475892963 ps
CPU time 7.31 seconds
Started Mar 26 02:53:13 PM PDT 24
Finished Mar 26 02:53:20 PM PDT 24
Peak memory 203508 kb
Host smart-763d0ca9-6638-475b-a997-2357d29f3a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34369
51556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.3436951556
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.205973552
Short name T426
Test name
Test status
Simulation time 8368748658 ps
CPU time 7.9 seconds
Started Mar 26 02:53:55 PM PDT 24
Finished Mar 26 02:54:03 PM PDT 24
Peak memory 203472 kb
Host smart-fb97c803-2392-4cc7-bd45-d5ff90303963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20597
3552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.205973552
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_enable.4011208829
Short name T209
Test name
Test status
Simulation time 8368995701 ps
CPU time 8.22 seconds
Started Mar 26 02:53:20 PM PDT 24
Finished Mar 26 02:53:28 PM PDT 24
Peak memory 203464 kb
Host smart-0cbc820d-0f12-42f5-b090-cffec337d34b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40112
08829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.4011208829
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.1912876723
Short name T657
Test name
Test status
Simulation time 47242225 ps
CPU time 1.22 seconds
Started Mar 26 02:53:10 PM PDT 24
Finished Mar 26 02:53:12 PM PDT 24
Peak memory 203536 kb
Host smart-4cf2d259-8cf6-42f5-a84e-4ee270954751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19128
76723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.1912876723
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.1449069792
Short name T167
Test name
Test status
Simulation time 8359048305 ps
CPU time 7.03 seconds
Started Mar 26 02:53:10 PM PDT 24
Finished Mar 26 02:53:17 PM PDT 24
Peak memory 203460 kb
Host smart-c72917f3-99ab-41ef-b650-d0abfde772ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14490
69792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.1449069792
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.2849159672
Short name T404
Test name
Test status
Simulation time 8436728422 ps
CPU time 7.07 seconds
Started Mar 26 02:53:02 PM PDT 24
Finished Mar 26 02:53:09 PM PDT 24
Peak memory 203472 kb
Host smart-c8141f50-a7e5-4bed-926c-4065eed4f0a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28491
59672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.2849159672
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.451585140
Short name T629
Test name
Test status
Simulation time 8413065484 ps
CPU time 7.22 seconds
Started Mar 26 02:53:06 PM PDT 24
Finished Mar 26 02:53:13 PM PDT 24
Peak memory 203480 kb
Host smart-c7ee53e7-20e9-43e4-81d8-adf16aeec8ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45158
5140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.451585140
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.2740857788
Short name T422
Test name
Test status
Simulation time 8362382011 ps
CPU time 7.52 seconds
Started Mar 26 02:53:26 PM PDT 24
Finished Mar 26 02:53:33 PM PDT 24
Peak memory 203488 kb
Host smart-5a4725d3-d4ee-4d7b-a651-4010b4f28674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27408
57788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.2740857788
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1171803233
Short name T30
Test name
Test status
Simulation time 8420860060 ps
CPU time 7.1 seconds
Started Mar 26 02:53:48 PM PDT 24
Finished Mar 26 02:53:56 PM PDT 24
Peak memory 203476 kb
Host smart-6a4be2c9-2271-4e0b-80e1-ce2ae3df14dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11718
03233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1171803233
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.1878177793
Short name T885
Test name
Test status
Simulation time 8399224281 ps
CPU time 6.97 seconds
Started Mar 26 02:53:09 PM PDT 24
Finished Mar 26 02:53:17 PM PDT 24
Peak memory 203456 kb
Host smart-80809623-f802-49a4-a4d8-4b9a66d20651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18781
77793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1878177793
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.1425508135
Short name T416
Test name
Test status
Simulation time 8378216897 ps
CPU time 8 seconds
Started Mar 26 02:53:20 PM PDT 24
Finished Mar 26 02:53:29 PM PDT 24
Peak memory 203496 kb
Host smart-a1c3101d-760c-4152-bbe9-36ab6b9b7043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14255
08135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.1425508135
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.3275445745
Short name T876
Test name
Test status
Simulation time 8380865706 ps
CPU time 8.9 seconds
Started Mar 26 02:53:50 PM PDT 24
Finished Mar 26 02:53:58 PM PDT 24
Peak memory 203468 kb
Host smart-a7788203-b63d-43af-8807-c213d71b3378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32754
45745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3275445745
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.2420099281
Short name T118
Test name
Test status
Simulation time 8398097064 ps
CPU time 7.05 seconds
Started Mar 26 02:53:10 PM PDT 24
Finished Mar 26 02:53:18 PM PDT 24
Peak memory 203444 kb
Host smart-774b1e6f-3446-4328-ab78-028ab64f1813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24200
99281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.2420099281
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.977610612
Short name T804
Test name
Test status
Simulation time 8408880823 ps
CPU time 7.54 seconds
Started Mar 26 02:53:20 PM PDT 24
Finished Mar 26 02:53:27 PM PDT 24
Peak memory 203480 kb
Host smart-3e2be331-f28f-48e7-9954-ccd4418139b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97761
0612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.977610612
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.3475491385
Short name T381
Test name
Test status
Simulation time 8358979399 ps
CPU time 7.38 seconds
Started Mar 26 02:53:07 PM PDT 24
Finished Mar 26 02:53:14 PM PDT 24
Peak memory 203476 kb
Host smart-764ef245-cfdc-4e98-9d27-75c391035f83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34754
91385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.3475491385
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2215767622
Short name T717
Test name
Test status
Simulation time 8470761656 ps
CPU time 7.59 seconds
Started Mar 26 02:53:32 PM PDT 24
Finished Mar 26 02:53:40 PM PDT 24
Peak memory 203404 kb
Host smart-bbab6d66-5ac9-4743-9725-e43bdcf1c712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22157
67622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2215767622
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.2885421220
Short name T310
Test name
Test status
Simulation time 8367498447 ps
CPU time 7.71 seconds
Started Mar 26 02:53:56 PM PDT 24
Finished Mar 26 02:54:04 PM PDT 24
Peak memory 203476 kb
Host smart-ce5d811a-88fd-49ca-8d75-d1b76ef31da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28854
21220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.2885421220
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_enable.1454033699
Short name T407
Test name
Test status
Simulation time 8367154307 ps
CPU time 7.49 seconds
Started Mar 26 02:53:38 PM PDT 24
Finished Mar 26 02:53:46 PM PDT 24
Peak memory 203444 kb
Host smart-98d78c96-4219-4b6b-b583-dbe7755e77c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14540
33699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.1454033699
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.2225982072
Short name T494
Test name
Test status
Simulation time 98198287 ps
CPU time 1.31 seconds
Started Mar 26 02:53:15 PM PDT 24
Finished Mar 26 02:53:16 PM PDT 24
Peak memory 203544 kb
Host smart-0cbaab43-cdf6-4b72-9ecd-caa22d329b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22259
82072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2225982072
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.200439820
Short name T738
Test name
Test status
Simulation time 8410057755 ps
CPU time 7.76 seconds
Started Mar 26 02:53:55 PM PDT 24
Finished Mar 26 02:54:03 PM PDT 24
Peak memory 203676 kb
Host smart-3f8ffbd8-565c-42fc-a1b2-0122f61f6d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20043
9820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.200439820
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.2435525659
Short name T782
Test name
Test status
Simulation time 8404125584 ps
CPU time 7.27 seconds
Started Mar 26 02:53:51 PM PDT 24
Finished Mar 26 02:53:58 PM PDT 24
Peak memory 203408 kb
Host smart-fcb079e5-a472-4d44-aae2-f05c3636d1dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24355
25659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.2435525659
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.25185827
Short name T560
Test name
Test status
Simulation time 8359628706 ps
CPU time 7.07 seconds
Started Mar 26 02:53:17 PM PDT 24
Finished Mar 26 02:53:24 PM PDT 24
Peak memory 203480 kb
Host smart-bb1bd872-3d08-4e00-b885-7c3ccd118d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25185
827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.25185827
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.363021008
Short name T105
Test name
Test status
Simulation time 8421379011 ps
CPU time 9.85 seconds
Started Mar 26 02:53:39 PM PDT 24
Finished Mar 26 02:53:49 PM PDT 24
Peak memory 203480 kb
Host smart-4659e3d8-b443-4b81-8ecf-7faa96d16d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36302
1008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.363021008
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.478526107
Short name T500
Test name
Test status
Simulation time 8368746937 ps
CPU time 7.58 seconds
Started Mar 26 02:53:06 PM PDT 24
Finished Mar 26 02:53:14 PM PDT 24
Peak memory 203472 kb
Host smart-fea8f463-8f38-4983-8a50-be77af138e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47852
6107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.478526107
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.1337194983
Short name T447
Test name
Test status
Simulation time 8402155961 ps
CPU time 8.36 seconds
Started Mar 26 02:53:11 PM PDT 24
Finished Mar 26 02:53:19 PM PDT 24
Peak memory 203464 kb
Host smart-c2d45798-bec5-4d1d-af2d-325d9bd611b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13371
94983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.1337194983
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.3125870221
Short name T383
Test name
Test status
Simulation time 27688084 ps
CPU time 0.62 seconds
Started Mar 26 02:53:05 PM PDT 24
Finished Mar 26 02:53:06 PM PDT 24
Peak memory 203256 kb
Host smart-dbc7cb08-6aaa-4cd9-92ff-cd2edff1339c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31258
70221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.3125870221
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.3876051200
Short name T602
Test name
Test status
Simulation time 8371988885 ps
CPU time 7.7 seconds
Started Mar 26 02:53:06 PM PDT 24
Finished Mar 26 02:53:14 PM PDT 24
Peak memory 203472 kb
Host smart-3987b966-f757-4105-b7bf-186a1541f543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38760
51200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.3876051200
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.2044709129
Short name T391
Test name
Test status
Simulation time 8449767542 ps
CPU time 8.78 seconds
Started Mar 26 02:53:05 PM PDT 24
Finished Mar 26 02:53:14 PM PDT 24
Peak memory 203456 kb
Host smart-313db13e-370d-447b-8d7d-e51f4de3db62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20447
09129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2044709129
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.4278576439
Short name T351
Test name
Test status
Simulation time 8382510662 ps
CPU time 7.2 seconds
Started Mar 26 02:53:14 PM PDT 24
Finished Mar 26 02:53:22 PM PDT 24
Peak memory 203480 kb
Host smart-9882fbd3-749b-4d62-8360-65956dbadcff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42785
76439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.4278576439
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.575062531
Short name T821
Test name
Test status
Simulation time 8361887138 ps
CPU time 8.27 seconds
Started Mar 26 02:53:21 PM PDT 24
Finished Mar 26 02:53:30 PM PDT 24
Peak memory 203476 kb
Host smart-c1bcb2b4-3c4f-41ff-b738-5b89db184f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57506
2531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.575062531
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3586000698
Short name T771
Test name
Test status
Simulation time 8474125565 ps
CPU time 7.52 seconds
Started Mar 26 02:53:01 PM PDT 24
Finished Mar 26 02:53:09 PM PDT 24
Peak memory 203488 kb
Host smart-9561c62f-b3d8-40e3-b6cd-47ebf0816d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35860
00698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3586000698
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.1660562604
Short name T491
Test name
Test status
Simulation time 8373081826 ps
CPU time 8.75 seconds
Started Mar 26 02:53:10 PM PDT 24
Finished Mar 26 02:53:19 PM PDT 24
Peak memory 203436 kb
Host smart-339fc9b9-286c-46fa-8308-622b0cbd5df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16605
62604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1660562604
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_enable.2177350662
Short name T642
Test name
Test status
Simulation time 8367677042 ps
CPU time 8.69 seconds
Started Mar 26 02:53:16 PM PDT 24
Finished Mar 26 02:53:25 PM PDT 24
Peak memory 203488 kb
Host smart-83c0ea50-6232-476a-a961-e9ec13f22d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21773
50662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.2177350662
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.2333099750
Short name T568
Test name
Test status
Simulation time 65804847 ps
CPU time 1.81 seconds
Started Mar 26 02:53:09 PM PDT 24
Finished Mar 26 02:53:12 PM PDT 24
Peak memory 203568 kb
Host smart-dd795f68-6914-44d7-8c3d-15b0abb90853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23330
99750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.2333099750
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.140754852
Short name T668
Test name
Test status
Simulation time 8359216989 ps
CPU time 7.15 seconds
Started Mar 26 02:53:10 PM PDT 24
Finished Mar 26 02:53:17 PM PDT 24
Peak memory 203424 kb
Host smart-ae67fc9f-f547-4b9f-96be-7f653e815157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14075
4852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.140754852
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.2806056455
Short name T330
Test name
Test status
Simulation time 8428161795 ps
CPU time 7.63 seconds
Started Mar 26 02:53:15 PM PDT 24
Finished Mar 26 02:53:23 PM PDT 24
Peak memory 203476 kb
Host smart-f125af7c-5d09-4404-97a9-641712094a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28060
56455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.2806056455
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.3272135129
Short name T667
Test name
Test status
Simulation time 8404940417 ps
CPU time 9.46 seconds
Started Mar 26 02:53:12 PM PDT 24
Finished Mar 26 02:53:22 PM PDT 24
Peak memory 203516 kb
Host smart-0f71503b-75b0-41aa-b4f2-6aa0a0c6ca02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32721
35129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.3272135129
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.3292560610
Short name T402
Test name
Test status
Simulation time 8363336587 ps
CPU time 7.24 seconds
Started Mar 26 02:53:06 PM PDT 24
Finished Mar 26 02:53:14 PM PDT 24
Peak memory 203456 kb
Host smart-2d49159b-bf05-4ad7-a862-d6915cff491f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32925
60610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3292560610
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3217637160
Short name T112
Test name
Test status
Simulation time 8422900487 ps
CPU time 7.71 seconds
Started Mar 26 02:53:32 PM PDT 24
Finished Mar 26 02:53:40 PM PDT 24
Peak memory 203680 kb
Host smart-6c2dadf7-1e32-47ab-a790-400665965b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32176
37160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3217637160
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.2488151492
Short name T370
Test name
Test status
Simulation time 8384766553 ps
CPU time 7.21 seconds
Started Mar 26 02:53:23 PM PDT 24
Finished Mar 26 02:53:31 PM PDT 24
Peak memory 203472 kb
Host smart-4d331810-f9d2-418a-84b7-0eb34d550f5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24881
51492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2488151492
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.1589342369
Short name T817
Test name
Test status
Simulation time 8379498454 ps
CPU time 8.27 seconds
Started Mar 26 02:53:11 PM PDT 24
Finished Mar 26 02:53:19 PM PDT 24
Peak memory 203224 kb
Host smart-9e5b682a-0251-4a3e-a5c6-a025576b42ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15893
42369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.1589342369
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2568569255
Short name T829
Test name
Test status
Simulation time 31316763 ps
CPU time 0.65 seconds
Started Mar 26 02:53:43 PM PDT 24
Finished Mar 26 02:53:44 PM PDT 24
Peak memory 203292 kb
Host smart-76523226-a892-4737-9512-6ddad745c102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25685
69255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2568569255
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.2976147687
Short name T405
Test name
Test status
Simulation time 8404794080 ps
CPU time 8.57 seconds
Started Mar 26 02:53:22 PM PDT 24
Finished Mar 26 02:53:31 PM PDT 24
Peak memory 203476 kb
Host smart-bae0965e-037d-4158-a421-4353f95ede9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29761
47687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.2976147687
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.553362864
Short name T778
Test name
Test status
Simulation time 8432137281 ps
CPU time 9.7 seconds
Started Mar 26 02:53:12 PM PDT 24
Finished Mar 26 02:53:22 PM PDT 24
Peak memory 203456 kb
Host smart-264b3a89-6806-4d90-9cf8-2449125d5cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55336
2864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.553362864
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.1302089639
Short name T373
Test name
Test status
Simulation time 8394988250 ps
CPU time 7.19 seconds
Started Mar 26 02:53:35 PM PDT 24
Finished Mar 26 02:53:42 PM PDT 24
Peak memory 203468 kb
Host smart-2113ab7c-27b7-4aa3-8c3b-59b32f97687b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13020
89639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.1302089639
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2659208295
Short name T710
Test name
Test status
Simulation time 8357506057 ps
CPU time 6.98 seconds
Started Mar 26 02:53:15 PM PDT 24
Finished Mar 26 02:53:22 PM PDT 24
Peak memory 203372 kb
Host smart-b4151ee6-42d7-4016-8ee5-a8597d824edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26592
08295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2659208295
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1394563670
Short name T672
Test name
Test status
Simulation time 8468156977 ps
CPU time 7.81 seconds
Started Mar 26 02:53:25 PM PDT 24
Finished Mar 26 02:53:33 PM PDT 24
Peak memory 203400 kb
Host smart-50196c6b-1add-4a16-bc4b-07dc2a49bf65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13945
63670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1394563670
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1535019328
Short name T345
Test name
Test status
Simulation time 8372676819 ps
CPU time 7.05 seconds
Started Mar 26 02:52:10 PM PDT 24
Finished Mar 26 02:52:17 PM PDT 24
Peak memory 203448 kb
Host smart-7041e307-4a29-4191-a0ab-c054f515335e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15350
19328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1535019328
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_enable.980931458
Short name T521
Test name
Test status
Simulation time 8371395130 ps
CPU time 7.98 seconds
Started Mar 26 02:52:10 PM PDT 24
Finished Mar 26 02:52:18 PM PDT 24
Peak memory 203472 kb
Host smart-dcb04d06-ac73-4d94-b39f-93b43c3a72e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98093
1458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.980931458
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3283035353
Short name T41
Test name
Test status
Simulation time 226740037 ps
CPU time 1.94 seconds
Started Mar 26 02:52:15 PM PDT 24
Finished Mar 26 02:52:17 PM PDT 24
Peak memory 203528 kb
Host smart-afb7f72b-71ec-4ba3-9392-658eb114ad58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32830
35353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3283035353
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.2388434283
Short name T775
Test name
Test status
Simulation time 8363511611 ps
CPU time 6.84 seconds
Started Mar 26 02:52:06 PM PDT 24
Finished Mar 26 02:52:13 PM PDT 24
Peak memory 203448 kb
Host smart-9667e827-3485-4019-9fa3-0f8f0ffce72c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23884
34283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.2388434283
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.3081546403
Short name T312
Test name
Test status
Simulation time 8393392804 ps
CPU time 8.34 seconds
Started Mar 26 02:52:09 PM PDT 24
Finished Mar 26 02:52:18 PM PDT 24
Peak memory 203484 kb
Host smart-ec98a2d4-d3dd-45cc-a810-a5e6b879acf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30815
46403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.3081546403
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1037004549
Short name T384
Test name
Test status
Simulation time 8410413434 ps
CPU time 8.87 seconds
Started Mar 26 02:52:09 PM PDT 24
Finished Mar 26 02:52:18 PM PDT 24
Peak memory 203488 kb
Host smart-862e362a-aa3a-4516-acaf-9b9ccf6dbb8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10370
04549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1037004549
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.4241623648
Short name T389
Test name
Test status
Simulation time 8364856971 ps
CPU time 7.15 seconds
Started Mar 26 02:52:10 PM PDT 24
Finished Mar 26 02:52:17 PM PDT 24
Peak memory 203468 kb
Host smart-4b63a90a-b16a-45b4-aeaa-03add37d3ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42416
23648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.4241623648
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.3593211444
Short name T624
Test name
Test status
Simulation time 8436827152 ps
CPU time 7.88 seconds
Started Mar 26 02:52:11 PM PDT 24
Finished Mar 26 02:52:19 PM PDT 24
Peak memory 203436 kb
Host smart-c9a5d4db-2602-4f67-a852-64f1afa51067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35932
11444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.3593211444
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.904025947
Short name T722
Test name
Test status
Simulation time 8400101803 ps
CPU time 7.92 seconds
Started Mar 26 02:52:05 PM PDT 24
Finished Mar 26 02:52:13 PM PDT 24
Peak memory 203444 kb
Host smart-a3df174e-5647-47c8-972f-b9e4212312d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90402
5947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.904025947
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3037430168
Short name T357
Test name
Test status
Simulation time 8378295729 ps
CPU time 7.12 seconds
Started Mar 26 02:52:07 PM PDT 24
Finished Mar 26 02:52:14 PM PDT 24
Peak memory 203476 kb
Host smart-d47554dc-a0a0-4ecc-8dde-27cc0e5a38f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30374
30168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3037430168
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.392992199
Short name T36
Test name
Test status
Simulation time 30015870 ps
CPU time 0.63 seconds
Started Mar 26 02:52:08 PM PDT 24
Finished Mar 26 02:52:09 PM PDT 24
Peak memory 203356 kb
Host smart-ddc74567-010e-4826-8114-9a6e24e32eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39299
2199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.392992199
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.2112789933
Short name T603
Test name
Test status
Simulation time 8360608138 ps
CPU time 8.81 seconds
Started Mar 26 02:52:07 PM PDT 24
Finished Mar 26 02:52:16 PM PDT 24
Peak memory 203372 kb
Host smart-05eb053e-10d8-4e9b-b67e-7eb3be7f29fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21127
89933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.2112789933
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2635766082
Short name T765
Test name
Test status
Simulation time 8418707454 ps
CPU time 7.58 seconds
Started Mar 26 02:52:15 PM PDT 24
Finished Mar 26 02:52:22 PM PDT 24
Peak memory 203452 kb
Host smart-9cdaec9b-93e2-4856-8b04-99bdc6da7d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26357
66082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2635766082
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.1588861630
Short name T809
Test name
Test status
Simulation time 8405418894 ps
CPU time 7.84 seconds
Started Mar 26 02:52:08 PM PDT 24
Finished Mar 26 02:52:16 PM PDT 24
Peak memory 203488 kb
Host smart-82f5b748-ac93-40b8-b00b-8ea21b3e3777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15888
61630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.1588861630
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.3460400156
Short name T420
Test name
Test status
Simulation time 8359287133 ps
CPU time 8.79 seconds
Started Mar 26 02:52:15 PM PDT 24
Finished Mar 26 02:52:24 PM PDT 24
Peak memory 203404 kb
Host smart-2cd84ad5-e567-4125-8949-2bb7810a0543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34604
00156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.3460400156
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.4002533262
Short name T834
Test name
Test status
Simulation time 8479130072 ps
CPU time 7.91 seconds
Started Mar 26 02:52:06 PM PDT 24
Finished Mar 26 02:52:14 PM PDT 24
Peak memory 203480 kb
Host smart-02a498c2-5505-445f-acf7-1b16c6aa02ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40025
33262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.4002533262
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.4160927489
Short name T599
Test name
Test status
Simulation time 8369122356 ps
CPU time 7.35 seconds
Started Mar 26 02:53:25 PM PDT 24
Finished Mar 26 02:53:32 PM PDT 24
Peak memory 203416 kb
Host smart-b6939984-7cf6-41fd-a743-39a53e8b07be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41609
27489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.4160927489
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_enable.1164403672
Short name T442
Test name
Test status
Simulation time 8367704074 ps
CPU time 8.3 seconds
Started Mar 26 02:53:11 PM PDT 24
Finished Mar 26 02:53:20 PM PDT 24
Peak memory 203480 kb
Host smart-17cf12e7-b674-4298-8595-5471383cb4a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11644
03672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.1164403672
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.1502889103
Short name T601
Test name
Test status
Simulation time 133312790 ps
CPU time 1.27 seconds
Started Mar 26 02:53:12 PM PDT 24
Finished Mar 26 02:53:13 PM PDT 24
Peak memory 203544 kb
Host smart-9fab9ed2-ad58-4576-86ac-eb46876f21e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15028
89103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.1502889103
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.60749518
Short name T747
Test name
Test status
Simulation time 8359400588 ps
CPU time 7.54 seconds
Started Mar 26 02:53:19 PM PDT 24
Finished Mar 26 02:53:27 PM PDT 24
Peak memory 203468 kb
Host smart-d56d3fc7-87ff-4fc5-8c7e-f1dcbb476348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60749
518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.60749518
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.505855664
Short name T770
Test name
Test status
Simulation time 8413755890 ps
CPU time 6.97 seconds
Started Mar 26 02:53:16 PM PDT 24
Finished Mar 26 02:53:23 PM PDT 24
Peak memory 203452 kb
Host smart-cc69c1e5-9458-4607-89a2-356e1018b29c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50585
5664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.505855664
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.3456968778
Short name T467
Test name
Test status
Simulation time 8406505013 ps
CPU time 7.74 seconds
Started Mar 26 02:53:20 PM PDT 24
Finished Mar 26 02:53:28 PM PDT 24
Peak memory 203480 kb
Host smart-b153d92f-3c9d-4fed-93b0-f0cc991b1f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34569
68778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3456968778
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.4179235274
Short name T324
Test name
Test status
Simulation time 8362934064 ps
CPU time 8.49 seconds
Started Mar 26 02:53:10 PM PDT 24
Finished Mar 26 02:53:19 PM PDT 24
Peak memory 203476 kb
Host smart-af909efc-c9c0-4c46-a201-e578ac61542d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41792
35274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.4179235274
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.211456868
Short name T92
Test name
Test status
Simulation time 8401064991 ps
CPU time 9.31 seconds
Started Mar 26 02:53:28 PM PDT 24
Finished Mar 26 02:53:37 PM PDT 24
Peak memory 203472 kb
Host smart-6f823e47-216f-4bf5-a30a-71e5098dd8e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21145
6868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.211456868
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.3271700047
Short name T282
Test name
Test status
Simulation time 8382044864 ps
CPU time 7.67 seconds
Started Mar 26 02:53:22 PM PDT 24
Finished Mar 26 02:53:30 PM PDT 24
Peak memory 203432 kb
Host smart-db6a945e-b86f-4c12-8fac-46c23a7ba147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32717
00047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.3271700047
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.678819977
Short name T208
Test name
Test status
Simulation time 8368244123 ps
CPU time 9.7 seconds
Started Mar 26 02:53:20 PM PDT 24
Finished Mar 26 02:53:30 PM PDT 24
Peak memory 203448 kb
Host smart-b0ebc31d-c8a3-4c2e-81a6-6a4c3f31c5d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67881
9977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.678819977
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.3706832582
Short name T24
Test name
Test status
Simulation time 32867594 ps
CPU time 0.65 seconds
Started Mar 26 02:53:06 PM PDT 24
Finished Mar 26 02:53:07 PM PDT 24
Peak memory 203360 kb
Host smart-4518c6fb-c174-409b-af1d-d7beb2939925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37068
32582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.3706832582
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.3124430674
Short name T27
Test name
Test status
Simulation time 8373031172 ps
CPU time 7.19 seconds
Started Mar 26 02:53:15 PM PDT 24
Finished Mar 26 02:53:22 PM PDT 24
Peak memory 203476 kb
Host smart-404b41fc-2c1c-4f41-90c4-efb821ab1833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31244
30674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.3124430674
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.570342627
Short name T498
Test name
Test status
Simulation time 8397371138 ps
CPU time 9.27 seconds
Started Mar 26 02:53:16 PM PDT 24
Finished Mar 26 02:53:26 PM PDT 24
Peak memory 203468 kb
Host smart-91bd3c5a-bcb1-47ec-85f0-cc5519da64fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57034
2627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.570342627
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.1618382462
Short name T820
Test name
Test status
Simulation time 8390712000 ps
CPU time 9.56 seconds
Started Mar 26 02:53:22 PM PDT 24
Finished Mar 26 02:53:32 PM PDT 24
Peak memory 203456 kb
Host smart-60f1745f-0741-4c57-a024-786531f5b166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16183
82462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.1618382462
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.3611130345
Short name T744
Test name
Test status
Simulation time 8358037208 ps
CPU time 7.46 seconds
Started Mar 26 02:53:13 PM PDT 24
Finished Mar 26 02:53:20 PM PDT 24
Peak memory 203472 kb
Host smart-c11b4f36-3adb-46c9-b655-7184cc9af73c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36111
30345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.3611130345
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1318714782
Short name T418
Test name
Test status
Simulation time 8368623443 ps
CPU time 8.4 seconds
Started Mar 26 02:53:24 PM PDT 24
Finished Mar 26 02:53:32 PM PDT 24
Peak memory 203416 kb
Host smart-4c44216d-0cff-40b6-90ec-d2892539e7e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13187
14782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1318714782
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_enable.1009225120
Short name T216
Test name
Test status
Simulation time 8371080201 ps
CPU time 7.66 seconds
Started Mar 26 02:53:21 PM PDT 24
Finished Mar 26 02:53:29 PM PDT 24
Peak memory 203364 kb
Host smart-6ab8243f-fbc1-44bf-9930-d7a1fcfbec24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10092
25120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.1009225120
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.1471832698
Short name T213
Test name
Test status
Simulation time 106803136 ps
CPU time 1.37 seconds
Started Mar 26 02:53:15 PM PDT 24
Finished Mar 26 02:53:17 PM PDT 24
Peak memory 203428 kb
Host smart-c66923da-9b46-4dda-9c4b-2328ff417273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14718
32698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.1471832698
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.148748671
Short name T157
Test name
Test status
Simulation time 8363901646 ps
CPU time 9.76 seconds
Started Mar 26 02:53:30 PM PDT 24
Finished Mar 26 02:53:40 PM PDT 24
Peak memory 203408 kb
Host smart-8ea59a7b-9419-486e-bbd7-94adaf40a36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14874
8671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.148748671
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.1466064032
Short name T730
Test name
Test status
Simulation time 8435329274 ps
CPU time 9.29 seconds
Started Mar 26 02:53:10 PM PDT 24
Finished Mar 26 02:53:19 PM PDT 24
Peak memory 203460 kb
Host smart-b134b5f1-053c-4286-bb77-6c0bd3d4ea5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14660
64032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.1466064032
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.1316706998
Short name T280
Test name
Test status
Simulation time 8409905806 ps
CPU time 8.04 seconds
Started Mar 26 02:53:12 PM PDT 24
Finished Mar 26 02:53:21 PM PDT 24
Peak memory 203472 kb
Host smart-d3aa9a41-8d41-45f8-afb4-0a6855e9f9da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13167
06998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.1316706998
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1269962377
Short name T490
Test name
Test status
Simulation time 8367030717 ps
CPU time 7.44 seconds
Started Mar 26 02:53:17 PM PDT 24
Finished Mar 26 02:53:25 PM PDT 24
Peak memory 203448 kb
Host smart-fc472849-4816-4986-8710-ffe6505479b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12699
62377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1269962377
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2536819266
Short name T91
Test name
Test status
Simulation time 8421506137 ps
CPU time 8.06 seconds
Started Mar 26 02:53:37 PM PDT 24
Finished Mar 26 02:53:45 PM PDT 24
Peak memory 203492 kb
Host smart-7208eb17-a802-45a0-94fd-312340591700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25368
19266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2536819266
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.841214595
Short name T579
Test name
Test status
Simulation time 8401939720 ps
CPU time 6.86 seconds
Started Mar 26 02:53:19 PM PDT 24
Finished Mar 26 02:53:26 PM PDT 24
Peak memory 203468 kb
Host smart-e2aaec1c-3c16-41c4-b6b0-672d98882209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84121
4595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.841214595
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.3138968002
Short name T483
Test name
Test status
Simulation time 8406043787 ps
CPU time 7 seconds
Started Mar 26 02:53:10 PM PDT 24
Finished Mar 26 02:53:18 PM PDT 24
Peak memory 203484 kb
Host smart-a8c34ba2-abb2-43af-a5c2-a0a42ab9031a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31389
68002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.3138968002
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.1121764181
Short name T662
Test name
Test status
Simulation time 28572655 ps
CPU time 0.64 seconds
Started Mar 26 02:53:16 PM PDT 24
Finished Mar 26 02:53:17 PM PDT 24
Peak memory 203368 kb
Host smart-19df39c3-971d-4b63-af96-729df6fa0013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11217
64181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.1121764181
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.2123048307
Short name T221
Test name
Test status
Simulation time 8398180060 ps
CPU time 7.04 seconds
Started Mar 26 02:53:31 PM PDT 24
Finished Mar 26 02:53:38 PM PDT 24
Peak memory 203404 kb
Host smart-43bd8b47-f731-44d2-bb89-7c70677c710d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21230
48307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.2123048307
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.3640568534
Short name T496
Test name
Test status
Simulation time 8435872242 ps
CPU time 8.06 seconds
Started Mar 26 02:53:25 PM PDT 24
Finished Mar 26 02:53:33 PM PDT 24
Peak memory 203416 kb
Host smart-fb7407a4-0e41-436b-bb13-4c0bca5c07b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36405
68534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.3640568534
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.2693598025
Short name T369
Test name
Test status
Simulation time 8382160922 ps
CPU time 7.2 seconds
Started Mar 26 02:53:13 PM PDT 24
Finished Mar 26 02:53:20 PM PDT 24
Peak memory 203512 kb
Host smart-50837eae-d7e0-4a04-a918-ed4b5bdbfd4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26935
98025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.2693598025
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.2387650798
Short name T296
Test name
Test status
Simulation time 8355236543 ps
CPU time 8.34 seconds
Started Mar 26 02:53:17 PM PDT 24
Finished Mar 26 02:53:25 PM PDT 24
Peak memory 203464 kb
Host smart-17c8c735-b922-4ae3-90d0-a50aeef36dbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23876
50798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.2387650798
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.245815733
Short name T77
Test name
Test status
Simulation time 8474761327 ps
CPU time 7.72 seconds
Started Mar 26 02:53:11 PM PDT 24
Finished Mar 26 02:53:19 PM PDT 24
Peak memory 203172 kb
Host smart-ba408ce3-91e6-4397-ac0d-43656803f799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24581
5733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.245815733
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2470183270
Short name T309
Test name
Test status
Simulation time 8367540709 ps
CPU time 7.63 seconds
Started Mar 26 02:53:17 PM PDT 24
Finished Mar 26 02:53:25 PM PDT 24
Peak memory 203444 kb
Host smart-fecee91e-976e-4f95-b0c7-ffd6cf076800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24701
83270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2470183270
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_enable.2207202186
Short name T822
Test name
Test status
Simulation time 8370029766 ps
CPU time 8.91 seconds
Started Mar 26 02:53:37 PM PDT 24
Finished Mar 26 02:53:46 PM PDT 24
Peak memory 203468 kb
Host smart-6169138a-3825-4c5d-bfe3-476add0e7845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22072
02186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2207202186
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.4167126774
Short name T802
Test name
Test status
Simulation time 102099477 ps
CPU time 1.17 seconds
Started Mar 26 02:53:39 PM PDT 24
Finished Mar 26 02:53:40 PM PDT 24
Peak memory 203520 kb
Host smart-afc838ae-f210-449c-9960-66ea52291b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41671
26774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.4167126774
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.1007073155
Short name T152
Test name
Test status
Simulation time 8361458241 ps
CPU time 8.52 seconds
Started Mar 26 02:53:31 PM PDT 24
Finished Mar 26 02:53:40 PM PDT 24
Peak memory 203448 kb
Host smart-28a5a578-d077-4c43-a18c-6856bf45d215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10070
73155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1007073155
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.1105059159
Short name T652
Test name
Test status
Simulation time 8450586721 ps
CPU time 8.65 seconds
Started Mar 26 02:53:43 PM PDT 24
Finished Mar 26 02:53:52 PM PDT 24
Peak memory 203380 kb
Host smart-19c13a8d-28b1-47df-ba7a-3e00837a3821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11050
59159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.1105059159
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1071946226
Short name T748
Test name
Test status
Simulation time 8407615615 ps
CPU time 9.94 seconds
Started Mar 26 02:53:16 PM PDT 24
Finished Mar 26 02:53:26 PM PDT 24
Peak memory 203520 kb
Host smart-19df4988-0181-4024-828e-f335600cc297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10719
46226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1071946226
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.1368823620
Short name T567
Test name
Test status
Simulation time 8365205518 ps
CPU time 7.96 seconds
Started Mar 26 02:53:20 PM PDT 24
Finished Mar 26 02:53:28 PM PDT 24
Peak memory 203412 kb
Host smart-eaffe586-5f20-4d94-8109-65a5ae791de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13688
23620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.1368823620
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.2103688760
Short name T98
Test name
Test status
Simulation time 8416822769 ps
CPU time 7.48 seconds
Started Mar 26 02:53:17 PM PDT 24
Finished Mar 26 02:53:24 PM PDT 24
Peak memory 203468 kb
Host smart-8574b66c-6aea-42d7-8d7f-d3a020ac0a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21036
88760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2103688760
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1027233519
Short name T448
Test name
Test status
Simulation time 8384043640 ps
CPU time 7.28 seconds
Started Mar 26 02:53:14 PM PDT 24
Finished Mar 26 02:53:21 PM PDT 24
Peak memory 203428 kb
Host smart-57cd136b-7127-4367-819c-4dfe814b1940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10272
33519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1027233519
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.3579278532
Short name T40
Test name
Test status
Simulation time 8395819744 ps
CPU time 7.72 seconds
Started Mar 26 02:53:33 PM PDT 24
Finished Mar 26 02:53:41 PM PDT 24
Peak memory 203396 kb
Host smart-00e08000-c5b2-438e-acfc-cf2f05f38ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35792
78532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.3579278532
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.1493798019
Short name T669
Test name
Test status
Simulation time 25463261 ps
CPU time 0.63 seconds
Started Mar 26 02:53:23 PM PDT 24
Finished Mar 26 02:53:24 PM PDT 24
Peak memory 203248 kb
Host smart-554c818c-ba35-4345-8f8e-5b97654ada69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14937
98019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.1493798019
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.1428955445
Short name T561
Test name
Test status
Simulation time 8373692865 ps
CPU time 7.19 seconds
Started Mar 26 02:53:15 PM PDT 24
Finished Mar 26 02:53:23 PM PDT 24
Peak memory 203452 kb
Host smart-2e1e3065-eb3b-4a0d-b0c4-f787a15044a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14289
55445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.1428955445
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3132072223
Short name T374
Test name
Test status
Simulation time 8432262813 ps
CPU time 7.14 seconds
Started Mar 26 02:53:27 PM PDT 24
Finished Mar 26 02:53:34 PM PDT 24
Peak memory 203472 kb
Host smart-0a33aabb-15de-4d45-9f3a-b9de8b7e3cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31320
72223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3132072223
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.2195250456
Short name T785
Test name
Test status
Simulation time 8366629693 ps
CPU time 7.3 seconds
Started Mar 26 02:53:30 PM PDT 24
Finished Mar 26 02:53:38 PM PDT 24
Peak memory 203456 kb
Host smart-37b763db-65df-43ea-807b-e54e6b9c4929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21952
50456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.2195250456
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2279342700
Short name T385
Test name
Test status
Simulation time 8361423009 ps
CPU time 7.63 seconds
Started Mar 26 02:53:21 PM PDT 24
Finished Mar 26 02:53:30 PM PDT 24
Peak memory 203524 kb
Host smart-fdd992f1-1a5f-4dbe-aee8-989519414208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22793
42700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2279342700
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2628589377
Short name T125
Test name
Test status
Simulation time 8469762216 ps
CPU time 7.28 seconds
Started Mar 26 02:53:16 PM PDT 24
Finished Mar 26 02:53:24 PM PDT 24
Peak memory 203372 kb
Host smart-e3006edb-956c-4a78-808d-4981c295a732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26285
89377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2628589377
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.3081542571
Short name T321
Test name
Test status
Simulation time 8371863361 ps
CPU time 7.22 seconds
Started Mar 26 02:53:32 PM PDT 24
Finished Mar 26 02:53:39 PM PDT 24
Peak memory 203380 kb
Host smart-4f721a22-db66-4705-80e0-4ef4174ef11e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30815
42571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.3081542571
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_enable.1793340330
Short name T476
Test name
Test status
Simulation time 8373432561 ps
CPU time 8.22 seconds
Started Mar 26 02:53:34 PM PDT 24
Finished Mar 26 02:53:43 PM PDT 24
Peak memory 203464 kb
Host smart-5becb18c-db34-488c-8abe-9c8c1a5a7b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17933
40330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1793340330
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.3425859597
Short name T841
Test name
Test status
Simulation time 59940426 ps
CPU time 1.69 seconds
Started Mar 26 02:53:18 PM PDT 24
Finished Mar 26 02:53:20 PM PDT 24
Peak memory 203560 kb
Host smart-8821bd2a-3777-4592-8857-c1d3fa7bff5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34258
59597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3425859597
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.4294568401
Short name T159
Test name
Test status
Simulation time 8363337042 ps
CPU time 8.17 seconds
Started Mar 26 02:53:25 PM PDT 24
Finished Mar 26 02:53:33 PM PDT 24
Peak memory 203460 kb
Host smart-878d6dfd-c068-4b73-ae2d-25e775eb1e7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42945
68401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.4294568401
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.2824120263
Short name T745
Test name
Test status
Simulation time 8374806677 ps
CPU time 7.73 seconds
Started Mar 26 02:53:21 PM PDT 24
Finished Mar 26 02:53:29 PM PDT 24
Peak memory 203488 kb
Host smart-5a79af5a-155b-444d-854b-d7ad9f69527e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28241
20263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.2824120263
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.2802102837
Short name T862
Test name
Test status
Simulation time 8411673973 ps
CPU time 9.45 seconds
Started Mar 26 02:53:16 PM PDT 24
Finished Mar 26 02:53:26 PM PDT 24
Peak memory 203512 kb
Host smart-3617b6e0-0792-414b-bde0-47861bab7ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28021
02837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.2802102837
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.2684132152
Short name T573
Test name
Test status
Simulation time 8360920355 ps
CPU time 6.96 seconds
Started Mar 26 02:53:22 PM PDT 24
Finished Mar 26 02:53:30 PM PDT 24
Peak memory 203452 kb
Host smart-74ad5317-7e62-4e5c-aed5-9dbb5844ed8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26841
32152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.2684132152
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3993846927
Short name T94
Test name
Test status
Simulation time 8431709327 ps
CPU time 8.41 seconds
Started Mar 26 02:53:16 PM PDT 24
Finished Mar 26 02:53:25 PM PDT 24
Peak memory 203420 kb
Host smart-e224a628-bd4c-441a-bdab-2b8e4db1895c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39938
46927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3993846927
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.4077379196
Short name T676
Test name
Test status
Simulation time 8371281870 ps
CPU time 7.09 seconds
Started Mar 26 02:53:22 PM PDT 24
Finished Mar 26 02:53:29 PM PDT 24
Peak memory 203368 kb
Host smart-e9c066ad-c3a0-4116-859b-1b5d3f034677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40773
79196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.4077379196
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.3339378092
Short name T886
Test name
Test status
Simulation time 8398393021 ps
CPU time 7.5 seconds
Started Mar 26 02:53:14 PM PDT 24
Finished Mar 26 02:53:22 PM PDT 24
Peak memory 203384 kb
Host smart-687d7fd7-1373-4521-baf4-45a857f6773e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33393
78092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.3339378092
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1447200884
Short name T638
Test name
Test status
Simulation time 32364097 ps
CPU time 0.63 seconds
Started Mar 26 02:53:33 PM PDT 24
Finished Mar 26 02:53:33 PM PDT 24
Peak memory 203348 kb
Host smart-e0b27414-03d9-4e62-8d9b-5f35180ee27c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14472
00884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1447200884
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.1702662214
Short name T367
Test name
Test status
Simulation time 8383858373 ps
CPU time 7.32 seconds
Started Mar 26 02:53:16 PM PDT 24
Finished Mar 26 02:53:23 PM PDT 24
Peak memory 203472 kb
Host smart-8ecc823c-9ce8-4f35-8919-a4439973ae3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17026
62214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.1702662214
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.1973514845
Short name T464
Test name
Test status
Simulation time 8412190408 ps
CPU time 7.77 seconds
Started Mar 26 02:53:39 PM PDT 24
Finished Mar 26 02:53:47 PM PDT 24
Peak memory 203448 kb
Host smart-91007414-5713-481e-93a1-776e097c7e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19735
14845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.1973514845
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.4097332255
Short name T858
Test name
Test status
Simulation time 8383100266 ps
CPU time 9.29 seconds
Started Mar 26 02:53:47 PM PDT 24
Finished Mar 26 02:53:57 PM PDT 24
Peak memory 203488 kb
Host smart-ca12d1da-ad4a-4b84-a6be-739862670313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40973
32255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.4097332255
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.907428350
Short name T406
Test name
Test status
Simulation time 8357728161 ps
CPU time 7.67 seconds
Started Mar 26 02:53:30 PM PDT 24
Finished Mar 26 02:53:37 PM PDT 24
Peak memory 203484 kb
Host smart-9c3f03e6-275b-489e-a461-61aa8c90d89b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90742
8350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.907428350
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_enable.740018158
Short name T833
Test name
Test status
Simulation time 8368033005 ps
CPU time 9.17 seconds
Started Mar 26 02:53:50 PM PDT 24
Finished Mar 26 02:53:59 PM PDT 24
Peak memory 203456 kb
Host smart-f01b8385-7de5-436f-9167-bbf193777c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74001
8158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.740018158
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.1309110754
Short name T390
Test name
Test status
Simulation time 98623584 ps
CPU time 1.15 seconds
Started Mar 26 02:53:47 PM PDT 24
Finished Mar 26 02:53:48 PM PDT 24
Peak memory 203560 kb
Host smart-d2c750f8-dd4e-4c94-bb23-5e1993194788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13091
10754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.1309110754
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.3479335639
Short name T377
Test name
Test status
Simulation time 8365695402 ps
CPU time 7.28 seconds
Started Mar 26 02:53:39 PM PDT 24
Finished Mar 26 02:53:46 PM PDT 24
Peak memory 203488 kb
Host smart-84bd4852-a8b4-4078-8e86-54998e8aa3a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34793
35639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3479335639
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.4031278166
Short name T759
Test name
Test status
Simulation time 8441866398 ps
CPU time 7.36 seconds
Started Mar 26 02:53:45 PM PDT 24
Finished Mar 26 02:53:53 PM PDT 24
Peak memory 203468 kb
Host smart-2733e158-7629-4ae7-b650-bb101724feff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40312
78166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.4031278166
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.1386386179
Short name T359
Test name
Test status
Simulation time 8410520724 ps
CPU time 8.74 seconds
Started Mar 26 02:53:43 PM PDT 24
Finished Mar 26 02:53:52 PM PDT 24
Peak memory 203516 kb
Host smart-58ff7123-219f-43b7-8e8d-1391e91ee97d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13863
86179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.1386386179
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.1564940780
Short name T756
Test name
Test status
Simulation time 8363400482 ps
CPU time 9.01 seconds
Started Mar 26 02:53:36 PM PDT 24
Finished Mar 26 02:53:45 PM PDT 24
Peak memory 203460 kb
Host smart-36532179-e3cd-4bec-806e-97a68c25177c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15649
40780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.1564940780
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.245469296
Short name T790
Test name
Test status
Simulation time 8378250010 ps
CPU time 7.81 seconds
Started Mar 26 02:53:43 PM PDT 24
Finished Mar 26 02:53:51 PM PDT 24
Peak memory 203404 kb
Host smart-dba8b667-5978-4fce-89cf-29c240c3c56a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24546
9296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.245469296
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.3415293106
Short name T609
Test name
Test status
Simulation time 8381761776 ps
CPU time 9.57 seconds
Started Mar 26 02:53:39 PM PDT 24
Finished Mar 26 02:53:54 PM PDT 24
Peak memory 203440 kb
Host smart-16200a7d-bd26-4af4-ac32-ab9456d00347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34152
93106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.3415293106
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3814601543
Short name T656
Test name
Test status
Simulation time 27586569 ps
CPU time 0.65 seconds
Started Mar 26 02:53:40 PM PDT 24
Finished Mar 26 02:53:41 PM PDT 24
Peak memory 203356 kb
Host smart-d19c5454-1e35-4de1-983a-84fc31f70de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38146
01543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3814601543
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.2549015916
Short name T651
Test name
Test status
Simulation time 8388478526 ps
CPU time 8.57 seconds
Started Mar 26 02:53:37 PM PDT 24
Finished Mar 26 02:53:46 PM PDT 24
Peak memory 203492 kb
Host smart-fa602da3-f4b7-48f3-a7b2-43e8d0de1455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25490
15916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.2549015916
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.261232949
Short name T450
Test name
Test status
Simulation time 8385189987 ps
CPU time 7.71 seconds
Started Mar 26 02:53:53 PM PDT 24
Finished Mar 26 02:54:01 PM PDT 24
Peak memory 203440 kb
Host smart-cf82e0e4-6346-44aa-9302-492e9c9b0d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26123
2949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.261232949
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.2272669217
Short name T349
Test name
Test status
Simulation time 8393335588 ps
CPU time 7.61 seconds
Started Mar 26 02:53:41 PM PDT 24
Finished Mar 26 02:53:49 PM PDT 24
Peak memory 203496 kb
Host smart-edb39eea-2dc2-44d6-b09e-89e8805389d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22726
69217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.2272669217
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.670447083
Short name T789
Test name
Test status
Simulation time 8359737616 ps
CPU time 7.2 seconds
Started Mar 26 02:53:38 PM PDT 24
Finished Mar 26 02:53:45 PM PDT 24
Peak memory 203516 kb
Host smart-4e61dbac-e8e8-4950-a6dc-6db9c4f3bbf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67044
7083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.670447083
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1796508998
Short name T149
Test name
Test status
Simulation time 8482183108 ps
CPU time 8.36 seconds
Started Mar 26 02:53:34 PM PDT 24
Finished Mar 26 02:53:42 PM PDT 24
Peak memory 203496 kb
Host smart-ae591633-0871-4d44-9b2b-40a5418677ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17965
08998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1796508998
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.3222829197
Short name T415
Test name
Test status
Simulation time 8371631429 ps
CPU time 7.72 seconds
Started Mar 26 02:53:48 PM PDT 24
Finished Mar 26 02:53:56 PM PDT 24
Peak memory 203484 kb
Host smart-92ab2de0-de5d-4dc7-9c80-538e0b1dec4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32228
29197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.3222829197
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_enable.1132388620
Short name T441
Test name
Test status
Simulation time 8365812478 ps
CPU time 7.51 seconds
Started Mar 26 02:53:47 PM PDT 24
Finished Mar 26 02:53:54 PM PDT 24
Peak memory 203468 kb
Host smart-1e3db242-083f-4e81-8059-df327e6e6107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11323
88620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.1132388620
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.44019084
Short name T849
Test name
Test status
Simulation time 58592397 ps
CPU time 1.52 seconds
Started Mar 26 02:53:41 PM PDT 24
Finished Mar 26 02:53:43 PM PDT 24
Peak memory 203508 kb
Host smart-156349e1-45fb-4146-9a25-587901b5b38d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44019
084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.44019084
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.2866967358
Short name T168
Test name
Test status
Simulation time 8362572589 ps
CPU time 7.86 seconds
Started Mar 26 02:53:54 PM PDT 24
Finished Mar 26 02:54:02 PM PDT 24
Peak memory 203452 kb
Host smart-d402e38e-b9b1-4f80-aa63-5ee2bd67383e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28669
67358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.2866967358
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.2264804542
Short name T874
Test name
Test status
Simulation time 8380550537 ps
CPU time 9.3 seconds
Started Mar 26 02:53:49 PM PDT 24
Finished Mar 26 02:53:58 PM PDT 24
Peak memory 203404 kb
Host smart-1f44205f-557c-47d2-9316-f7ef5b2904cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22648
04542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2264804542
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.2464182767
Short name T634
Test name
Test status
Simulation time 8408923594 ps
CPU time 8.09 seconds
Started Mar 26 02:53:44 PM PDT 24
Finished Mar 26 02:53:52 PM PDT 24
Peak memory 203336 kb
Host smart-fb728812-9ddd-4406-a156-963c0b8bb5de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24641
82767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.2464182767
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2075013228
Short name T553
Test name
Test status
Simulation time 8361893085 ps
CPU time 8.41 seconds
Started Mar 26 02:53:49 PM PDT 24
Finished Mar 26 02:53:58 PM PDT 24
Peak memory 203488 kb
Host smart-3a8c4c9b-6975-43b2-a180-64ce22c8ce60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20750
13228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2075013228
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.3811090977
Short name T716
Test name
Test status
Simulation time 8414969626 ps
CPU time 9.15 seconds
Started Mar 26 02:53:51 PM PDT 24
Finished Mar 26 02:54:01 PM PDT 24
Peak memory 203472 kb
Host smart-b1466085-d4ad-4532-9ed5-bc4b6906d650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38110
90977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.3811090977
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.2751726506
Short name T556
Test name
Test status
Simulation time 8391554123 ps
CPU time 7.42 seconds
Started Mar 26 02:53:44 PM PDT 24
Finished Mar 26 02:53:52 PM PDT 24
Peak memory 203464 kb
Host smart-852d178c-7ed1-488c-b379-55c26b2e953d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27517
26506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.2751726506
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.796746970
Short name T347
Test name
Test status
Simulation time 8377877270 ps
CPU time 7.06 seconds
Started Mar 26 02:53:49 PM PDT 24
Finished Mar 26 02:53:56 PM PDT 24
Peak memory 203440 kb
Host smart-4e921b10-e692-4f83-9df6-28a7df1c0d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79674
6970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.796746970
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2067866841
Short name T458
Test name
Test status
Simulation time 24126795 ps
CPU time 0.68 seconds
Started Mar 26 02:53:44 PM PDT 24
Finished Mar 26 02:53:45 PM PDT 24
Peak memory 203356 kb
Host smart-ee097e4e-6fa6-4e32-835e-6359b23c7130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20678
66841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2067866841
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.3846141340
Short name T608
Test name
Test status
Simulation time 8391970608 ps
CPU time 9.89 seconds
Started Mar 26 02:53:51 PM PDT 24
Finished Mar 26 02:54:01 PM PDT 24
Peak memory 203476 kb
Host smart-45ef5572-ed4b-4c7b-b57a-c447c00eada3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38461
41340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.3846141340
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.4133029749
Short name T763
Test name
Test status
Simulation time 8436645674 ps
CPU time 7.49 seconds
Started Mar 26 02:53:47 PM PDT 24
Finished Mar 26 02:53:54 PM PDT 24
Peak memory 203460 kb
Host smart-89e4589a-f09b-44f6-b3da-8e19587369dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41330
29749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.4133029749
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.1896960916
Short name T589
Test name
Test status
Simulation time 8361906266 ps
CPU time 7.65 seconds
Started Mar 26 02:53:47 PM PDT 24
Finished Mar 26 02:53:55 PM PDT 24
Peak memory 203512 kb
Host smart-1d45b0f2-17ab-41ba-9dbe-bf67bfb105c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18969
60916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.1896960916
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.1439407467
Short name T610
Test name
Test status
Simulation time 8363125111 ps
CPU time 7.19 seconds
Started Mar 26 02:53:35 PM PDT 24
Finished Mar 26 02:53:42 PM PDT 24
Peak memory 203492 kb
Host smart-35c52dc4-73fb-40c6-a803-3612bd24a561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14394
07467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.1439407467
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.3368384631
Short name T128
Test name
Test status
Simulation time 8482418551 ps
CPU time 7.67 seconds
Started Mar 26 02:53:37 PM PDT 24
Finished Mar 26 02:53:45 PM PDT 24
Peak memory 203484 kb
Host smart-a11e40c1-f676-4fb7-a431-4f70ecdf62d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33683
84631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.3368384631
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.3228781425
Short name T741
Test name
Test status
Simulation time 8370319356 ps
CPU time 7.54 seconds
Started Mar 26 02:53:37 PM PDT 24
Finished Mar 26 02:53:45 PM PDT 24
Peak memory 203456 kb
Host smart-7fca656f-5e6a-40d0-88dd-f7336ba84cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32287
81425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.3228781425
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_enable.4182102310
Short name T276
Test name
Test status
Simulation time 8367502989 ps
CPU time 7.92 seconds
Started Mar 26 02:53:44 PM PDT 24
Finished Mar 26 02:53:52 PM PDT 24
Peak memory 203672 kb
Host smart-f0ce6591-7b45-47b6-ab63-1f476816cf50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41821
02310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.4182102310
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1797729447
Short name T459
Test name
Test status
Simulation time 124676108 ps
CPU time 1.25 seconds
Started Mar 26 02:53:44 PM PDT 24
Finished Mar 26 02:53:46 PM PDT 24
Peak memory 203548 kb
Host smart-cc487c44-20b6-4988-a88a-b45908d9d94e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17977
29447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1797729447
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.4146520626
Short name T162
Test name
Test status
Simulation time 8361140764 ps
CPU time 7.35 seconds
Started Mar 26 02:53:49 PM PDT 24
Finished Mar 26 02:53:56 PM PDT 24
Peak memory 203336 kb
Host smart-5867eb39-3488-4b5a-8465-6a2d0a3e562b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41465
20626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.4146520626
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.3875794499
Short name T74
Test name
Test status
Simulation time 8377619311 ps
CPU time 7.02 seconds
Started Mar 26 02:53:53 PM PDT 24
Finished Mar 26 02:54:00 PM PDT 24
Peak memory 203336 kb
Host smart-948bd15e-1d3e-4f18-ad0e-1b4e8d48ecf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38757
94499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.3875794499
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1211482239
Short name T43
Test name
Test status
Simulation time 8411188805 ps
CPU time 8.08 seconds
Started Mar 26 02:53:38 PM PDT 24
Finished Mar 26 02:53:47 PM PDT 24
Peak memory 203448 kb
Host smart-c91b3f67-3656-4d51-8b1c-e9aedb9b8142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12114
82239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1211482239
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.4249449889
Short name T831
Test name
Test status
Simulation time 8362085779 ps
CPU time 7.88 seconds
Started Mar 26 02:53:41 PM PDT 24
Finished Mar 26 02:53:49 PM PDT 24
Peak memory 203500 kb
Host smart-409f597b-4af5-44c7-83bc-a97c10bf000f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42494
49889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.4249449889
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.4279164526
Short name T107
Test name
Test status
Simulation time 8393484270 ps
CPU time 8.69 seconds
Started Mar 26 02:53:38 PM PDT 24
Finished Mar 26 02:53:46 PM PDT 24
Peak memory 203476 kb
Host smart-094e83e8-4c5a-41cc-9fea-4054edf2896a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42791
64526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.4279164526
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.445106707
Short name T434
Test name
Test status
Simulation time 8387703879 ps
CPU time 7.95 seconds
Started Mar 26 02:53:49 PM PDT 24
Finished Mar 26 02:53:57 PM PDT 24
Peak memory 203332 kb
Host smart-13366224-4f28-4fbd-ac8b-18619fceaaea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44510
6707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.445106707
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.2096801669
Short name T727
Test name
Test status
Simulation time 8388510006 ps
CPU time 8.07 seconds
Started Mar 26 02:53:41 PM PDT 24
Finished Mar 26 02:53:49 PM PDT 24
Peak memory 203516 kb
Host smart-b6cdf5b7-6815-4bfd-9a8c-14bd541e719d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20968
01669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.2096801669
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.3376907464
Short name T622
Test name
Test status
Simulation time 24279589 ps
CPU time 0.63 seconds
Started Mar 26 02:53:47 PM PDT 24
Finished Mar 26 02:53:47 PM PDT 24
Peak memory 203344 kb
Host smart-24c939a5-a6c4-4322-8ac0-8960ada5e00d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33769
07464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.3376907464
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.2377118117
Short name T871
Test name
Test status
Simulation time 8405916369 ps
CPU time 7.59 seconds
Started Mar 26 02:53:36 PM PDT 24
Finished Mar 26 02:53:44 PM PDT 24
Peak memory 203468 kb
Host smart-e9926520-c999-498c-995a-539241bcae8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23771
18117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.2377118117
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.590946090
Short name T346
Test name
Test status
Simulation time 8435930619 ps
CPU time 9.37 seconds
Started Mar 26 02:53:42 PM PDT 24
Finished Mar 26 02:53:51 PM PDT 24
Peak memory 203452 kb
Host smart-06e0e613-2115-443d-a160-77e788a3bf48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59094
6090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.590946090
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.2740067878
Short name T364
Test name
Test status
Simulation time 8370973149 ps
CPU time 6.99 seconds
Started Mar 26 02:54:02 PM PDT 24
Finished Mar 26 02:54:09 PM PDT 24
Peak memory 203464 kb
Host smart-ed1e555d-afa2-4fe3-b059-a8ab5028dfea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27400
67878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.2740067878
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1287007068
Short name T534
Test name
Test status
Simulation time 8358479741 ps
CPU time 7 seconds
Started Mar 26 02:53:48 PM PDT 24
Finished Mar 26 02:53:55 PM PDT 24
Peak memory 203484 kb
Host smart-2fb3e38e-f0d0-4cb0-811a-730007257673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12870
07068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1287007068
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.3744024878
Short name T142
Test name
Test status
Simulation time 8476131443 ps
CPU time 7.54 seconds
Started Mar 26 02:53:44 PM PDT 24
Finished Mar 26 02:53:52 PM PDT 24
Peak memory 203468 kb
Host smart-5c630402-0751-4026-923f-86f86599742f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37440
24878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.3744024878
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.4137187813
Short name T725
Test name
Test status
Simulation time 8373365843 ps
CPU time 8.81 seconds
Started Mar 26 02:53:44 PM PDT 24
Finished Mar 26 02:53:53 PM PDT 24
Peak memory 203480 kb
Host smart-9ebb2baa-d5e9-44bd-9f85-40d0d0ecb0c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41371
87813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.4137187813
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_enable.2220934007
Short name T525
Test name
Test status
Simulation time 8366811074 ps
CPU time 7.77 seconds
Started Mar 26 02:53:46 PM PDT 24
Finished Mar 26 02:53:53 PM PDT 24
Peak memory 203480 kb
Host smart-ad1fbde6-670a-4343-b8b4-de9190042705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22209
34007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.2220934007
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2434876501
Short name T220
Test name
Test status
Simulation time 142745221 ps
CPU time 1.66 seconds
Started Mar 26 02:53:51 PM PDT 24
Finished Mar 26 02:53:53 PM PDT 24
Peak memory 203544 kb
Host smart-d228ff54-9814-4425-b7e0-36cff22ced0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24348
76501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2434876501
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.1616498368
Short name T165
Test name
Test status
Simulation time 8358285316 ps
CPU time 7.33 seconds
Started Mar 26 02:53:53 PM PDT 24
Finished Mar 26 02:54:01 PM PDT 24
Peak memory 203352 kb
Host smart-c866fab0-5463-4ae3-abea-fc187cb417c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16164
98368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.1616498368
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.438326166
Short name T879
Test name
Test status
Simulation time 8406174423 ps
CPU time 7.45 seconds
Started Mar 26 02:53:54 PM PDT 24
Finished Mar 26 02:54:02 PM PDT 24
Peak memory 203484 kb
Host smart-67580a00-126d-40f5-9e2f-3f2dfce81ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43832
6166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.438326166
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.3006122075
Short name T823
Test name
Test status
Simulation time 8369670837 ps
CPU time 8.43 seconds
Started Mar 26 02:53:47 PM PDT 24
Finished Mar 26 02:53:56 PM PDT 24
Peak memory 203496 kb
Host smart-c09a2b54-3c45-45aa-94f3-06e80329d63e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30061
22075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.3006122075
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.1315768669
Short name T95
Test name
Test status
Simulation time 8409954326 ps
CPU time 7.25 seconds
Started Mar 26 02:53:58 PM PDT 24
Finished Mar 26 02:54:06 PM PDT 24
Peak memory 203452 kb
Host smart-0b9f69f7-a7ac-474b-aafd-800079b2f909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13157
68669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.1315768669
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.1722728370
Short name T475
Test name
Test status
Simulation time 8387386715 ps
CPU time 7.02 seconds
Started Mar 26 02:53:58 PM PDT 24
Finished Mar 26 02:54:05 PM PDT 24
Peak memory 203336 kb
Host smart-2a41bc3a-87d6-4232-871d-5ba31f4e0c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17227
28370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.1722728370
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.2083027034
Short name T509
Test name
Test status
Simulation time 8406930034 ps
CPU time 7.51 seconds
Started Mar 26 02:53:54 PM PDT 24
Finished Mar 26 02:54:02 PM PDT 24
Peak memory 203476 kb
Host smart-bcde2e95-3ffb-45a6-ac15-5e66919816e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20830
27034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2083027034
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.1022824029
Short name T435
Test name
Test status
Simulation time 25947741 ps
CPU time 0.63 seconds
Started Mar 26 02:53:59 PM PDT 24
Finished Mar 26 02:54:00 PM PDT 24
Peak memory 203336 kb
Host smart-05fa38c8-c12a-43e6-bd07-940c9e591074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10228
24029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.1022824029
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.1977522782
Short name T606
Test name
Test status
Simulation time 8401967631 ps
CPU time 8.83 seconds
Started Mar 26 02:53:44 PM PDT 24
Finished Mar 26 02:53:53 PM PDT 24
Peak memory 203472 kb
Host smart-13b14147-faea-4614-8904-c1019af83c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19775
22782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.1977522782
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.1779931284
Short name T439
Test name
Test status
Simulation time 8386025607 ps
CPU time 8.16 seconds
Started Mar 26 02:53:58 PM PDT 24
Finished Mar 26 02:54:06 PM PDT 24
Peak memory 203400 kb
Host smart-1c4a658c-29eb-4d03-b2d6-38e25189a88c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17799
31284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1779931284
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.222189969
Short name T591
Test name
Test status
Simulation time 8411120065 ps
CPU time 7.82 seconds
Started Mar 26 02:53:56 PM PDT 24
Finished Mar 26 02:54:04 PM PDT 24
Peak memory 203336 kb
Host smart-06f73a69-7843-4aac-9c6c-94e5ab60794c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22218
9969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.222189969
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.3328663697
Short name T695
Test name
Test status
Simulation time 8364415300 ps
CPU time 7.74 seconds
Started Mar 26 02:53:52 PM PDT 24
Finished Mar 26 02:54:00 PM PDT 24
Peak memory 203472 kb
Host smart-d531839d-5937-45ee-a813-a1d08bdd1178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33286
63697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.3328663697
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.3842283680
Short name T798
Test name
Test status
Simulation time 8468562596 ps
CPU time 7.79 seconds
Started Mar 26 02:53:46 PM PDT 24
Finished Mar 26 02:53:54 PM PDT 24
Peak memory 203476 kb
Host smart-5ed97f8b-edc5-489c-a5db-103ab8d9841d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38422
83680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.3842283680
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.721652363
Short name T529
Test name
Test status
Simulation time 8366081153 ps
CPU time 7.42 seconds
Started Mar 26 02:54:00 PM PDT 24
Finished Mar 26 02:54:08 PM PDT 24
Peak memory 203476 kb
Host smart-b463b902-1683-435f-bfa6-cabcbe66028b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72165
2363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.721652363
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_enable.2348045093
Short name T472
Test name
Test status
Simulation time 8370818449 ps
CPU time 7.22 seconds
Started Mar 26 02:53:59 PM PDT 24
Finished Mar 26 02:54:06 PM PDT 24
Peak memory 203460 kb
Host smart-ebe25a54-0f93-492d-994c-198b1265691f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23480
45093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.2348045093
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.2815622595
Short name T400
Test name
Test status
Simulation time 77425207 ps
CPU time 2.01 seconds
Started Mar 26 02:54:00 PM PDT 24
Finished Mar 26 02:54:03 PM PDT 24
Peak memory 203492 kb
Host smart-3c854435-f683-481f-977e-559bb03697e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28156
22595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2815622595
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.1177095106
Short name T543
Test name
Test status
Simulation time 8362816632 ps
CPU time 8.96 seconds
Started Mar 26 02:53:57 PM PDT 24
Finished Mar 26 02:54:06 PM PDT 24
Peak memory 203476 kb
Host smart-1cb614c2-a850-4b3f-922e-d47b60b2b09e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11770
95106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.1177095106
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.2598169436
Short name T414
Test name
Test status
Simulation time 8406563034 ps
CPU time 7.35 seconds
Started Mar 26 02:53:47 PM PDT 24
Finished Mar 26 02:53:54 PM PDT 24
Peak memory 203436 kb
Host smart-838a7be0-cf69-4244-9618-c9bb106936e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25981
69436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.2598169436
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.4188888380
Short name T571
Test name
Test status
Simulation time 8412592556 ps
CPU time 9.47 seconds
Started Mar 26 02:53:56 PM PDT 24
Finished Mar 26 02:54:06 PM PDT 24
Peak memory 203368 kb
Host smart-3e23c3e1-7485-4261-8a5f-46e178a985f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41888
88380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.4188888380
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.2387829892
Short name T443
Test name
Test status
Simulation time 8367319276 ps
CPU time 7.46 seconds
Started Mar 26 02:53:57 PM PDT 24
Finished Mar 26 02:54:05 PM PDT 24
Peak memory 203484 kb
Host smart-f476af64-dde1-4955-bb17-0b53c2a3dcce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23878
29892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.2387829892
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.205762882
Short name T633
Test name
Test status
Simulation time 8384761242 ps
CPU time 7.15 seconds
Started Mar 26 02:53:51 PM PDT 24
Finished Mar 26 02:53:59 PM PDT 24
Peak memory 203440 kb
Host smart-baf4f4b0-bd39-4fab-b606-d47a660027b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20576
2882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.205762882
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.590101390
Short name T807
Test name
Test status
Simulation time 8371458478 ps
CPU time 6.89 seconds
Started Mar 26 02:54:08 PM PDT 24
Finished Mar 26 02:54:16 PM PDT 24
Peak memory 203468 kb
Host smart-412c7e0e-ba75-4c54-aafb-a57536e07a19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59010
1390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.590101390
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.1656341040
Short name T572
Test name
Test status
Simulation time 26497350 ps
CPU time 0.62 seconds
Started Mar 26 02:53:50 PM PDT 24
Finished Mar 26 02:53:50 PM PDT 24
Peak memory 203360 kb
Host smart-24735318-4cfa-4930-a900-d2fdcab3e1c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16563
41040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.1656341040
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.679787071
Short name T354
Test name
Test status
Simulation time 8368632368 ps
CPU time 7.29 seconds
Started Mar 26 02:53:56 PM PDT 24
Finished Mar 26 02:54:04 PM PDT 24
Peak memory 203476 kb
Host smart-46122e25-7727-4897-af17-39b95108d688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67978
7071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.679787071
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.1299537076
Short name T465
Test name
Test status
Simulation time 8450668740 ps
CPU time 9.01 seconds
Started Mar 26 02:53:48 PM PDT 24
Finished Mar 26 02:53:57 PM PDT 24
Peak memory 203448 kb
Host smart-7a702b4a-1b89-42e0-981f-efe43f6999aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12995
37076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.1299537076
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.919053053
Short name T563
Test name
Test status
Simulation time 8409583513 ps
CPU time 8.3 seconds
Started Mar 26 02:53:50 PM PDT 24
Finished Mar 26 02:53:58 PM PDT 24
Peak memory 203504 kb
Host smart-fac0e2d0-dbba-49cd-b9b0-f6e9e5663d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91905
3053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.919053053
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.2194228697
Short name T873
Test name
Test status
Simulation time 8358836628 ps
CPU time 9.81 seconds
Started Mar 26 02:54:00 PM PDT 24
Finished Mar 26 02:54:10 PM PDT 24
Peak memory 203408 kb
Host smart-7e4a7928-30d5-49e9-9e95-34f14deba226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21942
28697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.2194228697
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.1325674663
Short name T146
Test name
Test status
Simulation time 8479321052 ps
CPU time 7.53 seconds
Started Mar 26 02:53:49 PM PDT 24
Finished Mar 26 02:53:57 PM PDT 24
Peak memory 203516 kb
Host smart-d422590d-134c-43ba-aab9-677f26750ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13256
74663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.1325674663
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.2227903499
Short name T329
Test name
Test status
Simulation time 8370165623 ps
CPU time 7.04 seconds
Started Mar 26 02:54:02 PM PDT 24
Finished Mar 26 02:54:09 PM PDT 24
Peak memory 203464 kb
Host smart-cec5eb04-db27-4a95-af16-3608b538b581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22279
03499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.2227903499
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_enable.2849599095
Short name T769
Test name
Test status
Simulation time 8367357170 ps
CPU time 7.32 seconds
Started Mar 26 02:54:12 PM PDT 24
Finished Mar 26 02:54:19 PM PDT 24
Peak memory 203460 kb
Host smart-33836691-3aee-4f0f-ad0c-f2f2cbe6a744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28495
99095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.2849599095
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.137904188
Short name T824
Test name
Test status
Simulation time 252229003 ps
CPU time 2.08 seconds
Started Mar 26 02:53:52 PM PDT 24
Finished Mar 26 02:53:54 PM PDT 24
Peak memory 203564 kb
Host smart-51c22d08-099b-4cfb-8ea2-34b981bba611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13790
4188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.137904188
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.1178228594
Short name T386
Test name
Test status
Simulation time 8361365904 ps
CPU time 8.46 seconds
Started Mar 26 02:53:53 PM PDT 24
Finished Mar 26 02:54:01 PM PDT 24
Peak memory 203460 kb
Host smart-046f7545-5fd9-4cd0-b53b-0b4e3928df2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11782
28594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1178228594
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.1325139517
Short name T644
Test name
Test status
Simulation time 8401649661 ps
CPU time 8.51 seconds
Started Mar 26 02:54:02 PM PDT 24
Finished Mar 26 02:54:11 PM PDT 24
Peak memory 203384 kb
Host smart-25b41f06-0a74-462a-94b6-88d5cce5327b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13251
39517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.1325139517
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2508259485
Short name T299
Test name
Test status
Simulation time 8409836567 ps
CPU time 7.34 seconds
Started Mar 26 02:54:02 PM PDT 24
Finished Mar 26 02:54:09 PM PDT 24
Peak memory 203480 kb
Host smart-906cebde-8e7f-45b1-a867-0fc4036bed97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25082
59485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2508259485
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1337548811
Short name T691
Test name
Test status
Simulation time 8365544413 ps
CPU time 7.23 seconds
Started Mar 26 02:54:01 PM PDT 24
Finished Mar 26 02:54:08 PM PDT 24
Peak memory 203472 kb
Host smart-f5c134a2-eee7-4a35-bb33-85994a082ad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13375
48811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1337548811
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.608592721
Short name T29
Test name
Test status
Simulation time 8391645262 ps
CPU time 8.22 seconds
Started Mar 26 02:53:51 PM PDT 24
Finished Mar 26 02:54:00 PM PDT 24
Peak memory 203404 kb
Host smart-1709dda7-f0b9-47f8-b15b-888ba604e061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60859
2721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.608592721
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.3084748913
Short name T842
Test name
Test status
Simulation time 8375184696 ps
CPU time 7.4 seconds
Started Mar 26 02:53:50 PM PDT 24
Finished Mar 26 02:53:57 PM PDT 24
Peak memory 203460 kb
Host smart-42f18e2f-bdd7-4a19-b2a3-ea556e00f4bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30847
48913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.3084748913
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.417661358
Short name T315
Test name
Test status
Simulation time 8384845789 ps
CPU time 7.67 seconds
Started Mar 26 02:53:55 PM PDT 24
Finished Mar 26 02:54:03 PM PDT 24
Peak memory 203476 kb
Host smart-4f043201-f436-4b95-b342-da1ac3300b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41766
1358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.417661358
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3640860802
Short name T857
Test name
Test status
Simulation time 28252683 ps
CPU time 0.63 seconds
Started Mar 26 02:53:52 PM PDT 24
Finished Mar 26 02:53:52 PM PDT 24
Peak memory 203380 kb
Host smart-a49e08cc-f122-42f7-b16a-0b7d8b3b7081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36408
60802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3640860802
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.3913482801
Short name T368
Test name
Test status
Simulation time 8362016702 ps
CPU time 6.94 seconds
Started Mar 26 02:53:53 PM PDT 24
Finished Mar 26 02:54:00 PM PDT 24
Peak memory 203428 kb
Host smart-f2baea40-a40d-4fba-b778-7a7f89778e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39134
82801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.3913482801
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.3348975524
Short name T864
Test name
Test status
Simulation time 8437488018 ps
CPU time 8.46 seconds
Started Mar 26 02:53:57 PM PDT 24
Finished Mar 26 02:54:05 PM PDT 24
Peak memory 203496 kb
Host smart-6e4b0a75-7fb8-4fec-87b1-152cf77d6c44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33489
75524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.3348975524
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.3164613344
Short name T827
Test name
Test status
Simulation time 8368941522 ps
CPU time 9.57 seconds
Started Mar 26 02:53:59 PM PDT 24
Finished Mar 26 02:54:08 PM PDT 24
Peak memory 203484 kb
Host smart-7b358f82-3771-4a11-b485-54c50fd44fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31646
13344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.3164613344
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.2902147994
Short name T619
Test name
Test status
Simulation time 8356741323 ps
CPU time 7.11 seconds
Started Mar 26 02:54:03 PM PDT 24
Finished Mar 26 02:54:11 PM PDT 24
Peak memory 203420 kb
Host smart-1e49047c-7dc8-4c02-b8e1-c26868e0fb62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29021
47994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.2902147994
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.3091198908
Short name T82
Test name
Test status
Simulation time 8471866877 ps
CPU time 7.62 seconds
Started Mar 26 02:53:45 PM PDT 24
Finished Mar 26 02:53:52 PM PDT 24
Peak memory 203520 kb
Host smart-55243f24-ebe6-40ae-9536-4506c7af47fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30911
98908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3091198908
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.3032904103
Short name T788
Test name
Test status
Simulation time 8365987268 ps
CPU time 7.06 seconds
Started Mar 26 02:52:25 PM PDT 24
Finished Mar 26 02:52:32 PM PDT 24
Peak memory 203472 kb
Host smart-417ba489-8d7b-4f4a-bc2a-abaea2e54d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30329
04103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.3032904103
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_enable.1914309577
Short name T478
Test name
Test status
Simulation time 8365399281 ps
CPU time 7.59 seconds
Started Mar 26 02:52:24 PM PDT 24
Finished Mar 26 02:52:32 PM PDT 24
Peak memory 203404 kb
Host smart-461e7e33-2e86-46d3-bcb4-e7b065c27643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19143
09577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1914309577
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.3045899055
Short name T516
Test name
Test status
Simulation time 73909426 ps
CPU time 1.95 seconds
Started Mar 26 02:52:24 PM PDT 24
Finished Mar 26 02:52:26 PM PDT 24
Peak memory 203536 kb
Host smart-0aed84b4-be80-4feb-a702-2b7f2f0e8949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30458
99055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.3045899055
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.3339903345
Short name T160
Test name
Test status
Simulation time 8356369796 ps
CPU time 7.15 seconds
Started Mar 26 02:52:27 PM PDT 24
Finished Mar 26 02:52:34 PM PDT 24
Peak memory 203396 kb
Host smart-c378b960-a631-4403-9216-8a33d505237e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33399
03345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.3339903345
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.500347383
Short name T129
Test name
Test status
Simulation time 8385328871 ps
CPU time 6.92 seconds
Started Mar 26 02:52:28 PM PDT 24
Finished Mar 26 02:52:35 PM PDT 24
Peak memory 203472 kb
Host smart-786592a3-d0c2-41d7-8e2f-7ddb813ce913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50034
7383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.500347383
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.4143910521
Short name T754
Test name
Test status
Simulation time 8409370786 ps
CPU time 6.91 seconds
Started Mar 26 02:52:14 PM PDT 24
Finished Mar 26 02:52:21 PM PDT 24
Peak memory 203504 kb
Host smart-dd09522b-8a92-461d-81e9-7cf5a3b562f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41439
10521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.4143910521
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1159997462
Short name T510
Test name
Test status
Simulation time 8361629049 ps
CPU time 7.84 seconds
Started Mar 26 02:52:09 PM PDT 24
Finished Mar 26 02:52:17 PM PDT 24
Peak memory 203496 kb
Host smart-4d0a02cb-b864-4c3c-8b0d-a6eeb09f39ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11599
97462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1159997462
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.819416582
Short name T618
Test name
Test status
Simulation time 8389261668 ps
CPU time 8.91 seconds
Started Mar 26 02:52:08 PM PDT 24
Finished Mar 26 02:52:17 PM PDT 24
Peak memory 203480 kb
Host smart-7d2886b5-c898-4faa-8e0c-727413c704dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81941
6582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.819416582
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.88288182
Short name T437
Test name
Test status
Simulation time 8387107656 ps
CPU time 7.75 seconds
Started Mar 26 02:52:14 PM PDT 24
Finished Mar 26 02:52:22 PM PDT 24
Peak memory 203472 kb
Host smart-644b55a5-8778-439f-b6d3-786f0daec934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88288
182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.88288182
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.3596556619
Short name T597
Test name
Test status
Simulation time 8388288101 ps
CPU time 7.85 seconds
Started Mar 26 02:52:09 PM PDT 24
Finished Mar 26 02:52:18 PM PDT 24
Peak memory 203500 kb
Host smart-ef08a551-a3c3-4e34-b7ec-bf20aec35e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35965
56619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.3596556619
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.1148394904
Short name T819
Test name
Test status
Simulation time 28329766 ps
CPU time 0.63 seconds
Started Mar 26 02:52:09 PM PDT 24
Finished Mar 26 02:52:10 PM PDT 24
Peak memory 203356 kb
Host smart-2ad1f0a3-6440-4b4c-9e7b-4d218db5d0ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11483
94904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.1148394904
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.3281483629
Short name T223
Test name
Test status
Simulation time 8408921592 ps
CPU time 7.53 seconds
Started Mar 26 02:52:14 PM PDT 24
Finished Mar 26 02:52:22 PM PDT 24
Peak memory 203472 kb
Host smart-f6291e35-eab4-4305-a953-0c62c09d8b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32814
83629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3281483629
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2194256579
Short name T867
Test name
Test status
Simulation time 8400866931 ps
CPU time 7.29 seconds
Started Mar 26 02:52:21 PM PDT 24
Finished Mar 26 02:52:28 PM PDT 24
Peak memory 203440 kb
Host smart-fe4289d4-46be-43f3-9c23-880fc333c969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21942
56579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2194256579
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.3742411683
Short name T846
Test name
Test status
Simulation time 8376956236 ps
CPU time 7.33 seconds
Started Mar 26 02:52:41 PM PDT 24
Finished Mar 26 02:52:49 PM PDT 24
Peak memory 203464 kb
Host smart-d8ac9126-63da-4169-979b-325ea1e432cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37424
11683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.3742411683
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.981738591
Short name T55
Test name
Test status
Simulation time 121594182 ps
CPU time 0.94 seconds
Started Mar 26 02:52:12 PM PDT 24
Finished Mar 26 02:52:13 PM PDT 24
Peak memory 219304 kb
Host smart-8bacc53a-aa75-4462-8c02-030676076f7a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=981738591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.981738591
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.1418737387
Short name T337
Test name
Test status
Simulation time 8362896655 ps
CPU time 7.48 seconds
Started Mar 26 02:52:22 PM PDT 24
Finished Mar 26 02:52:30 PM PDT 24
Peak memory 203400 kb
Host smart-4d466177-d75c-4c07-9590-63c08c466ef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14187
37387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.1418737387
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.620909517
Short name T801
Test name
Test status
Simulation time 8481772837 ps
CPU time 7.73 seconds
Started Mar 26 02:52:22 PM PDT 24
Finished Mar 26 02:52:30 PM PDT 24
Peak memory 203480 kb
Host smart-be470223-33ab-4d90-b832-cd1a526f569d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62090
9517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.620909517
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1779839623
Short name T600
Test name
Test status
Simulation time 8370137698 ps
CPU time 7.27 seconds
Started Mar 26 02:53:56 PM PDT 24
Finished Mar 26 02:54:03 PM PDT 24
Peak memory 203436 kb
Host smart-0b127f69-60b3-410e-b825-5b1e0545804c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17798
39623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1779839623
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_enable.3044022297
Short name T428
Test name
Test status
Simulation time 8369884836 ps
CPU time 7.2 seconds
Started Mar 26 02:54:06 PM PDT 24
Finished Mar 26 02:54:14 PM PDT 24
Peak memory 203452 kb
Host smart-88ca6abf-c4b4-428c-9a39-2947d9dabbf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30440
22297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.3044022297
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.2156186254
Short name T320
Test name
Test status
Simulation time 243138677 ps
CPU time 2.13 seconds
Started Mar 26 02:53:42 PM PDT 24
Finished Mar 26 02:53:44 PM PDT 24
Peak memory 203548 kb
Host smart-35cb2425-e2b6-443e-b1c2-8e4b0b3ddbf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21561
86254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2156186254
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.979993891
Short name T174
Test name
Test status
Simulation time 8358830851 ps
CPU time 7.33 seconds
Started Mar 26 02:53:57 PM PDT 24
Finished Mar 26 02:54:05 PM PDT 24
Peak memory 203488 kb
Host smart-c66ac0f0-b160-4580-bdac-32ac1c1ce4c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97999
3891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.979993891
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2583293312
Short name T218
Test name
Test status
Simulation time 8439408969 ps
CPU time 8.79 seconds
Started Mar 26 02:53:56 PM PDT 24
Finished Mar 26 02:54:05 PM PDT 24
Peak memory 203452 kb
Host smart-58bc9b9f-ae75-4cfd-8791-77f56eb4b63d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25832
93312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2583293312
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.3887465669
Short name T806
Test name
Test status
Simulation time 8406484166 ps
CPU time 7.35 seconds
Started Mar 26 02:53:51 PM PDT 24
Finished Mar 26 02:53:58 PM PDT 24
Peak memory 203492 kb
Host smart-33653ca9-11f9-4491-8989-116a806640be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38874
65669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.3887465669
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.288125412
Short name T413
Test name
Test status
Simulation time 8368326500 ps
CPU time 9.63 seconds
Started Mar 26 02:53:57 PM PDT 24
Finished Mar 26 02:54:07 PM PDT 24
Peak memory 203472 kb
Host smart-93b9a858-bc6a-4836-b3ed-531895e549b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28812
5412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.288125412
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.911417876
Short name T566
Test name
Test status
Simulation time 8402710628 ps
CPU time 7.44 seconds
Started Mar 26 02:53:55 PM PDT 24
Finished Mar 26 02:54:02 PM PDT 24
Peak memory 203472 kb
Host smart-a767dc3d-1f82-4438-a45f-2471c22a71a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91141
7876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.911417876
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.517340187
Short name T21
Test name
Test status
Simulation time 8388841204 ps
CPU time 7.4 seconds
Started Mar 26 02:54:05 PM PDT 24
Finished Mar 26 02:54:13 PM PDT 24
Peak memory 203464 kb
Host smart-7bd5b2ad-8c43-4ea3-91c4-53815f089c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51734
0187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.517340187
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.2703350610
Short name T729
Test name
Test status
Simulation time 8370779417 ps
CPU time 7.36 seconds
Started Mar 26 02:53:57 PM PDT 24
Finished Mar 26 02:54:05 PM PDT 24
Peak memory 203472 kb
Host smart-52cd8a32-27e9-447d-b272-5e36c71a6e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27033
50610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2703350610
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.2617039842
Short name T768
Test name
Test status
Simulation time 27901402 ps
CPU time 0.62 seconds
Started Mar 26 02:53:54 PM PDT 24
Finished Mar 26 02:53:55 PM PDT 24
Peak memory 203328 kb
Host smart-a6663888-923b-4ec9-8fd4-73d552de7e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26170
39842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.2617039842
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.2150043433
Short name T577
Test name
Test status
Simulation time 8398388869 ps
CPU time 9.71 seconds
Started Mar 26 02:53:55 PM PDT 24
Finished Mar 26 02:54:05 PM PDT 24
Peak memory 203476 kb
Host smart-5144c0b8-7ff8-4370-834d-e49ca7fbcce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21500
43433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.2150043433
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.3349378045
Short name T511
Test name
Test status
Simulation time 8436357921 ps
CPU time 6.95 seconds
Started Mar 26 02:54:00 PM PDT 24
Finished Mar 26 02:54:08 PM PDT 24
Peak memory 203464 kb
Host smart-3f9f5ac7-2ec6-452e-a931-63b4b5a8b7de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33493
78045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.3349378045
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.2925167662
Short name T728
Test name
Test status
Simulation time 8393623095 ps
CPU time 7.94 seconds
Started Mar 26 02:54:05 PM PDT 24
Finished Mar 26 02:54:13 PM PDT 24
Peak memory 203464 kb
Host smart-ece273ac-decc-42b0-b6a2-bad0fb5630aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29251
67662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.2925167662
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.3507153098
Short name T394
Test name
Test status
Simulation time 8361070453 ps
CPU time 7.15 seconds
Started Mar 26 02:53:59 PM PDT 24
Finished Mar 26 02:54:06 PM PDT 24
Peak memory 203488 kb
Host smart-549b243b-9697-4707-b424-d704edcd77af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35071
53098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.3507153098
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.2228961987
Short name T131
Test name
Test status
Simulation time 8476023722 ps
CPU time 7.21 seconds
Started Mar 26 02:53:53 PM PDT 24
Finished Mar 26 02:54:01 PM PDT 24
Peak memory 203484 kb
Host smart-d6bab1a4-0213-453e-8f04-239fd3788b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22289
61987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2228961987
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.4137740674
Short name T425
Test name
Test status
Simulation time 8366110297 ps
CPU time 8.86 seconds
Started Mar 26 02:54:03 PM PDT 24
Finished Mar 26 02:54:12 PM PDT 24
Peak memory 203456 kb
Host smart-1eb6b914-91ff-44f5-9506-77306962aae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41377
40674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.4137740674
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_enable.4106702043
Short name T348
Test name
Test status
Simulation time 8366481996 ps
CPU time 9.4 seconds
Started Mar 26 02:53:58 PM PDT 24
Finished Mar 26 02:54:08 PM PDT 24
Peak memory 203392 kb
Host smart-ca5e530b-3d05-4a07-84f1-a40e612a6028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41067
02043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.4106702043
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.1758957159
Short name T455
Test name
Test status
Simulation time 164064799 ps
CPU time 1.46 seconds
Started Mar 26 02:54:02 PM PDT 24
Finished Mar 26 02:54:04 PM PDT 24
Peak memory 203524 kb
Host smart-7615a99a-bba1-4d7c-8e95-907b41e59a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17589
57159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.1758957159
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1092311913
Short name T175
Test name
Test status
Simulation time 8357036867 ps
CPU time 6.88 seconds
Started Mar 26 02:54:12 PM PDT 24
Finished Mar 26 02:54:20 PM PDT 24
Peak memory 203468 kb
Host smart-3bfeddc6-c041-4489-bae5-ff12dd6d8af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10923
11913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1092311913
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.4091562505
Short name T630
Test name
Test status
Simulation time 8395336468 ps
CPU time 8.2 seconds
Started Mar 26 02:53:56 PM PDT 24
Finished Mar 26 02:54:04 PM PDT 24
Peak memory 203468 kb
Host smart-9c8eb071-a625-4f4c-8cc5-1a714b3c42a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40915
62505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.4091562505
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.4249171792
Short name T273
Test name
Test status
Simulation time 8406597303 ps
CPU time 8.81 seconds
Started Mar 26 02:54:01 PM PDT 24
Finished Mar 26 02:54:10 PM PDT 24
Peak memory 203464 kb
Host smart-9acc2300-c111-4edb-9d10-c121baabd270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42491
71792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.4249171792
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.2487356621
Short name T287
Test name
Test status
Simulation time 8365301749 ps
CPU time 7.3 seconds
Started Mar 26 02:54:00 PM PDT 24
Finished Mar 26 02:54:08 PM PDT 24
Peak memory 202896 kb
Host smart-fd479563-c298-4b84-94de-716e38b49059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24873
56621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.2487356621
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.3181600298
Short name T108
Test name
Test status
Simulation time 8398348702 ps
CPU time 7.38 seconds
Started Mar 26 02:54:32 PM PDT 24
Finished Mar 26 02:54:40 PM PDT 24
Peak memory 203476 kb
Host smart-bdb6d029-e374-4820-90a1-9b8668645cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31816
00298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3181600298
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.2182523192
Short name T388
Test name
Test status
Simulation time 8400036737 ps
CPU time 7.37 seconds
Started Mar 26 02:53:59 PM PDT 24
Finished Mar 26 02:54:06 PM PDT 24
Peak memory 203460 kb
Host smart-bb1cf446-0428-4a6c-b580-133fb354827b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21825
23192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.2182523192
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3597892843
Short name T883
Test name
Test status
Simulation time 8376108350 ps
CPU time 7.31 seconds
Started Mar 26 02:53:54 PM PDT 24
Finished Mar 26 02:54:01 PM PDT 24
Peak memory 203484 kb
Host smart-7740d897-ab05-43ee-88f2-239b4dd05716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35978
92843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3597892843
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.211087919
Short name T399
Test name
Test status
Simulation time 30576927 ps
CPU time 0.68 seconds
Started Mar 26 02:53:59 PM PDT 24
Finished Mar 26 02:54:00 PM PDT 24
Peak memory 203380 kb
Host smart-890f8146-78d2-4097-91d1-2542b27955ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21108
7919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.211087919
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.576440451
Short name T522
Test name
Test status
Simulation time 8392598771 ps
CPU time 9.42 seconds
Started Mar 26 02:53:54 PM PDT 24
Finished Mar 26 02:54:04 PM PDT 24
Peak memory 203488 kb
Host smart-743e093b-0a15-4cc6-9776-fe3ffc662d75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57644
0451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.576440451
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3009351077
Short name T32
Test name
Test status
Simulation time 8448089820 ps
CPU time 8.27 seconds
Started Mar 26 02:54:27 PM PDT 24
Finished Mar 26 02:54:35 PM PDT 24
Peak memory 203680 kb
Host smart-7fe9c6fc-951a-42ef-85fe-50ccc273039e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30093
51077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3009351077
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.123820517
Short name T398
Test name
Test status
Simulation time 8406709307 ps
CPU time 9.31 seconds
Started Mar 26 02:53:55 PM PDT 24
Finished Mar 26 02:54:05 PM PDT 24
Peak memory 203492 kb
Host smart-c3f1aeae-513f-4d51-92ea-112b33efb3a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12382
0517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.123820517
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.46794078
Short name T542
Test name
Test status
Simulation time 8359358941 ps
CPU time 7.33 seconds
Started Mar 26 02:53:53 PM PDT 24
Finished Mar 26 02:54:00 PM PDT 24
Peak memory 203480 kb
Host smart-556e02e7-0ef3-4134-985f-c834cbcfe53b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46794
078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.46794078
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.2258460498
Short name T519
Test name
Test status
Simulation time 8479033787 ps
CPU time 7.42 seconds
Started Mar 26 02:54:01 PM PDT 24
Finished Mar 26 02:54:09 PM PDT 24
Peak memory 203404 kb
Host smart-16267602-3996-46da-a7db-e1835bbb4794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22584
60498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.2258460498
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2446523246
Short name T512
Test name
Test status
Simulation time 8369283651 ps
CPU time 7.98 seconds
Started Mar 26 02:53:59 PM PDT 24
Finished Mar 26 02:54:08 PM PDT 24
Peak memory 203472 kb
Host smart-c95fb019-add5-453a-a95b-58efaab78018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24465
23246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2446523246
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_enable.2093853985
Short name T734
Test name
Test status
Simulation time 8364571714 ps
CPU time 7.92 seconds
Started Mar 26 02:54:27 PM PDT 24
Finished Mar 26 02:54:36 PM PDT 24
Peak memory 203468 kb
Host smart-28c4ee6b-3c35-4117-b864-20149e5459f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20938
53985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.2093853985
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.2467905851
Short name T225
Test name
Test status
Simulation time 113608693 ps
CPU time 1.4 seconds
Started Mar 26 02:53:58 PM PDT 24
Finished Mar 26 02:54:00 PM PDT 24
Peak memory 203544 kb
Host smart-8d422369-bb18-4ac0-91e2-5a07c3e17b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24679
05851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.2467905851
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.281710350
Short name T5
Test name
Test status
Simulation time 8360955198 ps
CPU time 7.27 seconds
Started Mar 26 02:53:56 PM PDT 24
Finished Mar 26 02:54:04 PM PDT 24
Peak memory 203452 kb
Host smart-44f3ad8f-360a-4b57-a8a5-02d8521a5e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28171
0350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.281710350
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.1849945834
Short name T852
Test name
Test status
Simulation time 8444588549 ps
CPU time 7.12 seconds
Started Mar 26 02:54:51 PM PDT 24
Finished Mar 26 02:54:58 PM PDT 24
Peak memory 203472 kb
Host smart-712d461b-098c-43a2-9d1d-51102fbcab8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18499
45834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1849945834
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.3990010620
Short name T810
Test name
Test status
Simulation time 8409031564 ps
CPU time 9.59 seconds
Started Mar 26 02:53:59 PM PDT 24
Finished Mar 26 02:54:09 PM PDT 24
Peak memory 202892 kb
Host smart-f46b62ba-88bf-4881-9026-dfc28ee893fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39900
10620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.3990010620
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.1957818478
Short name T659
Test name
Test status
Simulation time 8366196741 ps
CPU time 6.92 seconds
Started Mar 26 02:54:45 PM PDT 24
Finished Mar 26 02:54:53 PM PDT 24
Peak memory 203392 kb
Host smart-5bf260f7-6b11-41f2-b6ad-5cc44edfcc46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19578
18478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.1957818478
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.4063362104
Short name T446
Test name
Test status
Simulation time 8398887755 ps
CPU time 7.61 seconds
Started Mar 26 02:53:58 PM PDT 24
Finished Mar 26 02:54:05 PM PDT 24
Peak memory 203496 kb
Host smart-0dd90ccd-30b1-4d14-906c-217f43566f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40633
62104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.4063362104
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.518815298
Short name T795
Test name
Test status
Simulation time 8377232086 ps
CPU time 9.05 seconds
Started Mar 26 02:54:19 PM PDT 24
Finished Mar 26 02:54:28 PM PDT 24
Peak memory 203448 kb
Host smart-241bc60a-07f8-4dee-b77e-950a729c0718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51881
5298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.518815298
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.3272825330
Short name T503
Test name
Test status
Simulation time 8382773509 ps
CPU time 9.01 seconds
Started Mar 26 02:54:38 PM PDT 24
Finished Mar 26 02:54:48 PM PDT 24
Peak memory 203476 kb
Host smart-15215c45-93a1-44cc-a242-855d65ba367a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32728
25330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.3272825330
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.2242957508
Short name T410
Test name
Test status
Simulation time 25154860 ps
CPU time 0.62 seconds
Started Mar 26 02:53:57 PM PDT 24
Finished Mar 26 02:53:57 PM PDT 24
Peak memory 203392 kb
Host smart-3164507d-12d5-44df-99da-ea52e0d4f024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22429
57508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2242957508
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.54243661
Short name T295
Test name
Test status
Simulation time 8397181943 ps
CPU time 8.42 seconds
Started Mar 26 02:54:13 PM PDT 24
Finished Mar 26 02:54:22 PM PDT 24
Peak memory 203416 kb
Host smart-cbfb6301-3fb4-4447-b590-76ea0cb0297b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54243
661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.54243661
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.80313242
Short name T720
Test name
Test status
Simulation time 8385849815 ps
CPU time 7.22 seconds
Started Mar 26 02:53:56 PM PDT 24
Finished Mar 26 02:54:03 PM PDT 24
Peak memory 203448 kb
Host smart-4655c1f3-ba50-49d0-ab06-985d74f514b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80313
242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.80313242
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.2776301108
Short name T681
Test name
Test status
Simulation time 8395780496 ps
CPU time 8.6 seconds
Started Mar 26 02:53:55 PM PDT 24
Finished Mar 26 02:54:04 PM PDT 24
Peak memory 203436 kb
Host smart-5ffa0a97-ccac-4e18-a0b0-e4dbbbcb2801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27763
01108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.2776301108
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2220965140
Short name T680
Test name
Test status
Simulation time 8358271690 ps
CPU time 7.66 seconds
Started Mar 26 02:54:04 PM PDT 24
Finished Mar 26 02:54:12 PM PDT 24
Peak memory 203480 kb
Host smart-7d84db75-bfa2-41d5-98a5-6f51918ef62f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22209
65140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2220965140
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.104300221
Short name T121
Test name
Test status
Simulation time 8476098296 ps
CPU time 8.32 seconds
Started Mar 26 02:54:01 PM PDT 24
Finished Mar 26 02:54:09 PM PDT 24
Peak memory 203480 kb
Host smart-af5810a2-b2ac-49a6-a869-21e7e07edf56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10430
0221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.104300221
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.688687985
Short name T283
Test name
Test status
Simulation time 8368102653 ps
CPU time 7.91 seconds
Started Mar 26 02:56:05 PM PDT 24
Finished Mar 26 02:56:13 PM PDT 24
Peak memory 203228 kb
Host smart-5bd282f3-f9e7-4a20-a506-2bd0e8440383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68868
7985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.688687985
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_enable.4163182929
Short name T504
Test name
Test status
Simulation time 8372749585 ps
CPU time 8.12 seconds
Started Mar 26 02:53:57 PM PDT 24
Finished Mar 26 02:54:05 PM PDT 24
Peak memory 203476 kb
Host smart-cb324fee-3b45-47c2-80fb-492c18ce27d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41631
82929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.4163182929
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.3358096964
Short name T172
Test name
Test status
Simulation time 8362625112 ps
CPU time 8.46 seconds
Started Mar 26 02:53:58 PM PDT 24
Finished Mar 26 02:54:07 PM PDT 24
Peak memory 203452 kb
Host smart-85264201-e084-4796-9ba2-7079a2ce656a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33580
96964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.3358096964
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.3969407501
Short name T690
Test name
Test status
Simulation time 8394923617 ps
CPU time 7.51 seconds
Started Mar 26 02:53:55 PM PDT 24
Finished Mar 26 02:54:02 PM PDT 24
Peak memory 203472 kb
Host smart-89769cd8-e15d-4607-bb5a-b49151375407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39694
07501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3969407501
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.3076306023
Short name T424
Test name
Test status
Simulation time 8409393399 ps
CPU time 10.17 seconds
Started Mar 26 02:53:52 PM PDT 24
Finished Mar 26 02:54:02 PM PDT 24
Peak memory 203472 kb
Host smart-bef267f9-d854-4a72-a529-0c695351828c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30763
06023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.3076306023
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.1535147776
Short name T774
Test name
Test status
Simulation time 8361624140 ps
CPU time 7.38 seconds
Started Mar 26 02:53:57 PM PDT 24
Finished Mar 26 02:54:04 PM PDT 24
Peak memory 203488 kb
Host smart-deaedd08-f44f-49c7-ad56-33493a4f62a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15351
47776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1535147776
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.3785475505
Short name T412
Test name
Test status
Simulation time 8384787861 ps
CPU time 7.79 seconds
Started Mar 26 02:54:04 PM PDT 24
Finished Mar 26 02:54:12 PM PDT 24
Peak memory 203432 kb
Host smart-485cf3fd-8259-4c55-98e1-c50aa842af76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37854
75505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.3785475505
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.4115025273
Short name T605
Test name
Test status
Simulation time 8378287381 ps
CPU time 7.9 seconds
Started Mar 26 02:54:01 PM PDT 24
Finished Mar 26 02:54:09 PM PDT 24
Peak memory 203664 kb
Host smart-9c4a6210-6952-4712-ac16-c9b90a7f3b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41150
25273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.4115025273
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.419716159
Short name T38
Test name
Test status
Simulation time 32019224 ps
CPU time 0.64 seconds
Started Mar 26 02:53:59 PM PDT 24
Finished Mar 26 02:54:00 PM PDT 24
Peak memory 202652 kb
Host smart-f62c0dc0-afc6-410e-90bf-6507bc6ebb65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41971
6159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.419716159
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.859915914
Short name T702
Test name
Test status
Simulation time 8400913259 ps
CPU time 7.99 seconds
Started Mar 26 02:53:59 PM PDT 24
Finished Mar 26 02:54:07 PM PDT 24
Peak memory 203408 kb
Host smart-0e78cfad-b663-4112-a5b9-f6bdeec64438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85991
5914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.859915914
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2534475085
Short name T664
Test name
Test status
Simulation time 8445062080 ps
CPU time 8.28 seconds
Started Mar 26 02:54:09 PM PDT 24
Finished Mar 26 02:54:22 PM PDT 24
Peak memory 203384 kb
Host smart-5e0beaf4-8640-4645-b327-8e2a2dd72662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25344
75085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2534475085
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.1596397509
Short name T872
Test name
Test status
Simulation time 8399549171 ps
CPU time 8.7 seconds
Started Mar 26 02:53:55 PM PDT 24
Finished Mar 26 02:54:04 PM PDT 24
Peak memory 203488 kb
Host smart-2a0f3a68-e3b4-4936-8875-d7bf0c1fa25e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15963
97509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.1596397509
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.659102742
Short name T751
Test name
Test status
Simulation time 8358693621 ps
CPU time 8.53 seconds
Started Mar 26 02:53:58 PM PDT 24
Finished Mar 26 02:54:06 PM PDT 24
Peak memory 203484 kb
Host smart-e7e64eec-db45-4d08-b5c2-28f90a37b3f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65910
2742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.659102742
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.4112742773
Short name T587
Test name
Test status
Simulation time 8368887759 ps
CPU time 7.94 seconds
Started Mar 26 02:53:59 PM PDT 24
Finished Mar 26 02:54:07 PM PDT 24
Peak memory 203440 kb
Host smart-7b13c3a4-523b-4682-a1a2-db98e12916ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41127
42773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.4112742773
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_enable.4287697146
Short name T322
Test name
Test status
Simulation time 8374216346 ps
CPU time 7.33 seconds
Started Mar 26 02:54:01 PM PDT 24
Finished Mar 26 02:54:09 PM PDT 24
Peak memory 203464 kb
Host smart-8347c6f4-4e51-4900-bfdb-fc38ad1bd8c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42876
97146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.4287697146
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.1616672710
Short name T203
Test name
Test status
Simulation time 71335014 ps
CPU time 1.75 seconds
Started Mar 26 02:54:00 PM PDT 24
Finished Mar 26 02:54:02 PM PDT 24
Peak memory 203536 kb
Host smart-0388def7-556d-4604-a889-6756cbc58814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16166
72710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.1616672710
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2615321327
Short name T515
Test name
Test status
Simulation time 8364294285 ps
CPU time 8.61 seconds
Started Mar 26 02:54:04 PM PDT 24
Finished Mar 26 02:54:13 PM PDT 24
Peak memory 203448 kb
Host smart-817edad1-1895-45f0-aa3b-d8b676a4c43d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26153
21327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2615321327
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.1121735310
Short name T533
Test name
Test status
Simulation time 8459672126 ps
CPU time 7.95 seconds
Started Mar 26 02:53:56 PM PDT 24
Finished Mar 26 02:54:05 PM PDT 24
Peak memory 203440 kb
Host smart-a4511522-983e-427c-bb32-ddb81a372160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11217
35310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.1121735310
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1265016175
Short name T856
Test name
Test status
Simulation time 8404349727 ps
CPU time 7.3 seconds
Started Mar 26 02:54:28 PM PDT 24
Finished Mar 26 02:54:35 PM PDT 24
Peak memory 203456 kb
Host smart-17986fca-4b39-48fc-90c1-adfd3c249b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12650
16175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1265016175
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3261493793
Short name T319
Test name
Test status
Simulation time 8365046028 ps
CPU time 7.6 seconds
Started Mar 26 02:53:59 PM PDT 24
Finished Mar 26 02:54:07 PM PDT 24
Peak memory 203476 kb
Host smart-89e2af05-c930-4c22-bd0d-fd4f8a5eb2db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32614
93793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3261493793
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.467484766
Short name T10
Test name
Test status
Simulation time 8448223246 ps
CPU time 9.54 seconds
Started Mar 26 02:53:58 PM PDT 24
Finished Mar 26 02:54:08 PM PDT 24
Peak memory 203500 kb
Host smart-9d475b9a-bf13-4b88-b760-605005deb295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46748
4766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.467484766
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.4045564145
Short name T19
Test name
Test status
Simulation time 8377703295 ps
CPU time 7.85 seconds
Started Mar 26 02:53:49 PM PDT 24
Finished Mar 26 02:53:57 PM PDT 24
Peak memory 203452 kb
Host smart-2231720d-63e1-4d12-bc3b-797b79d462b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40455
64145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.4045564145
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.1743140506
Short name T869
Test name
Test status
Simulation time 8394403222 ps
CPU time 7.81 seconds
Started Mar 26 02:53:55 PM PDT 24
Finished Mar 26 02:54:03 PM PDT 24
Peak memory 203504 kb
Host smart-d501c69c-41e1-4001-8786-17d460872d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17431
40506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.1743140506
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.429924612
Short name T26
Test name
Test status
Simulation time 24874583 ps
CPU time 0.63 seconds
Started Mar 26 02:53:58 PM PDT 24
Finished Mar 26 02:53:59 PM PDT 24
Peak memory 203388 kb
Host smart-75baeaf9-5068-4d77-b3d9-7d015780fe8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42992
4612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.429924612
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.2028532867
Short name T805
Test name
Test status
Simulation time 8403367812 ps
CPU time 7.9 seconds
Started Mar 26 02:54:00 PM PDT 24
Finished Mar 26 02:54:08 PM PDT 24
Peak memory 203504 kb
Host smart-c35d4716-19fb-4b6a-b46c-d7180889df6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20285
32867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.2028532867
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1738395558
Short name T88
Test name
Test status
Simulation time 8408265422 ps
CPU time 8.31 seconds
Started Mar 26 02:54:00 PM PDT 24
Finished Mar 26 02:54:13 PM PDT 24
Peak memory 203464 kb
Host smart-47849fc0-b183-478a-bd99-8171570cb863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17383
95558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1738395558
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.2746479646
Short name T860
Test name
Test status
Simulation time 8378271906 ps
CPU time 7.57 seconds
Started Mar 26 02:54:03 PM PDT 24
Finished Mar 26 02:54:11 PM PDT 24
Peak memory 203500 kb
Host smart-952d853c-e606-477b-8f57-c342cba06726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27464
79646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.2746479646
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.843603661
Short name T440
Test name
Test status
Simulation time 8360784891 ps
CPU time 7.18 seconds
Started Mar 26 02:54:02 PM PDT 24
Finished Mar 26 02:54:10 PM PDT 24
Peak memory 203456 kb
Host smart-76e3d900-12f1-487e-89ee-aeec381a9a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84360
3661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.843603661
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.745502528
Short name T471
Test name
Test status
Simulation time 8470790889 ps
CPU time 7.58 seconds
Started Mar 26 02:53:50 PM PDT 24
Finished Mar 26 02:53:58 PM PDT 24
Peak memory 203396 kb
Host smart-80f6e7b9-2a2f-4b63-a9b4-f1fde097be70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74550
2528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.745502528
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.404882397
Short name T781
Test name
Test status
Simulation time 8371687818 ps
CPU time 7.63 seconds
Started Mar 26 02:53:56 PM PDT 24
Finished Mar 26 02:54:04 PM PDT 24
Peak memory 203420 kb
Host smart-7810be15-5461-4869-b88e-b556463abaff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40488
2397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.404882397
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_enable.3447111154
Short name T470
Test name
Test status
Simulation time 8368021457 ps
CPU time 7.65 seconds
Started Mar 26 02:54:09 PM PDT 24
Finished Mar 26 02:54:17 PM PDT 24
Peak memory 203440 kb
Host smart-2912323b-060a-43b2-a0e8-0f2057f4893f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34471
11154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.3447111154
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.772244007
Short name T682
Test name
Test status
Simulation time 120907148 ps
CPU time 1.23 seconds
Started Mar 26 02:54:00 PM PDT 24
Finished Mar 26 02:54:02 PM PDT 24
Peak memory 203488 kb
Host smart-333f49cf-f922-4bea-ac65-35f31ef8bf0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77224
4007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.772244007
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3383697753
Short name T721
Test name
Test status
Simulation time 8357563471 ps
CPU time 7.84 seconds
Started Mar 26 02:54:05 PM PDT 24
Finished Mar 26 02:54:13 PM PDT 24
Peak memory 203472 kb
Host smart-0a5f8c2d-dffb-4db1-817d-a69c8a2e0381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33836
97753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3383697753
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2361997646
Short name T431
Test name
Test status
Simulation time 8424541052 ps
CPU time 9.99 seconds
Started Mar 26 02:54:08 PM PDT 24
Finished Mar 26 02:54:19 PM PDT 24
Peak memory 203336 kb
Host smart-1dedb431-228b-4547-8f30-0df7ee6a63c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23619
97646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2361997646
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.2878115552
Short name T615
Test name
Test status
Simulation time 8409732824 ps
CPU time 7.45 seconds
Started Mar 26 02:54:01 PM PDT 24
Finished Mar 26 02:54:09 PM PDT 24
Peak memory 203520 kb
Host smart-53f3054d-dad7-4d24-9a98-3d5bc503d3c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28781
15552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.2878115552
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2396245280
Short name T432
Test name
Test status
Simulation time 8362339014 ps
CPU time 7.85 seconds
Started Mar 26 02:54:25 PM PDT 24
Finished Mar 26 02:54:33 PM PDT 24
Peak memory 203512 kb
Host smart-97d64350-a0bf-4df2-a87a-2076b7fc8329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23962
45280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2396245280
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.3381207680
Short name T724
Test name
Test status
Simulation time 8412088435 ps
CPU time 9.48 seconds
Started Mar 26 02:54:06 PM PDT 24
Finished Mar 26 02:54:16 PM PDT 24
Peak memory 203480 kb
Host smart-84ced719-efcc-4a99-88ae-dbd1ea8ee27f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33812
07680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3381207680
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.266813346
Short name T449
Test name
Test status
Simulation time 8401848415 ps
CPU time 8.7 seconds
Started Mar 26 02:53:59 PM PDT 24
Finished Mar 26 02:54:08 PM PDT 24
Peak memory 203408 kb
Host smart-7b2d0e2d-2f04-4dd0-bae7-3c1537dc3205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26681
3346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.266813346
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3891399201
Short name T743
Test name
Test status
Simulation time 8403892811 ps
CPU time 8.61 seconds
Started Mar 26 02:54:00 PM PDT 24
Finished Mar 26 02:54:09 PM PDT 24
Peak memory 203504 kb
Host smart-6b349a95-49fa-4f38-9419-4f2940aafb7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38913
99201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3891399201
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.100863057
Short name T733
Test name
Test status
Simulation time 27761349 ps
CPU time 0.64 seconds
Started Mar 26 02:54:07 PM PDT 24
Finished Mar 26 02:54:08 PM PDT 24
Peak memory 203328 kb
Host smart-f75e751a-8a9e-4393-916d-4c5c14298bca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10086
3057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.100863057
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.1075708073
Short name T444
Test name
Test status
Simulation time 8379821825 ps
CPU time 8.61 seconds
Started Mar 26 02:54:04 PM PDT 24
Finished Mar 26 02:54:13 PM PDT 24
Peak memory 203484 kb
Host smart-d32efe7f-4fe4-4413-b609-4a75c3f49e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10757
08073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.1075708073
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.6064940
Short name T39
Test name
Test status
Simulation time 8443044625 ps
CPU time 7.12 seconds
Started Mar 26 02:53:59 PM PDT 24
Finished Mar 26 02:54:07 PM PDT 24
Peak memory 203472 kb
Host smart-91dfcf8d-573b-417e-a2a6-932b8deb7f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60649
40 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.6064940
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.511561858
Short name T268
Test name
Test status
Simulation time 8382753530 ps
CPU time 6.88 seconds
Started Mar 26 02:54:02 PM PDT 24
Finished Mar 26 02:54:09 PM PDT 24
Peak memory 203392 kb
Host smart-20fd2285-de79-4657-aca4-1ac3fc7dc47f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51156
1858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.511561858
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.3021580683
Short name T463
Test name
Test status
Simulation time 8362860169 ps
CPU time 7.61 seconds
Started Mar 26 02:54:02 PM PDT 24
Finished Mar 26 02:54:09 PM PDT 24
Peak memory 203516 kb
Host smart-c0af17c1-db06-4208-8fb0-3a3ab47a46b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30215
80683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.3021580683
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.1769142044
Short name T17
Test name
Test status
Simulation time 8477263040 ps
CPU time 7.66 seconds
Started Mar 26 02:53:58 PM PDT 24
Finished Mar 26 02:54:06 PM PDT 24
Peak memory 203488 kb
Host smart-49fb2a8d-bfe2-4562-bf52-3af2ea26ac0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17691
42044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1769142044
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.223099279
Short name T646
Test name
Test status
Simulation time 8370964895 ps
CPU time 7.42 seconds
Started Mar 26 02:54:05 PM PDT 24
Finished Mar 26 02:54:13 PM PDT 24
Peak memory 203480 kb
Host smart-86821db5-4f7b-4835-879f-feca490cd019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22309
9279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.223099279
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_enable.922535464
Short name T473
Test name
Test status
Simulation time 8374889543 ps
CPU time 7.48 seconds
Started Mar 26 02:53:56 PM PDT 24
Finished Mar 26 02:54:04 PM PDT 24
Peak memory 203516 kb
Host smart-c8fa4343-ccb3-4e05-9450-c0ba17c1c5c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92253
5464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.922535464
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3916661754
Short name T639
Test name
Test status
Simulation time 8361253378 ps
CPU time 8.34 seconds
Started Mar 26 02:53:59 PM PDT 24
Finished Mar 26 02:54:08 PM PDT 24
Peak memory 203464 kb
Host smart-ca8e202e-4be9-4953-9d40-82e43d64705e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39166
61754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3916661754
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.770993629
Short name T705
Test name
Test status
Simulation time 8452679721 ps
CPU time 7.87 seconds
Started Mar 26 02:53:55 PM PDT 24
Finished Mar 26 02:54:03 PM PDT 24
Peak memory 203468 kb
Host smart-547cb444-74e5-4471-9fd3-857942344357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77099
3629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.770993629
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.1152672169
Short name T323
Test name
Test status
Simulation time 8410741205 ps
CPU time 8.93 seconds
Started Mar 26 02:54:07 PM PDT 24
Finished Mar 26 02:54:16 PM PDT 24
Peak memory 203680 kb
Host smart-ad128e6a-bf65-4e4c-bf0f-baa36ee09cee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11526
72169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.1152672169
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.743058425
Short name T793
Test name
Test status
Simulation time 8364847325 ps
CPU time 7.2 seconds
Started Mar 26 02:54:22 PM PDT 24
Finished Mar 26 02:54:30 PM PDT 24
Peak memory 203512 kb
Host smart-0e817cde-672c-4286-882a-8faa8a3a8cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74305
8425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.743058425
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.3607161165
Short name T698
Test name
Test status
Simulation time 8427465639 ps
CPU time 8.01 seconds
Started Mar 26 02:54:02 PM PDT 24
Finished Mar 26 02:54:10 PM PDT 24
Peak memory 203456 kb
Host smart-b85ab970-9da9-4d61-a526-20297c04b90c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36071
61165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.3607161165
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2058202204
Short name T648
Test name
Test status
Simulation time 8406203260 ps
CPU time 7.47 seconds
Started Mar 26 02:54:04 PM PDT 24
Finished Mar 26 02:54:11 PM PDT 24
Peak memory 203476 kb
Host smart-2e6ad0a7-97c5-4491-971d-738a764455b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20582
02204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2058202204
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.3332692162
Short name T9
Test name
Test status
Simulation time 8399332027 ps
CPU time 7.29 seconds
Started Mar 26 02:54:13 PM PDT 24
Finished Mar 26 02:54:21 PM PDT 24
Peak memory 203464 kb
Host smart-dd49fb77-c0fb-4b71-8230-b05bb40d70a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33326
92162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.3332692162
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.2292732144
Short name T623
Test name
Test status
Simulation time 29662456 ps
CPU time 0.63 seconds
Started Mar 26 02:54:06 PM PDT 24
Finished Mar 26 02:54:07 PM PDT 24
Peak memory 203212 kb
Host smart-a8f92afb-01ce-40c6-9347-c34d5267683a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22927
32144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.2292732144
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.268944845
Short name T281
Test name
Test status
Simulation time 8392371567 ps
CPU time 8.05 seconds
Started Mar 26 02:54:01 PM PDT 24
Finished Mar 26 02:54:09 PM PDT 24
Peak memory 203472 kb
Host smart-76241a2e-3cae-47ec-a627-7fa6f657846f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26894
4845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.268944845
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.14628183
Short name T497
Test name
Test status
Simulation time 8374377673 ps
CPU time 8.93 seconds
Started Mar 26 02:53:59 PM PDT 24
Finished Mar 26 02:54:09 PM PDT 24
Peak memory 203448 kb
Host smart-78bc0798-e2c3-4b86-a2d2-fc1329b6424c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14628
183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.14628183
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.1686436318
Short name T304
Test name
Test status
Simulation time 8380301712 ps
CPU time 7.01 seconds
Started Mar 26 02:54:04 PM PDT 24
Finished Mar 26 02:54:11 PM PDT 24
Peak memory 203464 kb
Host smart-40ae9d07-8ae3-476b-b5aa-32e82cd12c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16864
36318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.1686436318
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.175163982
Short name T640
Test name
Test status
Simulation time 8358934703 ps
CPU time 7.48 seconds
Started Mar 26 02:53:58 PM PDT 24
Finished Mar 26 02:54:05 PM PDT 24
Peak memory 203384 kb
Host smart-42c5a105-c105-4e30-af0a-e327ea8f6fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17516
3982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.175163982
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.3328785247
Short name T140
Test name
Test status
Simulation time 8473581842 ps
CPU time 7.72 seconds
Started Mar 26 02:54:10 PM PDT 24
Finished Mar 26 02:54:18 PM PDT 24
Peak memory 203472 kb
Host smart-8874a2d1-0efb-485c-b4cf-9bcb6140c316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33287
85247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3328785247
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.3204221586
Short name T72
Test name
Test status
Simulation time 8371877706 ps
CPU time 7.09 seconds
Started Mar 26 02:53:57 PM PDT 24
Finished Mar 26 02:54:04 PM PDT 24
Peak memory 203516 kb
Host smart-761260e3-737b-4592-849e-e86fe1e988a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32042
21586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.3204221586
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_enable.2394952117
Short name T574
Test name
Test status
Simulation time 8367237845 ps
CPU time 7.23 seconds
Started Mar 26 02:54:12 PM PDT 24
Finished Mar 26 02:54:19 PM PDT 24
Peak memory 203460 kb
Host smart-01789e26-02de-4270-8f62-1611026b16b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23949
52117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2394952117
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.126471458
Short name T224
Test name
Test status
Simulation time 65253159 ps
CPU time 1.84 seconds
Started Mar 26 02:54:03 PM PDT 24
Finished Mar 26 02:54:05 PM PDT 24
Peak memory 203576 kb
Host smart-db92a8ad-2ba2-4303-bec0-22b5b0af586e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12647
1458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.126471458
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.745458623
Short name T171
Test name
Test status
Simulation time 8358278623 ps
CPU time 7.89 seconds
Started Mar 26 02:53:56 PM PDT 24
Finished Mar 26 02:54:04 PM PDT 24
Peak memory 203436 kb
Host smart-2ffea75e-9c48-4206-bd25-f0b2cafc3a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74545
8623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.745458623
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.2861508207
Short name T132
Test name
Test status
Simulation time 8404769438 ps
CPU time 7.91 seconds
Started Mar 26 02:53:57 PM PDT 24
Finished Mar 26 02:54:05 PM PDT 24
Peak memory 203488 kb
Host smart-e0af259c-6065-480a-a230-45156ece9f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28615
08207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2861508207
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.1471270475
Short name T362
Test name
Test status
Simulation time 8411613301 ps
CPU time 7.64 seconds
Started Mar 26 02:53:59 PM PDT 24
Finished Mar 26 02:54:07 PM PDT 24
Peak memory 203456 kb
Host smart-33c1941f-f47a-4b38-8368-1af929e5c5ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14712
70475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.1471270475
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.1868614139
Short name T631
Test name
Test status
Simulation time 8363151669 ps
CPU time 7.71 seconds
Started Mar 26 02:54:11 PM PDT 24
Finished Mar 26 02:54:18 PM PDT 24
Peak memory 203340 kb
Host smart-5ddadba2-e59a-40c9-9ef1-2c66aed50e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18686
14139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.1868614139
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.2328693916
Short name T665
Test name
Test status
Simulation time 8438614805 ps
CPU time 7.24 seconds
Started Mar 26 02:54:06 PM PDT 24
Finished Mar 26 02:54:14 PM PDT 24
Peak memory 203476 kb
Host smart-f30c72e0-fa64-4a41-bd02-3d67d77524a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23286
93916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.2328693916
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.3251458661
Short name T811
Test name
Test status
Simulation time 8365837990 ps
CPU time 8.03 seconds
Started Mar 26 02:54:09 PM PDT 24
Finished Mar 26 02:54:17 PM PDT 24
Peak memory 203472 kb
Host smart-7a44baa4-3796-4990-ac51-27bdf65bf2b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32514
58661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.3251458661
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.739959098
Short name T536
Test name
Test status
Simulation time 8376736136 ps
CPU time 8.44 seconds
Started Mar 26 02:54:28 PM PDT 24
Finished Mar 26 02:54:37 PM PDT 24
Peak memory 203452 kb
Host smart-f7ef6884-36c3-4d22-8d9e-e65deef087fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73995
9098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.739959098
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.4195806361
Short name T704
Test name
Test status
Simulation time 34114342 ps
CPU time 0.63 seconds
Started Mar 26 02:54:11 PM PDT 24
Finished Mar 26 02:54:12 PM PDT 24
Peak memory 203344 kb
Host smart-ca18be7e-744c-4681-b809-337644eda6a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41958
06361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.4195806361
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.1677708050
Short name T451
Test name
Test status
Simulation time 8383573562 ps
CPU time 7.2 seconds
Started Mar 26 02:54:39 PM PDT 24
Finished Mar 26 02:54:47 PM PDT 24
Peak memory 203468 kb
Host smart-e5a76c02-9be1-45e4-93c1-5111c5ab44cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16777
08050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1677708050
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.3719773068
Short name T489
Test name
Test status
Simulation time 8422187965 ps
CPU time 8.26 seconds
Started Mar 26 02:54:02 PM PDT 24
Finished Mar 26 02:54:10 PM PDT 24
Peak memory 203476 kb
Host smart-77f65094-87b4-4b0b-8bf8-e0eaf7343a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37197
73068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3719773068
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.614908764
Short name T277
Test name
Test status
Simulation time 8365438781 ps
CPU time 7.09 seconds
Started Mar 26 02:53:59 PM PDT 24
Finished Mar 26 02:54:06 PM PDT 24
Peak memory 203440 kb
Host smart-7a0d9edc-a0da-47a7-8c76-0c9c9e4bbc1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61490
8764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.614908764
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2935981944
Short name T453
Test name
Test status
Simulation time 8365010002 ps
CPU time 7.54 seconds
Started Mar 26 02:54:00 PM PDT 24
Finished Mar 26 02:54:08 PM PDT 24
Peak memory 203388 kb
Host smart-35a2a0b1-8b7a-461b-ac01-a18ae30050d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29359
81944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2935981944
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.2444149907
Short name T548
Test name
Test status
Simulation time 8470554733 ps
CPU time 8.87 seconds
Started Mar 26 02:53:59 PM PDT 24
Finished Mar 26 02:54:09 PM PDT 24
Peak memory 203480 kb
Host smart-3817359e-c7e9-4a6d-ae84-5ab8a222ce45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24441
49907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.2444149907
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.890834362
Short name T212
Test name
Test status
Simulation time 8370701707 ps
CPU time 8.5 seconds
Started Mar 26 02:53:55 PM PDT 24
Finished Mar 26 02:54:04 PM PDT 24
Peak memory 203452 kb
Host smart-b9adac92-cad0-4138-a233-554610f25580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89083
4362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.890834362
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_enable.195854483
Short name T380
Test name
Test status
Simulation time 8371313865 ps
CPU time 8.38 seconds
Started Mar 26 02:54:03 PM PDT 24
Finished Mar 26 02:54:12 PM PDT 24
Peak memory 203404 kb
Host smart-ed810785-231e-4e67-b0c4-81ebfd9330da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19585
4483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.195854483
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.2733650229
Short name T837
Test name
Test status
Simulation time 175901611 ps
CPU time 1.92 seconds
Started Mar 26 02:54:02 PM PDT 24
Finished Mar 26 02:54:04 PM PDT 24
Peak memory 203564 kb
Host smart-80f0dad4-92af-4e48-8325-642e05e86d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27336
50229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.2733650229
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.3372243639
Short name T675
Test name
Test status
Simulation time 8357790478 ps
CPU time 7.39 seconds
Started Mar 26 02:54:30 PM PDT 24
Finished Mar 26 02:54:38 PM PDT 24
Peak memory 203464 kb
Host smart-8073aa59-653d-4f63-97a1-666f5ba81ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33722
43639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.3372243639
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.2684922214
Short name T739
Test name
Test status
Simulation time 8408550477 ps
CPU time 9.62 seconds
Started Mar 26 02:54:05 PM PDT 24
Finished Mar 26 02:54:14 PM PDT 24
Peak memory 203408 kb
Host smart-9e325f75-403d-4fd0-abd7-bd1e7f7feb73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26849
22214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.2684922214
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.2540550555
Short name T316
Test name
Test status
Simulation time 8405902045 ps
CPU time 8.1 seconds
Started Mar 26 02:54:39 PM PDT 24
Finished Mar 26 02:54:48 PM PDT 24
Peak memory 203344 kb
Host smart-4dd47604-e881-4e38-b063-b90fcd31df27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25405
50555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.2540550555
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.3356368756
Short name T70
Test name
Test status
Simulation time 8361023173 ps
CPU time 10.02 seconds
Started Mar 26 02:54:00 PM PDT 24
Finished Mar 26 02:54:11 PM PDT 24
Peak memory 203476 kb
Host smart-402ee397-50d3-42de-840b-bc2f0a09026b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33563
68756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.3356368756
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.442101785
Short name T31
Test name
Test status
Simulation time 8434981684 ps
CPU time 7.68 seconds
Started Mar 26 02:53:56 PM PDT 24
Finished Mar 26 02:54:04 PM PDT 24
Peak memory 203456 kb
Host smart-463f3451-f094-4a00-856e-7b449f857b1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44210
1785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.442101785
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.225006640
Short name T658
Test name
Test status
Simulation time 8391256985 ps
CPU time 7.38 seconds
Started Mar 26 02:54:05 PM PDT 24
Finished Mar 26 02:54:12 PM PDT 24
Peak memory 203456 kb
Host smart-c5607cb9-4813-4ab0-a91f-64608f53c8f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22500
6640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.225006640
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.3137362847
Short name T726
Test name
Test status
Simulation time 8387249997 ps
CPU time 8.97 seconds
Started Mar 26 02:54:00 PM PDT 24
Finished Mar 26 02:54:09 PM PDT 24
Peak memory 203480 kb
Host smart-6a75cf8f-ae19-4436-968e-a17722c1281b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31373
62847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.3137362847
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.2544637616
Short name T546
Test name
Test status
Simulation time 26622561 ps
CPU time 0.63 seconds
Started Mar 26 02:54:14 PM PDT 24
Finished Mar 26 02:54:15 PM PDT 24
Peak memory 203284 kb
Host smart-bac8a4e9-e93b-4d7b-a3f3-2baf9df4fa79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25446
37616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.2544637616
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.3264748533
Short name T700
Test name
Test status
Simulation time 8392581513 ps
CPU time 7.53 seconds
Started Mar 26 02:54:01 PM PDT 24
Finished Mar 26 02:54:08 PM PDT 24
Peak memory 203448 kb
Host smart-d1bbe425-a996-437d-bbe7-9c311da1ca13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32647
48533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.3264748533
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.508048607
Short name T764
Test name
Test status
Simulation time 8442714165 ps
CPU time 7.41 seconds
Started Mar 26 02:53:59 PM PDT 24
Finished Mar 26 02:54:06 PM PDT 24
Peak memory 203452 kb
Host smart-3faa77e2-58ad-4a27-b63d-fc1c76657d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50804
8607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.508048607
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.534307072
Short name T48
Test name
Test status
Simulation time 8387615193 ps
CPU time 7.37 seconds
Started Mar 26 02:54:03 PM PDT 24
Finished Mar 26 02:54:11 PM PDT 24
Peak memory 203472 kb
Host smart-4c98b8c3-7624-4cb7-83d3-7a53fafcd376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53430
7072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.534307072
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.225826820
Short name T750
Test name
Test status
Simulation time 8362286599 ps
CPU time 7.23 seconds
Started Mar 26 02:54:02 PM PDT 24
Finished Mar 26 02:54:10 PM PDT 24
Peak memory 203476 kb
Host smart-08604d52-47ce-470a-899f-5e778e9be8f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22582
6820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.225826820
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.2508612939
Short name T866
Test name
Test status
Simulation time 8370413127 ps
CPU time 7.61 seconds
Started Mar 26 02:54:02 PM PDT 24
Finished Mar 26 02:54:10 PM PDT 24
Peak memory 203492 kb
Host smart-17289881-8a8d-4e00-a2c9-8fdc0cfedbb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25086
12939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.2508612939
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_enable.3904473040
Short name T350
Test name
Test status
Simulation time 8374146361 ps
CPU time 7.71 seconds
Started Mar 26 02:54:06 PM PDT 24
Finished Mar 26 02:54:14 PM PDT 24
Peak memory 203484 kb
Host smart-721115af-ff96-474c-82c2-f4be9ccaefc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39044
73040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.3904473040
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.453295419
Short name T524
Test name
Test status
Simulation time 175874218 ps
CPU time 2 seconds
Started Mar 26 02:54:00 PM PDT 24
Finished Mar 26 02:54:03 PM PDT 24
Peak memory 203400 kb
Host smart-6e3ed5e5-a788-4776-937b-e923b68a1bb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45329
5419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.453295419
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.579591624
Short name T787
Test name
Test status
Simulation time 8364306483 ps
CPU time 7.86 seconds
Started Mar 26 02:54:33 PM PDT 24
Finished Mar 26 02:54:41 PM PDT 24
Peak memory 203488 kb
Host smart-24856d3c-fbee-4979-b62a-81b8018cc08e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57959
1624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.579591624
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.4233362516
Short name T119
Test name
Test status
Simulation time 8391017979 ps
CPU time 7.68 seconds
Started Mar 26 02:54:00 PM PDT 24
Finished Mar 26 02:54:08 PM PDT 24
Peak memory 203444 kb
Host smart-51dc8aef-8efe-4e71-b0c2-d0348a5ac298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42333
62516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.4233362516
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.3455518921
Short name T505
Test name
Test status
Simulation time 8406465002 ps
CPU time 8.36 seconds
Started Mar 26 02:54:08 PM PDT 24
Finished Mar 26 02:54:17 PM PDT 24
Peak memory 203392 kb
Host smart-0bda8415-fe05-4c44-8cd1-30ee82e82ad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34555
18921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.3455518921
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3110089035
Short name T269
Test name
Test status
Simulation time 8360322273 ps
CPU time 10.04 seconds
Started Mar 26 02:54:00 PM PDT 24
Finished Mar 26 02:54:11 PM PDT 24
Peak memory 203500 kb
Host smart-279af560-3250-4829-b6e4-211261986766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31100
89035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3110089035
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.1153968322
Short name T506
Test name
Test status
Simulation time 8434060163 ps
CPU time 7.57 seconds
Started Mar 26 02:54:27 PM PDT 24
Finished Mar 26 02:54:35 PM PDT 24
Peak memory 203496 kb
Host smart-79140b2d-3ad3-432f-a40f-1074d6d16cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11539
68322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.1153968322
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3078738073
Short name T523
Test name
Test status
Simulation time 8370130466 ps
CPU time 7.63 seconds
Started Mar 26 02:54:15 PM PDT 24
Finished Mar 26 02:54:23 PM PDT 24
Peak memory 203452 kb
Host smart-f37ae9fa-7331-4929-b5ce-fb0637a9d16f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30787
38073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3078738073
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.504472726
Short name T468
Test name
Test status
Simulation time 8378381636 ps
CPU time 7.61 seconds
Started Mar 26 02:54:04 PM PDT 24
Finished Mar 26 02:54:12 PM PDT 24
Peak memory 203476 kb
Host smart-07c02c5b-6ff2-4c14-8efc-8df7348040bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50447
2726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.504472726
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.1209161885
Short name T34
Test name
Test status
Simulation time 20709348 ps
CPU time 0.64 seconds
Started Mar 26 02:54:05 PM PDT 24
Finished Mar 26 02:54:06 PM PDT 24
Peak memory 203272 kb
Host smart-d3426a92-d9eb-464b-bcb5-86682b4d6b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12091
61885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.1209161885
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3031246570
Short name T484
Test name
Test status
Simulation time 8395674521 ps
CPU time 7.59 seconds
Started Mar 26 02:53:59 PM PDT 24
Finished Mar 26 02:54:06 PM PDT 24
Peak memory 203464 kb
Host smart-1923bfed-5aec-417a-8dda-c800101a5d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30312
46570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3031246570
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1104987776
Short name T544
Test name
Test status
Simulation time 8407204195 ps
CPU time 7.11 seconds
Started Mar 26 02:54:02 PM PDT 24
Finished Mar 26 02:54:09 PM PDT 24
Peak memory 203464 kb
Host smart-8975a757-c3dd-4c5b-91ff-f44bedf2a827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11049
87776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1104987776
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.3787177746
Short name T513
Test name
Test status
Simulation time 8400768107 ps
CPU time 7.45 seconds
Started Mar 26 02:54:07 PM PDT 24
Finished Mar 26 02:54:15 PM PDT 24
Peak memory 203404 kb
Host smart-7caa113c-30eb-4801-8b9f-6bd4f401fd81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37871
77746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.3787177746
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.1049878663
Short name T12
Test name
Test status
Simulation time 8361414271 ps
CPU time 9.51 seconds
Started Mar 26 02:54:11 PM PDT 24
Finished Mar 26 02:54:21 PM PDT 24
Peak memory 203460 kb
Host smart-0bb344ef-ac1c-4a8f-b89d-85f8488bf14f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10498
78663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.1049878663
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.566807719
Short name T123
Test name
Test status
Simulation time 8473185798 ps
CPU time 7.7 seconds
Started Mar 26 02:54:15 PM PDT 24
Finished Mar 26 02:54:23 PM PDT 24
Peak memory 203472 kb
Host smart-a3761f5b-9627-48c6-951d-025da27a4183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56680
7719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.566807719
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.1211741697
Short name T303
Test name
Test status
Simulation time 8368910008 ps
CPU time 7.24 seconds
Started Mar 26 02:52:08 PM PDT 24
Finished Mar 26 02:52:16 PM PDT 24
Peak memory 203464 kb
Host smart-5643543d-5f89-41f9-8a90-0c40d1cdad81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12117
41697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1211741697
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_enable.2941954742
Short name T592
Test name
Test status
Simulation time 8369929036 ps
CPU time 9.93 seconds
Started Mar 26 02:52:12 PM PDT 24
Finished Mar 26 02:52:22 PM PDT 24
Peak memory 203672 kb
Host smart-ee3600c4-151e-4f7b-be0d-64e122abddef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29419
54742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2941954742
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.1489794539
Short name T481
Test name
Test status
Simulation time 54208587 ps
CPU time 1.49 seconds
Started Mar 26 02:52:08 PM PDT 24
Finished Mar 26 02:52:10 PM PDT 24
Peak memory 203488 kb
Host smart-0c7fa11f-ad11-424d-b5a4-6aa50f9eda66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14897
94539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.1489794539
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.3117034096
Short name T158
Test name
Test status
Simulation time 8356966475 ps
CPU time 6.93 seconds
Started Mar 26 02:52:26 PM PDT 24
Finished Mar 26 02:52:33 PM PDT 24
Peak memory 203476 kb
Host smart-65665fda-1910-4493-8f0a-9b77a726dbdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31170
34096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.3117034096
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.1018566400
Short name T363
Test name
Test status
Simulation time 8417699626 ps
CPU time 8.2 seconds
Started Mar 26 02:52:40 PM PDT 24
Finished Mar 26 02:52:49 PM PDT 24
Peak memory 203468 kb
Host smart-08d85311-49bd-49fc-a56e-e35b8c272e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10185
66400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1018566400
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.4204095316
Short name T709
Test name
Test status
Simulation time 8416272646 ps
CPU time 8.25 seconds
Started Mar 26 02:52:10 PM PDT 24
Finished Mar 26 02:52:18 PM PDT 24
Peak memory 203472 kb
Host smart-f4eae548-dbc2-48b4-8dd9-075a0d0e15b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42040
95316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.4204095316
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.4154848782
Short name T279
Test name
Test status
Simulation time 8360794609 ps
CPU time 7.11 seconds
Started Mar 26 02:52:08 PM PDT 24
Finished Mar 26 02:52:15 PM PDT 24
Peak memory 203492 kb
Host smart-f8e974e8-ef40-410f-92fb-eaafff80f917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41548
48782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.4154848782
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.448400877
Short name T742
Test name
Test status
Simulation time 8379768533 ps
CPU time 9.86 seconds
Started Mar 26 02:52:10 PM PDT 24
Finished Mar 26 02:52:20 PM PDT 24
Peak memory 203472 kb
Host smart-cbf79440-bb4b-4e92-9c67-9475a7727cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44840
0877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.448400877
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.4001677720
Short name T584
Test name
Test status
Simulation time 8388503620 ps
CPU time 9.56 seconds
Started Mar 26 02:52:43 PM PDT 24
Finished Mar 26 02:52:52 PM PDT 24
Peak memory 203476 kb
Host smart-5de18bed-3a21-4b26-9cfe-b9a4135ffdb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40016
77720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.4001677720
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.2203653153
Short name T884
Test name
Test status
Simulation time 8393408309 ps
CPU time 9.89 seconds
Started Mar 26 02:52:43 PM PDT 24
Finished Mar 26 02:52:53 PM PDT 24
Peak memory 203480 kb
Host smart-b1eaee35-d7ef-4cee-9122-8a2a4c45db6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22036
53153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2203653153
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.3869682358
Short name T660
Test name
Test status
Simulation time 24223780 ps
CPU time 0.63 seconds
Started Mar 26 02:52:22 PM PDT 24
Finished Mar 26 02:52:23 PM PDT 24
Peak memory 203324 kb
Host smart-e62a2579-c6aa-477e-b832-f7a636c93e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38696
82358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.3869682358
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.2096006029
Short name T45
Test name
Test status
Simulation time 8366793982 ps
CPU time 8.03 seconds
Started Mar 26 02:52:08 PM PDT 24
Finished Mar 26 02:52:17 PM PDT 24
Peak memory 203452 kb
Host smart-47d5954a-aead-47d3-a59b-b3caef0fad61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20960
06029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2096006029
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.1611703474
Short name T421
Test name
Test status
Simulation time 8417854237 ps
CPU time 7.61 seconds
Started Mar 26 02:52:12 PM PDT 24
Finished Mar 26 02:52:20 PM PDT 24
Peak memory 203464 kb
Host smart-36b8c493-3c27-4e3a-93ef-4f66d851a83f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16117
03474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.1611703474
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.3571247604
Short name T569
Test name
Test status
Simulation time 8399516219 ps
CPU time 9.02 seconds
Started Mar 26 02:52:14 PM PDT 24
Finished Mar 26 02:52:23 PM PDT 24
Peak memory 203508 kb
Host smart-090b4bde-1698-4534-b62f-d952ecfe8893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35712
47604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.3571247604
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1840500328
Short name T843
Test name
Test status
Simulation time 8356079051 ps
CPU time 8.42 seconds
Started Mar 26 02:52:15 PM PDT 24
Finished Mar 26 02:52:23 PM PDT 24
Peak memory 203400 kb
Host smart-f19e5b5c-9f9b-4fa2-8245-707e484675c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18405
00328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1840500328
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.225644772
Short name T124
Test name
Test status
Simulation time 8478577836 ps
CPU time 7.88 seconds
Started Mar 26 02:52:38 PM PDT 24
Finished Mar 26 02:52:46 PM PDT 24
Peak memory 203460 kb
Host smart-c81a1784-45f6-43b5-a1f5-fe46966bd789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22564
4772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.225644772
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.3014666298
Short name T564
Test name
Test status
Simulation time 8374241285 ps
CPU time 7.64 seconds
Started Mar 26 02:53:07 PM PDT 24
Finished Mar 26 02:53:15 PM PDT 24
Peak memory 203464 kb
Host smart-2303cf72-20df-4421-a173-35a715a8693a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30146
66298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.3014666298
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_enable.627379290
Short name T773
Test name
Test status
Simulation time 8374119575 ps
CPU time 8.06 seconds
Started Mar 26 02:52:46 PM PDT 24
Finished Mar 26 02:52:54 PM PDT 24
Peak memory 203332 kb
Host smart-b834ab78-2777-4129-b141-0c4457d52ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62737
9290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.627379290
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.3685698799
Short name T696
Test name
Test status
Simulation time 81243273 ps
CPU time 1.16 seconds
Started Mar 26 02:52:14 PM PDT 24
Finished Mar 26 02:52:15 PM PDT 24
Peak memory 203460 kb
Host smart-9a8d7e7c-5a9e-440b-b237-3e59ec7f5e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36856
98799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.3685698799
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.3395214148
Short name T151
Test name
Test status
Simulation time 8362298491 ps
CPU time 9.35 seconds
Started Mar 26 02:52:11 PM PDT 24
Finished Mar 26 02:52:21 PM PDT 24
Peak memory 203456 kb
Host smart-29899275-e95b-41bb-b429-3462deb31738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33952
14148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.3395214148
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.1119827267
Short name T133
Test name
Test status
Simulation time 8434439437 ps
CPU time 7.77 seconds
Started Mar 26 02:52:45 PM PDT 24
Finished Mar 26 02:52:53 PM PDT 24
Peak memory 203456 kb
Host smart-083c4667-b6cd-4b1e-b060-807c4ed1d2fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11198
27267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.1119827267
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.3919707605
Short name T461
Test name
Test status
Simulation time 8405980921 ps
CPU time 7.51 seconds
Started Mar 26 02:52:09 PM PDT 24
Finished Mar 26 02:52:17 PM PDT 24
Peak memory 203500 kb
Host smart-6a87b950-0847-494c-8bda-d665cfe466aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39197
07605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.3919707605
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.1964215742
Short name T707
Test name
Test status
Simulation time 8365975977 ps
CPU time 9.31 seconds
Started Mar 26 02:52:22 PM PDT 24
Finished Mar 26 02:52:32 PM PDT 24
Peak memory 203456 kb
Host smart-5801a4d6-6600-437b-abc2-9c936b97f54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19642
15742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.1964215742
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.2928830186
Short name T749
Test name
Test status
Simulation time 8413081049 ps
CPU time 7.44 seconds
Started Mar 26 02:52:09 PM PDT 24
Finished Mar 26 02:52:17 PM PDT 24
Peak memory 203456 kb
Host smart-e856ca85-b157-499e-b17a-c3ef29129bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29288
30186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.2928830186
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3714466563
Short name T712
Test name
Test status
Simulation time 8394894474 ps
CPU time 7.44 seconds
Started Mar 26 02:52:15 PM PDT 24
Finished Mar 26 02:52:23 PM PDT 24
Peak memory 203472 kb
Host smart-8e525104-5651-47ca-a419-7cddb4a273a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37144
66563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3714466563
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.3527577507
Short name T881
Test name
Test status
Simulation time 8383937243 ps
CPU time 7.43 seconds
Started Mar 26 02:52:33 PM PDT 24
Finished Mar 26 02:52:41 PM PDT 24
Peak memory 203452 kb
Host smart-7f194625-4613-48bd-97fb-ba81848d9893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35275
77507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.3527577507
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.309424524
Short name T596
Test name
Test status
Simulation time 23834334 ps
CPU time 0.63 seconds
Started Mar 26 02:52:50 PM PDT 24
Finished Mar 26 02:52:51 PM PDT 24
Peak memory 203332 kb
Host smart-2bfe04a7-cafd-466f-b077-cf8675cbc6fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30942
4524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.309424524
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.4187964357
Short name T701
Test name
Test status
Simulation time 8380852795 ps
CPU time 7.56 seconds
Started Mar 26 02:52:10 PM PDT 24
Finished Mar 26 02:52:18 PM PDT 24
Peak memory 203672 kb
Host smart-f04346ff-e0f4-4adf-b3d7-880c524ea926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41879
64357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.4187964357
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.510300820
Short name T127
Test name
Test status
Simulation time 8376354840 ps
CPU time 8.35 seconds
Started Mar 26 02:52:15 PM PDT 24
Finished Mar 26 02:52:24 PM PDT 24
Peak memory 203396 kb
Host smart-8ccacfd3-0ccc-455f-97b5-a576a9487a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51030
0820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.510300820
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.461923426
Short name T301
Test name
Test status
Simulation time 8386852991 ps
CPU time 7.59 seconds
Started Mar 26 02:52:14 PM PDT 24
Finished Mar 26 02:52:22 PM PDT 24
Peak memory 203472 kb
Host smart-71b5fec1-da26-481c-9391-afe925b4e029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46192
3426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.461923426
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.3756065434
Short name T545
Test name
Test status
Simulation time 8355739220 ps
CPU time 9.5 seconds
Started Mar 26 02:52:46 PM PDT 24
Finished Mar 26 02:52:56 PM PDT 24
Peak memory 203456 kb
Host smart-98646471-6dbf-487d-8c98-524455ed585f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37560
65434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.3756065434
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.2158977694
Short name T818
Test name
Test status
Simulation time 8474465508 ps
CPU time 7.92 seconds
Started Mar 26 02:52:46 PM PDT 24
Finished Mar 26 02:52:55 PM PDT 24
Peak memory 203448 kb
Host smart-33d45eb0-e659-406a-b7cf-74a27b263816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21589
77694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.2158977694
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.1890033392
Short name T419
Test name
Test status
Simulation time 8372414459 ps
CPU time 7.38 seconds
Started Mar 26 02:52:12 PM PDT 24
Finished Mar 26 02:52:19 PM PDT 24
Peak memory 203460 kb
Host smart-f9fc8032-95b8-4a97-9375-c24050f63ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18900
33392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.1890033392
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_enable.2141447298
Short name T517
Test name
Test status
Simulation time 8370734064 ps
CPU time 7.56 seconds
Started Mar 26 02:53:03 PM PDT 24
Finished Mar 26 02:53:10 PM PDT 24
Peak memory 203448 kb
Host smart-dcaa9766-e904-4e49-9cc0-1ec33c375c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21414
47298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2141447298
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.4200876839
Short name T501
Test name
Test status
Simulation time 39475344 ps
CPU time 1.02 seconds
Started Mar 26 02:53:04 PM PDT 24
Finished Mar 26 02:53:05 PM PDT 24
Peak memory 203564 kb
Host smart-6640cf43-12ea-438e-879f-8c27928070c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42008
76839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.4200876839
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3542866846
Short name T164
Test name
Test status
Simulation time 8364225583 ps
CPU time 9 seconds
Started Mar 26 02:52:10 PM PDT 24
Finished Mar 26 02:52:19 PM PDT 24
Peak memory 203456 kb
Host smart-232c968b-9cbc-457f-87a6-78ba35d9b372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35428
66846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3542866846
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.2947458135
Short name T113
Test name
Test status
Simulation time 8447977236 ps
CPU time 7.62 seconds
Started Mar 26 02:52:12 PM PDT 24
Finished Mar 26 02:52:20 PM PDT 24
Peak memory 203428 kb
Host smart-fa418674-d7c0-49e5-9c66-d100269220d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29474
58135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2947458135
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.1754267669
Short name T217
Test name
Test status
Simulation time 8407389798 ps
CPU time 8.71 seconds
Started Mar 26 02:52:09 PM PDT 24
Finished Mar 26 02:52:18 PM PDT 24
Peak memory 203488 kb
Host smart-f3f6998a-04d8-45bc-bb62-50d91f4cb70d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17542
67669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.1754267669
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2053590261
Short name T499
Test name
Test status
Simulation time 8364204802 ps
CPU time 7.27 seconds
Started Mar 26 02:52:15 PM PDT 24
Finished Mar 26 02:52:22 PM PDT 24
Peak memory 203388 kb
Host smart-ca784721-eb51-482c-abf2-446157f2f588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20535
90261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2053590261
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2249054522
Short name T333
Test name
Test status
Simulation time 8371379393 ps
CPU time 6.86 seconds
Started Mar 26 02:52:12 PM PDT 24
Finished Mar 26 02:52:19 PM PDT 24
Peak memory 203476 kb
Host smart-05bd1cba-e412-496b-a20e-f77884cce127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22490
54522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2249054522
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.1250318521
Short name T847
Test name
Test status
Simulation time 8386927438 ps
CPU time 7.59 seconds
Started Mar 26 02:52:20 PM PDT 24
Finished Mar 26 02:52:27 PM PDT 24
Peak memory 203476 kb
Host smart-55105920-69ac-42ef-85d1-bb1dd2d214b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12503
18521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.1250318521
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2726876668
Short name T863
Test name
Test status
Simulation time 27135266 ps
CPU time 0.66 seconds
Started Mar 26 02:52:12 PM PDT 24
Finished Mar 26 02:52:13 PM PDT 24
Peak memory 203336 kb
Host smart-bf45d661-0d2f-4cee-b84c-d43a38b47f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27268
76668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2726876668
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.3990883693
Short name T457
Test name
Test status
Simulation time 8379054734 ps
CPU time 9.09 seconds
Started Mar 26 02:52:11 PM PDT 24
Finished Mar 26 02:52:21 PM PDT 24
Peak memory 203448 kb
Host smart-1f63c9d1-2dcd-4425-a478-ac4fc31b2b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39908
83693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.3990883693
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.114128705
Short name T815
Test name
Test status
Simulation time 8418640906 ps
CPU time 9.07 seconds
Started Mar 26 02:52:46 PM PDT 24
Finished Mar 26 02:52:56 PM PDT 24
Peak memory 203464 kb
Host smart-3753c4ac-ff6b-4a5d-930f-9265f5c9cdef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11412
8705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.114128705
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.4070280263
Short name T466
Test name
Test status
Simulation time 8399186657 ps
CPU time 7.36 seconds
Started Mar 26 02:53:10 PM PDT 24
Finished Mar 26 02:53:17 PM PDT 24
Peak memory 203384 kb
Host smart-d12286a8-fbbe-411f-ab09-4b273c708acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40702
80263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.4070280263
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.3871143073
Short name T372
Test name
Test status
Simulation time 8363252920 ps
CPU time 8.05 seconds
Started Mar 26 02:53:15 PM PDT 24
Finished Mar 26 02:53:23 PM PDT 24
Peak memory 203456 kb
Host smart-aff97593-0ebf-4ef4-ae5a-60b7fe538df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38711
43073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3871143073
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2059575061
Short name T126
Test name
Test status
Simulation time 8472492483 ps
CPU time 9.44 seconds
Started Mar 26 02:52:23 PM PDT 24
Finished Mar 26 02:52:33 PM PDT 24
Peak memory 203404 kb
Host smart-fc541506-b4c9-4998-8f28-d4779f998ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20595
75061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2059575061
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.3707533063
Short name T336
Test name
Test status
Simulation time 8369031210 ps
CPU time 7.31 seconds
Started Mar 26 02:52:20 PM PDT 24
Finished Mar 26 02:52:28 PM PDT 24
Peak memory 203344 kb
Host smart-bdb4e59f-ea65-4ae8-987c-438481d64c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37075
33063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.3707533063
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_enable.1734665586
Short name T628
Test name
Test status
Simulation time 8367373482 ps
CPU time 6.8 seconds
Started Mar 26 02:52:21 PM PDT 24
Finished Mar 26 02:52:28 PM PDT 24
Peak memory 203444 kb
Host smart-ea947011-478d-49ea-baab-8355e9be78da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17346
65586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.1734665586
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1311981214
Short name T625
Test name
Test status
Simulation time 251770784 ps
CPU time 2.06 seconds
Started Mar 26 02:52:16 PM PDT 24
Finished Mar 26 02:52:18 PM PDT 24
Peak memory 203556 kb
Host smart-9cb04fa3-4a80-46b8-8823-206231d46b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13119
81214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1311981214
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.18631669
Short name T655
Test name
Test status
Simulation time 8361620348 ps
CPU time 8.98 seconds
Started Mar 26 02:52:19 PM PDT 24
Finished Mar 26 02:52:28 PM PDT 24
Peak memory 203400 kb
Host smart-158831c0-38b9-45a2-989a-6e334a682ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18631
669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.18631669
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3048091674
Short name T711
Test name
Test status
Simulation time 8449401797 ps
CPU time 8.24 seconds
Started Mar 26 02:52:16 PM PDT 24
Finished Mar 26 02:52:25 PM PDT 24
Peak memory 203424 kb
Host smart-da7d22be-b4da-48d1-807b-742e59dbc043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30480
91674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3048091674
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.2081189711
Short name T2
Test name
Test status
Simulation time 8416000847 ps
CPU time 7.53 seconds
Started Mar 26 02:52:11 PM PDT 24
Finished Mar 26 02:52:18 PM PDT 24
Peak memory 203472 kb
Host smart-677e87a2-1a98-4411-94a1-bb285d67190b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20811
89711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.2081189711
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.1890685111
Short name T293
Test name
Test status
Simulation time 8364742495 ps
CPU time 8.76 seconds
Started Mar 26 02:52:18 PM PDT 24
Finished Mar 26 02:52:27 PM PDT 24
Peak memory 203508 kb
Host smart-b90bea77-9d7a-468d-9e13-cce6d2566da0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18906
85111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.1890685111
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.2821037190
Short name T93
Test name
Test status
Simulation time 8391098116 ps
CPU time 7.45 seconds
Started Mar 26 02:52:27 PM PDT 24
Finished Mar 26 02:52:34 PM PDT 24
Peak memory 203472 kb
Host smart-34a36abc-b6ef-47e9-b44f-e6c259c521c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28210
37190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.2821037190
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.921620416
Short name T278
Test name
Test status
Simulation time 8399370542 ps
CPU time 6.87 seconds
Started Mar 26 02:52:13 PM PDT 24
Finished Mar 26 02:52:20 PM PDT 24
Peak memory 203496 kb
Host smart-21ca1e82-817d-4144-a22a-0df55579f81f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92162
0416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.921620416
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.735238127
Short name T356
Test name
Test status
Simulation time 8401885031 ps
CPU time 9.63 seconds
Started Mar 26 02:52:20 PM PDT 24
Finished Mar 26 02:52:30 PM PDT 24
Peak memory 203452 kb
Host smart-d30b7545-807d-4bcb-9b2a-1f5d70913364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73523
8127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.735238127
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.925815409
Short name T582
Test name
Test status
Simulation time 26603537 ps
CPU time 0.64 seconds
Started Mar 26 02:52:22 PM PDT 24
Finished Mar 26 02:52:23 PM PDT 24
Peak memory 203376 kb
Host smart-35f149f7-e29c-490d-af56-8767237c594b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92581
5409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.925815409
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.796043134
Short name T462
Test name
Test status
Simulation time 8371295920 ps
CPU time 9.09 seconds
Started Mar 26 02:52:20 PM PDT 24
Finished Mar 26 02:52:29 PM PDT 24
Peak memory 203456 kb
Host smart-73d9d694-94d8-406b-95f0-d373e5c35a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79604
3134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.796043134
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3962932355
Short name T116
Test name
Test status
Simulation time 8399849681 ps
CPU time 7.09 seconds
Started Mar 26 02:52:27 PM PDT 24
Finished Mar 26 02:52:34 PM PDT 24
Peak memory 203460 kb
Host smart-e74c0b32-542a-4891-9812-71f4317a3fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39629
32355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3962932355
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.596162506
Short name T799
Test name
Test status
Simulation time 8403515314 ps
CPU time 7 seconds
Started Mar 26 02:52:22 PM PDT 24
Finished Mar 26 02:52:29 PM PDT 24
Peak memory 203448 kb
Host smart-27fb7edc-de26-4d62-817b-ffdfd9183d75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59616
2506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.596162506
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.3905998703
Short name T480
Test name
Test status
Simulation time 8358279529 ps
CPU time 7.14 seconds
Started Mar 26 02:52:22 PM PDT 24
Finished Mar 26 02:52:29 PM PDT 24
Peak memory 203464 kb
Host smart-460f9f9e-fbae-4277-83ff-110d8def337a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39059
98703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.3905998703
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.3966387436
Short name T645
Test name
Test status
Simulation time 8474971186 ps
CPU time 6.98 seconds
Started Mar 26 02:52:17 PM PDT 24
Finished Mar 26 02:52:24 PM PDT 24
Peak memory 203516 kb
Host smart-481cc16d-b485-4006-ad82-21b781c031f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39663
87436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.3966387436
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.1927643805
Short name T686
Test name
Test status
Simulation time 8373204135 ps
CPU time 7.27 seconds
Started Mar 26 02:52:58 PM PDT 24
Finished Mar 26 02:53:06 PM PDT 24
Peak memory 203464 kb
Host smart-dabae5be-1786-4d40-9ace-e12fce492cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19276
43805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.1927643805
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_enable.42277042
Short name T713
Test name
Test status
Simulation time 8367145205 ps
CPU time 7.22 seconds
Started Mar 26 02:52:39 PM PDT 24
Finished Mar 26 02:52:47 PM PDT 24
Peak memory 203432 kb
Host smart-035ca3e5-ef7d-4984-837e-5a848d395ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42277
042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.42277042
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.2236417311
Short name T752
Test name
Test status
Simulation time 59951225 ps
CPU time 1.69 seconds
Started Mar 26 02:52:45 PM PDT 24
Finished Mar 26 02:52:47 PM PDT 24
Peak memory 203532 kb
Host smart-8d02aa13-a16e-4b26-9a9e-6424a78ad82c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22364
17311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.2236417311
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.1973137120
Short name T156
Test name
Test status
Simulation time 8357411626 ps
CPU time 8.85 seconds
Started Mar 26 02:52:23 PM PDT 24
Finished Mar 26 02:52:32 PM PDT 24
Peak memory 202020 kb
Host smart-e1969755-6420-4aa2-a3b5-027b9dcf9586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19731
37120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.1973137120
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.3583189940
Short name T228
Test name
Test status
Simulation time 8452228318 ps
CPU time 7.63 seconds
Started Mar 26 02:52:20 PM PDT 24
Finished Mar 26 02:52:28 PM PDT 24
Peak memory 203336 kb
Host smart-f193570d-222e-48b4-ba22-ba99731de665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35831
89940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3583189940
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.657346520
Short name T588
Test name
Test status
Simulation time 8412953966 ps
CPU time 7.08 seconds
Started Mar 26 02:52:20 PM PDT 24
Finished Mar 26 02:52:27 PM PDT 24
Peak memory 203456 kb
Host smart-60883455-207b-4833-9f26-4a864d6632f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65734
6520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.657346520
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.1551231733
Short name T570
Test name
Test status
Simulation time 8365122587 ps
CPU time 9.07 seconds
Started Mar 26 02:52:24 PM PDT 24
Finished Mar 26 02:52:33 PM PDT 24
Peak memory 203496 kb
Host smart-fba00b12-d378-48b4-9ff9-634ff5ecc679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15512
31733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.1551231733
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.3035597912
Short name T15
Test name
Test status
Simulation time 8391718144 ps
CPU time 7.5 seconds
Started Mar 26 02:52:23 PM PDT 24
Finished Mar 26 02:52:31 PM PDT 24
Peak memory 203368 kb
Host smart-d6ff230c-b26b-451e-bb54-81b2754a5469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30355
97912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.3035597912
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.1894545389
Short name T551
Test name
Test status
Simulation time 8371522311 ps
CPU time 9 seconds
Started Mar 26 02:52:23 PM PDT 24
Finished Mar 26 02:52:33 PM PDT 24
Peak memory 203208 kb
Host smart-67b4353b-1257-47bb-a88a-946807b4a48e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18945
45389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.1894545389
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.845440145
Short name T757
Test name
Test status
Simulation time 8385012348 ps
CPU time 7.23 seconds
Started Mar 26 02:52:49 PM PDT 24
Finished Mar 26 02:52:57 PM PDT 24
Peak memory 203468 kb
Host smart-4cea94a1-8c80-4cac-9d20-e6de80b47ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84544
0145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.845440145
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.1311021513
Short name T678
Test name
Test status
Simulation time 32793514 ps
CPU time 0.68 seconds
Started Mar 26 02:52:47 PM PDT 24
Finished Mar 26 02:52:48 PM PDT 24
Peak memory 203536 kb
Host smart-69a9c404-c240-4edb-b6d7-4982b6064bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13110
21513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1311021513
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.3129358768
Short name T352
Test name
Test status
Simulation time 8396675602 ps
CPU time 8.58 seconds
Started Mar 26 02:52:51 PM PDT 24
Finished Mar 26 02:53:00 PM PDT 24
Peak memory 203384 kb
Host smart-8953b41f-79bf-4d09-8773-06a37b6a5996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31293
58768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.3129358768
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.2156181093
Short name T436
Test name
Test status
Simulation time 8432108950 ps
CPU time 7.23 seconds
Started Mar 26 02:52:20 PM PDT 24
Finished Mar 26 02:52:27 PM PDT 24
Peak memory 203452 kb
Host smart-34538d40-af82-479b-a01c-db3373ecb36e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21561
81093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.2156181093
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.6588807
Short name T334
Test name
Test status
Simulation time 8379628890 ps
CPU time 7.96 seconds
Started Mar 26 02:52:17 PM PDT 24
Finished Mar 26 02:52:25 PM PDT 24
Peak memory 203480 kb
Host smart-41bbdaad-e08d-42f3-aa44-669d6ab05bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65888
07 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.6588807
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2186576392
Short name T469
Test name
Test status
Simulation time 8356342832 ps
CPU time 8.59 seconds
Started Mar 26 02:52:54 PM PDT 24
Finished Mar 26 02:53:03 PM PDT 24
Peak memory 203480 kb
Host smart-6e36267b-d653-48fc-b978-b8df1215b6bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21865
76392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2186576392
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.3017962407
Short name T76
Test name
Test status
Simulation time 8477490069 ps
CPU time 7.79 seconds
Started Mar 26 02:52:23 PM PDT 24
Finished Mar 26 02:52:31 PM PDT 24
Peak memory 203272 kb
Host smart-9ac94782-c848-4c30-b354-e053bd587638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30179
62407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.3017962407
Directory /workspace/9.usbdev_smoke/latest
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