Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3364	1		T1	4		T2	4		T3	3
all_values[1]	3364	1		T1	4		T2	4		T3	3
all_values[2]	3364	1		T1	4		T2	4		T3	3
all_values[3]	3364	1		T1	4		T2	4		T3	3
all_values[4]	3364	1		T1	4		T2	4		T3	3
all_values[5]	3364	1		T1	4		T2	4		T3	3
all_values[6]	3364	1		T1	4		T2	4		T3	3
all_values[7]	3364	1		T1	4		T2	4		T3	3
all_values[8]	3364	1		T1	4		T2	4		T3	3
all_values[9]	3364	1		T1	4		T2	4		T3	3
all_values[10]	3364	1		T1	4		T2	4		T3	3
all_values[11]	3364	1		T1	4		T2	4		T3	3
all_values[12]	3364	1		T1	4		T2	4		T3	3
all_values[13]	3364	1		T1	4		T2	4		T3	3
all_values[14]	3364	1		T1	4		T2	4		T3	3
all_values[15]	3364	1		T1	4		T2	4		T3	3
all_values[16]	3364	1		T1	4		T2	4		T3	3
all_values[17]	3364	1		T1	4		T2	4		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	57428	1		T1	72		T2	68		T3	54
auto[1]	3124	1		T2	4		T21	3		T22	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	56975	1		T1	72		T2	72		T3	54
auto[1]	3577	1		T72	115		T76	76		T74	131

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2455	1		T1	4		T3	3		T17	2
all_values[0]	auto[0]	auto[1]	96	1		T72	2		T74	5		T77	8
all_values[0]	auto[1]	auto[0]	712	1		T2	4		T22	3		T44	4
all_values[0]	auto[1]	auto[1]	101	1		T72	3		T76	3		T74	3
all_values[1]	auto[0]	auto[0]	2852	1		T1	4		T2	4		T3	3
all_values[1]	auto[0]	auto[1]	100	1		T72	3		T76	3		T74	7
all_values[1]	auto[1]	auto[0]	327	1		T21	3		T39	3		T40	3
all_values[1]	auto[1]	auto[1]	85	1		T76	1		T74	1		T77	1
all_values[2]	auto[0]	auto[0]	3147	1		T1	4		T2	4		T3	3
all_values[2]	auto[0]	auto[1]	88	1		T72	2		T74	2		T77	3
all_values[2]	auto[1]	auto[0]	11	1		T72	1		T276	1		T277	1
all_values[2]	auto[1]	auto[1]	118	1		T72	5		T76	5		T74	5
all_values[3]	auto[0]	auto[0]	3160	1		T1	4		T2	4		T3	3
all_values[3]	auto[0]	auto[1]	92	1		T72	4		T74	1		T75	4
all_values[3]	auto[1]	auto[0]	20	1		T72	2		T76	1		T74	2
all_values[3]	auto[1]	auto[1]	92	1		T72	2		T74	4		T75	1
all_values[4]	auto[0]	auto[0]	3138	1		T1	4		T2	4		T3	3
all_values[4]	auto[0]	auto[1]	97	1		T72	2		T76	1		T74	3
all_values[4]	auto[1]	auto[0]	10	1		T278	1		T276	1		T279	1
all_values[4]	auto[1]	auto[1]	119	1		T72	5		T76	4		T74	5
all_values[5]	auto[0]	auto[0]	3154	1		T1	4		T2	4		T3	3
all_values[5]	auto[0]	auto[1]	97	1		T72	3		T76	4		T74	2
all_values[5]	auto[1]	auto[0]	23	1		T72	2		T77	1		T278	4
all_values[5]	auto[1]	auto[1]	90	1		T72	2		T76	1		T74	6
all_values[6]	auto[0]	auto[0]	3140	1		T1	4		T2	4		T3	3
all_values[6]	auto[0]	auto[1]	100	1		T72	4		T76	3		T74	6
all_values[6]	auto[1]	auto[0]	18	1		T75	5		T77	1		T78	1
all_values[6]	auto[1]	auto[1]	106	1		T72	3		T76	1		T74	2
all_values[7]	auto[0]	auto[0]	3146	1		T1	4		T2	4		T3	3
all_values[7]	auto[0]	auto[1]	122	1		T72	5		T76	5		T74	6
all_values[7]	auto[1]	auto[0]	12	1		T72	1		T280	2		T281	2
all_values[7]	auto[1]	auto[1]	84	1		T72	1		T74	2		T75	4
all_values[8]	auto[0]	auto[0]	3141	1		T1	4		T2	4		T3	3
all_values[8]	auto[0]	auto[1]	89	1		T72	4		T76	3		T74	4
all_values[8]	auto[1]	auto[0]	15	1		T76	1		T75	1		T77	2
all_values[8]	auto[1]	auto[1]	119	1		T72	4		T76	1		T74	4
all_values[9]	auto[0]	auto[0]	3143	1		T1	4		T2	4		T3	3
all_values[9]	auto[0]	auto[1]	101	1		T72	7		T76	3		T74	5
all_values[9]	auto[1]	auto[0]	19	1		T278	1		T281	1		T279	1
all_values[9]	auto[1]	auto[1]	101	1		T72	1		T76	1		T74	3
all_values[10]	auto[0]	auto[0]	3149	1		T1	4		T2	4		T3	3
all_values[10]	auto[0]	auto[1]	86	1		T72	5		T76	1		T74	3
all_values[10]	auto[1]	auto[0]	18	1		T76	1		T74	1		T77	1
all_values[10]	auto[1]	auto[1]	111	1		T72	1		T76	3		T74	4
all_values[11]	auto[0]	auto[0]	3158	1		T1	4		T2	4		T3	3
all_values[11]	auto[0]	auto[1]	85	1		T72	2		T74	2		T75	4
all_values[11]	auto[1]	auto[0]	21	1		T72	2		T74	2		T278	1
all_values[11]	auto[1]	auto[1]	100	1		T72	4		T76	5		T74	4
all_values[12]	auto[0]	auto[0]	3143	1		T1	4		T2	4		T3	3
all_values[12]	auto[0]	auto[1]	109	1		T72	6		T76	4		T75	5
all_values[12]	auto[1]	auto[0]	16	1		T74	1		T77	1		T276	1
all_values[12]	auto[1]	auto[1]	96	1		T72	1		T76	1		T74	7
all_values[13]	auto[0]	auto[0]	3146	1		T1	4		T2	4		T3	3
all_values[13]	auto[0]	auto[1]	97	1		T72	4		T74	2		T75	3
all_values[13]	auto[1]	auto[0]	33	1		T72	1		T76	1		T74	1
all_values[13]	auto[1]	auto[1]	88	1		T72	3		T76	3		T74	5
all_values[14]	auto[0]	auto[0]	3144	1		T1	4		T2	4		T3	3
all_values[14]	auto[0]	auto[1]	104	1		T72	4		T76	4		T74	2
all_values[14]	auto[1]	auto[0]	12	1		T74	2		T77	1		T78	1
all_values[14]	auto[1]	auto[1]	104	1		T72	4		T76	1		T74	4
all_values[15]	auto[0]	auto[0]	3141	1		T1	4		T2	4		T3	3
all_values[15]	auto[0]	auto[1]	115	1		T72	3		T76	5		T74	4
all_values[15]	auto[1]	auto[0]	16	1		T72	3		T74	1		T278	2
all_values[15]	auto[1]	auto[1]	92	1		T72	2		T74	2		T75	5
all_values[16]	auto[0]	auto[0]	3146	1		T1	4		T2	4		T3	3
all_values[16]	auto[0]	auto[1]	110	1		T72	2		T76	3		T74	6
all_values[16]	auto[1]	auto[0]	19	1		T275	3		T278	1		T276	1
all_values[16]	auto[1]	auto[1]	89	1		T72	6		T76	2		T74	2
all_values[17]	auto[0]	auto[0]	3152	1		T1	4		T2	4		T3	3
all_values[17]	auto[0]	auto[1]	85	1		T72	3		T76	1		T74	5
all_values[17]	auto[1]	auto[0]	18	1		T72	1		T278	1		T280	1
all_values[17]	auto[1]	auto[1]	109	1		T72	3		T76	4		T74	3