Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3364	1		T1	4		T2	4		T3	3
all_pins[1]	3364	1		T1	4		T2	4		T3	3
all_pins[2]	3364	1		T1	4		T2	4		T3	3
all_pins[3]	3364	1		T1	4		T2	4		T3	3
all_pins[4]	3364	1		T1	4		T2	4		T3	3
all_pins[5]	3364	1		T1	4		T2	4		T3	3
all_pins[6]	3364	1		T1	4		T2	4		T3	3
all_pins[7]	3364	1		T1	4		T2	4		T3	3
all_pins[8]	3364	1		T1	4		T2	4		T3	3
all_pins[9]	3364	1		T1	4		T2	4		T3	3
all_pins[10]	3364	1		T1	4		T2	4		T3	3
all_pins[11]	3364	1		T1	4		T2	4		T3	3
all_pins[12]	3364	1		T1	4		T2	4		T3	3
all_pins[13]	3364	1		T1	4		T2	4		T3	3
all_pins[14]	3364	1		T1	4		T2	4		T3	3
all_pins[15]	3364	1		T1	4		T2	4		T3	3
all_pins[16]	3364	1		T1	4		T2	4		T3	3
all_pins[17]	3364	1		T1	4		T2	4		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	59533	1		T1	72		T2	71		T3	54
values[0x1]	1019	1		T2	1		T21	1		T44	1
transitions[0x0=>0x1]	802	1		T2	1		T21	1		T44	1
transitions[0x1=>0x0]	812	1		T2	1		T21	1		T44	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3226	1		T1	4		T2	3		T3	3
all_pins[0]	values[0x1]	138	1		T2	1		T44	1		T92	1
all_pins[0]	transitions[0x0=>0x1]	129	1		T2	1		T44	1		T92	1
all_pins[0]	transitions[0x1=>0x0]	125	1		T21	1		T39	1		T40	1
all_pins[1]	values[0x0]	3230	1		T1	4		T2	4		T3	3
all_pins[1]	values[0x1]	134	1		T21	1		T39	1		T40	1
all_pins[1]	transitions[0x0=>0x1]	120	1		T21	1		T39	1		T40	1
all_pins[1]	transitions[0x1=>0x0]	49	1		T76	1		T74	4		T75	1
all_pins[2]	values[0x0]	3301	1		T1	4		T2	4		T3	3
all_pins[2]	values[0x1]	63	1		T76	1		T74	4		T75	1
all_pins[2]	transitions[0x0=>0x1]	43	1		T76	1		T74	1		T75	1
all_pins[2]	transitions[0x1=>0x0]	22	1		T72	1		T77	1		T78	1
all_pins[3]	values[0x0]	3322	1		T1	4		T2	4		T3	3
all_pins[3]	values[0x1]	42	1		T72	1		T74	3		T77	3
all_pins[3]	transitions[0x0=>0x1]	29	1		T74	3		T77	1		T78	2
all_pins[3]	transitions[0x1=>0x0]	40	1		T72	2		T76	2		T74	2
all_pins[4]	values[0x0]	3311	1		T1	4		T2	4		T3	3
all_pins[4]	values[0x1]	53	1		T72	3		T76	2		T74	2
all_pins[4]	transitions[0x0=>0x1]	48	1		T72	3		T76	2		T74	1
all_pins[4]	transitions[0x1=>0x0]	30	1		T75	2		T77	1		T78	2
all_pins[5]	values[0x0]	3329	1		T1	4		T2	4		T3	3
all_pins[5]	values[0x1]	35	1		T74	1		T75	2		T77	1
all_pins[5]	transitions[0x0=>0x1]	30	1		T74	1		T75	2		T77	1
all_pins[5]	transitions[0x1=>0x0]	41	1		T76	1		T77	1		T78	1
all_pins[6]	values[0x0]	3318	1		T1	4		T2	4		T3	3
all_pins[6]	values[0x1]	46	1		T76	1		T77	1		T78	1
all_pins[6]	transitions[0x0=>0x1]	37	1		T76	1		T77	1		T78	1
all_pins[6]	transitions[0x1=>0x0]	24	1		T74	2		T75	1		T77	2
all_pins[7]	values[0x0]	3331	1		T1	4		T2	4		T3	3
all_pins[7]	values[0x1]	33	1		T74	2		T75	1		T77	2
all_pins[7]	transitions[0x0=>0x1]	24	1		T74	2		T75	1		T77	2
all_pins[7]	transitions[0x1=>0x0]	37	1		T72	1		T76	1		T74	2
all_pins[8]	values[0x0]	3318	1		T1	4		T2	4		T3	3
all_pins[8]	values[0x1]	46	1		T72	1		T76	1		T74	2
all_pins[8]	transitions[0x0=>0x1]	37	1		T72	1		T76	1		T74	2
all_pins[8]	transitions[0x1=>0x0]	39	1		T72	1		T74	1		T77	6
all_pins[9]	values[0x0]	3316	1		T1	4		T2	4		T3	3
all_pins[9]	values[0x1]	48	1		T72	1		T74	1		T77	6
all_pins[9]	transitions[0x0=>0x1]	27	1		T77	5		T78	1		T276	3
all_pins[9]	transitions[0x1=>0x0]	34	1		T76	2		T74	2		T75	2
all_pins[10]	values[0x0]	3309	1		T1	4		T2	4		T3	3
all_pins[10]	values[0x1]	55	1		T72	1		T76	2		T74	3
all_pins[10]	transitions[0x0=>0x1]	42	1		T72	1		T75	2		T77	1
all_pins[10]	transitions[0x1=>0x0]	42	1		T72	3		T76	2		T75	1
all_pins[11]	values[0x0]	3309	1		T1	4		T2	4		T3	3
all_pins[11]	values[0x1]	55	1		T72	3		T76	4		T74	3
all_pins[11]	transitions[0x0=>0x1]	37	1		T72	3		T76	3		T75	1
all_pins[11]	transitions[0x1=>0x0]	46	1		T72	1		T77	2		T275	2
all_pins[12]	values[0x0]	3300	1		T1	4		T2	4		T3	3
all_pins[12]	values[0x1]	64	1		T72	1		T76	1		T74	3
all_pins[12]	transitions[0x0=>0x1]	49	1		T76	1		T74	3		T77	2
all_pins[12]	transitions[0x1=>0x0]	24	1		T72	1		T75	1		T278	3
all_pins[13]	values[0x0]	3325	1		T1	4		T2	4		T3	3
all_pins[13]	values[0x1]	39	1		T72	2		T75	1		T278	3
all_pins[13]	transitions[0x0=>0x1]	29	1		T72	2		T75	1		T278	2
all_pins[13]	transitions[0x1=>0x0]	42	1		T72	1		T76	1		T77	3
all_pins[14]	values[0x0]	3312	1		T1	4		T2	4		T3	3
all_pins[14]	values[0x1]	52	1		T72	1		T76	1		T77	3
all_pins[14]	transitions[0x0=>0x1]	42	1		T72	1		T76	1		T77	2
all_pins[14]	transitions[0x1=>0x0]	27	1		T72	1		T74	2		T276	3
all_pins[15]	values[0x0]	3327	1		T1	4		T2	4		T3	3
all_pins[15]	values[0x1]	37	1		T72	1		T74	2		T77	1
all_pins[15]	transitions[0x0=>0x1]	29	1		T74	2		T275	2		T276	3
all_pins[15]	transitions[0x1=>0x0]	28	1		T72	2		T76	1		T74	2
all_pins[16]	values[0x0]	3328	1		T1	4		T2	4		T3	3
all_pins[16]	values[0x1]	36	1		T72	3		T76	1		T74	2
all_pins[16]	transitions[0x0=>0x1]	27	1		T72	3		T74	2		T77	3
all_pins[16]	transitions[0x1=>0x0]	34	1		T72	1		T275	1		T78	1
all_pins[17]	values[0x0]	3321	1		T1	4		T2	4		T3	3
all_pins[17]	values[0x1]	43	1		T72	1		T76	1		T77	1
all_pins[17]	transitions[0x0=>0x1]	23	1		T72	1		T78	2		T277	1
all_pins[17]	transitions[0x1=>0x0]	128	1		T2	1		T44	1		T92	1