Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	198	1		T72	7		T76	4		T74	7
all_values[1]	198	1		T72	7		T76	4		T74	7
all_values[2]	198	1		T72	7		T76	4		T74	7
all_values[3]	198	1		T72	7		T76	4		T74	7
all_values[4]	198	1		T72	7		T76	4		T74	7
all_values[5]	198	1		T72	7		T76	4		T74	7
all_values[6]	198	1		T72	7		T76	4		T74	7
all_values[7]	198	1		T72	7		T76	4		T74	7
all_values[8]	198	1		T72	7		T76	4		T74	7
all_values[9]	198	1		T72	7		T76	4		T74	7
all_values[10]	198	1		T72	7		T76	4		T74	7
all_values[11]	198	1		T72	7		T76	4		T74	7
all_values[12]	198	1		T72	7		T76	4		T74	7
all_values[13]	198	1		T72	7		T76	4		T74	7
all_values[14]	198	1		T72	7		T76	4		T74	7
all_values[15]	198	1		T72	7		T76	4		T74	7
all_values[16]	198	1		T72	7		T76	4		T74	7
all_values[17]	198	1		T72	7		T76	4		T74	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1906	1		T72	75		T76	34		T74	64
auto[1]	1658	1		T72	51		T76	38		T74	62

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	601	1		T72	29		T76	13		T74	13
auto[1]	2963	1		T72	97		T76	59		T74	113

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2049	1		T72	75		T76	43		T74	66
auto[1]	1515	1		T72	51		T76	29		T74	60

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	31	1		T72	3		T75	4		T275	2
all_values[0]	auto[0]	auto[0]	auto[1]	44	1		T74	2		T77	4		T275	1
all_values[0]	auto[0]	auto[1]	auto[0]	5	1		T76	2		T282	1		T283	1
all_values[0]	auto[0]	auto[1]	auto[1]	39	1		T72	1		T76	1		T74	2
all_values[0]	auto[1]	auto[0]	auto[1]	49	1		T72	2		T76	1		T74	1
all_values[0]	auto[1]	auto[1]	auto[1]	30	1		T72	1		T74	2		T78	1
all_values[1]	auto[0]	auto[0]	auto[0]	28	1		T72	2		T75	1		T275	1
all_values[1]	auto[0]	auto[0]	auto[1]	44	1		T72	1		T76	1		T74	3
all_values[1]	auto[0]	auto[1]	auto[0]	18	1		T72	3		T76	1		T275	3
all_values[1]	auto[0]	auto[1]	auto[1]	39	1		T76	1		T77	1		T78	2
all_values[1]	auto[1]	auto[0]	auto[1]	38	1		T72	1		T74	4		T75	1
all_values[1]	auto[1]	auto[1]	auto[1]	31	1		T76	1		T278	1		T78	3
all_values[2]	auto[0]	auto[0]	auto[0]	18	1		T72	1		T74	1		T78	1
all_values[2]	auto[0]	auto[0]	auto[1]	26	1		T278	1		T78	1		T281	2
all_values[2]	auto[0]	auto[1]	auto[0]	8	1		T276	1		T277	1		T282	3
all_values[2]	auto[0]	auto[1]	auto[1]	54	1		T72	2		T76	2		T74	1
all_values[2]	auto[1]	auto[0]	auto[1]	56	1		T72	2		T74	3		T75	1
all_values[2]	auto[1]	auto[1]	auto[1]	36	1		T72	2		T76	2		T74	2
all_values[3]	auto[0]	auto[0]	auto[0]	29	1		T72	1		T76	3		T74	2
all_values[3]	auto[0]	auto[0]	auto[1]	34	1		T72	3		T75	1		T278	1
all_values[3]	auto[0]	auto[1]	auto[0]	17	1		T72	1		T76	1		T74	1
all_values[3]	auto[0]	auto[1]	auto[1]	37	1		T72	1		T74	1		T77	2
all_values[3]	auto[1]	auto[0]	auto[1]	47	1		T74	2		T75	2		T275	1
all_values[3]	auto[1]	auto[1]	auto[1]	34	1		T72	1		T74	1		T75	1
all_values[4]	auto[0]	auto[0]	auto[0]	10	1		T72	1		T277	1		T281	1
all_values[4]	auto[0]	auto[0]	auto[1]	32	1		T72	1		T75	1		T278	1
all_values[4]	auto[0]	auto[1]	auto[0]	8	1		T278	1		T276	1		T283	2
all_values[4]	auto[0]	auto[1]	auto[1]	44	1		T72	1		T76	1		T74	1
all_values[4]	auto[1]	auto[0]	auto[1]	55	1		T72	1		T76	1		T74	2
all_values[4]	auto[1]	auto[1]	auto[1]	49	1		T72	3		T76	2		T74	4
all_values[5]	auto[0]	auto[0]	auto[0]	29	1		T72	1		T278	2		T276	1
all_values[5]	auto[0]	auto[0]	auto[1]	36	1		T72	1		T76	2		T74	1
all_values[5]	auto[0]	auto[1]	auto[0]	14	1		T72	2		T77	1		T278	2
all_values[5]	auto[0]	auto[1]	auto[1]	34	1		T74	2		T75	1		T77	2
all_values[5]	auto[1]	auto[0]	auto[1]	50	1		T72	1		T76	1		T74	1
all_values[5]	auto[1]	auto[1]	auto[1]	35	1		T72	2		T76	1		T74	3
all_values[6]	auto[0]	auto[0]	auto[0]	15	1		T72	1		T76	1		T75	1
all_values[6]	auto[0]	auto[0]	auto[1]	38	1		T72	2		T76	1		T74	3
all_values[6]	auto[0]	auto[1]	auto[0]	11	1		T75	3		T77	1		T78	1
all_values[6]	auto[0]	auto[1]	auto[1]	46	1		T72	2		T74	3		T77	3
all_values[6]	auto[1]	auto[0]	auto[1]	49	1		T72	2		T76	1		T74	1
all_values[6]	auto[1]	auto[1]	auto[1]	39	1		T76	1		T77	1		T78	3
all_values[7]	auto[0]	auto[0]	auto[0]	16	1		T72	1		T276	1		T280	2
all_values[7]	auto[0]	auto[0]	auto[1]	49	1		T72	3		T76	1		T74	3
all_values[7]	auto[0]	auto[1]	auto[0]	11	1		T72	1		T280	2		T281	2
all_values[7]	auto[0]	auto[1]	auto[1]	35	1		T72	1		T75	2		T77	1
all_values[7]	auto[1]	auto[0]	auto[1]	53	1		T72	1		T76	3		T74	3
all_values[7]	auto[1]	auto[1]	auto[1]	34	1		T74	1		T77	2		T278	1
all_values[8]	auto[0]	auto[0]	auto[0]	17	1		T75	2		T77	2		T275	1
all_values[8]	auto[0]	auto[0]	auto[1]	38	1		T72	3		T76	1		T74	1
all_values[8]	auto[0]	auto[1]	auto[0]	8	1		T76	1		T77	1		T283	1
all_values[8]	auto[0]	auto[1]	auto[1]	54	1		T72	2		T74	2		T75	1
all_values[8]	auto[1]	auto[0]	auto[1]	42	1		T72	2		T74	3		T77	2
all_values[8]	auto[1]	auto[1]	auto[1]	39	1		T76	2		T74	1		T75	1
all_values[9]	auto[0]	auto[0]	auto[0]	18	1		T76	1		T75	1		T275	1
all_values[9]	auto[0]	auto[0]	auto[1]	44	1		T72	2		T76	1		T74	1
all_values[9]	auto[0]	auto[1]	auto[0]	12	1		T278	1		T284	1		T285	1
all_values[9]	auto[0]	auto[1]	auto[1]	40	1		T76	1		T74	1		T75	2
all_values[9]	auto[1]	auto[0]	auto[1]	47	1		T72	4		T76	1		T74	4
all_values[9]	auto[1]	auto[1]	auto[1]	37	1		T72	1		T74	1		T75	1
all_values[10]	auto[0]	auto[0]	auto[0]	19	1		T72	2		T75	2		T275	1
all_values[10]	auto[0]	auto[0]	auto[1]	36	1		T72	1		T74	2		T77	2
all_values[10]	auto[0]	auto[1]	auto[0]	16	1		T76	1		T74	1		T77	2
all_values[10]	auto[0]	auto[1]	auto[1]	41	1		T76	1		T74	2		T75	1
all_values[10]	auto[1]	auto[0]	auto[1]	43	1		T72	3		T76	1		T74	1
all_values[10]	auto[1]	auto[1]	auto[1]	43	1		T72	1		T76	1		T74	1
all_values[11]	auto[0]	auto[0]	auto[0]	36	1		T72	1		T278	1		T280	5
all_values[11]	auto[0]	auto[0]	auto[1]	34	1		T72	1		T75	1		T77	3
all_values[11]	auto[0]	auto[1]	auto[0]	10	1		T72	1		T74	2		T278	1
all_values[11]	auto[0]	auto[1]	auto[1]	31	1		T72	1		T76	2		T74	2
all_values[11]	auto[1]	auto[0]	auto[1]	41	1		T72	1		T74	2		T75	2
all_values[11]	auto[1]	auto[1]	auto[1]	46	1		T72	2		T76	2		T74	1
all_values[12]	auto[0]	auto[0]	auto[0]	19	1		T72	1		T278	1		T276	1
all_values[12]	auto[0]	auto[0]	auto[1]	41	1		T72	4		T76	2		T75	1
all_values[12]	auto[0]	auto[1]	auto[0]	9	1		T74	1		T77	1		T276	1
all_values[12]	auto[0]	auto[1]	auto[1]	36	1		T76	1		T74	3		T77	1
all_values[12]	auto[1]	auto[0]	auto[1]	43	1		T72	1		T75	3		T77	2
all_values[12]	auto[1]	auto[1]	auto[1]	50	1		T72	1		T76	1		T74	3
all_values[13]	auto[0]	auto[0]	auto[0]	24	1		T72	1		T76	2		T75	1
all_values[13]	auto[0]	auto[0]	auto[1]	41	1		T72	2		T74	1		T75	1
all_values[13]	auto[0]	auto[1]	auto[0]	23	1		T74	1		T77	1		T276	1
all_values[13]	auto[0]	auto[1]	auto[1]	36	1		T72	1		T76	1		T74	3
all_values[13]	auto[1]	auto[0]	auto[1]	41	1		T72	1		T74	1		T75	1
all_values[13]	auto[1]	auto[1]	auto[1]	33	1		T72	2		T76	1		T74	1
all_values[14]	auto[0]	auto[0]	auto[0]	14	1		T278	1		T277	1		T281	4
all_values[14]	auto[0]	auto[0]	auto[1]	41	1		T72	1		T76	2		T74	2
all_values[14]	auto[0]	auto[1]	auto[0]	11	1		T74	2		T77	1		T78	2
all_values[14]	auto[0]	auto[1]	auto[1]	44	1		T72	1		T76	1		T74	2
all_values[14]	auto[1]	auto[0]	auto[1]	45	1		T72	2		T76	1		T75	2
all_values[14]	auto[1]	auto[1]	auto[1]	43	1		T72	3		T74	1		T77	3
all_values[15]	auto[0]	auto[0]	auto[0]	10	1		T72	1		T278	1		T283	1
all_values[15]	auto[0]	auto[0]	auto[1]	49	1		T72	1		T76	3		T74	2
all_values[15]	auto[0]	auto[1]	auto[0]	16	1		T72	2		T74	2		T278	3
all_values[15]	auto[0]	auto[1]	auto[1]	40	1		T75	2		T275	1		T276	2
all_values[15]	auto[1]	auto[0]	auto[1]	56	1		T72	1		T76	1		T74	2
all_values[15]	auto[1]	auto[1]	auto[1]	27	1		T72	2		T74	1		T75	1
all_values[16]	auto[0]	auto[0]	auto[0]	16	1		T275	2		T276	1		T282	2
all_values[16]	auto[0]	auto[0]	auto[1]	46	1		T72	2		T76	1		T74	3
all_values[16]	auto[0]	auto[1]	auto[0]	16	1		T275	2		T278	1		T276	1
all_values[16]	auto[0]	auto[1]	auto[1]	43	1		T72	2		T76	1		T75	3
all_values[16]	auto[1]	auto[0]	auto[1]	38	1		T72	1		T74	1		T75	1
all_values[16]	auto[1]	auto[1]	auto[1]	39	1		T72	2		T76	2		T74	3
all_values[17]	auto[0]	auto[0]	auto[0]	26	1		T72	2		T75	2		T277	2
all_values[17]	auto[0]	auto[0]	auto[1]	33	1		T72	1		T76	1		T74	3
all_values[17]	auto[0]	auto[1]	auto[0]	13	1		T278	1		T280	1		T286	4
all_values[17]	auto[0]	auto[1]	auto[1]	49	1		T72	2		T76	1		T74	1
all_values[17]	auto[1]	auto[0]	auto[1]	32	1		T72	1		T74	3		T75	1
all_values[17]	auto[1]	auto[1]	auto[1]	45	1		T72	1		T76	2		T77	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal