Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.75 96.43 89.11 97.62 50.00 94.13 97.36 96.58


Total test records in report: 1153
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T1069 /workspace/coverage/default/11.usbdev_enable.4168082606 Mar 28 01:33:21 PM PDT 24 Mar 28 01:33:32 PM PDT 24 8369738557 ps
T1070 /workspace/coverage/default/46.usbdev_fifo_rst.2583389770 Mar 28 01:35:47 PM PDT 24 Mar 28 01:35:49 PM PDT 24 160578449 ps
T68 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2773910769 Mar 28 12:30:37 PM PDT 24 Mar 28 12:30:39 PM PDT 24 57849249 ps
T60 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.900534260 Mar 28 12:30:54 PM PDT 24 Mar 28 12:30:59 PM PDT 24 478938459 ps
T1071 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3846925035 Mar 28 12:30:48 PM PDT 24 Mar 28 12:30:50 PM PDT 24 84431150 ps
T73 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2627996840 Mar 28 12:30:58 PM PDT 24 Mar 28 12:31:00 PM PDT 24 150612198 ps
T72 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.4103451222 Mar 28 12:31:18 PM PDT 24 Mar 28 12:31:19 PM PDT 24 23622735 ps
T76 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2929675815 Mar 28 12:31:18 PM PDT 24 Mar 28 12:31:19 PM PDT 24 22713235 ps
T61 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.4167429170 Mar 28 12:31:12 PM PDT 24 Mar 28 12:31:15 PM PDT 24 138639684 ps
T105 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.951104731 Mar 28 12:31:18 PM PDT 24 Mar 28 12:31:21 PM PDT 24 148664357 ps
T69 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1062945574 Mar 28 12:31:00 PM PDT 24 Mar 28 12:31:02 PM PDT 24 34557790 ps
T66 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2413968128 Mar 28 12:30:56 PM PDT 24 Mar 28 12:30:57 PM PDT 24 30560251 ps
T106 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2159124044 Mar 28 12:30:47 PM PDT 24 Mar 28 12:30:48 PM PDT 24 77642041 ps
T74 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2020379164 Mar 28 12:31:25 PM PDT 24 Mar 28 12:31:27 PM PDT 24 26131621 ps
T107 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2854744339 Mar 28 12:31:21 PM PDT 24 Mar 28 12:31:22 PM PDT 24 37820079 ps
T75 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.37944491 Mar 28 12:31:31 PM PDT 24 Mar 28 12:31:32 PM PDT 24 25914809 ps
T62 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3246279983 Mar 28 12:31:22 PM PDT 24 Mar 28 12:31:25 PM PDT 24 326212069 ps
T108 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3043691631 Mar 28 12:31:29 PM PDT 24 Mar 28 12:31:30 PM PDT 24 25589191 ps
T77 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.2628011325 Mar 28 12:31:21 PM PDT 24 Mar 28 12:31:21 PM PDT 24 31217726 ps
T109 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.529198037 Mar 28 12:31:11 PM PDT 24 Mar 28 12:31:12 PM PDT 24 33348749 ps
T257 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2248151014 Mar 28 12:31:28 PM PDT 24 Mar 28 12:31:29 PM PDT 24 32266021 ps
T1072 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.669311715 Mar 28 12:31:00 PM PDT 24 Mar 28 12:31:03 PM PDT 24 246554551 ps
T228 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3052038268 Mar 28 12:31:29 PM PDT 24 Mar 28 12:31:30 PM PDT 24 71361071 ps
T275 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1363412566 Mar 28 12:31:20 PM PDT 24 Mar 28 12:31:21 PM PDT 24 27308052 ps
T267 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2129154748 Mar 28 12:31:20 PM PDT 24 Mar 28 12:31:21 PM PDT 24 61227165 ps
T268 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3265862160 Mar 28 12:31:28 PM PDT 24 Mar 28 12:31:29 PM PDT 24 113998178 ps
T278 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.4231990567 Mar 28 12:31:21 PM PDT 24 Mar 28 12:31:22 PM PDT 24 30016692 ps
T230 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2319927607 Mar 28 12:31:30 PM PDT 24 Mar 28 12:31:32 PM PDT 24 253937216 ps
T231 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2879844101 Mar 28 12:31:19 PM PDT 24 Mar 28 12:31:23 PM PDT 24 498284471 ps
T78 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2065662823 Mar 28 12:31:31 PM PDT 24 Mar 28 12:31:32 PM PDT 24 28157029 ps
T258 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2333080289 Mar 28 12:30:55 PM PDT 24 Mar 28 12:30:56 PM PDT 24 29128121 ps
T276 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3377715267 Mar 28 12:31:32 PM PDT 24 Mar 28 12:31:32 PM PDT 24 21371367 ps
T227 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2909222004 Mar 28 12:31:05 PM PDT 24 Mar 28 12:31:07 PM PDT 24 180573490 ps
T277 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.469366491 Mar 28 12:31:23 PM PDT 24 Mar 28 12:31:24 PM PDT 24 24114465 ps
T241 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1385032010 Mar 28 12:31:22 PM PDT 24 Mar 28 12:31:24 PM PDT 24 83310708 ps
T259 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2977975474 Mar 28 12:31:11 PM PDT 24 Mar 28 12:31:12 PM PDT 24 64441515 ps
T240 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.4111076929 Mar 28 12:31:21 PM PDT 24 Mar 28 12:31:24 PM PDT 24 217358620 ps
T280 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.21491793 Mar 28 12:31:16 PM PDT 24 Mar 28 12:31:16 PM PDT 24 20403314 ps
T244 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3541758756 Mar 28 12:31:25 PM PDT 24 Mar 28 12:31:28 PM PDT 24 234708055 ps
T245 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.866322289 Mar 28 12:30:45 PM PDT 24 Mar 28 12:30:48 PM PDT 24 141802304 ps
T260 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1937868832 Mar 28 12:31:03 PM PDT 24 Mar 28 12:31:05 PM PDT 24 89714732 ps
T261 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1309686380 Mar 28 12:30:45 PM PDT 24 Mar 28 12:30:49 PM PDT 24 371341692 ps
T246 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.377146544 Mar 28 12:30:43 PM PDT 24 Mar 28 12:30:45 PM PDT 24 39898486 ps
T1073 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1853042118 Mar 28 12:31:15 PM PDT 24 Mar 28 12:31:16 PM PDT 24 38087014 ps
T1074 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3748928658 Mar 28 12:30:45 PM PDT 24 Mar 28 12:30:47 PM PDT 24 83896853 ps
T1075 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2568171596 Mar 28 12:31:21 PM PDT 24 Mar 28 12:31:22 PM PDT 24 50932141 ps
T272 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3885863155 Mar 28 12:30:44 PM PDT 24 Mar 28 12:30:46 PM PDT 24 39805915 ps
T281 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1744416049 Mar 28 12:31:19 PM PDT 24 Mar 28 12:31:19 PM PDT 24 26147390 ps
T282 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.205212477 Mar 28 12:31:17 PM PDT 24 Mar 28 12:31:17 PM PDT 24 20550083 ps
T279 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1979332936 Mar 28 12:31:30 PM PDT 24 Mar 28 12:31:30 PM PDT 24 25749450 ps
T1076 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3738890190 Mar 28 12:31:18 PM PDT 24 Mar 28 12:31:19 PM PDT 24 21867270 ps
T248 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2806374160 Mar 28 12:30:47 PM PDT 24 Mar 28 12:30:50 PM PDT 24 238642939 ps
T262 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4195165999 Mar 28 12:31:16 PM PDT 24 Mar 28 12:31:17 PM PDT 24 43467974 ps
T284 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2186508766 Mar 28 12:31:24 PM PDT 24 Mar 28 12:31:25 PM PDT 24 22154084 ps
T1077 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4093998027 Mar 28 12:31:31 PM PDT 24 Mar 28 12:31:33 PM PDT 24 52756358 ps
T273 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1796573386 Mar 28 12:31:20 PM PDT 24 Mar 28 12:31:21 PM PDT 24 46039454 ps
T283 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1290965417 Mar 28 12:31:21 PM PDT 24 Mar 28 12:31:22 PM PDT 24 27774353 ps
T247 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1970878139 Mar 28 12:31:19 PM PDT 24 Mar 28 12:31:20 PM PDT 24 82175281 ps
T1078 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2087071675 Mar 28 12:31:22 PM PDT 24 Mar 28 12:31:23 PM PDT 24 59905477 ps
T1079 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3494300834 Mar 28 12:31:12 PM PDT 24 Mar 28 12:31:14 PM PDT 24 110251999 ps
T288 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2991093320 Mar 28 12:31:16 PM PDT 24 Mar 28 12:31:20 PM PDT 24 206363156 ps
T1080 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2801223179 Mar 28 12:31:09 PM PDT 24 Mar 28 12:31:10 PM PDT 24 23527012 ps
T287 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3128861572 Mar 28 12:31:08 PM PDT 24 Mar 28 12:31:12 PM PDT 24 448962925 ps
T274 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2754137075 Mar 28 12:31:22 PM PDT 24 Mar 28 12:31:24 PM PDT 24 138680444 ps
T285 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1407059523 Mar 28 12:30:48 PM PDT 24 Mar 28 12:30:50 PM PDT 24 31177859 ps
T286 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.508894392 Mar 28 12:31:23 PM PDT 24 Mar 28 12:31:23 PM PDT 24 28949157 ps
T242 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2502205997 Mar 28 12:31:28 PM PDT 24 Mar 28 12:31:29 PM PDT 24 53938082 ps
T1081 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2570947125 Mar 28 12:30:44 PM PDT 24 Mar 28 12:30:47 PM PDT 24 78402643 ps
T67 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.130428401 Mar 28 12:31:13 PM PDT 24 Mar 28 12:31:14 PM PDT 24 56152539 ps
T243 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.4080751319 Mar 28 12:31:21 PM PDT 24 Mar 28 12:31:24 PM PDT 24 173604995 ps
T263 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3314135895 Mar 28 12:31:16 PM PDT 24 Mar 28 12:31:17 PM PDT 24 59545939 ps
T1082 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2564460395 Mar 28 12:31:28 PM PDT 24 Mar 28 12:31:30 PM PDT 24 151960763 ps
T1083 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3294915409 Mar 28 12:31:24 PM PDT 24 Mar 28 12:31:26 PM PDT 24 151382579 ps
T1084 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.351831564 Mar 28 12:30:48 PM PDT 24 Mar 28 12:30:50 PM PDT 24 80303392 ps
T1085 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3659944665 Mar 28 12:31:16 PM PDT 24 Mar 28 12:31:18 PM PDT 24 52145687 ps
T1086 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1304821117 Mar 28 12:31:23 PM PDT 24 Mar 28 12:31:24 PM PDT 24 22826984 ps
T1087 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.525060670 Mar 28 12:31:22 PM PDT 24 Mar 28 12:31:23 PM PDT 24 77368078 ps
T1088 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3763035201 Mar 28 12:31:20 PM PDT 24 Mar 28 12:31:21 PM PDT 24 150239795 ps
T292 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1094016414 Mar 28 12:31:00 PM PDT 24 Mar 28 12:31:03 PM PDT 24 281455409 ps
T1089 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.719232661 Mar 28 12:31:21 PM PDT 24 Mar 28 12:31:22 PM PDT 24 30440772 ps
T264 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1925010218 Mar 28 12:31:20 PM PDT 24 Mar 28 12:31:23 PM PDT 24 108192129 ps
T290 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2336429937 Mar 28 12:31:06 PM PDT 24 Mar 28 12:31:09 PM PDT 24 299333697 ps
T1090 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3285190057 Mar 28 12:30:48 PM PDT 24 Mar 28 12:30:54 PM PDT 24 66339615 ps
T1091 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1121337742 Mar 28 12:31:28 PM PDT 24 Mar 28 12:31:30 PM PDT 24 114610318 ps
T289 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3990075461 Mar 28 12:31:11 PM PDT 24 Mar 28 12:31:14 PM PDT 24 216782033 ps
T1092 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1493935053 Mar 28 12:31:13 PM PDT 24 Mar 28 12:31:14 PM PDT 24 27140625 ps
T1093 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2747170017 Mar 28 12:31:21 PM PDT 24 Mar 28 12:31:23 PM PDT 24 38042121 ps
T1094 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3038087102 Mar 28 12:31:13 PM PDT 24 Mar 28 12:31:15 PM PDT 24 52703570 ps
T265 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.140795205 Mar 28 12:30:46 PM PDT 24 Mar 28 12:30:53 PM PDT 24 281410823 ps
T1095 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.473503387 Mar 28 12:31:21 PM PDT 24 Mar 28 12:31:22 PM PDT 24 28560620 ps
T1096 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3020043513 Mar 28 12:31:09 PM PDT 24 Mar 28 12:31:10 PM PDT 24 27880465 ps
T1097 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.453479173 Mar 28 12:31:14 PM PDT 24 Mar 28 12:31:15 PM PDT 24 25370186 ps
T1098 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4246348268 Mar 28 12:31:18 PM PDT 24 Mar 28 12:31:20 PM PDT 24 91878935 ps
T1099 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3272113842 Mar 28 12:31:19 PM PDT 24 Mar 28 12:31:23 PM PDT 24 102353435 ps
T1100 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.4101442562 Mar 28 12:31:22 PM PDT 24 Mar 28 12:31:23 PM PDT 24 21750285 ps
T266 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1913314320 Mar 28 12:31:00 PM PDT 24 Mar 28 12:31:07 PM PDT 24 275440910 ps
T1101 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3319198248 Mar 28 12:31:02 PM PDT 24 Mar 28 12:31:03 PM PDT 24 105382361 ps
T1102 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3822953374 Mar 28 12:31:28 PM PDT 24 Mar 28 12:31:30 PM PDT 24 146929968 ps
T1103 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.706262537 Mar 28 12:31:05 PM PDT 24 Mar 28 12:31:06 PM PDT 24 42176374 ps
T1104 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3932475385 Mar 28 12:31:13 PM PDT 24 Mar 28 12:31:14 PM PDT 24 95668244 ps
T1105 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2074719845 Mar 28 12:31:21 PM PDT 24 Mar 28 12:31:25 PM PDT 24 336623282 ps
T70 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.4162828504 Mar 28 12:30:49 PM PDT 24 Mar 28 12:30:51 PM PDT 24 55882970 ps
T1106 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2714964823 Mar 28 12:31:19 PM PDT 24 Mar 28 12:31:20 PM PDT 24 65183739 ps
T1107 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1942694181 Mar 28 12:31:29 PM PDT 24 Mar 28 12:31:30 PM PDT 24 25153063 ps
T1108 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3082784602 Mar 28 12:31:24 PM PDT 24 Mar 28 12:31:25 PM PDT 24 27334844 ps
T1109 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1510712798 Mar 28 12:31:09 PM PDT 24 Mar 28 12:31:10 PM PDT 24 40264318 ps
T1110 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2218580756 Mar 28 12:31:22 PM PDT 24 Mar 28 12:31:23 PM PDT 24 73542181 ps
T1111 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.171052699 Mar 28 12:31:23 PM PDT 24 Mar 28 12:31:24 PM PDT 24 33696979 ps
T1112 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3046841950 Mar 28 12:31:15 PM PDT 24 Mar 28 12:31:17 PM PDT 24 137933201 ps
T1113 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.713683508 Mar 28 12:31:21 PM PDT 24 Mar 28 12:31:24 PM PDT 24 257143656 ps
T1114 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3061298870 Mar 28 12:31:12 PM PDT 24 Mar 28 12:31:14 PM PDT 24 61388685 ps
T1115 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2342775993 Mar 28 12:31:28 PM PDT 24 Mar 28 12:31:31 PM PDT 24 222827527 ps
T1116 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1269825532 Mar 28 12:31:05 PM PDT 24 Mar 28 12:31:08 PM PDT 24 81762512 ps
T1117 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.783490886 Mar 28 12:31:22 PM PDT 24 Mar 28 12:31:23 PM PDT 24 25950083 ps
T1118 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1171592049 Mar 28 12:31:04 PM PDT 24 Mar 28 12:31:07 PM PDT 24 260839440 ps
T1119 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1764851166 Mar 28 12:30:45 PM PDT 24 Mar 28 12:30:58 PM PDT 24 78071371 ps
T1120 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2434959220 Mar 28 12:31:09 PM PDT 24 Mar 28 12:31:10 PM PDT 24 33647603 ps
T1121 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2168558098 Mar 28 12:31:28 PM PDT 24 Mar 28 12:31:28 PM PDT 24 26694129 ps
T1122 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.325532225 Mar 28 12:31:26 PM PDT 24 Mar 28 12:31:27 PM PDT 24 23162437 ps
T1123 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3197135542 Mar 28 12:31:23 PM PDT 24 Mar 28 12:31:25 PM PDT 24 51708604 ps
T1124 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2864660125 Mar 28 12:31:29 PM PDT 24 Mar 28 12:31:34 PM PDT 24 439747258 ps
T1125 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.660749135 Mar 28 12:31:22 PM PDT 24 Mar 28 12:31:23 PM PDT 24 50566820 ps
T291 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1681589091 Mar 28 12:31:20 PM PDT 24 Mar 28 12:31:25 PM PDT 24 467941511 ps
T1126 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.4043436188 Mar 28 12:31:20 PM PDT 24 Mar 28 12:31:22 PM PDT 24 52696226 ps
T1127 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.92469807 Mar 28 12:31:20 PM PDT 24 Mar 28 12:31:24 PM PDT 24 148690761 ps
T1128 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.814671564 Mar 28 12:31:23 PM PDT 24 Mar 28 12:31:23 PM PDT 24 21088706 ps
T1129 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2796422976 Mar 28 12:31:12 PM PDT 24 Mar 28 12:31:14 PM PDT 24 169265424 ps
T1130 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2530744283 Mar 28 12:31:28 PM PDT 24 Mar 28 12:31:30 PM PDT 24 50312562 ps
T1131 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2838071511 Mar 28 12:31:05 PM PDT 24 Mar 28 12:31:06 PM PDT 24 38377941 ps
T1132 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1500282600 Mar 28 12:31:20 PM PDT 24 Mar 28 12:31:21 PM PDT 24 41552523 ps
T1133 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1201200911 Mar 28 12:30:59 PM PDT 24 Mar 28 12:31:00 PM PDT 24 30239159 ps
T1134 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4172961131 Mar 28 12:31:27 PM PDT 24 Mar 28 12:31:28 PM PDT 24 21302478 ps
T1135 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2499558756 Mar 28 12:31:22 PM PDT 24 Mar 28 12:31:24 PM PDT 24 98014618 ps
T1136 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3295240978 Mar 28 12:31:15 PM PDT 24 Mar 28 12:31:16 PM PDT 24 114474650 ps
T1137 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1468877212 Mar 28 12:31:16 PM PDT 24 Mar 28 12:31:16 PM PDT 24 31970242 ps
T1138 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3769561572 Mar 28 12:31:15 PM PDT 24 Mar 28 12:31:17 PM PDT 24 84899513 ps
T1139 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1284315323 Mar 28 12:31:22 PM PDT 24 Mar 28 12:31:23 PM PDT 24 27499943 ps
T1140 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2381805707 Mar 28 12:31:01 PM PDT 24 Mar 28 12:31:03 PM PDT 24 181880845 ps
T1141 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3430435800 Mar 28 12:31:14 PM PDT 24 Mar 28 12:31:17 PM PDT 24 227778300 ps
T1142 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3227275009 Mar 28 12:31:13 PM PDT 24 Mar 28 12:31:16 PM PDT 24 90153587 ps
T229 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2461046603 Mar 28 12:31:24 PM PDT 24 Mar 28 12:31:28 PM PDT 24 316691246 ps
T1143 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2069822435 Mar 28 12:31:16 PM PDT 24 Mar 28 12:31:17 PM PDT 24 36753628 ps
T1144 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3957964772 Mar 28 12:30:43 PM PDT 24 Mar 28 12:30:45 PM PDT 24 43463789 ps
T71 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1616292848 Mar 28 12:31:18 PM PDT 24 Mar 28 12:31:18 PM PDT 24 34353840 ps
T1145 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1701397298 Mar 28 12:31:21 PM PDT 24 Mar 28 12:31:21 PM PDT 24 25663291 ps
T1146 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.803221387 Mar 28 12:31:14 PM PDT 24 Mar 28 12:31:16 PM PDT 24 82050862 ps
T1147 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.110124502 Mar 28 12:31:09 PM PDT 24 Mar 28 12:31:11 PM PDT 24 63476318 ps
T1148 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3050002305 Mar 28 12:31:11 PM PDT 24 Mar 28 12:31:13 PM PDT 24 67596364 ps
T1149 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2830403877 Mar 28 12:30:57 PM PDT 24 Mar 28 12:31:01 PM PDT 24 256731233 ps
T1150 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3579326666 Mar 28 12:30:46 PM PDT 24 Mar 28 12:30:52 PM PDT 24 54181272 ps
T1151 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1686289744 Mar 28 12:31:25 PM PDT 24 Mar 28 12:31:26 PM PDT 24 86692714 ps
T1152 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3195691359 Mar 28 12:31:19 PM PDT 24 Mar 28 12:31:20 PM PDT 24 40589552 ps
T1153 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1344921145 Mar 28 12:30:41 PM PDT 24 Mar 28 12:30:45 PM PDT 24 156565885 ps

Test location /workspace/coverage/default/19.usbdev_in_trans.4131447107
Short name T21
Test name
Test status
Simulation time 8431332836 ps
CPU time 7.32 seconds
Started Mar 28 01:33:46 PM PDT 24
Finished Mar 28 01:33:54 PM PDT 24
Peak memory 203992 kb
Host smart-ecba968e-2d00-4ea0-a577-52574fde3502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41314
47107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.4131447107
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_smoke.3252009116
Short name T23
Test name
Test status
Simulation time 8401260061 ps
CPU time 9.68 seconds
Started Mar 28 01:34:53 PM PDT 24
Finished Mar 28 01:35:03 PM PDT 24
Peak memory 204088 kb
Host smart-8836c84d-e807-4a35-8f9f-f98b97782365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32520
09116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.3252009116
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.3165830827
Short name T13
Test name
Test status
Simulation time 23479714049 ps
CPU time 39.72 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:34:01 PM PDT 24
Peak memory 204300 kb
Host smart-17286d38-c1c1-4c27-b200-5c6caa50bd09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31658
30827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.3165830827
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.4103451222
Short name T72
Test name
Test status
Simulation time 23622735 ps
CPU time 0.67 seconds
Started Mar 28 12:31:18 PM PDT 24
Finished Mar 28 12:31:19 PM PDT 24
Peak memory 202252 kb
Host smart-c60bb5bb-c986-44d7-8cb8-f1d9d433acca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4103451222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.4103451222
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.900534260
Short name T60
Test name
Test status
Simulation time 478938459 ps
CPU time 4.22 seconds
Started Mar 28 12:30:54 PM PDT 24
Finished Mar 28 12:30:59 PM PDT 24
Peak memory 202828 kb
Host smart-24d5e1b2-c2cb-4cd6-9adc-a1a18958a4d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=900534260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.900534260
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.2628011325
Short name T77
Test name
Test status
Simulation time 31217726 ps
CPU time 0.65 seconds
Started Mar 28 12:31:21 PM PDT 24
Finished Mar 28 12:31:21 PM PDT 24
Peak memory 202380 kb
Host smart-a2714748-ba0d-46f2-a2a3-0c5ca07cb766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2628011325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.2628011325
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.1920693203
Short name T41
Test name
Test status
Simulation time 8411932641 ps
CPU time 7.49 seconds
Started Mar 28 01:34:54 PM PDT 24
Finished Mar 28 01:35:03 PM PDT 24
Peak memory 204020 kb
Host smart-db4e331e-a493-4025-929f-910c164527a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19206
93203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.1920693203
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.in_iso.2149180332
Short name T3
Test name
Test status
Simulation time 8390487692 ps
CPU time 7 seconds
Started Mar 28 01:35:45 PM PDT 24
Finished Mar 28 01:35:52 PM PDT 24
Peak memory 204056 kb
Host smart-dd66bd1e-5aaa-4d44-bb63-73cf98df5962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21491
80332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.in_iso.2149180332
Directory /workspace/45.in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.847430529
Short name T5
Test name
Test status
Simulation time 8360128598 ps
CPU time 7.23 seconds
Started Mar 28 01:34:44 PM PDT 24
Finished Mar 28 01:34:52 PM PDT 24
Peak memory 204116 kb
Host smart-1356403f-f9f4-4259-8d78-27264e6a47c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84743
0529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.847430529
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3246279983
Short name T62
Test name
Test status
Simulation time 326212069 ps
CPU time 3.43 seconds
Started Mar 28 12:31:22 PM PDT 24
Finished Mar 28 12:31:25 PM PDT 24
Peak memory 202804 kb
Host smart-3ae8615c-7fef-4183-804e-71c25b76fab1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3246279983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3246279983
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/default/38.phy_config_usb_ref_disable.431181374
Short name T27
Test name
Test status
Simulation time 8365189936 ps
CPU time 7.4 seconds
Started Mar 28 01:35:11 PM PDT 24
Finished Mar 28 01:35:19 PM PDT 24
Peak memory 204024 kb
Host smart-050ad134-9675-40ad-b02c-4da078d3cdb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43118
1374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.phy_config_usb_ref_disable.431181374
Directory /workspace/38.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.505782763
Short name T17
Test name
Test status
Simulation time 100262808 ps
CPU time 1.31 seconds
Started Mar 28 01:35:05 PM PDT 24
Finished Mar 28 01:35:07 PM PDT 24
Peak memory 204044 kb
Host smart-95f0ff3a-e0f4-4602-9032-9b0430e75649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50578
2763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.505782763
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.4059482073
Short name T36
Test name
Test status
Simulation time 26715159 ps
CPU time 0.66 seconds
Started Mar 28 01:35:28 PM PDT 24
Finished Mar 28 01:35:28 PM PDT 24
Peak memory 204012 kb
Host smart-403081e5-cd6b-4ccc-b9a5-dbe9c109a2d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40594
82073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.4059482073
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.1603775881
Short name T64
Test name
Test status
Simulation time 104784421 ps
CPU time 0.89 seconds
Started Mar 28 01:32:30 PM PDT 24
Finished Mar 28 01:32:31 PM PDT 24
Peak memory 220072 kb
Host smart-95477513-e95d-4bcc-b43b-8871fbb67c3c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1603775881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1603775881
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.4231990567
Short name T278
Test name
Test status
Simulation time 30016692 ps
CPU time 0.65 seconds
Started Mar 28 12:31:21 PM PDT 24
Finished Mar 28 12:31:22 PM PDT 24
Peak memory 202496 kb
Host smart-dc34fe40-426f-4a3b-ae41-d5daa3c77943
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4231990567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.4231990567
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.3263880384
Short name T44
Test name
Test status
Simulation time 8362330957 ps
CPU time 9.03 seconds
Started Mar 28 01:33:24 PM PDT 24
Finished Mar 28 01:33:38 PM PDT 24
Peak memory 203844 kb
Host smart-96e8d058-0071-48b4-a1b7-fae9b63c42df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32638
80384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.3263880384
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.130428401
Short name T67
Test name
Test status
Simulation time 56152539 ps
CPU time 0.87 seconds
Started Mar 28 12:31:13 PM PDT 24
Finished Mar 28 12:31:14 PM PDT 24
Peak memory 202520 kb
Host smart-720ca10e-6445-46b1-9659-9480b2ce66e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130428401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.130428401
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2186508766
Short name T284
Test name
Test status
Simulation time 22154084 ps
CPU time 0.66 seconds
Started Mar 28 12:31:24 PM PDT 24
Finished Mar 28 12:31:25 PM PDT 24
Peak memory 202516 kb
Host smart-d2204942-9070-4709-bd08-8e8add83f877
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2186508766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2186508766
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2461046603
Short name T229
Test name
Test status
Simulation time 316691246 ps
CPU time 3.94 seconds
Started Mar 28 12:31:24 PM PDT 24
Finished Mar 28 12:31:28 PM PDT 24
Peak memory 202740 kb
Host smart-9d283051-e09a-42bb-81c5-1048cd7039e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2461046603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2461046603
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2991093320
Short name T288
Test name
Test status
Simulation time 206363156 ps
CPU time 3.69 seconds
Started Mar 28 12:31:16 PM PDT 24
Finished Mar 28 12:31:20 PM PDT 24
Peak memory 202804 kb
Host smart-ce3c1f1b-0f0e-4234-8524-3c5c9f6c80e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2991093320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2991093320
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2773910769
Short name T68
Test name
Test status
Simulation time 57849249 ps
CPU time 1.37 seconds
Started Mar 28 12:30:37 PM PDT 24
Finished Mar 28 12:30:39 PM PDT 24
Peak memory 201964 kb
Host smart-04d9ce5f-4dd9-4912-9143-491ad009b2a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773910769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_c
sr_outstanding.2773910769
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.205212477
Short name T282
Test name
Test status
Simulation time 20550083 ps
CPU time 0.59 seconds
Started Mar 28 12:31:17 PM PDT 24
Finished Mar 28 12:31:17 PM PDT 24
Peak memory 202364 kb
Host smart-a96e743d-12d7-47df-868f-355ff93b830a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=205212477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.205212477
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.1054018872
Short name T100
Test name
Test status
Simulation time 30012854090 ps
CPU time 57.97 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:36:49 PM PDT 24
Peak memory 204352 kb
Host smart-ab581c9c-cf5f-4b70-aeb9-a65ce30d5ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10540
18872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.1054018872
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2413968128
Short name T66
Test name
Test status
Simulation time 30560251 ps
CPU time 0.74 seconds
Started Mar 28 12:30:56 PM PDT 24
Finished Mar 28 12:30:57 PM PDT 24
Peak memory 202392 kb
Host smart-b454deb7-1a2b-4cc0-ab26-fa7d35301c37
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413968128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2413968128
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3128861572
Short name T287
Test name
Test status
Simulation time 448962925 ps
CPU time 4.3 seconds
Started Mar 28 12:31:08 PM PDT 24
Finished Mar 28 12:31:12 PM PDT 24
Peak memory 202744 kb
Host smart-39e07626-44fe-4a76-bb3f-bd4147e6d855
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3128861572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.3128861572
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1094016414
Short name T292
Test name
Test status
Simulation time 281455409 ps
CPU time 2.55 seconds
Started Mar 28 12:31:00 PM PDT 24
Finished Mar 28 12:31:03 PM PDT 24
Peak memory 202852 kb
Host smart-9827572f-cced-4e47-8ed1-d9c9a81a1d49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1094016414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1094016414
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3272113842
Short name T1099
Test name
Test status
Simulation time 102353435 ps
CPU time 3.25 seconds
Started Mar 28 12:31:19 PM PDT 24
Finished Mar 28 12:31:23 PM PDT 24
Peak memory 202792 kb
Host smart-6dbe45a1-f2ee-4045-9ce4-f0b535026344
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3272113842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3272113842
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.2928427523
Short name T312
Test name
Test status
Simulation time 29349349 ps
CPU time 0.69 seconds
Started Mar 28 01:32:24 PM PDT 24
Finished Mar 28 01:32:25 PM PDT 24
Peak memory 203864 kb
Host smart-c5aad395-a190-453b-a598-56b31856ec22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29284
27523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.2928427523
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.1538405321
Short name T51
Test name
Test status
Simulation time 8458496673 ps
CPU time 7.5 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:31 PM PDT 24
Peak memory 203940 kb
Host smart-98e255ea-823e-4f38-b786-ffa77ef336eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15384
05321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.1538405321
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.572081399
Short name T204
Test name
Test status
Simulation time 29426147252 ps
CPU time 51.45 seconds
Started Mar 28 01:35:30 PM PDT 24
Finished Mar 28 01:36:22 PM PDT 24
Peak memory 204300 kb
Host smart-fdd60551-4789-456c-94e4-4b9483b9520a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57208
1399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.572081399
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_smoke.133725418
Short name T170
Test name
Test status
Simulation time 8442210796 ps
CPU time 7.34 seconds
Started Mar 28 01:32:28 PM PDT 24
Finished Mar 28 01:32:35 PM PDT 24
Peak memory 203868 kb
Host smart-0f2ef9b3-0e62-4348-ac14-36cd26168891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13372
5418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.133725418
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_smoke.408298667
Short name T150
Test name
Test status
Simulation time 8416685810 ps
CPU time 7.51 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:31 PM PDT 24
Peak memory 204072 kb
Host smart-8466bed9-4676-4ec5-95c8-10e8171b8544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40829
8667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.408298667
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_smoke.2155406017
Short name T98
Test name
Test status
Simulation time 8423015450 ps
CPU time 7.24 seconds
Started Mar 28 01:33:18 PM PDT 24
Finished Mar 28 01:33:26 PM PDT 24
Peak memory 203800 kb
Host smart-099c639e-8dc4-4fc4-9500-1a9f908ab8bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21554
06017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.2155406017
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3180528257
Short name T834
Test name
Test status
Simulation time 8438436182 ps
CPU time 10.17 seconds
Started Mar 28 01:34:24 PM PDT 24
Finished Mar 28 01:34:34 PM PDT 24
Peak memory 204044 kb
Host smart-e03b2826-da0a-4074-9c3c-b42c28f2a76a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31805
28257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3180528257
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2846786030
Short name T171
Test name
Test status
Simulation time 8435203242 ps
CPU time 8.63 seconds
Started Mar 28 01:34:24 PM PDT 24
Finished Mar 28 01:34:32 PM PDT 24
Peak memory 204040 kb
Host smart-bcadb954-079c-48e0-a22f-2ad443ac5064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28467
86030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2846786030
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_smoke.522906518
Short name T362
Test name
Test status
Simulation time 8432079349 ps
CPU time 7.34 seconds
Started Mar 28 01:32:39 PM PDT 24
Finished Mar 28 01:32:46 PM PDT 24
Peak memory 203924 kb
Host smart-9f378d50-04bf-410e-b2b4-8a024577dd07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52290
6518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.522906518
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_smoke.850688445
Short name T147
Test name
Test status
Simulation time 8435971473 ps
CPU time 7.08 seconds
Started Mar 28 01:34:48 PM PDT 24
Finished Mar 28 01:34:55 PM PDT 24
Peak memory 204044 kb
Host smart-e8bdc609-d8fa-4924-94c5-b82713d51fdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85068
8445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.850688445
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_smoke.3903140826
Short name T178
Test name
Test status
Simulation time 8412274100 ps
CPU time 7.4 seconds
Started Mar 28 01:34:44 PM PDT 24
Finished Mar 28 01:34:51 PM PDT 24
Peak memory 204040 kb
Host smart-fb559bc3-6a50-4e6c-bb06-874b939583a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39031
40826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.3903140826
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.1345438079
Short name T19
Test name
Test status
Simulation time 8398933333 ps
CPU time 8.32 seconds
Started Mar 28 01:33:25 PM PDT 24
Finished Mar 28 01:33:37 PM PDT 24
Peak memory 204088 kb
Host smart-e9c7827f-9f13-4491-9f3f-1627aad0b5b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13454
38079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.1345438079
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.4162828504
Short name T70
Test name
Test status
Simulation time 55882970 ps
CPU time 0.85 seconds
Started Mar 28 12:30:49 PM PDT 24
Finished Mar 28 12:30:51 PM PDT 24
Peak memory 202488 kb
Host smart-afa18dbc-c6d4-4315-b073-b0d4f2369aa2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162828504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.4162828504
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.3947130127
Short name T326
Test name
Test status
Simulation time 8354781437 ps
CPU time 8.96 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:32 PM PDT 24
Peak memory 204100 kb
Host smart-357774cf-6edd-49e0-9862-e839382e2fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39471
30127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.3947130127
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.3821172304
Short name T164
Test name
Test status
Simulation time 8457142148 ps
CPU time 8.7 seconds
Started Mar 28 01:33:18 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 204040 kb
Host smart-f4380c9a-a152-4f89-94c1-e747317d8365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38211
72304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.3821172304
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.4010039788
Short name T1063
Test name
Test status
Simulation time 30098550814 ps
CPU time 50.49 seconds
Started Mar 28 01:33:32 PM PDT 24
Finished Mar 28 01:34:22 PM PDT 24
Peak memory 204236 kb
Host smart-3b5d55be-4f80-48b9-8801-e72db0dc14c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40100
39788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.4010039788
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_smoke.799524873
Short name T981
Test name
Test status
Simulation time 8454531831 ps
CPU time 7.21 seconds
Started Mar 28 01:33:47 PM PDT 24
Finished Mar 28 01:33:54 PM PDT 24
Peak memory 204080 kb
Host smart-00037457-54fe-4ba1-b9e7-54f4f1f22b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79952
4873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.799524873
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2404345136
Short name T190
Test name
Test status
Simulation time 8357415828 ps
CPU time 8.2 seconds
Started Mar 28 01:32:26 PM PDT 24
Finished Mar 28 01:32:35 PM PDT 24
Peak memory 204024 kb
Host smart-35b6883b-bd91-42e4-8e3a-75d6eeac633c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24043
45136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2404345136
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.3037288040
Short name T117
Test name
Test status
Simulation time 8454747866 ps
CPU time 7.03 seconds
Started Mar 28 01:32:28 PM PDT 24
Finished Mar 28 01:32:35 PM PDT 24
Peak memory 203876 kb
Host smart-6b2c7d67-b0c4-4804-ac52-a97804224f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30372
88040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.3037288040
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.383864777
Short name T207
Test name
Test status
Simulation time 8364548337 ps
CPU time 7.63 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:31 PM PDT 24
Peak memory 204100 kb
Host smart-c3de98d7-df01-467a-b0a6-1c7e6f2e6a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38386
4777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.383864777
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.673937213
Short name T134
Test name
Test status
Simulation time 8421611278 ps
CPU time 7.61 seconds
Started Mar 28 01:33:17 PM PDT 24
Finished Mar 28 01:33:25 PM PDT 24
Peak memory 204088 kb
Host smart-43d1dba2-08c5-487a-8715-55d693332c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67393
7213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.673937213
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.in_iso.1134523790
Short name T836
Test name
Test status
Simulation time 8421697749 ps
CPU time 8.87 seconds
Started Mar 28 01:33:26 PM PDT 24
Finished Mar 28 01:33:37 PM PDT 24
Peak memory 204084 kb
Host smart-2c4f50a8-e06a-474c-8c23-8c082420b74c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11345
23790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.in_iso.1134523790
Directory /workspace/11.in_iso/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.3132172798
Short name T827
Test name
Test status
Simulation time 8435342964 ps
CPU time 8.64 seconds
Started Mar 28 01:33:23 PM PDT 24
Finished Mar 28 01:33:36 PM PDT 24
Peak memory 204092 kb
Host smart-9343367c-7260-4d53-ad95-f9d3fae4b7f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31321
72798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.3132172798
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1207399626
Short name T10
Test name
Test status
Simulation time 8411222268 ps
CPU time 9.59 seconds
Started Mar 28 01:33:18 PM PDT 24
Finished Mar 28 01:33:29 PM PDT 24
Peak memory 204092 kb
Host smart-c5652617-e5e0-4057-af95-1382e7916eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12073
99626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1207399626
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.2530525032
Short name T122
Test name
Test status
Simulation time 8437765477 ps
CPU time 9.57 seconds
Started Mar 28 01:33:19 PM PDT 24
Finished Mar 28 01:33:30 PM PDT 24
Peak memory 204120 kb
Host smart-246d9627-45a4-4090-811d-f4248a17f6ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25305
25032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.2530525032
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.1535715810
Short name T220
Test name
Test status
Simulation time 8361929815 ps
CPU time 8 seconds
Started Mar 28 01:33:26 PM PDT 24
Finished Mar 28 01:33:37 PM PDT 24
Peak memory 204088 kb
Host smart-a6b3c822-84e6-4014-968e-09936b5b0147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15357
15810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.1535715810
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.2170809994
Short name T137
Test name
Test status
Simulation time 8423227778 ps
CPU time 7.01 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:31 PM PDT 24
Peak memory 204032 kb
Host smart-73041068-7dea-450b-be94-92302eec3eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21708
09994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.2170809994
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.2052803059
Short name T183
Test name
Test status
Simulation time 23210440011 ps
CPU time 42.53 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:34:06 PM PDT 24
Peak memory 204268 kb
Host smart-7c2c8fed-41fc-40e1-9b60-243772b4b198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20528
03059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.2052803059
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.2220570427
Short name T643
Test name
Test status
Simulation time 8390647706 ps
CPU time 7.15 seconds
Started Mar 28 01:33:26 PM PDT 24
Finished Mar 28 01:33:36 PM PDT 24
Peak memory 204052 kb
Host smart-139f542a-b7d1-407b-98f5-1cb9ba65a17f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22205
70427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.2220570427
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.1068781422
Short name T199
Test name
Test status
Simulation time 8357829712 ps
CPU time 7.7 seconds
Started Mar 28 01:33:49 PM PDT 24
Finished Mar 28 01:33:57 PM PDT 24
Peak memory 204024 kb
Host smart-53285a44-06cb-420d-bd05-b4f493908c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10687
81422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.1068781422
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.965479113
Short name T128
Test name
Test status
Simulation time 8433447070 ps
CPU time 9.16 seconds
Started Mar 28 01:33:51 PM PDT 24
Finished Mar 28 01:34:01 PM PDT 24
Peak memory 204056 kb
Host smart-3472b23c-18a1-4b0e-9a5d-ec7b2b521037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96547
9113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.965479113
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.4071746258
Short name T786
Test name
Test status
Simulation time 8414460705 ps
CPU time 7.97 seconds
Started Mar 28 01:32:35 PM PDT 24
Finished Mar 28 01:32:43 PM PDT 24
Peak memory 204044 kb
Host smart-781a1333-35a7-4d60-9918-3cce83316b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40717
46258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.4071746258
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.2646652697
Short name T760
Test name
Test status
Simulation time 8359155434 ps
CPU time 7.67 seconds
Started Mar 28 01:34:26 PM PDT 24
Finished Mar 28 01:34:33 PM PDT 24
Peak memory 203952 kb
Host smart-2811a6a5-5ee8-48ff-8d0a-3aa9676fdcc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26466
52697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.2646652697
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.2375273912
Short name T918
Test name
Test status
Simulation time 8421975204 ps
CPU time 7.47 seconds
Started Mar 28 01:34:23 PM PDT 24
Finished Mar 28 01:34:31 PM PDT 24
Peak memory 204080 kb
Host smart-83829e87-fbb8-4090-8385-9114f4f1c3b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23752
73912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.2375273912
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.117953972
Short name T131
Test name
Test status
Simulation time 8413848571 ps
CPU time 7.07 seconds
Started Mar 28 01:33:00 PM PDT 24
Finished Mar 28 01:33:09 PM PDT 24
Peak memory 204056 kb
Host smart-bd92c19f-6041-4396-8469-6998e1199a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11795
3972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.117953972
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.1884548092
Short name T219
Test name
Test status
Simulation time 29759137519 ps
CPU time 51.13 seconds
Started Mar 28 01:33:00 PM PDT 24
Finished Mar 28 01:33:53 PM PDT 24
Peak memory 204236 kb
Host smart-6be0a6b1-0823-4831-9165-8ab67a7f3b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18845
48092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.1884548092
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.611430036
Short name T120
Test name
Test status
Simulation time 8382911685 ps
CPU time 7.16 seconds
Started Mar 28 01:35:31 PM PDT 24
Finished Mar 28 01:35:38 PM PDT 24
Peak memory 204028 kb
Host smart-720aa01f-6e91-45a1-bc67-1b1cbf9ff664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61143
0036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.611430036
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1925010218
Short name T264
Test name
Test status
Simulation time 108192129 ps
CPU time 3.21 seconds
Started Mar 28 12:31:20 PM PDT 24
Finished Mar 28 12:31:23 PM PDT 24
Peak memory 202832 kb
Host smart-26b5d881-95a3-4ec4-bd50-b3b8996d3697
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925010218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1925010218
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1764851166
Short name T1119
Test name
Test status
Simulation time 78071371 ps
CPU time 2.6 seconds
Started Mar 28 12:30:45 PM PDT 24
Finished Mar 28 12:30:58 PM PDT 24
Peak memory 210972 kb
Host smart-f07fa061-c271-4ca7-8c8c-34f1dbfb041c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764851166 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.1764851166
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3885863155
Short name T272
Test name
Test status
Simulation time 39805915 ps
CPU time 0.77 seconds
Started Mar 28 12:30:44 PM PDT 24
Finished Mar 28 12:30:46 PM PDT 24
Peak memory 202716 kb
Host smart-9cc9dc10-6186-450a-9cce-2321bee42ab5
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885863155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.3885863155
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1344921145
Short name T1153
Test name
Test status
Simulation time 156565885 ps
CPU time 2.28 seconds
Started Mar 28 12:30:41 PM PDT 24
Finished Mar 28 12:30:45 PM PDT 24
Peak memory 210988 kb
Host smart-013d5ac5-d0cf-4fef-bbd8-94d214f760df
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1344921145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1344921145
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.669311715
Short name T1072
Test name
Test status
Simulation time 246554551 ps
CPU time 2.48 seconds
Started Mar 28 12:31:00 PM PDT 24
Finished Mar 28 12:31:03 PM PDT 24
Peak memory 202628 kb
Host smart-f5c3e145-b79d-4999-afc8-ec5e85b8e3c1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=669311715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.669311715
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2838071511
Short name T1131
Test name
Test status
Simulation time 38377941 ps
CPU time 1.11 seconds
Started Mar 28 12:31:05 PM PDT 24
Finished Mar 28 12:31:06 PM PDT 24
Peak memory 202824 kb
Host smart-63773474-fc29-42fb-96d4-34d10250507c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838071511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_c
sr_outstanding.2838071511
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2909222004
Short name T227
Test name
Test status
Simulation time 180573490 ps
CPU time 2.21 seconds
Started Mar 28 12:31:05 PM PDT 24
Finished Mar 28 12:31:07 PM PDT 24
Peak memory 202720 kb
Host smart-3789fba2-1823-45f1-9095-a41c82b0d70f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2909222004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2909222004
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2806374160
Short name T248
Test name
Test status
Simulation time 238642939 ps
CPU time 2.59 seconds
Started Mar 28 12:30:47 PM PDT 24
Finished Mar 28 12:30:50 PM PDT 24
Peak memory 202852 kb
Host smart-59c309dc-a5ce-46ee-9e33-e6f124179c2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2806374160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2806374160
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2627996840
Short name T73
Test name
Test status
Simulation time 150612198 ps
CPU time 1.99 seconds
Started Mar 28 12:30:58 PM PDT 24
Finished Mar 28 12:31:00 PM PDT 24
Peak memory 203036 kb
Host smart-9a5ddbb6-d503-4084-8e98-af29d66bb6f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627996840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2627996840
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1913314320
Short name T266
Test name
Test status
Simulation time 275440910 ps
CPU time 6.64 seconds
Started Mar 28 12:31:00 PM PDT 24
Finished Mar 28 12:31:07 PM PDT 24
Peak memory 202828 kb
Host smart-b14252db-6f2c-4f91-be85-729b09dbddbe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913314320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1913314320
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3579326666
Short name T1150
Test name
Test status
Simulation time 54181272 ps
CPU time 0.85 seconds
Started Mar 28 12:30:46 PM PDT 24
Finished Mar 28 12:30:52 PM PDT 24
Peak memory 202512 kb
Host smart-5c5efa3f-a102-425f-80f0-ad39ec0e27d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579326666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.3579326666
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.706262537
Short name T1103
Test name
Test status
Simulation time 42176374 ps
CPU time 1.23 seconds
Started Mar 28 12:31:05 PM PDT 24
Finished Mar 28 12:31:06 PM PDT 24
Peak memory 210984 kb
Host smart-e57d9925-1382-46f2-9ad4-5ea5f602df7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706262537 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.706262537
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1062945574
Short name T69
Test name
Test status
Simulation time 34557790 ps
CPU time 0.92 seconds
Started Mar 28 12:31:00 PM PDT 24
Finished Mar 28 12:31:02 PM PDT 24
Peak memory 202856 kb
Host smart-c80e19a3-e599-487b-8693-74c9d4ea1770
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062945574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1062945574
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1201200911
Short name T1133
Test name
Test status
Simulation time 30239159 ps
CPU time 0.64 seconds
Started Mar 28 12:30:59 PM PDT 24
Finished Mar 28 12:31:00 PM PDT 24
Peak memory 202400 kb
Host smart-50b4c862-1636-4786-b271-e1f82c633705
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1201200911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.1201200911
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3748928658
Short name T1074
Test name
Test status
Simulation time 83896853 ps
CPU time 1.45 seconds
Started Mar 28 12:30:45 PM PDT 24
Finished Mar 28 12:30:47 PM PDT 24
Peak memory 202636 kb
Host smart-fd6d3a49-ea13-4f1d-b86b-23adb4bf82ed
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3748928658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.3748928658
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.92469807
Short name T1127
Test name
Test status
Simulation time 148690761 ps
CPU time 4.02 seconds
Started Mar 28 12:31:20 PM PDT 24
Finished Mar 28 12:31:24 PM PDT 24
Peak memory 202692 kb
Host smart-782b9f98-de4e-43ba-acbe-3d241d4f10d2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=92469807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.92469807
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3197135542
Short name T1123
Test name
Test status
Simulation time 51708604 ps
CPU time 1.42 seconds
Started Mar 28 12:31:23 PM PDT 24
Finished Mar 28 12:31:25 PM PDT 24
Peak memory 202820 kb
Host smart-cac788db-c3f2-4e27-a7e4-9a01dc26710c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197135542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_c
sr_outstanding.3197135542
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2830403877
Short name T1149
Test name
Test status
Simulation time 256731233 ps
CPU time 3.15 seconds
Started Mar 28 12:30:57 PM PDT 24
Finished Mar 28 12:31:01 PM PDT 24
Peak memory 202684 kb
Host smart-52f66684-c53d-4faf-8fc5-16f78afc02df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2830403877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.2830403877
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1171592049
Short name T1118
Test name
Test status
Simulation time 260839440 ps
CPU time 2.53 seconds
Started Mar 28 12:31:04 PM PDT 24
Finished Mar 28 12:31:07 PM PDT 24
Peak memory 202808 kb
Host smart-0e440a80-94cc-4b27-8f61-5ea6b42a60a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1171592049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1171592049
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2069822435
Short name T1143
Test name
Test status
Simulation time 36753628 ps
CPU time 1.09 seconds
Started Mar 28 12:31:16 PM PDT 24
Finished Mar 28 12:31:17 PM PDT 24
Peak memory 211048 kb
Host smart-adac30e8-04f7-463e-a324-e177f7bbc065
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069822435 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.2069822435
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2977975474
Short name T259
Test name
Test status
Simulation time 64441515 ps
CPU time 1.02 seconds
Started Mar 28 12:31:11 PM PDT 24
Finished Mar 28 12:31:12 PM PDT 24
Peak memory 202732 kb
Host smart-c7c66606-64aa-468c-af11-16a27ca46674
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977975474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2977975474
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1493935053
Short name T1092
Test name
Test status
Simulation time 27140625 ps
CPU time 0.62 seconds
Started Mar 28 12:31:13 PM PDT 24
Finished Mar 28 12:31:14 PM PDT 24
Peak memory 202480 kb
Host smart-63330d29-04e6-42c6-b7f8-aad38ae5e792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1493935053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.1493935053
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2087071675
Short name T1078
Test name
Test status
Simulation time 59905477 ps
CPU time 1.39 seconds
Started Mar 28 12:31:22 PM PDT 24
Finished Mar 28 12:31:23 PM PDT 24
Peak memory 202760 kb
Host smart-6fa83dff-b926-44b4-a32a-5355254d36b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087071675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_
csr_outstanding.2087071675
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2796422976
Short name T1129
Test name
Test status
Simulation time 169265424 ps
CPU time 2.17 seconds
Started Mar 28 12:31:12 PM PDT 24
Finished Mar 28 12:31:14 PM PDT 24
Peak memory 202804 kb
Host smart-6b6efb22-a986-4b8c-9a3c-1e9868f14446
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2796422976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2796422976
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1686289744
Short name T1151
Test name
Test status
Simulation time 86692714 ps
CPU time 1.26 seconds
Started Mar 28 12:31:25 PM PDT 24
Finished Mar 28 12:31:26 PM PDT 24
Peak memory 210972 kb
Host smart-8001eef8-b681-476c-9b8f-123289580200
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686289744 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.1686289744
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3195691359
Short name T1152
Test name
Test status
Simulation time 40589552 ps
CPU time 0.85 seconds
Started Mar 28 12:31:19 PM PDT 24
Finished Mar 28 12:31:20 PM PDT 24
Peak memory 202488 kb
Host smart-84e395c4-ec1a-4e92-95f4-3c53f77bb4fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195691359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3195691359
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.4101442562
Short name T1100
Test name
Test status
Simulation time 21750285 ps
CPU time 0.66 seconds
Started Mar 28 12:31:22 PM PDT 24
Finished Mar 28 12:31:23 PM PDT 24
Peak memory 202412 kb
Host smart-74f7a0a6-e660-415f-adc8-33849f579df7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4101442562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.4101442562
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2568171596
Short name T1075
Test name
Test status
Simulation time 50932141 ps
CPU time 1.35 seconds
Started Mar 28 12:31:21 PM PDT 24
Finished Mar 28 12:31:22 PM PDT 24
Peak memory 202820 kb
Host smart-70ca64c2-5452-4374-b390-33f2febc74bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568171596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_
csr_outstanding.2568171596
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1269825532
Short name T1116
Test name
Test status
Simulation time 81762512 ps
CPU time 1.43 seconds
Started Mar 28 12:31:05 PM PDT 24
Finished Mar 28 12:31:08 PM PDT 24
Peak memory 211140 kb
Host smart-fc95ab79-715b-4c42-9fe7-65de003fe324
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269825532 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.1269825532
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.529198037
Short name T109
Test name
Test status
Simulation time 33348749 ps
CPU time 0.82 seconds
Started Mar 28 12:31:11 PM PDT 24
Finished Mar 28 12:31:12 PM PDT 24
Peak memory 202448 kb
Host smart-c78a544e-f848-40b9-b463-fae19336a773
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529198037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.529198037
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.508894392
Short name T286
Test name
Test status
Simulation time 28949157 ps
CPU time 0.69 seconds
Started Mar 28 12:31:23 PM PDT 24
Finished Mar 28 12:31:23 PM PDT 24
Peak memory 202380 kb
Host smart-33d027ff-2c16-4ba3-a9b3-4beb9662ffa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=508894392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.508894392
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3052038268
Short name T228
Test name
Test status
Simulation time 71361071 ps
CPU time 1.05 seconds
Started Mar 28 12:31:29 PM PDT 24
Finished Mar 28 12:31:30 PM PDT 24
Peak memory 202828 kb
Host smart-0f9e690b-e49b-46a5-aeaf-a8f5949a5d99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052038268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_
csr_outstanding.3052038268
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2502205997
Short name T242
Test name
Test status
Simulation time 53938082 ps
CPU time 1.72 seconds
Started Mar 28 12:31:28 PM PDT 24
Finished Mar 28 12:31:29 PM PDT 24
Peak memory 202760 kb
Host smart-8df6190d-c4a9-43bc-811f-2793814cdc22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2502205997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2502205997
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3659944665
Short name T1085
Test name
Test status
Simulation time 52145687 ps
CPU time 1.79 seconds
Started Mar 28 12:31:16 PM PDT 24
Finished Mar 28 12:31:18 PM PDT 24
Peak memory 211024 kb
Host smart-ba89261e-9ec8-495f-8b94-f4e3b3f2e999
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659944665 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.3659944665
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3043691631
Short name T108
Test name
Test status
Simulation time 25589191 ps
CPU time 0.79 seconds
Started Mar 28 12:31:29 PM PDT 24
Finished Mar 28 12:31:30 PM PDT 24
Peak memory 202540 kb
Host smart-b0ca392c-4f07-449c-84c9-d98cf546b245
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043691631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3043691631
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1290965417
Short name T283
Test name
Test status
Simulation time 27774353 ps
CPU time 0.6 seconds
Started Mar 28 12:31:21 PM PDT 24
Finished Mar 28 12:31:22 PM PDT 24
Peak memory 202372 kb
Host smart-d45a05a0-b44e-468b-9018-604b363e16c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1290965417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1290965417
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2129154748
Short name T267
Test name
Test status
Simulation time 61227165 ps
CPU time 1.04 seconds
Started Mar 28 12:31:20 PM PDT 24
Finished Mar 28 12:31:21 PM PDT 24
Peak memory 202732 kb
Host smart-600e0973-d430-4a66-8fa3-25735bd6cb36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129154748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_
csr_outstanding.2129154748
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2499558756
Short name T1135
Test name
Test status
Simulation time 98014618 ps
CPU time 1.63 seconds
Started Mar 28 12:31:22 PM PDT 24
Finished Mar 28 12:31:24 PM PDT 24
Peak memory 202752 kb
Host smart-942c0fbb-678a-4776-929b-ff8b447ef2aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2499558756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2499558756
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2879844101
Short name T231
Test name
Test status
Simulation time 498284471 ps
CPU time 4.33 seconds
Started Mar 28 12:31:19 PM PDT 24
Finished Mar 28 12:31:23 PM PDT 24
Peak memory 202840 kb
Host smart-4699c250-eae6-4dd2-a3c0-dfee52332faa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2879844101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.2879844101
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1510712798
Short name T1109
Test name
Test status
Simulation time 40264318 ps
CPU time 1.11 seconds
Started Mar 28 12:31:09 PM PDT 24
Finished Mar 28 12:31:10 PM PDT 24
Peak memory 211136 kb
Host smart-9a121130-628b-4419-8fce-e51d0f95728f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510712798 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.1510712798
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4195165999
Short name T262
Test name
Test status
Simulation time 43467974 ps
CPU time 0.8 seconds
Started Mar 28 12:31:16 PM PDT 24
Finished Mar 28 12:31:17 PM PDT 24
Peak memory 202552 kb
Host smart-a536a6ad-0dcb-4a93-8f04-27ce0d79c06b
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195165999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.4195165999
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4093998027
Short name T1077
Test name
Test status
Simulation time 52756358 ps
CPU time 1.29 seconds
Started Mar 28 12:31:31 PM PDT 24
Finished Mar 28 12:31:33 PM PDT 24
Peak memory 202840 kb
Host smart-7e9fff02-2284-452b-97a8-91a99c4ab7fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093998027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_
csr_outstanding.4093998027
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.713683508
Short name T1113
Test name
Test status
Simulation time 257143656 ps
CPU time 2.78 seconds
Started Mar 28 12:31:21 PM PDT 24
Finished Mar 28 12:31:24 PM PDT 24
Peak memory 202804 kb
Host smart-1126719f-0479-40f0-9b30-0fac98d17768
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=713683508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.713683508
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3763035201
Short name T1088
Test name
Test status
Simulation time 150239795 ps
CPU time 1.75 seconds
Started Mar 28 12:31:20 PM PDT 24
Finished Mar 28 12:31:21 PM PDT 24
Peak memory 211036 kb
Host smart-95d61a8a-7901-422b-8d45-98a0119532b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763035201 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.3763035201
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.171052699
Short name T1111
Test name
Test status
Simulation time 33696979 ps
CPU time 0.89 seconds
Started Mar 28 12:31:23 PM PDT 24
Finished Mar 28 12:31:24 PM PDT 24
Peak memory 202856 kb
Host smart-9cd75e0e-9958-4ded-8f00-bebb8be9d323
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171052699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.171052699
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1284315323
Short name T1139
Test name
Test status
Simulation time 27499943 ps
CPU time 0.67 seconds
Started Mar 28 12:31:22 PM PDT 24
Finished Mar 28 12:31:23 PM PDT 24
Peak memory 202292 kb
Host smart-a5612a0f-d584-4c72-914e-60d4ffa58526
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1284315323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1284315323
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2564460395
Short name T1082
Test name
Test status
Simulation time 151960763 ps
CPU time 1.62 seconds
Started Mar 28 12:31:28 PM PDT 24
Finished Mar 28 12:31:30 PM PDT 24
Peak memory 202796 kb
Host smart-d818fdca-a412-47ab-b4cd-79add1f1d8b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564460395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_
csr_outstanding.2564460395
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3061298870
Short name T1114
Test name
Test status
Simulation time 61388685 ps
CPU time 1.86 seconds
Started Mar 28 12:31:12 PM PDT 24
Finished Mar 28 12:31:14 PM PDT 24
Peak memory 202664 kb
Host smart-5e33baad-b670-4d5f-802c-ab8b1018ee24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3061298870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3061298870
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3822953374
Short name T1102
Test name
Test status
Simulation time 146929968 ps
CPU time 1.89 seconds
Started Mar 28 12:31:28 PM PDT 24
Finished Mar 28 12:31:30 PM PDT 24
Peak memory 211168 kb
Host smart-2c71fcc2-7570-4e6e-b1ff-b69534a61e4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822953374 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.3822953374
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2248151014
Short name T257
Test name
Test status
Simulation time 32266021 ps
CPU time 0.96 seconds
Started Mar 28 12:31:28 PM PDT 24
Finished Mar 28 12:31:29 PM PDT 24
Peak memory 202708 kb
Host smart-b7f724da-0b96-4aa8-9fc4-7059d2f2e360
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248151014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2248151014
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3738890190
Short name T1076
Test name
Test status
Simulation time 21867270 ps
CPU time 0.64 seconds
Started Mar 28 12:31:18 PM PDT 24
Finished Mar 28 12:31:19 PM PDT 24
Peak memory 202252 kb
Host smart-0e9ace59-c248-47ff-9f3e-9114b053c448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3738890190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.3738890190
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.4043436188
Short name T1126
Test name
Test status
Simulation time 52696226 ps
CPU time 1.42 seconds
Started Mar 28 12:31:20 PM PDT 24
Finished Mar 28 12:31:22 PM PDT 24
Peak memory 202824 kb
Host smart-565e5b91-17c2-4362-b4be-d2fc8e9b5c8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043436188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_
csr_outstanding.4043436188
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.803221387
Short name T1146
Test name
Test status
Simulation time 82050862 ps
CPU time 2.58 seconds
Started Mar 28 12:31:14 PM PDT 24
Finished Mar 28 12:31:16 PM PDT 24
Peak memory 202692 kb
Host smart-0eb1df71-5309-4267-9b12-db6ed55976ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=803221387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.803221387
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2319927607
Short name T230
Test name
Test status
Simulation time 253937216 ps
CPU time 2.23 seconds
Started Mar 28 12:31:30 PM PDT 24
Finished Mar 28 12:31:32 PM PDT 24
Peak memory 202776 kb
Host smart-8cffb32c-27e8-4886-ba58-43e0edfc75a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2319927607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.2319927607
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1970878139
Short name T247
Test name
Test status
Simulation time 82175281 ps
CPU time 1.22 seconds
Started Mar 28 12:31:19 PM PDT 24
Finished Mar 28 12:31:20 PM PDT 24
Peak memory 212164 kb
Host smart-c4ebf366-35f9-4132-93ff-fb15ed33a2ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970878139 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.1970878139
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1853042118
Short name T1073
Test name
Test status
Simulation time 38087014 ps
CPU time 0.81 seconds
Started Mar 28 12:31:15 PM PDT 24
Finished Mar 28 12:31:16 PM PDT 24
Peak memory 202468 kb
Host smart-c24611d3-89e9-4c31-8b28-84eafbfea5e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853042118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.1853042118
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3494300834
Short name T1079
Test name
Test status
Simulation time 110251999 ps
CPU time 1.46 seconds
Started Mar 28 12:31:12 PM PDT 24
Finished Mar 28 12:31:14 PM PDT 24
Peak memory 202836 kb
Host smart-7f0ffcbb-ce9d-4a03-96b3-c5c7e508e10b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494300834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_
csr_outstanding.3494300834
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1385032010
Short name T241
Test name
Test status
Simulation time 83310708 ps
CPU time 2.64 seconds
Started Mar 28 12:31:22 PM PDT 24
Finished Mar 28 12:31:24 PM PDT 24
Peak memory 202760 kb
Host smart-837b7fce-eec6-49db-a753-1f53b864b5ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1385032010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1385032010
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3990075461
Short name T289
Test name
Test status
Simulation time 216782033 ps
CPU time 2.46 seconds
Started Mar 28 12:31:11 PM PDT 24
Finished Mar 28 12:31:14 PM PDT 24
Peak memory 202804 kb
Host smart-d35f27ce-1c76-4133-ac1a-7f102a0cb857
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3990075461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3990075461
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3294915409
Short name T1083
Test name
Test status
Simulation time 151382579 ps
CPU time 1.73 seconds
Started Mar 28 12:31:24 PM PDT 24
Finished Mar 28 12:31:26 PM PDT 24
Peak memory 218664 kb
Host smart-9eb0eb23-3d19-4b96-b638-99d10b125078
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294915409 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.3294915409
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3082784602
Short name T1108
Test name
Test status
Simulation time 27334844 ps
CPU time 0.8 seconds
Started Mar 28 12:31:24 PM PDT 24
Finished Mar 28 12:31:25 PM PDT 24
Peak memory 202444 kb
Host smart-7187c0c1-d8ec-46b4-9c47-a75ea857d375
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082784602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3082784602
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1468877212
Short name T1137
Test name
Test status
Simulation time 31970242 ps
CPU time 0.63 seconds
Started Mar 28 12:31:16 PM PDT 24
Finished Mar 28 12:31:16 PM PDT 24
Peak memory 202356 kb
Host smart-eb750546-29db-4bd4-95c7-2dfbc3929825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1468877212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.1468877212
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3265862160
Short name T268
Test name
Test status
Simulation time 113998178 ps
CPU time 1.52 seconds
Started Mar 28 12:31:28 PM PDT 24
Finished Mar 28 12:31:29 PM PDT 24
Peak memory 202820 kb
Host smart-7b8d4010-c2c3-45aa-8aae-ae52ff099278
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265862160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_
csr_outstanding.3265862160
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3932475385
Short name T1104
Test name
Test status
Simulation time 95668244 ps
CPU time 1.3 seconds
Started Mar 28 12:31:13 PM PDT 24
Finished Mar 28 12:31:14 PM PDT 24
Peak memory 202816 kb
Host smart-e5880bdd-c90f-4533-99cd-6be16f34942b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3932475385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3932475385
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2754137075
Short name T274
Test name
Test status
Simulation time 138680444 ps
CPU time 1.88 seconds
Started Mar 28 12:31:22 PM PDT 24
Finished Mar 28 12:31:24 PM PDT 24
Peak memory 214344 kb
Host smart-894cb9fa-3c12-4294-ba7f-d1d5a0765ba9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754137075 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.2754137075
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.660749135
Short name T1125
Test name
Test status
Simulation time 50566820 ps
CPU time 0.83 seconds
Started Mar 28 12:31:22 PM PDT 24
Finished Mar 28 12:31:23 PM PDT 24
Peak memory 202716 kb
Host smart-e12fc06f-feae-442b-aae7-6369fb9491a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660749135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.660749135
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.473503387
Short name T1095
Test name
Test status
Simulation time 28560620 ps
CPU time 0.65 seconds
Started Mar 28 12:31:21 PM PDT 24
Finished Mar 28 12:31:22 PM PDT 24
Peak memory 202516 kb
Host smart-b21a854d-b093-44d6-942d-dd27a80dfa51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=473503387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.473503387
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3046841950
Short name T1112
Test name
Test status
Simulation time 137933201 ps
CPU time 1.5 seconds
Started Mar 28 12:31:15 PM PDT 24
Finished Mar 28 12:31:17 PM PDT 24
Peak memory 202924 kb
Host smart-44700792-13ba-48c2-9acd-caccb3b94a86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046841950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_
csr_outstanding.3046841950
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2530744283
Short name T1130
Test name
Test status
Simulation time 50312562 ps
CPU time 1.66 seconds
Started Mar 28 12:31:28 PM PDT 24
Finished Mar 28 12:31:30 PM PDT 24
Peak memory 202760 kb
Host smart-1e02a3bc-1b18-4c77-977b-f022e8429c4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2530744283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.2530744283
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.110124502
Short name T1147
Test name
Test status
Simulation time 63476318 ps
CPU time 1.93 seconds
Started Mar 28 12:31:09 PM PDT 24
Finished Mar 28 12:31:11 PM PDT 24
Peak memory 202996 kb
Host smart-5f01037b-11d4-4fe3-a330-f88335ac9782
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110124502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.110124502
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.377146544
Short name T246
Test name
Test status
Simulation time 39898486 ps
CPU time 1.26 seconds
Started Mar 28 12:30:43 PM PDT 24
Finished Mar 28 12:30:45 PM PDT 24
Peak memory 212220 kb
Host smart-21fbb934-646a-4825-9a76-f1a1e07674cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377146544 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.377146544
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2434959220
Short name T1120
Test name
Test status
Simulation time 33647603 ps
CPU time 0.84 seconds
Started Mar 28 12:31:09 PM PDT 24
Finished Mar 28 12:31:10 PM PDT 24
Peak memory 202552 kb
Host smart-f462feee-1cf8-44f0-9159-fa591a600eb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434959220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2434959220
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2801223179
Short name T1080
Test name
Test status
Simulation time 23527012 ps
CPU time 0.63 seconds
Started Mar 28 12:31:09 PM PDT 24
Finished Mar 28 12:31:10 PM PDT 24
Peak memory 202400 kb
Host smart-5dd6cdb4-1375-469a-85f1-877543a6b600
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2801223179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2801223179
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1937868832
Short name T260
Test name
Test status
Simulation time 89714732 ps
CPU time 1.5 seconds
Started Mar 28 12:31:03 PM PDT 24
Finished Mar 28 12:31:05 PM PDT 24
Peak memory 202780 kb
Host smart-a6503b5e-3da7-44d3-a776-103d7059d40e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1937868832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1937868832
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3846925035
Short name T1071
Test name
Test status
Simulation time 84431150 ps
CPU time 2.18 seconds
Started Mar 28 12:30:48 PM PDT 24
Finished Mar 28 12:30:50 PM PDT 24
Peak memory 202700 kb
Host smart-d7b1678b-4586-45ee-b46e-98b30e2add4c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3846925035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3846925035
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3295240978
Short name T1136
Test name
Test status
Simulation time 114474650 ps
CPU time 1.48 seconds
Started Mar 28 12:31:15 PM PDT 24
Finished Mar 28 12:31:16 PM PDT 24
Peak memory 202968 kb
Host smart-20443248-86ec-4ea9-a0bb-6ed421cdc0eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295240978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c
sr_outstanding.3295240978
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3430435800
Short name T1141
Test name
Test status
Simulation time 227778300 ps
CPU time 3 seconds
Started Mar 28 12:31:14 PM PDT 24
Finished Mar 28 12:31:17 PM PDT 24
Peak memory 202652 kb
Host smart-09a94e18-eb9c-41c1-972b-b2e72f71f8da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3430435800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.3430435800
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.453479173
Short name T1097
Test name
Test status
Simulation time 25370186 ps
CPU time 0.66 seconds
Started Mar 28 12:31:14 PM PDT 24
Finished Mar 28 12:31:15 PM PDT 24
Peak memory 202512 kb
Host smart-fb6ab0e5-fe5e-4ea9-8c9f-5501a78c1943
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=453479173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.453479173
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2020379164
Short name T74
Test name
Test status
Simulation time 26131621 ps
CPU time 0.69 seconds
Started Mar 28 12:31:25 PM PDT 24
Finished Mar 28 12:31:27 PM PDT 24
Peak memory 202368 kb
Host smart-28d5da98-852f-4326-b460-960d3ea55357
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2020379164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2020379164
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2168558098
Short name T1121
Test name
Test status
Simulation time 26694129 ps
CPU time 0.68 seconds
Started Mar 28 12:31:28 PM PDT 24
Finished Mar 28 12:31:28 PM PDT 24
Peak memory 202356 kb
Host smart-11ae0ff0-6643-474b-83b4-064cd48b8435
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2168558098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2168558098
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.783490886
Short name T1117
Test name
Test status
Simulation time 25950083 ps
CPU time 0.7 seconds
Started Mar 28 12:31:22 PM PDT 24
Finished Mar 28 12:31:23 PM PDT 24
Peak memory 202380 kb
Host smart-da8c21fc-9d02-44b1-b9d6-ed3d17122b6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=783490886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.783490886
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1701397298
Short name T1145
Test name
Test status
Simulation time 25663291 ps
CPU time 0.66 seconds
Started Mar 28 12:31:21 PM PDT 24
Finished Mar 28 12:31:21 PM PDT 24
Peak memory 202380 kb
Host smart-dfc374e2-279e-4a1a-b53b-b30a2ea008a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1701397298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.1701397298
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1304821117
Short name T1086
Test name
Test status
Simulation time 22826984 ps
CPU time 0.65 seconds
Started Mar 28 12:31:23 PM PDT 24
Finished Mar 28 12:31:24 PM PDT 24
Peak memory 202296 kb
Host smart-87179de0-25e9-4f56-8f62-0262be3b69de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1304821117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1304821117
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1942694181
Short name T1107
Test name
Test status
Simulation time 25153063 ps
CPU time 0.66 seconds
Started Mar 28 12:31:29 PM PDT 24
Finished Mar 28 12:31:30 PM PDT 24
Peak memory 202368 kb
Host smart-79097e14-df90-4081-a170-c086ccd7fcfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1942694181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.1942694181
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3377715267
Short name T276
Test name
Test status
Simulation time 21371367 ps
CPU time 0.63 seconds
Started Mar 28 12:31:32 PM PDT 24
Finished Mar 28 12:31:32 PM PDT 24
Peak memory 202352 kb
Host smart-6990a889-55aa-4fce-b001-7b5318c25df2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3377715267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3377715267
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1363412566
Short name T275
Test name
Test status
Simulation time 27308052 ps
CPU time 0.61 seconds
Started Mar 28 12:31:20 PM PDT 24
Finished Mar 28 12:31:21 PM PDT 24
Peak memory 202348 kb
Host smart-38c9b626-5e70-412d-9cfe-aaaac8fc0c92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1363412566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1363412566
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1309686380
Short name T261
Test name
Test status
Simulation time 371341692 ps
CPU time 3.44 seconds
Started Mar 28 12:30:45 PM PDT 24
Finished Mar 28 12:30:49 PM PDT 24
Peak memory 202732 kb
Host smart-5a26390a-16b0-425c-8a9d-cac7dfa86103
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309686380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.1309686380
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.140795205
Short name T265
Test name
Test status
Simulation time 281410823 ps
CPU time 6.48 seconds
Started Mar 28 12:30:46 PM PDT 24
Finished Mar 28 12:30:53 PM PDT 24
Peak memory 202796 kb
Host smart-3115d45c-12d9-423f-98c5-770025100a5b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140795205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.140795205
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1616292848
Short name T71
Test name
Test status
Simulation time 34353840 ps
CPU time 0.74 seconds
Started Mar 28 12:31:18 PM PDT 24
Finished Mar 28 12:31:18 PM PDT 24
Peak memory 202460 kb
Host smart-c1d78343-e34b-485c-afc4-faae2d67a33d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616292848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1616292848
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2570947125
Short name T1081
Test name
Test status
Simulation time 78402643 ps
CPU time 2.48 seconds
Started Mar 28 12:30:44 PM PDT 24
Finished Mar 28 12:30:47 PM PDT 24
Peak memory 211096 kb
Host smart-68001ac9-441e-4558-b314-01c9d2bd03f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570947125 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.2570947125
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3020043513
Short name T1096
Test name
Test status
Simulation time 27880465 ps
CPU time 0.8 seconds
Started Mar 28 12:31:09 PM PDT 24
Finished Mar 28 12:31:10 PM PDT 24
Peak memory 202440 kb
Host smart-8c690185-6e44-40cd-a113-ea2ca1fbe366
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020043513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3020043513
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1407059523
Short name T285
Test name
Test status
Simulation time 31177859 ps
CPU time 0.66 seconds
Started Mar 28 12:30:48 PM PDT 24
Finished Mar 28 12:30:50 PM PDT 24
Peak memory 202524 kb
Host smart-6266a81f-3779-4d45-915a-f9c7b5b33b29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1407059523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1407059523
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2381805707
Short name T1140
Test name
Test status
Simulation time 181880845 ps
CPU time 2.32 seconds
Started Mar 28 12:31:01 PM PDT 24
Finished Mar 28 12:31:03 PM PDT 24
Peak memory 210992 kb
Host smart-5ceb99fa-d401-4417-9373-e5e1f3f449a5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2381805707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2381805707
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.4111076929
Short name T240
Test name
Test status
Simulation time 217358620 ps
CPU time 2.93 seconds
Started Mar 28 12:31:21 PM PDT 24
Finished Mar 28 12:31:24 PM PDT 24
Peak memory 202900 kb
Host smart-b0f0e962-ad8d-48ee-bf2e-ecd71a8886c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4111076929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.4111076929
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2336429937
Short name T290
Test name
Test status
Simulation time 299333697 ps
CPU time 2.73 seconds
Started Mar 28 12:31:06 PM PDT 24
Finished Mar 28 12:31:09 PM PDT 24
Peak memory 202968 kb
Host smart-a09f1cf0-89c6-49c9-983a-7208da23bcea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2336429937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2336429937
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2065662823
Short name T78
Test name
Test status
Simulation time 28157029 ps
CPU time 0.64 seconds
Started Mar 28 12:31:31 PM PDT 24
Finished Mar 28 12:31:32 PM PDT 24
Peak memory 202396 kb
Host smart-23a8bb1c-f6cf-4f06-8d97-6888f071006f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2065662823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2065662823
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.814671564
Short name T1128
Test name
Test status
Simulation time 21088706 ps
CPU time 0.61 seconds
Started Mar 28 12:31:23 PM PDT 24
Finished Mar 28 12:31:23 PM PDT 24
Peak memory 202364 kb
Host smart-916a7423-920e-4a41-8121-f13c122f0ad0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=814671564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.814671564
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4172961131
Short name T1134
Test name
Test status
Simulation time 21302478 ps
CPU time 0.75 seconds
Started Mar 28 12:31:27 PM PDT 24
Finished Mar 28 12:31:28 PM PDT 24
Peak memory 202368 kb
Host smart-1e8e3b3c-260f-486b-a016-7f81ad04ed9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4172961131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.4172961131
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1979332936
Short name T279
Test name
Test status
Simulation time 25749450 ps
CPU time 0.66 seconds
Started Mar 28 12:31:30 PM PDT 24
Finished Mar 28 12:31:30 PM PDT 24
Peak memory 202496 kb
Host smart-2bb93842-3f1a-4f3e-968e-aabdc5f9707a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1979332936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1979332936
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.951104731
Short name T105
Test name
Test status
Simulation time 148664357 ps
CPU time 2.09 seconds
Started Mar 28 12:31:18 PM PDT 24
Finished Mar 28 12:31:21 PM PDT 24
Peak memory 202752 kb
Host smart-9ade37cb-89e9-4e8a-91aa-fcbf4d8e4039
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951104731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.951104731
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3285190057
Short name T1090
Test name
Test status
Simulation time 66339615 ps
CPU time 1.81 seconds
Started Mar 28 12:30:48 PM PDT 24
Finished Mar 28 12:30:54 PM PDT 24
Peak memory 211252 kb
Host smart-3e0f9d81-7488-4dc0-913e-05da7f0a3829
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285190057 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.3285190057
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2333080289
Short name T258
Test name
Test status
Simulation time 29128121 ps
CPU time 0.76 seconds
Started Mar 28 12:30:55 PM PDT 24
Finished Mar 28 12:30:56 PM PDT 24
Peak memory 202552 kb
Host smart-1deb58a1-b2cf-4e53-a359-9f66841bfcd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333080289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2333080289
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3957964772
Short name T1144
Test name
Test status
Simulation time 43463789 ps
CPU time 1.31 seconds
Started Mar 28 12:30:43 PM PDT 24
Finished Mar 28 12:30:45 PM PDT 24
Peak memory 202388 kb
Host smart-79640dcf-ea07-4b66-8f14-584599a71719
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3957964772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3957964772
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3319198248
Short name T1101
Test name
Test status
Simulation time 105382361 ps
CPU time 1.43 seconds
Started Mar 28 12:31:02 PM PDT 24
Finished Mar 28 12:31:03 PM PDT 24
Peak memory 202848 kb
Host smart-d836dae6-493c-4453-ab5a-f54b62d89435
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319198248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_c
sr_outstanding.3319198248
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3227275009
Short name T1142
Test name
Test status
Simulation time 90153587 ps
CPU time 2.74 seconds
Started Mar 28 12:31:13 PM PDT 24
Finished Mar 28 12:31:16 PM PDT 24
Peak memory 202760 kb
Host smart-89779dfc-1dc8-4e17-a701-c925f47593ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3227275009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3227275009
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.325532225
Short name T1122
Test name
Test status
Simulation time 23162437 ps
CPU time 0.63 seconds
Started Mar 28 12:31:26 PM PDT 24
Finished Mar 28 12:31:27 PM PDT 24
Peak memory 202384 kb
Host smart-be8dac22-a4c5-47ec-881e-374ebfeca6ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=325532225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.325532225
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1744416049
Short name T281
Test name
Test status
Simulation time 26147390 ps
CPU time 0.66 seconds
Started Mar 28 12:31:19 PM PDT 24
Finished Mar 28 12:31:19 PM PDT 24
Peak memory 202520 kb
Host smart-69dc2d56-53b6-4c99-99c9-64e58e7ff3ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1744416049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.1744416049
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.21491793
Short name T280
Test name
Test status
Simulation time 20403314 ps
CPU time 0.68 seconds
Started Mar 28 12:31:16 PM PDT 24
Finished Mar 28 12:31:16 PM PDT 24
Peak memory 202364 kb
Host smart-1bd8cc67-f5a2-4204-bb69-17e6e355a7b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=21491793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.21491793
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.469366491
Short name T277
Test name
Test status
Simulation time 24114465 ps
CPU time 0.7 seconds
Started Mar 28 12:31:23 PM PDT 24
Finished Mar 28 12:31:24 PM PDT 24
Peak memory 202304 kb
Host smart-cf762202-7e07-4a34-8405-c159acca64aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=469366491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.469366491
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.351831564
Short name T1084
Test name
Test status
Simulation time 80303392 ps
CPU time 1.17 seconds
Started Mar 28 12:30:48 PM PDT 24
Finished Mar 28 12:30:50 PM PDT 24
Peak memory 211036 kb
Host smart-fa935cbe-37b8-44d6-9a63-a9627cc2b324
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351831564 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.351831564
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2714964823
Short name T1106
Test name
Test status
Simulation time 65183739 ps
CPU time 0.96 seconds
Started Mar 28 12:31:19 PM PDT 24
Finished Mar 28 12:31:20 PM PDT 24
Peak memory 202748 kb
Host smart-d1e81f06-370d-42a0-86ac-3d7e28176523
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714964823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.2714964823
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.719232661
Short name T1089
Test name
Test status
Simulation time 30440772 ps
CPU time 0.68 seconds
Started Mar 28 12:31:21 PM PDT 24
Finished Mar 28 12:31:22 PM PDT 24
Peak memory 202376 kb
Host smart-c62dff09-0251-4d28-8735-939b28a23d36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=719232661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.719232661
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2159124044
Short name T106
Test name
Test status
Simulation time 77642041 ps
CPU time 1.12 seconds
Started Mar 28 12:30:47 PM PDT 24
Finished Mar 28 12:30:48 PM PDT 24
Peak memory 202768 kb
Host smart-197cb4d3-46f9-46ef-85be-173e050115b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159124044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c
sr_outstanding.2159124044
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.4167429170
Short name T61
Test name
Test status
Simulation time 138639684 ps
CPU time 1.65 seconds
Started Mar 28 12:31:12 PM PDT 24
Finished Mar 28 12:31:15 PM PDT 24
Peak memory 202724 kb
Host smart-46289064-9972-4ea0-b8c3-9c5fc9e71038
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4167429170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.4167429170
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3050002305
Short name T1148
Test name
Test status
Simulation time 67596364 ps
CPU time 2.25 seconds
Started Mar 28 12:31:11 PM PDT 24
Finished Mar 28 12:31:13 PM PDT 24
Peak memory 210960 kb
Host smart-e3ce6cb3-4a30-4280-80f4-a0c7e2cb8a3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050002305 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.3050002305
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3314135895
Short name T263
Test name
Test status
Simulation time 59545939 ps
CPU time 1.03 seconds
Started Mar 28 12:31:16 PM PDT 24
Finished Mar 28 12:31:17 PM PDT 24
Peak memory 202752 kb
Host smart-63d00b53-1286-4b93-b2b0-470e3938e479
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314135895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3314135895
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.37944491
Short name T75
Test name
Test status
Simulation time 25914809 ps
CPU time 0.64 seconds
Started Mar 28 12:31:31 PM PDT 24
Finished Mar 28 12:31:32 PM PDT 24
Peak memory 202336 kb
Host smart-5c1dc465-0f55-44a8-abb9-7d0a3f1fd0e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=37944491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.37944491
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4246348268
Short name T1098
Test name
Test status
Simulation time 91878935 ps
CPU time 1.04 seconds
Started Mar 28 12:31:18 PM PDT 24
Finished Mar 28 12:31:20 PM PDT 24
Peak memory 202836 kb
Host smart-dc04056d-d602-41c0-bdb9-ab76cc874131
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246348268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c
sr_outstanding.4246348268
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.866322289
Short name T245
Test name
Test status
Simulation time 141802304 ps
CPU time 1.83 seconds
Started Mar 28 12:30:45 PM PDT 24
Finished Mar 28 12:30:48 PM PDT 24
Peak memory 202676 kb
Host smart-211ecd6c-e800-4f22-a9d7-08318961c74b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=866322289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.866322289
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1121337742
Short name T1091
Test name
Test status
Simulation time 114610318 ps
CPU time 1.62 seconds
Started Mar 28 12:31:28 PM PDT 24
Finished Mar 28 12:31:30 PM PDT 24
Peak memory 213804 kb
Host smart-a8b16eb8-3df3-4e59-8437-23166f5604ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121337742 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.1121337742
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1796573386
Short name T273
Test name
Test status
Simulation time 46039454 ps
CPU time 0.88 seconds
Started Mar 28 12:31:20 PM PDT 24
Finished Mar 28 12:31:21 PM PDT 24
Peak memory 202444 kb
Host smart-30cff391-2253-4ec0-a54f-6660e08d1194
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796573386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1796573386
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3769561572
Short name T1138
Test name
Test status
Simulation time 84899513 ps
CPU time 1.07 seconds
Started Mar 28 12:31:15 PM PDT 24
Finished Mar 28 12:31:17 PM PDT 24
Peak memory 202704 kb
Host smart-9a14e1fa-d866-4d78-addd-b4b3b231f2dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769561572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_c
sr_outstanding.3769561572
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.4080751319
Short name T243
Test name
Test status
Simulation time 173604995 ps
CPU time 2.3 seconds
Started Mar 28 12:31:21 PM PDT 24
Finished Mar 28 12:31:24 PM PDT 24
Peak memory 202816 kb
Host smart-3fef6135-6dc7-4d3f-8c63-42523173a3a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4080751319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.4080751319
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2864660125
Short name T1124
Test name
Test status
Simulation time 439747258 ps
CPU time 4.91 seconds
Started Mar 28 12:31:29 PM PDT 24
Finished Mar 28 12:31:34 PM PDT 24
Peak memory 202856 kb
Host smart-64857900-3340-4ae2-a12f-930b8f8e5619
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2864660125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.2864660125
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.525060670
Short name T1087
Test name
Test status
Simulation time 77368078 ps
CPU time 1.37 seconds
Started Mar 28 12:31:22 PM PDT 24
Finished Mar 28 12:31:23 PM PDT 24
Peak memory 211032 kb
Host smart-e4c53d6d-c737-4ecf-b435-ed108b7ce896
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525060670 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.525060670
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2854744339
Short name T107
Test name
Test status
Simulation time 37820079 ps
CPU time 0.79 seconds
Started Mar 28 12:31:21 PM PDT 24
Finished Mar 28 12:31:22 PM PDT 24
Peak memory 202444 kb
Host smart-e9998582-3168-445d-a1f0-9912ee28019e
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854744339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2854744339
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2929675815
Short name T76
Test name
Test status
Simulation time 22713235 ps
CPU time 0.65 seconds
Started Mar 28 12:31:18 PM PDT 24
Finished Mar 28 12:31:19 PM PDT 24
Peak memory 202364 kb
Host smart-81942a28-a90c-4589-9c18-d77c2297b195
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2929675815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2929675815
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3038087102
Short name T1094
Test name
Test status
Simulation time 52703570 ps
CPU time 1.3 seconds
Started Mar 28 12:31:13 PM PDT 24
Finished Mar 28 12:31:15 PM PDT 24
Peak memory 202860 kb
Host smart-ff207b2f-5531-4252-a395-7a65ee55232f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038087102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_c
sr_outstanding.3038087102
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2074719845
Short name T1105
Test name
Test status
Simulation time 336623282 ps
CPU time 3.58 seconds
Started Mar 28 12:31:21 PM PDT 24
Finished Mar 28 12:31:25 PM PDT 24
Peak memory 202784 kb
Host smart-3d684ee4-38f1-4fc1-9273-f5893eccd344
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2074719845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2074719845
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1681589091
Short name T291
Test name
Test status
Simulation time 467941511 ps
CPU time 4.34 seconds
Started Mar 28 12:31:20 PM PDT 24
Finished Mar 28 12:31:25 PM PDT 24
Peak memory 202844 kb
Host smart-5405d489-eacc-42ec-b6a5-0b07b75959f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1681589091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.1681589091
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2747170017
Short name T1093
Test name
Test status
Simulation time 38042121 ps
CPU time 1.21 seconds
Started Mar 28 12:31:21 PM PDT 24
Finished Mar 28 12:31:23 PM PDT 24
Peak memory 210948 kb
Host smart-b9084901-156f-4a2c-b8a5-2e0803c95b3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747170017 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.2747170017
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1500282600
Short name T1132
Test name
Test status
Simulation time 41552523 ps
CPU time 0.77 seconds
Started Mar 28 12:31:20 PM PDT 24
Finished Mar 28 12:31:21 PM PDT 24
Peak memory 202528 kb
Host smart-a047a034-eac6-4ac0-8bb2-e1b0454a6708
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500282600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1500282600
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2218580756
Short name T1110
Test name
Test status
Simulation time 73542181 ps
CPU time 1.13 seconds
Started Mar 28 12:31:22 PM PDT 24
Finished Mar 28 12:31:23 PM PDT 24
Peak memory 202848 kb
Host smart-175e3a3b-3986-4583-8fbf-8cbaec2eb447
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218580756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_c
sr_outstanding.2218580756
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2342775993
Short name T1115
Test name
Test status
Simulation time 222827527 ps
CPU time 2.51 seconds
Started Mar 28 12:31:28 PM PDT 24
Finished Mar 28 12:31:31 PM PDT 24
Peak memory 202788 kb
Host smart-c61bab5e-1e6d-4040-a627-e428be34f5a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2342775993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2342775993
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3541758756
Short name T244
Test name
Test status
Simulation time 234708055 ps
CPU time 2.56 seconds
Started Mar 28 12:31:25 PM PDT 24
Finished Mar 28 12:31:28 PM PDT 24
Peak memory 202716 kb
Host smart-65420896-49fc-440f-9ffa-0a1b3aa21d28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3541758756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3541758756
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.in_iso.1255623023
Short name T378
Test name
Test status
Simulation time 8425242632 ps
CPU time 7.43 seconds
Started Mar 28 01:32:24 PM PDT 24
Finished Mar 28 01:32:32 PM PDT 24
Peak memory 203932 kb
Host smart-31d401f6-4e42-4cc0-90f3-27f54cc162b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12556
23023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.in_iso.1255623023
Directory /workspace/0.in_iso/latest

Test location /workspace/coverage/default/0.phy_config_usb_ref_disable.2287494035
Short name T884
Test name
Test status
Simulation time 8366380220 ps
CPU time 7.45 seconds
Started Mar 28 01:32:19 PM PDT 24
Finished Mar 28 01:32:27 PM PDT 24
Peak memory 204044 kb
Host smart-de03693b-05c2-4358-9afd-a9d3f885f749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22874
94035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.phy_config_usb_ref_disable.2287494035
Directory /workspace/0.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.2832306062
Short name T800
Test name
Test status
Simulation time 8367401182 ps
CPU time 7.82 seconds
Started Mar 28 01:32:29 PM PDT 24
Finished Mar 28 01:32:38 PM PDT 24
Peak memory 204052 kb
Host smart-2fcd7547-0ab6-40f1-9028-2d0495748590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28323
06062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.2832306062
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_enable.3768467218
Short name T998
Test name
Test status
Simulation time 8374564758 ps
CPU time 10.12 seconds
Started Mar 28 01:32:29 PM PDT 24
Finished Mar 28 01:32:39 PM PDT 24
Peak memory 204036 kb
Host smart-3f7fd4f9-92a8-4a4c-813e-d4d310eda972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37684
67218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.3768467218
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.960626772
Short name T749
Test name
Test status
Simulation time 283479376 ps
CPU time 2.32 seconds
Started Mar 28 01:32:28 PM PDT 24
Finished Mar 28 01:32:30 PM PDT 24
Peak memory 204132 kb
Host smart-0947a436-041a-466c-932f-84c5ed9821e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96062
6772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.960626772
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.3975140901
Short name T612
Test name
Test status
Simulation time 8397980706 ps
CPU time 9.4 seconds
Started Mar 28 01:32:19 PM PDT 24
Finished Mar 28 01:32:29 PM PDT 24
Peak memory 204052 kb
Host smart-9cbe4b1f-7769-4bcd-9701-ad46d8884d64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39751
40901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.3975140901
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.133880219
Short name T793
Test name
Test status
Simulation time 8410613085 ps
CPU time 7.31 seconds
Started Mar 28 01:32:19 PM PDT 24
Finished Mar 28 01:32:27 PM PDT 24
Peak memory 204048 kb
Host smart-b91a5406-04cf-465a-a301-169789fb3cee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13388
0219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.133880219
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.1400563374
Short name T559
Test name
Test status
Simulation time 8362863354 ps
CPU time 7.53 seconds
Started Mar 28 01:32:24 PM PDT 24
Finished Mar 28 01:32:32 PM PDT 24
Peak memory 203900 kb
Host smart-bbd18a56-e842-4cf5-a3eb-14d40baf581f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14005
63374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.1400563374
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.41585020
Short name T360
Test name
Test status
Simulation time 8373328602 ps
CPU time 9.29 seconds
Started Mar 28 01:32:29 PM PDT 24
Finished Mar 28 01:32:38 PM PDT 24
Peak memory 204076 kb
Host smart-8bdc8597-4513-4602-991d-a003ee9988a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41585
020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.41585020
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2365954278
Short name T765
Test name
Test status
Simulation time 8373773811 ps
CPU time 8.5 seconds
Started Mar 28 01:32:26 PM PDT 24
Finished Mar 28 01:32:35 PM PDT 24
Peak memory 204024 kb
Host smart-92b5c1c7-d700-4be5-bf56-d526dd073888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23659
54278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2365954278
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.2318058883
Short name T544
Test name
Test status
Simulation time 25128320887 ps
CPU time 46.9 seconds
Started Mar 28 01:32:15 PM PDT 24
Finished Mar 28 01:33:02 PM PDT 24
Peak memory 204344 kb
Host smart-7596b28b-ce55-4add-8c4d-3b87db938783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23180
58883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.2318058883
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.1180951275
Short name T970
Test name
Test status
Simulation time 8374592893 ps
CPU time 7.67 seconds
Started Mar 28 01:32:26 PM PDT 24
Finished Mar 28 01:32:34 PM PDT 24
Peak memory 204016 kb
Host smart-dd87731c-972d-4972-ae15-76b25fb452b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11809
51275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.1180951275
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.4045358409
Short name T40
Test name
Test status
Simulation time 8411105610 ps
CPU time 7.26 seconds
Started Mar 28 01:32:26 PM PDT 24
Finished Mar 28 01:32:34 PM PDT 24
Peak memory 204020 kb
Host smart-58da83f5-e533-4f96-a0ff-1d1a881388d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40453
58409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.4045358409
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.3399571999
Short name T832
Test name
Test status
Simulation time 8391921494 ps
CPU time 7.41 seconds
Started Mar 28 01:32:28 PM PDT 24
Finished Mar 28 01:32:36 PM PDT 24
Peak memory 203956 kb
Host smart-8113907b-4a39-4f5b-ad39-f8141aaf7031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33995
71999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.3399571999
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.803813733
Short name T577
Test name
Test status
Simulation time 8357457758 ps
CPU time 8.63 seconds
Started Mar 28 01:32:19 PM PDT 24
Finished Mar 28 01:32:28 PM PDT 24
Peak memory 204068 kb
Host smart-74aa83a2-f88b-409e-9e6e-1c2634a13e35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80381
3733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.803813733
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.4019726925
Short name T886
Test name
Test status
Simulation time 8420675882 ps
CPU time 8.06 seconds
Started Mar 28 01:32:27 PM PDT 24
Finished Mar 28 01:32:35 PM PDT 24
Peak memory 204020 kb
Host smart-6f1d69f8-1e5b-4c63-9d74-59a6f94281da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40197
26925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.4019726925
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.3179993769
Short name T650
Test name
Test status
Simulation time 8372598273 ps
CPU time 8.38 seconds
Started Mar 28 01:32:29 PM PDT 24
Finished Mar 28 01:32:37 PM PDT 24
Peak memory 204080 kb
Host smart-af03b96a-039e-44ad-9333-be11c78d823f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31799
93769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.3179993769
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.in_iso.3107856219
Short name T815
Test name
Test status
Simulation time 8423873833 ps
CPU time 7.57 seconds
Started Mar 28 01:32:35 PM PDT 24
Finished Mar 28 01:32:43 PM PDT 24
Peak memory 204116 kb
Host smart-688cf8b4-cf70-4d03-b287-b69a06be3d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31078
56219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.in_iso.3107856219
Directory /workspace/1.in_iso/latest

Test location /workspace/coverage/default/1.phy_config_usb_ref_disable.2685743654
Short name T9
Test name
Test status
Simulation time 8358812184 ps
CPU time 8.19 seconds
Started Mar 28 01:32:39 PM PDT 24
Finished Mar 28 01:32:47 PM PDT 24
Peak memory 204052 kb
Host smart-b8d88f60-0076-4c92-b282-5816ea7e5936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26857
43654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.phy_config_usb_ref_disable.2685743654
Directory /workspace/1.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1946539193
Short name T964
Test name
Test status
Simulation time 8367412694 ps
CPU time 7.66 seconds
Started Mar 28 01:32:30 PM PDT 24
Finished Mar 28 01:32:38 PM PDT 24
Peak memory 204024 kb
Host smart-efc3d866-2d5e-411f-b557-03aece55dc5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19465
39193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1946539193
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_enable.533094372
Short name T754
Test name
Test status
Simulation time 8370589177 ps
CPU time 7.63 seconds
Started Mar 28 01:32:30 PM PDT 24
Finished Mar 28 01:32:38 PM PDT 24
Peak memory 203996 kb
Host smart-b1ec3ed4-88de-422a-8770-877a29e9f419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53309
4372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.533094372
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.897805377
Short name T582
Test name
Test status
Simulation time 53374063 ps
CPU time 1.36 seconds
Started Mar 28 01:32:28 PM PDT 24
Finished Mar 28 01:32:29 PM PDT 24
Peak memory 204128 kb
Host smart-093c2ad4-e255-4e58-b42e-a57f810e3fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89780
5377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.897805377
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.1136643582
Short name T216
Test name
Test status
Simulation time 8364658960 ps
CPU time 8.28 seconds
Started Mar 28 01:32:35 PM PDT 24
Finished Mar 28 01:32:43 PM PDT 24
Peak memory 204020 kb
Host smart-859c4fa7-4a90-4e4f-8071-ce822961be63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11366
43582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.1136643582
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.3108302674
Short name T819
Test name
Test status
Simulation time 8414688988 ps
CPU time 7.34 seconds
Started Mar 28 01:32:28 PM PDT 24
Finished Mar 28 01:32:35 PM PDT 24
Peak memory 203952 kb
Host smart-ebf3cd9a-9d64-4b4c-a444-8b0675c3ecdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31083
02674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.3108302674
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.89214465
Short name T542
Test name
Test status
Simulation time 8415003301 ps
CPU time 7.91 seconds
Started Mar 28 01:32:29 PM PDT 24
Finished Mar 28 01:32:37 PM PDT 24
Peak memory 204056 kb
Host smart-6a7ee148-be33-4206-a737-bb62fca8af9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89214
465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.89214465
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.76870646
Short name T939
Test name
Test status
Simulation time 8365588205 ps
CPU time 8.51 seconds
Started Mar 28 01:32:27 PM PDT 24
Finished Mar 28 01:32:36 PM PDT 24
Peak memory 204032 kb
Host smart-ce20f0a9-c8a2-4a47-aa5a-80310f601135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76870
646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.76870646
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.2115698597
Short name T938
Test name
Test status
Simulation time 8374922908 ps
CPU time 9.56 seconds
Started Mar 28 01:32:28 PM PDT 24
Finished Mar 28 01:32:38 PM PDT 24
Peak memory 203960 kb
Host smart-6b712498-82d7-4715-8abd-7f462f89c93a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21156
98597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2115698597
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.3958138081
Short name T473
Test name
Test status
Simulation time 8379645232 ps
CPU time 7.3 seconds
Started Mar 28 01:32:27 PM PDT 24
Finished Mar 28 01:32:35 PM PDT 24
Peak memory 203960 kb
Host smart-70065254-7cea-4f2a-9648-61be1b81dbd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39581
38081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3958138081
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.2555102458
Short name T49
Test name
Test status
Simulation time 24618117 ps
CPU time 0.65 seconds
Started Mar 28 01:32:40 PM PDT 24
Finished Mar 28 01:32:41 PM PDT 24
Peak memory 203996 kb
Host smart-f214cf5d-3dae-4350-95a8-4d1b2a54ce43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25551
02458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.2555102458
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.3580615491
Short name T187
Test name
Test status
Simulation time 19036466161 ps
CPU time 32.51 seconds
Started Mar 28 01:32:27 PM PDT 24
Finished Mar 28 01:33:00 PM PDT 24
Peak memory 204220 kb
Host smart-b04868cb-f32a-47d8-b889-99bba887fa6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35806
15491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.3580615491
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.1272692980
Short name T388
Test name
Test status
Simulation time 8391260143 ps
CPU time 8.03 seconds
Started Mar 28 01:32:30 PM PDT 24
Finished Mar 28 01:32:38 PM PDT 24
Peak memory 204072 kb
Host smart-8ade6bdc-4739-488f-aba5-b8f4b7cf51aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12726
92980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.1272692980
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.3817626808
Short name T776
Test name
Test status
Simulation time 8382715090 ps
CPU time 7.24 seconds
Started Mar 28 01:32:36 PM PDT 24
Finished Mar 28 01:32:44 PM PDT 24
Peak memory 204052 kb
Host smart-4bd2674c-2e70-4cfd-82ba-2cbbea196df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38176
26808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.3817626808
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.1242461241
Short name T537
Test name
Test status
Simulation time 8366637353 ps
CPU time 7.04 seconds
Started Mar 28 01:32:39 PM PDT 24
Finished Mar 28 01:32:46 PM PDT 24
Peak memory 203412 kb
Host smart-1b3b0ce9-75a4-4da3-99cc-db52c0270b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12424
61241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.1242461241
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.3444024879
Short name T63
Test name
Test status
Simulation time 143701035 ps
CPU time 1.04 seconds
Started Mar 28 01:32:37 PM PDT 24
Finished Mar 28 01:32:39 PM PDT 24
Peak memory 220964 kb
Host smart-19ed0e76-7d32-46e8-8c07-8fd80a85ff1b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3444024879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.3444024879
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.310606212
Short name T909
Test name
Test status
Simulation time 8357717207 ps
CPU time 8.17 seconds
Started Mar 28 01:32:45 PM PDT 24
Finished Mar 28 01:32:54 PM PDT 24
Peak memory 204048 kb
Host smart-3cdc321e-b1ab-4842-aded-2746c3abd55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31060
6212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.310606212
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.319374961
Short name T417
Test name
Test status
Simulation time 8374858263 ps
CPU time 7.54 seconds
Started Mar 28 01:32:41 PM PDT 24
Finished Mar 28 01:32:48 PM PDT 24
Peak memory 204036 kb
Host smart-a33f86e0-9a68-4514-b31d-c8c10761abfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31937
4961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.319374961
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.in_iso.3014901096
Short name T893
Test name
Test status
Simulation time 8428618021 ps
CPU time 7.87 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:29 PM PDT 24
Peak memory 204084 kb
Host smart-1496c1de-6c67-4d56-ab98-ccf23736e525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30149
01096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.in_iso.3014901096
Directory /workspace/10.in_iso/latest

Test location /workspace/coverage/default/10.phy_config_usb_ref_disable.4274711909
Short name T545
Test name
Test status
Simulation time 8364125954 ps
CPU time 9.03 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:32 PM PDT 24
Peak memory 204044 kb
Host smart-86e45110-395e-495a-84c4-da26afe2609d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42747
11909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.phy_config_usb_ref_disable.4274711909
Directory /workspace/10.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.1785987138
Short name T531
Test name
Test status
Simulation time 8367663615 ps
CPU time 7.54 seconds
Started Mar 28 01:33:19 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 204052 kb
Host smart-61e18dd1-b919-4b11-842b-2003c13c0028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17859
87138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.1785987138
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_enable.2977124154
Short name T724
Test name
Test status
Simulation time 8372372651 ps
CPU time 8.02 seconds
Started Mar 28 01:33:20 PM PDT 24
Finished Mar 28 01:33:29 PM PDT 24
Peak memory 204080 kb
Host smart-968609cb-a6bd-4af9-9c5a-e9f1a961892e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29771
24154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.2977124154
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.1963727199
Short name T59
Test name
Test status
Simulation time 93502505 ps
CPU time 1.23 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 204136 kb
Host smart-ffd1769a-4aef-48cf-9490-3d12748cb738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19637
27199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.1963727199
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.52989710
Short name T641
Test name
Test status
Simulation time 8410460460 ps
CPU time 9.87 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:34 PM PDT 24
Peak memory 203960 kb
Host smart-288cc5d1-fb4c-47b2-9cf3-dadb15395ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52989
710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.52989710
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.1546608971
Short name T794
Test name
Test status
Simulation time 8365612547 ps
CPU time 7.35 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:34 PM PDT 24
Peak memory 203964 kb
Host smart-219f68e6-6643-4106-aeb7-40b2f6554193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15466
08971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.1546608971
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.343626763
Short name T370
Test name
Test status
Simulation time 8365736952 ps
CPU time 8.29 seconds
Started Mar 28 01:33:22 PM PDT 24
Finished Mar 28 01:33:32 PM PDT 24
Peak memory 204048 kb
Host smart-de17b52f-6097-4205-9d2c-227f04f43217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34362
6763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.343626763
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.3326867163
Short name T304
Test name
Test status
Simulation time 8402876386 ps
CPU time 7.33 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:30 PM PDT 24
Peak memory 204052 kb
Host smart-ca30777a-33e0-41ba-a510-cf62e2d431c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33268
67163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.3326867163
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.76724845
Short name T629
Test name
Test status
Simulation time 31693302 ps
CPU time 0.62 seconds
Started Mar 28 01:33:24 PM PDT 24
Finished Mar 28 01:33:29 PM PDT 24
Peak memory 204064 kb
Host smart-20e4f227-afc1-4617-b437-59873793900f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76724
845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.76724845
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.4179645605
Short name T637
Test name
Test status
Simulation time 24144342260 ps
CPU time 41.17 seconds
Started Mar 28 01:33:22 PM PDT 24
Finished Mar 28 01:34:09 PM PDT 24
Peak memory 204312 kb
Host smart-9771cf91-216d-44ad-ac04-577929186cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41796
45605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.4179645605
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.1429915229
Short name T622
Test name
Test status
Simulation time 8404483726 ps
CPU time 7.77 seconds
Started Mar 28 01:33:22 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 204040 kb
Host smart-487564ec-b419-48f7-a4d3-f66dff4f1388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14299
15229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.1429915229
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.1846702852
Short name T662
Test name
Test status
Simulation time 8378478036 ps
CPU time 7.04 seconds
Started Mar 28 01:33:13 PM PDT 24
Finished Mar 28 01:33:21 PM PDT 24
Peak memory 204056 kb
Host smart-07ebc9b4-d589-4d7c-bd32-c197d53ecb39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18467
02852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.1846702852
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.82472491
Short name T1010
Test name
Test status
Simulation time 8387101736 ps
CPU time 7.44 seconds
Started Mar 28 01:33:22 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 204052 kb
Host smart-3ef82d27-c4fe-4f37-83f3-16bbd4e1a6ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82472
491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.82472491
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.2689910025
Short name T812
Test name
Test status
Simulation time 8390939561 ps
CPU time 7.66 seconds
Started Mar 28 01:33:23 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 204124 kb
Host smart-326436a6-57e0-420f-a01c-c770364748b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26899
10025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.2689910025
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.phy_config_usb_ref_disable.253780788
Short name T902
Test name
Test status
Simulation time 8366072866 ps
CPU time 8.55 seconds
Started Mar 28 01:33:25 PM PDT 24
Finished Mar 28 01:33:37 PM PDT 24
Peak memory 204028 kb
Host smart-e4b6e11c-29ae-4d24-8b24-ee002588b10c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25378
0788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.phy_config_usb_ref_disable.253780788
Directory /workspace/11.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.3932670267
Short name T481
Test name
Test status
Simulation time 8370600005 ps
CPU time 7.17 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:31 PM PDT 24
Peak memory 204084 kb
Host smart-70a791b5-32b4-4e3c-8e1c-acaa2cb6d054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39326
70267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.3932670267
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_enable.4168082606
Short name T1069
Test name
Test status
Simulation time 8369738557 ps
CPU time 8.65 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:32 PM PDT 24
Peak memory 204068 kb
Host smart-f0c1ed0d-3344-4d3e-b0f4-8fcbc09deeb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41680
82606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.4168082606
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.1796686666
Short name T951
Test name
Test status
Simulation time 154598554 ps
CPU time 1.66 seconds
Started Mar 28 01:33:24 PM PDT 24
Finished Mar 28 01:33:30 PM PDT 24
Peak memory 204104 kb
Host smart-64b1f59b-fc87-421b-bb07-bff8044747c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17966
86666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.1796686666
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.1027136307
Short name T6
Test name
Test status
Simulation time 8358315615 ps
CPU time 7.24 seconds
Started Mar 28 01:33:25 PM PDT 24
Finished Mar 28 01:33:36 PM PDT 24
Peak memory 204088 kb
Host smart-21fc8931-aaa1-453f-a2aa-ad97b8dfc05a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10271
36307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.1027136307
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.4017027049
Short name T333
Test name
Test status
Simulation time 8435346190 ps
CPU time 7.04 seconds
Started Mar 28 01:33:15 PM PDT 24
Finished Mar 28 01:33:22 PM PDT 24
Peak memory 204076 kb
Host smart-6b09d337-851e-47de-92ae-8666e9b0112d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40170
27049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.4017027049
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.3428309849
Short name T1039
Test name
Test status
Simulation time 8413279651 ps
CPU time 7.94 seconds
Started Mar 28 01:33:23 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 203764 kb
Host smart-d55f8003-1dec-4df5-ad10-60a98b49379e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34283
09849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.3428309849
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.1768842651
Short name T270
Test name
Test status
Simulation time 8364240368 ps
CPU time 6.9 seconds
Started Mar 28 01:33:24 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 204068 kb
Host smart-2bd88e6f-e1d9-4bd4-8796-12cae488c412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17688
42651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.1768842651
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.3366178652
Short name T483
Test name
Test status
Simulation time 8387201331 ps
CPU time 7.18 seconds
Started Mar 28 01:33:23 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 203740 kb
Host smart-7dae7bc0-2ce4-47d7-8343-e650d2f61aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33661
78652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.3366178652
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.2493192344
Short name T1048
Test name
Test status
Simulation time 8363152212 ps
CPU time 9.24 seconds
Started Mar 28 01:33:23 PM PDT 24
Finished Mar 28 01:33:37 PM PDT 24
Peak memory 204092 kb
Host smart-a0adbb1a-90dc-4abc-8053-84d81846caff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24931
92344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.2493192344
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.2338507812
Short name T424
Test name
Test status
Simulation time 22148469 ps
CPU time 0.65 seconds
Started Mar 28 01:33:26 PM PDT 24
Finished Mar 28 01:33:29 PM PDT 24
Peak memory 203968 kb
Host smart-bee077b9-5897-44ec-9d5a-0259cbc081ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23385
07812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.2338507812
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.537775842
Short name T14
Test name
Test status
Simulation time 24643793217 ps
CPU time 42.8 seconds
Started Mar 28 01:33:23 PM PDT 24
Finished Mar 28 01:34:10 PM PDT 24
Peak memory 204352 kb
Host smart-b2da87c9-ff9e-40e6-a875-ace0744a5d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53777
5842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.537775842
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.211439896
Short name T961
Test name
Test status
Simulation time 8379958517 ps
CPU time 7.56 seconds
Started Mar 28 01:33:25 PM PDT 24
Finished Mar 28 01:33:36 PM PDT 24
Peak memory 204020 kb
Host smart-41e1ba3f-72cc-4127-b778-a61e90cd0f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21143
9896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.211439896
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.1329590241
Short name T39
Test name
Test status
Simulation time 8420039168 ps
CPU time 7.43 seconds
Started Mar 28 01:33:23 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 204000 kb
Host smart-30fdef35-6d12-4243-92c0-b5d6005bd4c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13295
90241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.1329590241
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.3046626473
Short name T440
Test name
Test status
Simulation time 8402323498 ps
CPU time 8.25 seconds
Started Mar 28 01:33:26 PM PDT 24
Finished Mar 28 01:33:37 PM PDT 24
Peak memory 204096 kb
Host smart-89f31b46-65f0-4e7c-a238-aa99d5601019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30466
26473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.3046626473
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.1454781305
Short name T31
Test name
Test status
Simulation time 8356174794 ps
CPU time 6.93 seconds
Started Mar 28 01:33:25 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 204104 kb
Host smart-1694a1a8-85f6-4d7c-aebc-4734d7b2c839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14547
81305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.1454781305
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.in_iso.2362834381
Short name T367
Test name
Test status
Simulation time 8384034787 ps
CPU time 7.62 seconds
Started Mar 28 01:33:20 PM PDT 24
Finished Mar 28 01:33:29 PM PDT 24
Peak memory 204060 kb
Host smart-3aa8ba23-6b0f-4550-899f-089258f0dbfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23628
34381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.in_iso.2362834381
Directory /workspace/12.in_iso/latest

Test location /workspace/coverage/default/12.phy_config_usb_ref_disable.1497078644
Short name T877
Test name
Test status
Simulation time 8362141505 ps
CPU time 7.41 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:31 PM PDT 24
Peak memory 204036 kb
Host smart-f3cdfa7f-6fce-4f94-9c2f-10739999094a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14970
78644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.phy_config_usb_ref_disable.1497078644
Directory /workspace/12.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.1679075751
Short name T611
Test name
Test status
Simulation time 8367897507 ps
CPU time 7.86 seconds
Started Mar 28 01:33:20 PM PDT 24
Finished Mar 28 01:33:29 PM PDT 24
Peak memory 203980 kb
Host smart-8efb2c99-4b56-45d2-92b8-7ed02cabc00d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16790
75751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.1679075751
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_enable.2112459649
Short name T610
Test name
Test status
Simulation time 8373435444 ps
CPU time 7.36 seconds
Started Mar 28 01:33:18 PM PDT 24
Finished Mar 28 01:33:27 PM PDT 24
Peak memory 204040 kb
Host smart-23fdb251-5d4e-45bc-8142-d288352d3cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21124
59649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.2112459649
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.2811796714
Short name T1018
Test name
Test status
Simulation time 43434102 ps
CPU time 1.33 seconds
Started Mar 28 01:33:20 PM PDT 24
Finished Mar 28 01:33:22 PM PDT 24
Peak memory 204000 kb
Host smart-ed8bd7a9-5ce2-4dd9-952d-f963138e45f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28117
96714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2811796714
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.2189140964
Short name T195
Test name
Test status
Simulation time 8359646820 ps
CPU time 7.24 seconds
Started Mar 28 01:33:22 PM PDT 24
Finished Mar 28 01:33:34 PM PDT 24
Peak memory 203912 kb
Host smart-d70b8ed4-45f0-4b83-a0d0-c9e39a369b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21891
40964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.2189140964
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.3933382055
Short name T843
Test name
Test status
Simulation time 8378483916 ps
CPU time 9.53 seconds
Started Mar 28 01:33:13 PM PDT 24
Finished Mar 28 01:33:23 PM PDT 24
Peak memory 204024 kb
Host smart-df5619c5-55d5-4bb1-80af-eee11d4dee06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39333
82055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.3933382055
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.1528067506
Short name T950
Test name
Test status
Simulation time 8366174091 ps
CPU time 7.68 seconds
Started Mar 28 01:33:18 PM PDT 24
Finished Mar 28 01:33:27 PM PDT 24
Peak memory 204064 kb
Host smart-72790076-aa8c-4cef-9141-8493b48e915b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15280
67506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.1528067506
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.3145485581
Short name T640
Test name
Test status
Simulation time 8386273831 ps
CPU time 7.49 seconds
Started Mar 28 01:33:19 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 204120 kb
Host smart-aea2f846-a8d4-4ceb-ac87-c24d611eb3fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31454
85581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.3145485581
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.3689136769
Short name T380
Test name
Test status
Simulation time 8399882197 ps
CPU time 7.56 seconds
Started Mar 28 01:33:17 PM PDT 24
Finished Mar 28 01:33:25 PM PDT 24
Peak memory 204116 kb
Host smart-b6ba16a3-d9b1-4b8d-bf40-0d4cae90455e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36891
36769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.3689136769
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.3846964256
Short name T328
Test name
Test status
Simulation time 25810094 ps
CPU time 0.66 seconds
Started Mar 28 01:33:20 PM PDT 24
Finished Mar 28 01:33:21 PM PDT 24
Peak memory 203992 kb
Host smart-0f6522a9-3734-45e8-8fbf-cdbc7388b34d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38469
64256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.3846964256
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.3732661346
Short name T103
Test name
Test status
Simulation time 29281760318 ps
CPU time 60.21 seconds
Started Mar 28 01:33:19 PM PDT 24
Finished Mar 28 01:34:21 PM PDT 24
Peak memory 204348 kb
Host smart-1aedd9dc-aa1a-4a43-8f1e-cfd3a8e91ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37326
61346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.3732661346
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.408383990
Short name T311
Test name
Test status
Simulation time 8375839186 ps
CPU time 7.68 seconds
Started Mar 28 01:33:22 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 204048 kb
Host smart-a459fcfe-3a8f-42f6-aee7-1d3557357edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40838
3990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.408383990
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3759319671
Short name T705
Test name
Test status
Simulation time 8455487413 ps
CPU time 7.81 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:32 PM PDT 24
Peak memory 203952 kb
Host smart-bfb8758d-dd02-48a4-bd3d-5df486e375a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37593
19671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3759319671
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.1196148543
Short name T1058
Test name
Test status
Simulation time 8399149626 ps
CPU time 7.88 seconds
Started Mar 28 01:33:22 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 203972 kb
Host smart-ada9f804-99b0-472d-8448-e0b241f369e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11961
48543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.1196148543
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.1671964866
Short name T32
Test name
Test status
Simulation time 8358515918 ps
CPU time 7.44 seconds
Started Mar 28 01:33:22 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 204060 kb
Host smart-ecf02287-3ed1-4cf5-959e-c564c9d07c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16719
64866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.1671964866
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.3488238671
Short name T572
Test name
Test status
Simulation time 8389458683 ps
CPU time 8.5 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:30 PM PDT 24
Peak memory 204060 kb
Host smart-40298989-fdd6-4652-87c8-56045d35b951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34882
38671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.3488238671
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.in_iso.1351892549
Short name T553
Test name
Test status
Simulation time 8423527828 ps
CPU time 7.45 seconds
Started Mar 28 01:33:25 PM PDT 24
Finished Mar 28 01:33:36 PM PDT 24
Peak memory 204080 kb
Host smart-688a2b0e-434f-4bcd-9ec9-c7c909484753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13518
92549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.in_iso.1351892549
Directory /workspace/13.in_iso/latest

Test location /workspace/coverage/default/13.phy_config_usb_ref_disable.2332738564
Short name T490
Test name
Test status
Simulation time 8361946798 ps
CPU time 6.86 seconds
Started Mar 28 01:33:16 PM PDT 24
Finished Mar 28 01:33:23 PM PDT 24
Peak memory 204024 kb
Host smart-e1fa7a22-22dd-496a-aaea-39bdfb12eb99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23327
38564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.phy_config_usb_ref_disable.2332738564
Directory /workspace/13.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.3670460573
Short name T319
Test name
Test status
Simulation time 8372217627 ps
CPU time 7.28 seconds
Started Mar 28 01:33:19 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 204060 kb
Host smart-22459d70-920d-45a2-80ed-8b4e4df47bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36704
60573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.3670460573
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_enable.1946470237
Short name T1023
Test name
Test status
Simulation time 8371596790 ps
CPU time 7.83 seconds
Started Mar 28 01:33:24 PM PDT 24
Finished Mar 28 01:33:36 PM PDT 24
Peak memory 204120 kb
Host smart-6a265871-eca5-4350-a138-df3085adf102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19464
70237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.1946470237
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.3717363188
Short name T430
Test name
Test status
Simulation time 261791628 ps
CPU time 2.01 seconds
Started Mar 28 01:33:20 PM PDT 24
Finished Mar 28 01:33:23 PM PDT 24
Peak memory 204184 kb
Host smart-48d8428e-8997-4ec4-9415-917ab82eeba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37173
63188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.3717363188
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.861424066
Short name T331
Test name
Test status
Simulation time 8402472014 ps
CPU time 7.73 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:32 PM PDT 24
Peak memory 204036 kb
Host smart-66722df8-46d8-47a7-b0d1-35565384a6b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86142
4066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.861424066
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3070201344
Short name T34
Test name
Test status
Simulation time 8411998677 ps
CPU time 8.68 seconds
Started Mar 28 01:33:23 PM PDT 24
Finished Mar 28 01:33:36 PM PDT 24
Peak memory 204124 kb
Host smart-40a9a73f-465b-4764-9007-98e02909ae93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30702
01344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3070201344
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.3791108985
Short name T748
Test name
Test status
Simulation time 8364962456 ps
CPU time 8.68 seconds
Started Mar 28 01:33:22 PM PDT 24
Finished Mar 28 01:33:36 PM PDT 24
Peak memory 204064 kb
Host smart-8eddf05e-955e-46bd-8ce2-9620033329fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37911
08985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.3791108985
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.249984713
Short name T125
Test name
Test status
Simulation time 8418098344 ps
CPU time 7.27 seconds
Started Mar 28 01:33:20 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 204080 kb
Host smart-456479b8-af2c-4f72-a43a-cdb3d8fe862c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24998
4713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.249984713
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.3114062371
Short name T865
Test name
Test status
Simulation time 8395262573 ps
CPU time 8.47 seconds
Started Mar 28 01:33:25 PM PDT 24
Finished Mar 28 01:33:37 PM PDT 24
Peak memory 203932 kb
Host smart-821d551a-f35d-423f-9b82-fec27977edd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31140
62371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3114062371
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1460397368
Short name T1029
Test name
Test status
Simulation time 8372958831 ps
CPU time 7.15 seconds
Started Mar 28 01:33:25 PM PDT 24
Finished Mar 28 01:33:36 PM PDT 24
Peak memory 204060 kb
Host smart-d2447b78-cf8c-4be0-8d55-bcd3ca168f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14603
97368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1460397368
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.3326467641
Short name T659
Test name
Test status
Simulation time 33811708 ps
CPU time 0.64 seconds
Started Mar 28 01:33:26 PM PDT 24
Finished Mar 28 01:33:29 PM PDT 24
Peak memory 204024 kb
Host smart-632f9a20-907e-4890-a4e6-0b56229e30d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33264
67641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.3326467641
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.3372547752
Short name T632
Test name
Test status
Simulation time 8427494571 ps
CPU time 7.23 seconds
Started Mar 28 01:33:25 PM PDT 24
Finished Mar 28 01:33:36 PM PDT 24
Peak memory 203992 kb
Host smart-dbf9e210-7aa2-44b9-ae45-4de17f06dcb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33725
47752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.3372547752
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.1097387291
Short name T91
Test name
Test status
Simulation time 8391551995 ps
CPU time 7.09 seconds
Started Mar 28 01:33:24 PM PDT 24
Finished Mar 28 01:33:36 PM PDT 24
Peak memory 204056 kb
Host smart-28976cb3-158d-485e-bac0-1be73680e3f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10973
87291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.1097387291
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.1781971745
Short name T525
Test name
Test status
Simulation time 8359891031 ps
CPU time 7.49 seconds
Started Mar 28 01:33:23 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 204112 kb
Host smart-1d4d40f3-ca65-4d93-9ac6-aa44f7970163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17819
71745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.1781971745
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.111988121
Short name T868
Test name
Test status
Simulation time 8424487612 ps
CPU time 7.98 seconds
Started Mar 28 01:33:20 PM PDT 24
Finished Mar 28 01:33:29 PM PDT 24
Peak memory 204064 kb
Host smart-d59b2660-e202-4b23-8bb7-c84e4f653898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11198
8121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.111988121
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.2711628633
Short name T693
Test name
Test status
Simulation time 8397991411 ps
CPU time 8.33 seconds
Started Mar 28 01:33:24 PM PDT 24
Finished Mar 28 01:33:37 PM PDT 24
Peak memory 204092 kb
Host smart-c31a4d4c-599b-4935-936e-301fd3f9987c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27116
28633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.2711628633
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.in_iso.2297955374
Short name T790
Test name
Test status
Simulation time 8415452551 ps
CPU time 7.89 seconds
Started Mar 28 01:33:22 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 204040 kb
Host smart-82e2f1c2-c99f-4b2d-ae7d-9f0ee18bf5ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22979
55374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.in_iso.2297955374
Directory /workspace/14.in_iso/latest

Test location /workspace/coverage/default/14.phy_config_usb_ref_disable.785542236
Short name T299
Test name
Test status
Simulation time 8363470641 ps
CPU time 7.11 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:31 PM PDT 24
Peak memory 203956 kb
Host smart-6671df28-0e3b-4581-8e0b-1da352b32b9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78554
2236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.phy_config_usb_ref_disable.785542236
Directory /workspace/14.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.3595695240
Short name T830
Test name
Test status
Simulation time 8373267067 ps
CPU time 8.35 seconds
Started Mar 28 01:33:25 PM PDT 24
Finished Mar 28 01:33:37 PM PDT 24
Peak memory 204092 kb
Host smart-ff0a8cac-0053-45a3-85fe-831269ffee9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35956
95240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3595695240
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_enable.2766695753
Short name T509
Test name
Test status
Simulation time 8367315702 ps
CPU time 7.1 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:31 PM PDT 24
Peak memory 204044 kb
Host smart-71f609f4-98f7-4a4d-b2a6-dae1bb173b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27666
95753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.2766695753
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.569141308
Short name T601
Test name
Test status
Simulation time 60606632 ps
CPU time 1.69 seconds
Started Mar 28 01:33:25 PM PDT 24
Finished Mar 28 01:33:30 PM PDT 24
Peak memory 204240 kb
Host smart-f5a74367-860b-485f-a7ed-a9bbbda40f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56914
1308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.569141308
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.3530020689
Short name T55
Test name
Test status
Simulation time 8362943943 ps
CPU time 7.09 seconds
Started Mar 28 01:33:20 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 204028 kb
Host smart-0adb95c4-46af-4c9b-a2a6-f019ea463cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35300
20689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3530020689
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.271738377
Short name T1051
Test name
Test status
Simulation time 8397827879 ps
CPU time 8.25 seconds
Started Mar 28 01:33:26 PM PDT 24
Finished Mar 28 01:33:37 PM PDT 24
Peak memory 204064 kb
Host smart-7dc7d2a9-7d73-447d-a1c1-13b9b16d6f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27173
8377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.271738377
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.1237792371
Short name T863
Test name
Test status
Simulation time 8407504254 ps
CPU time 6.97 seconds
Started Mar 28 01:33:18 PM PDT 24
Finished Mar 28 01:33:26 PM PDT 24
Peak memory 203876 kb
Host smart-94da4cc6-1081-454d-9f2b-574b47f5e614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12377
92371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.1237792371
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.305396059
Short name T1017
Test name
Test status
Simulation time 8367122445 ps
CPU time 7.36 seconds
Started Mar 28 01:33:19 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 204000 kb
Host smart-12fdad00-a214-4a6b-81a4-d020173e66bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30539
6059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.305396059
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.1305800242
Short name T124
Test name
Test status
Simulation time 8416538328 ps
CPU time 7.47 seconds
Started Mar 28 01:33:19 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 204052 kb
Host smart-dc7f99c4-ebcf-497a-8d6f-91571cb314c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13058
00242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.1305800242
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.357265359
Short name T744
Test name
Test status
Simulation time 8380052600 ps
CPU time 7.5 seconds
Started Mar 28 01:33:20 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 204088 kb
Host smart-00e41348-b0b4-4d79-8db5-76ab8f3b8a58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35726
5359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.357265359
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.1087615278
Short name T623
Test name
Test status
Simulation time 8364146321 ps
CPU time 6.95 seconds
Started Mar 28 01:33:19 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 204120 kb
Host smart-881104c5-919b-42e5-97a1-6cd513ed0719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10876
15278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.1087615278
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.1305513558
Short name T400
Test name
Test status
Simulation time 27770934 ps
CPU time 0.63 seconds
Started Mar 28 01:33:18 PM PDT 24
Finished Mar 28 01:33:19 PM PDT 24
Peak memory 204052 kb
Host smart-39ba2b4b-5a30-4017-834e-fb9f87b716a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13055
13558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.1305513558
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.45887738
Short name T625
Test name
Test status
Simulation time 30018456074 ps
CPU time 55.91 seconds
Started Mar 28 01:33:18 PM PDT 24
Finished Mar 28 01:34:15 PM PDT 24
Peak memory 204328 kb
Host smart-579f36b4-1ffd-4289-a16f-2a0583d9d7ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45887
738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.45887738
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.1213217727
Short name T377
Test name
Test status
Simulation time 8386052422 ps
CPU time 7.45 seconds
Started Mar 28 01:33:20 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 203956 kb
Host smart-04f0435f-173e-40c5-aba4-762df86dc71d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12132
17727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.1213217727
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.15856974
Short name T558
Test name
Test status
Simulation time 8373220326 ps
CPU time 7.56 seconds
Started Mar 28 01:33:20 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 203988 kb
Host smart-d92967c5-76f1-4fe5-ad1d-e2f8142b39b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15856
974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.15856974
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.3955828142
Short name T314
Test name
Test status
Simulation time 8388419600 ps
CPU time 7.41 seconds
Started Mar 28 01:33:20 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 204092 kb
Host smart-b88a960b-0c3c-4b46-bd47-1fa1415f56b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39558
28142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.3955828142
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.2486340757
Short name T591
Test name
Test status
Simulation time 8361024963 ps
CPU time 7.45 seconds
Started Mar 28 01:33:19 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 204104 kb
Host smart-b01be0e2-9c98-4290-b8e2-56c91dbf4181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24863
40757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.2486340757
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.3339534278
Short name T706
Test name
Test status
Simulation time 8455749557 ps
CPU time 7.59 seconds
Started Mar 28 01:33:26 PM PDT 24
Finished Mar 28 01:33:36 PM PDT 24
Peak memory 203532 kb
Host smart-e5c18aff-0ed3-459d-ae27-0c29f2f7db47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33395
34278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.3339534278
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.1290100357
Short name T1027
Test name
Test status
Simulation time 8391823371 ps
CPU time 7.64 seconds
Started Mar 28 01:33:17 PM PDT 24
Finished Mar 28 01:33:25 PM PDT 24
Peak memory 204116 kb
Host smart-ad1ed462-49a1-4de6-b95c-637a6d4f6d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12901
00357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.1290100357
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.in_iso.2686284085
Short name T839
Test name
Test status
Simulation time 8456156451 ps
CPU time 7.43 seconds
Started Mar 28 01:33:23 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 204112 kb
Host smart-af0d2296-a78c-40b6-a1c3-b15467ef2ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26862
84085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.in_iso.2686284085
Directory /workspace/15.in_iso/latest

Test location /workspace/coverage/default/15.phy_config_usb_ref_disable.491187461
Short name T468
Test name
Test status
Simulation time 8361736971 ps
CPU time 7.57 seconds
Started Mar 28 01:33:24 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 204068 kb
Host smart-60b9a88a-8458-497f-8337-8b6bd57dfe69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49118
7461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.phy_config_usb_ref_disable.491187461
Directory /workspace/15.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.1749659763
Short name T801
Test name
Test status
Simulation time 8369904953 ps
CPU time 7.47 seconds
Started Mar 28 01:33:22 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 204040 kb
Host smart-d2a38240-afd2-4d58-8a0c-516df9797414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17496
59763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.1749659763
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_enable.4061103804
Short name T1053
Test name
Test status
Simulation time 8373933440 ps
CPU time 7.73 seconds
Started Mar 28 01:33:22 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 204028 kb
Host smart-169c812e-03ef-4369-91e5-250e5fbc58bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40611
03804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.4061103804
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2632801635
Short name T1036
Test name
Test status
Simulation time 62116892 ps
CPU time 1.7 seconds
Started Mar 28 01:33:24 PM PDT 24
Finished Mar 28 01:33:30 PM PDT 24
Peak memory 204260 kb
Host smart-8969cc51-67f0-456b-9175-f879dcd66241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26328
01635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2632801635
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.3854759157
Short name T214
Test name
Test status
Simulation time 8358676676 ps
CPU time 9.02 seconds
Started Mar 28 01:33:23 PM PDT 24
Finished Mar 28 01:33:37 PM PDT 24
Peak memory 203936 kb
Host smart-ab61d56b-cb12-4994-a06c-7539284ead45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38547
59157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.3854759157
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.4087160948
Short name T156
Test name
Test status
Simulation time 8454956831 ps
CPU time 8.23 seconds
Started Mar 28 01:33:24 PM PDT 24
Finished Mar 28 01:33:37 PM PDT 24
Peak memory 204120 kb
Host smart-3c40a471-5dca-49ab-a5df-34ffb194dd5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40871
60948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.4087160948
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.1330733222
Short name T1044
Test name
Test status
Simulation time 8410823422 ps
CPU time 7.06 seconds
Started Mar 28 01:33:24 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 204124 kb
Host smart-fefb14ca-c5ef-43a5-a4bc-cb147bc36508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13307
33222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.1330733222
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.2277622057
Short name T757
Test name
Test status
Simulation time 8368390133 ps
CPU time 8.06 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:29 PM PDT 24
Peak memory 204052 kb
Host smart-a335b547-e468-4b2d-9199-78f4fbb37779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22776
22057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.2277622057
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.3927274857
Short name T1050
Test name
Test status
Simulation time 8376387840 ps
CPU time 7.06 seconds
Started Mar 28 01:33:24 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 204060 kb
Host smart-a8101873-5d56-459d-a8a3-533b7d012117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39272
74857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.3927274857
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.1173787766
Short name T738
Test name
Test status
Simulation time 8369864772 ps
CPU time 7.33 seconds
Started Mar 28 01:33:23 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 204060 kb
Host smart-af408f12-b4c7-40f9-9d19-92f5bf2017cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11737
87766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.1173787766
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3852583495
Short name T47
Test name
Test status
Simulation time 23760505 ps
CPU time 0.62 seconds
Started Mar 28 01:33:23 PM PDT 24
Finished Mar 28 01:33:24 PM PDT 24
Peak memory 204048 kb
Host smart-2318155e-b921-40a4-9b98-4973d1628fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38525
83495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3852583495
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.3067978067
Short name T323
Test name
Test status
Simulation time 8365406531 ps
CPU time 8.35 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:30 PM PDT 24
Peak memory 204112 kb
Host smart-1b1ebcee-790e-4c84-a926-779744c54af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30679
78067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.3067978067
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3335774570
Short name T967
Test name
Test status
Simulation time 8392936609 ps
CPU time 8.77 seconds
Started Mar 28 01:33:23 PM PDT 24
Finished Mar 28 01:33:36 PM PDT 24
Peak memory 204052 kb
Host smart-06a309a8-72f8-48b3-b252-cefbba011969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33357
74570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3335774570
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.3385733008
Short name T828
Test name
Test status
Simulation time 8377598671 ps
CPU time 7.21 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:31 PM PDT 24
Peak memory 204052 kb
Host smart-90892027-4e41-401e-8b99-a45d3c18b0d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33857
33008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.3385733008
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.291868120
Short name T720
Test name
Test status
Simulation time 8363133106 ps
CPU time 9.77 seconds
Started Mar 28 01:33:24 PM PDT 24
Finished Mar 28 01:33:38 PM PDT 24
Peak memory 203820 kb
Host smart-8a5472b8-cd4e-4c69-8542-c3952385acbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29186
8120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.291868120
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2094560646
Short name T157
Test name
Test status
Simulation time 8457748887 ps
CPU time 7.27 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:31 PM PDT 24
Peak memory 204044 kb
Host smart-2404e571-2383-4ba3-9bac-4f59bfc8877a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20945
60646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2094560646
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.3239410002
Short name T763
Test name
Test status
Simulation time 8386150737 ps
CPU time 7.46 seconds
Started Mar 28 01:33:23 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 204096 kb
Host smart-d915abe6-d50b-458f-a880-b858ea153bda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32394
10002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.3239410002
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.in_iso.554379022
Short name T916
Test name
Test status
Simulation time 8448609034 ps
CPU time 7.68 seconds
Started Mar 28 01:33:28 PM PDT 24
Finished Mar 28 01:33:36 PM PDT 24
Peak memory 204088 kb
Host smart-58f13487-4a37-484c-a0e5-f24941b75cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55437
9022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.in_iso.554379022
Directory /workspace/16.in_iso/latest

Test location /workspace/coverage/default/16.phy_config_usb_ref_disable.3138668657
Short name T356
Test name
Test status
Simulation time 8360632935 ps
CPU time 7.76 seconds
Started Mar 28 01:33:27 PM PDT 24
Finished Mar 28 01:33:36 PM PDT 24
Peak memory 204016 kb
Host smart-0be36eba-54f5-420b-a835-9ec2747d6c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31386
68657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.phy_config_usb_ref_disable.3138668657
Directory /workspace/16.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2190339024
Short name T1008
Test name
Test status
Simulation time 8374192886 ps
CPU time 7.51 seconds
Started Mar 28 01:33:26 PM PDT 24
Finished Mar 28 01:33:36 PM PDT 24
Peak memory 204056 kb
Host smart-564b6999-a4bb-48e7-aa1d-f400b1570828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21903
39024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2190339024
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_enable.1458924078
Short name T743
Test name
Test status
Simulation time 8363992865 ps
CPU time 7.14 seconds
Started Mar 28 01:33:26 PM PDT 24
Finished Mar 28 01:33:36 PM PDT 24
Peak memory 204044 kb
Host smart-868e095d-0184-4cab-8f6b-3cbdca8edbcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14589
24078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1458924078
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.1923902416
Short name T592
Test name
Test status
Simulation time 55869706 ps
CPU time 1.58 seconds
Started Mar 28 01:33:26 PM PDT 24
Finished Mar 28 01:33:30 PM PDT 24
Peak memory 204256 kb
Host smart-a5c49353-dee1-4ac7-994c-939b1900a738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19239
02416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.1923902416
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.3077021385
Short name T824
Test name
Test status
Simulation time 8357677531 ps
CPU time 8.93 seconds
Started Mar 28 01:33:30 PM PDT 24
Finished Mar 28 01:33:39 PM PDT 24
Peak memory 204052 kb
Host smart-f300a5b5-636f-4dbb-b451-86a583308201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30770
21385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.3077021385
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.3657807625
Short name T746
Test name
Test status
Simulation time 8386262169 ps
CPU time 8.42 seconds
Started Mar 28 01:33:26 PM PDT 24
Finished Mar 28 01:33:37 PM PDT 24
Peak memory 203992 kb
Host smart-00a2535e-aff6-4592-ac84-30d6cad06f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36578
07625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.3657807625
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.2164020797
Short name T683
Test name
Test status
Simulation time 8408178163 ps
CPU time 7.91 seconds
Started Mar 28 01:33:27 PM PDT 24
Finished Mar 28 01:33:37 PM PDT 24
Peak memory 204076 kb
Host smart-1cdfb7d1-ea7a-4030-94d3-d7aa3360846f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21640
20797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.2164020797
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3297979257
Short name T317
Test name
Test status
Simulation time 8362938942 ps
CPU time 7.11 seconds
Started Mar 28 01:33:25 PM PDT 24
Finished Mar 28 01:33:36 PM PDT 24
Peak memory 204020 kb
Host smart-2b767650-42b8-457b-ae26-b1bf9bb6af71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32979
79257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3297979257
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.1887098191
Short name T785
Test name
Test status
Simulation time 8376096101 ps
CPU time 7.89 seconds
Started Mar 28 01:33:30 PM PDT 24
Finished Mar 28 01:33:38 PM PDT 24
Peak memory 204056 kb
Host smart-4c3257be-79b1-4f40-8789-40c80fe53ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18870
98191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.1887098191
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2994279574
Short name T15
Test name
Test status
Simulation time 8384297572 ps
CPU time 7.67 seconds
Started Mar 28 01:33:28 PM PDT 24
Finished Mar 28 01:33:36 PM PDT 24
Peak memory 204072 kb
Host smart-db78f956-f545-4fb0-bb96-aeabaa94ed60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29942
79574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2994279574
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.1332766187
Short name T1041
Test name
Test status
Simulation time 30788807 ps
CPU time 0.63 seconds
Started Mar 28 01:33:30 PM PDT 24
Finished Mar 28 01:33:31 PM PDT 24
Peak memory 203960 kb
Host smart-42adfece-f420-4691-8e3a-b90f18c275cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13327
66187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.1332766187
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.786760595
Short name T764
Test name
Test status
Simulation time 17208224805 ps
CPU time 27.55 seconds
Started Mar 28 01:33:35 PM PDT 24
Finished Mar 28 01:34:03 PM PDT 24
Peak memory 204220 kb
Host smart-732dd3d8-3fa0-498c-b642-ef72a1cdbaa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78676
0595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.786760595
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.1771142430
Short name T899
Test name
Test status
Simulation time 8375646099 ps
CPU time 8.32 seconds
Started Mar 28 01:33:42 PM PDT 24
Finished Mar 28 01:33:51 PM PDT 24
Peak memory 204024 kb
Host smart-8ad01705-d09b-45e6-953c-3f989e7ff8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17711
42430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.1771142430
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.2437316153
Short name T485
Test name
Test status
Simulation time 8414951894 ps
CPU time 7 seconds
Started Mar 28 01:33:30 PM PDT 24
Finished Mar 28 01:33:37 PM PDT 24
Peak memory 204076 kb
Host smart-81672f9c-5975-4245-b5ab-02ee6b4a56f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24373
16153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.2437316153
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.3586674226
Short name T403
Test name
Test status
Simulation time 8405794875 ps
CPU time 6.91 seconds
Started Mar 28 01:33:33 PM PDT 24
Finished Mar 28 01:33:40 PM PDT 24
Peak memory 204052 kb
Host smart-18fa1d05-d44e-47d5-9ba0-844b22a461ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35866
74226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.3586674226
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.740905634
Short name T972
Test name
Test status
Simulation time 8363919739 ps
CPU time 7.18 seconds
Started Mar 28 01:33:33 PM PDT 24
Finished Mar 28 01:33:40 PM PDT 24
Peak memory 204052 kb
Host smart-9e6cb65e-ac96-4c35-990c-c3f27070d818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74090
5634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.740905634
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1937585881
Short name T432
Test name
Test status
Simulation time 8426473793 ps
CPU time 8.18 seconds
Started Mar 28 01:33:25 PM PDT 24
Finished Mar 28 01:33:37 PM PDT 24
Peak memory 203664 kb
Host smart-23d0f2ae-0c46-4168-a894-81e32839cf1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19375
85881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1937585881
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.3350945758
Short name T690
Test name
Test status
Simulation time 8402104986 ps
CPU time 7.69 seconds
Started Mar 28 01:33:29 PM PDT 24
Finished Mar 28 01:33:37 PM PDT 24
Peak memory 204120 kb
Host smart-34705d6d-f4f6-4773-b7a8-41a9179fb83c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33509
45758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.3350945758
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.in_iso.1079345558
Short name T624
Test name
Test status
Simulation time 8450935168 ps
CPU time 8.43 seconds
Started Mar 28 01:33:33 PM PDT 24
Finished Mar 28 01:33:42 PM PDT 24
Peak memory 204020 kb
Host smart-f6c55282-c643-4152-bf50-b86427cd6422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10793
45558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.in_iso.1079345558
Directory /workspace/17.in_iso/latest

Test location /workspace/coverage/default/17.phy_config_usb_ref_disable.4180467264
Short name T386
Test name
Test status
Simulation time 8367274683 ps
CPU time 7.35 seconds
Started Mar 28 01:33:42 PM PDT 24
Finished Mar 28 01:33:50 PM PDT 24
Peak memory 204012 kb
Host smart-2879af5f-e96b-4b9f-9ab3-af49c7065513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41804
67264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.phy_config_usb_ref_disable.4180467264
Directory /workspace/17.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.29610953
Short name T315
Test name
Test status
Simulation time 8373494165 ps
CPU time 8.91 seconds
Started Mar 28 01:33:41 PM PDT 24
Finished Mar 28 01:33:50 PM PDT 24
Peak memory 204012 kb
Host smart-80e4ec0d-c8d0-4673-80c5-b992fca0057b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29610
953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.29610953
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_enable.2694466152
Short name T387
Test name
Test status
Simulation time 8366544445 ps
CPU time 7.89 seconds
Started Mar 28 01:33:29 PM PDT 24
Finished Mar 28 01:33:37 PM PDT 24
Peak memory 204020 kb
Host smart-78bafae8-9556-494c-8566-035bf1233a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26944
66152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.2694466152
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.396624127
Short name T441
Test name
Test status
Simulation time 71125057 ps
CPU time 2.08 seconds
Started Mar 28 01:33:33 PM PDT 24
Finished Mar 28 01:33:36 PM PDT 24
Peak memory 204228 kb
Host smart-1f2f3df3-e7a7-4875-8fc1-9fe5c74f9ced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39662
4127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.396624127
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.2841780020
Short name T876
Test name
Test status
Simulation time 8360686074 ps
CPU time 7.83 seconds
Started Mar 28 01:33:42 PM PDT 24
Finished Mar 28 01:33:50 PM PDT 24
Peak memory 204064 kb
Host smart-ff5e2f8e-c37a-4a1c-a3c9-dea5ced426c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28417
80020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2841780020
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.2934288834
Short name T822
Test name
Test status
Simulation time 8375900128 ps
CPU time 6.93 seconds
Started Mar 28 01:33:31 PM PDT 24
Finished Mar 28 01:33:38 PM PDT 24
Peak memory 203896 kb
Host smart-64410f01-0bf7-4c4b-877e-605ae069009f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29342
88834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.2934288834
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.112227505
Short name T710
Test name
Test status
Simulation time 8416136916 ps
CPU time 8.74 seconds
Started Mar 28 01:33:42 PM PDT 24
Finished Mar 28 01:33:51 PM PDT 24
Peak memory 204048 kb
Host smart-4b7f9f3d-c9cf-45ae-8bfa-29ff396cb5bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11222
7505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.112227505
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.1064203617
Short name T799
Test name
Test status
Simulation time 8362471380 ps
CPU time 7.66 seconds
Started Mar 28 01:33:30 PM PDT 24
Finished Mar 28 01:33:38 PM PDT 24
Peak memory 204084 kb
Host smart-2416d9d1-eacf-4780-820a-2d188ed3b88f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10642
03617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.1064203617
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.931349101
Short name T736
Test name
Test status
Simulation time 8397489048 ps
CPU time 7.07 seconds
Started Mar 28 01:33:37 PM PDT 24
Finished Mar 28 01:33:44 PM PDT 24
Peak memory 204068 kb
Host smart-82f45fe7-618a-44b9-b1d8-ceeb5ffbddd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93134
9101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.931349101
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.760447087
Short name T416
Test name
Test status
Simulation time 8377235681 ps
CPU time 7.74 seconds
Started Mar 28 01:33:42 PM PDT 24
Finished Mar 28 01:33:50 PM PDT 24
Peak memory 204064 kb
Host smart-24e02794-3755-4fc1-b584-e0f9a14097ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76044
7087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.760447087
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1761032105
Short name T618
Test name
Test status
Simulation time 8395391607 ps
CPU time 7.59 seconds
Started Mar 28 01:33:40 PM PDT 24
Finished Mar 28 01:33:48 PM PDT 24
Peak memory 204020 kb
Host smart-b34c2304-90ac-407a-8e34-ccb7cb781635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17610
32105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1761032105
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.432694273
Short name T81
Test name
Test status
Simulation time 24910965 ps
CPU time 0.65 seconds
Started Mar 28 01:33:34 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 204032 kb
Host smart-7f6519c4-75c3-4929-8f3a-43eb1c03b19f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43269
4273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.432694273
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.2439900343
Short name T93
Test name
Test status
Simulation time 8388642196 ps
CPU time 8.25 seconds
Started Mar 28 01:33:36 PM PDT 24
Finished Mar 28 01:33:44 PM PDT 24
Peak memory 204092 kb
Host smart-ab1819bc-eb32-4c0a-897b-307450f40745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24399
00343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.2439900343
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.2050366225
Short name T479
Test name
Test status
Simulation time 8392790144 ps
CPU time 7.77 seconds
Started Mar 28 01:33:33 PM PDT 24
Finished Mar 28 01:33:41 PM PDT 24
Peak memory 204096 kb
Host smart-3a52bd21-7a3f-4686-a9b9-3a28e460a628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20503
66225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2050366225
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.1722752182
Short name T798
Test name
Test status
Simulation time 8398612096 ps
CPU time 9 seconds
Started Mar 28 01:33:35 PM PDT 24
Finished Mar 28 01:33:44 PM PDT 24
Peak memory 203964 kb
Host smart-1305f166-0f8b-447f-a94c-62e4fed5cfbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17227
52182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.1722752182
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.1265189185
Short name T557
Test name
Test status
Simulation time 8355843574 ps
CPU time 8.94 seconds
Started Mar 28 01:33:28 PM PDT 24
Finished Mar 28 01:33:38 PM PDT 24
Peak memory 204080 kb
Host smart-9e5c2136-344a-4d79-bb20-b97b895cf785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12651
89185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.1265189185
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.180960306
Short name T960
Test name
Test status
Simulation time 8473081987 ps
CPU time 7.92 seconds
Started Mar 28 01:33:41 PM PDT 24
Finished Mar 28 01:33:49 PM PDT 24
Peak memory 203652 kb
Host smart-8ce9aa09-f81c-4d38-9c4e-8e1515031166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18096
0306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.180960306
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.3616896485
Short name T747
Test name
Test status
Simulation time 8377257428 ps
CPU time 7.99 seconds
Started Mar 28 01:33:32 PM PDT 24
Finished Mar 28 01:33:40 PM PDT 24
Peak memory 204112 kb
Host smart-4e024437-b9e6-41ab-9f27-0fae112c208c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36168
96485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.3616896485
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.in_iso.884230623
Short name T703
Test name
Test status
Simulation time 8404336511 ps
CPU time 7.86 seconds
Started Mar 28 01:33:42 PM PDT 24
Finished Mar 28 01:33:50 PM PDT 24
Peak memory 204020 kb
Host smart-4b9f6f74-6c2e-462b-8f68-901fefa8e8ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88423
0623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.in_iso.884230623
Directory /workspace/18.in_iso/latest

Test location /workspace/coverage/default/18.phy_config_usb_ref_disable.2328392157
Short name T599
Test name
Test status
Simulation time 8359620574 ps
CPU time 7.08 seconds
Started Mar 28 01:33:31 PM PDT 24
Finished Mar 28 01:33:38 PM PDT 24
Peak memory 204032 kb
Host smart-5f87afe0-3a3b-4979-a412-020bcfd65da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23283
92157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.phy_config_usb_ref_disable.2328392157
Directory /workspace/18.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.4290324959
Short name T1034
Test name
Test status
Simulation time 8373252120 ps
CPU time 9.5 seconds
Started Mar 28 01:33:33 PM PDT 24
Finished Mar 28 01:33:43 PM PDT 24
Peak memory 204028 kb
Host smart-65ab8813-2287-4b89-ad7a-2c6bb02c5b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42903
24959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.4290324959
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_enable.2311302659
Short name T320
Test name
Test status
Simulation time 8367061686 ps
CPU time 6.89 seconds
Started Mar 28 01:33:29 PM PDT 24
Finished Mar 28 01:33:36 PM PDT 24
Peak memory 204000 kb
Host smart-d965734d-fde6-4a95-adea-f6561b201bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23113
02659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.2311302659
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.498388780
Short name T58
Test name
Test status
Simulation time 42980888 ps
CPU time 1.24 seconds
Started Mar 28 01:33:33 PM PDT 24
Finished Mar 28 01:33:35 PM PDT 24
Peak memory 204188 kb
Host smart-01628869-9031-494a-bacb-d36ec4ba3e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49838
8780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.498388780
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.3706954215
Short name T1043
Test name
Test status
Simulation time 8357537097 ps
CPU time 7.49 seconds
Started Mar 28 01:33:34 PM PDT 24
Finished Mar 28 01:33:42 PM PDT 24
Peak memory 204024 kb
Host smart-05026ac3-8d02-4a01-ad4b-c014d2894a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37069
54215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3706954215
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.3604697984
Short name T1068
Test name
Test status
Simulation time 8383667926 ps
CPU time 8.11 seconds
Started Mar 28 01:33:40 PM PDT 24
Finished Mar 28 01:33:48 PM PDT 24
Peak memory 204044 kb
Host smart-d4dc5a70-8151-44bf-9813-9367a84fc4bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36046
97984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3604697984
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.239036232
Short name T621
Test name
Test status
Simulation time 8405986708 ps
CPU time 7.19 seconds
Started Mar 28 01:33:30 PM PDT 24
Finished Mar 28 01:33:38 PM PDT 24
Peak memory 204084 kb
Host smart-bef3e3ed-e314-4f9c-801e-77b0868d03ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23903
6232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.239036232
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.1247547794
Short name T1061
Test name
Test status
Simulation time 8362859728 ps
CPU time 7.54 seconds
Started Mar 28 01:33:31 PM PDT 24
Finished Mar 28 01:33:39 PM PDT 24
Peak memory 204048 kb
Host smart-f6e09509-38ba-4f16-883a-51d344b6b4da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12475
47794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.1247547794
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.3353478084
Short name T905
Test name
Test status
Simulation time 8429146169 ps
CPU time 8.25 seconds
Started Mar 28 01:33:30 PM PDT 24
Finished Mar 28 01:33:39 PM PDT 24
Peak memory 204036 kb
Host smart-10986d75-1398-4a10-9ce6-0df2cfccda1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33534
78084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.3353478084
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.4254387681
Short name T753
Test name
Test status
Simulation time 8380335480 ps
CPU time 8.53 seconds
Started Mar 28 01:33:33 PM PDT 24
Finished Mar 28 01:33:42 PM PDT 24
Peak memory 204048 kb
Host smart-6755fefd-d8be-4ee5-af6a-d6c92b372aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42543
87681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.4254387681
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.2635729456
Short name T913
Test name
Test status
Simulation time 8388258384 ps
CPU time 9.9 seconds
Started Mar 28 01:33:26 PM PDT 24
Finished Mar 28 01:33:38 PM PDT 24
Peak memory 204052 kb
Host smart-04c0dc54-aaff-4cf1-9586-29d106407cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26357
29456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.2635729456
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.1292652732
Short name T313
Test name
Test status
Simulation time 28126693 ps
CPU time 0.66 seconds
Started Mar 28 01:33:41 PM PDT 24
Finished Mar 28 01:33:42 PM PDT 24
Peak memory 203960 kb
Host smart-849c8fa2-922b-48ce-904a-2d75bdf97c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12926
52732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.1292652732
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.1784161672
Short name T213
Test name
Test status
Simulation time 21421428702 ps
CPU time 40 seconds
Started Mar 28 01:33:31 PM PDT 24
Finished Mar 28 01:34:11 PM PDT 24
Peak memory 204228 kb
Host smart-0873e587-fbec-4eb0-8b42-37af7776dc8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17841
61672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.1784161672
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.364447132
Short name T428
Test name
Test status
Simulation time 8401955336 ps
CPU time 8.9 seconds
Started Mar 28 01:33:41 PM PDT 24
Finished Mar 28 01:33:50 PM PDT 24
Peak memory 203544 kb
Host smart-43e9da7b-b7e7-4e2b-841d-3f3d91f13289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36444
7132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.364447132
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.1781986134
Short name T162
Test name
Test status
Simulation time 8411688107 ps
CPU time 7.8 seconds
Started Mar 28 01:33:34 PM PDT 24
Finished Mar 28 01:33:42 PM PDT 24
Peak memory 204028 kb
Host smart-6be41f55-6e04-4485-8f5e-35bc527e96f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17819
86134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.1781986134
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.4287360921
Short name T958
Test name
Test status
Simulation time 8400124263 ps
CPU time 7.19 seconds
Started Mar 28 01:33:42 PM PDT 24
Finished Mar 28 01:33:50 PM PDT 24
Peak memory 204056 kb
Host smart-adb472ec-414b-41d2-af01-154a82c03094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42873
60921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.4287360921
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.2307141287
Short name T733
Test name
Test status
Simulation time 8354864156 ps
CPU time 8.89 seconds
Started Mar 28 01:33:42 PM PDT 24
Finished Mar 28 01:33:51 PM PDT 24
Peak memory 204040 kb
Host smart-a596f4cd-109f-4930-ac14-bb932d229397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23071
41287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.2307141287
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.794351109
Short name T175
Test name
Test status
Simulation time 8435498200 ps
CPU time 7.2 seconds
Started Mar 28 01:33:35 PM PDT 24
Finished Mar 28 01:33:42 PM PDT 24
Peak memory 204084 kb
Host smart-e3c1f6af-f2b4-4a74-997d-7f9a8d472ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79435
1109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.794351109
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.1903164234
Short name T792
Test name
Test status
Simulation time 8373299316 ps
CPU time 6.91 seconds
Started Mar 28 01:33:33 PM PDT 24
Finished Mar 28 01:33:40 PM PDT 24
Peak memory 204044 kb
Host smart-0a0f12b4-b67e-470b-9dca-58c795d6e665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19031
64234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.1903164234
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.in_iso.1654162529
Short name T491
Test name
Test status
Simulation time 8378919817 ps
CPU time 9.45 seconds
Started Mar 28 01:33:49 PM PDT 24
Finished Mar 28 01:33:59 PM PDT 24
Peak memory 204084 kb
Host smart-7e2a8e94-ef9d-4039-bce0-b44a5a8ef84a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16541
62529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.in_iso.1654162529
Directory /workspace/19.in_iso/latest

Test location /workspace/coverage/default/19.phy_config_usb_ref_disable.1404478345
Short name T762
Test name
Test status
Simulation time 8361327567 ps
CPU time 7.22 seconds
Started Mar 28 01:33:47 PM PDT 24
Finished Mar 28 01:33:54 PM PDT 24
Peak memory 204020 kb
Host smart-4e1c7a3b-1687-4574-9ec8-577265b2bff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14044
78345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.phy_config_usb_ref_disable.1404478345
Directory /workspace/19.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.2685220375
Short name T526
Test name
Test status
Simulation time 8364449901 ps
CPU time 9.06 seconds
Started Mar 28 01:33:30 PM PDT 24
Finished Mar 28 01:33:40 PM PDT 24
Peak memory 204024 kb
Host smart-f38e0cb0-a110-45fa-9b17-9aa459dd3ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26852
20375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.2685220375
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_enable.2873082028
Short name T379
Test name
Test status
Simulation time 8365766594 ps
CPU time 7.04 seconds
Started Mar 28 01:33:41 PM PDT 24
Finished Mar 28 01:33:48 PM PDT 24
Peak memory 203956 kb
Host smart-8013140a-6975-46d3-9540-5bbf45199f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28730
82028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.2873082028
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.1232601292
Short name T1064
Test name
Test status
Simulation time 91710754 ps
CPU time 1.11 seconds
Started Mar 28 01:33:39 PM PDT 24
Finished Mar 28 01:33:41 PM PDT 24
Peak memory 204164 kb
Host smart-19de85fe-1571-453b-bfa1-064737beb8a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12326
01292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.1232601292
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1958723638
Short name T603
Test name
Test status
Simulation time 8408376795 ps
CPU time 7.29 seconds
Started Mar 28 01:33:49 PM PDT 24
Finished Mar 28 01:33:56 PM PDT 24
Peak memory 204052 kb
Host smart-df5091d8-9db3-4579-8060-e87999a23ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19587
23638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1958723638
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.41755534
Short name T321
Test name
Test status
Simulation time 8365120184 ps
CPU time 8.1 seconds
Started Mar 28 01:33:49 PM PDT 24
Finished Mar 28 01:33:57 PM PDT 24
Peak memory 204052 kb
Host smart-b92f13ef-f2d2-49b3-9e83-7685c6513b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41755
534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.41755534
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.3090439951
Short name T934
Test name
Test status
Simulation time 8385337392 ps
CPU time 8.66 seconds
Started Mar 28 01:33:45 PM PDT 24
Finished Mar 28 01:33:54 PM PDT 24
Peak memory 204084 kb
Host smart-6446bc59-b920-4d7d-abf5-4e015f2bbef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30904
39951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.3090439951
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.1726173214
Short name T554
Test name
Test status
Simulation time 8376243506 ps
CPU time 8.78 seconds
Started Mar 28 01:33:46 PM PDT 24
Finished Mar 28 01:33:55 PM PDT 24
Peak memory 204052 kb
Host smart-93b0b13e-068d-4a54-8f63-7297f9ec9131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17261
73214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.1726173214
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.3834515130
Short name T452
Test name
Test status
Simulation time 27300745 ps
CPU time 0.65 seconds
Started Mar 28 01:33:49 PM PDT 24
Finished Mar 28 01:33:50 PM PDT 24
Peak memory 203984 kb
Host smart-d32c81bb-2482-400d-be82-755df54b7255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38345
15130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.3834515130
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.3587307947
Short name T256
Test name
Test status
Simulation time 29320834555 ps
CPU time 55.7 seconds
Started Mar 28 01:33:46 PM PDT 24
Finished Mar 28 01:34:42 PM PDT 24
Peak memory 204344 kb
Host smart-3ba9efd4-4665-4906-82ce-716c60f6b744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35873
07947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.3587307947
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.3465007434
Short name T448
Test name
Test status
Simulation time 8401234777 ps
CPU time 7.4 seconds
Started Mar 28 01:33:46 PM PDT 24
Finished Mar 28 01:33:53 PM PDT 24
Peak memory 204108 kb
Host smart-32ce78e0-94cb-4726-aabb-7c31b0b79a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34650
07434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.3465007434
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.3654634745
Short name T1009
Test name
Test status
Simulation time 8450024469 ps
CPU time 7.9 seconds
Started Mar 28 01:33:45 PM PDT 24
Finished Mar 28 01:33:53 PM PDT 24
Peak memory 204056 kb
Host smart-82f39800-151a-4726-80dc-e9cd50bfc66e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36546
34745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.3654634745
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.3209181946
Short name T837
Test name
Test status
Simulation time 8381326778 ps
CPU time 8.42 seconds
Started Mar 28 01:33:46 PM PDT 24
Finished Mar 28 01:33:55 PM PDT 24
Peak memory 204052 kb
Host smart-5a655e3c-4ea8-4d4f-9396-1f30804c18d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32091
81946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.3209181946
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3989194689
Short name T570
Test name
Test status
Simulation time 8365754772 ps
CPU time 8.85 seconds
Started Mar 28 01:33:47 PM PDT 24
Finished Mar 28 01:33:56 PM PDT 24
Peak memory 203976 kb
Host smart-9a5e6686-feca-4c71-bb23-a8def950c2a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39891
94689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3989194689
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.3234765748
Short name T165
Test name
Test status
Simulation time 8393507876 ps
CPU time 8.33 seconds
Started Mar 28 01:33:42 PM PDT 24
Finished Mar 28 01:33:51 PM PDT 24
Peak memory 204036 kb
Host smart-af4d05a0-9890-4e8c-bb7e-334c9431c7b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32347
65748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.3234765748
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.1461275719
Short name T516
Test name
Test status
Simulation time 8404687344 ps
CPU time 7.93 seconds
Started Mar 28 01:33:49 PM PDT 24
Finished Mar 28 01:33:57 PM PDT 24
Peak memory 204052 kb
Host smart-639cfed0-4514-4c2a-ba6b-56e7cbdc4f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14612
75719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.1461275719
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.in_iso.1417869373
Short name T152
Test name
Test status
Simulation time 8378688142 ps
CPU time 7.42 seconds
Started Mar 28 01:32:39 PM PDT 24
Finished Mar 28 01:32:47 PM PDT 24
Peak memory 204044 kb
Host smart-0f7296ba-12da-491e-8992-dc96a094288c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14178
69373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.in_iso.1417869373
Directory /workspace/2.in_iso/latest

Test location /workspace/coverage/default/2.phy_config_usb_ref_disable.376042752
Short name T714
Test name
Test status
Simulation time 8357605207 ps
CPU time 7.75 seconds
Started Mar 28 01:32:39 PM PDT 24
Finished Mar 28 01:32:47 PM PDT 24
Peak memory 204100 kb
Host smart-ab22dc0f-47bf-449d-a891-2da8e16cba42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37604
2752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.phy_config_usb_ref_disable.376042752
Directory /workspace/2.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.1763174452
Short name T1060
Test name
Test status
Simulation time 8375062813 ps
CPU time 8.79 seconds
Started Mar 28 01:32:41 PM PDT 24
Finished Mar 28 01:32:50 PM PDT 24
Peak memory 204044 kb
Host smart-08d88f85-02c0-4907-8e69-ddf0eb9d7d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17631
74452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.1763174452
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_enable.1699619487
Short name T2
Test name
Test status
Simulation time 8371362876 ps
CPU time 7.56 seconds
Started Mar 28 01:32:39 PM PDT 24
Finished Mar 28 01:32:47 PM PDT 24
Peak memory 204076 kb
Host smart-06f3f5fd-4d70-4047-8b89-7d9c105b2950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16996
19487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.1699619487
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2458252268
Short name T1042
Test name
Test status
Simulation time 49570722 ps
CPU time 1.36 seconds
Started Mar 28 01:32:39 PM PDT 24
Finished Mar 28 01:32:41 PM PDT 24
Peak memory 204228 kb
Host smart-b4614af5-5fe7-4c66-9344-fb3593336528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24582
52268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2458252268
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.2441919894
Short name T644
Test name
Test status
Simulation time 8365528053 ps
CPU time 9.83 seconds
Started Mar 28 01:32:38 PM PDT 24
Finished Mar 28 01:32:49 PM PDT 24
Peak memory 203928 kb
Host smart-1faf9e65-9d20-4184-a5b0-5c15a7a161a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24419
19894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2441919894
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.605960605
Short name T159
Test name
Test status
Simulation time 8382066879 ps
CPU time 7.68 seconds
Started Mar 28 01:32:40 PM PDT 24
Finished Mar 28 01:32:47 PM PDT 24
Peak memory 203940 kb
Host smart-1439dcd9-07b9-451d-9384-08e0e730e098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60596
0605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.605960605
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.1577073974
Short name T668
Test name
Test status
Simulation time 8411873128 ps
CPU time 7.97 seconds
Started Mar 28 01:32:39 PM PDT 24
Finished Mar 28 01:32:47 PM PDT 24
Peak memory 203324 kb
Host smart-1e547565-b866-485e-b525-8d2fa7ef9995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15770
73974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.1577073974
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.3239387495
Short name T781
Test name
Test status
Simulation time 8362427512 ps
CPU time 7.67 seconds
Started Mar 28 01:32:45 PM PDT 24
Finished Mar 28 01:32:53 PM PDT 24
Peak memory 204052 kb
Host smart-6b77aa8d-1c2f-4285-80e9-a2a1619cacff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32393
87495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.3239387495
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.3055514975
Short name T672
Test name
Test status
Simulation time 8370018742 ps
CPU time 7.7 seconds
Started Mar 28 01:32:38 PM PDT 24
Finished Mar 28 01:32:46 PM PDT 24
Peak memory 204000 kb
Host smart-c506bd17-b36a-4210-af28-23883fce9850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30555
14975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3055514975
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2692322852
Short name T84
Test name
Test status
Simulation time 8381399975 ps
CPU time 7.2 seconds
Started Mar 28 01:32:39 PM PDT 24
Finished Mar 28 01:32:46 PM PDT 24
Peak memory 203272 kb
Host smart-d777258a-3733-46a2-b67c-cb0e8b86617f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26923
22852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2692322852
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.3989484656
Short name T413
Test name
Test status
Simulation time 31048178 ps
CPU time 0.65 seconds
Started Mar 28 01:32:36 PM PDT 24
Finished Mar 28 01:32:37 PM PDT 24
Peak memory 204020 kb
Host smart-8ed43ad9-2595-4059-948b-89efb18b1abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39894
84656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.3989484656
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.2491422034
Short name T862
Test name
Test status
Simulation time 26095364434 ps
CPU time 47.11 seconds
Started Mar 28 01:32:38 PM PDT 24
Finished Mar 28 01:33:26 PM PDT 24
Peak memory 204380 kb
Host smart-5773b02c-4c5b-44f9-92cc-3c3a98a3a51b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24914
22034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.2491422034
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.3401046402
Short name T897
Test name
Test status
Simulation time 8406869086 ps
CPU time 7.48 seconds
Started Mar 28 01:32:40 PM PDT 24
Finished Mar 28 01:32:47 PM PDT 24
Peak memory 204088 kb
Host smart-5d95074c-334f-464e-b7f3-42da3310106c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34010
46402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.3401046402
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.1292316312
Short name T517
Test name
Test status
Simulation time 8409608639 ps
CPU time 7.07 seconds
Started Mar 28 01:32:37 PM PDT 24
Finished Mar 28 01:32:45 PM PDT 24
Peak memory 204052 kb
Host smart-05c4ee58-c779-4795-a2a6-b0a47438780b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12923
16312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.1292316312
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.1738944113
Short name T300
Test name
Test status
Simulation time 8403577012 ps
CPU time 7.27 seconds
Started Mar 28 01:32:34 PM PDT 24
Finished Mar 28 01:32:42 PM PDT 24
Peak memory 204048 kb
Host smart-cacd9ace-254b-4a78-a5c4-a2eedeedd35a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17389
44113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.1738944113
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.191681367
Short name T65
Test name
Test status
Simulation time 184606448 ps
CPU time 0.97 seconds
Started Mar 28 01:32:36 PM PDT 24
Finished Mar 28 01:32:37 PM PDT 24
Peak memory 220000 kb
Host smart-be06df75-7a49-441a-8d18-90e8a2b5733e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=191681367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.191681367
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.889468721
Short name T697
Test name
Test status
Simulation time 8361982779 ps
CPU time 7.18 seconds
Started Mar 28 01:32:38 PM PDT 24
Finished Mar 28 01:32:46 PM PDT 24
Peak memory 204112 kb
Host smart-1c393457-d85d-43df-b480-0763ce697de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88946
8721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.889468721
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.2056619241
Short name T848
Test name
Test status
Simulation time 8434957163 ps
CPU time 8.29 seconds
Started Mar 28 01:32:34 PM PDT 24
Finished Mar 28 01:32:43 PM PDT 24
Peak memory 204048 kb
Host smart-4fb2eec8-1a84-4750-b568-9d42099ac595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20566
19241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.2056619241
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.484772563
Short name T614
Test name
Test status
Simulation time 8394712518 ps
CPU time 9.22 seconds
Started Mar 28 01:32:36 PM PDT 24
Finished Mar 28 01:32:46 PM PDT 24
Peak memory 204024 kb
Host smart-5ac106ac-c032-4c66-95e2-6ed8d4296f4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48477
2563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.484772563
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.in_iso.2859455412
Short name T50
Test name
Test status
Simulation time 8451999768 ps
CPU time 8.63 seconds
Started Mar 28 01:34:17 PM PDT 24
Finished Mar 28 01:34:26 PM PDT 24
Peak memory 204116 kb
Host smart-fc4a753d-aeb5-4cd0-a2b0-5dad88d10287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28594
55412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.in_iso.2859455412
Directory /workspace/20.in_iso/latest

Test location /workspace/coverage/default/20.phy_config_usb_ref_disable.3781101238
Short name T911
Test name
Test status
Simulation time 8365044613 ps
CPU time 7.47 seconds
Started Mar 28 01:33:48 PM PDT 24
Finished Mar 28 01:33:56 PM PDT 24
Peak memory 204020 kb
Host smart-834cc11f-d924-4e6c-9c33-1cfff1d57001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37811
01238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.phy_config_usb_ref_disable.3781101238
Directory /workspace/20.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3647721989
Short name T587
Test name
Test status
Simulation time 8369722818 ps
CPU time 7.37 seconds
Started Mar 28 01:33:51 PM PDT 24
Finished Mar 28 01:33:58 PM PDT 24
Peak memory 204064 kb
Host smart-52d3e39d-3773-4680-9157-3d15ef261881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36477
21989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3647721989
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_enable.1686059208
Short name T520
Test name
Test status
Simulation time 8366761382 ps
CPU time 8.38 seconds
Started Mar 28 01:33:47 PM PDT 24
Finished Mar 28 01:33:56 PM PDT 24
Peak memory 204080 kb
Host smart-fdbdf54a-b153-49db-9bbc-c4b61380ceba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16860
59208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1686059208
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1860433270
Short name T1033
Test name
Test status
Simulation time 48252734 ps
CPU time 1.25 seconds
Started Mar 28 01:33:48 PM PDT 24
Finished Mar 28 01:33:50 PM PDT 24
Peak memory 204160 kb
Host smart-71ef5f64-f036-46ad-af99-ac800ae2d39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18604
33270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1860433270
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.2418182494
Short name T222
Test name
Test status
Simulation time 8357235562 ps
CPU time 7.09 seconds
Started Mar 28 01:34:15 PM PDT 24
Finished Mar 28 01:34:23 PM PDT 24
Peak memory 204052 kb
Host smart-9395ecd3-3d0d-4cf4-83ad-de7ef251fe1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24181
82494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.2418182494
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.1547250487
Short name T805
Test name
Test status
Simulation time 8378075989 ps
CPU time 9.64 seconds
Started Mar 28 01:33:48 PM PDT 24
Finished Mar 28 01:33:58 PM PDT 24
Peak memory 204048 kb
Host smart-e85eda5d-4109-48f6-8550-7a038f0ced2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15472
50487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.1547250487
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.2338820115
Short name T415
Test name
Test status
Simulation time 8409186867 ps
CPU time 9.55 seconds
Started Mar 28 01:33:47 PM PDT 24
Finished Mar 28 01:33:57 PM PDT 24
Peak memory 204124 kb
Host smart-da3b4370-4618-4c78-8621-1494c96aa9a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23388
20115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.2338820115
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.3163710654
Short name T96
Test name
Test status
Simulation time 8365790728 ps
CPU time 7.21 seconds
Started Mar 28 01:33:50 PM PDT 24
Finished Mar 28 01:33:57 PM PDT 24
Peak memory 204084 kb
Host smart-5355797c-951c-4845-b098-3a10ee8ab977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31637
10654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.3163710654
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.4034610588
Short name T121
Test name
Test status
Simulation time 8406545260 ps
CPU time 8.17 seconds
Started Mar 28 01:33:51 PM PDT 24
Finished Mar 28 01:33:59 PM PDT 24
Peak memory 204076 kb
Host smart-080cff2c-4552-4976-bd8b-a2bfce873108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40346
10588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.4034610588
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.2132183552
Short name T680
Test name
Test status
Simulation time 8369166253 ps
CPU time 7.43 seconds
Started Mar 28 01:33:50 PM PDT 24
Finished Mar 28 01:33:58 PM PDT 24
Peak memory 204080 kb
Host smart-fe37f013-cfb5-42c4-8259-68fc5459fe71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21321
83552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.2132183552
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.681016929
Short name T638
Test name
Test status
Simulation time 8400626068 ps
CPU time 7.64 seconds
Started Mar 28 01:33:49 PM PDT 24
Finished Mar 28 01:33:57 PM PDT 24
Peak memory 204060 kb
Host smart-f4e9d0e9-33b1-4a86-9f97-365a1f2d3ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68101
6929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.681016929
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.1252447885
Short name T538
Test name
Test status
Simulation time 23931153 ps
CPU time 0.67 seconds
Started Mar 28 01:33:51 PM PDT 24
Finished Mar 28 01:33:52 PM PDT 24
Peak memory 203968 kb
Host smart-ef0d7b9e-c580-435c-a93f-ba06040d15e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12524
47885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.1252447885
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3362050845
Short name T201
Test name
Test status
Simulation time 28756480981 ps
CPU time 52.5 seconds
Started Mar 28 01:33:50 PM PDT 24
Finished Mar 28 01:34:42 PM PDT 24
Peak memory 204376 kb
Host smart-5eba0e5e-3346-4a8a-a90b-67089c284e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33620
50845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3362050845
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.1128285077
Short name T94
Test name
Test status
Simulation time 8392476654 ps
CPU time 7.67 seconds
Started Mar 28 01:33:49 PM PDT 24
Finished Mar 28 01:33:57 PM PDT 24
Peak memory 204052 kb
Host smart-f1787f6a-66e7-4a2e-b489-11578419f95b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11282
85077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.1128285077
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.2855576405
Short name T635
Test name
Test status
Simulation time 8416187367 ps
CPU time 7.78 seconds
Started Mar 28 01:33:51 PM PDT 24
Finished Mar 28 01:33:59 PM PDT 24
Peak memory 204004 kb
Host smart-fb65a09c-8515-4721-8ad5-8a9bf102a950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28555
76405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.2855576405
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.1478570286
Short name T334
Test name
Test status
Simulation time 8400909936 ps
CPU time 7.8 seconds
Started Mar 28 01:33:51 PM PDT 24
Finished Mar 28 01:33:59 PM PDT 24
Peak memory 204020 kb
Host smart-ddab1f9a-680f-4c58-af5e-90536e6f3a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14785
70286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.1478570286
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.627980626
Short name T529
Test name
Test status
Simulation time 8357431478 ps
CPU time 8.15 seconds
Started Mar 28 01:33:47 PM PDT 24
Finished Mar 28 01:33:55 PM PDT 24
Peak memory 204060 kb
Host smart-6da905c8-68bb-4521-ab2a-5658de587ac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62798
0626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.627980626
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.3150689849
Short name T385
Test name
Test status
Simulation time 8376421792 ps
CPU time 7.16 seconds
Started Mar 28 01:33:47 PM PDT 24
Finished Mar 28 01:33:54 PM PDT 24
Peak memory 204052 kb
Host smart-78c23cdf-1a07-4590-b77f-55e075bbcb69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31506
89849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.3150689849
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.in_iso.2952360017
Short name T414
Test name
Test status
Simulation time 8413900846 ps
CPU time 8.37 seconds
Started Mar 28 01:34:20 PM PDT 24
Finished Mar 28 01:34:29 PM PDT 24
Peak memory 204116 kb
Host smart-98e782fc-06d4-4212-a3e4-f4a5bff5225d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29523
60017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.in_iso.2952360017
Directory /workspace/21.in_iso/latest

Test location /workspace/coverage/default/21.phy_config_usb_ref_disable.2542158416
Short name T28
Test name
Test status
Simulation time 8362756533 ps
CPU time 9.02 seconds
Started Mar 28 01:34:25 PM PDT 24
Finished Mar 28 01:34:35 PM PDT 24
Peak memory 204080 kb
Host smart-463577e1-15bf-4faa-8c45-e08e3312ea3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25421
58416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.phy_config_usb_ref_disable.2542158416
Directory /workspace/21.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2299982847
Short name T616
Test name
Test status
Simulation time 8371338942 ps
CPU time 7.34 seconds
Started Mar 28 01:34:17 PM PDT 24
Finished Mar 28 01:34:25 PM PDT 24
Peak memory 204096 kb
Host smart-36a291ec-ac25-4003-8b8f-0aaae91b2bde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22999
82847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2299982847
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_enable.1656136020
Short name T605
Test name
Test status
Simulation time 8373835442 ps
CPU time 8.25 seconds
Started Mar 28 01:34:20 PM PDT 24
Finished Mar 28 01:34:29 PM PDT 24
Peak memory 204048 kb
Host smart-c650dcfa-49a1-459f-a66c-bbf4f38bfbcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16561
36020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.1656136020
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1160348479
Short name T994
Test name
Test status
Simulation time 112044733 ps
CPU time 1.43 seconds
Started Mar 28 01:34:18 PM PDT 24
Finished Mar 28 01:34:20 PM PDT 24
Peak memory 204260 kb
Host smart-1ff91165-556f-468b-abfe-4197d9b89937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11603
48479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1160348479
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.4072206727
Short name T917
Test name
Test status
Simulation time 8358092035 ps
CPU time 7.02 seconds
Started Mar 28 01:34:20 PM PDT 24
Finished Mar 28 01:34:27 PM PDT 24
Peak memory 204088 kb
Host smart-8b3c4584-149f-471a-af67-3abf967ec603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40722
06727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.4072206727
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.1174258594
Short name T477
Test name
Test status
Simulation time 8395173260 ps
CPU time 7.34 seconds
Started Mar 28 01:34:19 PM PDT 24
Finished Mar 28 01:34:27 PM PDT 24
Peak memory 204020 kb
Host smart-6e096f5b-dbd5-4bc6-9ed4-49fb1939361d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11742
58594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.1174258594
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.2049663944
Short name T1032
Test name
Test status
Simulation time 8416392600 ps
CPU time 9.35 seconds
Started Mar 28 01:34:18 PM PDT 24
Finished Mar 28 01:34:27 PM PDT 24
Peak memory 204096 kb
Host smart-f2ca29ea-4ff3-4532-8d0b-e0cfe922fa4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20496
63944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.2049663944
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3069762169
Short name T501
Test name
Test status
Simulation time 8362909335 ps
CPU time 9.2 seconds
Started Mar 28 01:34:18 PM PDT 24
Finished Mar 28 01:34:27 PM PDT 24
Peak memory 204056 kb
Host smart-c910e512-d1cf-4cc1-aafd-0949c8c78662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30697
62169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3069762169
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1957274950
Short name T915
Test name
Test status
Simulation time 8455499969 ps
CPU time 8.03 seconds
Started Mar 28 01:34:21 PM PDT 24
Finished Mar 28 01:34:29 PM PDT 24
Peak memory 204048 kb
Host smart-b0ffef3d-e1cb-42ff-9ae9-542cd9205501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19572
74950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1957274950
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2316030949
Short name T646
Test name
Test status
Simulation time 8390235191 ps
CPU time 8.34 seconds
Started Mar 28 01:34:18 PM PDT 24
Finished Mar 28 01:34:26 PM PDT 24
Peak memory 204056 kb
Host smart-73094e3c-5452-41b6-b9a6-f629ea780e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23160
30949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2316030949
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.115422812
Short name T406
Test name
Test status
Simulation time 8407629324 ps
CPU time 6.86 seconds
Started Mar 28 01:34:23 PM PDT 24
Finished Mar 28 01:34:30 PM PDT 24
Peak memory 204048 kb
Host smart-35f3ecdf-dca4-4324-9b28-e3f69ef1f009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11542
2812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.115422812
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.3971121872
Short name T735
Test name
Test status
Simulation time 30706413 ps
CPU time 0.63 seconds
Started Mar 28 01:34:25 PM PDT 24
Finished Mar 28 01:34:26 PM PDT 24
Peak memory 204024 kb
Host smart-01dcfc66-b311-4834-97c0-3b93f37e4caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39711
21872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.3971121872
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.3751178861
Short name T189
Test name
Test status
Simulation time 21585314144 ps
CPU time 37.72 seconds
Started Mar 28 01:34:24 PM PDT 24
Finished Mar 28 01:35:01 PM PDT 24
Peak memory 204264 kb
Host smart-e5029071-d60f-4e8a-8c75-dafeb54c16d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37511
78861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.3751178861
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.3855309463
Short name T696
Test name
Test status
Simulation time 8377223636 ps
CPU time 7.61 seconds
Started Mar 28 01:34:19 PM PDT 24
Finished Mar 28 01:34:27 PM PDT 24
Peak memory 204016 kb
Host smart-4dcc1749-a3c1-46fc-858e-bdee61260e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38553
09463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.3855309463
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.428573852
Short name T567
Test name
Test status
Simulation time 8454375985 ps
CPU time 6.91 seconds
Started Mar 28 01:34:22 PM PDT 24
Finished Mar 28 01:34:29 PM PDT 24
Peak memory 204076 kb
Host smart-c740b5f4-c731-4da9-8aaa-c5d4952bf5f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42857
3852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.428573852
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.1484668315
Short name T20
Test name
Test status
Simulation time 8385761558 ps
CPU time 7.88 seconds
Started Mar 28 01:34:25 PM PDT 24
Finished Mar 28 01:34:33 PM PDT 24
Peak memory 204028 kb
Host smart-29bf7b18-9f41-42b8-8c81-4b6af3af2525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14846
68315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.1484668315
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.2753394119
Short name T709
Test name
Test status
Simulation time 8364743308 ps
CPU time 7.21 seconds
Started Mar 28 01:34:23 PM PDT 24
Finished Mar 28 01:34:31 PM PDT 24
Peak memory 204056 kb
Host smart-6c20e4fe-2a9c-42d3-8bac-6aba6588f249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27533
94119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.2753394119
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.3757370282
Short name T925
Test name
Test status
Simulation time 8442226200 ps
CPU time 8.19 seconds
Started Mar 28 01:34:18 PM PDT 24
Finished Mar 28 01:34:26 PM PDT 24
Peak memory 204076 kb
Host smart-d1c7779b-8128-48c5-9365-985319cdc476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37573
70282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.3757370282
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.2244214400
Short name T608
Test name
Test status
Simulation time 8382454786 ps
CPU time 8.8 seconds
Started Mar 28 01:34:20 PM PDT 24
Finished Mar 28 01:34:29 PM PDT 24
Peak memory 203992 kb
Host smart-94bace39-e132-4d10-b420-2ff521bf01dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22442
14400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.2244214400
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.in_iso.1590814886
Short name T341
Test name
Test status
Simulation time 8419311735 ps
CPU time 7.86 seconds
Started Mar 28 01:34:24 PM PDT 24
Finished Mar 28 01:34:32 PM PDT 24
Peak memory 204084 kb
Host smart-9291fbd0-e15c-4f6d-9b30-4c8628c5a89e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15908
14886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.in_iso.1590814886
Directory /workspace/22.in_iso/latest

Test location /workspace/coverage/default/22.phy_config_usb_ref_disable.2627766061
Short name T864
Test name
Test status
Simulation time 8362077459 ps
CPU time 8.95 seconds
Started Mar 28 01:34:24 PM PDT 24
Finished Mar 28 01:34:33 PM PDT 24
Peak memory 204020 kb
Host smart-39f0f1af-1523-43e1-9485-004030f4fa2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26277
66061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.phy_config_usb_ref_disable.2627766061
Directory /workspace/22.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.573432086
Short name T398
Test name
Test status
Simulation time 8371619221 ps
CPU time 7.74 seconds
Started Mar 28 01:34:25 PM PDT 24
Finished Mar 28 01:34:33 PM PDT 24
Peak memory 204084 kb
Host smart-6119e4fd-5a52-4475-8c98-a709c434aa71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57343
2086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.573432086
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_enable.2147562434
Short name T689
Test name
Test status
Simulation time 8368817572 ps
CPU time 7.24 seconds
Started Mar 28 01:34:21 PM PDT 24
Finished Mar 28 01:34:29 PM PDT 24
Peak memory 204024 kb
Host smart-d3fbf5a3-bba4-4509-9954-ef8ab50af44c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21475
62434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.2147562434
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.1162760192
Short name T453
Test name
Test status
Simulation time 129107619 ps
CPU time 1.64 seconds
Started Mar 28 01:34:25 PM PDT 24
Finished Mar 28 01:34:26 PM PDT 24
Peak memory 204264 kb
Host smart-48a5e7b1-b911-4fb2-8646-833455eeb869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11627
60192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1162760192
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.3531495059
Short name T423
Test name
Test status
Simulation time 8359192003 ps
CPU time 7.18 seconds
Started Mar 28 01:34:24 PM PDT 24
Finished Mar 28 01:34:31 PM PDT 24
Peak memory 204088 kb
Host smart-a17fb20b-8749-4f2d-9a6a-55a7e10c0550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35314
95059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.3531495059
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.4071605160
Short name T405
Test name
Test status
Simulation time 8422974035 ps
CPU time 9.47 seconds
Started Mar 28 01:34:22 PM PDT 24
Finished Mar 28 01:34:32 PM PDT 24
Peak memory 204044 kb
Host smart-f1582d27-297e-42d1-acc2-e80950402fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40716
05160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.4071605160
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.911246437
Short name T407
Test name
Test status
Simulation time 8407301021 ps
CPU time 7.86 seconds
Started Mar 28 01:34:26 PM PDT 24
Finished Mar 28 01:34:34 PM PDT 24
Peak memory 204056 kb
Host smart-38cf6d2a-c3b4-42cb-b820-b964b1752d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91124
6437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.911246437
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.579809060
Short name T540
Test name
Test status
Simulation time 8367104630 ps
CPU time 8.31 seconds
Started Mar 28 01:34:25 PM PDT 24
Finished Mar 28 01:34:33 PM PDT 24
Peak memory 204056 kb
Host smart-61779285-5bb9-4ea8-a797-9121a512b379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57980
9060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.579809060
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.2650474647
Short name T831
Test name
Test status
Simulation time 8412334175 ps
CPU time 7.36 seconds
Started Mar 28 01:34:24 PM PDT 24
Finished Mar 28 01:34:32 PM PDT 24
Peak memory 204064 kb
Host smart-f1267abe-74e1-4fd3-a38f-587c01ece929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26504
74647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.2650474647
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2283043390
Short name T307
Test name
Test status
Simulation time 8391907537 ps
CPU time 7.45 seconds
Started Mar 28 01:34:22 PM PDT 24
Finished Mar 28 01:34:30 PM PDT 24
Peak memory 204048 kb
Host smart-2a22498f-000c-4e2a-add7-ba843a979388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22830
43390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2283043390
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.2465010207
Short name T999
Test name
Test status
Simulation time 8401619612 ps
CPU time 7.82 seconds
Started Mar 28 01:34:26 PM PDT 24
Finished Mar 28 01:34:34 PM PDT 24
Peak memory 204044 kb
Host smart-9983be59-bac5-4562-ac3b-03f41e8c0cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24650
10207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2465010207
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.4136368156
Short name T595
Test name
Test status
Simulation time 29963095 ps
CPU time 0.64 seconds
Started Mar 28 01:34:23 PM PDT 24
Finished Mar 28 01:34:24 PM PDT 24
Peak memory 204016 kb
Host smart-3412f463-7898-4015-861c-3e262966fffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41363
68156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.4136368156
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.2404377028
Short name T202
Test name
Test status
Simulation time 20805603029 ps
CPU time 35.73 seconds
Started Mar 28 01:34:24 PM PDT 24
Finished Mar 28 01:35:00 PM PDT 24
Peak memory 204248 kb
Host smart-8cd85ec1-4011-45a1-ad43-5f46a22b28dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24043
77028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.2404377028
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.2430626972
Short name T339
Test name
Test status
Simulation time 8366062767 ps
CPU time 9.56 seconds
Started Mar 28 01:34:24 PM PDT 24
Finished Mar 28 01:34:34 PM PDT 24
Peak memory 204064 kb
Host smart-ff702f54-8f8a-4310-bcc0-f52fa3c3f807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24306
26972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.2430626972
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.1325176422
Short name T534
Test name
Test status
Simulation time 8376500652 ps
CPU time 7.62 seconds
Started Mar 28 01:34:25 PM PDT 24
Finished Mar 28 01:34:32 PM PDT 24
Peak memory 203964 kb
Host smart-b6f91b03-8554-48b6-b636-62dc5ee70c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13251
76422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1325176422
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.1436357722
Short name T978
Test name
Test status
Simulation time 8361127526 ps
CPU time 6.83 seconds
Started Mar 28 01:34:24 PM PDT 24
Finished Mar 28 01:34:31 PM PDT 24
Peak memory 204080 kb
Host smart-52bf5c2e-e50a-49bf-9e74-e2ccd48a471e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14363
57722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.1436357722
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.2393254092
Short name T470
Test name
Test status
Simulation time 8358717866 ps
CPU time 7.18 seconds
Started Mar 28 01:34:24 PM PDT 24
Finished Mar 28 01:34:31 PM PDT 24
Peak memory 204080 kb
Host smart-ab730585-42b7-494f-8a66-ca4c2304b719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23932
54092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.2393254092
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.3138350234
Short name T30
Test name
Test status
Simulation time 8431683635 ps
CPU time 8.51 seconds
Started Mar 28 01:34:25 PM PDT 24
Finished Mar 28 01:34:33 PM PDT 24
Peak memory 204076 kb
Host smart-e24419a6-f84c-4f31-a296-221440b37982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31383
50234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.3138350234
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.3794351681
Short name T343
Test name
Test status
Simulation time 8408729225 ps
CPU time 7.02 seconds
Started Mar 28 01:34:23 PM PDT 24
Finished Mar 28 01:34:30 PM PDT 24
Peak memory 204084 kb
Host smart-9ee01c75-60db-4fea-8064-f23b29f9ecdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37943
51681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.3794351681
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.in_iso.3544340984
Short name T1002
Test name
Test status
Simulation time 8406823121 ps
CPU time 8.15 seconds
Started Mar 28 01:34:20 PM PDT 24
Finished Mar 28 01:34:28 PM PDT 24
Peak memory 204028 kb
Host smart-99147fa5-5cde-4408-a7b5-c32c7450c39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35443
40984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.in_iso.3544340984
Directory /workspace/23.in_iso/latest

Test location /workspace/coverage/default/23.phy_config_usb_ref_disable.1023881895
Short name T1016
Test name
Test status
Simulation time 8361722393 ps
CPU time 8.39 seconds
Started Mar 28 01:34:23 PM PDT 24
Finished Mar 28 01:34:32 PM PDT 24
Peak memory 204036 kb
Host smart-3dee934b-47c0-4e17-af47-e1fa7c5cc586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10238
81895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.phy_config_usb_ref_disable.1023881895
Directory /workspace/23.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3942203417
Short name T869
Test name
Test status
Simulation time 8374287428 ps
CPU time 8.83 seconds
Started Mar 28 01:34:23 PM PDT 24
Finished Mar 28 01:34:31 PM PDT 24
Peak memory 204048 kb
Host smart-55f8260c-c640-4916-a22d-4f72290e2c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39422
03417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3942203417
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_enable.2899734551
Short name T530
Test name
Test status
Simulation time 8372042678 ps
CPU time 7.03 seconds
Started Mar 28 01:34:21 PM PDT 24
Finished Mar 28 01:34:28 PM PDT 24
Peak memory 204048 kb
Host smart-c1330a08-93bc-46ae-a044-372b4c3fc45f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28997
34551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2899734551
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2971436117
Short name T555
Test name
Test status
Simulation time 34164671 ps
CPU time 1.12 seconds
Started Mar 28 01:34:19 PM PDT 24
Finished Mar 28 01:34:21 PM PDT 24
Peak memory 204208 kb
Host smart-402660c3-e065-4f37-9f36-58a7f33c2e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29714
36117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2971436117
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.1422728788
Short name T4
Test name
Test status
Simulation time 8362017360 ps
CPU time 8.29 seconds
Started Mar 28 01:34:24 PM PDT 24
Finished Mar 28 01:34:33 PM PDT 24
Peak memory 204028 kb
Host smart-1165b5ca-30f8-4eb8-91c3-1919802cd4e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14227
28788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.1422728788
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.1421249439
Short name T759
Test name
Test status
Simulation time 8391658983 ps
CPU time 7.91 seconds
Started Mar 28 01:34:18 PM PDT 24
Finished Mar 28 01:34:26 PM PDT 24
Peak memory 204084 kb
Host smart-4b03cb4c-c69b-4d37-bb92-e292143cf042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14212
49439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.1421249439
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3211044717
Short name T930
Test name
Test status
Simulation time 8413065617 ps
CPU time 7.85 seconds
Started Mar 28 01:34:21 PM PDT 24
Finished Mar 28 01:34:29 PM PDT 24
Peak memory 204028 kb
Host smart-19c4ac84-8de7-41ec-b798-672e2e650656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32110
44717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3211044717
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.14869843
Short name T691
Test name
Test status
Simulation time 8361069224 ps
CPU time 7.59 seconds
Started Mar 28 01:34:17 PM PDT 24
Finished Mar 28 01:34:25 PM PDT 24
Peak memory 204024 kb
Host smart-29c3c361-f35c-4bc6-8b20-9d054fa75524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14869
843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.14869843
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.4042833657
Short name T112
Test name
Test status
Simulation time 8427034833 ps
CPU time 7.73 seconds
Started Mar 28 01:34:17 PM PDT 24
Finished Mar 28 01:34:25 PM PDT 24
Peak memory 204024 kb
Host smart-7e97d102-8205-48c9-93bf-abca64f89b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40428
33657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.4042833657
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.1390280701
Short name T1054
Test name
Test status
Simulation time 8401948946 ps
CPU time 7.72 seconds
Started Mar 28 01:34:21 PM PDT 24
Finished Mar 28 01:34:29 PM PDT 24
Peak memory 204052 kb
Host smart-56ae7848-dfc4-46f0-a296-c0032c783086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13902
80701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.1390280701
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.4189232122
Short name T1020
Test name
Test status
Simulation time 8372554497 ps
CPU time 7.37 seconds
Started Mar 28 01:34:17 PM PDT 24
Finished Mar 28 01:34:24 PM PDT 24
Peak memory 204056 kb
Host smart-09e07dab-8e4d-4656-b69e-b6891c697122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41892
32122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.4189232122
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2314575052
Short name T437
Test name
Test status
Simulation time 24413504 ps
CPU time 0.6 seconds
Started Mar 28 01:34:20 PM PDT 24
Finished Mar 28 01:34:21 PM PDT 24
Peak memory 203956 kb
Host smart-70934784-90ea-4cf2-95f4-62d6b1afd82d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23145
75052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2314575052
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.418752028
Short name T200
Test name
Test status
Simulation time 14023858070 ps
CPU time 22.48 seconds
Started Mar 28 01:34:18 PM PDT 24
Finished Mar 28 01:34:41 PM PDT 24
Peak memory 204240 kb
Host smart-90cd353c-6629-4b06-8166-4e7437afba2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41875
2028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.418752028
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.3455868846
Short name T536
Test name
Test status
Simulation time 8384091956 ps
CPU time 8.06 seconds
Started Mar 28 01:34:20 PM PDT 24
Finished Mar 28 01:34:28 PM PDT 24
Peak memory 204016 kb
Host smart-1cf0bdc9-2ca8-442e-8aa7-7529a74705f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34558
68846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.3455868846
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.1262295036
Short name T420
Test name
Test status
Simulation time 8401863674 ps
CPU time 8.6 seconds
Started Mar 28 01:34:17 PM PDT 24
Finished Mar 28 01:34:26 PM PDT 24
Peak memory 204056 kb
Host smart-17243220-15ae-4c5c-8c8a-2f10879f240b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12622
95036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.1262295036
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.3506775931
Short name T788
Test name
Test status
Simulation time 8388821170 ps
CPU time 7.04 seconds
Started Mar 28 01:34:24 PM PDT 24
Finished Mar 28 01:34:31 PM PDT 24
Peak memory 204052 kb
Host smart-9ffd18b8-8271-4231-9dad-511f4861fcd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35067
75931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.3506775931
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.815187434
Short name T655
Test name
Test status
Simulation time 8354296527 ps
CPU time 6.91 seconds
Started Mar 28 01:34:25 PM PDT 24
Finished Mar 28 01:34:32 PM PDT 24
Peak memory 204036 kb
Host smart-accf1eb4-cba8-4bf4-b6a2-bb42435afd0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81518
7434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.815187434
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.2373523006
Short name T589
Test name
Test status
Simulation time 8385970563 ps
CPU time 7.19 seconds
Started Mar 28 01:34:24 PM PDT 24
Finished Mar 28 01:34:31 PM PDT 24
Peak memory 204080 kb
Host smart-8c0df532-ccc8-4205-95f0-675a942457a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23735
23006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.2373523006
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.in_iso.840522093
Short name T371
Test name
Test status
Simulation time 8395084184 ps
CPU time 8.15 seconds
Started Mar 28 01:34:23 PM PDT 24
Finished Mar 28 01:34:31 PM PDT 24
Peak memory 204080 kb
Host smart-ee27d28c-3aa5-4808-a001-355d1215a8bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84052
2093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.in_iso.840522093
Directory /workspace/24.in_iso/latest

Test location /workspace/coverage/default/24.phy_config_usb_ref_disable.3364984872
Short name T678
Test name
Test status
Simulation time 8367457185 ps
CPU time 6.83 seconds
Started Mar 28 01:34:24 PM PDT 24
Finished Mar 28 01:34:31 PM PDT 24
Peak memory 204052 kb
Host smart-c8eac9da-80d5-4e73-9332-e4f692b1e198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33649
84872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.phy_config_usb_ref_disable.3364984872
Directory /workspace/24.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.1679884799
Short name T906
Test name
Test status
Simulation time 8366650210 ps
CPU time 7.12 seconds
Started Mar 28 01:34:26 PM PDT 24
Finished Mar 28 01:34:33 PM PDT 24
Peak memory 204076 kb
Host smart-2644bc41-0e25-414f-bba2-8beb7131bbdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16798
84799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.1679884799
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_enable.2857400029
Short name T937
Test name
Test status
Simulation time 8366061842 ps
CPU time 7.36 seconds
Started Mar 28 01:34:26 PM PDT 24
Finished Mar 28 01:34:33 PM PDT 24
Peak memory 204080 kb
Host smart-31f60cd9-66d2-4f99-9d84-72bd6da84da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28574
00029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.2857400029
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.67661676
Short name T728
Test name
Test status
Simulation time 219218075 ps
CPU time 1.98 seconds
Started Mar 28 01:34:21 PM PDT 24
Finished Mar 28 01:34:23 PM PDT 24
Peak memory 204164 kb
Host smart-88ab30ce-bc5b-4e0a-8540-e11fd7e16f06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67661
676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.67661676
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.753085995
Short name T684
Test name
Test status
Simulation time 8380039731 ps
CPU time 7.51 seconds
Started Mar 28 01:34:21 PM PDT 24
Finished Mar 28 01:34:28 PM PDT 24
Peak memory 204056 kb
Host smart-2363ead0-cb30-40be-9743-d8da663223f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75308
5995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.753085995
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.1707130405
Short name T586
Test name
Test status
Simulation time 8404977655 ps
CPU time 7.08 seconds
Started Mar 28 01:34:20 PM PDT 24
Finished Mar 28 01:34:27 PM PDT 24
Peak memory 204088 kb
Host smart-19512b00-8adc-417d-86fe-ef49a9be0644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17071
30405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.1707130405
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3677033738
Short name T269
Test name
Test status
Simulation time 8366491046 ps
CPU time 8.85 seconds
Started Mar 28 01:34:21 PM PDT 24
Finished Mar 28 01:34:30 PM PDT 24
Peak memory 204064 kb
Host smart-1aec0c47-21ac-4a2d-9dd0-6c7fa61de12f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36770
33738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3677033738
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.3167535753
Short name T127
Test name
Test status
Simulation time 8451467650 ps
CPU time 7.95 seconds
Started Mar 28 01:34:21 PM PDT 24
Finished Mar 28 01:34:29 PM PDT 24
Peak memory 204056 kb
Host smart-3885f7f7-14dc-4e07-b2f6-2fe7dcf90933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31675
35753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.3167535753
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.1418420565
Short name T426
Test name
Test status
Simulation time 8399858263 ps
CPU time 7.77 seconds
Started Mar 28 01:34:25 PM PDT 24
Finished Mar 28 01:34:33 PM PDT 24
Peak memory 204052 kb
Host smart-9499efa7-a933-48d7-9d68-2babcbdadc33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14184
20565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.1418420565
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.552247429
Short name T963
Test name
Test status
Simulation time 8393072034 ps
CPU time 9.16 seconds
Started Mar 28 01:34:25 PM PDT 24
Finished Mar 28 01:34:34 PM PDT 24
Peak memory 204116 kb
Host smart-409e8616-fe56-42c6-b3a6-9a6239f9b69a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55224
7429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.552247429
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.2340769317
Short name T751
Test name
Test status
Simulation time 22149163 ps
CPU time 0.62 seconds
Started Mar 28 01:34:22 PM PDT 24
Finished Mar 28 01:34:23 PM PDT 24
Peak memory 204012 kb
Host smart-86042056-b237-4b88-802c-995b7d593bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23407
69317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.2340769317
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.228453599
Short name T957
Test name
Test status
Simulation time 20986187781 ps
CPU time 34.12 seconds
Started Mar 28 01:34:20 PM PDT 24
Finished Mar 28 01:34:54 PM PDT 24
Peak memory 204352 kb
Host smart-16eb463d-709c-4825-890f-e44ff13d5cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22845
3599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.228453599
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.3172976787
Short name T946
Test name
Test status
Simulation time 8408464241 ps
CPU time 7.2 seconds
Started Mar 28 01:34:19 PM PDT 24
Finished Mar 28 01:34:27 PM PDT 24
Peak memory 204096 kb
Host smart-e302bb10-c484-4807-9f81-afa376d1eb3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31729
76787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.3172976787
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.3257124258
Short name T704
Test name
Test status
Simulation time 8439590760 ps
CPU time 7.87 seconds
Started Mar 28 01:34:25 PM PDT 24
Finished Mar 28 01:34:33 PM PDT 24
Peak memory 204088 kb
Host smart-cb874f7f-1837-46ff-908a-bd75e6b184fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32571
24258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.3257124258
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.187684092
Short name T457
Test name
Test status
Simulation time 8369229226 ps
CPU time 6.97 seconds
Started Mar 28 01:34:25 PM PDT 24
Finished Mar 28 01:34:32 PM PDT 24
Peak memory 203984 kb
Host smart-9aa692be-8c76-45cc-97a2-63760d7c15e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18768
4092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.187684092
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2872986835
Short name T482
Test name
Test status
Simulation time 8361422821 ps
CPU time 6.9 seconds
Started Mar 28 01:34:26 PM PDT 24
Finished Mar 28 01:34:32 PM PDT 24
Peak memory 204064 kb
Host smart-579574a5-046f-46b4-a954-c79b86cfc15e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28729
86835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2872986835
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.1300139960
Short name T177
Test name
Test status
Simulation time 8469193008 ps
CPU time 7.34 seconds
Started Mar 28 01:34:25 PM PDT 24
Finished Mar 28 01:34:32 PM PDT 24
Peak memory 204024 kb
Host smart-e7baee58-5cbf-406c-87cf-42220b7f9b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13001
39960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.1300139960
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.1418301393
Short name T435
Test name
Test status
Simulation time 8376950819 ps
CPU time 8.75 seconds
Started Mar 28 01:34:23 PM PDT 24
Finished Mar 28 01:34:32 PM PDT 24
Peak memory 204076 kb
Host smart-ffeb9190-7cf5-45e7-9ec3-9e1602f3a558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14183
01393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.1418301393
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.in_iso.3658152387
Short name T965
Test name
Test status
Simulation time 8414024825 ps
CPU time 9.4 seconds
Started Mar 28 01:34:43 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204112 kb
Host smart-04c69302-7278-4bd6-a7e2-d6908f34f617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36581
52387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.in_iso.3658152387
Directory /workspace/25.in_iso/latest

Test location /workspace/coverage/default/25.phy_config_usb_ref_disable.2342175796
Short name T829
Test name
Test status
Simulation time 8364289251 ps
CPU time 7.67 seconds
Started Mar 28 01:34:43 PM PDT 24
Finished Mar 28 01:34:52 PM PDT 24
Peak memory 204088 kb
Host smart-036b78c2-32f4-49a8-81d6-084e9f6baad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23421
75796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.phy_config_usb_ref_disable.2342175796
Directory /workspace/25.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.1747656207
Short name T761
Test name
Test status
Simulation time 8370047532 ps
CPU time 7.45 seconds
Started Mar 28 01:34:25 PM PDT 24
Finished Mar 28 01:34:32 PM PDT 24
Peak memory 204076 kb
Host smart-2279f230-2c1e-4726-aa44-833b95f54b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17476
56207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.1747656207
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_enable.3519782862
Short name T688
Test name
Test status
Simulation time 8374346855 ps
CPU time 7.11 seconds
Started Mar 28 01:34:23 PM PDT 24
Finished Mar 28 01:34:30 PM PDT 24
Peak memory 204080 kb
Host smart-700a6ba9-1437-4c34-906f-5a75572098bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35197
82862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3519782862
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1310629502
Short name T859
Test name
Test status
Simulation time 193015251 ps
CPU time 2.18 seconds
Started Mar 28 01:34:24 PM PDT 24
Finished Mar 28 01:34:26 PM PDT 24
Peak memory 204164 kb
Host smart-1cf44ef8-bfb1-42c2-809e-d6fc035b2249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13106
29502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1310629502
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.219619399
Short name T943
Test name
Test status
Simulation time 8447123422 ps
CPU time 8.04 seconds
Started Mar 28 01:34:22 PM PDT 24
Finished Mar 28 01:34:30 PM PDT 24
Peak memory 204072 kb
Host smart-90536c87-2ef4-4314-93e3-9f481a1dfcb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21961
9399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.219619399
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1389348553
Short name T104
Test name
Test status
Simulation time 8405270408 ps
CPU time 9.63 seconds
Started Mar 28 01:34:23 PM PDT 24
Finished Mar 28 01:34:33 PM PDT 24
Peak memory 204092 kb
Host smart-2d7209aa-f22a-49c3-9285-3afd388aefc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13893
48553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1389348553
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.127679060
Short name T351
Test name
Test status
Simulation time 8360417619 ps
CPU time 7.45 seconds
Started Mar 28 01:34:23 PM PDT 24
Finished Mar 28 01:34:31 PM PDT 24
Peak memory 204084 kb
Host smart-9abc1d8a-30ae-4d25-a58b-7f5b4a05dbbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12767
9060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.127679060
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.919137080
Short name T631
Test name
Test status
Simulation time 8371012177 ps
CPU time 7.62 seconds
Started Mar 28 01:34:18 PM PDT 24
Finished Mar 28 01:34:26 PM PDT 24
Peak memory 204056 kb
Host smart-6e00bf3e-2378-484a-b0a4-7e08d013f7da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91913
7080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.919137080
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3656089914
Short name T373
Test name
Test status
Simulation time 8375790800 ps
CPU time 7.73 seconds
Started Mar 28 01:34:20 PM PDT 24
Finished Mar 28 01:34:28 PM PDT 24
Peak memory 204060 kb
Host smart-813fb0c4-05be-4aea-9b4e-90a9d5b7a3e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36560
89914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3656089914
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.1754322310
Short name T858
Test name
Test status
Simulation time 27254287 ps
CPU time 0.63 seconds
Started Mar 28 01:34:40 PM PDT 24
Finished Mar 28 01:34:43 PM PDT 24
Peak memory 203968 kb
Host smart-1f1111d4-6a2d-463b-8e7e-4ee9bb007147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17543
22310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.1754322310
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.2641851988
Short name T192
Test name
Test status
Simulation time 18453826349 ps
CPU time 32.11 seconds
Started Mar 28 01:34:23 PM PDT 24
Finished Mar 28 01:34:55 PM PDT 24
Peak memory 204240 kb
Host smart-2e0c4a0d-9169-47d8-9ada-24b5987192d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26418
51988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.2641851988
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.1477431219
Short name T1030
Test name
Test status
Simulation time 8367323931 ps
CPU time 7.39 seconds
Started Mar 28 01:34:20 PM PDT 24
Finished Mar 28 01:34:27 PM PDT 24
Peak memory 204024 kb
Host smart-e4e27740-1757-4c74-9780-e498f9400da3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14774
31219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.1477431219
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1936313853
Short name T158
Test name
Test status
Simulation time 8380590003 ps
CPU time 7.16 seconds
Started Mar 28 01:34:18 PM PDT 24
Finished Mar 28 01:34:25 PM PDT 24
Peak memory 204084 kb
Host smart-5627e469-2437-4bcd-bf32-9c62bd80c914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19363
13853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1936313853
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.961875361
Short name T924
Test name
Test status
Simulation time 8399559598 ps
CPU time 7.96 seconds
Started Mar 28 01:34:20 PM PDT 24
Finished Mar 28 01:34:28 PM PDT 24
Peak memory 204060 kb
Host smart-d38a627d-cec5-4f24-9b18-81e90290ecd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96187
5361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.961875361
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.3777920999
Short name T1047
Test name
Test status
Simulation time 8362421589 ps
CPU time 9.13 seconds
Started Mar 28 01:34:22 PM PDT 24
Finished Mar 28 01:34:31 PM PDT 24
Peak memory 204048 kb
Host smart-b1c5f32a-5ec2-4abe-ac63-c139783e55af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37779
20999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.3777920999
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3400825386
Short name T254
Test name
Test status
Simulation time 8402770252 ps
CPU time 7.12 seconds
Started Mar 28 01:34:42 PM PDT 24
Finished Mar 28 01:34:50 PM PDT 24
Peak memory 204060 kb
Host smart-fb31677b-6fec-45c1-9bc0-da2e4a32525d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34008
25386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3400825386
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.in_iso.885261516
Short name T652
Test name
Test status
Simulation time 8398209170 ps
CPU time 7.65 seconds
Started Mar 28 01:34:48 PM PDT 24
Finished Mar 28 01:34:57 PM PDT 24
Peak memory 204080 kb
Host smart-37ad487c-0c67-47f6-a11f-70e762356afe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88526
1516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.in_iso.885261516
Directory /workspace/26.in_iso/latest

Test location /workspace/coverage/default/26.phy_config_usb_ref_disable.3582372187
Short name T936
Test name
Test status
Simulation time 8360455110 ps
CPU time 7.28 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:52 PM PDT 24
Peak memory 204040 kb
Host smart-332106fb-d611-4f22-8866-5e057234fad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35823
72187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.phy_config_usb_ref_disable.3582372187
Directory /workspace/26.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.3481750003
Short name T337
Test name
Test status
Simulation time 8369245497 ps
CPU time 8.38 seconds
Started Mar 28 01:34:36 PM PDT 24
Finished Mar 28 01:34:45 PM PDT 24
Peak memory 204056 kb
Host smart-50fa972f-24a1-4b9a-afdd-890772828074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34817
50003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.3481750003
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_enable.1070523783
Short name T92
Test name
Test status
Simulation time 8365782933 ps
CPU time 6.93 seconds
Started Mar 28 01:34:42 PM PDT 24
Finished Mar 28 01:34:50 PM PDT 24
Peak memory 204012 kb
Host smart-cb6774e1-b0e4-4f8c-b44c-5af61980d168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10705
23783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.1070523783
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.3463614897
Short name T500
Test name
Test status
Simulation time 197665464 ps
CPU time 1.79 seconds
Started Mar 28 01:34:40 PM PDT 24
Finished Mar 28 01:34:44 PM PDT 24
Peak memory 204228 kb
Host smart-8628c671-704c-446d-a369-e6f51dd0c7eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34636
14897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.3463614897
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.1151913184
Short name T813
Test name
Test status
Simulation time 8364642729 ps
CPU time 7.91 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204032 kb
Host smart-69c9c03f-f072-4562-b76f-c4848b2a30d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11519
13184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1151913184
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.1730052630
Short name T151
Test name
Test status
Simulation time 8388731321 ps
CPU time 9.21 seconds
Started Mar 28 01:34:44 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204088 kb
Host smart-1cedff43-d0bb-498a-bccc-2180fc987542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17300
52630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.1730052630
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.2899858833
Short name T82
Test name
Test status
Simulation time 8414662744 ps
CPU time 9.28 seconds
Started Mar 28 01:34:40 PM PDT 24
Finished Mar 28 01:34:52 PM PDT 24
Peak memory 203828 kb
Host smart-b52b1de2-32b7-43b4-9a5e-289f0eeaf339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28998
58833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.2899858833
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1187774039
Short name T989
Test name
Test status
Simulation time 8366078576 ps
CPU time 7.6 seconds
Started Mar 28 01:34:46 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204048 kb
Host smart-770a9762-b931-40eb-9468-939be12dac05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11877
74039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1187774039
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.1869135981
Short name T136
Test name
Test status
Simulation time 8440168869 ps
CPU time 7.12 seconds
Started Mar 28 01:34:43 PM PDT 24
Finished Mar 28 01:34:51 PM PDT 24
Peak memory 204092 kb
Host smart-8e862439-58c0-4946-8312-823f558d73a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18691
35981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.1869135981
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.1548057838
Short name T667
Test name
Test status
Simulation time 8400821903 ps
CPU time 7.06 seconds
Started Mar 28 01:34:43 PM PDT 24
Finished Mar 28 01:34:51 PM PDT 24
Peak memory 204088 kb
Host smart-0dc6f3bd-0d36-48e6-b8f9-8e7698f55f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15480
57838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.1548057838
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.280909267
Short name T342
Test name
Test status
Simulation time 8374130103 ps
CPU time 8.94 seconds
Started Mar 28 01:34:48 PM PDT 24
Finished Mar 28 01:34:58 PM PDT 24
Peak memory 204024 kb
Host smart-66efb51f-969b-43a2-a51a-781b7fbda9c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28090
9267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.280909267
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1630443847
Short name T628
Test name
Test status
Simulation time 25323891 ps
CPU time 0.69 seconds
Started Mar 28 01:34:43 PM PDT 24
Finished Mar 28 01:34:45 PM PDT 24
Peak memory 204048 kb
Host smart-ce16d0fa-4cd7-4b21-98ae-308466577c03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16304
43847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1630443847
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.1099245574
Short name T692
Test name
Test status
Simulation time 17022441437 ps
CPU time 28.3 seconds
Started Mar 28 01:34:48 PM PDT 24
Finished Mar 28 01:35:17 PM PDT 24
Peak memory 204168 kb
Host smart-ae87b989-9c11-4134-ab1a-7b367226af50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10992
45574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.1099245574
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.3267514741
Short name T347
Test name
Test status
Simulation time 8405098269 ps
CPU time 7.06 seconds
Started Mar 28 01:34:46 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204100 kb
Host smart-a156ad4f-6c31-48ae-adbf-20d0222c58c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32675
14741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.3267514741
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.3294851287
Short name T154
Test name
Test status
Simulation time 8451360291 ps
CPU time 8.66 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:54 PM PDT 24
Peak memory 204044 kb
Host smart-38165d05-bc53-4022-9673-aa84b4d2ce93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32948
51287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.3294851287
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.2072546585
Short name T235
Test name
Test status
Simulation time 8400121036 ps
CPU time 7.73 seconds
Started Mar 28 01:34:44 PM PDT 24
Finished Mar 28 01:34:52 PM PDT 24
Peak memory 204012 kb
Host smart-ff8770a0-1866-4ece-9199-6d7c89f7cd91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20725
46585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.2072546585
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2786974179
Short name T345
Test name
Test status
Simulation time 8358389620 ps
CPU time 7.75 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204004 kb
Host smart-b7319f9b-0727-4a2d-9226-a2a331709317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27869
74179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2786974179
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.4194215390
Short name T179
Test name
Test status
Simulation time 8413540764 ps
CPU time 7.38 seconds
Started Mar 28 01:34:39 PM PDT 24
Finished Mar 28 01:34:50 PM PDT 24
Peak memory 204044 kb
Host smart-d572680e-af49-445f-9c76-3c7108a14057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41942
15390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.4194215390
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.4262388277
Short name T419
Test name
Test status
Simulation time 8396565618 ps
CPU time 7.97 seconds
Started Mar 28 01:34:47 PM PDT 24
Finished Mar 28 01:34:56 PM PDT 24
Peak memory 204096 kb
Host smart-40d7754d-00cc-4e1f-9f5f-a9b4bf65685e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42623
88277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.4262388277
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.in_iso.2066267722
Short name T669
Test name
Test status
Simulation time 8372588809 ps
CPU time 7.56 seconds
Started Mar 28 01:34:49 PM PDT 24
Finished Mar 28 01:34:58 PM PDT 24
Peak memory 204020 kb
Host smart-e780f452-7b5f-44d8-a7fa-4c52a34ea396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20662
67722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.in_iso.2066267722
Directory /workspace/27.in_iso/latest

Test location /workspace/coverage/default/27.phy_config_usb_ref_disable.2175388912
Short name T719
Test name
Test status
Simulation time 8365685754 ps
CPU time 6.98 seconds
Started Mar 28 01:34:51 PM PDT 24
Finished Mar 28 01:34:58 PM PDT 24
Peak memory 204044 kb
Host smart-b55cdc42-918a-4aed-bf8d-8bd891afb60e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21753
88912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.phy_config_usb_ref_disable.2175388912
Directory /workspace/27.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.4203539504
Short name T849
Test name
Test status
Simulation time 8376819907 ps
CPU time 7.61 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204088 kb
Host smart-06212e2f-1eb6-43e9-99e4-55771348b255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42035
39504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.4203539504
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_enable.2415225669
Short name T734
Test name
Test status
Simulation time 8366886732 ps
CPU time 7.93 seconds
Started Mar 28 01:34:47 PM PDT 24
Finished Mar 28 01:34:55 PM PDT 24
Peak memory 204076 kb
Host smart-8e8ce00b-a06b-45a1-bdfb-fe7db565a682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24152
25669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2415225669
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.2777817526
Short name T366
Test name
Test status
Simulation time 102981705 ps
CPU time 1.1 seconds
Started Mar 28 01:34:50 PM PDT 24
Finished Mar 28 01:34:51 PM PDT 24
Peak memory 204136 kb
Host smart-d0a1332b-8dc6-4fad-b76f-436faa260267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27778
17526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2777817526
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.3378960381
Short name T185
Test name
Test status
Simulation time 8358467317 ps
CPU time 7.02 seconds
Started Mar 28 01:34:50 PM PDT 24
Finished Mar 28 01:34:57 PM PDT 24
Peak memory 204060 kb
Host smart-01b2e042-5343-4534-b240-a7134fe1db55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33789
60381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.3378960381
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.3318456253
Short name T1003
Test name
Test status
Simulation time 8442954544 ps
CPU time 7.73 seconds
Started Mar 28 01:34:47 PM PDT 24
Finished Mar 28 01:34:55 PM PDT 24
Peak memory 204076 kb
Host smart-77ead9b8-9c25-46f2-be19-19c48f1fd110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33184
56253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.3318456253
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.124122531
Short name T1055
Test name
Test status
Simulation time 8411568523 ps
CPU time 8.24 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:54 PM PDT 24
Peak memory 204080 kb
Host smart-536b4365-7a4e-40a9-8ee5-11ef3163847e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12412
2531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.124122531
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.1171114809
Short name T1059
Test name
Test status
Simulation time 8367460283 ps
CPU time 7.42 seconds
Started Mar 28 01:34:47 PM PDT 24
Finished Mar 28 01:34:54 PM PDT 24
Peak memory 204068 kb
Host smart-460faf77-66f3-4e14-9c20-2889485b4274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11711
14809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.1171114809
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1216212837
Short name T114
Test name
Test status
Simulation time 8420749181 ps
CPU time 8.28 seconds
Started Mar 28 01:34:46 PM PDT 24
Finished Mar 28 01:34:54 PM PDT 24
Peak memory 204068 kb
Host smart-d73f8507-647a-4975-aa9a-631ab7c7a375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12162
12837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1216212837
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.635180141
Short name T45
Test name
Test status
Simulation time 8389630227 ps
CPU time 7.33 seconds
Started Mar 28 01:34:46 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204084 kb
Host smart-2b4d39d3-1dbb-48d3-8e77-83340c338917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63518
0141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.635180141
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.3361377785
Short name T355
Test name
Test status
Simulation time 8405989514 ps
CPU time 7.12 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204100 kb
Host smart-69b39bea-32fb-4c1d-8dd5-5c4c266a9e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33613
77785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.3361377785
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.569554938
Short name T566
Test name
Test status
Simulation time 28521134 ps
CPU time 0.68 seconds
Started Mar 28 01:34:50 PM PDT 24
Finished Mar 28 01:34:51 PM PDT 24
Peak memory 203964 kb
Host smart-851e36b8-2435-4b02-8a9f-53fbe3a32edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56955
4938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.569554938
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.3250974043
Short name T223
Test name
Test status
Simulation time 28890030240 ps
CPU time 58.23 seconds
Started Mar 28 01:34:49 PM PDT 24
Finished Mar 28 01:35:47 PM PDT 24
Peak memory 204256 kb
Host smart-5ffb2d7f-185d-4133-9270-d21954ddf3fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32509
74043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.3250974043
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.2304085664
Short name T722
Test name
Test status
Simulation time 8397603485 ps
CPU time 8.62 seconds
Started Mar 28 01:34:52 PM PDT 24
Finished Mar 28 01:35:01 PM PDT 24
Peak memory 204048 kb
Host smart-24c96253-69c3-4ed9-8c4a-8d05d9a2f6cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23040
85664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.2304085664
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.348819663
Short name T739
Test name
Test status
Simulation time 8430716096 ps
CPU time 7.97 seconds
Started Mar 28 01:34:51 PM PDT 24
Finished Mar 28 01:34:59 PM PDT 24
Peak memory 204068 kb
Host smart-2ef63cbd-a0b4-41cd-aee2-26f4d9c34c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34881
9663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.348819663
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.4272509808
Short name T302
Test name
Test status
Simulation time 8407444383 ps
CPU time 8.27 seconds
Started Mar 28 01:34:50 PM PDT 24
Finished Mar 28 01:34:59 PM PDT 24
Peak memory 204048 kb
Host smart-e2f30b1e-691e-47a3-a6f1-a4026e18a09a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42725
09808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.4272509808
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.2811773875
Short name T784
Test name
Test status
Simulation time 8363998145 ps
CPU time 7.16 seconds
Started Mar 28 01:34:50 PM PDT 24
Finished Mar 28 01:34:57 PM PDT 24
Peak memory 204044 kb
Host smart-fee524bb-4c8a-4736-81b9-8fe18351de03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28117
73875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.2811773875
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.306137192
Short name T169
Test name
Test status
Simulation time 8397870240 ps
CPU time 8.83 seconds
Started Mar 28 01:34:44 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204072 kb
Host smart-21b93728-731a-4788-9bb9-5ec21cf20979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30613
7192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.306137192
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.2885882503
Short name T894
Test name
Test status
Simulation time 8395562007 ps
CPU time 7.28 seconds
Started Mar 28 01:34:47 PM PDT 24
Finished Mar 28 01:34:55 PM PDT 24
Peak memory 203172 kb
Host smart-227b2450-9ea5-473e-a260-3cdea0011f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28858
82503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.2885882503
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.in_iso.3160327500
Short name T325
Test name
Test status
Simulation time 8393328936 ps
CPU time 7.94 seconds
Started Mar 28 01:34:48 PM PDT 24
Finished Mar 28 01:34:57 PM PDT 24
Peak memory 204080 kb
Host smart-f6831c04-eed4-4612-a386-1a549ad08578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31603
27500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.in_iso.3160327500
Directory /workspace/28.in_iso/latest

Test location /workspace/coverage/default/28.phy_config_usb_ref_disable.4283849557
Short name T8
Test name
Test status
Simulation time 8359183285 ps
CPU time 7.31 seconds
Started Mar 28 01:34:46 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204040 kb
Host smart-04ea135e-217d-486a-84f4-d38fd34a3d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42838
49557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.phy_config_usb_ref_disable.4283849557
Directory /workspace/28.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.714966882
Short name T1035
Test name
Test status
Simulation time 8372583155 ps
CPU time 8.66 seconds
Started Mar 28 01:34:41 PM PDT 24
Finished Mar 28 01:34:51 PM PDT 24
Peak memory 204012 kb
Host smart-17cb10a8-2604-40ed-baf1-a3c571348894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71496
6882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.714966882
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_enable.3170435740
Short name T585
Test name
Test status
Simulation time 8370283888 ps
CPU time 7.5 seconds
Started Mar 28 01:34:43 PM PDT 24
Finished Mar 28 01:34:51 PM PDT 24
Peak memory 204084 kb
Host smart-c600b38e-8550-4f7b-b03e-019b1c22b97a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31704
35740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3170435740
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.3465842
Short name T1026
Test name
Test status
Simulation time 247897007 ps
CPU time 2.03 seconds
Started Mar 28 01:34:40 PM PDT 24
Finished Mar 28 01:34:44 PM PDT 24
Peak memory 204228 kb
Host smart-3b0f5a11-0b00-4b0a-ab7c-ea25d18b48a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34658
42 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.3465842
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.2623383620
Short name T224
Test name
Test status
Simulation time 8358111753 ps
CPU time 7.15 seconds
Started Mar 28 01:34:44 PM PDT 24
Finished Mar 28 01:34:52 PM PDT 24
Peak memory 203996 kb
Host smart-a2d9f3a1-fe4a-4a3d-9424-cb47b79209ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26233
83620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.2623383620
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.4281248134
Short name T626
Test name
Test status
Simulation time 8451031543 ps
CPU time 7.78 seconds
Started Mar 28 01:34:42 PM PDT 24
Finished Mar 28 01:34:50 PM PDT 24
Peak memory 204072 kb
Host smart-217fac8b-071f-453a-ae46-d00cb12241b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42812
48134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.4281248134
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.2842679308
Short name T410
Test name
Test status
Simulation time 8408358197 ps
CPU time 8.69 seconds
Started Mar 28 01:34:39 PM PDT 24
Finished Mar 28 01:34:51 PM PDT 24
Peak memory 204088 kb
Host smart-b2a7bde4-b593-4d73-b085-fc4ca1f0d7c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28426
79308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.2842679308
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.4279190933
Short name T527
Test name
Test status
Simulation time 8364108815 ps
CPU time 7.27 seconds
Started Mar 28 01:34:46 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204028 kb
Host smart-6268181f-45de-412e-a959-58fa1bc02278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42791
90933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.4279190933
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.124460327
Short name T115
Test name
Test status
Simulation time 8405129281 ps
CPU time 9.2 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:54 PM PDT 24
Peak memory 204048 kb
Host smart-d23f2c37-d722-45a2-905c-e78e1be9d7c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12446
0327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.124460327
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.4266156469
Short name T352
Test name
Test status
Simulation time 8382718596 ps
CPU time 7.66 seconds
Started Mar 28 01:34:43 PM PDT 24
Finished Mar 28 01:34:52 PM PDT 24
Peak memory 204124 kb
Host smart-04c800bd-2b1f-48f9-b8bd-b8083e4b91db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42661
56469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.4266156469
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.3089642206
Short name T316
Test name
Test status
Simulation time 8377055195 ps
CPU time 8.89 seconds
Started Mar 28 01:34:38 PM PDT 24
Finished Mar 28 01:34:51 PM PDT 24
Peak memory 204096 kb
Host smart-d0f3d240-f78c-4d8e-868f-8d58923d72f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30896
42206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.3089642206
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.383482983
Short name T460
Test name
Test status
Simulation time 23555453 ps
CPU time 0.64 seconds
Started Mar 28 01:34:46 PM PDT 24
Finished Mar 28 01:34:47 PM PDT 24
Peak memory 204032 kb
Host smart-98f28832-dc3d-4b99-a14f-277a53ae1ee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38348
2983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.383482983
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.2552746452
Short name T903
Test name
Test status
Simulation time 14489787072 ps
CPU time 23.5 seconds
Started Mar 28 01:34:41 PM PDT 24
Finished Mar 28 01:35:06 PM PDT 24
Peak memory 204264 kb
Host smart-d00aaa35-b8d1-4dc2-8b14-02e904ffc231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25527
46452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.2552746452
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.1430998597
Short name T514
Test name
Test status
Simulation time 8373940096 ps
CPU time 7.32 seconds
Started Mar 28 01:34:42 PM PDT 24
Finished Mar 28 01:34:50 PM PDT 24
Peak memory 204072 kb
Host smart-8236a3ea-fb68-44f7-a8ff-a8245a9d54ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14309
98597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.1430998597
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.900179099
Short name T956
Test name
Test status
Simulation time 8457681973 ps
CPU time 9.41 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:54 PM PDT 24
Peak memory 204112 kb
Host smart-72145ae5-04f4-49b3-8a80-0cdded9a0846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90017
9099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.900179099
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.1726284834
Short name T993
Test name
Test status
Simulation time 8396699645 ps
CPU time 7.29 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:52 PM PDT 24
Peak memory 204056 kb
Host smart-027d3fee-22ae-44b3-9b87-5d521e7335fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17262
84834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.1726284834
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.4124905431
Short name T985
Test name
Test status
Simulation time 8357150218 ps
CPU time 7.26 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:52 PM PDT 24
Peak memory 204120 kb
Host smart-26617acb-12e1-41dd-a8f5-7c24ae2c2588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41249
05431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.4124905431
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3838681660
Short name T163
Test name
Test status
Simulation time 8428605545 ps
CPU time 7.36 seconds
Started Mar 28 01:34:39 PM PDT 24
Finished Mar 28 01:34:50 PM PDT 24
Peak memory 204084 kb
Host smart-3a4973a3-3343-4ba6-8a3d-dd6614cd950b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38386
81660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3838681660
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.2606725361
Short name T551
Test name
Test status
Simulation time 8400805683 ps
CPU time 7.16 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:52 PM PDT 24
Peak memory 204048 kb
Host smart-c1c55f21-c9dc-4642-944b-2bf8a59ba061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26067
25361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.2606725361
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.in_iso.3204588617
Short name T653
Test name
Test status
Simulation time 8383884213 ps
CPU time 8.4 seconds
Started Mar 28 01:34:52 PM PDT 24
Finished Mar 28 01:35:01 PM PDT 24
Peak memory 204016 kb
Host smart-47bbada1-b63f-4e41-b1b9-a39da325f469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32045
88617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.in_iso.3204588617
Directory /workspace/29.in_iso/latest

Test location /workspace/coverage/default/29.phy_config_usb_ref_disable.4232226471
Short name T948
Test name
Test status
Simulation time 8365134886 ps
CPU time 7.01 seconds
Started Mar 28 01:34:51 PM PDT 24
Finished Mar 28 01:34:58 PM PDT 24
Peak memory 204044 kb
Host smart-5eb8f777-4f8e-40f9-84ed-2aca160b9083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42322
26471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.phy_config_usb_ref_disable.4232226471
Directory /workspace/29.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.4092705236
Short name T396
Test name
Test status
Simulation time 8371431618 ps
CPU time 7.31 seconds
Started Mar 28 01:34:53 PM PDT 24
Finished Mar 28 01:35:01 PM PDT 24
Peak memory 204092 kb
Host smart-1cad5da1-df4d-40ab-9a4f-e8229ab61d3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40927
05236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.4092705236
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_enable.1520425721
Short name T528
Test name
Test status
Simulation time 8365707646 ps
CPU time 7.33 seconds
Started Mar 28 01:34:43 PM PDT 24
Finished Mar 28 01:34:51 PM PDT 24
Peak memory 204072 kb
Host smart-ab7b18b0-e54e-4d7d-bf1f-79dedfd285ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15204
25721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.1520425721
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.1700070140
Short name T444
Test name
Test status
Simulation time 143849148 ps
CPU time 1.66 seconds
Started Mar 28 01:34:48 PM PDT 24
Finished Mar 28 01:34:51 PM PDT 24
Peak memory 204268 kb
Host smart-90e691e4-528a-433a-a632-22d1468e42b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17000
70140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1700070140
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.3911627788
Short name T932
Test name
Test status
Simulation time 8359998438 ps
CPU time 9.44 seconds
Started Mar 28 01:34:48 PM PDT 24
Finished Mar 28 01:34:58 PM PDT 24
Peak memory 204056 kb
Host smart-4d335215-8cf4-4f4b-ab37-ea2e1872951f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39116
27788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.3911627788
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.4014360187
Short name T807
Test name
Test status
Simulation time 8423560174 ps
CPU time 6.92 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:52 PM PDT 24
Peak memory 204032 kb
Host smart-f02f8a77-875c-43f8-8d58-356b872da64f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40143
60187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.4014360187
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.3226499592
Short name T399
Test name
Test status
Simulation time 8412737479 ps
CPU time 7.45 seconds
Started Mar 28 01:34:53 PM PDT 24
Finished Mar 28 01:35:01 PM PDT 24
Peak memory 204000 kb
Host smart-9064b58b-1823-49d1-9cc2-c83572b2b959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32264
99592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.3226499592
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.3079037558
Short name T670
Test name
Test status
Simulation time 8370462719 ps
CPU time 7.73 seconds
Started Mar 28 01:34:49 PM PDT 24
Finished Mar 28 01:34:57 PM PDT 24
Peak memory 203940 kb
Host smart-f0cc090a-9863-4103-a622-5edf348695fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30790
37558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3079037558
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.2685673545
Short name T113
Test name
Test status
Simulation time 8388505553 ps
CPU time 9.26 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:54 PM PDT 24
Peak memory 204116 kb
Host smart-ca17a331-51ff-47e4-bd60-9439fa0900e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26856
73545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.2685673545
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.1591779118
Short name T687
Test name
Test status
Simulation time 8396236632 ps
CPU time 7.81 seconds
Started Mar 28 01:34:46 PM PDT 24
Finished Mar 28 01:34:54 PM PDT 24
Peak memory 204084 kb
Host smart-4a27a289-dd63-4e89-973d-66e84c42b8bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15917
79118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.1591779118
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.3338559634
Short name T446
Test name
Test status
Simulation time 8376062998 ps
CPU time 7.72 seconds
Started Mar 28 01:34:47 PM PDT 24
Finished Mar 28 01:34:55 PM PDT 24
Peak memory 204072 kb
Host smart-77175ec1-5ad0-4837-9d47-79fa52821d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33385
59634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3338559634
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2805472055
Short name T548
Test name
Test status
Simulation time 25973798 ps
CPU time 0.64 seconds
Started Mar 28 01:34:46 PM PDT 24
Finished Mar 28 01:34:47 PM PDT 24
Peak memory 203988 kb
Host smart-56049193-9af2-441a-9386-1766fc9fd144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28054
72055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2805472055
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.2970321260
Short name T852
Test name
Test status
Simulation time 32199557930 ps
CPU time 61.72 seconds
Started Mar 28 01:34:47 PM PDT 24
Finished Mar 28 01:35:49 PM PDT 24
Peak memory 204332 kb
Host smart-be890fe9-da47-4528-b91d-d47dd5f4bfbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29703
21260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.2970321260
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.3759244937
Short name T90
Test name
Test status
Simulation time 8370709006 ps
CPU time 9.72 seconds
Started Mar 28 01:34:46 PM PDT 24
Finished Mar 28 01:34:56 PM PDT 24
Peak memory 204072 kb
Host smart-71b41c16-d634-4607-a385-9d463df05396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37592
44937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.3759244937
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.2677549255
Short name T673
Test name
Test status
Simulation time 8430665891 ps
CPU time 7.15 seconds
Started Mar 28 01:34:47 PM PDT 24
Finished Mar 28 01:34:54 PM PDT 24
Peak memory 204084 kb
Host smart-e289a6fc-6675-4c3d-8489-2fe6a50e1f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26775
49255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.2677549255
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.3868901694
Short name T777
Test name
Test status
Simulation time 8406550697 ps
CPU time 8.46 seconds
Started Mar 28 01:34:48 PM PDT 24
Finished Mar 28 01:34:57 PM PDT 24
Peak memory 204112 kb
Host smart-39a3a915-b530-47ad-aafa-8cf380f099be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38689
01694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.3868901694
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2643575679
Short name T436
Test name
Test status
Simulation time 8364502540 ps
CPU time 7.56 seconds
Started Mar 28 01:34:48 PM PDT 24
Finished Mar 28 01:34:57 PM PDT 24
Peak memory 204124 kb
Host smart-4ebc996d-5046-4ae5-957d-bb111dd65525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26435
75679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2643575679
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.3523379466
Short name T1052
Test name
Test status
Simulation time 8379027789 ps
CPU time 8.98 seconds
Started Mar 28 01:34:49 PM PDT 24
Finished Mar 28 01:34:58 PM PDT 24
Peak memory 204120 kb
Host smart-8536936e-1327-4b6a-ba3b-091c0abcdc6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35233
79466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.3523379466
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.in_iso.2994627625
Short name T654
Test name
Test status
Simulation time 8389078753 ps
CPU time 7.48 seconds
Started Mar 28 01:33:00 PM PDT 24
Finished Mar 28 01:33:09 PM PDT 24
Peak memory 204044 kb
Host smart-7167c7fb-61c3-4182-bf47-99ec84b9c45b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29946
27625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.in_iso.2994627625
Directory /workspace/3.in_iso/latest

Test location /workspace/coverage/default/3.phy_config_usb_ref_disable.1037865260
Short name T796
Test name
Test status
Simulation time 8360191394 ps
CPU time 8.62 seconds
Started Mar 28 01:33:01 PM PDT 24
Finished Mar 28 01:33:10 PM PDT 24
Peak memory 204044 kb
Host smart-45564c66-6218-4286-a5c9-c864f8452d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10378
65260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.phy_config_usb_ref_disable.1037865260
Directory /workspace/3.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.17981983
Short name T472
Test name
Test status
Simulation time 8371610108 ps
CPU time 7.42 seconds
Started Mar 28 01:32:39 PM PDT 24
Finished Mar 28 01:32:47 PM PDT 24
Peak memory 203436 kb
Host smart-25ce4229-6b8e-46a5-9f6f-743b83c52ae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17981
983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.17981983
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_enable.2864883487
Short name T368
Test name
Test status
Simulation time 8370214569 ps
CPU time 8.34 seconds
Started Mar 28 01:32:37 PM PDT 24
Finished Mar 28 01:32:46 PM PDT 24
Peak memory 204052 kb
Host smart-692425a9-563f-468a-ae9e-c8416ee4cfb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28648
83487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.2864883487
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.2823556306
Short name T803
Test name
Test status
Simulation time 269079151 ps
CPU time 2.19 seconds
Started Mar 28 01:32:38 PM PDT 24
Finished Mar 28 01:32:40 PM PDT 24
Peak memory 204224 kb
Host smart-b5b99e2d-c1cd-4602-b2f5-8550b91fe539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28235
56306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.2823556306
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.251848503
Short name T889
Test name
Test status
Simulation time 8362191870 ps
CPU time 8.48 seconds
Started Mar 28 01:32:59 PM PDT 24
Finished Mar 28 01:33:08 PM PDT 24
Peak memory 204052 kb
Host smart-90b8ae08-af57-4b19-a8d2-bec43d3b4530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25184
8503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.251848503
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.675515552
Short name T335
Test name
Test status
Simulation time 8375893026 ps
CPU time 7.1 seconds
Started Mar 28 01:32:39 PM PDT 24
Finished Mar 28 01:32:46 PM PDT 24
Peak memory 203392 kb
Host smart-ac87ba3e-9236-407f-81a3-9e5d59397256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67551
5552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.675515552
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.3940516286
Short name T701
Test name
Test status
Simulation time 8407521831 ps
CPU time 6.86 seconds
Started Mar 28 01:32:58 PM PDT 24
Finished Mar 28 01:33:05 PM PDT 24
Peak memory 204064 kb
Host smart-d1b3c9c7-9c0f-4421-ad48-30f7ee010ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39405
16286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.3940516286
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.1403766
Short name T774
Test name
Test status
Simulation time 8367983069 ps
CPU time 7.16 seconds
Started Mar 28 01:32:59 PM PDT 24
Finished Mar 28 01:33:06 PM PDT 24
Peak memory 204084 kb
Host smart-e4f1f563-f7c3-45c2-8a2f-56f119d8ad65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14037
66 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.1403766
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.2422738428
Short name T344
Test name
Test status
Simulation time 8394057130 ps
CPU time 7.74 seconds
Started Mar 28 01:33:00 PM PDT 24
Finished Mar 28 01:33:09 PM PDT 24
Peak memory 204044 kb
Host smart-183853b0-080b-4a8e-acca-380191e5bdbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24227
38428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.2422738428
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.2279018961
Short name T541
Test name
Test status
Simulation time 8401429150 ps
CPU time 7.47 seconds
Started Mar 28 01:33:04 PM PDT 24
Finished Mar 28 01:33:12 PM PDT 24
Peak memory 204048 kb
Host smart-6888011c-9696-442b-acbd-a584762b8181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22790
18961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.2279018961
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2910823645
Short name T48
Test name
Test status
Simulation time 24020864 ps
CPU time 0.64 seconds
Started Mar 28 01:32:56 PM PDT 24
Finished Mar 28 01:32:57 PM PDT 24
Peak memory 204012 kb
Host smart-a3ab44dd-ad55-4d25-92b9-4ed14786b0ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29108
23645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2910823645
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1843268444
Short name T861
Test name
Test status
Simulation time 8394823759 ps
CPU time 7.32 seconds
Started Mar 28 01:32:58 PM PDT 24
Finished Mar 28 01:33:06 PM PDT 24
Peak memory 204028 kb
Host smart-3891a03c-4842-4043-a6a0-40439646e604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18432
68444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1843268444
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2417144637
Short name T390
Test name
Test status
Simulation time 8453242680 ps
CPU time 8.63 seconds
Started Mar 28 01:32:59 PM PDT 24
Finished Mar 28 01:33:08 PM PDT 24
Peak memory 204068 kb
Host smart-63e0984c-3559-4aab-9bdd-bfd3c70415ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24171
44637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2417144637
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.741092306
Short name T1031
Test name
Test status
Simulation time 8372901054 ps
CPU time 8.71 seconds
Started Mar 28 01:32:59 PM PDT 24
Finished Mar 28 01:33:10 PM PDT 24
Peak memory 204044 kb
Host smart-6a8033d6-5b83-4e1c-ac66-0342b510d5f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74109
2306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.741092306
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.838402546
Short name T80
Test name
Test status
Simulation time 163705900 ps
CPU time 1.07 seconds
Started Mar 28 01:33:01 PM PDT 24
Finished Mar 28 01:33:03 PM PDT 24
Peak memory 220928 kb
Host smart-830fce70-9d84-4d0e-ab6d-35dab5bf0ad6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=838402546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.838402546
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.3350302176
Short name T513
Test name
Test status
Simulation time 8361936422 ps
CPU time 9.87 seconds
Started Mar 28 01:32:59 PM PDT 24
Finished Mar 28 01:33:09 PM PDT 24
Peak memory 204068 kb
Host smart-438bc7fa-196f-49dd-afd4-a67edd4cd60a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33503
02176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.3350302176
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.1578037180
Short name T729
Test name
Test status
Simulation time 8389908905 ps
CPU time 7.25 seconds
Started Mar 28 01:32:59 PM PDT 24
Finished Mar 28 01:33:06 PM PDT 24
Peak memory 204112 kb
Host smart-54636140-024c-48de-ab8a-d6478f7d6155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15780
37180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.1578037180
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.in_iso.3626122766
Short name T56
Test name
Test status
Simulation time 8437620381 ps
CPU time 8.01 seconds
Started Mar 28 01:34:44 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204032 kb
Host smart-7d7a04a9-a8ca-4c70-a777-c120303faafb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36261
22766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.in_iso.3626122766
Directory /workspace/30.in_iso/latest

Test location /workspace/coverage/default/30.phy_config_usb_ref_disable.680561363
Short name T458
Test name
Test status
Simulation time 8364002148 ps
CPU time 8.29 seconds
Started Mar 28 01:34:56 PM PDT 24
Finished Mar 28 01:35:04 PM PDT 24
Peak memory 204088 kb
Host smart-2cc788ba-13f9-4df1-91c5-68e383fef96a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68056
1363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.phy_config_usb_ref_disable.680561363
Directory /workspace/30.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.2986127337
Short name T271
Test name
Test status
Simulation time 8374167121 ps
CPU time 7.3 seconds
Started Mar 28 01:34:50 PM PDT 24
Finished Mar 28 01:34:58 PM PDT 24
Peak memory 204060 kb
Host smart-9f0c998f-b1bb-49bf-9483-28d0dda47e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29861
27337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.2986127337
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_enable.1815603044
Short name T995
Test name
Test status
Simulation time 8371079491 ps
CPU time 7.61 seconds
Started Mar 28 01:34:48 PM PDT 24
Finished Mar 28 01:34:57 PM PDT 24
Peak memory 204028 kb
Host smart-3cf05954-75f4-473d-9e38-e01bb864646f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18156
03044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.1815603044
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.943946174
Short name T568
Test name
Test status
Simulation time 69347783 ps
CPU time 1.89 seconds
Started Mar 28 01:34:48 PM PDT 24
Finished Mar 28 01:34:51 PM PDT 24
Peak memory 204168 kb
Host smart-0cdc8d7e-d835-493e-a7e6-de6a8690abe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94394
6174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.943946174
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.2795329485
Short name T515
Test name
Test status
Simulation time 8360823493 ps
CPU time 7 seconds
Started Mar 28 01:34:42 PM PDT 24
Finished Mar 28 01:34:50 PM PDT 24
Peak memory 204028 kb
Host smart-19124efc-de2e-4ac7-abbc-0bdd3be68853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27953
29485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.2795329485
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1124032455
Short name T549
Test name
Test status
Simulation time 8395658920 ps
CPU time 7.7 seconds
Started Mar 28 01:34:47 PM PDT 24
Finished Mar 28 01:34:55 PM PDT 24
Peak memory 204044 kb
Host smart-ad3c5403-9338-4b44-9cd9-e3c975aa978b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11240
32455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1124032455
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.2452830829
Short name T875
Test name
Test status
Simulation time 8416026290 ps
CPU time 9.46 seconds
Started Mar 28 01:34:43 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204028 kb
Host smart-3d92a9e0-18b7-4a6b-a8a9-e80ae40f3350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24528
30829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.2452830829
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1230724
Short name T695
Test name
Test status
Simulation time 8361860267 ps
CPU time 7.39 seconds
Started Mar 28 01:34:38 PM PDT 24
Finished Mar 28 01:34:50 PM PDT 24
Peak memory 204104 kb
Host smart-259c7a35-658a-49d5-a104-29cd50f125a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12307
24 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1230724
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.1433949510
Short name T140
Test name
Test status
Simulation time 8413975657 ps
CPU time 7.09 seconds
Started Mar 28 01:34:36 PM PDT 24
Finished Mar 28 01:34:43 PM PDT 24
Peak memory 204084 kb
Host smart-e2fa66b1-eb37-42b3-9631-bff2070c044e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14339
49510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.1433949510
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.405880209
Short name T493
Test name
Test status
Simulation time 8378123915 ps
CPU time 7.35 seconds
Started Mar 28 01:34:35 PM PDT 24
Finished Mar 28 01:34:43 PM PDT 24
Peak memory 204056 kb
Host smart-a798db5b-164d-4875-9d3e-40e391a4d355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40588
0209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.405880209
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.3218172658
Short name T1
Test name
Test status
Simulation time 8373280200 ps
CPU time 7.18 seconds
Started Mar 28 01:34:43 PM PDT 24
Finished Mar 28 01:34:51 PM PDT 24
Peak memory 204052 kb
Host smart-7dc74285-93cc-443d-8bb9-08e6eb3d1124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32181
72658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.3218172658
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1041853906
Short name T46
Test name
Test status
Simulation time 33290938 ps
CPU time 0.62 seconds
Started Mar 28 01:34:38 PM PDT 24
Finished Mar 28 01:34:43 PM PDT 24
Peak memory 204012 kb
Host smart-e5039036-24e2-4720-a9f7-9376f54f9b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10418
53906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1041853906
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.610052158
Short name T111
Test name
Test status
Simulation time 19945229450 ps
CPU time 32.4 seconds
Started Mar 28 01:34:38 PM PDT 24
Finished Mar 28 01:35:15 PM PDT 24
Peak memory 204212 kb
Host smart-98dfd003-968b-4169-a873-6235e58704bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61005
2158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.610052158
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.3623700771
Short name T851
Test name
Test status
Simulation time 8365738426 ps
CPU time 9.53 seconds
Started Mar 28 01:34:44 PM PDT 24
Finished Mar 28 01:34:54 PM PDT 24
Peak memory 204116 kb
Host smart-45733db3-e142-43cd-a13a-82b24dfef44b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36237
00771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.3623700771
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.4176914644
Short name T383
Test name
Test status
Simulation time 8396923583 ps
CPU time 6.99 seconds
Started Mar 28 01:34:44 PM PDT 24
Finished Mar 28 01:34:51 PM PDT 24
Peak memory 203248 kb
Host smart-4b004cad-3637-4d1f-bbc9-9f12e4f21339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41769
14644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.4176914644
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.1662136202
Short name T348
Test name
Test status
Simulation time 8379376935 ps
CPU time 7.07 seconds
Started Mar 28 01:34:36 PM PDT 24
Finished Mar 28 01:34:43 PM PDT 24
Peak memory 204076 kb
Host smart-b66034b9-4c89-421d-8590-252a20822448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16621
36202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.1662136202
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.3609036232
Short name T340
Test name
Test status
Simulation time 8364604057 ps
CPU time 7.24 seconds
Started Mar 28 01:34:41 PM PDT 24
Finished Mar 28 01:34:50 PM PDT 24
Peak memory 204060 kb
Host smart-8784ebbc-2870-4434-88af-efd6f8a732f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36090
36232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.3609036232
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.3065658429
Short name T18
Test name
Test status
Simulation time 8381008911 ps
CPU time 7.41 seconds
Started Mar 28 01:34:44 PM PDT 24
Finished Mar 28 01:34:52 PM PDT 24
Peak memory 204044 kb
Host smart-71e7ff1b-b56d-4db2-b2e3-368d0e4a2f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30656
58429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.3065658429
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.in_iso.1554664192
Short name T467
Test name
Test status
Simulation time 8438349707 ps
CPU time 7.56 seconds
Started Mar 28 01:34:49 PM PDT 24
Finished Mar 28 01:34:57 PM PDT 24
Peak memory 204120 kb
Host smart-357f26c1-3c6e-492c-ad2e-2ee7bcaa4c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15546
64192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.in_iso.1554664192
Directory /workspace/31.in_iso/latest

Test location /workspace/coverage/default/31.phy_config_usb_ref_disable.352757944
Short name T979
Test name
Test status
Simulation time 8365568374 ps
CPU time 7.45 seconds
Started Mar 28 01:34:52 PM PDT 24
Finished Mar 28 01:35:00 PM PDT 24
Peak memory 203376 kb
Host smart-08e751c4-e80c-4d49-b646-08c2437bba63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35275
7944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.phy_config_usb_ref_disable.352757944
Directory /workspace/31.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1810641316
Short name T293
Test name
Test status
Simulation time 8368571399 ps
CPU time 7.68 seconds
Started Mar 28 01:34:41 PM PDT 24
Finished Mar 28 01:34:50 PM PDT 24
Peak memory 204000 kb
Host smart-46497322-58de-4c28-9355-99eb1cbd40cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18106
41316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1810641316
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_enable.2149509816
Short name T648
Test name
Test status
Simulation time 8367668767 ps
CPU time 7.96 seconds
Started Mar 28 01:34:42 PM PDT 24
Finished Mar 28 01:34:51 PM PDT 24
Peak memory 204064 kb
Host smart-c1b86a41-4687-4116-9b7c-ec73753b231f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21495
09816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.2149509816
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.4024278952
Short name T1066
Test name
Test status
Simulation time 77926125 ps
CPU time 2.1 seconds
Started Mar 28 01:34:46 PM PDT 24
Finished Mar 28 01:34:48 PM PDT 24
Peak memory 204240 kb
Host smart-1a56bab9-f1d5-4096-aa8b-ea1c47beec2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40242
78952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.4024278952
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.1044647393
Short name T613
Test name
Test status
Simulation time 8361844804 ps
CPU time 7.92 seconds
Started Mar 28 01:34:49 PM PDT 24
Finished Mar 28 01:34:57 PM PDT 24
Peak memory 203948 kb
Host smart-255dc0ce-7290-4080-bc67-f9d46a61c993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10446
47393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.1044647393
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.3439012093
Short name T489
Test name
Test status
Simulation time 8382826981 ps
CPU time 7.93 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204048 kb
Host smart-c5c6521e-333a-4522-aab2-f0187c024aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34390
12093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.3439012093
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.3607329865
Short name T600
Test name
Test status
Simulation time 8411184065 ps
CPU time 8.47 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:54 PM PDT 24
Peak memory 204052 kb
Host smart-f63acba4-cd35-4ed9-8ba1-82f6a5e7a3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36073
29865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.3607329865
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.4240447631
Short name T329
Test name
Test status
Simulation time 8363178202 ps
CPU time 9.19 seconds
Started Mar 28 01:34:44 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204080 kb
Host smart-c984ca9d-3398-471c-a065-43423c87d5bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42404
47631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.4240447631
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.3425081873
Short name T674
Test name
Test status
Simulation time 8403638781 ps
CPU time 6.96 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:52 PM PDT 24
Peak memory 203996 kb
Host smart-0719ac7b-6b0d-4327-a383-3ce7595eead7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34250
81873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.3425081873
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.3841933591
Short name T727
Test name
Test status
Simulation time 8401054206 ps
CPU time 7.12 seconds
Started Mar 28 01:34:47 PM PDT 24
Finished Mar 28 01:34:54 PM PDT 24
Peak memory 204092 kb
Host smart-1715cf79-6037-4624-b4cf-09f816cf3354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38419
33591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.3841933591
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.1828192111
Short name T594
Test name
Test status
Simulation time 8395976952 ps
CPU time 7.61 seconds
Started Mar 28 01:34:46 PM PDT 24
Finished Mar 28 01:34:54 PM PDT 24
Peak memory 204100 kb
Host smart-409ac7bb-d121-4a6c-852f-04a360a22087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18281
92111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1828192111
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.2136283404
Short name T330
Test name
Test status
Simulation time 25892865 ps
CPU time 0.64 seconds
Started Mar 28 01:34:48 PM PDT 24
Finished Mar 28 01:34:50 PM PDT 24
Peak memory 203896 kb
Host smart-ddf13fda-b8c5-4f51-87b2-4038d0eaa8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21362
83404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.2136283404
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1277520917
Short name T910
Test name
Test status
Simulation time 14467583622 ps
CPU time 23.5 seconds
Started Mar 28 01:34:53 PM PDT 24
Finished Mar 28 01:35:17 PM PDT 24
Peak memory 204212 kb
Host smart-a2f9af05-d0b0-4978-8f01-dc8438838000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12775
20917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1277520917
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.2558267061
Short name T353
Test name
Test status
Simulation time 8384514498 ps
CPU time 7.56 seconds
Started Mar 28 01:34:53 PM PDT 24
Finished Mar 28 01:35:01 PM PDT 24
Peak memory 204092 kb
Host smart-676d2082-4ee9-4cbb-a065-625609f1eb62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25582
67061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.2558267061
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.1184599127
Short name T866
Test name
Test status
Simulation time 8448351367 ps
CPU time 9.2 seconds
Started Mar 28 01:34:50 PM PDT 24
Finished Mar 28 01:34:59 PM PDT 24
Peak memory 203948 kb
Host smart-5bec628c-a4d8-40f4-8d49-92bfe982b66d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11845
99127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1184599127
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.1772416387
Short name T853
Test name
Test status
Simulation time 8384032433 ps
CPU time 8.26 seconds
Started Mar 28 01:34:49 PM PDT 24
Finished Mar 28 01:34:57 PM PDT 24
Peak memory 203960 kb
Host smart-6a208946-1ec4-4e54-9c0f-ae6453c66c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17724
16387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.1772416387
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.915437513
Short name T565
Test name
Test status
Simulation time 8358028027 ps
CPU time 7.55 seconds
Started Mar 28 01:34:44 PM PDT 24
Finished Mar 28 01:34:52 PM PDT 24
Peak memory 204116 kb
Host smart-27b2ce2a-9650-449e-bc8f-694530f6d02f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91543
7513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.915437513
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.1558470628
Short name T713
Test name
Test status
Simulation time 8376709780 ps
CPU time 7.22 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204120 kb
Host smart-c9c25da8-d738-47c4-aa06-832f4f92dbf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15584
70628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.1558470628
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.in_iso.4063059896
Short name T952
Test name
Test status
Simulation time 8373152444 ps
CPU time 7.64 seconds
Started Mar 28 01:34:40 PM PDT 24
Finished Mar 28 01:34:50 PM PDT 24
Peak memory 204024 kb
Host smart-2a3ded46-50c4-41f2-9909-0fe96e537e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40630
59896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.in_iso.4063059896
Directory /workspace/32.in_iso/latest

Test location /workspace/coverage/default/32.phy_config_usb_ref_disable.643085380
Short name T478
Test name
Test status
Simulation time 8365714181 ps
CPU time 7.34 seconds
Started Mar 28 01:34:43 PM PDT 24
Finished Mar 28 01:34:51 PM PDT 24
Peak memory 204088 kb
Host smart-b4574e81-6130-4fa1-8983-0058ac146fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64308
5380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.phy_config_usb_ref_disable.643085380
Directory /workspace/32.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2569151863
Short name T873
Test name
Test status
Simulation time 8364541852 ps
CPU time 7.48 seconds
Started Mar 28 01:34:47 PM PDT 24
Finished Mar 28 01:34:55 PM PDT 24
Peak memory 204108 kb
Host smart-caaf140f-2d14-4e20-9033-7e95d4dd1111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25691
51863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2569151863
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_enable.1913564569
Short name T365
Test name
Test status
Simulation time 8371313135 ps
CPU time 7.31 seconds
Started Mar 28 01:34:48 PM PDT 24
Finished Mar 28 01:34:56 PM PDT 24
Peak memory 204116 kb
Host smart-6ccd5a27-3132-499a-8e39-bf226a1e72b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19135
64569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.1913564569
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.2729943416
Short name T346
Test name
Test status
Simulation time 43612549 ps
CPU time 1.23 seconds
Started Mar 28 01:34:48 PM PDT 24
Finished Mar 28 01:34:50 PM PDT 24
Peak memory 204284 kb
Host smart-54eb906a-e45c-4d44-985c-45f0e137e1e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27299
43416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.2729943416
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.1279433768
Short name T186
Test name
Test status
Simulation time 8357355947 ps
CPU time 8.18 seconds
Started Mar 28 01:34:38 PM PDT 24
Finished Mar 28 01:34:50 PM PDT 24
Peak memory 204052 kb
Host smart-cd79b9ef-bc74-436c-bbc3-ef46b2166dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12794
33768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1279433768
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.2233776344
Short name T596
Test name
Test status
Simulation time 8441661751 ps
CPU time 7.9 seconds
Started Mar 28 01:34:52 PM PDT 24
Finished Mar 28 01:35:00 PM PDT 24
Peak memory 203488 kb
Host smart-1382faeb-6975-4c7b-9241-7ad5c652eaab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22337
76344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2233776344
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1043249253
Short name T833
Test name
Test status
Simulation time 8410182027 ps
CPU time 7.11 seconds
Started Mar 28 01:34:46 PM PDT 24
Finished Mar 28 01:34:54 PM PDT 24
Peak memory 204028 kb
Host smart-c149be3e-cad3-4cb3-8321-387d3cc27fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10432
49253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1043249253
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.761710319
Short name T966
Test name
Test status
Simulation time 8363811551 ps
CPU time 7.01 seconds
Started Mar 28 01:34:50 PM PDT 24
Finished Mar 28 01:34:58 PM PDT 24
Peak memory 204028 kb
Host smart-b0bddd28-f06f-42e9-8a78-6e4d2684ac3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76171
0319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.761710319
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.165618815
Short name T135
Test name
Test status
Simulation time 8412936786 ps
CPU time 8.44 seconds
Started Mar 28 01:34:51 PM PDT 24
Finished Mar 28 01:34:59 PM PDT 24
Peak memory 204056 kb
Host smart-f075e661-59bf-4bc6-9387-efde69f9adc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16561
8815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.165618815
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1248307666
Short name T327
Test name
Test status
Simulation time 8388082272 ps
CPU time 7.25 seconds
Started Mar 28 01:34:50 PM PDT 24
Finished Mar 28 01:34:58 PM PDT 24
Peak memory 204060 kb
Host smart-45778bac-83c5-4636-a05a-fb35da0619a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12483
07666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1248307666
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.4231378799
Short name T466
Test name
Test status
Simulation time 8395818142 ps
CPU time 6.95 seconds
Started Mar 28 01:34:49 PM PDT 24
Finished Mar 28 01:34:57 PM PDT 24
Peak memory 204056 kb
Host smart-5a658159-ad6d-4d29-ac4d-d4cb4ffa9747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42313
78799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.4231378799
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.1655665011
Short name T752
Test name
Test status
Simulation time 27156015 ps
CPU time 0.63 seconds
Started Mar 28 01:34:46 PM PDT 24
Finished Mar 28 01:34:46 PM PDT 24
Peak memory 203980 kb
Host smart-5d739808-e8d1-46bd-b82e-3a20a8214c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16556
65011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.1655665011
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.3621497662
Short name T920
Test name
Test status
Simulation time 22418044830 ps
CPU time 39.28 seconds
Started Mar 28 01:34:51 PM PDT 24
Finished Mar 28 01:35:31 PM PDT 24
Peak memory 204320 kb
Host smart-53e71fdd-f122-4d83-8dc1-5280df8e9d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36214
97662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.3621497662
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.2931360653
Short name T1006
Test name
Test status
Simulation time 8387516813 ps
CPU time 7 seconds
Started Mar 28 01:34:37 PM PDT 24
Finished Mar 28 01:34:44 PM PDT 24
Peak memory 204056 kb
Host smart-e0189932-1130-4f8f-b918-246bfb5dabc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29313
60653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.2931360653
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3213160244
Short name T409
Test name
Test status
Simulation time 8379078664 ps
CPU time 8.09 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204052 kb
Host smart-78282dff-a177-42cb-8819-bb43f4dd6c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32131
60244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3213160244
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.2023204766
Short name T880
Test name
Test status
Simulation time 8404302892 ps
CPU time 7.72 seconds
Started Mar 28 01:34:43 PM PDT 24
Finished Mar 28 01:34:52 PM PDT 24
Peak memory 204120 kb
Host smart-653e92f7-ffab-413b-a22b-0614c5e1b801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20232
04766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.2023204766
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.4176538624
Short name T469
Test name
Test status
Simulation time 8355317137 ps
CPU time 7.52 seconds
Started Mar 28 01:34:36 PM PDT 24
Finished Mar 28 01:34:43 PM PDT 24
Peak memory 204112 kb
Host smart-3b0f9103-b0a0-4600-8c51-7e6737a125f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41765
38624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.4176538624
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.1121590810
Short name T464
Test name
Test status
Simulation time 8444856414 ps
CPU time 8 seconds
Started Mar 28 01:34:46 PM PDT 24
Finished Mar 28 01:34:55 PM PDT 24
Peak memory 203916 kb
Host smart-3b1a9f3c-a13c-4e5f-9166-772dbfa89fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11215
90810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.1121590810
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.4067665826
Short name T855
Test name
Test status
Simulation time 8363599712 ps
CPU time 7.73 seconds
Started Mar 28 01:34:43 PM PDT 24
Finished Mar 28 01:34:52 PM PDT 24
Peak memory 204092 kb
Host smart-4f5e3c39-1761-4b9b-8f05-7d0291c64019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40676
65826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.4067665826
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.in_iso.1480271838
Short name T771
Test name
Test status
Simulation time 8421167127 ps
CPU time 7.52 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204120 kb
Host smart-85fdfe3e-c935-4c54-93f7-807b2fdd7be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14802
71838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.in_iso.1480271838
Directory /workspace/33.in_iso/latest

Test location /workspace/coverage/default/33.phy_config_usb_ref_disable.3511602664
Short name T26
Test name
Test status
Simulation time 8361860768 ps
CPU time 8.39 seconds
Started Mar 28 01:34:53 PM PDT 24
Finished Mar 28 01:35:02 PM PDT 24
Peak memory 204080 kb
Host smart-60486b49-820f-42f2-b5a0-9998797160a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35116
02664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.phy_config_usb_ref_disable.3511602664
Directory /workspace/33.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.4196318085
Short name T987
Test name
Test status
Simulation time 8376497849 ps
CPU time 9.63 seconds
Started Mar 28 01:34:44 PM PDT 24
Finished Mar 28 01:34:54 PM PDT 24
Peak memory 204128 kb
Host smart-cfd1cb8e-0b15-421d-8996-f7aacfbd0341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41963
18085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.4196318085
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_enable.1573553000
Short name T1028
Test name
Test status
Simulation time 8370675806 ps
CPU time 7.64 seconds
Started Mar 28 01:34:41 PM PDT 24
Finished Mar 28 01:34:50 PM PDT 24
Peak memory 203992 kb
Host smart-7ebd5a4b-b1be-4dd6-8fda-07823b45dc0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15735
53000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1573553000
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1015028180
Short name T615
Test name
Test status
Simulation time 43339724 ps
CPU time 1.35 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:47 PM PDT 24
Peak memory 204156 kb
Host smart-01aded2b-53c9-4c1f-8fc8-f228eba8a9a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10150
28180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1015028180
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.659890555
Short name T205
Test name
Test status
Simulation time 8358205280 ps
CPU time 7.02 seconds
Started Mar 28 01:34:49 PM PDT 24
Finished Mar 28 01:34:56 PM PDT 24
Peak memory 203960 kb
Host smart-346100f1-82fb-4ced-ad68-8bc44d4655c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65989
0555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.659890555
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.1057959866
Short name T427
Test name
Test status
Simulation time 8390112850 ps
CPU time 6.96 seconds
Started Mar 28 01:34:41 PM PDT 24
Finished Mar 28 01:34:49 PM PDT 24
Peak memory 204040 kb
Host smart-8fe7e18f-24db-440f-a18c-76ef2f367b60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10579
59866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.1057959866
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.498824648
Short name T332
Test name
Test status
Simulation time 8408958464 ps
CPU time 7.66 seconds
Started Mar 28 01:34:41 PM PDT 24
Finished Mar 28 01:34:50 PM PDT 24
Peak memory 204124 kb
Host smart-416d0571-3ebb-466e-89b1-dbc6b2beedc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49882
4648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.498824648
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.4175375824
Short name T718
Test name
Test status
Simulation time 8364844331 ps
CPU time 8.37 seconds
Started Mar 28 01:34:44 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204052 kb
Host smart-6a82f33a-e7fd-4b93-80af-3971b77b77ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41753
75824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.4175375824
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.174485161
Short name T129
Test name
Test status
Simulation time 8399488397 ps
CPU time 7.5 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:52 PM PDT 24
Peak memory 204044 kb
Host smart-496a50af-38cb-44be-99b4-23b0b04a5cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17448
5161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.174485161
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.993742195
Short name T630
Test name
Test status
Simulation time 8391415842 ps
CPU time 7.05 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:52 PM PDT 24
Peak memory 204040 kb
Host smart-8ed29069-d24a-4300-b2fa-045400e33214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99374
2195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.993742195
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2686300088
Short name T338
Test name
Test status
Simulation time 8371359555 ps
CPU time 7.28 seconds
Started Mar 28 01:34:46 PM PDT 24
Finished Mar 28 01:34:54 PM PDT 24
Peak memory 204092 kb
Host smart-1aec5adf-c45e-4aa3-b337-9b0ae8fa2995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26863
00088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2686300088
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.2666382858
Short name T992
Test name
Test status
Simulation time 26859716 ps
CPU time 0.62 seconds
Started Mar 28 01:34:43 PM PDT 24
Finished Mar 28 01:34:45 PM PDT 24
Peak memory 204048 kb
Host smart-82607b07-c174-41ea-bdd3-bc28eb7323e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26663
82858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.2666382858
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.3304384773
Short name T203
Test name
Test status
Simulation time 15670317538 ps
CPU time 28.5 seconds
Started Mar 28 01:34:46 PM PDT 24
Finished Mar 28 01:35:14 PM PDT 24
Peak memory 204288 kb
Host smart-da9554f9-b957-4115-a48d-3e3863132167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33043
84773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.3304384773
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.948065784
Short name T619
Test name
Test status
Simulation time 8400541659 ps
CPU time 6.92 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:52 PM PDT 24
Peak memory 204048 kb
Host smart-96f4ac03-639a-4331-aa31-e8d5b8a38b26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94806
5784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.948065784
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.1369139097
Short name T782
Test name
Test status
Simulation time 8420646257 ps
CPU time 8.29 seconds
Started Mar 28 01:34:44 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 203992 kb
Host smart-0edab4af-1a15-4135-bafb-3aa9383aa727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13691
39097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.1369139097
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.1824669872
Short name T770
Test name
Test status
Simulation time 8382208371 ps
CPU time 7.42 seconds
Started Mar 28 01:34:47 PM PDT 24
Finished Mar 28 01:34:54 PM PDT 24
Peak memory 204084 kb
Host smart-12df2a44-2150-4ead-9705-129a0e99051c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18246
69872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.1824669872
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.4278711023
Short name T583
Test name
Test status
Simulation time 8355162827 ps
CPU time 9.73 seconds
Started Mar 28 01:34:46 PM PDT 24
Finished Mar 28 01:34:56 PM PDT 24
Peak memory 204100 kb
Host smart-72284540-a19c-48f5-8b23-384b77072283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42787
11023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.4278711023
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.1855235377
Short name T758
Test name
Test status
Simulation time 8414316492 ps
CPU time 7.62 seconds
Started Mar 28 01:34:40 PM PDT 24
Finished Mar 28 01:34:50 PM PDT 24
Peak memory 204016 kb
Host smart-df9f37d4-c8d3-46dc-81fb-0459b205da94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18552
35377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1855235377
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.4020429043
Short name T99
Test name
Test status
Simulation time 8378034810 ps
CPU time 8.13 seconds
Started Mar 28 01:34:53 PM PDT 24
Finished Mar 28 01:35:01 PM PDT 24
Peak memory 204096 kb
Host smart-3496fd34-667d-4061-af11-b8abc285592d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40204
29043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.4020429043
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.in_iso.4081945205
Short name T975
Test name
Test status
Simulation time 8457400482 ps
CPU time 7.66 seconds
Started Mar 28 01:34:35 PM PDT 24
Finished Mar 28 01:34:43 PM PDT 24
Peak memory 204052 kb
Host smart-b10a64b4-c43f-4096-9df1-c3233f09930a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40819
45205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.in_iso.4081945205
Directory /workspace/34.in_iso/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.3373310747
Short name T322
Test name
Test status
Simulation time 8368028252 ps
CPU time 7.32 seconds
Started Mar 28 01:34:46 PM PDT 24
Finished Mar 28 01:34:54 PM PDT 24
Peak memory 204072 kb
Host smart-7ffb0efb-ed8c-4a07-8f03-8a78dc8e0d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33733
10747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.3373310747
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_enable.409477735
Short name T698
Test name
Test status
Simulation time 8369730306 ps
CPU time 7.55 seconds
Started Mar 28 01:34:47 PM PDT 24
Finished Mar 28 01:34:55 PM PDT 24
Peak memory 204068 kb
Host smart-04028be4-1cf6-498d-942b-f2a4372b993e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40947
7735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.409477735
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.3046844922
Short name T991
Test name
Test status
Simulation time 60355699 ps
CPU time 1.67 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:47 PM PDT 24
Peak memory 204196 kb
Host smart-5f649151-8290-447d-bfdd-e8fd3dea1b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30468
44922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.3046844922
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.3953017825
Short name T209
Test name
Test status
Simulation time 8358091719 ps
CPU time 7.63 seconds
Started Mar 28 01:34:48 PM PDT 24
Finished Mar 28 01:34:57 PM PDT 24
Peak memory 204004 kb
Host smart-a9959dce-071d-4f66-aaf2-5f9652fa78c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39530
17825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3953017825
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2809850316
Short name T144
Test name
Test status
Simulation time 8390325596 ps
CPU time 9.19 seconds
Started Mar 28 01:34:51 PM PDT 24
Finished Mar 28 01:35:00 PM PDT 24
Peak memory 204020 kb
Host smart-6e275057-304f-40c1-ba81-38499cf30766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28098
50316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2809850316
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.1379694967
Short name T835
Test name
Test status
Simulation time 8404737381 ps
CPU time 8.13 seconds
Started Mar 28 01:34:52 PM PDT 24
Finished Mar 28 01:35:01 PM PDT 24
Peak memory 204028 kb
Host smart-377d8f99-3252-42c5-8568-3ac0c3696a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13796
94967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.1379694967
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.2844438069
Short name T372
Test name
Test status
Simulation time 8365588232 ps
CPU time 8.92 seconds
Started Mar 28 01:34:49 PM PDT 24
Finished Mar 28 01:34:58 PM PDT 24
Peak memory 204124 kb
Host smart-a30211f5-4147-4ec1-8b6f-3039783a6c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28444
38069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.2844438069
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.2084278791
Short name T42
Test name
Test status
Simulation time 8419201297 ps
CPU time 9.21 seconds
Started Mar 28 01:34:46 PM PDT 24
Finished Mar 28 01:34:56 PM PDT 24
Peak memory 203940 kb
Host smart-1477943e-3c33-4d1b-8bc7-4831f18eb4d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20842
78791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2084278791
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.3236907353
Short name T533
Test name
Test status
Simulation time 8379826081 ps
CPU time 9.92 seconds
Started Mar 28 01:34:46 PM PDT 24
Finished Mar 28 01:34:56 PM PDT 24
Peak memory 204028 kb
Host smart-2d981335-e793-43db-88fe-93b00cd4d4cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32369
07353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3236907353
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.103211886
Short name T543
Test name
Test status
Simulation time 8399067819 ps
CPU time 7.05 seconds
Started Mar 28 01:34:48 PM PDT 24
Finished Mar 28 01:34:56 PM PDT 24
Peak memory 204084 kb
Host smart-bcc5515f-032e-42df-a494-13b32c32bd58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10321
1886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.103211886
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3568855233
Short name T867
Test name
Test status
Simulation time 29228427 ps
CPU time 0.68 seconds
Started Mar 28 01:34:42 PM PDT 24
Finished Mar 28 01:34:43 PM PDT 24
Peak memory 204016 kb
Host smart-cc59d3d8-b45b-429f-87d3-16b97b909aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35688
55233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3568855233
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.788574546
Short name T665
Test name
Test status
Simulation time 18297433070 ps
CPU time 32.63 seconds
Started Mar 28 01:34:51 PM PDT 24
Finished Mar 28 01:35:23 PM PDT 24
Peak memory 204336 kb
Host smart-c7b3f8d6-7017-4895-994e-26aa5427ff9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78857
4546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.788574546
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.2233626827
Short name T1011
Test name
Test status
Simulation time 8395420849 ps
CPU time 7.33 seconds
Started Mar 28 01:34:50 PM PDT 24
Finished Mar 28 01:34:58 PM PDT 24
Peak memory 204028 kb
Host smart-72cf3565-d368-4498-b6f4-6e83ecbd4645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22336
26827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.2233626827
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.2307242094
Short name T702
Test name
Test status
Simulation time 8442604377 ps
CPU time 7.34 seconds
Started Mar 28 01:34:50 PM PDT 24
Finished Mar 28 01:34:58 PM PDT 24
Peak memory 204056 kb
Host smart-fbe4f211-8806-4866-b8fe-e866bc8f296f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23072
42094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2307242094
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.3977167107
Short name T982
Test name
Test status
Simulation time 8371118557 ps
CPU time 8.43 seconds
Started Mar 28 01:35:04 PM PDT 24
Finished Mar 28 01:35:13 PM PDT 24
Peak memory 204036 kb
Host smart-0d601098-54ba-43ec-a27b-663f0d59630c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39771
67107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.3977167107
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.261792334
Short name T422
Test name
Test status
Simulation time 8356565170 ps
CPU time 7.42 seconds
Started Mar 28 01:34:47 PM PDT 24
Finished Mar 28 01:34:55 PM PDT 24
Peak memory 203172 kb
Host smart-cfccefe0-a11c-4229-b0c9-66747dbf4a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26179
2334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.261792334
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1927736579
Short name T814
Test name
Test status
Simulation time 8435080801 ps
CPU time 9.3 seconds
Started Mar 28 01:34:47 PM PDT 24
Finished Mar 28 01:34:57 PM PDT 24
Peak memory 204064 kb
Host smart-49f07e8c-0bcc-4a5e-8b2c-81ae9bd77d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19277
36579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1927736579
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.4074194165
Short name T421
Test name
Test status
Simulation time 8404227163 ps
CPU time 6.81 seconds
Started Mar 28 01:34:51 PM PDT 24
Finished Mar 28 01:34:58 PM PDT 24
Peak memory 204060 kb
Host smart-910a271e-9a2f-40f2-a8a2-4581e4c8df47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40741
94165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.4074194165
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.in_iso.1923907848
Short name T947
Test name
Test status
Simulation time 8444205945 ps
CPU time 9.14 seconds
Started Mar 28 01:34:44 PM PDT 24
Finished Mar 28 01:34:54 PM PDT 24
Peak memory 204032 kb
Host smart-e42d4f90-758f-49a7-a9b4-6cd9bf066186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19239
07848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.in_iso.1923907848
Directory /workspace/35.in_iso/latest

Test location /workspace/coverage/default/35.phy_config_usb_ref_disable.2729312868
Short name T508
Test name
Test status
Simulation time 8357960589 ps
CPU time 7.7 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204040 kb
Host smart-ff8e477e-7f46-4f4f-997f-22e939b1be37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27293
12868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.phy_config_usb_ref_disable.2729312868
Directory /workspace/35.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.1472519865
Short name T767
Test name
Test status
Simulation time 8369314035 ps
CPU time 7.6 seconds
Started Mar 28 01:34:44 PM PDT 24
Finished Mar 28 01:34:52 PM PDT 24
Peak memory 203352 kb
Host smart-2d9fc785-4e45-420d-8ff0-958f8df4e8d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14725
19865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1472519865
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_enable.448422030
Short name T505
Test name
Test status
Simulation time 8369546297 ps
CPU time 7.46 seconds
Started Mar 28 01:34:37 PM PDT 24
Finished Mar 28 01:34:45 PM PDT 24
Peak memory 204048 kb
Host smart-f27955be-8296-41f5-a628-49dfcbd2ed5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44842
2030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.448422030
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1561813797
Short name T658
Test name
Test status
Simulation time 152973177 ps
CPU time 1.81 seconds
Started Mar 28 01:34:42 PM PDT 24
Finished Mar 28 01:34:44 PM PDT 24
Peak memory 204192 kb
Host smart-833cf6d5-9f16-441a-8c41-21e2b9f4a7aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15618
13797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1561813797
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.2697232027
Short name T225
Test name
Test status
Simulation time 8361624658 ps
CPU time 7.05 seconds
Started Mar 28 01:34:44 PM PDT 24
Finished Mar 28 01:34:52 PM PDT 24
Peak memory 203996 kb
Host smart-d974a998-9710-408a-b598-dc18b04f0ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26972
32027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.2697232027
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.393401452
Short name T997
Test name
Test status
Simulation time 8406182995 ps
CPU time 7.15 seconds
Started Mar 28 01:34:36 PM PDT 24
Finished Mar 28 01:34:44 PM PDT 24
Peak memory 204096 kb
Host smart-cf1e2ac7-9c64-4075-8066-fbc6de4b70ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39340
1452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.393401452
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.1343372426
Short name T850
Test name
Test status
Simulation time 8413410407 ps
CPU time 7.68 seconds
Started Mar 28 01:34:40 PM PDT 24
Finished Mar 28 01:34:50 PM PDT 24
Peak memory 203848 kb
Host smart-136cb47c-5ecf-4aee-a1fc-7376bbf51a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13433
72426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.1343372426
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.221183205
Short name T1000
Test name
Test status
Simulation time 8361540664 ps
CPU time 7.53 seconds
Started Mar 28 01:34:42 PM PDT 24
Finished Mar 28 01:34:50 PM PDT 24
Peak memory 204048 kb
Host smart-bc44c852-e098-447a-bad6-aedcc9c1a629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22118
3205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.221183205
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2974556739
Short name T871
Test name
Test status
Simulation time 8405055106 ps
CPU time 9.32 seconds
Started Mar 28 01:34:48 PM PDT 24
Finished Mar 28 01:34:58 PM PDT 24
Peak memory 203972 kb
Host smart-dd6e954d-eece-409e-9acb-e6044f152a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29745
56739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2974556739
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.1795451262
Short name T823
Test name
Test status
Simulation time 8389686250 ps
CPU time 7.62 seconds
Started Mar 28 01:34:41 PM PDT 24
Finished Mar 28 01:34:50 PM PDT 24
Peak memory 204044 kb
Host smart-7981c8de-badb-41b0-b143-77fc507d1a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17954
51262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.1795451262
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.2073835789
Short name T573
Test name
Test status
Simulation time 8368830945 ps
CPU time 7.09 seconds
Started Mar 28 01:34:46 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204052 kb
Host smart-b8036c12-68c3-412c-bb1d-ac2df5223b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20738
35789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.2073835789
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2023318242
Short name T901
Test name
Test status
Simulation time 26833675 ps
CPU time 0.67 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:46 PM PDT 24
Peak memory 203932 kb
Host smart-0c5d5840-3b34-4230-9b47-efa00fa3d570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20233
18242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2023318242
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.1190257273
Short name T54
Test name
Test status
Simulation time 30862121514 ps
CPU time 70.75 seconds
Started Mar 28 01:34:41 PM PDT 24
Finished Mar 28 01:35:53 PM PDT 24
Peak memory 204292 kb
Host smart-bfbee22b-7302-4661-9bcb-eb2d07a7d082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11902
57273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1190257273
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.2116060463
Short name T359
Test name
Test status
Simulation time 8363237089 ps
CPU time 8.78 seconds
Started Mar 28 01:34:41 PM PDT 24
Finished Mar 28 01:34:51 PM PDT 24
Peak memory 204120 kb
Host smart-0aacf9fd-3c49-4360-b167-375e75bd6e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21160
60463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.2116060463
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.2000523104
Short name T384
Test name
Test status
Simulation time 8406414282 ps
CPU time 6.85 seconds
Started Mar 28 01:34:48 PM PDT 24
Finished Mar 28 01:34:56 PM PDT 24
Peak memory 204016 kb
Host smart-bdfca8b9-7656-4d2e-be14-698ae929e7ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20005
23104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.2000523104
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.462120322
Short name T598
Test name
Test status
Simulation time 8404353308 ps
CPU time 7.03 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:52 PM PDT 24
Peak memory 204048 kb
Host smart-099015e2-7581-4282-a42c-5464b87fdaa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46212
0322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.462120322
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.914573946
Short name T494
Test name
Test status
Simulation time 8361455084 ps
CPU time 7.71 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:53 PM PDT 24
Peak memory 204060 kb
Host smart-1afbee97-c075-4326-9222-15680ef82918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91457
3946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.914573946
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.1850378505
Short name T167
Test name
Test status
Simulation time 8410271713 ps
CPU time 7.88 seconds
Started Mar 28 01:34:37 PM PDT 24
Finished Mar 28 01:34:45 PM PDT 24
Peak memory 204052 kb
Host smart-99c491d1-2cc9-4246-9871-7644dce6673c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18503
78505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.1850378505
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.850342467
Short name T804
Test name
Test status
Simulation time 8404019467 ps
CPU time 8.86 seconds
Started Mar 28 01:34:45 PM PDT 24
Finished Mar 28 01:34:54 PM PDT 24
Peak memory 204048 kb
Host smart-ef93ab8f-0bc2-448b-9d92-4afa8e95e04c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85034
2467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.850342467
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.in_iso.3942900393
Short name T996
Test name
Test status
Simulation time 8403592442 ps
CPU time 7.19 seconds
Started Mar 28 01:35:06 PM PDT 24
Finished Mar 28 01:35:14 PM PDT 24
Peak memory 204084 kb
Host smart-dfe4d3a2-d48f-4237-af56-111a64e7c774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39429
00393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.in_iso.3942900393
Directory /workspace/36.in_iso/latest

Test location /workspace/coverage/default/36.phy_config_usb_ref_disable.478222986
Short name T29
Test name
Test status
Simulation time 8357679039 ps
CPU time 7.52 seconds
Started Mar 28 01:35:01 PM PDT 24
Finished Mar 28 01:35:09 PM PDT 24
Peak memory 204072 kb
Host smart-b0c87b25-264a-4e71-9bb9-d69dc5d79e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47822
2986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.phy_config_usb_ref_disable.478222986
Directory /workspace/36.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.705620323
Short name T564
Test name
Test status
Simulation time 8372591069 ps
CPU time 9.34 seconds
Started Mar 28 01:34:58 PM PDT 24
Finished Mar 28 01:35:08 PM PDT 24
Peak memory 203844 kb
Host smart-78fa8987-4921-4963-9a3f-73a1521a4c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70562
0323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.705620323
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_enable.2091362714
Short name T602
Test name
Test status
Simulation time 8372055879 ps
CPU time 8 seconds
Started Mar 28 01:34:53 PM PDT 24
Finished Mar 28 01:35:01 PM PDT 24
Peak memory 204056 kb
Host smart-d554b137-8fcd-40a2-afc4-502f53a34d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20913
62714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.2091362714
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.693609481
Short name T382
Test name
Test status
Simulation time 193992095 ps
CPU time 2.04 seconds
Started Mar 28 01:35:06 PM PDT 24
Finished Mar 28 01:35:08 PM PDT 24
Peak memory 204108 kb
Host smart-cdd3970d-2a31-4091-9ff9-1a6b689ac5c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69360
9481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.693609481
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.2135642762
Short name T89
Test name
Test status
Simulation time 8360409730 ps
CPU time 7.75 seconds
Started Mar 28 01:35:04 PM PDT 24
Finished Mar 28 01:35:13 PM PDT 24
Peak memory 204064 kb
Host smart-13b9dad0-9f82-41f8-a826-ceb1f1b015ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21356
42762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.2135642762
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2003124253
Short name T983
Test name
Test status
Simulation time 8420858314 ps
CPU time 7.85 seconds
Started Mar 28 01:35:04 PM PDT 24
Finished Mar 28 01:35:12 PM PDT 24
Peak memory 204068 kb
Host smart-fa65f4b6-9dc4-4d23-8735-6cce486257ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20031
24253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2003124253
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.564832420
Short name T236
Test name
Test status
Simulation time 8413379546 ps
CPU time 7.83 seconds
Started Mar 28 01:35:05 PM PDT 24
Finished Mar 28 01:35:13 PM PDT 24
Peak memory 203732 kb
Host smart-2958fb5f-0898-4d56-a33d-d78d1e116c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56483
2420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.564832420
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.4281026412
Short name T679
Test name
Test status
Simulation time 8370234693 ps
CPU time 8.29 seconds
Started Mar 28 01:34:56 PM PDT 24
Finished Mar 28 01:35:04 PM PDT 24
Peak memory 204148 kb
Host smart-bc7baf0c-2603-446d-bf71-9cc9c39ab9d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42810
26412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.4281026412
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.3270253907
Short name T123
Test name
Test status
Simulation time 8382587535 ps
CPU time 7.41 seconds
Started Mar 28 01:34:54 PM PDT 24
Finished Mar 28 01:35:02 PM PDT 24
Peak memory 204056 kb
Host smart-cb436165-fca5-4158-bdd3-f29d8e224c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32702
53907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.3270253907
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3713272167
Short name T394
Test name
Test status
Simulation time 8373421358 ps
CPU time 6.96 seconds
Started Mar 28 01:35:07 PM PDT 24
Finished Mar 28 01:35:15 PM PDT 24
Peak memory 203772 kb
Host smart-ba84f3af-5d6e-4c3d-be7a-c980bd273a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37132
72167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3713272167
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.2686641951
Short name T397
Test name
Test status
Simulation time 8402501450 ps
CPU time 8.77 seconds
Started Mar 28 01:35:04 PM PDT 24
Finished Mar 28 01:35:13 PM PDT 24
Peak memory 204060 kb
Host smart-0cd2d00d-fd24-4107-9966-07c0820691ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26866
41951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.2686641951
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.3793018784
Short name T890
Test name
Test status
Simulation time 24626191 ps
CPU time 0.62 seconds
Started Mar 28 01:34:59 PM PDT 24
Finished Mar 28 01:35:00 PM PDT 24
Peak memory 203980 kb
Host smart-679b5a80-2bb4-41f9-bcc1-7db87490cc99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37930
18784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.3793018784
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3720919783
Short name T196
Test name
Test status
Simulation time 18430586518 ps
CPU time 34.42 seconds
Started Mar 28 01:34:58 PM PDT 24
Finished Mar 28 01:35:33 PM PDT 24
Peak memory 204304 kb
Host smart-9a41488c-bd83-4213-ae0d-5c3f80f83ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37209
19783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3720919783
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.431843528
Short name T681
Test name
Test status
Simulation time 8394514519 ps
CPU time 7.33 seconds
Started Mar 28 01:35:08 PM PDT 24
Finished Mar 28 01:35:15 PM PDT 24
Peak memory 204052 kb
Host smart-34cf9d17-8eee-48ad-aa7b-8053718ebf8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43184
3528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.431843528
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.638996752
Short name T940
Test name
Test status
Simulation time 8405071374 ps
CPU time 9.47 seconds
Started Mar 28 01:35:07 PM PDT 24
Finished Mar 28 01:35:17 PM PDT 24
Peak memory 203800 kb
Host smart-d9e3ace5-eed6-414d-a232-0f8779e5c2c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63899
6752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.638996752
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.2991014019
Short name T842
Test name
Test status
Simulation time 8411833367 ps
CPU time 7.97 seconds
Started Mar 28 01:34:53 PM PDT 24
Finished Mar 28 01:35:01 PM PDT 24
Peak memory 204052 kb
Host smart-899b4c58-face-402e-96ad-fc85edb92589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29910
14019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.2991014019
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.3657341717
Short name T523
Test name
Test status
Simulation time 8356537322 ps
CPU time 7.28 seconds
Started Mar 28 01:35:05 PM PDT 24
Finished Mar 28 01:35:13 PM PDT 24
Peak memory 204072 kb
Host smart-cdaff7bb-5f6d-4680-89b7-e73c91a75dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36573
41717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.3657341717
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.2627451184
Short name T495
Test name
Test status
Simulation time 8438459742 ps
CPU time 8.18 seconds
Started Mar 28 01:35:00 PM PDT 24
Finished Mar 28 01:35:09 PM PDT 24
Peak memory 204044 kb
Host smart-d31c608b-156d-490d-be11-f8de0d7b3d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26274
51184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2627451184
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.4029697260
Short name T795
Test name
Test status
Simulation time 8380622101 ps
CPU time 7.37 seconds
Started Mar 28 01:35:07 PM PDT 24
Finished Mar 28 01:35:15 PM PDT 24
Peak memory 203932 kb
Host smart-e1029a96-8021-4a18-8318-ca51c24449b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40296
97260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.4029697260
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.in_iso.1402450805
Short name T52
Test name
Test status
Simulation time 8460067726 ps
CPU time 8.32 seconds
Started Mar 28 01:34:59 PM PDT 24
Finished Mar 28 01:35:07 PM PDT 24
Peak memory 204080 kb
Host smart-c86b180e-d362-41e0-860c-e680a038df66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14024
50805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.in_iso.1402450805
Directory /workspace/37.in_iso/latest

Test location /workspace/coverage/default/37.phy_config_usb_ref_disable.2593936515
Short name T955
Test name
Test status
Simulation time 8361766638 ps
CPU time 7.95 seconds
Started Mar 28 01:35:05 PM PDT 24
Finished Mar 28 01:35:13 PM PDT 24
Peak memory 204064 kb
Host smart-9a86f4d5-d7db-42b2-8efd-1888ef0a1728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25939
36515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.phy_config_usb_ref_disable.2593936515
Directory /workspace/37.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.1750452596
Short name T510
Test name
Test status
Simulation time 8372623287 ps
CPU time 9.05 seconds
Started Mar 28 01:35:07 PM PDT 24
Finished Mar 28 01:35:17 PM PDT 24
Peak memory 204028 kb
Host smart-26856a99-61f6-4ecf-929c-6cfe62e8ce14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17504
52596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.1750452596
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_enable.904527705
Short name T369
Test name
Test status
Simulation time 8375253795 ps
CPU time 7.09 seconds
Started Mar 28 01:35:08 PM PDT 24
Finished Mar 28 01:35:15 PM PDT 24
Peak memory 204044 kb
Host smart-c6e188f6-9110-483b-b523-2eeeabe131b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90452
7705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.904527705
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.3639586601
Short name T1004
Test name
Test status
Simulation time 8360754416 ps
CPU time 8.02 seconds
Started Mar 28 01:35:07 PM PDT 24
Finished Mar 28 01:35:16 PM PDT 24
Peak memory 204052 kb
Host smart-5c938371-37ce-44c4-a7cb-8f201810c864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36395
86601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.3639586601
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.2864747720
Short name T503
Test name
Test status
Simulation time 8389832909 ps
CPU time 7.16 seconds
Started Mar 28 01:34:56 PM PDT 24
Finished Mar 28 01:35:03 PM PDT 24
Peak memory 204136 kb
Host smart-a0829cf8-a629-4fa9-bb66-229e089a6ef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28647
47720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.2864747720
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1695597320
Short name T574
Test name
Test status
Simulation time 8408107829 ps
CPU time 7.74 seconds
Started Mar 28 01:35:06 PM PDT 24
Finished Mar 28 01:35:14 PM PDT 24
Peak memory 204052 kb
Host smart-8cb80ad1-c1ea-4819-9888-32a2db410112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16955
97320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1695597320
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.590789714
Short name T389
Test name
Test status
Simulation time 8360482487 ps
CPU time 9.57 seconds
Started Mar 28 01:35:05 PM PDT 24
Finished Mar 28 01:35:14 PM PDT 24
Peak memory 203988 kb
Host smart-cea7698b-82d9-4fdd-8951-5af431abf061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59078
9714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.590789714
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.2870218798
Short name T1040
Test name
Test status
Simulation time 8403571462 ps
CPU time 6.89 seconds
Started Mar 28 01:35:05 PM PDT 24
Finished Mar 28 01:35:12 PM PDT 24
Peak memory 203768 kb
Host smart-6e6aa3ea-7ba7-499b-83c1-d8245a4c2935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28702
18798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.2870218798
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.412942219
Short name T1056
Test name
Test status
Simulation time 8382809586 ps
CPU time 7.53 seconds
Started Mar 28 01:35:04 PM PDT 24
Finished Mar 28 01:35:12 PM PDT 24
Peak memory 204096 kb
Host smart-b78b70b6-a279-4e07-8d5d-57779722a6f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41294
2219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.412942219
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.2971480353
Short name T86
Test name
Test status
Simulation time 30628050 ps
CPU time 0.63 seconds
Started Mar 28 01:35:05 PM PDT 24
Finished Mar 28 01:35:07 PM PDT 24
Peak memory 204000 kb
Host smart-978319e8-66eb-4fa3-a61e-b3e079cc8041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29714
80353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.2971480353
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.1986309605
Short name T694
Test name
Test status
Simulation time 16578031159 ps
CPU time 30.78 seconds
Started Mar 28 01:35:06 PM PDT 24
Finished Mar 28 01:35:38 PM PDT 24
Peak memory 204196 kb
Host smart-d7e45b47-bcda-45e4-a029-5ce299275c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19863
09605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.1986309605
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3412132486
Short name T463
Test name
Test status
Simulation time 8389880250 ps
CPU time 6.9 seconds
Started Mar 28 01:35:07 PM PDT 24
Finished Mar 28 01:35:15 PM PDT 24
Peak memory 204052 kb
Host smart-1fccba86-fcf8-44e9-9b2a-69c8e21d1450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34121
32486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3412132486
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.744974321
Short name T475
Test name
Test status
Simulation time 8428049138 ps
CPU time 7.7 seconds
Started Mar 28 01:35:06 PM PDT 24
Finished Mar 28 01:35:14 PM PDT 24
Peak memory 203924 kb
Host smart-18bc0d94-0083-416e-9e02-efcbddd69cac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74497
4321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.744974321
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.323764382
Short name T973
Test name
Test status
Simulation time 8386114037 ps
CPU time 7.51 seconds
Started Mar 28 01:34:57 PM PDT 24
Finished Mar 28 01:35:06 PM PDT 24
Peak memory 203728 kb
Host smart-3a2cab68-6afb-4056-81c4-ba2059489e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32376
4382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.323764382
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.675558290
Short name T590
Test name
Test status
Simulation time 8359455759 ps
CPU time 7.24 seconds
Started Mar 28 01:35:08 PM PDT 24
Finished Mar 28 01:35:15 PM PDT 24
Peak memory 204060 kb
Host smart-1665f7d8-edc3-4763-866a-fec5bface944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67555
8290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.675558290
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.714496106
Short name T181
Test name
Test status
Simulation time 8450951490 ps
CPU time 7.38 seconds
Started Mar 28 01:35:04 PM PDT 24
Finished Mar 28 01:35:12 PM PDT 24
Peak memory 204052 kb
Host smart-0b8a5a0e-4043-4133-8df2-05570c814cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71449
6106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.714496106
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.878017858
Short name T986
Test name
Test status
Simulation time 8367737090 ps
CPU time 9.36 seconds
Started Mar 28 01:35:08 PM PDT 24
Finished Mar 28 01:35:17 PM PDT 24
Peak memory 204048 kb
Host smart-d3b6fa0e-bf01-4374-afb2-980b73e0a124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87801
7858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.878017858
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.in_iso.2124677978
Short name T642
Test name
Test status
Simulation time 8452361719 ps
CPU time 7.7 seconds
Started Mar 28 01:35:11 PM PDT 24
Finished Mar 28 01:35:18 PM PDT 24
Peak memory 204112 kb
Host smart-1c524ec8-bedd-46b2-b6bf-454c4e0934be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21246
77978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.in_iso.2124677978
Directory /workspace/38.in_iso/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.3193434241
Short name T870
Test name
Test status
Simulation time 8371388959 ps
CPU time 7.52 seconds
Started Mar 28 01:35:05 PM PDT 24
Finished Mar 28 01:35:13 PM PDT 24
Peak memory 203900 kb
Host smart-ff48b4b6-6250-432e-a8f7-1ed2ed826f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31934
34241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3193434241
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_enable.2665085133
Short name T303
Test name
Test status
Simulation time 8369970976 ps
CPU time 9.05 seconds
Started Mar 28 01:35:02 PM PDT 24
Finished Mar 28 01:35:11 PM PDT 24
Peak memory 204060 kb
Host smart-a3578196-7b1c-45c7-bb31-0165a870d041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26650
85133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.2665085133
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.571813075
Short name T808
Test name
Test status
Simulation time 184579265 ps
CPU time 1.69 seconds
Started Mar 28 01:35:06 PM PDT 24
Finished Mar 28 01:35:08 PM PDT 24
Peak memory 204104 kb
Host smart-2ed0d7b8-2510-4b7e-8b78-cf1432b9f525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57181
3075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.571813075
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.936385468
Short name T191
Test name
Test status
Simulation time 8363286490 ps
CPU time 8.27 seconds
Started Mar 28 01:35:09 PM PDT 24
Finished Mar 28 01:35:17 PM PDT 24
Peak memory 204112 kb
Host smart-236acb28-6181-44ab-a156-219c509b7835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93638
5468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.936385468
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.3921514011
Short name T606
Test name
Test status
Simulation time 8382585766 ps
CPU time 7.12 seconds
Started Mar 28 01:34:56 PM PDT 24
Finished Mar 28 01:35:03 PM PDT 24
Peak memory 204140 kb
Host smart-6490ec66-ac3b-4340-afc1-5474314ba6d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39215
14011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.3921514011
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.353438908
Short name T584
Test name
Test status
Simulation time 8409903385 ps
CPU time 7.95 seconds
Started Mar 28 01:35:05 PM PDT 24
Finished Mar 28 01:35:13 PM PDT 24
Peak memory 203972 kb
Host smart-a0a6b2d2-6626-4524-9301-c8b6cb8e8bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35343
8908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.353438908
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3412515342
Short name T251
Test name
Test status
Simulation time 8360793389 ps
CPU time 7.86 seconds
Started Mar 28 01:34:58 PM PDT 24
Finished Mar 28 01:35:06 PM PDT 24
Peak memory 203812 kb
Host smart-8e411af9-b23e-4f13-a329-72aecc031552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34125
15342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3412515342
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.1995945537
Short name T841
Test name
Test status
Simulation time 8432210387 ps
CPU time 8.37 seconds
Started Mar 28 01:35:07 PM PDT 24
Finished Mar 28 01:35:16 PM PDT 24
Peak memory 204048 kb
Host smart-149c45bc-f1dc-4966-b34b-cdef9e404779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19959
45537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.1995945537
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.3046112954
Short name T821
Test name
Test status
Simulation time 8392507270 ps
CPU time 7.18 seconds
Started Mar 28 01:35:06 PM PDT 24
Finished Mar 28 01:35:13 PM PDT 24
Peak memory 203896 kb
Host smart-151a21e8-187c-42b4-9352-da7552783dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30461
12954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.3046112954
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.3837862168
Short name T298
Test name
Test status
Simulation time 8365100196 ps
CPU time 6.9 seconds
Started Mar 28 01:35:05 PM PDT 24
Finished Mar 28 01:35:12 PM PDT 24
Peak memory 204052 kb
Host smart-298d5b00-4de5-4d60-97cf-c5f1d8ad7ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38378
62168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.3837862168
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.3007150893
Short name T888
Test name
Test status
Simulation time 31595772 ps
CPU time 0.67 seconds
Started Mar 28 01:35:17 PM PDT 24
Finished Mar 28 01:35:18 PM PDT 24
Peak memory 204028 kb
Host smart-a987c8ac-b4b8-4c71-954f-b84821ce95bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30071
50893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.3007150893
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.2793534724
Short name T12
Test name
Test status
Simulation time 22065315048 ps
CPU time 42.92 seconds
Started Mar 28 01:35:06 PM PDT 24
Finished Mar 28 01:35:49 PM PDT 24
Peak memory 204120 kb
Host smart-a49f743f-98e4-42f5-a90d-b2d4e4b289b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27935
34724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.2793534724
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.3020237233
Short name T85
Test name
Test status
Simulation time 8370575835 ps
CPU time 7.3 seconds
Started Mar 28 01:34:58 PM PDT 24
Finished Mar 28 01:35:06 PM PDT 24
Peak memory 203752 kb
Host smart-c35e4f7a-4ef5-44df-8820-abccf4c9ea2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30202
37233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.3020237233
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.3458170041
Short name T155
Test name
Test status
Simulation time 8378083952 ps
CPU time 8.03 seconds
Started Mar 28 01:34:57 PM PDT 24
Finished Mar 28 01:35:06 PM PDT 24
Peak memory 203840 kb
Host smart-9dc94642-9d6d-4ba2-b7e4-d0ee15eb5dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34581
70041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.3458170041
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.1862748031
Short name T647
Test name
Test status
Simulation time 8398606583 ps
CPU time 9.11 seconds
Started Mar 28 01:35:06 PM PDT 24
Finished Mar 28 01:35:15 PM PDT 24
Peak memory 204056 kb
Host smart-a154c058-5ca4-42ed-ab76-4747576b9eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18627
48031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.1862748031
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.4018512388
Short name T297
Test name
Test status
Simulation time 8358498571 ps
CPU time 8.85 seconds
Started Mar 28 01:35:05 PM PDT 24
Finished Mar 28 01:35:14 PM PDT 24
Peak memory 204080 kb
Host smart-8406fbad-ef56-4ac7-9ffc-9be12982e193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40185
12388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.4018512388
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3397456022
Short name T43
Test name
Test status
Simulation time 8444894136 ps
CPU time 7.21 seconds
Started Mar 28 01:35:07 PM PDT 24
Finished Mar 28 01:35:15 PM PDT 24
Peak memory 204044 kb
Host smart-8a79a510-edbd-4c92-8c29-7e2b9f2b5040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33974
56022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3397456022
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.3255209372
Short name T439
Test name
Test status
Simulation time 8400914840 ps
CPU time 8.45 seconds
Started Mar 28 01:35:06 PM PDT 24
Finished Mar 28 01:35:15 PM PDT 24
Peak memory 204080 kb
Host smart-595566f8-7eb9-438b-96db-44db3b850071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32552
09372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.3255209372
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.in_iso.1473536264
Short name T685
Test name
Test status
Simulation time 8439831480 ps
CPU time 6.88 seconds
Started Mar 28 01:35:06 PM PDT 24
Finished Mar 28 01:35:13 PM PDT 24
Peak memory 204076 kb
Host smart-4608f5d9-2db5-4b4c-8df9-4dc91a944486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14735
36264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.in_iso.1473536264
Directory /workspace/39.in_iso/latest

Test location /workspace/coverage/default/39.phy_config_usb_ref_disable.3017376103
Short name T25
Test name
Test status
Simulation time 8362427772 ps
CPU time 7.75 seconds
Started Mar 28 01:35:11 PM PDT 24
Finished Mar 28 01:35:18 PM PDT 24
Peak memory 204052 kb
Host smart-62aa6083-5935-4dc3-a643-f4efeeac95ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30173
76103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.phy_config_usb_ref_disable.3017376103
Directory /workspace/39.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.3453397527
Short name T860
Test name
Test status
Simulation time 8372207527 ps
CPU time 7.13 seconds
Started Mar 28 01:35:08 PM PDT 24
Finished Mar 28 01:35:15 PM PDT 24
Peak memory 204048 kb
Host smart-026875e8-1913-42e2-a2d0-645fdb89599b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34533
97527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.3453397527
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_enable.1128757242
Short name T856
Test name
Test status
Simulation time 8370612031 ps
CPU time 7.12 seconds
Started Mar 28 01:35:06 PM PDT 24
Finished Mar 28 01:35:15 PM PDT 24
Peak memory 204076 kb
Host smart-537b2650-da80-4e6a-97d0-67271904db75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11287
57242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.1128757242
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.22933424
Short name T741
Test name
Test status
Simulation time 145534255 ps
CPU time 1.82 seconds
Started Mar 28 01:35:09 PM PDT 24
Finished Mar 28 01:35:11 PM PDT 24
Peak memory 204132 kb
Host smart-354ea9e6-e8e5-4f96-aa63-445c5b8fe464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22933
424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.22933424
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.996772465
Short name T1005
Test name
Test status
Simulation time 8359655692 ps
CPU time 7.33 seconds
Started Mar 28 01:35:12 PM PDT 24
Finished Mar 28 01:35:19 PM PDT 24
Peak memory 204112 kb
Host smart-294f1f89-33eb-48dd-a9a2-ed98599f0a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99677
2465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.996772465
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.3197222443
Short name T627
Test name
Test status
Simulation time 8456519472 ps
CPU time 7.55 seconds
Started Mar 28 01:35:09 PM PDT 24
Finished Mar 28 01:35:17 PM PDT 24
Peak memory 204056 kb
Host smart-c9677447-ca7d-41c3-ae71-877800db3a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31972
22443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3197222443
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2526111347
Short name T723
Test name
Test status
Simulation time 8412648997 ps
CPU time 7.81 seconds
Started Mar 28 01:35:19 PM PDT 24
Finished Mar 28 01:35:27 PM PDT 24
Peak memory 204032 kb
Host smart-3d15ccec-2c16-4db6-810e-31bbf8042077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25261
11347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2526111347
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3421738539
Short name T609
Test name
Test status
Simulation time 8367083534 ps
CPU time 7.22 seconds
Started Mar 28 01:35:05 PM PDT 24
Finished Mar 28 01:35:13 PM PDT 24
Peak memory 204060 kb
Host smart-ebaafafb-94da-4c8c-aa7b-dc1ce9c8b860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34217
38539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3421738539
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1659438876
Short name T139
Test name
Test status
Simulation time 8419932097 ps
CPU time 7.83 seconds
Started Mar 28 01:35:09 PM PDT 24
Finished Mar 28 01:35:17 PM PDT 24
Peak memory 204080 kb
Host smart-3f70a7f5-e7e5-4d6b-9c3f-395a197b9e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16594
38876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1659438876
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.3488538179
Short name T633
Test name
Test status
Simulation time 8371931096 ps
CPU time 7.32 seconds
Started Mar 28 01:35:06 PM PDT 24
Finished Mar 28 01:35:13 PM PDT 24
Peak memory 204048 kb
Host smart-fe0e692a-7e89-4835-9495-470ad5e7beaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34885
38179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.3488538179
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.189811252
Short name T349
Test name
Test status
Simulation time 8373202503 ps
CPU time 9.1 seconds
Started Mar 28 01:35:12 PM PDT 24
Finished Mar 28 01:35:22 PM PDT 24
Peak memory 204076 kb
Host smart-01a6bd1b-f191-4e8c-be17-f2f007abe71c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18981
1252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.189811252
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.284096032
Short name T462
Test name
Test status
Simulation time 27105315 ps
CPU time 0.71 seconds
Started Mar 28 01:35:09 PM PDT 24
Finished Mar 28 01:35:10 PM PDT 24
Peak memory 204020 kb
Host smart-665fef25-6040-451d-b1b7-13553096d215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28409
6032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.284096032
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.1826457147
Short name T218
Test name
Test status
Simulation time 16901069593 ps
CPU time 28.84 seconds
Started Mar 28 01:35:09 PM PDT 24
Finished Mar 28 01:35:38 PM PDT 24
Peak memory 204300 kb
Host smart-ef512dee-ec4c-4b5c-b29d-77f9b51103e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18264
57147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.1826457147
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.3647869999
Short name T361
Test name
Test status
Simulation time 8398748131 ps
CPU time 9.1 seconds
Started Mar 28 01:35:13 PM PDT 24
Finished Mar 28 01:35:22 PM PDT 24
Peak memory 204028 kb
Host smart-4fb1063d-36df-47de-82e6-f5a9ec0bc0a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36478
69999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.3647869999
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2852574120
Short name T789
Test name
Test status
Simulation time 8420250604 ps
CPU time 7.68 seconds
Started Mar 28 01:35:08 PM PDT 24
Finished Mar 28 01:35:16 PM PDT 24
Peak memory 204020 kb
Host smart-18aaa2c1-2faf-4c48-b18a-b423df54d8f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28525
74120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2852574120
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.2881358556
Short name T791
Test name
Test status
Simulation time 8390865670 ps
CPU time 9.05 seconds
Started Mar 28 01:35:16 PM PDT 24
Finished Mar 28 01:35:26 PM PDT 24
Peak memory 204064 kb
Host smart-2a3a81a2-beee-4fd8-bbbd-769e56bd9358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28813
58556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.2881358556
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.1794624361
Short name T24
Test name
Test status
Simulation time 8359353589 ps
CPU time 7.92 seconds
Started Mar 28 01:35:09 PM PDT 24
Finished Mar 28 01:35:17 PM PDT 24
Peak memory 204088 kb
Host smart-3249c466-d5a2-4c99-b3b7-a3a283d85b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17946
24361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.1794624361
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.593758605
Short name T95
Test name
Test status
Simulation time 8428281461 ps
CPU time 7.22 seconds
Started Mar 28 01:35:08 PM PDT 24
Finished Mar 28 01:35:15 PM PDT 24
Peak memory 204044 kb
Host smart-5c387349-9446-4f3a-b49b-0dfb3d1754d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59375
8605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.593758605
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.2722878995
Short name T237
Test name
Test status
Simulation time 8361111575 ps
CPU time 6.87 seconds
Started Mar 28 01:35:11 PM PDT 24
Finished Mar 28 01:35:18 PM PDT 24
Peak memory 204116 kb
Host smart-d198ee5a-7cc4-4129-88a7-ce8d80760274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27228
78995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.2722878995
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.in_iso.741571747
Short name T376
Test name
Test status
Simulation time 8374661459 ps
CPU time 7.41 seconds
Started Mar 28 01:32:57 PM PDT 24
Finished Mar 28 01:33:06 PM PDT 24
Peak memory 204032 kb
Host smart-52cdf10a-38a8-4984-8bbe-6badb984d3f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74157
1747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.in_iso.741571747
Directory /workspace/4.in_iso/latest

Test location /workspace/coverage/default/4.phy_config_usb_ref_disable.3329537969
Short name T845
Test name
Test status
Simulation time 8364387004 ps
CPU time 7.77 seconds
Started Mar 28 01:32:58 PM PDT 24
Finished Mar 28 01:33:06 PM PDT 24
Peak memory 204076 kb
Host smart-b8d672db-e270-4b6d-8a27-851346568e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33295
37969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.phy_config_usb_ref_disable.3329537969
Directory /workspace/4.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.393805841
Short name T250
Test name
Test status
Simulation time 8370554223 ps
CPU time 9.68 seconds
Started Mar 28 01:32:59 PM PDT 24
Finished Mar 28 01:33:09 PM PDT 24
Peak memory 204028 kb
Host smart-884b809d-b3d6-4b05-a0e9-36af9a2f192c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39380
5841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.393805841
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_enable.1491486169
Short name T933
Test name
Test status
Simulation time 8375141006 ps
CPU time 7.36 seconds
Started Mar 28 01:32:56 PM PDT 24
Finished Mar 28 01:33:04 PM PDT 24
Peak memory 204040 kb
Host smart-476e7ea3-b6f3-4d03-b6d0-9bc7d184f217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14914
86169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1491486169
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.3473508797
Short name T588
Test name
Test status
Simulation time 54565639 ps
CPU time 1.56 seconds
Started Mar 28 01:33:01 PM PDT 24
Finished Mar 28 01:33:03 PM PDT 24
Peak memory 204216 kb
Host smart-82a16b4f-f1c9-4b89-bb75-b1fec5ad3789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34735
08797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.3473508797
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.1463403406
Short name T197
Test name
Test status
Simulation time 8359665803 ps
CPU time 7.26 seconds
Started Mar 28 01:32:56 PM PDT 24
Finished Mar 28 01:33:04 PM PDT 24
Peak memory 204084 kb
Host smart-c0cf4caa-acc7-4733-8449-d002d4537162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14634
03406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.1463403406
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1757912973
Short name T450
Test name
Test status
Simulation time 8432499843 ps
CPU time 6.99 seconds
Started Mar 28 01:32:59 PM PDT 24
Finished Mar 28 01:33:06 PM PDT 24
Peak memory 204040 kb
Host smart-37333952-4244-4b81-bcc7-728215fd6ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17579
12973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1757912973
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.1145396424
Short name T35
Test name
Test status
Simulation time 8407546266 ps
CPU time 6.93 seconds
Started Mar 28 01:32:58 PM PDT 24
Finished Mar 28 01:33:05 PM PDT 24
Peak memory 204060 kb
Host smart-ae1a348b-e574-4912-b5c2-ae4a425e93b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11453
96424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.1145396424
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.2827782264
Short name T593
Test name
Test status
Simulation time 8366128789 ps
CPU time 7.25 seconds
Started Mar 28 01:32:59 PM PDT 24
Finished Mar 28 01:33:06 PM PDT 24
Peak memory 204092 kb
Host smart-f68cee35-a3d0-4157-b3f0-eeb61aa97c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28277
82264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.2827782264
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.4180551095
Short name T126
Test name
Test status
Simulation time 8399267776 ps
CPU time 9.75 seconds
Started Mar 28 01:32:58 PM PDT 24
Finished Mar 28 01:33:08 PM PDT 24
Peak memory 203744 kb
Host smart-ef1aba4c-18a1-4e74-8e61-c907b0c03715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41805
51095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.4180551095
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2027957660
Short name T872
Test name
Test status
Simulation time 8408130997 ps
CPU time 7.31 seconds
Started Mar 28 01:32:58 PM PDT 24
Finished Mar 28 01:33:06 PM PDT 24
Peak memory 204088 kb
Host smart-196ab9d8-9612-4ea0-abe8-36e8cff85d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20279
57660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2027957660
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.741250159
Short name T1045
Test name
Test status
Simulation time 8383825386 ps
CPU time 10.22 seconds
Started Mar 28 01:32:59 PM PDT 24
Finished Mar 28 01:33:09 PM PDT 24
Peak memory 204056 kb
Host smart-ecd4edb1-ae14-407f-9c8e-3f49dcd209dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74125
0159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.741250159
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3912996556
Short name T578
Test name
Test status
Simulation time 25021247 ps
CPU time 0.63 seconds
Started Mar 28 01:33:01 PM PDT 24
Finished Mar 28 01:33:02 PM PDT 24
Peak memory 203980 kb
Host smart-78ac7f11-2c58-4a95-b12f-221495b68f12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39129
96556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3912996556
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.2552459050
Short name T919
Test name
Test status
Simulation time 22431943275 ps
CPU time 41.1 seconds
Started Mar 28 01:32:58 PM PDT 24
Finished Mar 28 01:33:40 PM PDT 24
Peak memory 204320 kb
Host smart-cb5f9b40-8db0-43d6-a7c6-22bbeb10cec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25524
59050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.2552459050
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.2143841718
Short name T535
Test name
Test status
Simulation time 8395862817 ps
CPU time 7.63 seconds
Started Mar 28 01:32:56 PM PDT 24
Finished Mar 28 01:33:04 PM PDT 24
Peak memory 204008 kb
Host smart-330c40c2-df07-4adf-94e9-f1e9b0bb019f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21438
41718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.2143841718
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.1939378155
Short name T153
Test name
Test status
Simulation time 8445576325 ps
CPU time 8.36 seconds
Started Mar 28 01:32:56 PM PDT 24
Finished Mar 28 01:33:05 PM PDT 24
Peak memory 204084 kb
Host smart-d308144e-55c7-436d-813f-1acb7e2d39be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19393
78155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.1939378155
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.1717940622
Short name T617
Test name
Test status
Simulation time 8384068224 ps
CPU time 7.17 seconds
Started Mar 28 01:32:55 PM PDT 24
Finished Mar 28 01:33:02 PM PDT 24
Peak memory 204008 kb
Host smart-6380fe45-af08-4b1a-9de7-1783305f22d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17179
40622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.1717940622
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.2880567322
Short name T79
Test name
Test status
Simulation time 96205746 ps
CPU time 0.89 seconds
Started Mar 28 01:32:57 PM PDT 24
Finished Mar 28 01:32:59 PM PDT 24
Peak memory 219916 kb
Host smart-20ac9935-6d1b-4730-8968-316ec9a47f89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2880567322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2880567322
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.3417064010
Short name T438
Test name
Test status
Simulation time 8363134182 ps
CPU time 7.15 seconds
Started Mar 28 01:32:56 PM PDT 24
Finished Mar 28 01:33:04 PM PDT 24
Peak memory 204104 kb
Host smart-86824a11-4f78-43b6-853f-d5fcc142ad16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34170
64010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.3417064010
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.2616382267
Short name T502
Test name
Test status
Simulation time 8451074118 ps
CPU time 7.35 seconds
Started Mar 28 01:32:56 PM PDT 24
Finished Mar 28 01:33:04 PM PDT 24
Peak memory 204072 kb
Host smart-a006601d-0dfa-4b4f-a7f5-a8cc51fb2bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26163
82267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.2616382267
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.800893183
Short name T506
Test name
Test status
Simulation time 8397754358 ps
CPU time 7.55 seconds
Started Mar 28 01:32:58 PM PDT 24
Finished Mar 28 01:33:06 PM PDT 24
Peak memory 203996 kb
Host smart-37bc2997-8901-4538-9ff5-47d0c7e29480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80089
3183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.800893183
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.in_iso.205762412
Short name T146
Test name
Test status
Simulation time 8438625473 ps
CPU time 7.14 seconds
Started Mar 28 01:35:28 PM PDT 24
Finished Mar 28 01:35:35 PM PDT 24
Peak memory 204112 kb
Host smart-e10b3190-7873-40e6-9981-fb8217495e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20576
2412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.in_iso.205762412
Directory /workspace/40.in_iso/latest

Test location /workspace/coverage/default/40.phy_config_usb_ref_disable.2392320977
Short name T412
Test name
Test status
Simulation time 8363993943 ps
CPU time 8.36 seconds
Started Mar 28 01:35:30 PM PDT 24
Finished Mar 28 01:35:38 PM PDT 24
Peak memory 204084 kb
Host smart-82c0e41f-d921-47d9-8eb1-0e8caebe7843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23923
20977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.phy_config_usb_ref_disable.2392320977
Directory /workspace/40.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.3450514230
Short name T381
Test name
Test status
Simulation time 8372205039 ps
CPU time 7.32 seconds
Started Mar 28 01:35:32 PM PDT 24
Finished Mar 28 01:35:40 PM PDT 24
Peak memory 203856 kb
Host smart-55ebeb8f-91fe-4e09-a1a5-4b85e2812393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34505
14230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.3450514230
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_enable.2795663223
Short name T971
Test name
Test status
Simulation time 8371804009 ps
CPU time 8.22 seconds
Started Mar 28 01:35:26 PM PDT 24
Finished Mar 28 01:35:34 PM PDT 24
Peak memory 204080 kb
Host smart-cd0915f9-572f-45f3-9208-23a3e81e5cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27956
63223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.2795663223
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.896207553
Short name T929
Test name
Test status
Simulation time 203782320 ps
CPU time 1.88 seconds
Started Mar 28 01:35:27 PM PDT 24
Finished Mar 28 01:35:29 PM PDT 24
Peak memory 204172 kb
Host smart-0f6dc355-f07c-42c0-b551-c8d015f1e558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89620
7553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.896207553
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.3057878953
Short name T210
Test name
Test status
Simulation time 8356992291 ps
CPU time 7.54 seconds
Started Mar 28 01:35:40 PM PDT 24
Finished Mar 28 01:35:47 PM PDT 24
Peak memory 204048 kb
Host smart-ffc113f4-fa31-4582-9ea9-2b679aa14e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30578
78953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.3057878953
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.3162758344
Short name T499
Test name
Test status
Simulation time 8420667989 ps
CPU time 7.69 seconds
Started Mar 28 01:35:28 PM PDT 24
Finished Mar 28 01:35:37 PM PDT 24
Peak memory 204084 kb
Host smart-833e09d2-b5d9-40e3-a387-71486ad87705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31627
58344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.3162758344
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.3668145730
Short name T750
Test name
Test status
Simulation time 8408064524 ps
CPU time 8.44 seconds
Started Mar 28 01:35:24 PM PDT 24
Finished Mar 28 01:35:33 PM PDT 24
Peak memory 204056 kb
Host smart-3782aa93-8cd4-4639-bae1-8ec8eeda3836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36681
45730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.3668145730
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.4000065999
Short name T708
Test name
Test status
Simulation time 8368885045 ps
CPU time 8.03 seconds
Started Mar 28 01:35:28 PM PDT 24
Finished Mar 28 01:35:36 PM PDT 24
Peak memory 204084 kb
Host smart-70c90be4-3f5e-4997-8a32-b2aa50b7af8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40000
65999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.4000065999
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.4220418267
Short name T700
Test name
Test status
Simulation time 8397067522 ps
CPU time 7.63 seconds
Started Mar 28 01:35:30 PM PDT 24
Finished Mar 28 01:35:38 PM PDT 24
Peak memory 204052 kb
Host smart-cb69f7c3-8484-4ff8-9652-3de574e2901d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42204
18267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.4220418267
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.2960684948
Short name T660
Test name
Test status
Simulation time 8400516620 ps
CPU time 7.95 seconds
Started Mar 28 01:35:21 PM PDT 24
Finished Mar 28 01:35:30 PM PDT 24
Peak memory 204052 kb
Host smart-803344e7-40ab-4a5a-977b-95b2627734c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29606
84948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2960684948
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.642433877
Short name T878
Test name
Test status
Simulation time 25993392 ps
CPU time 0.65 seconds
Started Mar 28 01:35:26 PM PDT 24
Finished Mar 28 01:35:27 PM PDT 24
Peak memory 203944 kb
Host smart-000b4a80-216b-4611-ac35-dd803f6054e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64243
3877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.642433877
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.990001642
Short name T1062
Test name
Test status
Simulation time 8386760038 ps
CPU time 7.62 seconds
Started Mar 28 01:35:26 PM PDT 24
Finished Mar 28 01:35:35 PM PDT 24
Peak memory 204016 kb
Host smart-96d59794-9144-4e82-b62a-7f19556c9d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99000
1642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.990001642
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.664329481
Short name T772
Test name
Test status
Simulation time 8402953810 ps
CPU time 8.95 seconds
Started Mar 28 01:35:26 PM PDT 24
Finished Mar 28 01:35:35 PM PDT 24
Peak memory 204048 kb
Host smart-208abfad-0a7f-4930-9286-f2f8809607d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66432
9481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.664329481
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.3428199468
Short name T671
Test name
Test status
Simulation time 8371056915 ps
CPU time 7.88 seconds
Started Mar 28 01:35:25 PM PDT 24
Finished Mar 28 01:35:33 PM PDT 24
Peak memory 204060 kb
Host smart-f32a8976-24e1-4b3b-ae53-87cbe2e11c8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34281
99468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.3428199468
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.2527962830
Short name T838
Test name
Test status
Simulation time 8355656095 ps
CPU time 8.59 seconds
Started Mar 28 01:35:31 PM PDT 24
Finished Mar 28 01:35:40 PM PDT 24
Peak memory 204036 kb
Host smart-b32420e7-deae-4919-ab8d-c9eba97bbd5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25279
62830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.2527962830
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.2512159037
Short name T168
Test name
Test status
Simulation time 8448668078 ps
CPU time 7.61 seconds
Started Mar 28 01:35:11 PM PDT 24
Finished Mar 28 01:35:19 PM PDT 24
Peak memory 204012 kb
Host smart-05ea35c1-8610-4240-b4ec-5fb0e5e7f599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25121
59037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2512159037
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.512660272
Short name T433
Test name
Test status
Simulation time 8405303885 ps
CPU time 7.47 seconds
Started Mar 28 01:35:24 PM PDT 24
Finished Mar 28 01:35:31 PM PDT 24
Peak memory 204108 kb
Host smart-0f2518d0-dac5-4075-b9c5-7d7f32f5dfa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51266
0272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.512660272
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.in_iso.2463422281
Short name T634
Test name
Test status
Simulation time 8386833728 ps
CPU time 9.23 seconds
Started Mar 28 01:35:27 PM PDT 24
Finished Mar 28 01:35:37 PM PDT 24
Peak memory 204112 kb
Host smart-7096236c-dbd2-4db3-aba2-71a8a269953d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24634
22281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.in_iso.2463422281
Directory /workspace/41.in_iso/latest

Test location /workspace/coverage/default/41.phy_config_usb_ref_disable.2347053463
Short name T802
Test name
Test status
Simulation time 8361524680 ps
CPU time 7.02 seconds
Started Mar 28 01:35:26 PM PDT 24
Finished Mar 28 01:35:33 PM PDT 24
Peak memory 204088 kb
Host smart-1e147ff5-2af6-465a-9493-c7e51fa8cce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23470
53463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.phy_config_usb_ref_disable.2347053463
Directory /workspace/41.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2364953004
Short name T885
Test name
Test status
Simulation time 8371420301 ps
CPU time 7.83 seconds
Started Mar 28 01:35:29 PM PDT 24
Finished Mar 28 01:35:37 PM PDT 24
Peak memory 204084 kb
Host smart-21436af3-ccef-4d61-8a15-b6197ed78590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23649
53004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2364953004
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_enable.624028901
Short name T522
Test name
Test status
Simulation time 8369273345 ps
CPU time 8.39 seconds
Started Mar 28 01:35:31 PM PDT 24
Finished Mar 28 01:35:39 PM PDT 24
Peak memory 203988 kb
Host smart-f2887df7-48ab-4c36-9bc5-c6e001147233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62402
8901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.624028901
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.1304316251
Short name T511
Test name
Test status
Simulation time 62770024 ps
CPU time 1.63 seconds
Started Mar 28 01:35:31 PM PDT 24
Finished Mar 28 01:35:33 PM PDT 24
Peak memory 204036 kb
Host smart-a7bb46e4-de30-47a8-927f-c2c9054c604a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13043
16251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.1304316251
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1848174731
Short name T857
Test name
Test status
Simulation time 8364609302 ps
CPU time 8 seconds
Started Mar 28 01:35:32 PM PDT 24
Finished Mar 28 01:35:40 PM PDT 24
Peak memory 203840 kb
Host smart-0b445bc2-c060-4cae-b3f7-aa9db3d03dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18481
74731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1848174731
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3552646757
Short name T974
Test name
Test status
Simulation time 8458214726 ps
CPU time 7.88 seconds
Started Mar 28 01:35:31 PM PDT 24
Finished Mar 28 01:35:39 PM PDT 24
Peak memory 204024 kb
Host smart-6d44ddca-8143-48ed-8f04-587861acc7c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35526
46757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3552646757
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.2670244749
Short name T968
Test name
Test status
Simulation time 8409566421 ps
CPU time 10.1 seconds
Started Mar 28 01:35:28 PM PDT 24
Finished Mar 28 01:35:38 PM PDT 24
Peak memory 204048 kb
Host smart-445a0779-4c44-4f53-ae08-b43931cf0e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26702
44749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.2670244749
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.3869615333
Short name T895
Test name
Test status
Simulation time 8366365593 ps
CPU time 8.8 seconds
Started Mar 28 01:35:24 PM PDT 24
Finished Mar 28 01:35:33 PM PDT 24
Peak memory 204052 kb
Host smart-36b78bcd-fc68-4fdb-be50-70e0d3b685f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38696
15333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.3869615333
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.1446671577
Short name T636
Test name
Test status
Simulation time 8409778138 ps
CPU time 8.04 seconds
Started Mar 28 01:35:28 PM PDT 24
Finished Mar 28 01:35:37 PM PDT 24
Peak memory 204116 kb
Host smart-0d7e6846-f7c2-4488-863e-6da5f51d4858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14466
71577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.1446671577
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2755919587
Short name T928
Test name
Test status
Simulation time 8391828690 ps
CPU time 10.08 seconds
Started Mar 28 01:35:29 PM PDT 24
Finished Mar 28 01:35:39 PM PDT 24
Peak memory 204024 kb
Host smart-58449193-378c-4494-8b98-6b46166dbc2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27559
19587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2755919587
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.2435417622
Short name T208
Test name
Test status
Simulation time 17931034619 ps
CPU time 29.9 seconds
Started Mar 28 01:35:29 PM PDT 24
Finished Mar 28 01:35:59 PM PDT 24
Peak memory 204280 kb
Host smart-2cc839c8-037e-44be-8304-eeb5bed5a45a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24354
17622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.2435417622
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.2672163552
Short name T944
Test name
Test status
Simulation time 8369372064 ps
CPU time 9.29 seconds
Started Mar 28 01:35:31 PM PDT 24
Finished Mar 28 01:35:40 PM PDT 24
Peak memory 203988 kb
Host smart-7f455cde-cba8-41f5-8831-5e8780e67ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26721
63552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.2672163552
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.635200863
Short name T988
Test name
Test status
Simulation time 8379770204 ps
CPU time 7.93 seconds
Started Mar 28 01:35:29 PM PDT 24
Finished Mar 28 01:35:37 PM PDT 24
Peak memory 204084 kb
Host smart-b70811ef-d6a1-497a-a64c-be4179c9f5d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63520
0863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.635200863
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.1753331881
Short name T486
Test name
Test status
Simulation time 8383380954 ps
CPU time 8.34 seconds
Started Mar 28 01:35:31 PM PDT 24
Finished Mar 28 01:35:39 PM PDT 24
Peak memory 204052 kb
Host smart-d8ba7d02-be97-4c09-a5b8-265ef40bb72e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17533
31881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.1753331881
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3732245935
Short name T820
Test name
Test status
Simulation time 8362511019 ps
CPU time 7.5 seconds
Started Mar 28 01:35:29 PM PDT 24
Finished Mar 28 01:35:37 PM PDT 24
Peak memory 204072 kb
Host smart-9b4b5c33-8157-40bb-ab32-068f703c8a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37322
45935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3732245935
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.3657286356
Short name T182
Test name
Test status
Simulation time 8401819144 ps
CPU time 9.72 seconds
Started Mar 28 01:35:26 PM PDT 24
Finished Mar 28 01:35:36 PM PDT 24
Peak memory 204064 kb
Host smart-421571be-f6e2-4488-8613-48f60cbedbce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36572
86356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3657286356
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.3433727485
Short name T239
Test name
Test status
Simulation time 8398781910 ps
CPU time 7.38 seconds
Started Mar 28 01:35:26 PM PDT 24
Finished Mar 28 01:35:34 PM PDT 24
Peak memory 204032 kb
Host smart-2500c3b7-94b9-4707-8b6c-6176d53f6df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34337
27485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.3433727485
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.in_iso.2138241068
Short name T11
Test name
Test status
Simulation time 8400992870 ps
CPU time 8.63 seconds
Started Mar 28 01:35:30 PM PDT 24
Finished Mar 28 01:35:39 PM PDT 24
Peak memory 204044 kb
Host smart-56f79473-b974-4d9f-a713-fe695c8c379e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21382
41068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.in_iso.2138241068
Directory /workspace/42.in_iso/latest

Test location /workspace/coverage/default/42.phy_config_usb_ref_disable.4102858813
Short name T455
Test name
Test status
Simulation time 8359887662 ps
CPU time 8.29 seconds
Started Mar 28 01:35:30 PM PDT 24
Finished Mar 28 01:35:39 PM PDT 24
Peak memory 204052 kb
Host smart-65214f72-e032-4c23-a59f-252160d9574c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41028
58813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.phy_config_usb_ref_disable.4102858813
Directory /workspace/42.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.3858850789
Short name T649
Test name
Test status
Simulation time 8374256735 ps
CPU time 8.81 seconds
Started Mar 28 01:35:29 PM PDT 24
Finished Mar 28 01:35:38 PM PDT 24
Peak memory 204060 kb
Host smart-fd004a53-3c2d-4e7f-bd7e-b196a08d16f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38588
50789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3858850789
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_enable.1741610831
Short name T445
Test name
Test status
Simulation time 8368192416 ps
CPU time 8.13 seconds
Started Mar 28 01:35:30 PM PDT 24
Finished Mar 28 01:35:38 PM PDT 24
Peak memory 204048 kb
Host smart-5b92af46-6609-48c5-a5d5-a425e18ed861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17416
10831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.1741610831
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3518956056
Short name T234
Test name
Test status
Simulation time 55800939 ps
CPU time 1.54 seconds
Started Mar 28 01:35:32 PM PDT 24
Finished Mar 28 01:35:34 PM PDT 24
Peak memory 204080 kb
Host smart-02cb7e8f-2815-4196-87cd-f20ae8fb4570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35189
56056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3518956056
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.674463086
Short name T226
Test name
Test status
Simulation time 8364765880 ps
CPU time 8.24 seconds
Started Mar 28 01:35:29 PM PDT 24
Finished Mar 28 01:35:37 PM PDT 24
Peak memory 204076 kb
Host smart-c231fd31-88e0-44c8-bf89-241e7c029a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67446
3086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.674463086
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.1198422291
Short name T898
Test name
Test status
Simulation time 8436364810 ps
CPU time 7.67 seconds
Started Mar 28 01:35:26 PM PDT 24
Finished Mar 28 01:35:33 PM PDT 24
Peak memory 204016 kb
Host smart-5d4dc857-ea75-45cc-b2ec-9408f846fb11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11984
22291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1198422291
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.1244111080
Short name T731
Test name
Test status
Simulation time 8408369362 ps
CPU time 8.6 seconds
Started Mar 28 01:35:30 PM PDT 24
Finished Mar 28 01:35:38 PM PDT 24
Peak memory 204056 kb
Host smart-ebea3a6a-992f-4bdc-aa4e-7d5494884e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12441
11080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1244111080
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.1720511856
Short name T461
Test name
Test status
Simulation time 8362414227 ps
CPU time 7.61 seconds
Started Mar 28 01:35:29 PM PDT 24
Finished Mar 28 01:35:37 PM PDT 24
Peak memory 204060 kb
Host smart-0913569c-cbab-4fd9-82e2-ddbebe3645b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17205
11856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.1720511856
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.2413699270
Short name T562
Test name
Test status
Simulation time 8390023184 ps
CPU time 8.49 seconds
Started Mar 28 01:35:26 PM PDT 24
Finished Mar 28 01:35:35 PM PDT 24
Peak memory 204084 kb
Host smart-03e93994-b9fd-43a4-aed0-2e2ae572774e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24136
99270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.2413699270
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.3850385580
Short name T310
Test name
Test status
Simulation time 8368964369 ps
CPU time 9.47 seconds
Started Mar 28 01:35:28 PM PDT 24
Finished Mar 28 01:35:37 PM PDT 24
Peak memory 204060 kb
Host smart-94bfbd38-2bf2-4cd6-b8f0-6aee66183aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38503
85580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3850385580
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.1919715751
Short name T926
Test name
Test status
Simulation time 8364320778 ps
CPU time 8.34 seconds
Started Mar 28 01:35:32 PM PDT 24
Finished Mar 28 01:35:41 PM PDT 24
Peak memory 204076 kb
Host smart-2591b8e2-eb3c-4f01-b1db-ae77b9ce3e5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19197
15751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.1919715751
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.1838973492
Short name T37
Test name
Test status
Simulation time 31609624 ps
CPU time 0.64 seconds
Started Mar 28 01:35:30 PM PDT 24
Finished Mar 28 01:35:31 PM PDT 24
Peak memory 204016 kb
Host smart-bb0314e8-04e6-4fb2-a18f-362eed6d2791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18389
73492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.1838973492
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.1824523657
Short name T102
Test name
Test status
Simulation time 24841512635 ps
CPU time 44.2 seconds
Started Mar 28 01:35:30 PM PDT 24
Finished Mar 28 01:36:15 PM PDT 24
Peak memory 204344 kb
Host smart-8db6ebea-33c6-4c71-b669-3f7504e238d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18245
23657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.1824523657
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.3391812790
Short name T840
Test name
Test status
Simulation time 8399013105 ps
CPU time 9.1 seconds
Started Mar 28 01:35:31 PM PDT 24
Finished Mar 28 01:35:41 PM PDT 24
Peak memory 204056 kb
Host smart-d109b7c4-91a7-4511-9ae6-a93ddcaa4c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33918
12790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.3391812790
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.2755378834
Short name T1057
Test name
Test status
Simulation time 8417580359 ps
CPU time 9.53 seconds
Started Mar 28 01:35:28 PM PDT 24
Finished Mar 28 01:35:38 PM PDT 24
Peak memory 204088 kb
Host smart-a8e25985-4978-446b-8d40-414e70f48065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27553
78834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2755378834
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.3377686032
Short name T449
Test name
Test status
Simulation time 8367279662 ps
CPU time 7.29 seconds
Started Mar 28 01:35:27 PM PDT 24
Finished Mar 28 01:35:34 PM PDT 24
Peak memory 204052 kb
Host smart-0bd30f90-577c-45ea-bb12-d06ff25953c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33776
86032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.3377686032
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.953400746
Short name T1007
Test name
Test status
Simulation time 8362873157 ps
CPU time 9.61 seconds
Started Mar 28 01:35:35 PM PDT 24
Finished Mar 28 01:35:44 PM PDT 24
Peak memory 204116 kb
Host smart-07ca510c-6546-4c3a-b5eb-2c0e8b32587c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95340
0746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.953400746
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.3117994268
Short name T959
Test name
Test status
Simulation time 8420121380 ps
CPU time 8.77 seconds
Started Mar 28 01:35:26 PM PDT 24
Finished Mar 28 01:35:36 PM PDT 24
Peak memory 203984 kb
Host smart-6aa595ae-2de2-4beb-a0e0-764156f0080a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31179
94268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.3117994268
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2774177105
Short name T907
Test name
Test status
Simulation time 8399008613 ps
CPU time 9.41 seconds
Started Mar 28 01:35:26 PM PDT 24
Finished Mar 28 01:35:35 PM PDT 24
Peak memory 204028 kb
Host smart-3e617bfb-6ba0-499b-92c3-14e79228ac3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27741
77105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2774177105
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.in_iso.2464643136
Short name T57
Test name
Test status
Simulation time 8388496122 ps
CPU time 7.45 seconds
Started Mar 28 01:35:30 PM PDT 24
Finished Mar 28 01:35:38 PM PDT 24
Peak memory 204112 kb
Host smart-a6258309-5b91-4375-9716-4eddfd04c4df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24646
43136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.in_iso.2464643136
Directory /workspace/43.in_iso/latest

Test location /workspace/coverage/default/43.phy_config_usb_ref_disable.951562600
Short name T7
Test name
Test status
Simulation time 8358441526 ps
CPU time 7.58 seconds
Started Mar 28 01:35:26 PM PDT 24
Finished Mar 28 01:35:34 PM PDT 24
Peak memory 204072 kb
Host smart-a6464615-cc1d-4455-b753-0912088180dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95156
2600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.phy_config_usb_ref_disable.951562600
Directory /workspace/43.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.153837716
Short name T666
Test name
Test status
Simulation time 8372072854 ps
CPU time 9.14 seconds
Started Mar 28 01:35:29 PM PDT 24
Finished Mar 28 01:35:38 PM PDT 24
Peak memory 204048 kb
Host smart-7f24b240-8868-47b5-abf3-300bc0127a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15383
7716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.153837716
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_enable.1823483809
Short name T484
Test name
Test status
Simulation time 8369883431 ps
CPU time 7.39 seconds
Started Mar 28 01:35:28 PM PDT 24
Finished Mar 28 01:35:36 PM PDT 24
Peak memory 204040 kb
Host smart-b2cf184c-724a-42de-b60a-39cb8bd454d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18234
83809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1823483809
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.4166322127
Short name T811
Test name
Test status
Simulation time 57671449 ps
CPU time 1.6 seconds
Started Mar 28 01:35:29 PM PDT 24
Finished Mar 28 01:35:31 PM PDT 24
Peak memory 204168 kb
Host smart-f980e8dc-6fc1-4a2a-8cae-fcaf09841c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41663
22127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.4166322127
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.4228058880
Short name T194
Test name
Test status
Simulation time 8355753601 ps
CPU time 7.17 seconds
Started Mar 28 01:35:32 PM PDT 24
Finished Mar 28 01:35:39 PM PDT 24
Peak memory 203780 kb
Host smart-2066bad1-d206-437c-9c90-41f23dcc2616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42280
58880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.4228058880
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.2269027167
Short name T160
Test name
Test status
Simulation time 8424442828 ps
CPU time 7.93 seconds
Started Mar 28 01:35:30 PM PDT 24
Finished Mar 28 01:35:38 PM PDT 24
Peak memory 203920 kb
Host smart-6ed3d36c-bb40-4895-9454-d0d3ca3ef50c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22690
27167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.2269027167
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2992933885
Short name T844
Test name
Test status
Simulation time 8407986766 ps
CPU time 8.84 seconds
Started Mar 28 01:35:29 PM PDT 24
Finished Mar 28 01:35:38 PM PDT 24
Peak memory 204068 kb
Host smart-69ee48c3-1fb2-4529-b37c-fc573e8d9f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29929
33885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2992933885
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.2395522325
Short name T580
Test name
Test status
Simulation time 8362045559 ps
CPU time 8.07 seconds
Started Mar 28 01:35:30 PM PDT 24
Finished Mar 28 01:35:38 PM PDT 24
Peak memory 204052 kb
Host smart-033f11c4-d9ed-445e-93bd-0766c80a06e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23955
22325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.2395522325
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.1935918002
Short name T142
Test name
Test status
Simulation time 8385799038 ps
CPU time 7.29 seconds
Started Mar 28 01:35:29 PM PDT 24
Finished Mar 28 01:35:37 PM PDT 24
Peak memory 204080 kb
Host smart-1131edac-659e-4131-b337-572247e226db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19359
18002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.1935918002
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.2537273295
Short name T707
Test name
Test status
Simulation time 8371753198 ps
CPU time 7.11 seconds
Started Mar 28 01:35:31 PM PDT 24
Finished Mar 28 01:35:38 PM PDT 24
Peak memory 204080 kb
Host smart-e9ab780b-40af-4ba0-8a2c-cd98ab49a498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25372
73295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.2537273295
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3587604536
Short name T891
Test name
Test status
Simulation time 8374534792 ps
CPU time 7.17 seconds
Started Mar 28 01:35:30 PM PDT 24
Finished Mar 28 01:35:37 PM PDT 24
Peak memory 204080 kb
Host smart-e2e2a00d-7119-40c5-b136-5582c113e51a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35876
04536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3587604536
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.402773708
Short name T487
Test name
Test status
Simulation time 24667879 ps
CPU time 0.64 seconds
Started Mar 28 01:35:33 PM PDT 24
Finished Mar 28 01:35:34 PM PDT 24
Peak memory 203976 kb
Host smart-5f1bf0fd-e73a-436a-9a53-0a87ef86dd10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40277
3708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.402773708
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.146646668
Short name T101
Test name
Test status
Simulation time 19040747573 ps
CPU time 39.81 seconds
Started Mar 28 01:35:31 PM PDT 24
Finished Mar 28 01:36:11 PM PDT 24
Peak memory 204388 kb
Host smart-269e99a0-46a2-4d66-be7e-c9ce2662af8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14664
6668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.146646668
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.3862410011
Short name T306
Test name
Test status
Simulation time 8381848850 ps
CPU time 8.54 seconds
Started Mar 28 01:35:32 PM PDT 24
Finished Mar 28 01:35:41 PM PDT 24
Peak memory 204116 kb
Host smart-982f278b-491e-4643-b45e-eb5bf16d14f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38624
10011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.3862410011
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.1739596521
Short name T547
Test name
Test status
Simulation time 8431936087 ps
CPU time 7.56 seconds
Started Mar 28 01:35:30 PM PDT 24
Finished Mar 28 01:35:37 PM PDT 24
Peak memory 204064 kb
Host smart-d1b53ca4-1781-4577-bbe4-a95c31317a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17395
96521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.1739596521
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.316243873
Short name T253
Test name
Test status
Simulation time 8379873146 ps
CPU time 7.16 seconds
Started Mar 28 01:35:32 PM PDT 24
Finished Mar 28 01:35:39 PM PDT 24
Peak memory 204084 kb
Host smart-a98f490f-ee0a-4967-b1ec-4921c7edbff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31624
3873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.316243873
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.29435570
Short name T561
Test name
Test status
Simulation time 8362419179 ps
CPU time 7.52 seconds
Started Mar 28 01:35:31 PM PDT 24
Finished Mar 28 01:35:38 PM PDT 24
Peak memory 204036 kb
Host smart-ba8d8b2e-9423-415e-967a-aee5f06054d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29435
570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.29435570
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.322976318
Short name T787
Test name
Test status
Simulation time 8416392630 ps
CPU time 7.76 seconds
Started Mar 28 01:35:31 PM PDT 24
Finished Mar 28 01:35:39 PM PDT 24
Peak memory 204052 kb
Host smart-cc7e2930-fd9c-40d8-81a4-dd00413a74b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32297
6318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.322976318
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.3031213516
Short name T556
Test name
Test status
Simulation time 8376302792 ps
CPU time 8.26 seconds
Started Mar 28 01:35:32 PM PDT 24
Finished Mar 28 01:35:40 PM PDT 24
Peak memory 203932 kb
Host smart-146159fb-952d-406d-bddf-80766206385c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30312
13516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.3031213516
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.in_iso.881378788
Short name T745
Test name
Test status
Simulation time 8421451501 ps
CPU time 7.46 seconds
Started Mar 28 01:35:46 PM PDT 24
Finished Mar 28 01:35:53 PM PDT 24
Peak memory 204084 kb
Host smart-647170a3-5b77-4ee8-b3bd-af6a7665eea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88137
8788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.in_iso.881378788
Directory /workspace/44.in_iso/latest

Test location /workspace/coverage/default/44.phy_config_usb_ref_disable.2658507585
Short name T816
Test name
Test status
Simulation time 8361986332 ps
CPU time 8.14 seconds
Started Mar 28 01:35:44 PM PDT 24
Finished Mar 28 01:35:52 PM PDT 24
Peak memory 204016 kb
Host smart-295b499a-2790-4af8-8417-da7875ed06e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26585
07585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.phy_config_usb_ref_disable.2658507585
Directory /workspace/44.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.2077368899
Short name T507
Test name
Test status
Simulation time 8368675124 ps
CPU time 9.41 seconds
Started Mar 28 01:35:32 PM PDT 24
Finished Mar 28 01:35:42 PM PDT 24
Peak memory 203808 kb
Host smart-60a0ad35-123b-4f59-8697-9e6459af538b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20773
68899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.2077368899
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_enable.4279400725
Short name T249
Test name
Test status
Simulation time 8372274520 ps
CPU time 9.31 seconds
Started Mar 28 01:35:26 PM PDT 24
Finished Mar 28 01:35:36 PM PDT 24
Peak memory 204084 kb
Host smart-ee437158-5ff5-4b66-ae55-077735af5c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42794
00725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.4279400725
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.503804819
Short name T657
Test name
Test status
Simulation time 173062711 ps
CPU time 2.16 seconds
Started Mar 28 01:35:29 PM PDT 24
Finished Mar 28 01:35:32 PM PDT 24
Peak memory 204168 kb
Host smart-5b25cd7f-8143-42ac-95c9-ba40341d8aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50380
4819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.503804819
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.1820512070
Short name T931
Test name
Test status
Simulation time 8358230336 ps
CPU time 7.66 seconds
Started Mar 28 01:35:44 PM PDT 24
Finished Mar 28 01:35:52 PM PDT 24
Peak memory 204064 kb
Host smart-d3607827-4896-4414-9b82-46ee1d54f151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18205
12070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.1820512070
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3408406615
Short name T1046
Test name
Test status
Simulation time 8453338464 ps
CPU time 8.22 seconds
Started Mar 28 01:35:33 PM PDT 24
Finished Mar 28 01:35:41 PM PDT 24
Peak memory 204084 kb
Host smart-ae1b71d0-4cf3-4d82-b6c3-8198000c9a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34084
06615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3408406615
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.3203263819
Short name T725
Test name
Test status
Simulation time 8414560857 ps
CPU time 7.16 seconds
Started Mar 28 01:35:44 PM PDT 24
Finished Mar 28 01:35:51 PM PDT 24
Peak memory 204100 kb
Host smart-384ac68e-8ca5-49b9-be58-f4e0e89d1d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32032
63819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.3203263819
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.2394298035
Short name T404
Test name
Test status
Simulation time 8362391575 ps
CPU time 7.08 seconds
Started Mar 28 01:35:45 PM PDT 24
Finished Mar 28 01:35:52 PM PDT 24
Peak memory 204048 kb
Host smart-2aff4c28-40bb-4583-b09c-dba774e2dbe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23942
98035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.2394298035
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.470795801
Short name T119
Test name
Test status
Simulation time 8424161539 ps
CPU time 9.72 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:36:00 PM PDT 24
Peak memory 204088 kb
Host smart-06901718-c0b1-4952-89e8-4ff4493e7547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47079
5801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.470795801
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.2355040954
Short name T375
Test name
Test status
Simulation time 8382646405 ps
CPU time 7.34 seconds
Started Mar 28 01:35:46 PM PDT 24
Finished Mar 28 01:35:53 PM PDT 24
Peak memory 204052 kb
Host smart-d633c75a-48f3-491c-ae45-ec21583ffc44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23550
40954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.2355040954
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3920583717
Short name T418
Test name
Test status
Simulation time 8394006486 ps
CPU time 7.18 seconds
Started Mar 28 01:35:45 PM PDT 24
Finished Mar 28 01:35:52 PM PDT 24
Peak memory 204056 kb
Host smart-f0b21128-8269-46aa-a3ec-7576ab57982a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39205
83717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3920583717
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.2335095735
Short name T675
Test name
Test status
Simulation time 33595606 ps
CPU time 0.62 seconds
Started Mar 28 01:35:39 PM PDT 24
Finished Mar 28 01:35:39 PM PDT 24
Peak memory 203984 kb
Host smart-543c23b1-baf7-4928-96fa-b5bbcaebaa96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23350
95735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.2335095735
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.928089167
Short name T53
Test name
Test status
Simulation time 19287193670 ps
CPU time 33.26 seconds
Started Mar 28 01:35:48 PM PDT 24
Finished Mar 28 01:36:21 PM PDT 24
Peak memory 204376 kb
Host smart-6fb24a4a-0012-48be-8115-2f6a2c4c68eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92808
9167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.928089167
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.3636878850
Short name T984
Test name
Test status
Simulation time 8382986192 ps
CPU time 8.31 seconds
Started Mar 28 01:35:46 PM PDT 24
Finished Mar 28 01:35:54 PM PDT 24
Peak memory 204096 kb
Host smart-ea69b8d8-10a7-4d38-b2da-35688f01ac8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36368
78850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.3636878850
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1680217571
Short name T161
Test name
Test status
Simulation time 8447787013 ps
CPU time 7.26 seconds
Started Mar 28 01:35:45 PM PDT 24
Finished Mar 28 01:35:53 PM PDT 24
Peak memory 204080 kb
Host smart-c56db941-3048-4d96-80f6-40d24ecc0ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16802
17571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1680217571
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.1980319643
Short name T454
Test name
Test status
Simulation time 8369675488 ps
CPU time 9.11 seconds
Started Mar 28 01:35:48 PM PDT 24
Finished Mar 28 01:35:58 PM PDT 24
Peak memory 204028 kb
Host smart-240fd69e-7a7b-4b5e-8875-aea2254ce99f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19803
19643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.1980319643
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.695691821
Short name T949
Test name
Test status
Simulation time 8362001311 ps
CPU time 8.28 seconds
Started Mar 28 01:35:47 PM PDT 24
Finished Mar 28 01:35:55 PM PDT 24
Peak memory 204060 kb
Host smart-99dbeb70-b909-492b-b8ff-18ac903a522e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69569
1821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.695691821
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.2030757784
Short name T166
Test name
Test status
Simulation time 8430715874 ps
CPU time 8.42 seconds
Started Mar 28 01:35:33 PM PDT 24
Finished Mar 28 01:35:42 PM PDT 24
Peak memory 204040 kb
Host smart-be4c1741-950c-4943-a914-1ee985dad705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20307
57784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.2030757784
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.108790089
Short name T395
Test name
Test status
Simulation time 8406762462 ps
CPU time 9.94 seconds
Started Mar 28 01:35:44 PM PDT 24
Finished Mar 28 01:35:54 PM PDT 24
Peak memory 204052 kb
Host smart-92927ee3-b57e-4217-abb3-fe5b2d7e1161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10879
0089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.108790089
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.phy_config_usb_ref_disable.3050098401
Short name T797
Test name
Test status
Simulation time 8357632931 ps
CPU time 8.29 seconds
Started Mar 28 01:35:46 PM PDT 24
Finished Mar 28 01:35:54 PM PDT 24
Peak memory 204072 kb
Host smart-b984f5b9-0216-4036-b7a0-80ceb8033689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30500
98401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.phy_config_usb_ref_disable.3050098401
Directory /workspace/45.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.990795502
Short name T336
Test name
Test status
Simulation time 8369308189 ps
CPU time 7.61 seconds
Started Mar 28 01:35:47 PM PDT 24
Finished Mar 28 01:35:55 PM PDT 24
Peak memory 204052 kb
Host smart-02ab635a-2ce4-4fc6-a90b-948cec22a0b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99079
5502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.990795502
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_enable.52351945
Short name T976
Test name
Test status
Simulation time 8373552355 ps
CPU time 7.58 seconds
Started Mar 28 01:35:46 PM PDT 24
Finished Mar 28 01:35:54 PM PDT 24
Peak memory 204072 kb
Host smart-1100ba4d-3cbc-4431-9bb5-56727b9c26d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52351
945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.52351945
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.2006185417
Short name T699
Test name
Test status
Simulation time 48130908 ps
CPU time 1.56 seconds
Started Mar 28 01:35:48 PM PDT 24
Finished Mar 28 01:35:50 PM PDT 24
Peak memory 204112 kb
Host smart-9234188c-1f45-4b33-9f3c-adb2f43b6da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20061
85417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.2006185417
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.2817134678
Short name T969
Test name
Test status
Simulation time 8363651860 ps
CPU time 7.77 seconds
Started Mar 28 01:35:45 PM PDT 24
Finished Mar 28 01:35:53 PM PDT 24
Peak memory 204044 kb
Host smart-c0806808-6950-4c5e-a484-5571aa37a683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28171
34678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.2817134678
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.3427668583
Short name T1012
Test name
Test status
Simulation time 8459575549 ps
CPU time 7.98 seconds
Started Mar 28 01:35:47 PM PDT 24
Finished Mar 28 01:35:55 PM PDT 24
Peak memory 204044 kb
Host smart-0a5fb6ef-48a0-43e8-a18f-5deebab5bc79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34276
68583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3427668583
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.1885168937
Short name T817
Test name
Test status
Simulation time 8406551825 ps
CPU time 7.74 seconds
Started Mar 28 01:35:47 PM PDT 24
Finished Mar 28 01:35:55 PM PDT 24
Peak memory 204084 kb
Host smart-418a0f95-ab45-45a5-90d1-0889cbd11dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18851
68937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.1885168937
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.3436774018
Short name T521
Test name
Test status
Simulation time 8365049421 ps
CPU time 8.19 seconds
Started Mar 28 01:35:48 PM PDT 24
Finished Mar 28 01:35:57 PM PDT 24
Peak memory 204024 kb
Host smart-bcc2291e-96ae-49d8-a730-0829f614a59b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34367
74018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.3436774018
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.869088258
Short name T133
Test name
Test status
Simulation time 8414893670 ps
CPU time 8.51 seconds
Started Mar 28 01:35:45 PM PDT 24
Finished Mar 28 01:35:53 PM PDT 24
Peak memory 204056 kb
Host smart-6af4f3f6-daaf-4531-95be-713d4880302f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86908
8258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.869088258
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.59987339
Short name T308
Test name
Test status
Simulation time 8369146380 ps
CPU time 8.65 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:35:59 PM PDT 24
Peak memory 204088 kb
Host smart-2f75eb3f-add4-41b2-8bde-4930e1484360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59987
339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.59987339
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3258559187
Short name T806
Test name
Test status
Simulation time 8394863177 ps
CPU time 7.23 seconds
Started Mar 28 01:35:42 PM PDT 24
Finished Mar 28 01:35:49 PM PDT 24
Peak memory 204080 kb
Host smart-787d198e-f52a-46d8-af27-86939316c9ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32585
59187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3258559187
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.3381162350
Short name T818
Test name
Test status
Simulation time 24575888 ps
CPU time 0.65 seconds
Started Mar 28 01:35:45 PM PDT 24
Finished Mar 28 01:35:46 PM PDT 24
Peak memory 204020 kb
Host smart-5df2a681-bfbb-41ff-a553-b803b443ba5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33811
62350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.3381162350
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.3959039629
Short name T188
Test name
Test status
Simulation time 23739639126 ps
CPU time 41.97 seconds
Started Mar 28 01:35:46 PM PDT 24
Finished Mar 28 01:36:28 PM PDT 24
Peak memory 204268 kb
Host smart-1589986b-bd01-4d97-8712-9d9b055a2783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39590
39629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.3959039629
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.1689755238
Short name T425
Test name
Test status
Simulation time 8404031054 ps
CPU time 7.34 seconds
Started Mar 28 01:35:44 PM PDT 24
Finished Mar 28 01:35:51 PM PDT 24
Peak memory 204076 kb
Host smart-7a0a3c0c-732e-4c01-8e67-2258afa5bd39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16897
55238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.1689755238
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.249755340
Short name T677
Test name
Test status
Simulation time 8408175534 ps
CPU time 7.19 seconds
Started Mar 28 01:35:42 PM PDT 24
Finished Mar 28 01:35:49 PM PDT 24
Peak memory 204080 kb
Host smart-fa1c8c9c-8411-412d-8b53-ada3380ead49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24975
5340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.249755340
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.3856295850
Short name T496
Test name
Test status
Simulation time 8369017718 ps
CPU time 7.4 seconds
Started Mar 28 01:35:48 PM PDT 24
Finished Mar 28 01:35:56 PM PDT 24
Peak memory 204028 kb
Host smart-6c93f6f3-07f1-4063-a95e-8249cdfa15f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38562
95850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.3856295850
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.744068334
Short name T1001
Test name
Test status
Simulation time 8357730803 ps
CPU time 6.99 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:35:57 PM PDT 24
Peak memory 204116 kb
Host smart-66f376c3-e026-4182-a979-d087f6a3503b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74406
8334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.744068334
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.252087422
Short name T874
Test name
Test status
Simulation time 8438695905 ps
CPU time 7.06 seconds
Started Mar 28 01:35:41 PM PDT 24
Finished Mar 28 01:35:48 PM PDT 24
Peak memory 204036 kb
Host smart-3a412229-03c5-4855-9f74-115c62733895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25208
7422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.252087422
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.2911449747
Short name T465
Test name
Test status
Simulation time 8401957972 ps
CPU time 7.21 seconds
Started Mar 28 01:35:45 PM PDT 24
Finished Mar 28 01:35:53 PM PDT 24
Peak memory 204040 kb
Host smart-77983edc-031e-419d-8652-2c6a9874d132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29114
49747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.2911449747
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.in_iso.2420467933
Short name T712
Test name
Test status
Simulation time 8424206961 ps
CPU time 9.47 seconds
Started Mar 28 01:35:47 PM PDT 24
Finished Mar 28 01:35:57 PM PDT 24
Peak memory 204080 kb
Host smart-b357d459-d1fd-4ec7-90fa-4159cc45d9c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24204
67933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.in_iso.2420467933
Directory /workspace/46.in_iso/latest

Test location /workspace/coverage/default/46.phy_config_usb_ref_disable.3157805715
Short name T364
Test name
Test status
Simulation time 8363852933 ps
CPU time 7.14 seconds
Started Mar 28 01:35:47 PM PDT 24
Finished Mar 28 01:35:55 PM PDT 24
Peak memory 204084 kb
Host smart-dc41b977-a910-40de-aa62-0bda3df45256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31578
05715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.phy_config_usb_ref_disable.3157805715
Directory /workspace/46.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.793351606
Short name T498
Test name
Test status
Simulation time 8366895602 ps
CPU time 8.39 seconds
Started Mar 28 01:35:45 PM PDT 24
Finished Mar 28 01:35:53 PM PDT 24
Peak memory 204048 kb
Host smart-0ea4a1f3-6d3b-4a9a-bd1b-60cc04dfc327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79335
1606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.793351606
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_enable.4277292376
Short name T726
Test name
Test status
Simulation time 8368969493 ps
CPU time 6.94 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:35:57 PM PDT 24
Peak memory 204072 kb
Host smart-a7f431c3-5a8c-4049-b9bb-30bbc17d3b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42772
92376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.4277292376
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.2583389770
Short name T1070
Test name
Test status
Simulation time 160578449 ps
CPU time 1.52 seconds
Started Mar 28 01:35:47 PM PDT 24
Finished Mar 28 01:35:49 PM PDT 24
Peak memory 204264 kb
Host smart-6988b3a3-6ce6-4b98-ad89-e40598e6fdcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25833
89770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.2583389770
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.1668918829
Short name T217
Test name
Test status
Simulation time 8361599153 ps
CPU time 7.42 seconds
Started Mar 28 01:35:45 PM PDT 24
Finished Mar 28 01:35:53 PM PDT 24
Peak memory 204044 kb
Host smart-a4c0b56b-ae2e-4ae3-b715-a326dfebe421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16689
18829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.1668918829
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.3452918183
Short name T443
Test name
Test status
Simulation time 8379846832 ps
CPU time 7.28 seconds
Started Mar 28 01:35:48 PM PDT 24
Finished Mar 28 01:35:56 PM PDT 24
Peak memory 204016 kb
Host smart-c82a7123-03cb-4c20-a986-a42647d9b752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34529
18183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.3452918183
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.3065359369
Short name T451
Test name
Test status
Simulation time 8411216884 ps
CPU time 8.45 seconds
Started Mar 28 01:35:45 PM PDT 24
Finished Mar 28 01:35:54 PM PDT 24
Peak memory 204092 kb
Host smart-28685e0a-6368-48bb-aaff-2c04fc82e4cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30653
59369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.3065359369
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.3647145846
Short name T294
Test name
Test status
Simulation time 8368790511 ps
CPU time 8.38 seconds
Started Mar 28 01:35:44 PM PDT 24
Finished Mar 28 01:35:53 PM PDT 24
Peak memory 204096 kb
Host smart-61740470-610b-4270-8c7b-6e847d31d4ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36471
45846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.3647145846
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.588326368
Short name T130
Test name
Test status
Simulation time 8425130630 ps
CPU time 7.42 seconds
Started Mar 28 01:35:46 PM PDT 24
Finished Mar 28 01:35:54 PM PDT 24
Peak memory 204080 kb
Host smart-a4e49e91-e1af-4748-b306-a5f7a3ac7014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58832
6368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.588326368
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2278894502
Short name T87
Test name
Test status
Simulation time 8393678879 ps
CPU time 8.62 seconds
Started Mar 28 01:35:47 PM PDT 24
Finished Mar 28 01:35:55 PM PDT 24
Peak memory 204048 kb
Host smart-598ec119-4097-4c1e-a85a-07d414161eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22788
94502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2278894502
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.619502734
Short name T676
Test name
Test status
Simulation time 8360341885 ps
CPU time 7.84 seconds
Started Mar 28 01:35:44 PM PDT 24
Finished Mar 28 01:35:52 PM PDT 24
Peak memory 204048 kb
Host smart-f63cde1a-91ab-4da4-a515-1c77202f0a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61950
2734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.619502734
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.4014974456
Short name T38
Test name
Test status
Simulation time 28565302 ps
CPU time 0.64 seconds
Started Mar 28 01:35:48 PM PDT 24
Finished Mar 28 01:35:49 PM PDT 24
Peak memory 204048 kb
Host smart-9b244ad6-595e-4b48-86fe-e37530eac4a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40149
74456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.4014974456
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.3344214398
Short name T110
Test name
Test status
Simulation time 28554549154 ps
CPU time 49.23 seconds
Started Mar 28 01:35:45 PM PDT 24
Finished Mar 28 01:36:35 PM PDT 24
Peak memory 204304 kb
Host smart-b0725896-a857-44a5-a444-5c7690bf7360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33442
14398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.3344214398
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.273907134
Short name T480
Test name
Test status
Simulation time 8393632477 ps
CPU time 7.24 seconds
Started Mar 28 01:35:43 PM PDT 24
Finished Mar 28 01:35:50 PM PDT 24
Peak memory 204096 kb
Host smart-11e93386-92e6-4a2c-b123-85bbad805fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27390
7134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.273907134
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.723844104
Short name T563
Test name
Test status
Simulation time 8427944054 ps
CPU time 7.74 seconds
Started Mar 28 01:35:47 PM PDT 24
Finished Mar 28 01:35:55 PM PDT 24
Peak memory 204088 kb
Host smart-e73321f6-241d-47cb-a846-32b12e037205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72384
4104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.723844104
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.2051909679
Short name T755
Test name
Test status
Simulation time 8372386071 ps
CPU time 8.25 seconds
Started Mar 28 01:35:47 PM PDT 24
Finished Mar 28 01:35:55 PM PDT 24
Peak memory 204052 kb
Host smart-df51fb7d-69bf-4f1c-9c6d-3ab726f2d470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20519
09679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.2051909679
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.440813088
Short name T581
Test name
Test status
Simulation time 8361029244 ps
CPU time 7.05 seconds
Started Mar 28 01:35:47 PM PDT 24
Finished Mar 28 01:35:54 PM PDT 24
Peak memory 204064 kb
Host smart-06e41b38-0ab1-4faf-b05a-a1059126f729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44081
3088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.440813088
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.1775701356
Short name T1014
Test name
Test status
Simulation time 8432260344 ps
CPU time 7.31 seconds
Started Mar 28 01:35:47 PM PDT 24
Finished Mar 28 01:35:54 PM PDT 24
Peak memory 204048 kb
Host smart-b7181f08-c654-44ae-9f9a-96f7163957f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17757
01356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.1775701356
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.114968839
Short name T296
Test name
Test status
Simulation time 8370890163 ps
CPU time 7.54 seconds
Started Mar 28 01:35:46 PM PDT 24
Finished Mar 28 01:35:54 PM PDT 24
Peak memory 204052 kb
Host smart-50893d6a-97e5-4d44-8cf7-03d5b765df67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11496
8839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.114968839
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.in_iso.3756885174
Short name T953
Test name
Test status
Simulation time 8443998658 ps
CPU time 7.77 seconds
Started Mar 28 01:35:48 PM PDT 24
Finished Mar 28 01:35:56 PM PDT 24
Peak memory 204076 kb
Host smart-e53f150e-59e5-4d83-93b7-7ff340dfea4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37568
85174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.in_iso.3756885174
Directory /workspace/47.in_iso/latest

Test location /workspace/coverage/default/47.phy_config_usb_ref_disable.1253967423
Short name T881
Test name
Test status
Simulation time 8365395894 ps
CPU time 7.58 seconds
Started Mar 28 01:35:48 PM PDT 24
Finished Mar 28 01:35:56 PM PDT 24
Peak memory 204076 kb
Host smart-d8ea4c4f-08ee-4c2d-80ab-c45f3d061f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12539
67423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.phy_config_usb_ref_disable.1253967423
Directory /workspace/47.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.3689817487
Short name T908
Test name
Test status
Simulation time 8369303242 ps
CPU time 7.2 seconds
Started Mar 28 01:35:46 PM PDT 24
Finished Mar 28 01:35:54 PM PDT 24
Peak memory 204028 kb
Host smart-cc6845d1-e5fc-49c7-a0a3-3df790e2406a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36898
17487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.3689817487
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_enable.2527185107
Short name T730
Test name
Test status
Simulation time 8366220046 ps
CPU time 7.45 seconds
Started Mar 28 01:35:49 PM PDT 24
Finished Mar 28 01:35:56 PM PDT 24
Peak memory 204028 kb
Host smart-949540b8-2986-44ca-b94a-d8cf170bb6ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25271
85107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2527185107
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.2483195554
Short name T1037
Test name
Test status
Simulation time 55166124 ps
CPU time 1.62 seconds
Started Mar 28 01:35:49 PM PDT 24
Finished Mar 28 01:35:51 PM PDT 24
Peak memory 203616 kb
Host smart-07ae89b9-0a39-45ca-a69c-aa5d2b91ebca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24831
95554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.2483195554
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.3719333417
Short name T518
Test name
Test status
Simulation time 8363467075 ps
CPU time 7.21 seconds
Started Mar 28 01:35:46 PM PDT 24
Finished Mar 28 01:35:54 PM PDT 24
Peak memory 204056 kb
Host smart-118b3e98-89bb-4dd0-9337-c13840b7970f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37193
33417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.3719333417
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.1982219067
Short name T980
Test name
Test status
Simulation time 8454276818 ps
CPU time 8.68 seconds
Started Mar 28 01:35:47 PM PDT 24
Finished Mar 28 01:35:55 PM PDT 24
Peak memory 204016 kb
Host smart-08b3d95d-2aca-4257-9a14-35cd9d517dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19822
19067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.1982219067
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.664443621
Short name T305
Test name
Test status
Simulation time 8414054155 ps
CPU time 8.21 seconds
Started Mar 28 01:35:48 PM PDT 24
Finished Mar 28 01:35:57 PM PDT 24
Peak memory 204020 kb
Host smart-8b241cb7-0c59-45df-8e8d-5e7a8a691bc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66444
3621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.664443621
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.513583388
Short name T1065
Test name
Test status
Simulation time 8365450058 ps
CPU time 9.49 seconds
Started Mar 28 01:35:47 PM PDT 24
Finished Mar 28 01:35:57 PM PDT 24
Peak memory 204088 kb
Host smart-7f57670e-2ffe-48c3-a453-802269babc61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51358
3388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.513583388
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.4092681962
Short name T921
Test name
Test status
Simulation time 8404934348 ps
CPU time 7.12 seconds
Started Mar 28 01:35:48 PM PDT 24
Finished Mar 28 01:35:56 PM PDT 24
Peak memory 204024 kb
Host smart-98539a1c-f2c3-4080-939b-9377f2af1a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40926
81962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.4092681962
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.3770552774
Short name T16
Test name
Test status
Simulation time 8390731317 ps
CPU time 7.02 seconds
Started Mar 28 01:35:48 PM PDT 24
Finished Mar 28 01:35:55 PM PDT 24
Peak memory 204088 kb
Host smart-ed8c874c-257e-408e-890f-9641ebe0d658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37705
52774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.3770552774
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3952277354
Short name T357
Test name
Test status
Simulation time 8378998198 ps
CPU time 7.41 seconds
Started Mar 28 01:35:45 PM PDT 24
Finished Mar 28 01:35:53 PM PDT 24
Peak memory 204056 kb
Host smart-98715ad6-6bc4-4ad1-a216-e66908ba6e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39522
77354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3952277354
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.4277739529
Short name T1025
Test name
Test status
Simulation time 25081664 ps
CPU time 0.64 seconds
Started Mar 28 01:35:48 PM PDT 24
Finished Mar 28 01:35:49 PM PDT 24
Peak memory 204024 kb
Host smart-c2d30300-88e8-4881-ae59-985e2e31ab7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42777
39529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.4277739529
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.2958049037
Short name T193
Test name
Test status
Simulation time 27251214772 ps
CPU time 56.53 seconds
Started Mar 28 01:35:46 PM PDT 24
Finished Mar 28 01:36:43 PM PDT 24
Peak memory 204320 kb
Host smart-5d8af567-c773-4b96-9581-c9f5bd6a071f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29580
49037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.2958049037
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.606847333
Short name T664
Test name
Test status
Simulation time 8379515086 ps
CPU time 7.1 seconds
Started Mar 28 01:35:49 PM PDT 24
Finished Mar 28 01:35:56 PM PDT 24
Peak memory 204072 kb
Host smart-f26302af-5d58-4014-ae51-fd39d1e0a9cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60684
7333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.606847333
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.3911326630
Short name T546
Test name
Test status
Simulation time 8435295930 ps
CPU time 7.4 seconds
Started Mar 28 01:35:48 PM PDT 24
Finished Mar 28 01:35:56 PM PDT 24
Peak memory 204088 kb
Host smart-f3b2c6b8-1d7d-4e6d-9bc5-c7faec4bb427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39113
26630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3911326630
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.832059992
Short name T942
Test name
Test status
Simulation time 8406816706 ps
CPU time 7.37 seconds
Started Mar 28 01:35:49 PM PDT 24
Finished Mar 28 01:35:57 PM PDT 24
Peak memory 204076 kb
Host smart-382d07a4-d817-474c-94b9-47e4c37401a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83205
9992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.832059992
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.1306456380
Short name T847
Test name
Test status
Simulation time 8355077536 ps
CPU time 7.47 seconds
Started Mar 28 01:35:48 PM PDT 24
Finished Mar 28 01:35:56 PM PDT 24
Peak memory 204068 kb
Host smart-fabbbdc1-a45b-4e26-8798-a089493123b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13064
56380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.1306456380
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.46613834
Short name T174
Test name
Test status
Simulation time 8419373462 ps
CPU time 7.19 seconds
Started Mar 28 01:35:49 PM PDT 24
Finished Mar 28 01:35:57 PM PDT 24
Peak memory 203980 kb
Host smart-0694b242-9bca-4069-ae67-a36486bd2136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46613
834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.46613834
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.81102943
Short name T809
Test name
Test status
Simulation time 8385403483 ps
CPU time 7.5 seconds
Started Mar 28 01:35:48 PM PDT 24
Finished Mar 28 01:35:56 PM PDT 24
Peak memory 204048 kb
Host smart-c94139ff-fae9-4923-8aa6-65e4d16f15d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81102
943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.81102943
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.in_iso.3920495112
Short name T721
Test name
Test status
Simulation time 8434045312 ps
CPU time 7.4 seconds
Started Mar 28 01:35:52 PM PDT 24
Finished Mar 28 01:36:00 PM PDT 24
Peak memory 204116 kb
Host smart-073e4e85-fa55-439a-8c58-bfc7137dd693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39204
95112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.in_iso.3920495112
Directory /workspace/48.in_iso/latest

Test location /workspace/coverage/default/48.phy_config_usb_ref_disable.4060643174
Short name T715
Test name
Test status
Simulation time 8362149709 ps
CPU time 7.5 seconds
Started Mar 28 01:35:55 PM PDT 24
Finished Mar 28 01:36:03 PM PDT 24
Peak memory 204084 kb
Host smart-c3b5250c-07c7-46f6-a907-b88ebbb1da43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40606
43174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.phy_config_usb_ref_disable.4060643174
Directory /workspace/48.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.502497546
Short name T456
Test name
Test status
Simulation time 8373167966 ps
CPU time 7.29 seconds
Started Mar 28 01:35:52 PM PDT 24
Finished Mar 28 01:35:59 PM PDT 24
Peak memory 204072 kb
Host smart-ddc5f661-327d-4c7c-8ae5-4aa6721bdb03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50249
7546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.502497546
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_enable.2439112049
Short name T552
Test name
Test status
Simulation time 8373430856 ps
CPU time 7.48 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:35:57 PM PDT 24
Peak memory 204076 kb
Host smart-9cfd667f-06a3-41ff-9c4a-79f6e5e7a880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24391
12049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.2439112049
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.347760452
Short name T519
Test name
Test status
Simulation time 73267782 ps
CPU time 2.03 seconds
Started Mar 28 01:35:49 PM PDT 24
Finished Mar 28 01:35:51 PM PDT 24
Peak memory 204284 kb
Host smart-890e1141-38d1-4a04-8e95-2f0d3a5c2a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34776
0452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.347760452
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.2737993862
Short name T221
Test name
Test status
Simulation time 8359233437 ps
CPU time 7.43 seconds
Started Mar 28 01:35:52 PM PDT 24
Finished Mar 28 01:36:00 PM PDT 24
Peak memory 204084 kb
Host smart-cb7ab33f-0bc9-49be-a1c0-da71de717341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27379
93862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.2737993862
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1346817454
Short name T148
Test name
Test status
Simulation time 8409891101 ps
CPU time 7.65 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:35:57 PM PDT 24
Peak memory 204080 kb
Host smart-08007368-a883-48fc-adb1-be43198a3085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13468
17454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1346817454
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.292077855
Short name T766
Test name
Test status
Simulation time 8410366322 ps
CPU time 7.36 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:35:58 PM PDT 24
Peak memory 204012 kb
Host smart-23915860-4cdb-437f-af36-3de7c7bd6f63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29207
7855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.292077855
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.4030003477
Short name T879
Test name
Test status
Simulation time 8360473115 ps
CPU time 7.09 seconds
Started Mar 28 01:35:49 PM PDT 24
Finished Mar 28 01:35:57 PM PDT 24
Peak memory 204012 kb
Host smart-25d040ed-f54f-4380-adb8-f34698decdf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40300
03477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.4030003477
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.659060765
Short name T141
Test name
Test status
Simulation time 8420209408 ps
CPU time 7.23 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:35:58 PM PDT 24
Peak memory 204088 kb
Host smart-2eccefb3-83a6-42f4-a9c5-2df13aab7273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65906
0765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.659060765
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3483965610
Short name T447
Test name
Test status
Simulation time 8363059073 ps
CPU time 7.44 seconds
Started Mar 28 01:35:52 PM PDT 24
Finished Mar 28 01:36:00 PM PDT 24
Peak memory 204080 kb
Host smart-5a7a606c-b8bf-490c-93cd-df8802d4462e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34839
65610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3483965610
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.4131275393
Short name T408
Test name
Test status
Simulation time 8409989479 ps
CPU time 7.72 seconds
Started Mar 28 01:35:51 PM PDT 24
Finished Mar 28 01:35:58 PM PDT 24
Peak memory 204112 kb
Host smart-a7a2eb38-c474-46a7-9d7f-48b04c85d760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41312
75393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.4131275393
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.3764976489
Short name T941
Test name
Test status
Simulation time 32251731 ps
CPU time 0.67 seconds
Started Mar 28 01:35:52 PM PDT 24
Finished Mar 28 01:35:53 PM PDT 24
Peak memory 204044 kb
Host smart-bdc460b8-a826-4e65-8f49-e695bae5e0c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37649
76489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.3764976489
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.2612732360
Short name T512
Test name
Test status
Simulation time 8401502416 ps
CPU time 8.25 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:35:59 PM PDT 24
Peak memory 204084 kb
Host smart-8184383d-63af-451e-ac56-348c6e5a97a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26127
32360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2612732360
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.2190301908
Short name T717
Test name
Test status
Simulation time 8410537396 ps
CPU time 7.25 seconds
Started Mar 28 01:35:52 PM PDT 24
Finished Mar 28 01:36:00 PM PDT 24
Peak memory 204092 kb
Host smart-05719020-6add-4d30-a39b-cc2a3ffeb130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21903
01908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.2190301908
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.3800953560
Short name T524
Test name
Test status
Simulation time 8365350854 ps
CPU time 8.27 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:35:58 PM PDT 24
Peak memory 204096 kb
Host smart-4986253f-0e5c-468a-9077-37b010ca2c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38009
53560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.3800953560
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2762460894
Short name T83
Test name
Test status
Simulation time 8355060261 ps
CPU time 7.61 seconds
Started Mar 28 01:35:51 PM PDT 24
Finished Mar 28 01:35:59 PM PDT 24
Peak memory 204108 kb
Host smart-c966aa12-6bfa-4e25-91af-3d469d153499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27624
60894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2762460894
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1670166947
Short name T176
Test name
Test status
Simulation time 8403776610 ps
CPU time 7.98 seconds
Started Mar 28 01:35:51 PM PDT 24
Finished Mar 28 01:35:59 PM PDT 24
Peak memory 204088 kb
Host smart-3980afc3-6ecb-4b62-8aa5-276213511d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16701
66947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1670166947
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.3976580309
Short name T854
Test name
Test status
Simulation time 8376827315 ps
CPU time 8.32 seconds
Started Mar 28 01:35:52 PM PDT 24
Finished Mar 28 01:36:00 PM PDT 24
Peak memory 204112 kb
Host smart-cfce292f-fb23-49a9-a5e6-9f990868c090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39765
80309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.3976580309
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.in_iso.2388996514
Short name T442
Test name
Test status
Simulation time 8403263716 ps
CPU time 7.84 seconds
Started Mar 28 01:35:48 PM PDT 24
Finished Mar 28 01:35:56 PM PDT 24
Peak memory 204080 kb
Host smart-155b4c02-e5d0-4f58-bcee-b17ee1feb33d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23889
96514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.in_iso.2388996514
Directory /workspace/49.in_iso/latest

Test location /workspace/coverage/default/49.phy_config_usb_ref_disable.4161860920
Short name T431
Test name
Test status
Simulation time 8360555566 ps
CPU time 7 seconds
Started Mar 28 01:35:49 PM PDT 24
Finished Mar 28 01:35:56 PM PDT 24
Peak memory 204072 kb
Host smart-28b2a90e-5451-4400-a3e8-4364d8b82ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41618
60920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.phy_config_usb_ref_disable.4161860920
Directory /workspace/49.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3644306067
Short name T459
Test name
Test status
Simulation time 8366732348 ps
CPU time 8.09 seconds
Started Mar 28 01:35:48 PM PDT 24
Finished Mar 28 01:35:56 PM PDT 24
Peak memory 204052 kb
Host smart-93f1b595-53a9-4c6f-962d-b6dab29fc625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36443
06067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3644306067
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_enable.3382981987
Short name T656
Test name
Test status
Simulation time 8372245344 ps
CPU time 7.45 seconds
Started Mar 28 01:35:52 PM PDT 24
Finished Mar 28 01:36:00 PM PDT 24
Peak memory 204128 kb
Host smart-1c77cf24-fd88-4f2a-8456-845197b0c712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33829
81987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.3382981987
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.1202258096
Short name T560
Test name
Test status
Simulation time 54751902 ps
CPU time 1.56 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:35:51 PM PDT 24
Peak memory 204160 kb
Host smart-e91d893c-12c6-4bb7-b3cd-e096764edddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12022
58096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.1202258096
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.820197852
Short name T198
Test name
Test status
Simulation time 8357874437 ps
CPU time 8.35 seconds
Started Mar 28 01:35:47 PM PDT 24
Finished Mar 28 01:35:55 PM PDT 24
Peak memory 204060 kb
Host smart-c11f2883-50fa-4add-817b-b8b0bca7be0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82019
7852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.820197852
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.2362468074
Short name T887
Test name
Test status
Simulation time 8404456702 ps
CPU time 9.45 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:35:59 PM PDT 24
Peak memory 204048 kb
Host smart-e18d98b0-81cb-43b5-bb1e-7e1c46fe0fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23624
68074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.2362468074
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.1860251596
Short name T539
Test name
Test status
Simulation time 8405468330 ps
CPU time 7.43 seconds
Started Mar 28 01:35:49 PM PDT 24
Finished Mar 28 01:35:56 PM PDT 24
Peak memory 204028 kb
Host smart-ee7bedf1-9440-400f-baff-6bd40c0b6dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18602
51596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.1860251596
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3178474549
Short name T711
Test name
Test status
Simulation time 8366428035 ps
CPU time 8.17 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:35:58 PM PDT 24
Peak memory 203996 kb
Host smart-d4f8116d-c717-4761-9f67-0d93f48f3549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31784
74549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3178474549
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2397803417
Short name T354
Test name
Test status
Simulation time 8423033971 ps
CPU time 8.84 seconds
Started Mar 28 01:35:49 PM PDT 24
Finished Mar 28 01:35:58 PM PDT 24
Peak memory 203900 kb
Host smart-ba2b6705-c919-44f3-b935-39ceb9117c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23978
03417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2397803417
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1835773622
Short name T471
Test name
Test status
Simulation time 8403462944 ps
CPU time 8.05 seconds
Started Mar 28 01:35:47 PM PDT 24
Finished Mar 28 01:35:55 PM PDT 24
Peak memory 204060 kb
Host smart-8691b4ba-fda6-42fe-a5cc-51a9d9810d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18357
73622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1835773622
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.3811446529
Short name T318
Test name
Test status
Simulation time 8397632732 ps
CPU time 9.01 seconds
Started Mar 28 01:35:49 PM PDT 24
Finished Mar 28 01:35:58 PM PDT 24
Peak memory 203576 kb
Host smart-0b284853-008e-499e-9890-142d4d47bdba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38114
46529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.3811446529
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.1485904119
Short name T783
Test name
Test status
Simulation time 28509045 ps
CPU time 0.66 seconds
Started Mar 28 01:35:47 PM PDT 24
Finished Mar 28 01:35:48 PM PDT 24
Peak memory 203996 kb
Host smart-930c905d-2923-4bb6-8664-646edf8b79b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14859
04119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.1485904119
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.2106885920
Short name T904
Test name
Test status
Simulation time 15445721310 ps
CPU time 25.88 seconds
Started Mar 28 01:35:46 PM PDT 24
Finished Mar 28 01:36:12 PM PDT 24
Peak memory 204320 kb
Host smart-b3973956-d305-40e3-a094-52387e66ec06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21068
85920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.2106885920
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.2433412851
Short name T962
Test name
Test status
Simulation time 8383046147 ps
CPU time 9.96 seconds
Started Mar 28 01:35:47 PM PDT 24
Finished Mar 28 01:35:57 PM PDT 24
Peak memory 204120 kb
Host smart-b4ca0c44-f0aa-4319-8b02-f305a9411864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24334
12851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.2433412851
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.3806618420
Short name T1013
Test name
Test status
Simulation time 8419385811 ps
CPU time 8.87 seconds
Started Mar 28 01:35:46 PM PDT 24
Finished Mar 28 01:35:55 PM PDT 24
Peak memory 204024 kb
Host smart-c08dffe6-9fe4-4fb9-8456-1ce93289b5e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38066
18420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.3806618420
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.1560348609
Short name T826
Test name
Test status
Simulation time 8408168405 ps
CPU time 9.63 seconds
Started Mar 28 01:35:47 PM PDT 24
Finished Mar 28 01:35:56 PM PDT 24
Peak memory 204124 kb
Host smart-dd4fe712-ddf2-4f1f-87be-2bde58f70d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15603
48609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.1560348609
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.3703340653
Short name T238
Test name
Test status
Simulation time 8358711754 ps
CPU time 7.81 seconds
Started Mar 28 01:35:45 PM PDT 24
Finished Mar 28 01:35:53 PM PDT 24
Peak memory 204060 kb
Host smart-2b9dd603-2ef4-4fb0-a487-9e8f08bd7608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37033
40653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.3703340653
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3093422164
Short name T97
Test name
Test status
Simulation time 8460390543 ps
CPU time 8.41 seconds
Started Mar 28 01:35:52 PM PDT 24
Finished Mar 28 01:36:00 PM PDT 24
Peak memory 204124 kb
Host smart-493771d4-61a3-4f40-bebc-6c035a32e85b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30934
22164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3093422164
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.889079813
Short name T391
Test name
Test status
Simulation time 8391817409 ps
CPU time 7.22 seconds
Started Mar 28 01:35:50 PM PDT 24
Finished Mar 28 01:35:57 PM PDT 24
Peak memory 203996 kb
Host smart-c5b92286-42f3-4c96-a5fc-1e57854feaae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88907
9813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.889079813
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.in_iso.1922442000
Short name T497
Test name
Test status
Simulation time 8369515090 ps
CPU time 8.33 seconds
Started Mar 28 01:32:58 PM PDT 24
Finished Mar 28 01:33:07 PM PDT 24
Peak memory 204120 kb
Host smart-4fa809c2-a291-4f10-a78b-8927272a7f4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19224
42000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.in_iso.1922442000
Directory /workspace/5.in_iso/latest

Test location /workspace/coverage/default/5.phy_config_usb_ref_disable.1492963862
Short name T740
Test name
Test status
Simulation time 8360573690 ps
CPU time 8.38 seconds
Started Mar 28 01:32:56 PM PDT 24
Finished Mar 28 01:33:05 PM PDT 24
Peak memory 204052 kb
Host smart-e70efb84-66b0-4639-8948-3c4762ed50cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14929
63862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.phy_config_usb_ref_disable.1492963862
Directory /workspace/5.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.1069334184
Short name T846
Test name
Test status
Simulation time 8365380182 ps
CPU time 7 seconds
Started Mar 28 01:32:57 PM PDT 24
Finished Mar 28 01:33:05 PM PDT 24
Peak memory 204036 kb
Host smart-2c84b4be-b2af-45df-bb2a-391fd3b3595b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10693
34184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1069334184
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_enable.1282284927
Short name T1022
Test name
Test status
Simulation time 8367686046 ps
CPU time 7.36 seconds
Started Mar 28 01:33:00 PM PDT 24
Finished Mar 28 01:33:09 PM PDT 24
Peak memory 204044 kb
Host smart-40b2f803-cb09-468b-83c1-ee4cba8b634d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12822
84927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.1282284927
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.3499511738
Short name T476
Test name
Test status
Simulation time 116683897 ps
CPU time 1.25 seconds
Started Mar 28 01:32:58 PM PDT 24
Finished Mar 28 01:32:59 PM PDT 24
Peak memory 204224 kb
Host smart-013a7dd1-3e17-4721-a197-2c75c07e323c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34995
11738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.3499511738
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.488000240
Short name T211
Test name
Test status
Simulation time 8358268578 ps
CPU time 7.44 seconds
Started Mar 28 01:33:05 PM PDT 24
Finished Mar 28 01:33:12 PM PDT 24
Peak memory 204036 kb
Host smart-f9c74f9c-e94e-465b-b629-00a2a2faaa0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48800
0240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.488000240
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3155673865
Short name T1038
Test name
Test status
Simulation time 8451734937 ps
CPU time 7.55 seconds
Started Mar 28 01:32:59 PM PDT 24
Finished Mar 28 01:33:06 PM PDT 24
Peak memory 204076 kb
Host smart-138a76dc-d258-4f30-a667-919c2bb384e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31556
73865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3155673865
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.1574523473
Short name T769
Test name
Test status
Simulation time 8412998168 ps
CPU time 7.72 seconds
Started Mar 28 01:33:00 PM PDT 24
Finished Mar 28 01:33:09 PM PDT 24
Peak memory 204096 kb
Host smart-567e77a8-04ba-4c42-86f8-00dd860b5af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15745
23473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.1574523473
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.2752921358
Short name T393
Test name
Test status
Simulation time 8363230718 ps
CPU time 7.52 seconds
Started Mar 28 01:32:56 PM PDT 24
Finished Mar 28 01:33:04 PM PDT 24
Peak memory 204056 kb
Host smart-f00e3414-cfc1-4438-8788-d7cffc985230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27529
21358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.2752921358
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.277755280
Short name T116
Test name
Test status
Simulation time 8430428522 ps
CPU time 8.01 seconds
Started Mar 28 01:32:58 PM PDT 24
Finished Mar 28 01:33:07 PM PDT 24
Peak memory 204060 kb
Host smart-9f1a880c-d497-4a5a-9240-daddc2bf9b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27775
5280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.277755280
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.3872075381
Short name T429
Test name
Test status
Simulation time 8385656062 ps
CPU time 7.55 seconds
Started Mar 28 01:33:04 PM PDT 24
Finished Mar 28 01:33:11 PM PDT 24
Peak memory 204048 kb
Host smart-26960cf0-c589-4d5b-9ad4-7cc968ad1258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38720
75381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.3872075381
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.2920388879
Short name T651
Test name
Test status
Simulation time 8368689063 ps
CPU time 7.06 seconds
Started Mar 28 01:32:59 PM PDT 24
Finished Mar 28 01:33:06 PM PDT 24
Peak memory 204068 kb
Host smart-e318422b-ed98-453c-9da9-3047161a9766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29203
88879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2920388879
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.413320225
Short name T363
Test name
Test status
Simulation time 32752515 ps
CPU time 0.63 seconds
Started Mar 28 01:33:04 PM PDT 24
Finished Mar 28 01:33:05 PM PDT 24
Peak memory 203980 kb
Host smart-bb15d669-cb28-4a0e-94ef-17988fd3b5a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41332
0225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.413320225
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.1812986321
Short name T212
Test name
Test status
Simulation time 22287955461 ps
CPU time 45.25 seconds
Started Mar 28 01:33:00 PM PDT 24
Finished Mar 28 01:33:47 PM PDT 24
Peak memory 204316 kb
Host smart-b30a2e95-e246-4a4c-9082-1cb6abcb630d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18129
86321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.1812986321
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.1806223437
Short name T233
Test name
Test status
Simulation time 8407912203 ps
CPU time 7.39 seconds
Started Mar 28 01:33:00 PM PDT 24
Finished Mar 28 01:33:09 PM PDT 24
Peak memory 204052 kb
Host smart-537e6d4a-4e4e-457a-bbab-4e6b2523359b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18062
23437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.1806223437
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.4269770558
Short name T145
Test name
Test status
Simulation time 8415626979 ps
CPU time 7.5 seconds
Started Mar 28 01:32:58 PM PDT 24
Finished Mar 28 01:33:06 PM PDT 24
Peak memory 204076 kb
Host smart-1ae51f75-2114-4be6-a234-d7a44b3bbc82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42697
70558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.4269770558
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.641940032
Short name T732
Test name
Test status
Simulation time 8371438728 ps
CPU time 7.64 seconds
Started Mar 28 01:32:58 PM PDT 24
Finished Mar 28 01:33:06 PM PDT 24
Peak memory 204084 kb
Host smart-f2647299-4dc8-4e38-a871-0a94e3853b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64194
0032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.641940032
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1639899857
Short name T778
Test name
Test status
Simulation time 8361927726 ps
CPU time 7.25 seconds
Started Mar 28 01:32:59 PM PDT 24
Finished Mar 28 01:33:06 PM PDT 24
Peak memory 204052 kb
Host smart-1a4e78f6-3aa1-413a-9efc-7efba8434274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16398
99857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1639899857
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.2999040238
Short name T977
Test name
Test status
Simulation time 8428148964 ps
CPU time 7.3 seconds
Started Mar 28 01:32:58 PM PDT 24
Finished Mar 28 01:33:05 PM PDT 24
Peak memory 204056 kb
Host smart-b44daf85-1636-489d-8b9b-e5e0b3363194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29990
40238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2999040238
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.1572538457
Short name T411
Test name
Test status
Simulation time 8400176266 ps
CPU time 8.91 seconds
Started Mar 28 01:32:56 PM PDT 24
Finished Mar 28 01:33:05 PM PDT 24
Peak memory 204056 kb
Host smart-818bdde8-8dd6-45bf-bbc3-ce9fc50d425d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15725
38457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.1572538457
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.in_iso.1636376357
Short name T604
Test name
Test status
Simulation time 8405221463 ps
CPU time 8.2 seconds
Started Mar 28 01:33:01 PM PDT 24
Finished Mar 28 01:33:10 PM PDT 24
Peak memory 204120 kb
Host smart-9de48c0b-84d9-4ce9-8a1a-36aedcc1fc2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16363
76357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.in_iso.1636376357
Directory /workspace/6.in_iso/latest

Test location /workspace/coverage/default/6.phy_config_usb_ref_disable.3970665575
Short name T597
Test name
Test status
Simulation time 8363565469 ps
CPU time 7.43 seconds
Started Mar 28 01:33:01 PM PDT 24
Finished Mar 28 01:33:09 PM PDT 24
Peak memory 203900 kb
Host smart-2f02d53f-4b60-4eef-a489-60f3508bd10e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39706
65575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.phy_config_usb_ref_disable.3970665575
Directory /workspace/6.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.882038163
Short name T737
Test name
Test status
Simulation time 8367114850 ps
CPU time 9.55 seconds
Started Mar 28 01:32:59 PM PDT 24
Finished Mar 28 01:33:08 PM PDT 24
Peak memory 204060 kb
Host smart-99a47f62-a11b-4c38-b7c1-4ec3422c712f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88203
8163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.882038163
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_enable.3793672970
Short name T922
Test name
Test status
Simulation time 8369430855 ps
CPU time 7.75 seconds
Started Mar 28 01:32:57 PM PDT 24
Finished Mar 28 01:33:06 PM PDT 24
Peak memory 203988 kb
Host smart-59707073-9757-4856-97c4-00922e9f21c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37936
72970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.3793672970
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.3176121822
Short name T434
Test name
Test status
Simulation time 98103146 ps
CPU time 1.4 seconds
Started Mar 28 01:33:01 PM PDT 24
Finished Mar 28 01:33:03 PM PDT 24
Peak memory 204160 kb
Host smart-c107d1ed-a9c9-4393-83a3-0efe73b1bbc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31761
21822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.3176121822
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.1686865804
Short name T215
Test name
Test status
Simulation time 8361721770 ps
CPU time 8.39 seconds
Started Mar 28 01:33:00 PM PDT 24
Finished Mar 28 01:33:10 PM PDT 24
Peak memory 204028 kb
Host smart-bc2b1144-3d87-4ea5-9cd1-cb49053741e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16868
65804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.1686865804
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2958651515
Short name T1015
Test name
Test status
Simulation time 8422191798 ps
CPU time 7.39 seconds
Started Mar 28 01:32:57 PM PDT 24
Finished Mar 28 01:33:05 PM PDT 24
Peak memory 204024 kb
Host smart-a5c42707-9784-43f3-87ad-48cd11c7a4fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29586
51515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2958651515
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1663713353
Short name T639
Test name
Test status
Simulation time 8408396149 ps
CPU time 7.18 seconds
Started Mar 28 01:32:59 PM PDT 24
Finished Mar 28 01:33:06 PM PDT 24
Peak memory 204028 kb
Host smart-f1c3b929-5657-49a4-9991-156173555b95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16637
13353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1663713353
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.466013173
Short name T569
Test name
Test status
Simulation time 8367404279 ps
CPU time 7.45 seconds
Started Mar 28 01:33:00 PM PDT 24
Finished Mar 28 01:33:09 PM PDT 24
Peak memory 204092 kb
Host smart-21843ffe-56ae-41d0-9887-905f97f7b6f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46601
3173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.466013173
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.2464262756
Short name T1024
Test name
Test status
Simulation time 8428643312 ps
CPU time 7.61 seconds
Started Mar 28 01:32:58 PM PDT 24
Finished Mar 28 01:33:06 PM PDT 24
Peak memory 203764 kb
Host smart-e6d901b5-934a-40f8-90fc-a9a71f3352da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24642
62756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.2464262756
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3280117288
Short name T663
Test name
Test status
Simulation time 8389845672 ps
CPU time 8.08 seconds
Started Mar 28 01:33:00 PM PDT 24
Finished Mar 28 01:33:10 PM PDT 24
Peak memory 204092 kb
Host smart-3b509121-c6d8-40bf-ade0-6eaec8123eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32801
17288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3280117288
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.1440596105
Short name T295
Test name
Test status
Simulation time 8370346642 ps
CPU time 7.44 seconds
Started Mar 28 01:33:04 PM PDT 24
Finished Mar 28 01:33:12 PM PDT 24
Peak memory 204044 kb
Host smart-63e14630-175b-4e66-898e-7ea661aa423d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14405
96105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.1440596105
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.2706908706
Short name T775
Test name
Test status
Simulation time 23591118 ps
CPU time 0.63 seconds
Started Mar 28 01:32:54 PM PDT 24
Finished Mar 28 01:32:55 PM PDT 24
Peak memory 204044 kb
Host smart-5a6e6fee-60db-4b37-986a-71eb04a0d3d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27069
08706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.2706908706
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1630104557
Short name T184
Test name
Test status
Simulation time 15883741673 ps
CPU time 29.72 seconds
Started Mar 28 01:32:58 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 204244 kb
Host smart-b0c00af6-af49-45bd-99f3-34eaedfa04aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16301
04557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1630104557
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.1784396191
Short name T504
Test name
Test status
Simulation time 8390174545 ps
CPU time 7.22 seconds
Started Mar 28 01:33:01 PM PDT 24
Finished Mar 28 01:33:09 PM PDT 24
Peak memory 204116 kb
Host smart-0495401a-121c-49cd-8865-5f0cd0740fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17843
96191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.1784396191
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.519195902
Short name T935
Test name
Test status
Simulation time 8405067908 ps
CPU time 7.17 seconds
Started Mar 28 01:32:59 PM PDT 24
Finished Mar 28 01:33:06 PM PDT 24
Peak memory 204112 kb
Host smart-b5dbf290-6de9-41e1-af97-fcb89ceee6e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51919
5902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.519195902
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.2185724163
Short name T301
Test name
Test status
Simulation time 8370352121 ps
CPU time 8.29 seconds
Started Mar 28 01:33:01 PM PDT 24
Finished Mar 28 01:33:10 PM PDT 24
Peak memory 204088 kb
Host smart-b58e6cb1-471d-410a-801f-4222ba9c30f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21857
24163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.2185724163
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.183679494
Short name T742
Test name
Test status
Simulation time 8354887683 ps
CPU time 7.77 seconds
Started Mar 28 01:32:55 PM PDT 24
Finished Mar 28 01:33:04 PM PDT 24
Peak memory 204052 kb
Host smart-69600506-32ef-4386-8d11-bb33d6d7853f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18367
9494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.183679494
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.671475443
Short name T22
Test name
Test status
Simulation time 8443972607 ps
CPU time 7.6 seconds
Started Mar 28 01:32:59 PM PDT 24
Finished Mar 28 01:33:06 PM PDT 24
Peak memory 204080 kb
Host smart-750ee104-f53a-4d08-8fe3-2ae125421422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67147
5443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.671475443
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.718197775
Short name T945
Test name
Test status
Simulation time 8381604542 ps
CPU time 7.34 seconds
Started Mar 28 01:33:01 PM PDT 24
Finished Mar 28 01:33:09 PM PDT 24
Peak memory 204040 kb
Host smart-65307196-508f-4927-ba32-515279b4e7e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71819
7775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.718197775
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.in_iso.2134743259
Short name T143
Test name
Test status
Simulation time 8428191915 ps
CPU time 8.06 seconds
Started Mar 28 01:33:04 PM PDT 24
Finished Mar 28 01:33:13 PM PDT 24
Peak memory 204052 kb
Host smart-5b709d62-18b8-46c3-b39b-d6350d4e2de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21347
43259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.in_iso.2134743259
Directory /workspace/7.in_iso/latest

Test location /workspace/coverage/default/7.phy_config_usb_ref_disable.1681871926
Short name T716
Test name
Test status
Simulation time 8365376639 ps
CPU time 8.22 seconds
Started Mar 28 01:33:04 PM PDT 24
Finished Mar 28 01:33:13 PM PDT 24
Peak memory 204052 kb
Host smart-95dfb320-270d-4e52-a56d-ca04f7e1b3f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16818
71926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.phy_config_usb_ref_disable.1681871926
Directory /workspace/7.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2158267348
Short name T927
Test name
Test status
Simulation time 8372041226 ps
CPU time 7.52 seconds
Started Mar 28 01:33:00 PM PDT 24
Finished Mar 28 01:33:09 PM PDT 24
Peak memory 204044 kb
Host smart-0307598e-a1ff-4b36-b268-f5ac4001a4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21582
67348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2158267348
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_enable.442184046
Short name T1021
Test name
Test status
Simulation time 8365577416 ps
CPU time 7 seconds
Started Mar 28 01:33:01 PM PDT 24
Finished Mar 28 01:33:09 PM PDT 24
Peak memory 203888 kb
Host smart-141fcf6d-ec92-4067-b028-40ecb24baf00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44218
4046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.442184046
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.3560959094
Short name T232
Test name
Test status
Simulation time 77493970 ps
CPU time 1.99 seconds
Started Mar 28 01:32:57 PM PDT 24
Finished Mar 28 01:33:00 PM PDT 24
Peak memory 204120 kb
Host smart-612fa1c8-704e-4e6e-990c-101579091269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35609
59094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.3560959094
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.1304425035
Short name T206
Test name
Test status
Simulation time 8356640155 ps
CPU time 7.32 seconds
Started Mar 28 01:33:01 PM PDT 24
Finished Mar 28 01:33:09 PM PDT 24
Peak memory 204116 kb
Host smart-3b377920-d17b-4f6a-b263-354b0c89db9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13044
25035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.1304425035
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.2001741820
Short name T810
Test name
Test status
Simulation time 8421740335 ps
CPU time 9.28 seconds
Started Mar 28 01:33:02 PM PDT 24
Finished Mar 28 01:33:12 PM PDT 24
Peak memory 204044 kb
Host smart-c15c96b8-f711-40ed-89f6-b5215ddb4609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20017
41820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2001741820
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.268527093
Short name T892
Test name
Test status
Simulation time 8416249095 ps
CPU time 7.17 seconds
Started Mar 28 01:33:02 PM PDT 24
Finished Mar 28 01:33:09 PM PDT 24
Peak memory 204028 kb
Host smart-2859aefc-9457-433b-bc5e-c4b4b48400ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26852
7093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.268527093
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2493273451
Short name T579
Test name
Test status
Simulation time 8362644230 ps
CPU time 7.81 seconds
Started Mar 28 01:33:01 PM PDT 24
Finished Mar 28 01:33:09 PM PDT 24
Peak memory 204052 kb
Host smart-f66d0560-a283-4021-bcbc-c0bc0d5ed58d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24932
73451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2493273451
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.1987451899
Short name T118
Test name
Test status
Simulation time 8430100112 ps
CPU time 8.31 seconds
Started Mar 28 01:33:03 PM PDT 24
Finished Mar 28 01:33:11 PM PDT 24
Peak memory 204020 kb
Host smart-9a9ff3ca-6e95-4b28-a4f0-2a5e1b2d1f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19874
51899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.1987451899
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2284493884
Short name T550
Test name
Test status
Simulation time 8374080700 ps
CPU time 7.1 seconds
Started Mar 28 01:33:02 PM PDT 24
Finished Mar 28 01:33:09 PM PDT 24
Peak memory 204024 kb
Host smart-23dcfa29-8587-457b-8bad-ec16622de9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22844
93884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2284493884
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.3908151715
Short name T900
Test name
Test status
Simulation time 8380650691 ps
CPU time 7.85 seconds
Started Mar 28 01:33:04 PM PDT 24
Finished Mar 28 01:33:12 PM PDT 24
Peak memory 203900 kb
Host smart-895220b6-8f9f-46df-b84a-eca712d96906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39081
51715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.3908151715
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2427329465
Short name T392
Test name
Test status
Simulation time 24149859 ps
CPU time 0.73 seconds
Started Mar 28 01:33:04 PM PDT 24
Finished Mar 28 01:33:05 PM PDT 24
Peak memory 203884 kb
Host smart-e933c30f-da87-4456-bd5e-22e6d01f4410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24273
29465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2427329465
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.3496377969
Short name T255
Test name
Test status
Simulation time 30556073414 ps
CPU time 61.39 seconds
Started Mar 28 01:33:03 PM PDT 24
Finished Mar 28 01:34:04 PM PDT 24
Peak memory 204316 kb
Host smart-d59c0bf4-5c93-4f18-b884-8fecf1d93de6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34963
77969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.3496377969
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.2440332803
Short name T620
Test name
Test status
Simulation time 8398544578 ps
CPU time 8.48 seconds
Started Mar 28 01:33:03 PM PDT 24
Finished Mar 28 01:33:11 PM PDT 24
Peak memory 204048 kb
Host smart-d39d27c8-314c-4bce-8f17-1ac1bd8f6813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24403
32803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.2440332803
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.1147746905
Short name T883
Test name
Test status
Simulation time 8462662540 ps
CPU time 9.2 seconds
Started Mar 28 01:32:57 PM PDT 24
Finished Mar 28 01:33:07 PM PDT 24
Peak memory 203972 kb
Host smart-31e7e316-222d-4e97-943e-82328b87805a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11477
46905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.1147746905
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.1774852142
Short name T374
Test name
Test status
Simulation time 8405102069 ps
CPU time 7.01 seconds
Started Mar 28 01:32:59 PM PDT 24
Finished Mar 28 01:33:06 PM PDT 24
Peak memory 204084 kb
Host smart-62805cf6-7f9a-4802-bb22-bdc28d8b39b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17748
52142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.1774852142
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.2634087155
Short name T773
Test name
Test status
Simulation time 8360371181 ps
CPU time 7.62 seconds
Started Mar 28 01:32:57 PM PDT 24
Finished Mar 28 01:33:06 PM PDT 24
Peak memory 203880 kb
Host smart-4ab2dfd1-fb40-4db9-aa35-0160600bebaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26340
87155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.2634087155
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.4225787686
Short name T172
Test name
Test status
Simulation time 8450059304 ps
CPU time 7.2 seconds
Started Mar 28 01:33:00 PM PDT 24
Finished Mar 28 01:33:09 PM PDT 24
Peak memory 203988 kb
Host smart-f017729f-a3e6-429b-a141-382de5299bc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42257
87686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.4225787686
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.818719033
Short name T914
Test name
Test status
Simulation time 8365684720 ps
CPU time 7.21 seconds
Started Mar 28 01:32:57 PM PDT 24
Finished Mar 28 01:33:05 PM PDT 24
Peak memory 204080 kb
Host smart-176ddf03-3639-4268-bb2b-a5d95b402e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81871
9033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.818719033
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.in_iso.2795577246
Short name T954
Test name
Test status
Simulation time 8437260954 ps
CPU time 7.17 seconds
Started Mar 28 01:33:19 PM PDT 24
Finished Mar 28 01:33:27 PM PDT 24
Peak memory 204136 kb
Host smart-1e823e89-88c2-49ec-ae7f-f7baa7e1acc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27955
77246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.in_iso.2795577246
Directory /workspace/8.in_iso/latest

Test location /workspace/coverage/default/8.phy_config_usb_ref_disable.3112594016
Short name T825
Test name
Test status
Simulation time 8365111484 ps
CPU time 7.88 seconds
Started Mar 28 01:33:18 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 204144 kb
Host smart-d82f952d-bac5-4e3c-8922-6bcd8ae9f352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31125
94016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.phy_config_usb_ref_disable.3112594016
Directory /workspace/8.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.1704578753
Short name T324
Test name
Test status
Simulation time 8369353151 ps
CPU time 7.37 seconds
Started Mar 28 01:33:02 PM PDT 24
Finished Mar 28 01:33:09 PM PDT 24
Peak memory 204028 kb
Host smart-0510de10-a2ff-49f8-ab34-8e7daa699539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17045
78753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1704578753
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_enable.4215094200
Short name T309
Test name
Test status
Simulation time 8370155112 ps
CPU time 8.02 seconds
Started Mar 28 01:33:12 PM PDT 24
Finished Mar 28 01:33:22 PM PDT 24
Peak memory 204076 kb
Host smart-dbdeb0f3-4520-4ede-a4c4-6f9ed6ce9866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42150
94200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.4215094200
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1152993928
Short name T923
Test name
Test status
Simulation time 43141250 ps
CPU time 1.09 seconds
Started Mar 28 01:33:19 PM PDT 24
Finished Mar 28 01:33:22 PM PDT 24
Peak memory 204300 kb
Host smart-80c44d37-e796-4a1c-85ea-2a053c897777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11529
93928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1152993928
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1709204200
Short name T756
Test name
Test status
Simulation time 8357908013 ps
CPU time 6.9 seconds
Started Mar 28 01:33:18 PM PDT 24
Finished Mar 28 01:33:25 PM PDT 24
Peak memory 204116 kb
Host smart-63033ec6-d2a2-48fc-9325-18c44267f454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17092
04200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1709204200
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.2992198842
Short name T912
Test name
Test status
Simulation time 8435056054 ps
CPU time 8.55 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:32 PM PDT 24
Peak memory 204080 kb
Host smart-0f73e8fa-1c7f-4e4d-aadf-0235974b66b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29921
98842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.2992198842
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.2092158600
Short name T575
Test name
Test status
Simulation time 8410315019 ps
CPU time 7 seconds
Started Mar 28 01:33:16 PM PDT 24
Finished Mar 28 01:33:24 PM PDT 24
Peak memory 204048 kb
Host smart-24bb715d-4020-4b9c-a746-d111c7cf3297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20921
58600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.2092158600
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.2647548660
Short name T88
Test name
Test status
Simulation time 8366658284 ps
CPU time 7.36 seconds
Started Mar 28 01:33:20 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 204056 kb
Host smart-fc69c739-9b6d-48a4-af77-034d69637473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26475
48660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.2647548660
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.3069104108
Short name T132
Test name
Test status
Simulation time 8398914389 ps
CPU time 7.04 seconds
Started Mar 28 01:33:20 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 204052 kb
Host smart-acb882aa-64e8-4360-892d-a57332289542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30691
04108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3069104108
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.1604702925
Short name T358
Test name
Test status
Simulation time 8397361720 ps
CPU time 8.81 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:32 PM PDT 24
Peak memory 204024 kb
Host smart-ff75a6df-e848-412d-9b25-2ff68da0af77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16047
02925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.1604702925
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.368707643
Short name T33
Test name
Test status
Simulation time 8378186342 ps
CPU time 7.01 seconds
Started Mar 28 01:33:18 PM PDT 24
Finished Mar 28 01:33:25 PM PDT 24
Peak memory 204116 kb
Host smart-a9f80bb8-75de-46fc-9784-df162ed19216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36870
7643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.368707643
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.432902358
Short name T492
Test name
Test status
Simulation time 27778421 ps
CPU time 0.64 seconds
Started Mar 28 01:33:18 PM PDT 24
Finished Mar 28 01:33:19 PM PDT 24
Peak memory 204052 kb
Host smart-6819ec82-b5de-4a6d-ab57-095f1177a6df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43290
2358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.432902358
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.428791489
Short name T682
Test name
Test status
Simulation time 21140384126 ps
CPU time 36.3 seconds
Started Mar 28 01:33:19 PM PDT 24
Finished Mar 28 01:33:56 PM PDT 24
Peak memory 204168 kb
Host smart-a7082d69-5ee7-45e2-8404-873f9e010700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42879
1489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.428791489
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.3304819949
Short name T780
Test name
Test status
Simulation time 8370409919 ps
CPU time 7.97 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:31 PM PDT 24
Peak memory 203932 kb
Host smart-94245265-6950-4053-adc6-25b23cc5de3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33048
19949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.3304819949
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.1522980563
Short name T488
Test name
Test status
Simulation time 8374597342 ps
CPU time 7.39 seconds
Started Mar 28 01:33:17 PM PDT 24
Finished Mar 28 01:33:25 PM PDT 24
Peak memory 203984 kb
Host smart-191d1267-18c3-47cc-8c4a-44f21243b1a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15229
80563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1522980563
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.2404918158
Short name T571
Test name
Test status
Simulation time 8409881571 ps
CPU time 7.68 seconds
Started Mar 28 01:33:13 PM PDT 24
Finished Mar 28 01:33:22 PM PDT 24
Peak memory 204044 kb
Host smart-e6250b15-225b-4d1d-88d9-9daac7e55896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24049
18158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.2404918158
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.905236387
Short name T1049
Test name
Test status
Simulation time 8357892679 ps
CPU time 7.98 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:31 PM PDT 24
Peak memory 204024 kb
Host smart-58d911af-c784-4f30-8dc8-077718b198a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90523
6387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.905236387
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.3979496059
Short name T173
Test name
Test status
Simulation time 8401269466 ps
CPU time 6.9 seconds
Started Mar 28 01:32:58 PM PDT 24
Finished Mar 28 01:33:05 PM PDT 24
Peak memory 204076 kb
Host smart-0484f999-8a65-4c18-b838-8021908b64ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39794
96059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.3979496059
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.4159112571
Short name T990
Test name
Test status
Simulation time 8369013139 ps
CPU time 9.43 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:33 PM PDT 24
Peak memory 203988 kb
Host smart-2a2fb634-5900-4edf-adcb-c6b74fd89e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41591
12571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.4159112571
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.in_iso.2487223290
Short name T252
Test name
Test status
Simulation time 8445364667 ps
CPU time 8.26 seconds
Started Mar 28 01:33:18 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 204060 kb
Host smart-899eea61-70d3-4ee8-8399-4ca8995d70c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24872
23290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.in_iso.2487223290
Directory /workspace/9.in_iso/latest

Test location /workspace/coverage/default/9.phy_config_usb_ref_disable.667313034
Short name T686
Test name
Test status
Simulation time 8365453249 ps
CPU time 7.82 seconds
Started Mar 28 01:33:18 PM PDT 24
Finished Mar 28 01:33:27 PM PDT 24
Peak memory 204116 kb
Host smart-b9465ba2-7e50-4e88-b147-268eaad49891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66731
3034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.phy_config_usb_ref_disable.667313034
Directory /workspace/9.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.3766922389
Short name T576
Test name
Test status
Simulation time 8368678119 ps
CPU time 7.47 seconds
Started Mar 28 01:33:17 PM PDT 24
Finished Mar 28 01:33:25 PM PDT 24
Peak memory 204084 kb
Host smart-3ebbdd51-4186-45a0-8631-dc7558187c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37669
22389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.3766922389
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_enable.4040148585
Short name T532
Test name
Test status
Simulation time 8373226910 ps
CPU time 8.63 seconds
Started Mar 28 01:33:18 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 203888 kb
Host smart-9744c3a8-3b6f-4317-8977-3303c5c0846d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40401
48585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.4040148585
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.2532974046
Short name T645
Test name
Test status
Simulation time 58887277 ps
CPU time 1.62 seconds
Started Mar 28 01:33:17 PM PDT 24
Finished Mar 28 01:33:19 PM PDT 24
Peak memory 204164 kb
Host smart-4cb9c7d0-ee3b-45e7-9c3d-0613d84088ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25329
74046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.2532974046
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.2119915069
Short name T882
Test name
Test status
Simulation time 8359273292 ps
CPU time 8.88 seconds
Started Mar 28 01:33:18 PM PDT 24
Finished Mar 28 01:33:27 PM PDT 24
Peak memory 204060 kb
Host smart-4ae8ab91-6faa-495f-95f1-2908aec7cac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21199
15069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.2119915069
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.3049871767
Short name T149
Test name
Test status
Simulation time 8371960526 ps
CPU time 7.96 seconds
Started Mar 28 01:33:17 PM PDT 24
Finished Mar 28 01:33:25 PM PDT 24
Peak memory 204104 kb
Host smart-6695aec5-80eb-45d9-a553-55adce84d5ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30498
71767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3049871767
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3306986154
Short name T1019
Test name
Test status
Simulation time 8413761322 ps
CPU time 7.74 seconds
Started Mar 28 01:33:20 PM PDT 24
Finished Mar 28 01:33:29 PM PDT 24
Peak memory 204144 kb
Host smart-28770d66-a96a-4987-a8a2-c7306e7eecf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33069
86154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3306986154
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.2890863539
Short name T607
Test name
Test status
Simulation time 8369608765 ps
CPU time 7.26 seconds
Started Mar 28 01:33:19 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 204096 kb
Host smart-06e37e91-820e-48d4-b6c4-534c7ae465b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28908
63539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.2890863539
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.2314888773
Short name T138
Test name
Test status
Simulation time 8435687952 ps
CPU time 8.26 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:32 PM PDT 24
Peak memory 204048 kb
Host smart-69e7dd7b-9e5e-4a0d-9969-2e754458dc70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23148
88773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.2314888773
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.183663631
Short name T896
Test name
Test status
Simulation time 8390773522 ps
CPU time 8.58 seconds
Started Mar 28 01:33:17 PM PDT 24
Finished Mar 28 01:33:26 PM PDT 24
Peak memory 204064 kb
Host smart-3073a86c-3d71-4c30-bba0-c66344e4de95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18366
3631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.183663631
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.221009845
Short name T402
Test name
Test status
Simulation time 8386238613 ps
CPU time 6.88 seconds
Started Mar 28 01:33:18 PM PDT 24
Finished Mar 28 01:33:26 PM PDT 24
Peak memory 204072 kb
Host smart-524ccfee-d5d1-4c05-b1cb-8c226ba85d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22100
9845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.221009845
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.3600599933
Short name T474
Test name
Test status
Simulation time 31191845 ps
CPU time 0.63 seconds
Started Mar 28 01:33:17 PM PDT 24
Finished Mar 28 01:33:18 PM PDT 24
Peak memory 204012 kb
Host smart-3d881b26-0270-4e97-9682-1ef11b8f09cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36005
99933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.3600599933
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.219592949
Short name T779
Test name
Test status
Simulation time 22921878659 ps
CPU time 39.86 seconds
Started Mar 28 01:33:18 PM PDT 24
Finished Mar 28 01:34:00 PM PDT 24
Peak memory 204236 kb
Host smart-4a0ea0ad-1d2e-40e1-9e04-0502a0c38417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21959
2949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.219592949
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.3646665638
Short name T401
Test name
Test status
Simulation time 8403445033 ps
CPU time 7.3 seconds
Started Mar 28 01:33:21 PM PDT 24
Finished Mar 28 01:33:31 PM PDT 24
Peak memory 204016 kb
Host smart-8f7465b9-499d-4d0a-9cd3-1509149e0ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36466
65638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.3646665638
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.1129474613
Short name T1067
Test name
Test status
Simulation time 8439455155 ps
CPU time 7.18 seconds
Started Mar 28 01:33:18 PM PDT 24
Finished Mar 28 01:33:26 PM PDT 24
Peak memory 203932 kb
Host smart-d0308c53-e2f8-4eae-bffd-7f828705b95f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11294
74613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1129474613
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.2355382799
Short name T350
Test name
Test status
Simulation time 8374577290 ps
CPU time 8.13 seconds
Started Mar 28 01:33:19 PM PDT 24
Finished Mar 28 01:33:28 PM PDT 24
Peak memory 203904 kb
Host smart-0402ab37-b0a0-4491-a512-beebb0a027b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23553
82799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.2355382799
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.3014258119
Short name T661
Test name
Test status
Simulation time 8355969417 ps
CPU time 7.53 seconds
Started Mar 28 01:33:14 PM PDT 24
Finished Mar 28 01:33:22 PM PDT 24
Peak memory 204068 kb
Host smart-83f6a091-376b-4d9c-b6f1-3089739703a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30142
58119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.3014258119
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.1215743524
Short name T180
Test name
Test status
Simulation time 8437484072 ps
CPU time 7.97 seconds
Started Mar 28 01:33:19 PM PDT 24
Finished Mar 28 01:33:29 PM PDT 24
Peak memory 204088 kb
Host smart-64e7048d-9b8c-4a3e-975e-84d278f4a767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12157
43524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.1215743524
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.2575793246
Short name T768
Test name
Test status
Simulation time 8387501635 ps
CPU time 7.52 seconds
Started Mar 28 01:33:18 PM PDT 24
Finished Mar 28 01:33:27 PM PDT 24
Peak memory 204076 kb
Host smart-6ccdcd1a-0ec9-46e8-aaf7-7063a3912075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25757
93246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.2575793246
Directory /workspace/9.usbdev_stall_priority_over_nak/latest
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