Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3188	1		T1	3		T2	4		T3	4
all_values[1]	3188	1		T1	3		T2	4		T3	4
all_values[2]	3188	1		T1	3		T2	4		T3	4
all_values[3]	3188	1		T1	3		T2	4		T3	4
all_values[4]	3188	1		T1	3		T2	4		T3	4
all_values[5]	3188	1		T1	3		T2	4		T3	4
all_values[6]	3188	1		T1	3		T2	4		T3	4
all_values[7]	3188	1		T1	3		T2	4		T3	4
all_values[8]	3188	1		T1	3		T2	4		T3	4
all_values[9]	3188	1		T1	3		T2	4		T3	4
all_values[10]	3188	1		T1	3		T2	4		T3	4
all_values[11]	3188	1		T1	3		T2	4		T3	4
all_values[12]	3188	1		T1	3		T2	4		T3	4
all_values[13]	3188	1		T1	3		T2	4		T3	4
all_values[14]	3188	1		T1	3		T2	4		T3	4
all_values[15]	3188	1		T1	3		T2	4		T3	4
all_values[16]	3188	1		T1	3		T2	4		T3	4
all_values[17]	3188	1		T1	3		T2	4		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	55082	1		T1	51		T2	68		T3	72
auto[1]	2302	1		T1	3		T2	4		T19	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	55174	1		T1	54		T2	72		T3	72
auto[1]	2210	1		T72	72		T68	133		T69	64

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2356	1		T1	3		T3	4		T17	3
all_values[0]	auto[0]	auto[1]	62	1		T72	5		T68	5		T70	2
all_values[0]	auto[1]	auto[0]	709	1		T2	4		T21	4		T23	3
all_values[0]	auto[1]	auto[1]	61	1		T68	1		T69	5		T70	6
all_values[1]	auto[0]	auto[0]	2750	1		T2	4		T3	4		T17	3
all_values[1]	auto[0]	auto[1]	63	1		T68	2		T69	4		T70	1
all_values[1]	auto[1]	auto[0]	310	1		T1	3		T19	3		T20	3
all_values[1]	auto[1]	auto[1]	65	1		T72	5		T68	6		T70	6
all_values[2]	auto[0]	auto[0]	3058	1		T1	3		T2	4		T3	4
all_values[2]	auto[0]	auto[1]	66	1		T72	1		T68	3		T70	4
all_values[2]	auto[1]	auto[0]	11	1		T69	1		T73	3		T272	2
all_values[2]	auto[1]	auto[1]	53	1		T72	4		T68	5		T70	4
all_values[3]	auto[0]	auto[0]	3058	1		T1	3		T2	4		T3	4
all_values[3]	auto[0]	auto[1]	56	1		T68	3		T69	4		T70	1
all_values[3]	auto[1]	auto[0]	18	1		T69	1		T70	1		T73	1
all_values[3]	auto[1]	auto[1]	56	1		T68	5		T70	4		T73	2
all_values[4]	auto[0]	auto[0]	3045	1		T1	3		T2	4		T3	4
all_values[4]	auto[0]	auto[1]	58	1		T72	3		T68	1		T69	1
all_values[4]	auto[1]	auto[0]	12	1		T273	1		T272	5		T274	1
all_values[4]	auto[1]	auto[1]	73	1		T72	2		T68	7		T69	4
all_values[5]	auto[0]	auto[0]	3060	1		T1	3		T2	4		T3	4
all_values[5]	auto[0]	auto[1]	64	1		T72	2		T68	3		T70	5
all_values[5]	auto[1]	auto[0]	18	1		T69	4		T70	1		T73	1
all_values[5]	auto[1]	auto[1]	46	1		T72	3		T68	5		T70	2
all_values[6]	auto[0]	auto[0]	3056	1		T1	3		T2	4		T3	4
all_values[6]	auto[0]	auto[1]	67	1		T72	1		T68	7		T69	4
all_values[6]	auto[1]	auto[0]	16	1		T69	1		T70	3		T272	1
all_values[6]	auto[1]	auto[1]	49	1		T72	4		T68	1		T70	2
all_values[7]	auto[0]	auto[0]	3056	1		T1	3		T2	4		T3	4
all_values[7]	auto[0]	auto[1]	63	1		T68	3		T69	1		T70	7
all_values[7]	auto[1]	auto[0]	17	1		T72	5		T75	1		T270	1
all_values[7]	auto[1]	auto[1]	52	1		T68	5		T69	3		T70	1
all_values[8]	auto[0]	auto[0]	3047	1		T1	3		T2	4		T3	4
all_values[8]	auto[0]	auto[1]	73	1		T72	1		T68	4		T69	2
all_values[8]	auto[1]	auto[0]	6	1		T72	1		T274	3		T275	1
all_values[8]	auto[1]	auto[1]	62	1		T72	3		T68	4		T69	3
all_values[9]	auto[0]	auto[0]	3043	1		T1	3		T2	4		T3	4
all_values[9]	auto[0]	auto[1]	62	1		T72	4		T68	6		T69	2
all_values[9]	auto[1]	auto[0]	17	1		T72	1		T270	1		T272	4
all_values[9]	auto[1]	auto[1]	66	1		T68	2		T69	3		T70	5
all_values[10]	auto[0]	auto[0]	3052	1		T1	3		T2	4		T3	4
all_values[10]	auto[0]	auto[1]	77	1		T72	5		T68	2		T70	5
all_values[10]	auto[1]	auto[0]	9	1		T68	1		T69	1		T70	1
all_values[10]	auto[1]	auto[1]	50	1		T68	4		T73	5		T74	1
all_values[11]	auto[0]	auto[0]	3067	1		T1	3		T2	4		T3	4
all_values[11]	auto[0]	auto[1]	49	1		T72	3		T68	1		T69	4
all_values[11]	auto[1]	auto[0]	18	1		T72	1		T70	2		T73	2
all_values[11]	auto[1]	auto[1]	54	1		T68	6		T69	1		T73	4
all_values[12]	auto[0]	auto[0]	3053	1		T1	3		T2	4		T3	4
all_values[12]	auto[0]	auto[1]	69	1		T72	4		T68	5		T69	4
all_values[12]	auto[1]	auto[0]	12	1		T70	2		T274	4		T276	4
all_values[12]	auto[1]	auto[1]	54	1		T70	1		T73	3		T75	4
all_values[13]	auto[0]	auto[0]	3046	1		T1	3		T2	4		T3	4
all_values[13]	auto[0]	auto[1]	58	1		T68	2		T70	2		T73	5
all_values[13]	auto[1]	auto[0]	8	1		T69	1		T270	1		T277	1
all_values[13]	auto[1]	auto[1]	76	1		T72	5		T68	6		T69	4
all_values[14]	auto[0]	auto[0]	3051	1		T1	3		T2	4		T3	4
all_values[14]	auto[0]	auto[1]	74	1		T72	4		T68	4		T69	4
all_values[14]	auto[1]	auto[0]	12	1		T70	1		T74	1		T272	1
all_values[14]	auto[1]	auto[1]	51	1		T72	1		T68	3		T69	1
all_values[15]	auto[0]	auto[0]	3050	1		T1	3		T2	4		T3	4
all_values[15]	auto[0]	auto[1]	67	1		T72	3		T68	8		T70	3
all_values[15]	auto[1]	auto[0]	12	1		T72	2		T69	1		T278	2
all_values[15]	auto[1]	auto[1]	59	1		T69	3		T70	5		T73	1
all_values[16]	auto[0]	auto[0]	3055	1		T1	3		T2	4		T3	4
all_values[16]	auto[0]	auto[1]	43	1		T68	2		T70	2		T73	1
all_values[16]	auto[1]	auto[0]	13	1		T68	1		T69	1		T73	1
all_values[16]	auto[1]	auto[1]	77	1		T72	4		T68	4		T69	3
all_values[17]	auto[0]	auto[0]	3047	1		T1	3		T2	4		T3	4
all_values[17]	auto[0]	auto[1]	61	1		T68	2		T69	3		T70	5
all_values[17]	auto[1]	auto[0]	6	1		T70	2		T74	1		T270	1
all_values[17]	auto[1]	auto[1]	74	1		T72	5		T68	6		T69	1