Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3188	1		T1	3		T2	4		T3	4
all_pins[1]	3188	1		T1	3		T2	4		T3	4
all_pins[2]	3188	1		T1	3		T2	4		T3	4
all_pins[3]	3188	1		T1	3		T2	4		T3	4
all_pins[4]	3188	1		T1	3		T2	4		T3	4
all_pins[5]	3188	1		T1	3		T2	4		T3	4
all_pins[6]	3188	1		T1	3		T2	4		T3	4
all_pins[7]	3188	1		T1	3		T2	4		T3	4
all_pins[8]	3188	1		T1	3		T2	4		T3	4
all_pins[9]	3188	1		T1	3		T2	4		T3	4
all_pins[10]	3188	1		T1	3		T2	4		T3	4
all_pins[11]	3188	1		T1	3		T2	4		T3	4
all_pins[12]	3188	1		T1	3		T2	4		T3	4
all_pins[13]	3188	1		T1	3		T2	4		T3	4
all_pins[14]	3188	1		T1	3		T2	4		T3	4
all_pins[15]	3188	1		T1	3		T2	4		T3	4
all_pins[16]	3188	1		T1	3		T2	4		T3	4
all_pins[17]	3188	1		T1	3		T2	4		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	56654	1		T1	53		T2	71		T3	72
values[0x1]	730	1		T1	1		T2	1		T19	1
transitions[0x0=>0x1]	586	1		T1	1		T2	1		T19	1
transitions[0x1=>0x0]	595	1		T1	1		T2	1		T19	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3060	1		T1	3		T2	3		T3	4
all_pins[0]	values[0x1]	128	1		T2	1		T21	1		T89	1
all_pins[0]	transitions[0x0=>0x1]	121	1		T2	1		T21	1		T89	1
all_pins[0]	transitions[0x1=>0x0]	119	1		T1	1		T19	1		T20	1
all_pins[1]	values[0x0]	3062	1		T1	2		T2	4		T3	4
all_pins[1]	values[0x1]	126	1		T1	1		T19	1		T20	1
all_pins[1]	transitions[0x0=>0x1]	118	1		T1	1		T19	1		T20	1
all_pins[1]	transitions[0x1=>0x0]	19	1		T72	2		T75	2		T273	1
all_pins[2]	values[0x0]	3161	1		T1	3		T2	4		T3	4
all_pins[2]	values[0x1]	27	1		T72	3		T68	2		T75	2
all_pins[2]	transitions[0x0=>0x1]	17	1		T72	3		T68	2		T75	1
all_pins[2]	transitions[0x1=>0x0]	18	1		T68	3		T70	2		T73	2
all_pins[3]	values[0x0]	3160	1		T1	3		T2	4		T3	4
all_pins[3]	values[0x1]	28	1		T68	3		T70	2		T73	2
all_pins[3]	transitions[0x0=>0x1]	19	1		T70	2		T73	1		T75	3
all_pins[3]	transitions[0x1=>0x0]	28	1		T72	1		T68	2		T69	2
all_pins[4]	values[0x0]	3151	1		T1	3		T2	4		T3	4
all_pins[4]	values[0x1]	37	1		T72	1		T68	5		T69	2
all_pins[4]	transitions[0x0=>0x1]	31	1		T72	1		T68	4		T69	2
all_pins[4]	transitions[0x1=>0x0]	16	1		T72	2		T70	1		T73	1
all_pins[5]	values[0x0]	3166	1		T1	3		T2	4		T3	4
all_pins[5]	values[0x1]	22	1		T72	2		T68	1		T70	2
all_pins[5]	transitions[0x0=>0x1]	16	1		T68	1		T73	1		T75	1
all_pins[5]	transitions[0x1=>0x0]	22	1		T72	1		T68	1		T74	3
all_pins[6]	values[0x0]	3160	1		T1	3		T2	4		T3	4
all_pins[6]	values[0x1]	28	1		T72	3		T68	1		T70	2
all_pins[6]	transitions[0x0=>0x1]	22	1		T72	3		T68	1		T70	1
all_pins[6]	transitions[0x1=>0x0]	16	1		T68	2		T73	4		T75	1
all_pins[7]	values[0x0]	3166	1		T1	3		T2	4		T3	4
all_pins[7]	values[0x1]	22	1		T68	2		T70	1		T73	4
all_pins[7]	transitions[0x0=>0x1]	12	1		T68	2		T70	1		T73	3
all_pins[7]	transitions[0x1=>0x0]	16	1		T72	1		T68	1		T75	2
all_pins[8]	values[0x0]	3162	1		T1	3		T2	4		T3	4
all_pins[8]	values[0x1]	26	1		T72	1		T68	1		T73	1
all_pins[8]	transitions[0x0=>0x1]	21	1		T72	1		T73	1		T75	3
all_pins[8]	transitions[0x1=>0x0]	35	1		T69	2		T70	3		T73	1
all_pins[9]	values[0x0]	3148	1		T1	3		T2	4		T3	4
all_pins[9]	values[0x1]	40	1		T68	1		T69	2		T70	3
all_pins[9]	transitions[0x0=>0x1]	26	1		T69	2		T70	3		T73	1
all_pins[9]	transitions[0x1=>0x0]	12	1		T68	2		T73	3		T274	1
all_pins[10]	values[0x0]	3162	1		T1	3		T2	4		T3	4
all_pins[10]	values[0x1]	26	1		T68	3		T73	3		T74	1
all_pins[10]	transitions[0x0=>0x1]	18	1		T68	3		T73	3		T74	1
all_pins[10]	transitions[0x1=>0x0]	21	1		T68	1		T73	1		T75	3
all_pins[11]	values[0x0]	3159	1		T1	3		T2	4		T3	4
all_pins[11]	values[0x1]	29	1		T68	1		T73	1		T75	3
all_pins[11]	transitions[0x0=>0x1]	24	1		T68	1		T73	1		T75	2
all_pins[11]	transitions[0x1=>0x0]	29	1		T70	1		T73	1		T74	1
all_pins[12]	values[0x0]	3154	1		T1	3		T2	4		T3	4
all_pins[12]	values[0x1]	34	1		T70	1		T73	1		T75	1
all_pins[12]	transitions[0x0=>0x1]	26	1		T73	1		T75	1		T273	1
all_pins[12]	transitions[0x1=>0x0]	30	1		T72	2		T68	4		T69	3
all_pins[13]	values[0x0]	3150	1		T1	3		T2	4		T3	4
all_pins[13]	values[0x1]	38	1		T72	2		T68	4		T69	3
all_pins[13]	transitions[0x0=>0x1]	32	1		T72	1		T68	3		T69	3
all_pins[13]	transitions[0x1=>0x0]	14	1		T70	1		T75	1		T270	3
all_pins[14]	values[0x0]	3168	1		T1	3		T2	4		T3	4
all_pins[14]	values[0x1]	20	1		T72	1		T68	1		T70	1
all_pins[14]	transitions[0x0=>0x1]	16	1		T72	1		T68	1		T70	1
all_pins[14]	transitions[0x1=>0x0]	27	1		T69	2		T70	3		T73	1
all_pins[15]	values[0x0]	3157	1		T1	3		T2	4		T3	4
all_pins[15]	values[0x1]	31	1		T69	2		T70	3		T73	1
all_pins[15]	transitions[0x0=>0x1]	19	1		T70	1		T73	1		T75	1
all_pins[15]	transitions[0x1=>0x0]	25	1		T72	1		T70	1		T73	1
all_pins[16]	values[0x0]	3151	1		T1	3		T2	4		T3	4
all_pins[16]	values[0x1]	37	1		T72	1		T69	2		T70	3
all_pins[16]	transitions[0x0=>0x1]	32	1		T69	2		T70	3		T75	1
all_pins[16]	transitions[0x1=>0x0]	26	1		T72	2		T68	2		T69	1
all_pins[17]	values[0x0]	3157	1		T1	3		T2	4		T3	4
all_pins[17]	values[0x1]	31	1		T72	3		T68	2		T69	1
all_pins[17]	transitions[0x0=>0x1]	16	1		T72	2		T68	2		T73	2
all_pins[17]	transitions[0x1=>0x0]	122	1		T2	1		T21	1		T89	1