Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	125	1		T72	4		T68	7		T69	4
all_values[1]	125	1		T72	4		T68	7		T69	4
all_values[2]	125	1		T72	4		T68	7		T69	4
all_values[3]	125	1		T72	4		T68	7		T69	4
all_values[4]	125	1		T72	4		T68	7		T69	4
all_values[5]	125	1		T72	4		T68	7		T69	4
all_values[6]	125	1		T72	4		T68	7		T69	4
all_values[7]	125	1		T72	4		T68	7		T69	4
all_values[8]	125	1		T72	4		T68	7		T69	4
all_values[9]	125	1		T72	4		T68	7		T69	4
all_values[10]	125	1		T72	4		T68	7		T69	4
all_values[11]	125	1		T72	4		T68	7		T69	4
all_values[12]	125	1		T72	4		T68	7		T69	4
all_values[13]	125	1		T72	4		T68	7		T69	4
all_values[14]	125	1		T72	4		T68	7		T69	4
all_values[15]	125	1		T72	4		T68	7		T69	4
all_values[16]	125	1		T72	4		T68	7		T69	4
all_values[17]	125	1		T72	4		T68	7		T69	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1271	1		T72	35		T68	80		T69	47
auto[1]	979	1		T72	37		T68	46		T69	25

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	419	1		T72	16		T68	11		T69	23
auto[1]	1831	1		T72	56		T68	115		T69	49

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1321	1		T72	41		T68	60		T69	49
auto[1]	929	1		T72	31		T68	66		T69	23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	17	1		T68	2		T73	2		T74	3
all_values[0]	auto[0]	auto[0]	auto[1]	28	1		T72	1		T68	3		T70	2
all_values[0]	auto[0]	auto[1]	auto[0]	6	1		T274	2		T279	1		T280	3
all_values[0]	auto[0]	auto[1]	auto[1]	23	1		T69	1		T70	2		T73	1
all_values[0]	auto[1]	auto[0]	auto[1]	25	1		T72	3		T68	1		T69	1
all_values[0]	auto[1]	auto[1]	auto[1]	26	1		T68	1		T69	2		T70	2
all_values[1]	auto[0]	auto[0]	auto[0]	14	1		T69	1		T70	1		T73	2
all_values[1]	auto[0]	auto[0]	auto[1]	27	1		T69	1		T73	2		T74	3
all_values[1]	auto[0]	auto[1]	auto[0]	5	1		T277	3		T279	1		T275	1
all_values[1]	auto[0]	auto[1]	auto[1]	25	1		T72	2		T68	1		T70	3
all_values[1]	auto[1]	auto[0]	auto[1]	30	1		T68	2		T69	2		T70	1
all_values[1]	auto[1]	auto[1]	auto[1]	24	1		T72	2		T68	4		T70	2
all_values[2]	auto[0]	auto[0]	auto[0]	17	1		T69	3		T73	3		T272	3
all_values[2]	auto[0]	auto[0]	auto[1]	27	1		T70	2		T73	1		T75	1
all_values[2]	auto[0]	auto[1]	auto[0]	8	1		T69	1		T73	2		T272	1
all_values[2]	auto[0]	auto[1]	auto[1]	19	1		T72	1		T68	2		T70	2
all_values[2]	auto[1]	auto[0]	auto[1]	32	1		T72	2		T68	3		T70	3
all_values[2]	auto[1]	auto[1]	auto[1]	22	1		T72	1		T68	2		T73	1
all_values[3]	auto[0]	auto[0]	auto[0]	21	1		T72	4		T69	1		T70	1
all_values[3]	auto[0]	auto[0]	auto[1]	25	1		T68	2		T69	2		T73	2
all_values[3]	auto[0]	auto[1]	auto[0]	12	1		T70	2		T274	1		T277	2
all_values[3]	auto[0]	auto[1]	auto[1]	20	1		T68	1		T70	1		T73	1
all_values[3]	auto[1]	auto[0]	auto[1]	27	1		T68	3		T70	3		T73	1
all_values[3]	auto[1]	auto[1]	auto[1]	20	1		T68	1		T69	1		T73	2
all_values[4]	auto[0]	auto[0]	auto[0]	9	1		T272	1		T274	2		T276	2
all_values[4]	auto[0]	auto[0]	auto[1]	30	1		T72	1		T70	3		T73	3
all_values[4]	auto[0]	auto[1]	auto[0]	7	1		T273	1		T272	3		T281	1
all_values[4]	auto[0]	auto[1]	auto[1]	27	1		T72	1		T68	2		T69	1
all_values[4]	auto[1]	auto[0]	auto[1]	25	1		T68	2		T69	2		T73	3
all_values[4]	auto[1]	auto[1]	auto[1]	27	1		T72	2		T68	3		T69	1
all_values[5]	auto[0]	auto[0]	auto[0]	21	1		T69	1		T73	1		T75	1
all_values[5]	auto[0]	auto[0]	auto[1]	23	1		T72	1		T68	2		T70	2
all_values[5]	auto[0]	auto[1]	auto[0]	13	1		T69	3		T70	1		T73	1
all_values[5]	auto[0]	auto[1]	auto[1]	20	1		T72	1		T68	2		T70	1
all_values[5]	auto[1]	auto[0]	auto[1]	31	1		T72	2		T68	2		T70	1
all_values[5]	auto[1]	auto[1]	auto[1]	17	1		T68	1		T70	2		T75	1
all_values[6]	auto[0]	auto[0]	auto[0]	16	1		T69	1		T73	1		T273	1
all_values[6]	auto[0]	auto[0]	auto[1]	30	1		T72	2		T68	2		T69	1
all_values[6]	auto[0]	auto[1]	auto[0]	13	1		T70	3		T272	1		T274	3
all_values[6]	auto[0]	auto[1]	auto[1]	17	1		T72	1		T68	1		T73	1
all_values[6]	auto[1]	auto[0]	auto[1]	28	1		T68	4		T69	1		T73	2
all_values[6]	auto[1]	auto[1]	auto[1]	21	1		T72	1		T69	1		T70	3
all_values[7]	auto[0]	auto[0]	auto[0]	18	1		T69	1		T75	1		T270	2
all_values[7]	auto[0]	auto[0]	auto[1]	26	1		T68	1		T70	2		T73	3
all_values[7]	auto[0]	auto[1]	auto[0]	13	1		T72	4		T272	1		T282	3
all_values[7]	auto[0]	auto[1]	auto[1]	19	1		T68	1		T69	2		T75	2
all_values[7]	auto[1]	auto[0]	auto[1]	30	1		T68	3		T69	1		T70	5
all_values[7]	auto[1]	auto[1]	auto[1]	19	1		T68	2		T73	3		T75	1
all_values[8]	auto[0]	auto[0]	auto[0]	9	1		T73	1		T274	2		T281	1
all_values[8]	auto[0]	auto[0]	auto[1]	33	1		T68	1		T70	3		T73	2
all_values[8]	auto[0]	auto[1]	auto[0]	3	1		T72	1		T274	2		-	-
all_values[8]	auto[0]	auto[1]	auto[1]	21	1		T72	1		T68	1		T69	2
all_values[8]	auto[1]	auto[0]	auto[1]	39	1		T72	2		T68	4		T69	2
all_values[8]	auto[1]	auto[1]	auto[1]	20	1		T68	1		T75	2		T273	1
all_values[9]	auto[0]	auto[0]	auto[0]	5	1		T272	1		T274	1		T278	1
all_values[9]	auto[0]	auto[0]	auto[1]	20	1		T72	1		T68	1		T69	1
all_values[9]	auto[0]	auto[1]	auto[0]	13	1		T72	1		T270	1		T272	3
all_values[9]	auto[0]	auto[1]	auto[1]	26	1		T68	1		T69	2		T70	3
all_values[9]	auto[1]	auto[0]	auto[1]	35	1		T72	2		T68	4		T69	1
all_values[9]	auto[1]	auto[1]	auto[1]	26	1		T68	1		T70	1		T73	2
all_values[10]	auto[0]	auto[0]	auto[0]	13	1		T68	2		T69	4		T70	1
all_values[10]	auto[0]	auto[0]	auto[1]	35	1		T72	3		T68	1		T70	2
all_values[10]	auto[0]	auto[1]	auto[0]	7	1		T70	2		T270	2		T279	1
all_values[10]	auto[0]	auto[1]	auto[1]	22	1		T68	1		T73	3		T273	2
all_values[10]	auto[1]	auto[0]	auto[1]	33	1		T72	1		T68	2		T70	2
all_values[10]	auto[1]	auto[1]	auto[1]	15	1		T68	1		T74	1		T270	1
all_values[11]	auto[0]	auto[0]	auto[0]	28	1		T72	1		T68	1		T70	3
all_values[11]	auto[0]	auto[0]	auto[1]	24	1		T72	1		T69	2		T70	1
all_values[11]	auto[0]	auto[1]	auto[0]	13	1		T72	1		T70	1		T73	1
all_values[11]	auto[0]	auto[1]	auto[1]	16	1		T68	2		T69	1		T73	1
all_values[11]	auto[1]	auto[0]	auto[1]	20	1		T68	2		T69	1		T70	2
all_values[11]	auto[1]	auto[1]	auto[1]	24	1		T72	1		T68	2		T73	2
all_values[12]	auto[0]	auto[0]	auto[0]	16	1		T72	1		T68	3		T69	1
all_values[12]	auto[0]	auto[0]	auto[1]	29	1		T72	1		T68	3		T69	2
all_values[12]	auto[0]	auto[1]	auto[0]	7	1		T70	1		T274	2		T276	3
all_values[12]	auto[0]	auto[1]	auto[1]	23	1		T70	1		T73	2		T75	1
all_values[12]	auto[1]	auto[0]	auto[1]	26	1		T72	2		T68	1		T69	1
all_values[12]	auto[1]	auto[1]	auto[1]	24	1		T70	1		T73	2		T75	1
all_values[13]	auto[0]	auto[0]	auto[0]	5	1		T69	1		T277	2		T275	2
all_values[13]	auto[0]	auto[0]	auto[1]	22	1		T68	1		T73	2		T75	1
all_values[13]	auto[0]	auto[1]	auto[0]	8	1		T270	2		T283	1		T275	5
all_values[13]	auto[0]	auto[1]	auto[1]	26	1		T72	1		T68	2		T69	1
all_values[13]	auto[1]	auto[0]	auto[1]	30	1		T68	3		T70	1		T73	1
all_values[13]	auto[1]	auto[1]	auto[1]	34	1		T72	3		T68	1		T69	2
all_values[14]	auto[0]	auto[0]	auto[0]	12	1		T68	1		T73	1		T74	2
all_values[14]	auto[0]	auto[0]	auto[1]	35	1		T72	1		T68	3		T69	3
all_values[14]	auto[0]	auto[1]	auto[0]	10	1		T70	1		T276	1		T284	1
all_values[14]	auto[0]	auto[1]	auto[1]	25	1		T72	1		T68	1		T73	4
all_values[14]	auto[1]	auto[0]	auto[1]	30	1		T72	1		T68	1		T69	1
all_values[14]	auto[1]	auto[1]	auto[1]	13	1		T72	1		T68	1		T70	2
all_values[15]	auto[0]	auto[0]	auto[0]	12	1		T69	2		T270	1		T276	4
all_values[15]	auto[0]	auto[0]	auto[1]	27	1		T72	1		T68	4		T70	1
all_values[15]	auto[0]	auto[1]	auto[0]	8	1		T72	2		T278	1		T280	1
all_values[15]	auto[0]	auto[1]	auto[1]	28	1		T69	1		T70	1		T75	2
all_values[15]	auto[1]	auto[0]	auto[1]	30	1		T68	3		T70	2		T73	2
all_values[15]	auto[1]	auto[1]	auto[1]	20	1		T72	1		T69	1		T70	3
all_values[16]	auto[0]	auto[0]	auto[0]	19	1		T72	1		T68	2		T69	2
all_values[16]	auto[0]	auto[0]	auto[1]	15	1		T68	1		T70	1		T74	2
all_values[16]	auto[0]	auto[1]	auto[0]	8	1		T273	2		T274	3		T279	1
all_values[16]	auto[0]	auto[1]	auto[1]	31	1		T72	2		T68	2		T69	1
all_values[16]	auto[1]	auto[0]	auto[1]	30	1		T68	2		T70	2		T75	2
all_values[16]	auto[1]	auto[1]	auto[1]	22	1		T72	1		T69	1		T73	3
all_values[17]	auto[0]	auto[0]	auto[0]	9	1		T69	1		T73	1		T74	2
all_values[17]	auto[0]	auto[0]	auto[1]	27	1		T68	1		T69	2		T70	3
all_values[17]	auto[0]	auto[1]	auto[0]	4	1		T70	3		T270	1		-	-
all_values[17]	auto[0]	auto[1]	auto[1]	31	1		T72	1		T68	3		T73	2
all_values[17]	auto[1]	auto[0]	auto[1]	26	1		T68	1		T69	1		T70	1
all_values[17]	auto[1]	auto[1]	auto[1]	28	1		T72	3		T68	2		T73	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal