Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.75 96.43 89.16 97.62 50.00 94.13 97.36 96.58


Total test records in report: 1144
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T1084 /workspace/coverage/default/12.usbdev_av_buffer.3069228529 Mar 31 01:47:55 PM PDT 24 Mar 31 01:48:04 PM PDT 24 8367202339 ps
T1085 /workspace/coverage/default/10.usbdev_setup_trans_ignored.1057939277 Mar 31 01:47:36 PM PDT 24 Mar 31 01:47:44 PM PDT 24 8363142347 ps
T211 /workspace/coverage/default/41.usbdev_in_stall.958027665 Mar 31 01:51:59 PM PDT 24 Mar 31 01:52:08 PM PDT 24 8359970161 ps
T1086 /workspace/coverage/default/49.usbdev_in_trans.3801600881 Mar 31 01:52:53 PM PDT 24 Mar 31 01:53:02 PM PDT 24 8387699701 ps
T1087 /workspace/coverage/default/36.usbdev_out_trans_nak.1941400868 Mar 31 01:51:28 PM PDT 24 Mar 31 01:51:36 PM PDT 24 8395461891 ps
T63 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.469977327 Mar 31 12:34:56 PM PDT 24 Mar 31 12:34:57 PM PDT 24 30978054 ps
T65 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2085270432 Mar 31 12:34:59 PM PDT 24 Mar 31 12:34:59 PM PDT 24 40783344 ps
T64 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2242090805 Mar 31 12:35:03 PM PDT 24 Mar 31 12:35:04 PM PDT 24 32781277 ps
T54 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1005544666 Mar 31 12:34:51 PM PDT 24 Mar 31 12:34:54 PM PDT 24 229101309 ps
T55 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.330814106 Mar 31 12:34:45 PM PDT 24 Mar 31 12:34:48 PM PDT 24 246295312 ps
T71 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3265644704 Mar 31 12:35:12 PM PDT 24 Mar 31 12:35:13 PM PDT 24 36740802 ps
T56 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.458291474 Mar 31 12:34:52 PM PDT 24 Mar 31 12:34:53 PM PDT 24 50326375 ps
T101 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1686199188 Mar 31 12:34:52 PM PDT 24 Mar 31 12:34:53 PM PDT 24 35034285 ps
T222 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3375713007 Mar 31 12:34:55 PM PDT 24 Mar 31 12:34:57 PM PDT 24 60952856 ps
T67 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.4101973852 Mar 31 12:34:56 PM PDT 24 Mar 31 12:34:58 PM PDT 24 312109845 ps
T72 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3277132575 Mar 31 12:34:47 PM PDT 24 Mar 31 12:34:49 PM PDT 24 23481955 ps
T102 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.435487594 Mar 31 12:34:55 PM PDT 24 Mar 31 12:34:56 PM PDT 24 51897607 ps
T68 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1171195744 Mar 31 12:35:06 PM PDT 24 Mar 31 12:35:07 PM PDT 24 27166561 ps
T69 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2933576574 Mar 31 12:35:12 PM PDT 24 Mar 31 12:35:13 PM PDT 24 22825752 ps
T70 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.4114800456 Mar 31 12:35:05 PM PDT 24 Mar 31 12:35:06 PM PDT 24 21824887 ps
T103 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1389140865 Mar 31 12:34:59 PM PDT 24 Mar 31 12:35:04 PM PDT 24 429487723 ps
T73 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.475915484 Mar 31 12:35:12 PM PDT 24 Mar 31 12:35:13 PM PDT 24 23989427 ps
T104 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2651509455 Mar 31 12:34:56 PM PDT 24 Mar 31 12:34:58 PM PDT 24 195005652 ps
T241 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1136110420 Mar 31 12:34:56 PM PDT 24 Mar 31 12:34:59 PM PDT 24 275964087 ps
T75 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2020045711 Mar 31 12:35:26 PM PDT 24 Mar 31 12:35:26 PM PDT 24 27034512 ps
T238 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2685435726 Mar 31 12:34:59 PM PDT 24 Mar 31 12:35:01 PM PDT 24 55021852 ps
T239 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1510711694 Mar 31 12:34:59 PM PDT 24 Mar 31 12:35:03 PM PDT 24 447594384 ps
T247 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3433157572 Mar 31 12:34:44 PM PDT 24 Mar 31 12:34:45 PM PDT 24 56714744 ps
T223 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1807239154 Mar 31 12:35:05 PM PDT 24 Mar 31 12:35:06 PM PDT 24 124133449 ps
T226 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.4005839209 Mar 31 12:34:59 PM PDT 24 Mar 31 12:35:02 PM PDT 24 215344562 ps
T259 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.602353124 Mar 31 12:34:58 PM PDT 24 Mar 31 12:34:59 PM PDT 24 36689771 ps
T260 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.4194554133 Mar 31 12:34:57 PM PDT 24 Mar 31 12:34:58 PM PDT 24 36688245 ps
T240 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2643405960 Mar 31 12:34:57 PM PDT 24 Mar 31 12:34:59 PM PDT 24 130186143 ps
T289 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3147019415 Mar 31 12:35:32 PM PDT 24 Mar 31 12:35:35 PM PDT 24 248873418 ps
T232 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3512843459 Mar 31 12:34:50 PM PDT 24 Mar 31 12:34:52 PM PDT 24 52035544 ps
T74 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3278697399 Mar 31 12:34:47 PM PDT 24 Mar 31 12:34:49 PM PDT 24 22872240 ps
T224 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1778494749 Mar 31 12:34:56 PM PDT 24 Mar 31 12:34:58 PM PDT 24 125451722 ps
T273 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3485595215 Mar 31 12:35:09 PM PDT 24 Mar 31 12:35:09 PM PDT 24 24542072 ps
T230 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.4066445624 Mar 31 12:35:01 PM PDT 24 Mar 31 12:35:04 PM PDT 24 218677011 ps
T1088 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1696465976 Mar 31 12:34:58 PM PDT 24 Mar 31 12:35:00 PM PDT 24 87481498 ps
T248 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.638651259 Mar 31 12:34:46 PM PDT 24 Mar 31 12:34:50 PM PDT 24 55588150 ps
T1089 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.398155321 Mar 31 12:35:09 PM PDT 24 Mar 31 12:35:10 PM PDT 24 28518398 ps
T233 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3054229044 Mar 31 12:34:56 PM PDT 24 Mar 31 12:34:57 PM PDT 24 99186389 ps
T249 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.919982722 Mar 31 12:34:53 PM PDT 24 Mar 31 12:34:54 PM PDT 24 59216325 ps
T291 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.577138311 Mar 31 12:34:49 PM PDT 24 Mar 31 12:34:54 PM PDT 24 226957266 ps
T265 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3865401523 Mar 31 12:35:18 PM PDT 24 Mar 31 12:35:20 PM PDT 24 131632420 ps
T60 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3986072847 Mar 31 12:34:52 PM PDT 24 Mar 31 12:34:53 PM PDT 24 49346711 ps
T1090 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1720869111 Mar 31 12:35:07 PM PDT 24 Mar 31 12:35:08 PM PDT 24 36352971 ps
T270 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1829362915 Mar 31 12:35:05 PM PDT 24 Mar 31 12:35:05 PM PDT 24 25087267 ps
T225 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3578228279 Mar 31 12:35:29 PM PDT 24 Mar 31 12:35:30 PM PDT 24 34657650 ps
T266 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.788262928 Mar 31 12:35:12 PM PDT 24 Mar 31 12:35:14 PM PDT 24 149308324 ps
T272 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3279674369 Mar 31 12:35:06 PM PDT 24 Mar 31 12:35:07 PM PDT 24 21249987 ps
T250 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2670179282 Mar 31 12:35:17 PM PDT 24 Mar 31 12:35:17 PM PDT 24 44068526 ps
T274 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3157445130 Mar 31 12:34:46 PM PDT 24 Mar 31 12:34:49 PM PDT 24 25154059 ps
T277 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1882279061 Mar 31 12:34:58 PM PDT 24 Mar 31 12:34:59 PM PDT 24 21814565 ps
T1091 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3837093574 Mar 31 12:34:54 PM PDT 24 Mar 31 12:34:58 PM PDT 24 111713601 ps
T1092 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.448123896 Mar 31 12:34:48 PM PDT 24 Mar 31 12:34:50 PM PDT 24 70228250 ps
T231 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2159672827 Mar 31 12:34:48 PM PDT 24 Mar 31 12:34:52 PM PDT 24 95426868 ps
T61 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2979153933 Mar 31 12:34:43 PM PDT 24 Mar 31 12:34:44 PM PDT 24 28419420 ps
T236 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3982900603 Mar 31 12:34:54 PM PDT 24 Mar 31 12:34:58 PM PDT 24 216178982 ps
T234 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1278304168 Mar 31 12:34:54 PM PDT 24 Mar 31 12:34:57 PM PDT 24 100079707 ps
T267 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2308916229 Mar 31 12:34:49 PM PDT 24 Mar 31 12:34:52 PM PDT 24 150260937 ps
T276 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.921395409 Mar 31 12:35:16 PM PDT 24 Mar 31 12:35:16 PM PDT 24 23994055 ps
T1093 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1632496134 Mar 31 12:34:51 PM PDT 24 Mar 31 12:34:53 PM PDT 24 123738412 ps
T281 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2400159378 Mar 31 12:35:06 PM PDT 24 Mar 31 12:35:07 PM PDT 24 24031606 ps
T278 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3973643553 Mar 31 12:35:06 PM PDT 24 Mar 31 12:35:07 PM PDT 24 31197719 ps
T288 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3074279044 Mar 31 12:34:56 PM PDT 24 Mar 31 12:34:58 PM PDT 24 107508859 ps
T1094 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1226390827 Mar 31 12:34:44 PM PDT 24 Mar 31 12:34:46 PM PDT 24 119304910 ps
T268 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.392504213 Mar 31 12:34:54 PM PDT 24 Mar 31 12:34:56 PM PDT 24 174772369 ps
T251 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.4166611211 Mar 31 12:34:58 PM PDT 24 Mar 31 12:34:59 PM PDT 24 27766601 ps
T282 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3575489583 Mar 31 12:35:09 PM PDT 24 Mar 31 12:35:10 PM PDT 24 29514875 ps
T279 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1024743094 Mar 31 12:35:21 PM PDT 24 Mar 31 12:35:22 PM PDT 24 28689865 ps
T1095 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.620487021 Mar 31 12:35:16 PM PDT 24 Mar 31 12:35:18 PM PDT 24 71042198 ps
T252 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1854780671 Mar 31 12:34:49 PM PDT 24 Mar 31 12:34:52 PM PDT 24 67382050 ps
T1096 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.166190781 Mar 31 12:34:54 PM PDT 24 Mar 31 12:34:55 PM PDT 24 104764564 ps
T1097 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1246928725 Mar 31 12:35:08 PM PDT 24 Mar 31 12:35:10 PM PDT 24 70028808 ps
T269 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3638824651 Mar 31 12:34:56 PM PDT 24 Mar 31 12:34:58 PM PDT 24 134136002 ps
T1098 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3331528750 Mar 31 12:35:17 PM PDT 24 Mar 31 12:35:20 PM PDT 24 80894732 ps
T1099 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2498516234 Mar 31 12:34:57 PM PDT 24 Mar 31 12:34:59 PM PDT 24 61368715 ps
T1100 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.401798110 Mar 31 12:35:01 PM PDT 24 Mar 31 12:35:04 PM PDT 24 169430187 ps
T235 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.403966000 Mar 31 12:34:56 PM PDT 24 Mar 31 12:34:58 PM PDT 24 59780997 ps
T271 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1301504473 Mar 31 12:34:49 PM PDT 24 Mar 31 12:34:52 PM PDT 24 152804674 ps
T253 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.4059646848 Mar 31 12:34:51 PM PDT 24 Mar 31 12:34:59 PM PDT 24 286493042 ps
T1101 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2758178544 Mar 31 12:34:53 PM PDT 24 Mar 31 12:34:55 PM PDT 24 54161946 ps
T1102 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.4124393357 Mar 31 12:34:59 PM PDT 24 Mar 31 12:35:00 PM PDT 24 61641141 ps
T1103 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.258436418 Mar 31 12:34:53 PM PDT 24 Mar 31 12:34:55 PM PDT 24 130303410 ps
T284 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1525727388 Mar 31 12:35:04 PM PDT 24 Mar 31 12:35:05 PM PDT 24 21911881 ps
T292 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2776604002 Mar 31 12:34:46 PM PDT 24 Mar 31 12:34:51 PM PDT 24 290056931 ps
T1104 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1946973371 Mar 31 12:34:52 PM PDT 24 Mar 31 12:34:56 PM PDT 24 204742152 ps
T1105 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2180648031 Mar 31 12:34:45 PM PDT 24 Mar 31 12:34:47 PM PDT 24 127908777 ps
T1106 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4139245496 Mar 31 12:34:50 PM PDT 24 Mar 31 12:34:52 PM PDT 24 58727622 ps
T1107 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.347321073 Mar 31 12:34:56 PM PDT 24 Mar 31 12:34:57 PM PDT 24 72509933 ps
T1108 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.977476672 Mar 31 12:34:41 PM PDT 24 Mar 31 12:34:45 PM PDT 24 152293784 ps
T280 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1891755363 Mar 31 12:35:13 PM PDT 24 Mar 31 12:35:14 PM PDT 24 29742661 ps
T1109 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2900669221 Mar 31 12:35:07 PM PDT 24 Mar 31 12:35:08 PM PDT 24 57229539 ps
T254 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1074542652 Mar 31 12:34:45 PM PDT 24 Mar 31 12:34:50 PM PDT 24 176784431 ps
T1110 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1369187124 Mar 31 12:34:55 PM PDT 24 Mar 31 12:34:57 PM PDT 24 123968762 ps
T1111 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3507584047 Mar 31 12:35:11 PM PDT 24 Mar 31 12:35:12 PM PDT 24 36277677 ps
T1112 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3219539695 Mar 31 12:34:44 PM PDT 24 Mar 31 12:34:48 PM PDT 24 288033644 ps
T1113 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3198284301 Mar 31 12:34:57 PM PDT 24 Mar 31 12:35:00 PM PDT 24 134824690 ps
T290 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3307372135 Mar 31 12:34:44 PM PDT 24 Mar 31 12:34:47 PM PDT 24 123232727 ps
T1114 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2985083821 Mar 31 12:34:41 PM PDT 24 Mar 31 12:34:43 PM PDT 24 119273223 ps
T1115 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2905342233 Mar 31 12:34:53 PM PDT 24 Mar 31 12:34:55 PM PDT 24 113476762 ps
T66 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1504188108 Mar 31 12:34:50 PM PDT 24 Mar 31 12:34:52 PM PDT 24 40969847 ps
T255 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2511129346 Mar 31 12:34:56 PM PDT 24 Mar 31 12:34:57 PM PDT 24 22492716 ps
T1116 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3177537026 Mar 31 12:34:43 PM PDT 24 Mar 31 12:34:46 PM PDT 24 141768753 ps
T1117 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.757402785 Mar 31 12:35:12 PM PDT 24 Mar 31 12:35:14 PM PDT 24 117059741 ps
T1118 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2608410059 Mar 31 12:34:50 PM PDT 24 Mar 31 12:34:52 PM PDT 24 64364867 ps
T256 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3573117998 Mar 31 12:34:46 PM PDT 24 Mar 31 12:34:56 PM PDT 24 284516755 ps
T1119 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1722105244 Mar 31 12:34:48 PM PDT 24 Mar 31 12:34:50 PM PDT 24 42942190 ps
T1120 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.711576196 Mar 31 12:35:11 PM PDT 24 Mar 31 12:35:13 PM PDT 24 61748732 ps
T1121 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1895328421 Mar 31 12:34:59 PM PDT 24 Mar 31 12:35:00 PM PDT 24 123729117 ps
T257 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1689959775 Mar 31 12:34:45 PM PDT 24 Mar 31 12:34:48 PM PDT 24 35606739 ps
T1122 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3628712879 Mar 31 12:34:59 PM PDT 24 Mar 31 12:35:00 PM PDT 24 68618262 ps
T1123 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.231485784 Mar 31 12:34:55 PM PDT 24 Mar 31 12:34:56 PM PDT 24 41053929 ps
T1124 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.40488464 Mar 31 12:34:49 PM PDT 24 Mar 31 12:34:51 PM PDT 24 129117885 ps
T62 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2904285963 Mar 31 12:34:52 PM PDT 24 Mar 31 12:34:53 PM PDT 24 35082683 ps
T1125 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1045803702 Mar 31 12:34:52 PM PDT 24 Mar 31 12:34:54 PM PDT 24 142400230 ps
T1126 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3390345903 Mar 31 12:34:58 PM PDT 24 Mar 31 12:35:00 PM PDT 24 81416484 ps
T285 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.4053959364 Mar 31 12:34:42 PM PDT 24 Mar 31 12:34:44 PM PDT 24 119698642 ps
T258 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1251174975 Mar 31 12:34:43 PM PDT 24 Mar 31 12:34:46 PM PDT 24 143877374 ps
T1127 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1122749785 Mar 31 12:34:50 PM PDT 24 Mar 31 12:34:52 PM PDT 24 59670386 ps
T283 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2187504139 Mar 31 12:35:11 PM PDT 24 Mar 31 12:35:11 PM PDT 24 21496508 ps
T1128 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2627107472 Mar 31 12:34:42 PM PDT 24 Mar 31 12:34:44 PM PDT 24 44229377 ps
T275 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2448185418 Mar 31 12:35:02 PM PDT 24 Mar 31 12:35:03 PM PDT 24 30204804 ps
T1129 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3592507855 Mar 31 12:34:49 PM PDT 24 Mar 31 12:34:50 PM PDT 24 30632551 ps
T286 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2898453214 Mar 31 12:35:06 PM PDT 24 Mar 31 12:35:10 PM PDT 24 455762730 ps
T287 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3813129862 Mar 31 12:34:57 PM PDT 24 Mar 31 12:35:01 PM PDT 24 235279245 ps
T1130 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.58808817 Mar 31 12:34:55 PM PDT 24 Mar 31 12:34:58 PM PDT 24 95976968 ps
T214 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2951602070 Mar 31 12:34:53 PM PDT 24 Mar 31 12:34:54 PM PDT 24 37051943 ps
T1131 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2118683095 Mar 31 12:34:44 PM PDT 24 Mar 31 12:34:46 PM PDT 24 38092360 ps
T1132 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3897353942 Mar 31 12:34:50 PM PDT 24 Mar 31 12:34:53 PM PDT 24 87856595 ps
T1133 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.220678024 Mar 31 12:35:04 PM PDT 24 Mar 31 12:35:05 PM PDT 24 138657267 ps
T1134 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.716371278 Mar 31 12:34:51 PM PDT 24 Mar 31 12:34:52 PM PDT 24 40367246 ps
T1135 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3612110428 Mar 31 12:35:02 PM PDT 24 Mar 31 12:35:03 PM PDT 24 20863415 ps
T1136 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2063796969 Mar 31 12:34:44 PM PDT 24 Mar 31 12:34:48 PM PDT 24 356825104 ps
T1137 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2576161941 Mar 31 12:35:04 PM PDT 24 Mar 31 12:35:04 PM PDT 24 32986549 ps
T1138 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.127438561 Mar 31 12:34:53 PM PDT 24 Mar 31 12:34:55 PM PDT 24 183794144 ps
T1139 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2666965618 Mar 31 12:34:53 PM PDT 24 Mar 31 12:34:55 PM PDT 24 84212093 ps
T1140 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3189476851 Mar 31 12:34:54 PM PDT 24 Mar 31 12:34:57 PM PDT 24 63059588 ps
T1141 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.122877807 Mar 31 12:35:06 PM PDT 24 Mar 31 12:35:09 PM PDT 24 206914752 ps
T1142 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.966715033 Mar 31 12:34:57 PM PDT 24 Mar 31 12:34:58 PM PDT 24 96701002 ps
T1143 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2389334623 Mar 31 12:34:53 PM PDT 24 Mar 31 12:34:55 PM PDT 24 170674204 ps
T1144 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3430022473 Mar 31 12:35:07 PM PDT 24 Mar 31 12:35:09 PM PDT 24 117640287 ps

Test location /workspace/coverage/default/43.usbdev_in_trans.3214676558
Short name T1
Test name
Test status
Simulation time 8427704118 ps
CPU time 8.27 seconds
Started Mar 31 01:52:09 PM PDT 24
Finished Mar 31 01:52:17 PM PDT 24
Peak memory 204128 kb
Host smart-1e5daf9d-a896-4847-8277-73622757a045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32146
76558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3214676558
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.3268560702
Short name T12
Test name
Test status
Simulation time 18573934089 ps
CPU time 30.61 seconds
Started Mar 31 01:51:20 PM PDT 24
Finished Mar 31 01:51:51 PM PDT 24
Peak memory 204232 kb
Host smart-0fc60649-8122-4930-ad14-cf78659e19da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32685
60702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.3268560702
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.475915484
Short name T73
Test name
Test status
Simulation time 23989427 ps
CPU time 0.7 seconds
Started Mar 31 12:35:12 PM PDT 24
Finished Mar 31 12:35:13 PM PDT 24
Peak memory 202492 kb
Host smart-0120c500-3f6f-419a-bdc8-df05da3755bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=475915484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.475915484
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.4101973852
Short name T67
Test name
Test status
Simulation time 312109845 ps
CPU time 2.86 seconds
Started Mar 31 12:34:56 PM PDT 24
Finished Mar 31 12:34:58 PM PDT 24
Peak memory 203100 kb
Host smart-2b962a47-32f9-43f5-be8a-d142680b447c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4101973852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.4101973852
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/38.usbdev_smoke.2114754831
Short name T24
Test name
Test status
Simulation time 8457325645 ps
CPU time 7.27 seconds
Started Mar 31 01:51:41 PM PDT 24
Finished Mar 31 01:51:49 PM PDT 24
Peak memory 204108 kb
Host smart-92c03b85-ce07-4851-9745-98b758c26461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21147
54831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.2114754831
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/1.in_iso.851026292
Short name T18
Test name
Test status
Simulation time 8439576607 ps
CPU time 8.88 seconds
Started Mar 31 01:45:11 PM PDT 24
Finished Mar 31 01:45:20 PM PDT 24
Peak memory 204096 kb
Host smart-9fefc6ab-271e-4838-9ca5-a6c5ebf47d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85102
6292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.in_iso.851026292
Directory /workspace/1.in_iso/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.4114800456
Short name T70
Test name
Test status
Simulation time 21824887 ps
CPU time 0.64 seconds
Started Mar 31 12:35:05 PM PDT 24
Finished Mar 31 12:35:06 PM PDT 24
Peak memory 202448 kb
Host smart-c53965ec-20e7-4651-8d6c-b66940f652cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4114800456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.4114800456
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2810029274
Short name T38
Test name
Test status
Simulation time 24600748 ps
CPU time 0.61 seconds
Started Mar 31 01:50:44 PM PDT 24
Finished Mar 31 01:50:45 PM PDT 24
Peak memory 204096 kb
Host smart-02351af0-a08d-4812-bb86-bd120a3edac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28100
29274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2810029274
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.3517594130
Short name T4
Test name
Test status
Simulation time 8355707752 ps
CPU time 7 seconds
Started Mar 31 01:49:47 PM PDT 24
Finished Mar 31 01:49:55 PM PDT 24
Peak memory 204076 kb
Host smart-926114f5-bfd8-4adc-b27b-f4c80f9852bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35175
94130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.3517594130
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.phy_config_usb_ref_disable.3765399248
Short name T29
Test name
Test status
Simulation time 8363562005 ps
CPU time 7.21 seconds
Started Mar 31 01:51:16 PM PDT 24
Finished Mar 31 01:51:24 PM PDT 24
Peak memory 204080 kb
Host smart-4052a8c1-12a3-4712-b5bb-f8cd4bd29dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37653
99248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.phy_config_usb_ref_disable.3765399248
Directory /workspace/35.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.4066445624
Short name T230
Test name
Test status
Simulation time 218677011 ps
CPU time 2.95 seconds
Started Mar 31 12:35:01 PM PDT 24
Finished Mar 31 12:35:04 PM PDT 24
Peak memory 202960 kb
Host smart-1fca4a6d-c2bb-4c47-a19f-22393b6f80aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4066445624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.4066445624
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.2406871055
Short name T26
Test name
Test status
Simulation time 8442575852 ps
CPU time 7.64 seconds
Started Mar 31 01:46:56 PM PDT 24
Finished Mar 31 01:47:04 PM PDT 24
Peak memory 204144 kb
Host smart-b58b5cdd-86d2-4da1-9dab-fce9a5ead9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24068
71055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.2406871055
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.867071578
Short name T58
Test name
Test status
Simulation time 185277223 ps
CPU time 1.04 seconds
Started Mar 31 01:44:40 PM PDT 24
Finished Mar 31 01:44:42 PM PDT 24
Peak memory 221000 kb
Host smart-b27f3332-f13a-4326-a477-bc4c14e1fc3e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=867071578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.867071578
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2699950462
Short name T22
Test name
Test status
Simulation time 138631621 ps
CPU time 1.46 seconds
Started Mar 31 01:51:23 PM PDT 24
Finished Mar 31 01:51:25 PM PDT 24
Peak memory 204296 kb
Host smart-fd46e85f-24d7-441d-94d9-69175cf1c631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26999
50462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2699950462
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3973643553
Short name T278
Test name
Test status
Simulation time 31197719 ps
CPU time 0.72 seconds
Started Mar 31 12:35:06 PM PDT 24
Finished Mar 31 12:35:07 PM PDT 24
Peak memory 202532 kb
Host smart-71a6d4fe-9156-452f-b447-616b5444a6b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3973643553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3973643553
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2448185418
Short name T275
Test name
Test status
Simulation time 30204804 ps
CPU time 0.67 seconds
Started Mar 31 12:35:02 PM PDT 24
Finished Mar 31 12:35:03 PM PDT 24
Peak memory 202520 kb
Host smart-c3f5522f-fa70-4feb-8382-6f7ad3a6f4c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2448185418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2448185418
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/default/24.usbdev_enable.1880769796
Short name T2
Test name
Test status
Simulation time 8367685723 ps
CPU time 7.85 seconds
Started Mar 31 01:49:46 PM PDT 24
Finished Mar 31 01:49:54 PM PDT 24
Peak memory 204096 kb
Host smart-8be96ef1-4176-4a38-90b8-adcd06be56dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18807
69796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.1880769796
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2979153933
Short name T61
Test name
Test status
Simulation time 28419420 ps
CPU time 0.78 seconds
Started Mar 31 12:34:43 PM PDT 24
Finished Mar 31 12:34:44 PM PDT 24
Peak memory 202796 kb
Host smart-1de82c89-9838-452d-a46f-a41a4da06098
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979153933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2979153933
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3982900603
Short name T236
Test name
Test status
Simulation time 216178982 ps
CPU time 4.2 seconds
Started Mar 31 12:34:54 PM PDT 24
Finished Mar 31 12:34:58 PM PDT 24
Peak memory 203040 kb
Host smart-134ce37b-d5c4-4b4c-8a02-64060033c196
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3982900603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3982900603
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1024743094
Short name T279
Test name
Test status
Simulation time 28689865 ps
CPU time 0.66 seconds
Started Mar 31 12:35:21 PM PDT 24
Finished Mar 31 12:35:22 PM PDT 24
Peak memory 202520 kb
Host smart-6b461ab2-eeed-4efc-82fd-523a311e94dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1024743094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.1024743094
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2898453214
Short name T286
Test name
Test status
Simulation time 455762730 ps
CPU time 4 seconds
Started Mar 31 12:35:06 PM PDT 24
Finished Mar 31 12:35:10 PM PDT 24
Peak memory 203032 kb
Host smart-13851443-f2a0-43d0-972f-b8e85fc2db79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2898453214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2898453214
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.1017599885
Short name T13
Test name
Test status
Simulation time 17015827495 ps
CPU time 25.87 seconds
Started Mar 31 01:47:35 PM PDT 24
Finished Mar 31 01:48:01 PM PDT 24
Peak memory 204304 kb
Host smart-1f681ab1-6bff-465e-8fbc-cf260c10a624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10175
99885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.1017599885
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1807239154
Short name T223
Test name
Test status
Simulation time 124133449 ps
CPU time 1.6 seconds
Started Mar 31 12:35:05 PM PDT 24
Finished Mar 31 12:35:06 PM PDT 24
Peak memory 202956 kb
Host smart-460de03d-9ca4-4499-ad78-daaeac257764
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807239154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_
csr_outstanding.1807239154
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.4053959364
Short name T285
Test name
Test status
Simulation time 119698642 ps
CPU time 2.26 seconds
Started Mar 31 12:34:42 PM PDT 24
Finished Mar 31 12:34:44 PM PDT 24
Peak memory 202996 kb
Host smart-1a73612f-7630-40c7-92ac-91169fe557c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4053959364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.4053959364
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2904285963
Short name T62
Test name
Test status
Simulation time 35082683 ps
CPU time 0.89 seconds
Started Mar 31 12:34:52 PM PDT 24
Finished Mar 31 12:34:53 PM PDT 24
Peak memory 202776 kb
Host smart-ef3b0fa3-e156-43c8-b3d5-2380aab2f61b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904285963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2904285963
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2159672827
Short name T231
Test name
Test status
Simulation time 95426868 ps
CPU time 2.95 seconds
Started Mar 31 12:34:48 PM PDT 24
Finished Mar 31 12:34:52 PM PDT 24
Peak memory 202920 kb
Host smart-0c261b69-d205-4308-8baf-09ec87b6bfb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2159672827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2159672827
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/default/19.usbdev_smoke.251290983
Short name T25
Test name
Test status
Simulation time 8417614897 ps
CPU time 7.52 seconds
Started Mar 31 01:49:03 PM PDT 24
Finished Mar 31 01:49:10 PM PDT 24
Peak memory 204056 kb
Host smart-84e0f735-7f3e-465c-9d17-7ae85886e722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25129
0983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.251290983
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3157445130
Short name T274
Test name
Test status
Simulation time 25154059 ps
CPU time 0.64 seconds
Started Mar 31 12:34:46 PM PDT 24
Finished Mar 31 12:34:49 PM PDT 24
Peak memory 202504 kb
Host smart-55f26d18-4df8-4d7d-8eda-6f533b7836fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3157445130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3157445130
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/default/2.usbdev_smoke.3287049073
Short name T159
Test name
Test status
Simulation time 8478073433 ps
CPU time 7.32 seconds
Started Mar 31 01:45:12 PM PDT 24
Finished Mar 31 01:45:20 PM PDT 24
Peak memory 204132 kb
Host smart-9692ab5a-a4b8-4455-bf4d-658bbe448346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32870
49073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.3287049073
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.4147090008
Short name T644
Test name
Test status
Simulation time 18784756385 ps
CPU time 34.55 seconds
Started Mar 31 01:47:42 PM PDT 24
Finished Mar 31 01:48:17 PM PDT 24
Peak memory 204396 kb
Host smart-77c50c90-59e0-4529-a7be-256e409a5ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41470
90008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.4147090008
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_smoke.3268567008
Short name T184
Test name
Test status
Simulation time 8404049574 ps
CPU time 7.1 seconds
Started Mar 31 01:44:10 PM PDT 24
Finished Mar 31 01:44:17 PM PDT 24
Peak memory 204136 kb
Host smart-2652facf-3623-4911-8ddc-e326a4eab3f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32685
67008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3268567008
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_smoke.484642549
Short name T93
Test name
Test status
Simulation time 8410019378 ps
CPU time 7.67 seconds
Started Mar 31 01:47:33 PM PDT 24
Finished Mar 31 01:47:40 PM PDT 24
Peak memory 204132 kb
Host smart-bc1b67b2-be0f-4818-81ec-225d4ba561ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48464
2549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.484642549
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.340732357
Short name T39
Test name
Test status
Simulation time 25790779 ps
CPU time 0.65 seconds
Started Mar 31 01:48:15 PM PDT 24
Finished Mar 31 01:48:16 PM PDT 24
Peak memory 204124 kb
Host smart-eb6fc6af-7332-4e0a-95ca-26068181caef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34073
2357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.340732357
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_smoke.768938968
Short name T178
Test name
Test status
Simulation time 8425868306 ps
CPU time 7.54 seconds
Started Mar 31 01:48:47 PM PDT 24
Finished Mar 31 01:48:55 PM PDT 24
Peak memory 204104 kb
Host smart-6d079394-b6ff-414a-bda0-f686991cfa42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76893
8968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.768938968
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_smoke.2672705254
Short name T160
Test name
Test status
Simulation time 8454996230 ps
CPU time 9.35 seconds
Started Mar 31 01:49:45 PM PDT 24
Finished Mar 31 01:49:55 PM PDT 24
Peak memory 204032 kb
Host smart-87f7d234-abd9-4657-bff4-161d540dbce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26727
05254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.2672705254
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_smoke.3117282348
Short name T171
Test name
Test status
Simulation time 8409620946 ps
CPU time 8.51 seconds
Started Mar 31 01:49:53 PM PDT 24
Finished Mar 31 01:50:01 PM PDT 24
Peak memory 204128 kb
Host smart-cdd63ab1-78ac-470b-ae88-603fd14d6a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31172
82348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.3117282348
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_smoke.995482582
Short name T140
Test name
Test status
Simulation time 8436481603 ps
CPU time 8.63 seconds
Started Mar 31 01:51:23 PM PDT 24
Finished Mar 31 01:51:33 PM PDT 24
Peak memory 204124 kb
Host smart-68ee69eb-9198-4e5b-bc21-a350bb82e8fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99548
2582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.995482582
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.90089500
Short name T296
Test name
Test status
Simulation time 8373786360 ps
CPU time 7.71 seconds
Started Mar 31 01:44:57 PM PDT 24
Finished Mar 31 01:45:05 PM PDT 24
Peak memory 204132 kb
Host smart-ad439e2e-0a25-4417-819e-8c9678f5c9b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90089
500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.90089500
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2685435726
Short name T238
Test name
Test status
Simulation time 55021852 ps
CPU time 1.68 seconds
Started Mar 31 12:34:59 PM PDT 24
Finished Mar 31 12:35:01 PM PDT 24
Peak memory 211296 kb
Host smart-740bfa96-838d-4429-99b9-f9b13db1dad3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685435726 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.2685435726
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.usbdev_smoke.1307704069
Short name T168
Test name
Test status
Simulation time 8416753073 ps
CPU time 8.03 seconds
Started Mar 31 01:44:39 PM PDT 24
Finished Mar 31 01:44:47 PM PDT 24
Peak memory 204068 kb
Host smart-2fc1eb55-5746-413f-9f95-36351699a890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13077
04069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.1307704069
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_smoke.3311642981
Short name T174
Test name
Test status
Simulation time 8451451444 ps
CPU time 8.25 seconds
Started Mar 31 01:48:06 PM PDT 24
Finished Mar 31 01:48:15 PM PDT 24
Peak memory 204144 kb
Host smart-bb78506b-8f80-4f24-bae2-f849624306c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33116
42981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.3311642981
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.4175837293
Short name T371
Test name
Test status
Simulation time 8361795117 ps
CPU time 8.95 seconds
Started Mar 31 01:48:34 PM PDT 24
Finished Mar 31 01:48:44 PM PDT 24
Peak memory 204096 kb
Host smart-285805ee-0b81-42c9-acf5-29c49c68befb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41758
37293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.4175837293
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.681125209
Short name T177
Test name
Test status
Simulation time 8432635199 ps
CPU time 7.64 seconds
Started Mar 31 01:49:33 PM PDT 24
Finished Mar 31 01:49:41 PM PDT 24
Peak memory 204136 kb
Host smart-308bf7c3-57c8-46c1-a2a7-64ea01f1d3bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68112
5209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.681125209
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3986072847
Short name T60
Test name
Test status
Simulation time 49346711 ps
CPU time 0.85 seconds
Started Mar 31 12:34:52 PM PDT 24
Finished Mar 31 12:34:53 PM PDT 24
Peak memory 202696 kb
Host smart-2830c274-befc-4e7a-af69-24cc26eb6486
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986072847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3986072847
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2951602070
Short name T214
Test name
Test status
Simulation time 37051943 ps
CPU time 0.78 seconds
Started Mar 31 12:34:53 PM PDT 24
Finished Mar 31 12:34:54 PM PDT 24
Peak memory 202528 kb
Host smart-55e4ee30-d1c4-45b3-bd80-53c1567d0270
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951602070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2951602070
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.101883928
Short name T852
Test name
Test status
Simulation time 8362835045 ps
CPU time 7.44 seconds
Started Mar 31 01:44:40 PM PDT 24
Finished Mar 31 01:44:48 PM PDT 24
Peak memory 204108 kb
Host smart-406d6390-b4f3-498d-9791-ea512b98f12c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10188
3928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.101883928
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.772492470
Short name T116
Test name
Test status
Simulation time 8398261079 ps
CPU time 8.17 seconds
Started Mar 31 01:44:28 PM PDT 24
Finished Mar 31 01:44:36 PM PDT 24
Peak memory 204108 kb
Host smart-01c1ab79-237a-4bd7-b7ac-7720231fbf43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77249
2470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.772492470
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.1343806586
Short name T671
Test name
Test status
Simulation time 8425993531 ps
CPU time 7.92 seconds
Started Mar 31 01:44:54 PM PDT 24
Finished Mar 31 01:45:02 PM PDT 24
Peak memory 204132 kb
Host smart-03ab9a2f-dbd6-4f84-bf63-a117e6de8dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13438
06586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.1343806586
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.122689453
Short name T106
Test name
Test status
Simulation time 8412550773 ps
CPU time 8.47 seconds
Started Mar 31 01:44:54 PM PDT 24
Finished Mar 31 01:45:03 PM PDT 24
Peak memory 204096 kb
Host smart-3f93b2e7-369e-47c8-ba4e-487dd2086435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12268
9453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.122689453
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.1943703966
Short name T122
Test name
Test status
Simulation time 8420590669 ps
CPU time 7.19 seconds
Started Mar 31 01:47:33 PM PDT 24
Finished Mar 31 01:47:40 PM PDT 24
Peak memory 204168 kb
Host smart-0e1ad915-456a-4092-add1-6d4a4d7abea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19437
03966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.1943703966
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.687378653
Short name T489
Test name
Test status
Simulation time 8414722952 ps
CPU time 7.12 seconds
Started Mar 31 01:47:44 PM PDT 24
Finished Mar 31 01:47:51 PM PDT 24
Peak memory 204112 kb
Host smart-904d4ca0-2fbf-4a50-9e83-2210fc1b57e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68737
8653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.687378653
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.402249444
Short name T119
Test name
Test status
Simulation time 8427825103 ps
CPU time 7.48 seconds
Started Mar 31 01:48:00 PM PDT 24
Finished Mar 31 01:48:08 PM PDT 24
Peak memory 204132 kb
Host smart-bd0b1dc0-f77d-4633-b011-9aeecb0b916d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40224
9444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.402249444
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.2728558834
Short name T186
Test name
Test status
Simulation time 26860520592 ps
CPU time 47.57 seconds
Started Mar 31 01:48:15 PM PDT 24
Finished Mar 31 01:49:03 PM PDT 24
Peak memory 204304 kb
Host smart-e0d3b87b-f909-4286-9f0b-67414b73d070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27285
58834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.2728558834
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.1892806287
Short name T218
Test name
Test status
Simulation time 8362152998 ps
CPU time 7.5 seconds
Started Mar 31 01:48:19 PM PDT 24
Finished Mar 31 01:48:27 PM PDT 24
Peak memory 204076 kb
Host smart-50d3dbd0-21aa-43f0-9ffb-99aa6faf1f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18928
06287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1892806287
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.2827023065
Short name T1024
Test name
Test status
Simulation time 8415279196 ps
CPU time 7.71 seconds
Started Mar 31 01:48:19 PM PDT 24
Finished Mar 31 01:48:27 PM PDT 24
Peak memory 204104 kb
Host smart-c5739195-d546-48e9-b9dc-6ca6e990575a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28270
23065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.2827023065
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.2036016629
Short name T573
Test name
Test status
Simulation time 8363838374 ps
CPU time 6.96 seconds
Started Mar 31 01:48:37 PM PDT 24
Finished Mar 31 01:48:44 PM PDT 24
Peak memory 204108 kb
Host smart-c0c253ec-d7ba-4c82-8bea-c18084dd07e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20360
16629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.2036016629
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.in_iso.263719764
Short name T304
Test name
Test status
Simulation time 8448375621 ps
CPU time 7.67 seconds
Started Mar 31 01:48:51 PM PDT 24
Finished Mar 31 01:48:59 PM PDT 24
Peak memory 203556 kb
Host smart-a0bdceb4-6aa5-433d-90a4-e5d93eddaa0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26371
9764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.in_iso.263719764
Directory /workspace/16.in_iso/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.1168587444
Short name T127
Test name
Test status
Simulation time 8431180277 ps
CPU time 9.09 seconds
Started Mar 31 01:48:52 PM PDT 24
Finished Mar 31 01:49:02 PM PDT 24
Peak memory 204144 kb
Host smart-b137c28d-d309-4bac-a078-073d68e7b511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11685
87444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.1168587444
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2872771896
Short name T135
Test name
Test status
Simulation time 8402958179 ps
CPU time 9 seconds
Started Mar 31 01:49:03 PM PDT 24
Finished Mar 31 01:49:12 PM PDT 24
Peak memory 204136 kb
Host smart-d544c872-acf2-40e7-ae23-8f60a6661806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28727
71896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2872771896
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.phy_config_usb_ref_disable.3647025008
Short name T10
Test name
Test status
Simulation time 8364216080 ps
CPU time 8.36 seconds
Started Mar 31 01:49:25 PM PDT 24
Finished Mar 31 01:49:33 PM PDT 24
Peak memory 204116 kb
Host smart-5fcc6045-308f-40b0-8473-805f5ae3f2e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36470
25008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.phy_config_usb_ref_disable.3647025008
Directory /workspace/20.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.524924152
Short name T121
Test name
Test status
Simulation time 8410342458 ps
CPU time 7.81 seconds
Started Mar 31 01:50:25 PM PDT 24
Finished Mar 31 01:50:33 PM PDT 24
Peak memory 204196 kb
Host smart-02094f70-831d-401c-8a34-dd0ea1eb029d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52492
4152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.524924152
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.783869230
Short name T209
Test name
Test status
Simulation time 8357324489 ps
CPU time 7.47 seconds
Started Mar 31 01:50:58 PM PDT 24
Finished Mar 31 01:51:05 PM PDT 24
Peak memory 204128 kb
Host smart-21c1133c-1f81-40c1-a2b4-d8c7efaccfc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78386
9230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.783869230
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.1682056237
Short name T201
Test name
Test status
Simulation time 21615571222 ps
CPU time 40.7 seconds
Started Mar 31 01:51:08 PM PDT 24
Finished Mar 31 01:51:49 PM PDT 24
Peak memory 204332 kb
Host smart-b2141bd4-e1c1-494e-8c95-0527ef743e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16820
56237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.1682056237
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.2304606795
Short name T117
Test name
Test status
Simulation time 8407510737 ps
CPU time 9.26 seconds
Started Mar 31 01:51:57 PM PDT 24
Finished Mar 31 01:52:06 PM PDT 24
Peak memory 204100 kb
Host smart-91229a39-827a-4928-80d0-3782783a80a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23046
06795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.2304606795
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.2968106051
Short name T112
Test name
Test status
Simulation time 8418410957 ps
CPU time 7.79 seconds
Started Mar 31 01:52:46 PM PDT 24
Finished Mar 31 01:52:54 PM PDT 24
Peak memory 204128 kb
Host smart-8f0fa4a4-ab89-4b03-a939-02e5a8f88bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29681
06051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.2968106051
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1251174975
Short name T258
Test name
Test status
Simulation time 143877374 ps
CPU time 2.01 seconds
Started Mar 31 12:34:43 PM PDT 24
Finished Mar 31 12:34:46 PM PDT 24
Peak memory 202924 kb
Host smart-8e9254b3-3b47-4123-b4e4-808019cb6913
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251174975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1251174975
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.4059646848
Short name T253
Test name
Test status
Simulation time 286493042 ps
CPU time 6.64 seconds
Started Mar 31 12:34:51 PM PDT 24
Finished Mar 31 12:34:59 PM PDT 24
Peak memory 202960 kb
Host smart-ee7a325b-2a7a-4e5a-bf6d-537fa0bb3e19
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059646848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.4059646848
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2180648031
Short name T1105
Test name
Test status
Simulation time 127908777 ps
CPU time 1.76 seconds
Started Mar 31 12:34:45 PM PDT 24
Finished Mar 31 12:34:47 PM PDT 24
Peak memory 211232 kb
Host smart-31426997-9680-4a45-8b7a-74b8ca59fdaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180648031 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.2180648031
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.638651259
Short name T248
Test name
Test status
Simulation time 55588150 ps
CPU time 0.98 seconds
Started Mar 31 12:34:46 PM PDT 24
Finished Mar 31 12:34:50 PM PDT 24
Peak memory 203024 kb
Host smart-4556f22a-fefb-4e0a-8bc8-45a5d16cb5a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638651259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.638651259
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.966715033
Short name T1142
Test name
Test status
Simulation time 96701002 ps
CPU time 1.44 seconds
Started Mar 31 12:34:57 PM PDT 24
Finished Mar 31 12:34:58 PM PDT 24
Peak memory 202856 kb
Host smart-a5fc44a5-2d39-42cb-ba6a-4ab7a92f644a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=966715033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.966715033
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2063796969
Short name T1136
Test name
Test status
Simulation time 356825104 ps
CPU time 2.63 seconds
Started Mar 31 12:34:44 PM PDT 24
Finished Mar 31 12:34:48 PM PDT 24
Peak memory 202876 kb
Host smart-8d309034-a5a5-4ba9-8029-ed2ed68c42ba
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2063796969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2063796969
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2118683095
Short name T1131
Test name
Test status
Simulation time 38092360 ps
CPU time 0.98 seconds
Started Mar 31 12:34:44 PM PDT 24
Finished Mar 31 12:34:46 PM PDT 24
Peak memory 202896 kb
Host smart-d6d196e0-abf5-4b59-bfe4-43ce94d569ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118683095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_c
sr_outstanding.2118683095
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1632496134
Short name T1093
Test name
Test status
Simulation time 123738412 ps
CPU time 1.87 seconds
Started Mar 31 12:34:51 PM PDT 24
Finished Mar 31 12:34:53 PM PDT 24
Peak memory 202876 kb
Host smart-8d0cd8a6-f2ae-40e8-897b-bba4bd1e0248
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1632496134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1632496134
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1074542652
Short name T254
Test name
Test status
Simulation time 176784431 ps
CPU time 2.18 seconds
Started Mar 31 12:34:45 PM PDT 24
Finished Mar 31 12:34:50 PM PDT 24
Peak memory 202848 kb
Host smart-1bd49800-4a4c-4ba7-8318-f5995cd24fc9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074542652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1074542652
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3177537026
Short name T1116
Test name
Test status
Simulation time 141768753 ps
CPU time 1.7 seconds
Started Mar 31 12:34:43 PM PDT 24
Finished Mar 31 12:34:46 PM PDT 24
Peak memory 211224 kb
Host smart-b588bf78-57ad-4952-b650-7e335e89b5a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177537026 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.3177537026
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1689959775
Short name T257
Test name
Test status
Simulation time 35606739 ps
CPU time 0.99 seconds
Started Mar 31 12:34:45 PM PDT 24
Finished Mar 31 12:34:48 PM PDT 24
Peak memory 202916 kb
Host smart-6ea244e5-448d-45d5-9042-13e642b127d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689959775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1689959775
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2627107472
Short name T1128
Test name
Test status
Simulation time 44229377 ps
CPU time 1.37 seconds
Started Mar 31 12:34:42 PM PDT 24
Finished Mar 31 12:34:44 PM PDT 24
Peak memory 202920 kb
Host smart-419899e1-912c-4571-bb48-69b484c7a358
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2627107472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2627107472
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.977476672
Short name T1108
Test name
Test status
Simulation time 152293784 ps
CPU time 3.99 seconds
Started Mar 31 12:34:41 PM PDT 24
Finished Mar 31 12:34:45 PM PDT 24
Peak memory 202800 kb
Host smart-883eacc9-be48-4be7-96ed-534aa64d8ded
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=977476672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.977476672
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.448123896
Short name T1092
Test name
Test status
Simulation time 70228250 ps
CPU time 1.07 seconds
Started Mar 31 12:34:48 PM PDT 24
Finished Mar 31 12:34:50 PM PDT 24
Peak memory 203060 kb
Host smart-48abe20a-e3ff-480d-a060-387c848eadfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448123896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_cs
r_outstanding.448123896
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3897353942
Short name T1132
Test name
Test status
Simulation time 87856595 ps
CPU time 2.74 seconds
Started Mar 31 12:34:50 PM PDT 24
Finished Mar 31 12:34:53 PM PDT 24
Peak memory 202872 kb
Host smart-f9ba9231-dd50-4667-839f-9533515e1b7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3897353942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3897353942
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.330814106
Short name T55
Test name
Test status
Simulation time 246295312 ps
CPU time 2.62 seconds
Started Mar 31 12:34:45 PM PDT 24
Finished Mar 31 12:34:48 PM PDT 24
Peak memory 202960 kb
Host smart-c63409ea-386c-47d9-a519-113db4e1165b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=330814106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.330814106
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1895328421
Short name T1121
Test name
Test status
Simulation time 123729117 ps
CPU time 1.67 seconds
Started Mar 31 12:34:59 PM PDT 24
Finished Mar 31 12:35:00 PM PDT 24
Peak memory 213940 kb
Host smart-0b588e28-cbdc-469c-a2f2-2ca83ef2d1a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895328421 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.1895328421
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.435487594
Short name T102
Test name
Test status
Simulation time 51897607 ps
CPU time 0.92 seconds
Started Mar 31 12:34:55 PM PDT 24
Finished Mar 31 12:34:56 PM PDT 24
Peak memory 202928 kb
Host smart-00ab26c7-4d1e-475e-acc4-dea82d6872c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435487594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.435487594
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.716371278
Short name T1134
Test name
Test status
Simulation time 40367246 ps
CPU time 1.07 seconds
Started Mar 31 12:34:51 PM PDT 24
Finished Mar 31 12:34:52 PM PDT 24
Peak memory 202988 kb
Host smart-c8a50798-e5ef-42a7-9a4b-cd1bffde7527
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716371278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_c
sr_outstanding.716371278
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1278304168
Short name T234
Test name
Test status
Simulation time 100079707 ps
CPU time 2.95 seconds
Started Mar 31 12:34:54 PM PDT 24
Finished Mar 31 12:34:57 PM PDT 24
Peak memory 202880 kb
Host smart-887dc9e9-0183-453b-95e1-36821521e917
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1278304168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1278304168
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1136110420
Short name T241
Test name
Test status
Simulation time 275964087 ps
CPU time 2.78 seconds
Started Mar 31 12:34:56 PM PDT 24
Finished Mar 31 12:34:59 PM PDT 24
Peak memory 202956 kb
Host smart-8805b9a1-7d5c-4afe-afc7-084e9eb05a99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1136110420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1136110420
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3198284301
Short name T1113
Test name
Test status
Simulation time 134824690 ps
CPU time 2.14 seconds
Started Mar 31 12:34:57 PM PDT 24
Finished Mar 31 12:35:00 PM PDT 24
Peak memory 211256 kb
Host smart-d635e17b-874f-45b6-b9cc-3a94dffedee1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198284301 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.3198284301
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.4124393357
Short name T1102
Test name
Test status
Simulation time 61641141 ps
CPU time 0.91 seconds
Started Mar 31 12:34:59 PM PDT 24
Finished Mar 31 12:35:00 PM PDT 24
Peak memory 203068 kb
Host smart-e9a61507-620e-44cf-a4d4-cd5401b9f45c
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124393357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.4124393357
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3578228279
Short name T225
Test name
Test status
Simulation time 34657650 ps
CPU time 1.01 seconds
Started Mar 31 12:35:29 PM PDT 24
Finished Mar 31 12:35:30 PM PDT 24
Peak memory 202876 kb
Host smart-290c34c2-c5ad-43ed-aca7-fb68758740bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578228279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_
csr_outstanding.3578228279
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.58808817
Short name T1130
Test name
Test status
Simulation time 95976968 ps
CPU time 2.92 seconds
Started Mar 31 12:34:55 PM PDT 24
Finished Mar 31 12:34:58 PM PDT 24
Peak memory 202836 kb
Host smart-76414aff-561b-4c3f-ad95-22db9878e0d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=58808817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.58808817
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3074279044
Short name T288
Test name
Test status
Simulation time 107508859 ps
CPU time 2.12 seconds
Started Mar 31 12:34:56 PM PDT 24
Finished Mar 31 12:34:58 PM PDT 24
Peak memory 202952 kb
Host smart-8977d57e-ea62-4c60-9670-c21c955aeb75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3074279044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.3074279044
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1369187124
Short name T1110
Test name
Test status
Simulation time 123968762 ps
CPU time 1.71 seconds
Started Mar 31 12:34:55 PM PDT 24
Finished Mar 31 12:34:57 PM PDT 24
Peak memory 213492 kb
Host smart-1c059c1b-1fc1-4c84-992f-8404fe5fdf40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369187124 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.1369187124
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.4166611211
Short name T251
Test name
Test status
Simulation time 27766601 ps
CPU time 0.74 seconds
Started Mar 31 12:34:58 PM PDT 24
Finished Mar 31 12:34:59 PM PDT 24
Peak memory 202632 kb
Host smart-11d4fca4-2595-4445-a509-b2198ec5aa75
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166611211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.4166611211
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3612110428
Short name T1135
Test name
Test status
Simulation time 20863415 ps
CPU time 0.64 seconds
Started Mar 31 12:35:02 PM PDT 24
Finished Mar 31 12:35:03 PM PDT 24
Peak memory 202528 kb
Host smart-3ce7ebf8-7953-49bd-97bb-5fa9c23c6472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3612110428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.3612110428
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.392504213
Short name T268
Test name
Test status
Simulation time 174772369 ps
CPU time 1.71 seconds
Started Mar 31 12:34:54 PM PDT 24
Finished Mar 31 12:34:56 PM PDT 24
Peak memory 203056 kb
Host smart-c4f400e0-794f-4ef1-b39d-65bd71931fd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392504213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_c
sr_outstanding.392504213
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.166190781
Short name T1096
Test name
Test status
Simulation time 104764564 ps
CPU time 1.32 seconds
Started Mar 31 12:34:54 PM PDT 24
Finished Mar 31 12:34:55 PM PDT 24
Peak memory 202880 kb
Host smart-224fc537-9790-4d08-9ada-45467da8be2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=166190781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.166190781
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3813129862
Short name T287
Test name
Test status
Simulation time 235279245 ps
CPU time 3.75 seconds
Started Mar 31 12:34:57 PM PDT 24
Finished Mar 31 12:35:01 PM PDT 24
Peak memory 202932 kb
Host smart-f90228b0-3c5d-4769-90e1-75e2cc1da3c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3813129862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.3813129862
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2498516234
Short name T1099
Test name
Test status
Simulation time 61368715 ps
CPU time 2.16 seconds
Started Mar 31 12:34:57 PM PDT 24
Finished Mar 31 12:34:59 PM PDT 24
Peak memory 210996 kb
Host smart-f77d0db1-9277-4cdc-afa9-b1046e561424
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498516234 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.2498516234
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.4194554133
Short name T260
Test name
Test status
Simulation time 36688245 ps
CPU time 0.83 seconds
Started Mar 31 12:34:57 PM PDT 24
Finished Mar 31 12:34:58 PM PDT 24
Peak memory 202664 kb
Host smart-3513b872-4ba6-4259-a201-9dfcfa7568f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194554133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.4194554133
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1882279061
Short name T277
Test name
Test status
Simulation time 21814565 ps
CPU time 0.62 seconds
Started Mar 31 12:34:58 PM PDT 24
Finished Mar 31 12:34:59 PM PDT 24
Peak memory 202608 kb
Host smart-f7ca3d08-03c6-4410-854d-cb436e132683
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1882279061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1882279061
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2242090805
Short name T64
Test name
Test status
Simulation time 32781277 ps
CPU time 1.05 seconds
Started Mar 31 12:35:03 PM PDT 24
Finished Mar 31 12:35:04 PM PDT 24
Peak memory 203164 kb
Host smart-adfbd98f-b682-4611-a465-1914e8d9ff62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242090805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_
csr_outstanding.2242090805
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.403966000
Short name T235
Test name
Test status
Simulation time 59780997 ps
CPU time 1.62 seconds
Started Mar 31 12:34:56 PM PDT 24
Finished Mar 31 12:34:58 PM PDT 24
Peak memory 203036 kb
Host smart-4c460a18-6d55-44ec-9ec7-4a47d0f8721e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=403966000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.403966000
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1720869111
Short name T1090
Test name
Test status
Simulation time 36352971 ps
CPU time 1.1 seconds
Started Mar 31 12:35:07 PM PDT 24
Finished Mar 31 12:35:08 PM PDT 24
Peak memory 211200 kb
Host smart-93040bf8-b4e1-4fda-a94b-601152b1f411
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720869111 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.1720869111
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.398155321
Short name T1089
Test name
Test status
Simulation time 28518398 ps
CPU time 0.8 seconds
Started Mar 31 12:35:09 PM PDT 24
Finished Mar 31 12:35:10 PM PDT 24
Peak memory 202720 kb
Host smart-aaa4f5b1-05e5-40a8-9140-b5bfbb95f10e
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398155321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.398155321
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.711576196
Short name T1120
Test name
Test status
Simulation time 61748732 ps
CPU time 0.95 seconds
Started Mar 31 12:35:11 PM PDT 24
Finished Mar 31 12:35:13 PM PDT 24
Peak memory 202828 kb
Host smart-9b2e2920-2052-4988-bf72-73f08a0cae9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711576196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_c
sr_outstanding.711576196
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.401798110
Short name T1100
Test name
Test status
Simulation time 169430187 ps
CPU time 2.22 seconds
Started Mar 31 12:35:01 PM PDT 24
Finished Mar 31 12:35:04 PM PDT 24
Peak memory 202956 kb
Host smart-8b61fe15-e475-4f66-b6bb-51bd3cd7eb85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=401798110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.401798110
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1510711694
Short name T239
Test name
Test status
Simulation time 447594384 ps
CPU time 4.52 seconds
Started Mar 31 12:34:59 PM PDT 24
Finished Mar 31 12:35:03 PM PDT 24
Peak memory 203036 kb
Host smart-3ec125de-c09d-4c2f-a91a-8077a588222d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1510711694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1510711694
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2670179282
Short name T250
Test name
Test status
Simulation time 44068526 ps
CPU time 0.78 seconds
Started Mar 31 12:35:17 PM PDT 24
Finished Mar 31 12:35:17 PM PDT 24
Peak memory 202576 kb
Host smart-e3eba5a5-034a-4efc-b6a6-11f7df1f8e86
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670179282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2670179282
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.220678024
Short name T1133
Test name
Test status
Simulation time 138657267 ps
CPU time 1.43 seconds
Started Mar 31 12:35:04 PM PDT 24
Finished Mar 31 12:35:05 PM PDT 24
Peak memory 203068 kb
Host smart-536766ef-7a9d-4157-9ea7-076728778246
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220678024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_c
sr_outstanding.220678024
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2643405960
Short name T240
Test name
Test status
Simulation time 130186143 ps
CPU time 1.67 seconds
Started Mar 31 12:34:57 PM PDT 24
Finished Mar 31 12:34:59 PM PDT 24
Peak memory 202892 kb
Host smart-06464273-0a9f-42ea-87a6-c6f86b14d622
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2643405960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2643405960
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1389140865
Short name T103
Test name
Test status
Simulation time 429487723 ps
CPU time 4.59 seconds
Started Mar 31 12:34:59 PM PDT 24
Finished Mar 31 12:35:04 PM PDT 24
Peak memory 203020 kb
Host smart-dac1d5c7-c0b2-4425-a0dc-d55ef5d0a75c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1389140865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1389140865
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3331528750
Short name T1098
Test name
Test status
Simulation time 80894732 ps
CPU time 2.57 seconds
Started Mar 31 12:35:17 PM PDT 24
Finished Mar 31 12:35:20 PM PDT 24
Peak memory 211076 kb
Host smart-2c48cf7c-c971-4fc8-9c58-8d40487b63f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331528750 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.3331528750
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2085270432
Short name T65
Test name
Test status
Simulation time 40783344 ps
CPU time 0.76 seconds
Started Mar 31 12:34:59 PM PDT 24
Finished Mar 31 12:34:59 PM PDT 24
Peak memory 202700 kb
Host smart-41ca36a0-5ef5-406f-a67c-b6c33c32fc9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085270432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2085270432
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.788262928
Short name T266
Test name
Test status
Simulation time 149308324 ps
CPU time 1.6 seconds
Started Mar 31 12:35:12 PM PDT 24
Finished Mar 31 12:35:14 PM PDT 24
Peak memory 202912 kb
Host smart-ee73992d-e5d7-4a83-9a34-11328e3f66b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788262928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_c
sr_outstanding.788262928
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1246928725
Short name T1097
Test name
Test status
Simulation time 70028808 ps
CPU time 1.25 seconds
Started Mar 31 12:35:08 PM PDT 24
Finished Mar 31 12:35:10 PM PDT 24
Peak memory 211236 kb
Host smart-93713eba-347e-42e9-b822-548a7595fe7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246928725 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.1246928725
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.602353124
Short name T259
Test name
Test status
Simulation time 36689771 ps
CPU time 0.77 seconds
Started Mar 31 12:34:58 PM PDT 24
Finished Mar 31 12:34:59 PM PDT 24
Peak memory 202652 kb
Host smart-6a899088-f7ad-4134-a688-86ccd5b6366a
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602353124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.602353124
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3430022473
Short name T1144
Test name
Test status
Simulation time 117640287 ps
CPU time 1.53 seconds
Started Mar 31 12:35:07 PM PDT 24
Finished Mar 31 12:35:09 PM PDT 24
Peak memory 203044 kb
Host smart-d9a26f1b-0e5c-425a-bec6-46f2ef95f7f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430022473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_
csr_outstanding.3430022473
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.4005839209
Short name T226
Test name
Test status
Simulation time 215344562 ps
CPU time 3.11 seconds
Started Mar 31 12:34:59 PM PDT 24
Finished Mar 31 12:35:02 PM PDT 24
Peak memory 203000 kb
Host smart-449df0ee-e91c-4891-a1bc-7ac952f6dfaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4005839209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.4005839209
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.620487021
Short name T1095
Test name
Test status
Simulation time 71042198 ps
CPU time 1.22 seconds
Started Mar 31 12:35:16 PM PDT 24
Finished Mar 31 12:35:18 PM PDT 24
Peak memory 212136 kb
Host smart-c6ea2168-5535-4a97-8ef0-9e0e7e880655
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620487021 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.620487021
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3265644704
Short name T71
Test name
Test status
Simulation time 36740802 ps
CPU time 0.79 seconds
Started Mar 31 12:35:12 PM PDT 24
Finished Mar 31 12:35:13 PM PDT 24
Peak memory 202700 kb
Host smart-2efd4a5c-78b0-4a17-97be-7b7b7b2eddea
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265644704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3265644704
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.757402785
Short name T1117
Test name
Test status
Simulation time 117059741 ps
CPU time 1.76 seconds
Started Mar 31 12:35:12 PM PDT 24
Finished Mar 31 12:35:14 PM PDT 24
Peak memory 203036 kb
Host smart-aca9cc8f-b54e-45ce-8d6b-ba063d4b5b33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=757402785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.757402785
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3147019415
Short name T289
Test name
Test status
Simulation time 248873418 ps
CPU time 2.58 seconds
Started Mar 31 12:35:32 PM PDT 24
Finished Mar 31 12:35:35 PM PDT 24
Peak memory 202980 kb
Host smart-ef81d2a4-4865-4648-a478-36b167793dcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3147019415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3147019415
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3865401523
Short name T265
Test name
Test status
Simulation time 131632420 ps
CPU time 1.63 seconds
Started Mar 31 12:35:18 PM PDT 24
Finished Mar 31 12:35:20 PM PDT 24
Peak memory 214332 kb
Host smart-7076de61-ae21-4704-83e5-0320fb2e586d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865401523 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.3865401523
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3507584047
Short name T1111
Test name
Test status
Simulation time 36277677 ps
CPU time 0.77 seconds
Started Mar 31 12:35:11 PM PDT 24
Finished Mar 31 12:35:12 PM PDT 24
Peak memory 202752 kb
Host smart-edf9a16f-c0b9-4e0b-9ae3-ccf9b72286bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507584047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3507584047
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2900669221
Short name T1109
Test name
Test status
Simulation time 57229539 ps
CPU time 1.32 seconds
Started Mar 31 12:35:07 PM PDT 24
Finished Mar 31 12:35:08 PM PDT 24
Peak memory 202848 kb
Host smart-d25f7dc5-1f17-45cf-82c4-083b99a6ac51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900669221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_
csr_outstanding.2900669221
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.122877807
Short name T1141
Test name
Test status
Simulation time 206914752 ps
CPU time 2.46 seconds
Started Mar 31 12:35:06 PM PDT 24
Finished Mar 31 12:35:09 PM PDT 24
Peak memory 203012 kb
Host smart-5f91ebe8-5225-4c46-9179-aed11b3bff01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=122877807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.122877807
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3219539695
Short name T1112
Test name
Test status
Simulation time 288033644 ps
CPU time 3.3 seconds
Started Mar 31 12:34:44 PM PDT 24
Finished Mar 31 12:34:48 PM PDT 24
Peak memory 202900 kb
Host smart-e90defa6-48e3-4701-abdf-85393acd4352
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219539695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3219539695
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3573117998
Short name T256
Test name
Test status
Simulation time 284516755 ps
CPU time 6.85 seconds
Started Mar 31 12:34:46 PM PDT 24
Finished Mar 31 12:34:56 PM PDT 24
Peak memory 202752 kb
Host smart-7cc1d056-09fe-4f81-b1b1-10f0d69d2591
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573117998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.3573117998
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1504188108
Short name T66
Test name
Test status
Simulation time 40969847 ps
CPU time 0.75 seconds
Started Mar 31 12:34:50 PM PDT 24
Finished Mar 31 12:34:52 PM PDT 24
Peak memory 202604 kb
Host smart-fa12a5ac-b34b-428f-9586-6fbb6c2cefdd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504188108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1504188108
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2985083821
Short name T1114
Test name
Test status
Simulation time 119273223 ps
CPU time 1.78 seconds
Started Mar 31 12:34:41 PM PDT 24
Finished Mar 31 12:34:43 PM PDT 24
Peak memory 211220 kb
Host smart-664f906b-47db-4aa3-b5f2-10e43e03142c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985083821 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.2985083821
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3433157572
Short name T247
Test name
Test status
Simulation time 56714744 ps
CPU time 0.96 seconds
Started Mar 31 12:34:44 PM PDT 24
Finished Mar 31 12:34:45 PM PDT 24
Peak memory 202896 kb
Host smart-060f442d-d637-4ff6-b1fe-e375f131d36f
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433157572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.3433157572
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1854780671
Short name T252
Test name
Test status
Simulation time 67382050 ps
CPU time 1.97 seconds
Started Mar 31 12:34:49 PM PDT 24
Finished Mar 31 12:34:52 PM PDT 24
Peak memory 202916 kb
Host smart-13b19930-8e31-41ff-a8d1-be2625f8436e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1854780671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1854780671
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1226390827
Short name T1094
Test name
Test status
Simulation time 119304910 ps
CPU time 1.52 seconds
Started Mar 31 12:34:44 PM PDT 24
Finished Mar 31 12:34:46 PM PDT 24
Peak memory 202992 kb
Host smart-d6b312f1-502b-4949-9ad8-79c7ef7402c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226390827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c
sr_outstanding.1226390827
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1005544666
Short name T54
Test name
Test status
Simulation time 229101309 ps
CPU time 2.66 seconds
Started Mar 31 12:34:51 PM PDT 24
Finished Mar 31 12:34:54 PM PDT 24
Peak memory 202868 kb
Host smart-0d814739-8f3d-4325-9001-27d66d310d50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1005544666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1005544666
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3307372135
Short name T290
Test name
Test status
Simulation time 123232727 ps
CPU time 2.28 seconds
Started Mar 31 12:34:44 PM PDT 24
Finished Mar 31 12:34:47 PM PDT 24
Peak memory 202824 kb
Host smart-f372af6d-f519-4311-9011-309764ef7f4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3307372135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.3307372135
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1829362915
Short name T270
Test name
Test status
Simulation time 25087267 ps
CPU time 0.61 seconds
Started Mar 31 12:35:05 PM PDT 24
Finished Mar 31 12:35:05 PM PDT 24
Peak memory 202620 kb
Host smart-a00f1be6-95c8-41b4-8ba2-95b22053d52e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1829362915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1829362915
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2400159378
Short name T281
Test name
Test status
Simulation time 24031606 ps
CPU time 0.64 seconds
Started Mar 31 12:35:06 PM PDT 24
Finished Mar 31 12:35:07 PM PDT 24
Peak memory 202584 kb
Host smart-2b668c8a-f4be-4b02-9dc2-3980a5286c40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2400159378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2400159378
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3485595215
Short name T273
Test name
Test status
Simulation time 24542072 ps
CPU time 0.63 seconds
Started Mar 31 12:35:09 PM PDT 24
Finished Mar 31 12:35:09 PM PDT 24
Peak memory 202540 kb
Host smart-13e288e5-a92c-49f9-8c46-a47ef514e787
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3485595215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.3485595215
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3837093574
Short name T1091
Test name
Test status
Simulation time 111713601 ps
CPU time 3.24 seconds
Started Mar 31 12:34:54 PM PDT 24
Finished Mar 31 12:34:58 PM PDT 24
Peak memory 202932 kb
Host smart-f9e46a06-07fd-42b8-82f2-76b9a987f927
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837093574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3837093574
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.258436418
Short name T1103
Test name
Test status
Simulation time 130303410 ps
CPU time 1.66 seconds
Started Mar 31 12:34:53 PM PDT 24
Finished Mar 31 12:34:55 PM PDT 24
Peak memory 211296 kb
Host smart-67e4def6-95a5-4fcc-b193-a47d26b97223
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258436418 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.258436418
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1722105244
Short name T1119
Test name
Test status
Simulation time 42942190 ps
CPU time 0.77 seconds
Started Mar 31 12:34:48 PM PDT 24
Finished Mar 31 12:34:50 PM PDT 24
Peak memory 202664 kb
Host smart-aeb8bc21-c245-41ab-beff-72cc170b5e7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722105244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1722105244
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3277132575
Short name T72
Test name
Test status
Simulation time 23481955 ps
CPU time 0.6 seconds
Started Mar 31 12:34:47 PM PDT 24
Finished Mar 31 12:34:49 PM PDT 24
Peak memory 202520 kb
Host smart-7c5fb9aa-db37-4cc3-99eb-4e46252b18ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3277132575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3277132575
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2389334623
Short name T1143
Test name
Test status
Simulation time 170674204 ps
CPU time 2.12 seconds
Started Mar 31 12:34:53 PM PDT 24
Finished Mar 31 12:34:55 PM PDT 24
Peak memory 202888 kb
Host smart-a9470af4-7391-45d6-9d29-e89e7533128f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2389334623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2389334623
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1696465976
Short name T1088
Test name
Test status
Simulation time 87481498 ps
CPU time 2.2 seconds
Started Mar 31 12:34:58 PM PDT 24
Finished Mar 31 12:35:00 PM PDT 24
Peak memory 202852 kb
Host smart-45781a43-d431-4abb-afee-5a6bd7119f66
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1696465976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.1696465976
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2308916229
Short name T267
Test name
Test status
Simulation time 150260937 ps
CPU time 1.57 seconds
Started Mar 31 12:34:49 PM PDT 24
Finished Mar 31 12:34:52 PM PDT 24
Peak memory 202960 kb
Host smart-19ba8812-4269-45f4-93f2-b2aa3a26342a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308916229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_c
sr_outstanding.2308916229
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2776604002
Short name T292
Test name
Test status
Simulation time 290056931 ps
CPU time 2.47 seconds
Started Mar 31 12:34:46 PM PDT 24
Finished Mar 31 12:34:51 PM PDT 24
Peak memory 202896 kb
Host smart-e24875ea-2e30-474a-8cb5-15441cebb0ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2776604002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2776604002
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1171195744
Short name T68
Test name
Test status
Simulation time 27166561 ps
CPU time 0.63 seconds
Started Mar 31 12:35:06 PM PDT 24
Finished Mar 31 12:35:07 PM PDT 24
Peak memory 202120 kb
Host smart-61a93a44-b2b8-41d4-86d6-54e468393927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1171195744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1171195744
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1525727388
Short name T284
Test name
Test status
Simulation time 21911881 ps
CPU time 0.67 seconds
Started Mar 31 12:35:04 PM PDT 24
Finished Mar 31 12:35:05 PM PDT 24
Peak memory 202448 kb
Host smart-6253c951-593f-4620-91a2-a0dbb23cbe35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1525727388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1525727388
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3575489583
Short name T282
Test name
Test status
Simulation time 29514875 ps
CPU time 0.65 seconds
Started Mar 31 12:35:09 PM PDT 24
Finished Mar 31 12:35:10 PM PDT 24
Peak memory 202532 kb
Host smart-8aecbed6-3366-4857-a1c8-96553e07b5d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3575489583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3575489583
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2020045711
Short name T75
Test name
Test status
Simulation time 27034512 ps
CPU time 0.63 seconds
Started Mar 31 12:35:26 PM PDT 24
Finished Mar 31 12:35:26 PM PDT 24
Peak memory 202500 kb
Host smart-a93f8f02-2d4b-43e8-b6f5-a4484f09a90c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2020045711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2020045711
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1891755363
Short name T280
Test name
Test status
Simulation time 29742661 ps
CPU time 0.68 seconds
Started Mar 31 12:35:13 PM PDT 24
Finished Mar 31 12:35:14 PM PDT 24
Peak memory 202604 kb
Host smart-eec904d4-8e62-495f-8400-91506dcda726
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1891755363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.1891755363
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2651509455
Short name T104
Test name
Test status
Simulation time 195005652 ps
CPU time 2.19 seconds
Started Mar 31 12:34:56 PM PDT 24
Finished Mar 31 12:34:58 PM PDT 24
Peak memory 202972 kb
Host smart-e49316b8-b050-4770-9e2e-96573f36d13a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651509455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2651509455
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.347321073
Short name T1107
Test name
Test status
Simulation time 72509933 ps
CPU time 1.18 seconds
Started Mar 31 12:34:56 PM PDT 24
Finished Mar 31 12:34:57 PM PDT 24
Peak memory 211240 kb
Host smart-ef323bd8-c54d-4010-94ce-f4cdede9ecf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347321073 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.347321073
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3592507855
Short name T1129
Test name
Test status
Simulation time 30632551 ps
CPU time 1.04 seconds
Started Mar 31 12:34:49 PM PDT 24
Finished Mar 31 12:34:50 PM PDT 24
Peak memory 202960 kb
Host smart-1220184d-45cd-46d0-809b-5903c45c6fe6
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592507855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3592507855
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3278697399
Short name T74
Test name
Test status
Simulation time 22872240 ps
CPU time 0.65 seconds
Started Mar 31 12:34:47 PM PDT 24
Finished Mar 31 12:34:49 PM PDT 24
Peak memory 202592 kb
Host smart-4e222b2f-28ea-49ee-a712-98a5e76171b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3278697399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3278697399
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3189476851
Short name T1140
Test name
Test status
Simulation time 63059588 ps
CPU time 2.2 seconds
Started Mar 31 12:34:54 PM PDT 24
Finished Mar 31 12:34:57 PM PDT 24
Peak memory 211092 kb
Host smart-d918e602-7630-44cf-be8b-364d4efdf1c3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3189476851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3189476851
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2666965618
Short name T1139
Test name
Test status
Simulation time 84212093 ps
CPU time 2.25 seconds
Started Mar 31 12:34:53 PM PDT 24
Finished Mar 31 12:34:55 PM PDT 24
Peak memory 202840 kb
Host smart-c4b9e526-0a8c-45c8-bd89-6e45ac39fad8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2666965618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.2666965618
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1045803702
Short name T1125
Test name
Test status
Simulation time 142400230 ps
CPU time 1.5 seconds
Started Mar 31 12:34:52 PM PDT 24
Finished Mar 31 12:34:54 PM PDT 24
Peak memory 202992 kb
Host smart-c12786d7-bf22-45a0-b26b-209e463da011
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045803702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_c
sr_outstanding.1045803702
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.127438561
Short name T1138
Test name
Test status
Simulation time 183794144 ps
CPU time 2.34 seconds
Started Mar 31 12:34:53 PM PDT 24
Finished Mar 31 12:34:55 PM PDT 24
Peak memory 202828 kb
Host smart-3034b9a3-9d5f-4e05-bddf-e86a700c4f68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=127438561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.127438561
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2933576574
Short name T69
Test name
Test status
Simulation time 22825752 ps
CPU time 0.63 seconds
Started Mar 31 12:35:12 PM PDT 24
Finished Mar 31 12:35:13 PM PDT 24
Peak memory 202556 kb
Host smart-5bc200d3-6243-4131-a571-65b2e3df41ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2933576574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2933576574
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3279674369
Short name T272
Test name
Test status
Simulation time 21249987 ps
CPU time 0.62 seconds
Started Mar 31 12:35:06 PM PDT 24
Finished Mar 31 12:35:07 PM PDT 24
Peak memory 202240 kb
Host smart-50a80f7a-732d-4697-aa1a-c5a3fc505ed1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3279674369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3279674369
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2187504139
Short name T283
Test name
Test status
Simulation time 21496508 ps
CPU time 0.64 seconds
Started Mar 31 12:35:11 PM PDT 24
Finished Mar 31 12:35:11 PM PDT 24
Peak memory 202528 kb
Host smart-b2de63c3-93e3-46b2-b8a3-8de558c28b4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2187504139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2187504139
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2576161941
Short name T1137
Test name
Test status
Simulation time 32986549 ps
CPU time 0.64 seconds
Started Mar 31 12:35:04 PM PDT 24
Finished Mar 31 12:35:04 PM PDT 24
Peak memory 202568 kb
Host smart-a1d592e4-bd25-4b20-a6db-543073cdcb12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2576161941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2576161941
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.921395409
Short name T276
Test name
Test status
Simulation time 23994055 ps
CPU time 0.64 seconds
Started Mar 31 12:35:16 PM PDT 24
Finished Mar 31 12:35:16 PM PDT 24
Peak memory 202532 kb
Host smart-9520ab48-cafa-4800-abd2-c1b95b44a438
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=921395409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.921395409
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.458291474
Short name T56
Test name
Test status
Simulation time 50326375 ps
CPU time 1.51 seconds
Started Mar 31 12:34:52 PM PDT 24
Finished Mar 31 12:34:53 PM PDT 24
Peak memory 211148 kb
Host smart-c5e22f8e-d765-4ce7-8e00-01cfe1b33d1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458291474 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.458291474
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1686199188
Short name T101
Test name
Test status
Simulation time 35034285 ps
CPU time 0.75 seconds
Started Mar 31 12:34:52 PM PDT 24
Finished Mar 31 12:34:53 PM PDT 24
Peak memory 202628 kb
Host smart-7d874b6a-65dc-4260-b298-4d03ce070b59
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686199188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1686199188
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2758178544
Short name T1101
Test name
Test status
Simulation time 54161946 ps
CPU time 1.35 seconds
Started Mar 31 12:34:53 PM PDT 24
Finished Mar 31 12:34:55 PM PDT 24
Peak memory 203000 kb
Host smart-be6296a5-92b8-4384-bd7a-1ff299903cbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758178544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c
sr_outstanding.2758178544
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3375713007
Short name T222
Test name
Test status
Simulation time 60952856 ps
CPU time 1.79 seconds
Started Mar 31 12:34:55 PM PDT 24
Finished Mar 31 12:34:57 PM PDT 24
Peak memory 202960 kb
Host smart-bf2e57de-09e0-4b75-94c8-7eeb19a79667
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3375713007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3375713007
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.577138311
Short name T291
Test name
Test status
Simulation time 226957266 ps
CPU time 3.87 seconds
Started Mar 31 12:34:49 PM PDT 24
Finished Mar 31 12:34:54 PM PDT 24
Peak memory 202844 kb
Host smart-e08e8a3c-2df8-4f38-902a-f33e439f4fa2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=577138311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.577138311
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3628712879
Short name T1122
Test name
Test status
Simulation time 68618262 ps
CPU time 1.1 seconds
Started Mar 31 12:34:59 PM PDT 24
Finished Mar 31 12:35:00 PM PDT 24
Peak memory 211336 kb
Host smart-7e9614d5-0981-4ab0-8c70-99223f24a737
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628712879 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.3628712879
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.231485784
Short name T1123
Test name
Test status
Simulation time 41053929 ps
CPU time 0.76 seconds
Started Mar 31 12:34:55 PM PDT 24
Finished Mar 31 12:34:56 PM PDT 24
Peak memory 202600 kb
Host smart-65137fb7-3e9c-4e04-aaf6-0565cccbbdbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231485784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.231485784
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4139245496
Short name T1106
Test name
Test status
Simulation time 58727622 ps
CPU time 1.42 seconds
Started Mar 31 12:34:50 PM PDT 24
Finished Mar 31 12:34:52 PM PDT 24
Peak memory 202964 kb
Host smart-e11deefd-527d-4b67-a4c3-abf254248c13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139245496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c
sr_outstanding.4139245496
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2905342233
Short name T1115
Test name
Test status
Simulation time 113476762 ps
CPU time 1.69 seconds
Started Mar 31 12:34:53 PM PDT 24
Finished Mar 31 12:34:55 PM PDT 24
Peak memory 202900 kb
Host smart-9700b2b2-f262-44e4-861a-de6b8689d834
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2905342233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2905342233
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1301504473
Short name T271
Test name
Test status
Simulation time 152804674 ps
CPU time 1.86 seconds
Started Mar 31 12:34:49 PM PDT 24
Finished Mar 31 12:34:52 PM PDT 24
Peak memory 214352 kb
Host smart-be7ad9f4-1e09-44b4-b7fd-b975500e63b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301504473 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.1301504473
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2511129346
Short name T255
Test name
Test status
Simulation time 22492716 ps
CPU time 0.76 seconds
Started Mar 31 12:34:56 PM PDT 24
Finished Mar 31 12:34:57 PM PDT 24
Peak memory 202600 kb
Host smart-0e069be4-76c9-4f44-a860-a9607453306e
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511129346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2511129346
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1122749785
Short name T1127
Test name
Test status
Simulation time 59670386 ps
CPU time 1.45 seconds
Started Mar 31 12:34:50 PM PDT 24
Finished Mar 31 12:34:52 PM PDT 24
Peak memory 202956 kb
Host smart-576147df-29bf-46d5-a460-65e5b0373d14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122749785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_c
sr_outstanding.1122749785
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.40488464
Short name T1124
Test name
Test status
Simulation time 129117885 ps
CPU time 1.71 seconds
Started Mar 31 12:34:49 PM PDT 24
Finished Mar 31 12:34:51 PM PDT 24
Peak memory 202984 kb
Host smart-f20d1553-bbad-4268-a44d-354134c7faa5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=40488464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.40488464
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3638824651
Short name T269
Test name
Test status
Simulation time 134136002 ps
CPU time 1.76 seconds
Started Mar 31 12:34:56 PM PDT 24
Finished Mar 31 12:34:58 PM PDT 24
Peak memory 211256 kb
Host smart-9c4bfffa-c72e-42b9-9b0d-72eac9840566
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638824651 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.3638824651
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.919982722
Short name T249
Test name
Test status
Simulation time 59216325 ps
CPU time 0.92 seconds
Started Mar 31 12:34:53 PM PDT 24
Finished Mar 31 12:34:54 PM PDT 24
Peak memory 202900 kb
Host smart-bbff8d38-e9ea-4c27-8eb2-4f23a321bd69
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919982722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.919982722
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2608410059
Short name T1118
Test name
Test status
Simulation time 64364867 ps
CPU time 1.03 seconds
Started Mar 31 12:34:50 PM PDT 24
Finished Mar 31 12:34:52 PM PDT 24
Peak memory 202848 kb
Host smart-99035304-dbfe-4ad5-b011-10e21ce968e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608410059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_c
sr_outstanding.2608410059
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3054229044
Short name T233
Test name
Test status
Simulation time 99186389 ps
CPU time 1.3 seconds
Started Mar 31 12:34:56 PM PDT 24
Finished Mar 31 12:34:57 PM PDT 24
Peak memory 202936 kb
Host smart-9fb8d7fa-7734-41bb-af41-5bbaa32b4f91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3054229044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.3054229044
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3390345903
Short name T1126
Test name
Test status
Simulation time 81416484 ps
CPU time 2.64 seconds
Started Mar 31 12:34:58 PM PDT 24
Finished Mar 31 12:35:00 PM PDT 24
Peak memory 211372 kb
Host smart-7d0b1ff5-4a7d-4d66-8296-b39512a5b961
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390345903 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.3390345903
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.469977327
Short name T63
Test name
Test status
Simulation time 30978054 ps
CPU time 0.9 seconds
Started Mar 31 12:34:56 PM PDT 24
Finished Mar 31 12:34:57 PM PDT 24
Peak memory 202848 kb
Host smart-936f0730-dd9a-4fd9-a7ed-26c8e39c42e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469977327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.469977327
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1778494749
Short name T224
Test name
Test status
Simulation time 125451722 ps
CPU time 1.53 seconds
Started Mar 31 12:34:56 PM PDT 24
Finished Mar 31 12:34:58 PM PDT 24
Peak memory 203024 kb
Host smart-04a2b3ea-c071-4bff-9328-8ed9d81694ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778494749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_c
sr_outstanding.1778494749
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3512843459
Short name T232
Test name
Test status
Simulation time 52035544 ps
CPU time 1.51 seconds
Started Mar 31 12:34:50 PM PDT 24
Finished Mar 31 12:34:52 PM PDT 24
Peak memory 202976 kb
Host smart-83173791-9afa-406a-a0dd-56239bfa3bac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3512843459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3512843459
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1946973371
Short name T1104
Test name
Test status
Simulation time 204742152 ps
CPU time 3.97 seconds
Started Mar 31 12:34:52 PM PDT 24
Finished Mar 31 12:34:56 PM PDT 24
Peak memory 202960 kb
Host smart-a071588a-53ac-4749-9e16-34079a03e76e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1946973371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1946973371
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.in_iso.4052825928
Short name T720
Test name
Test status
Simulation time 8445287667 ps
CPU time 7.28 seconds
Started Mar 31 01:44:39 PM PDT 24
Finished Mar 31 01:44:47 PM PDT 24
Peak memory 204136 kb
Host smart-4a9ca8bd-210b-4b1c-bfa4-1e0b2eb28760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40528
25928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.in_iso.4052825928
Directory /workspace/0.in_iso/latest

Test location /workspace/coverage/default/0.phy_config_usb_ref_disable.882820257
Short name T474
Test name
Test status
Simulation time 8364468356 ps
CPU time 7.43 seconds
Started Mar 31 01:44:32 PM PDT 24
Finished Mar 31 01:44:40 PM PDT 24
Peak memory 204148 kb
Host smart-2cf6353f-fdac-43e0-b816-fa5dab293018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88282
0257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.phy_config_usb_ref_disable.882820257
Directory /workspace/0.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.3660035477
Short name T340
Test name
Test status
Simulation time 8370788657 ps
CPU time 7.59 seconds
Started Mar 31 01:44:09 PM PDT 24
Finished Mar 31 01:44:17 PM PDT 24
Peak memory 204144 kb
Host smart-2e9bb371-917c-4ce0-ba05-3760e815354d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36600
35477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.3660035477
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_enable.725545931
Short name T723
Test name
Test status
Simulation time 8370738907 ps
CPU time 7.08 seconds
Started Mar 31 01:44:10 PM PDT 24
Finished Mar 31 01:44:17 PM PDT 24
Peak memory 204112 kb
Host smart-243c0fbd-aaa4-4908-87a4-0195a717fc60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72554
5931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.725545931
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.537208630
Short name T401
Test name
Test status
Simulation time 48817396 ps
CPU time 1.39 seconds
Started Mar 31 01:44:10 PM PDT 24
Finished Mar 31 01:44:12 PM PDT 24
Peak memory 204292 kb
Host smart-a3680787-b386-418b-914e-16e2228b8694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53720
8630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.537208630
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.4148624387
Short name T41
Test name
Test status
Simulation time 8375328642 ps
CPU time 7.07 seconds
Started Mar 31 01:44:09 PM PDT 24
Finished Mar 31 01:44:17 PM PDT 24
Peak memory 204100 kb
Host smart-230c51a4-d44d-434c-9996-33be2117b820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41486
24387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.4148624387
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.2019464087
Short name T467
Test name
Test status
Simulation time 8410199617 ps
CPU time 7.76 seconds
Started Mar 31 01:44:16 PM PDT 24
Finished Mar 31 01:44:24 PM PDT 24
Peak memory 204080 kb
Host smart-093cd234-dffe-447d-a5d8-d410cd5eea25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20194
64087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.2019464087
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.3072396952
Short name T989
Test name
Test status
Simulation time 8368012297 ps
CPU time 9.48 seconds
Started Mar 31 01:44:18 PM PDT 24
Finished Mar 31 01:44:28 PM PDT 24
Peak memory 204120 kb
Host smart-487f631b-96b2-4fb9-8ae6-381c62cac5cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30723
96952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.3072396952
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.2819166439
Short name T580
Test name
Test status
Simulation time 8364232031 ps
CPU time 7.47 seconds
Started Mar 31 01:44:29 PM PDT 24
Finished Mar 31 01:44:37 PM PDT 24
Peak memory 204112 kb
Host smart-13a75e25-f020-4d85-83f5-624c734623a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28191
66439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.2819166439
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.1023291833
Short name T603
Test name
Test status
Simulation time 8396268770 ps
CPU time 7.31 seconds
Started Mar 31 01:44:28 PM PDT 24
Finished Mar 31 01:44:36 PM PDT 24
Peak memory 204104 kb
Host smart-0eafcacd-1658-42c5-89c0-8a6fd42ab93d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10232
91833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.1023291833
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1772601443
Short name T537
Test name
Test status
Simulation time 24920548 ps
CPU time 0.61 seconds
Started Mar 31 01:44:40 PM PDT 24
Finished Mar 31 01:44:41 PM PDT 24
Peak memory 204052 kb
Host smart-50008afb-2695-4372-9022-3aa7b53beac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17726
01443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1772601443
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.479346140
Short name T867
Test name
Test status
Simulation time 24275864031 ps
CPU time 45.12 seconds
Started Mar 31 01:44:27 PM PDT 24
Finished Mar 31 01:45:12 PM PDT 24
Peak memory 204280 kb
Host smart-609ae8f9-e032-41b6-8372-b43638864704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47934
6140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.479346140
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.1342205280
Short name T582
Test name
Test status
Simulation time 8368843905 ps
CPU time 7.56 seconds
Started Mar 31 01:44:27 PM PDT 24
Finished Mar 31 01:44:35 PM PDT 24
Peak memory 204140 kb
Host smart-68868943-3646-46c2-8e51-e23d84b6a191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13422
05280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.1342205280
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.2631438895
Short name T543
Test name
Test status
Simulation time 8399639221 ps
CPU time 7.3 seconds
Started Mar 31 01:44:28 PM PDT 24
Finished Mar 31 01:44:35 PM PDT 24
Peak memory 204128 kb
Host smart-2ffe4aa2-522a-402b-a7b6-ddd4d2008585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26314
38895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.2631438895
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.410718473
Short name T309
Test name
Test status
Simulation time 8370860749 ps
CPU time 7.61 seconds
Started Mar 31 01:44:28 PM PDT 24
Finished Mar 31 01:44:36 PM PDT 24
Peak memory 204084 kb
Host smart-81bf4252-b959-4e9c-8302-9d89e4edf0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41071
8473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.410718473
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.2874716955
Short name T742
Test name
Test status
Simulation time 8358951003 ps
CPU time 8.56 seconds
Started Mar 31 01:44:34 PM PDT 24
Finished Mar 31 01:44:42 PM PDT 24
Peak memory 204164 kb
Host smart-425ba6a5-0215-4db9-ba6c-b397ec5313ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28747
16955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.2874716955
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.3655985881
Short name T754
Test name
Test status
Simulation time 8393598035 ps
CPU time 7.55 seconds
Started Mar 31 01:44:34 PM PDT 24
Finished Mar 31 01:44:42 PM PDT 24
Peak memory 204100 kb
Host smart-d00dc5ba-d713-4fe9-a1b7-b7ac9c048ad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36559
85881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.3655985881
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.phy_config_usb_ref_disable.2564421323
Short name T458
Test name
Test status
Simulation time 8361815791 ps
CPU time 8.16 seconds
Started Mar 31 01:45:12 PM PDT 24
Finished Mar 31 01:45:20 PM PDT 24
Peak memory 204116 kb
Host smart-e0843c4c-daff-4ee7-9751-0f63a32f6c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25644
21323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.phy_config_usb_ref_disable.2564421323
Directory /workspace/1.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.2806072486
Short name T686
Test name
Test status
Simulation time 8367676342 ps
CPU time 7.58 seconds
Started Mar 31 01:44:47 PM PDT 24
Finished Mar 31 01:44:55 PM PDT 24
Peak memory 204140 kb
Host smart-ca62d82c-1bf1-4e81-b21e-f343df4c0c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28060
72486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.2806072486
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_enable.745889558
Short name T475
Test name
Test status
Simulation time 8367900981 ps
CPU time 8.32 seconds
Started Mar 31 01:44:46 PM PDT 24
Finished Mar 31 01:44:54 PM PDT 24
Peak memory 204100 kb
Host smart-8bb5d2f6-4cdd-469f-a950-4fe361cf2ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74588
9558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.745889558
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1221107773
Short name T53
Test name
Test status
Simulation time 58624343 ps
CPU time 1.46 seconds
Started Mar 31 01:44:51 PM PDT 24
Finished Mar 31 01:44:53 PM PDT 24
Peak memory 204268 kb
Host smart-5f113a11-8889-466e-8d40-59d8c186d383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12211
07773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1221107773
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.3394669539
Short name T216
Test name
Test status
Simulation time 8361946081 ps
CPU time 7.24 seconds
Started Mar 31 01:45:14 PM PDT 24
Finished Mar 31 01:45:22 PM PDT 24
Peak memory 204168 kb
Host smart-3ad59bcb-1744-46f9-86cf-c399bb154673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33946
69539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3394669539
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.4069172762
Short name T586
Test name
Test status
Simulation time 8406951057 ps
CPU time 7.39 seconds
Started Mar 31 01:44:51 PM PDT 24
Finished Mar 31 01:44:58 PM PDT 24
Peak memory 204020 kb
Host smart-fbb3861b-c756-46e1-b50c-e6652e071d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40691
72762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.4069172762
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.4109669069
Short name T563
Test name
Test status
Simulation time 8365945694 ps
CPU time 9.37 seconds
Started Mar 31 01:44:53 PM PDT 24
Finished Mar 31 01:45:03 PM PDT 24
Peak memory 204116 kb
Host smart-5174549d-dd80-40b7-a07b-d5a6d94264d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41096
69069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.4109669069
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.3371586299
Short name T984
Test name
Test status
Simulation time 8388371315 ps
CPU time 7.23 seconds
Started Mar 31 01:45:06 PM PDT 24
Finished Mar 31 01:45:13 PM PDT 24
Peak memory 204144 kb
Host smart-08e21722-6bf0-4a88-b6fa-06da324893b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33715
86299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3371586299
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3954747817
Short name T872
Test name
Test status
Simulation time 28546426 ps
CPU time 0.65 seconds
Started Mar 31 01:45:13 PM PDT 24
Finished Mar 31 01:45:15 PM PDT 24
Peak memory 204048 kb
Host smart-b3f79a15-90e1-4dfe-83fd-99e3c3a35189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39547
47817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3954747817
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.1865658946
Short name T97
Test name
Test status
Simulation time 17357102161 ps
CPU time 30.03 seconds
Started Mar 31 01:45:05 PM PDT 24
Finished Mar 31 01:45:35 PM PDT 24
Peak memory 204420 kb
Host smart-2d624941-cb1c-4cc1-a86d-968f1513c764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18656
58946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.1865658946
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.3578002220
Short name T590
Test name
Test status
Simulation time 8395459039 ps
CPU time 8.29 seconds
Started Mar 31 01:45:05 PM PDT 24
Finished Mar 31 01:45:13 PM PDT 24
Peak memory 204172 kb
Host smart-a92477a3-073e-43b8-8cd3-a4880a672423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35780
02220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.3578002220
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.3559941009
Short name T721
Test name
Test status
Simulation time 8432185704 ps
CPU time 7.18 seconds
Started Mar 31 01:45:06 PM PDT 24
Finished Mar 31 01:45:13 PM PDT 24
Peak memory 204172 kb
Host smart-b5344c84-276e-46ec-83bd-bb5ab51777b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35599
41009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.3559941009
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.2900327426
Short name T540
Test name
Test status
Simulation time 8376422400 ps
CPU time 7.36 seconds
Started Mar 31 01:45:07 PM PDT 24
Finished Mar 31 01:45:14 PM PDT 24
Peak memory 204108 kb
Host smart-88f4d531-61f7-4dd3-89e1-50855de0944e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29003
27426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.2900327426
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.2011855332
Short name T57
Test name
Test status
Simulation time 390590164 ps
CPU time 1.12 seconds
Started Mar 31 01:45:12 PM PDT 24
Finished Mar 31 01:45:14 PM PDT 24
Peak memory 221028 kb
Host smart-e6cbc908-1b3f-4aeb-90c3-45a8e225910c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2011855332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2011855332
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.635653306
Short name T1074
Test name
Test status
Simulation time 8360735231 ps
CPU time 8.01 seconds
Started Mar 31 01:45:13 PM PDT 24
Finished Mar 31 01:45:21 PM PDT 24
Peak memory 204120 kb
Host smart-0d50b5b7-6a5b-40d8-975d-41c79f9a1009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63565
3306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.635653306
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.3086805178
Short name T758
Test name
Test status
Simulation time 8396468966 ps
CPU time 9.31 seconds
Started Mar 31 01:45:11 PM PDT 24
Finished Mar 31 01:45:20 PM PDT 24
Peak memory 204108 kb
Host smart-79828e28-48da-4ee7-9a88-5d6d2a126ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30868
05178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.3086805178
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.in_iso.1380352898
Short name T521
Test name
Test status
Simulation time 8455226086 ps
CPU time 8.35 seconds
Started Mar 31 01:47:35 PM PDT 24
Finished Mar 31 01:47:44 PM PDT 24
Peak memory 204100 kb
Host smart-131489df-d4fe-41b6-844d-6acc11f69173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13803
52898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.in_iso.1380352898
Directory /workspace/10.in_iso/latest

Test location /workspace/coverage/default/10.phy_config_usb_ref_disable.4147608869
Short name T27
Test name
Test status
Simulation time 8360919349 ps
CPU time 8.92 seconds
Started Mar 31 01:47:35 PM PDT 24
Finished Mar 31 01:47:44 PM PDT 24
Peak memory 204076 kb
Host smart-994ca395-db05-470e-9df5-6a0ec619c9c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41476
08869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.phy_config_usb_ref_disable.4147608869
Directory /workspace/10.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.2773981703
Short name T818
Test name
Test status
Simulation time 8373292127 ps
CPU time 7.17 seconds
Started Mar 31 01:47:30 PM PDT 24
Finished Mar 31 01:47:37 PM PDT 24
Peak memory 204128 kb
Host smart-55a676ca-eaab-4b1a-808b-102d170a38a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27739
81703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.2773981703
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_enable.2167407398
Short name T297
Test name
Test status
Simulation time 8375465010 ps
CPU time 7.63 seconds
Started Mar 31 01:47:30 PM PDT 24
Finished Mar 31 01:47:37 PM PDT 24
Peak memory 204132 kb
Host smart-b7d356ca-f7bd-4e53-b81c-0f903fe9471b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21674
07398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.2167407398
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.260399603
Short name T558
Test name
Test status
Simulation time 264474933 ps
CPU time 2.11 seconds
Started Mar 31 01:47:29 PM PDT 24
Finished Mar 31 01:47:31 PM PDT 24
Peak memory 204280 kb
Host smart-8133a5e0-ff55-4e12-983c-b2a1fd725c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26039
9603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.260399603
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.760100957
Short name T189
Test name
Test status
Simulation time 8363247057 ps
CPU time 7.3 seconds
Started Mar 31 01:47:36 PM PDT 24
Finished Mar 31 01:47:43 PM PDT 24
Peak memory 204096 kb
Host smart-b48630bd-b32b-403b-98c9-22db5826f73d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76010
0957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.760100957
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.2759661471
Short name T136
Test name
Test status
Simulation time 8419772199 ps
CPU time 7.57 seconds
Started Mar 31 01:47:30 PM PDT 24
Finished Mar 31 01:47:38 PM PDT 24
Peak memory 204144 kb
Host smart-19532d65-c5b7-4cec-af05-79654f0cd937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27596
61471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.2759661471
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.2244818732
Short name T587
Test name
Test status
Simulation time 8404891286 ps
CPU time 7.55 seconds
Started Mar 31 01:47:30 PM PDT 24
Finished Mar 31 01:47:37 PM PDT 24
Peak memory 204096 kb
Host smart-9f8357e2-79ac-48aa-ab38-19127d85064f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22448
18732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2244818732
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.2832693497
Short name T693
Test name
Test status
Simulation time 8367752465 ps
CPU time 7.14 seconds
Started Mar 31 01:47:33 PM PDT 24
Finished Mar 31 01:47:40 PM PDT 24
Peak memory 204144 kb
Host smart-cd5451e9-b0c7-4501-953d-ed213d93c3ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28326
93497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2832693497
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.738501545
Short name T969
Test name
Test status
Simulation time 8390757199 ps
CPU time 7.11 seconds
Started Mar 31 01:47:30 PM PDT 24
Finished Mar 31 01:47:37 PM PDT 24
Peak memory 204120 kb
Host smart-0127b936-2734-4c05-86b9-d96c53a7e02e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73850
1545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.738501545
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.3965181499
Short name T977
Test name
Test status
Simulation time 8389981297 ps
CPU time 7.83 seconds
Started Mar 31 01:47:32 PM PDT 24
Finished Mar 31 01:47:40 PM PDT 24
Peak memory 204112 kb
Host smart-591d37cd-0332-4890-b915-8859a3e2b1cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39651
81499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.3965181499
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.44114176
Short name T487
Test name
Test status
Simulation time 25823991 ps
CPU time 0.65 seconds
Started Mar 31 01:47:36 PM PDT 24
Finished Mar 31 01:47:36 PM PDT 24
Peak memory 204084 kb
Host smart-04d30245-e435-4d66-b714-e0f98b82baf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44114
176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.44114176
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.2900740672
Short name T552
Test name
Test status
Simulation time 8367177808 ps
CPU time 7.68 seconds
Started Mar 31 01:47:37 PM PDT 24
Finished Mar 31 01:47:44 PM PDT 24
Peak memory 204156 kb
Host smart-1200317a-3f1d-48b9-9743-8df53d7b8293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29007
40672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.2900740672
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.3916913956
Short name T263
Test name
Test status
Simulation time 8448442668 ps
CPU time 7.72 seconds
Started Mar 31 01:47:36 PM PDT 24
Finished Mar 31 01:47:44 PM PDT 24
Peak memory 204112 kb
Host smart-28023d56-a94b-424b-8686-eeb696cf1a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39169
13956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.3916913956
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.2407946018
Short name T439
Test name
Test status
Simulation time 8389368350 ps
CPU time 7.28 seconds
Started Mar 31 01:47:36 PM PDT 24
Finished Mar 31 01:47:43 PM PDT 24
Peak memory 204112 kb
Host smart-06d8c830-e97d-4725-9d49-54c97f229cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24079
46018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.2407946018
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1057939277
Short name T1085
Test name
Test status
Simulation time 8363142347 ps
CPU time 7.01 seconds
Started Mar 31 01:47:36 PM PDT 24
Finished Mar 31 01:47:44 PM PDT 24
Peak memory 204132 kb
Host smart-ba23b06c-1d64-45a3-8a4c-c35a259a7df0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10579
39277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1057939277
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.2977593507
Short name T417
Test name
Test status
Simulation time 8404457932 ps
CPU time 6.99 seconds
Started Mar 31 01:47:35 PM PDT 24
Finished Mar 31 01:47:42 PM PDT 24
Peak memory 204124 kb
Host smart-fffd3a5d-c748-45a8-9662-ef8fc1348c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29775
93507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.2977593507
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.in_iso.737858224
Short name T771
Test name
Test status
Simulation time 8450339981 ps
CPU time 7.74 seconds
Started Mar 31 01:47:54 PM PDT 24
Finished Mar 31 01:48:02 PM PDT 24
Peak memory 204108 kb
Host smart-36fe88be-197c-4837-83f1-8204a9702750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73785
8224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.in_iso.737858224
Directory /workspace/11.in_iso/latest

Test location /workspace/coverage/default/11.phy_config_usb_ref_disable.3088686006
Short name T907
Test name
Test status
Simulation time 8362224255 ps
CPU time 7.87 seconds
Started Mar 31 01:47:52 PM PDT 24
Finished Mar 31 01:48:00 PM PDT 24
Peak memory 204096 kb
Host smart-99c00668-8b30-4186-9f83-209da53ccb2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30886
86006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.phy_config_usb_ref_disable.3088686006
Directory /workspace/11.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.1858832523
Short name T508
Test name
Test status
Simulation time 8369967809 ps
CPU time 7.07 seconds
Started Mar 31 01:47:46 PM PDT 24
Finished Mar 31 01:47:53 PM PDT 24
Peak memory 204136 kb
Host smart-7ba7c39b-1ebc-4a92-aef8-a506b5461fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18588
32523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.1858832523
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_enable.1596917914
Short name T699
Test name
Test status
Simulation time 8367679870 ps
CPU time 7.76 seconds
Started Mar 31 01:47:42 PM PDT 24
Finished Mar 31 01:47:50 PM PDT 24
Peak memory 204136 kb
Host smart-2aab7538-86a2-4b00-bfb7-5289c21ad22f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15969
17914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.1596917914
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.2358062390
Short name T607
Test name
Test status
Simulation time 62055967 ps
CPU time 1.6 seconds
Started Mar 31 01:47:43 PM PDT 24
Finished Mar 31 01:47:44 PM PDT 24
Peak memory 204244 kb
Host smart-e323c518-9948-4746-b638-a78a394be026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23580
62390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.2358062390
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.1845879673
Short name T188
Test name
Test status
Simulation time 8358491787 ps
CPU time 7.25 seconds
Started Mar 31 01:47:54 PM PDT 24
Finished Mar 31 01:48:01 PM PDT 24
Peak memory 204104 kb
Host smart-cb97bdda-eddd-40b5-9119-e788128cfee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18458
79673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.1845879673
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.2938678052
Short name T148
Test name
Test status
Simulation time 8373744990 ps
CPU time 7.57 seconds
Started Mar 31 01:47:42 PM PDT 24
Finished Mar 31 01:47:50 PM PDT 24
Peak memory 204068 kb
Host smart-94f1ebec-d1c7-435e-af56-943966834a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29386
78052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.2938678052
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.401544251
Short name T967
Test name
Test status
Simulation time 8412140509 ps
CPU time 7.74 seconds
Started Mar 31 01:47:43 PM PDT 24
Finished Mar 31 01:47:51 PM PDT 24
Peak memory 204060 kb
Host smart-9e13c80e-af74-4935-b3ae-1e440b128415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40154
4251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.401544251
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.3225011713
Short name T293
Test name
Test status
Simulation time 8366300256 ps
CPU time 7.91 seconds
Started Mar 31 01:47:43 PM PDT 24
Finished Mar 31 01:47:51 PM PDT 24
Peak memory 204136 kb
Host smart-7babf4da-fdd1-49b4-8fc7-1dc52854a7f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32250
11713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.3225011713
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1105700476
Short name T453
Test name
Test status
Simulation time 8381103629 ps
CPU time 8.1 seconds
Started Mar 31 01:47:43 PM PDT 24
Finished Mar 31 01:47:51 PM PDT 24
Peak memory 204140 kb
Host smart-fba78e53-aa85-41d7-885e-2143c50eb571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11057
00476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1105700476
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.4170768268
Short name T423
Test name
Test status
Simulation time 8389867141 ps
CPU time 8.97 seconds
Started Mar 31 01:47:43 PM PDT 24
Finished Mar 31 01:47:53 PM PDT 24
Peak memory 204120 kb
Host smart-e82cb272-1421-44a3-ba80-edd09078ffd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41707
68268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.4170768268
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.802616149
Short name T531
Test name
Test status
Simulation time 27802589 ps
CPU time 0.61 seconds
Started Mar 31 01:47:49 PM PDT 24
Finished Mar 31 01:47:50 PM PDT 24
Peak memory 204064 kb
Host smart-b936a91e-6a0c-418c-babb-2379554a8744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80261
6149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.802616149
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.3540044725
Short name T698
Test name
Test status
Simulation time 8381644337 ps
CPU time 7.39 seconds
Started Mar 31 01:47:49 PM PDT 24
Finished Mar 31 01:47:56 PM PDT 24
Peak memory 204144 kb
Host smart-1f09025e-fc66-4963-9258-14a898ae23b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35400
44725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3540044725
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.4177126400
Short name T840
Test name
Test status
Simulation time 8390015743 ps
CPU time 7.97 seconds
Started Mar 31 01:47:50 PM PDT 24
Finished Mar 31 01:47:58 PM PDT 24
Peak memory 204144 kb
Host smart-e59648a8-4b0b-4ecd-81c4-151b5271bb2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41771
26400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.4177126400
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.3434609509
Short name T736
Test name
Test status
Simulation time 8394422782 ps
CPU time 8.44 seconds
Started Mar 31 01:47:51 PM PDT 24
Finished Mar 31 01:48:00 PM PDT 24
Peak memory 204108 kb
Host smart-c175682f-dc3e-408e-8929-b342b9acc2ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34346
09509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.3434609509
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.4143816613
Short name T819
Test name
Test status
Simulation time 8360053827 ps
CPU time 7.9 seconds
Started Mar 31 01:47:49 PM PDT 24
Finished Mar 31 01:47:57 PM PDT 24
Peak memory 204124 kb
Host smart-a63a6480-6d0d-4e46-ba0a-b7f7a29721d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41438
16613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.4143816613
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.3334714570
Short name T169
Test name
Test status
Simulation time 8419973537 ps
CPU time 7.36 seconds
Started Mar 31 01:47:42 PM PDT 24
Finished Mar 31 01:47:49 PM PDT 24
Peak memory 204100 kb
Host smart-a2f5b5b1-21f0-444a-9de2-f68ff58459ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33347
14570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.3334714570
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.3325429987
Short name T884
Test name
Test status
Simulation time 8406396643 ps
CPU time 7.03 seconds
Started Mar 31 01:47:52 PM PDT 24
Finished Mar 31 01:47:59 PM PDT 24
Peak memory 204108 kb
Host smart-18fa574c-ec29-4519-aa90-61857487e1e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33254
29987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.3325429987
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.in_iso.2187484488
Short name T321
Test name
Test status
Simulation time 8437695766 ps
CPU time 7.42 seconds
Started Mar 31 01:48:08 PM PDT 24
Finished Mar 31 01:48:16 PM PDT 24
Peak memory 204108 kb
Host smart-7dab60ff-d31f-4602-9a66-1e831cbd7cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21874
84488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.in_iso.2187484488
Directory /workspace/12.in_iso/latest

Test location /workspace/coverage/default/12.phy_config_usb_ref_disable.1701442996
Short name T8
Test name
Test status
Simulation time 8365664039 ps
CPU time 7.47 seconds
Started Mar 31 01:48:08 PM PDT 24
Finished Mar 31 01:48:15 PM PDT 24
Peak memory 204128 kb
Host smart-2836ceef-6609-4669-9a7f-c646fc157766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17014
42996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.phy_config_usb_ref_disable.1701442996
Directory /workspace/12.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.3069228529
Short name T1084
Test name
Test status
Simulation time 8367202339 ps
CPU time 8.55 seconds
Started Mar 31 01:47:55 PM PDT 24
Finished Mar 31 01:48:04 PM PDT 24
Peak memory 204100 kb
Host smart-bea6f202-b7a7-42ff-a280-f31cdfc4d02f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30692
28529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.3069228529
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_enable.2677207153
Short name T608
Test name
Test status
Simulation time 8373763562 ps
CPU time 7.17 seconds
Started Mar 31 01:47:55 PM PDT 24
Finished Mar 31 01:48:02 PM PDT 24
Peak memory 204008 kb
Host smart-6836ca7b-5bba-41ff-a6aa-fe6687e5de85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26772
07153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.2677207153
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.962830427
Short name T405
Test name
Test status
Simulation time 142295265 ps
CPU time 1.34 seconds
Started Mar 31 01:47:59 PM PDT 24
Finished Mar 31 01:48:01 PM PDT 24
Peak memory 204244 kb
Host smart-0e8fef63-c833-48e7-9f6d-130a795246fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96283
0427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.962830427
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.3023324309
Short name T187
Test name
Test status
Simulation time 8359303495 ps
CPU time 8.21 seconds
Started Mar 31 01:48:08 PM PDT 24
Finished Mar 31 01:48:16 PM PDT 24
Peak memory 204132 kb
Host smart-db636c04-93db-4a05-9edf-afc9215601b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30233
24309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.3023324309
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.2927427103
Short name T1049
Test name
Test status
Simulation time 8406542718 ps
CPU time 8.79 seconds
Started Mar 31 01:47:55 PM PDT 24
Finished Mar 31 01:48:04 PM PDT 24
Peak memory 204128 kb
Host smart-a8d85a7b-1071-4e80-8e11-5cc3472abc14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29274
27103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.2927427103
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.3744254244
Short name T903
Test name
Test status
Simulation time 8408630048 ps
CPU time 7.63 seconds
Started Mar 31 01:47:55 PM PDT 24
Finished Mar 31 01:48:02 PM PDT 24
Peak memory 204108 kb
Host smart-687ee7ab-c39d-4c0f-89ef-f2622fa6d01b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37442
54244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.3744254244
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.416225946
Short name T848
Test name
Test status
Simulation time 8362004991 ps
CPU time 9.9 seconds
Started Mar 31 01:47:54 PM PDT 24
Finished Mar 31 01:48:04 PM PDT 24
Peak memory 204144 kb
Host smart-354a51b7-3075-442d-b4d0-b3a1017c9f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41622
5946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.416225946
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.2094304332
Short name T677
Test name
Test status
Simulation time 8372578618 ps
CPU time 7.4 seconds
Started Mar 31 01:48:01 PM PDT 24
Finished Mar 31 01:48:08 PM PDT 24
Peak memory 204104 kb
Host smart-897c37d7-5681-4ee4-9446-15e5afae3fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20943
04332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.2094304332
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.914330834
Short name T963
Test name
Test status
Simulation time 8401955333 ps
CPU time 7.95 seconds
Started Mar 31 01:47:59 PM PDT 24
Finished Mar 31 01:48:07 PM PDT 24
Peak memory 204164 kb
Host smart-165ade1f-3c63-4086-a622-15df0c6272ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91433
0834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.914330834
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.4179477628
Short name T916
Test name
Test status
Simulation time 30004790 ps
CPU time 0.66 seconds
Started Mar 31 01:48:05 PM PDT 24
Finished Mar 31 01:48:06 PM PDT 24
Peak memory 204036 kb
Host smart-68b277f9-e96a-4ce6-9f76-da2b9e106abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41794
77628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.4179477628
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.2872362754
Short name T49
Test name
Test status
Simulation time 23019446046 ps
CPU time 40.39 seconds
Started Mar 31 01:48:02 PM PDT 24
Finished Mar 31 01:48:42 PM PDT 24
Peak memory 204392 kb
Host smart-c335ac74-d7ee-459a-a8fe-c0b00695f9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28723
62754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.2872362754
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.101651027
Short name T912
Test name
Test status
Simulation time 8392238824 ps
CPU time 7.32 seconds
Started Mar 31 01:48:01 PM PDT 24
Finished Mar 31 01:48:09 PM PDT 24
Peak memory 204140 kb
Host smart-bf603fb5-2a08-4b5b-93a3-ababc793ea9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10165
1027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.101651027
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3208646525
Short name T566
Test name
Test status
Simulation time 8387339902 ps
CPU time 7.16 seconds
Started Mar 31 01:48:02 PM PDT 24
Finished Mar 31 01:48:09 PM PDT 24
Peak memory 204068 kb
Host smart-720e92cd-23ba-4d50-81ba-cf34b1fd9b01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32086
46525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3208646525
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.3123607975
Short name T547
Test name
Test status
Simulation time 8391756299 ps
CPU time 9.9 seconds
Started Mar 31 01:48:00 PM PDT 24
Finished Mar 31 01:48:10 PM PDT 24
Peak memory 204084 kb
Host smart-478878ad-3f86-4ee9-95dc-c1430884a385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31236
07975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.3123607975
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3220565932
Short name T1082
Test name
Test status
Simulation time 8363018926 ps
CPU time 8.74 seconds
Started Mar 31 01:48:01 PM PDT 24
Finished Mar 31 01:48:10 PM PDT 24
Peak memory 204156 kb
Host smart-3db27c96-a94d-4589-b8c2-f718a2341b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32205
65932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3220565932
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.4213691849
Short name T960
Test name
Test status
Simulation time 8470268138 ps
CPU time 7.8 seconds
Started Mar 31 01:47:53 PM PDT 24
Finished Mar 31 01:48:01 PM PDT 24
Peak memory 204088 kb
Host smart-8176e404-12ba-4b6c-b9b7-cadf19f61c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42136
91849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.4213691849
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.1320720967
Short name T593
Test name
Test status
Simulation time 8397705925 ps
CPU time 7.56 seconds
Started Mar 31 01:48:01 PM PDT 24
Finished Mar 31 01:48:09 PM PDT 24
Peak memory 204152 kb
Host smart-8ccc6c76-ee4c-41b3-9285-9ef0a1f1aa63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13207
20967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.1320720967
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.in_iso.1443861165
Short name T142
Test name
Test status
Simulation time 8454301632 ps
CPU time 9.89 seconds
Started Mar 31 01:48:22 PM PDT 24
Finished Mar 31 01:48:33 PM PDT 24
Peak memory 204100 kb
Host smart-1e48202c-cada-4d43-a2fe-172b87bc17dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14438
61165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.in_iso.1443861165
Directory /workspace/13.in_iso/latest

Test location /workspace/coverage/default/13.phy_config_usb_ref_disable.1004192263
Short name T757
Test name
Test status
Simulation time 8368302323 ps
CPU time 9.83 seconds
Started Mar 31 01:48:13 PM PDT 24
Finished Mar 31 01:48:23 PM PDT 24
Peak memory 204108 kb
Host smart-b91f4b1e-67dc-44ae-b6b2-c57580355dd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10041
92263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.phy_config_usb_ref_disable.1004192263
Directory /workspace/13.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.2912779168
Short name T344
Test name
Test status
Simulation time 8371263790 ps
CPU time 7.76 seconds
Started Mar 31 01:48:07 PM PDT 24
Finished Mar 31 01:48:15 PM PDT 24
Peak memory 204108 kb
Host smart-060fa5b6-4621-431c-9c75-95d2023af726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29127
79168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.2912779168
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_enable.2768233902
Short name T856
Test name
Test status
Simulation time 8370559274 ps
CPU time 7.97 seconds
Started Mar 31 01:48:08 PM PDT 24
Finished Mar 31 01:48:17 PM PDT 24
Peak memory 204132 kb
Host smart-b83ce13d-8bb8-4159-94b8-1bd4b647cb7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27682
33902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.2768233902
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.575099357
Short name T94
Test name
Test status
Simulation time 127189591 ps
CPU time 1.54 seconds
Started Mar 31 01:48:09 PM PDT 24
Finished Mar 31 01:48:11 PM PDT 24
Peak memory 204216 kb
Host smart-347f90dc-56c0-4da5-8e29-0be6b958f8fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57509
9357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.575099357
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.579579087
Short name T194
Test name
Test status
Simulation time 8363120285 ps
CPU time 8.09 seconds
Started Mar 31 01:48:16 PM PDT 24
Finished Mar 31 01:48:24 PM PDT 24
Peak memory 204128 kb
Host smart-22940890-19c9-47d5-a572-6746ceaebeb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57957
9087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.579579087
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.741742497
Short name T838
Test name
Test status
Simulation time 8427552807 ps
CPU time 7.92 seconds
Started Mar 31 01:48:06 PM PDT 24
Finished Mar 31 01:48:14 PM PDT 24
Peak memory 204124 kb
Host smart-9551336e-06ea-475f-8c84-7d52c997bd7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74174
2497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.741742497
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3096572578
Short name T262
Test name
Test status
Simulation time 8410219333 ps
CPU time 7.55 seconds
Started Mar 31 01:48:16 PM PDT 24
Finished Mar 31 01:48:23 PM PDT 24
Peak memory 204124 kb
Host smart-5638e3c5-170f-40f8-9455-83840ee8a398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30965
72578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3096572578
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.1435881458
Short name T657
Test name
Test status
Simulation time 8361986447 ps
CPU time 7.09 seconds
Started Mar 31 01:48:15 PM PDT 24
Finished Mar 31 01:48:22 PM PDT 24
Peak memory 204100 kb
Host smart-76c8454a-7138-43ac-8477-587fc915f81f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14358
81458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.1435881458
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.2366754440
Short name T363
Test name
Test status
Simulation time 8398721166 ps
CPU time 8.41 seconds
Started Mar 31 01:48:13 PM PDT 24
Finished Mar 31 01:48:22 PM PDT 24
Peak memory 204120 kb
Host smart-ca1f150d-7a7d-4cb5-85d4-765ee2bba129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23667
54440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.2366754440
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.894378703
Short name T710
Test name
Test status
Simulation time 8384949089 ps
CPU time 7.13 seconds
Started Mar 31 01:48:16 PM PDT 24
Finished Mar 31 01:48:23 PM PDT 24
Peak memory 204104 kb
Host smart-b22c776a-4068-4e07-bde9-3c1440b45b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89437
8703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.894378703
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1153261403
Short name T15
Test name
Test status
Simulation time 8378780962 ps
CPU time 7.82 seconds
Started Mar 31 01:48:14 PM PDT 24
Finished Mar 31 01:48:22 PM PDT 24
Peak memory 204152 kb
Host smart-fc77a2f6-03d8-4a04-ab9d-236f5bacb532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11532
61403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1153261403
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.570895426
Short name T495
Test name
Test status
Simulation time 8372969771 ps
CPU time 7.59 seconds
Started Mar 31 01:48:15 PM PDT 24
Finished Mar 31 01:48:23 PM PDT 24
Peak memory 204152 kb
Host smart-5a267a4e-406d-4a82-a9fd-e7f4dc347f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57089
5426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.570895426
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.2436782142
Short name T372
Test name
Test status
Simulation time 8405502897 ps
CPU time 7.79 seconds
Started Mar 31 01:48:14 PM PDT 24
Finished Mar 31 01:48:22 PM PDT 24
Peak memory 204128 kb
Host smart-ad27b850-a963-44a4-8544-4cbc45187820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24367
82142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.2436782142
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.196288213
Short name T940
Test name
Test status
Simulation time 8381595541 ps
CPU time 7.41 seconds
Started Mar 31 01:48:15 PM PDT 24
Finished Mar 31 01:48:23 PM PDT 24
Peak memory 204016 kb
Host smart-88cae7ba-da1d-43b2-aae8-9bd1f2690b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19628
8213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.196288213
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.1855192231
Short name T666
Test name
Test status
Simulation time 8361401843 ps
CPU time 8.45 seconds
Started Mar 31 01:48:13 PM PDT 24
Finished Mar 31 01:48:22 PM PDT 24
Peak memory 204124 kb
Host smart-cef0b7e6-cb3a-468e-ac51-8651597221d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18551
92231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.1855192231
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.4232011230
Short name T440
Test name
Test status
Simulation time 8365930783 ps
CPU time 7.34 seconds
Started Mar 31 01:48:14 PM PDT 24
Finished Mar 31 01:48:21 PM PDT 24
Peak memory 204152 kb
Host smart-c675822e-7ba1-44af-b9d3-718133f31ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42320
11230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.4232011230
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.in_iso.2189250177
Short name T364
Test name
Test status
Simulation time 8398812530 ps
CPU time 7.61 seconds
Started Mar 31 01:48:27 PM PDT 24
Finished Mar 31 01:48:35 PM PDT 24
Peak memory 204100 kb
Host smart-ac8b188c-d065-42db-a42e-bf21007cc9d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21892
50177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.in_iso.2189250177
Directory /workspace/14.in_iso/latest

Test location /workspace/coverage/default/14.phy_config_usb_ref_disable.2800886609
Short name T1055
Test name
Test status
Simulation time 8365766933 ps
CPU time 6.97 seconds
Started Mar 31 01:48:19 PM PDT 24
Finished Mar 31 01:48:26 PM PDT 24
Peak memory 204144 kb
Host smart-d8702e23-8261-4811-944f-dc349b7599b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28008
86609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.phy_config_usb_ref_disable.2800886609
Directory /workspace/14.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.1881127326
Short name T312
Test name
Test status
Simulation time 8369328915 ps
CPU time 8.37 seconds
Started Mar 31 01:48:20 PM PDT 24
Finished Mar 31 01:48:28 PM PDT 24
Peak memory 204116 kb
Host smart-ca3545e1-7d31-4aaf-b1bc-463953ab26c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18811
27326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.1881127326
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_enable.1715060162
Short name T668
Test name
Test status
Simulation time 8369422505 ps
CPU time 7.88 seconds
Started Mar 31 01:48:19 PM PDT 24
Finished Mar 31 01:48:27 PM PDT 24
Peak memory 204100 kb
Host smart-97482771-8a2e-4761-bb0e-c9496db2cff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17150
60162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1715060162
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.3942459073
Short name T877
Test name
Test status
Simulation time 125771056 ps
CPU time 1.26 seconds
Started Mar 31 01:48:21 PM PDT 24
Finished Mar 31 01:48:23 PM PDT 24
Peak memory 204188 kb
Host smart-8f8567e8-4022-4497-8094-86e588e7bc43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39424
59073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.3942459073
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2545250399
Short name T864
Test name
Test status
Simulation time 8393727336 ps
CPU time 7.14 seconds
Started Mar 31 01:48:19 PM PDT 24
Finished Mar 31 01:48:26 PM PDT 24
Peak memory 204120 kb
Host smart-bf742306-cd9d-43f3-af2f-c6e0beff54b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25452
50399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2545250399
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.3637303645
Short name T813
Test name
Test status
Simulation time 8411812484 ps
CPU time 7.47 seconds
Started Mar 31 01:48:22 PM PDT 24
Finished Mar 31 01:48:30 PM PDT 24
Peak memory 204068 kb
Host smart-eaf925bf-e3d9-41be-93cc-34565bebfb55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36373
03645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.3637303645
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.3840080762
Short name T766
Test name
Test status
Simulation time 8364957195 ps
CPU time 7.56 seconds
Started Mar 31 01:48:19 PM PDT 24
Finished Mar 31 01:48:26 PM PDT 24
Peak memory 204072 kb
Host smart-4a952de9-410c-4fa4-b325-4cc914b1cad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38400
80762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.3840080762
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.285267
Short name T936
Test name
Test status
Simulation time 8400586262 ps
CPU time 7.54 seconds
Started Mar 31 01:48:18 PM PDT 24
Finished Mar 31 01:48:26 PM PDT 24
Peak memory 204112 kb
Host smart-b06891b0-9032-4eb7-8c85-86884111acd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28526
7 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.285267
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2324368857
Short name T553
Test name
Test status
Simulation time 8370524391 ps
CPU time 7.35 seconds
Started Mar 31 01:48:19 PM PDT 24
Finished Mar 31 01:48:27 PM PDT 24
Peak memory 204108 kb
Host smart-552fc8e2-1eb3-4d22-8147-6f6955a82406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23243
68857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2324368857
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.564430864
Short name T454
Test name
Test status
Simulation time 28888270 ps
CPU time 0.65 seconds
Started Mar 31 01:48:22 PM PDT 24
Finished Mar 31 01:48:23 PM PDT 24
Peak memory 204032 kb
Host smart-9e350789-eca4-4055-a90d-fb8c3b8e79fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56443
0864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.564430864
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3586496814
Short name T185
Test name
Test status
Simulation time 26782432911 ps
CPU time 50.57 seconds
Started Mar 31 01:48:21 PM PDT 24
Finished Mar 31 01:49:11 PM PDT 24
Peak memory 204356 kb
Host smart-22cebc52-3062-419e-839f-7676bdfabbca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35864
96814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3586496814
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.2638095689
Short name T1032
Test name
Test status
Simulation time 8387111521 ps
CPU time 7.17 seconds
Started Mar 31 01:48:20 PM PDT 24
Finished Mar 31 01:48:27 PM PDT 24
Peak memory 204100 kb
Host smart-127e81aa-4e28-4c58-92df-f05710850d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26380
95689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.2638095689
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.1444624778
Short name T449
Test name
Test status
Simulation time 8429221140 ps
CPU time 7.23 seconds
Started Mar 31 01:48:19 PM PDT 24
Finished Mar 31 01:48:26 PM PDT 24
Peak memory 204124 kb
Host smart-864edd9d-5ba5-4c76-a730-e862a211d511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14446
24778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.1444624778
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.2111775636
Short name T228
Test name
Test status
Simulation time 8400993899 ps
CPU time 7.39 seconds
Started Mar 31 01:48:19 PM PDT 24
Finished Mar 31 01:48:27 PM PDT 24
Peak memory 204104 kb
Host smart-7a82e5f8-1e8f-4faf-a7c8-2869231801e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21117
75636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.2111775636
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.2641089216
Short name T860
Test name
Test status
Simulation time 8356909169 ps
CPU time 8.15 seconds
Started Mar 31 01:48:19 PM PDT 24
Finished Mar 31 01:48:27 PM PDT 24
Peak memory 204140 kb
Host smart-cacfafdb-23d9-4dca-b2ee-07c1d5366f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26410
89216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.2641089216
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.3620808639
Short name T473
Test name
Test status
Simulation time 8461107322 ps
CPU time 7.32 seconds
Started Mar 31 01:48:20 PM PDT 24
Finished Mar 31 01:48:27 PM PDT 24
Peak memory 204100 kb
Host smart-3c3523ab-4389-4b70-8f2e-ee99176a5c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36208
08639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.3620808639
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.4266064412
Short name T712
Test name
Test status
Simulation time 8382981944 ps
CPU time 7.44 seconds
Started Mar 31 01:48:19 PM PDT 24
Finished Mar 31 01:48:26 PM PDT 24
Peak memory 204108 kb
Host smart-b6ba93f6-b9ab-45db-80b4-bb16bc4c41b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42660
64412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.4266064412
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.in_iso.3111600026
Short name T459
Test name
Test status
Simulation time 8413410477 ps
CPU time 9.02 seconds
Started Mar 31 01:48:44 PM PDT 24
Finished Mar 31 01:48:53 PM PDT 24
Peak memory 204180 kb
Host smart-a2858b86-6422-4f28-b53c-68b7a96c646a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31116
00026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.in_iso.3111600026
Directory /workspace/15.in_iso/latest

Test location /workspace/coverage/default/15.phy_config_usb_ref_disable.3036136565
Short name T368
Test name
Test status
Simulation time 8362914752 ps
CPU time 7.78 seconds
Started Mar 31 01:48:34 PM PDT 24
Finished Mar 31 01:48:42 PM PDT 24
Peak memory 204084 kb
Host smart-821dd9d7-f817-4ca6-89e4-e667c683dde3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30361
36565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.phy_config_usb_ref_disable.3036136565
Directory /workspace/15.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.752432525
Short name T366
Test name
Test status
Simulation time 8368539794 ps
CPU time 8.41 seconds
Started Mar 31 01:48:27 PM PDT 24
Finished Mar 31 01:48:36 PM PDT 24
Peak memory 204112 kb
Host smart-3cf0d70b-ca7e-44d4-9d16-f571fa7e41e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75243
2525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.752432525
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_enable.3975418289
Short name T970
Test name
Test status
Simulation time 8372791165 ps
CPU time 7.56 seconds
Started Mar 31 01:48:26 PM PDT 24
Finished Mar 31 01:48:34 PM PDT 24
Peak memory 204140 kb
Host smart-62197b00-f92e-4196-9206-a1ba76af06b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39754
18289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.3975418289
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.3214850095
Short name T568
Test name
Test status
Simulation time 66808121 ps
CPU time 1.72 seconds
Started Mar 31 01:48:25 PM PDT 24
Finished Mar 31 01:48:27 PM PDT 24
Peak memory 204208 kb
Host smart-c713b36c-d219-4f2c-8610-2bb25f987e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32148
50095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.3214850095
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.1430468612
Short name T887
Test name
Test status
Simulation time 8450708756 ps
CPU time 7.5 seconds
Started Mar 31 01:48:29 PM PDT 24
Finished Mar 31 01:48:37 PM PDT 24
Peak memory 204140 kb
Host smart-4c2e3899-da5c-4b34-8f69-3ceda1dc3133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14304
68612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.1430468612
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.292666240
Short name T373
Test name
Test status
Simulation time 8408887294 ps
CPU time 8.6 seconds
Started Mar 31 01:48:28 PM PDT 24
Finished Mar 31 01:48:37 PM PDT 24
Peak memory 204144 kb
Host smart-2a5ab3a4-1857-413e-8100-b686a09eb53b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29266
6240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.292666240
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.1869444882
Short name T237
Test name
Test status
Simulation time 8362920639 ps
CPU time 7.45 seconds
Started Mar 31 01:48:35 PM PDT 24
Finished Mar 31 01:48:43 PM PDT 24
Peak memory 204068 kb
Host smart-5b40dda6-333c-40b4-abfa-49686a857534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18694
44882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.1869444882
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3271494565
Short name T505
Test name
Test status
Simulation time 8398181795 ps
CPU time 7.48 seconds
Started Mar 31 01:48:31 PM PDT 24
Finished Mar 31 01:48:39 PM PDT 24
Peak memory 204264 kb
Host smart-d07e9131-fe5e-48ff-b98a-390e0b054dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32714
94565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3271494565
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.2959138249
Short name T1047
Test name
Test status
Simulation time 8372519078 ps
CPU time 7.66 seconds
Started Mar 31 01:48:31 PM PDT 24
Finished Mar 31 01:48:39 PM PDT 24
Peak memory 204036 kb
Host smart-a802dc4e-efb9-4fbf-8159-276595a8e009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29591
38249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.2959138249
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.3821601072
Short name T731
Test name
Test status
Simulation time 8373885215 ps
CPU time 7.99 seconds
Started Mar 31 01:48:30 PM PDT 24
Finished Mar 31 01:48:39 PM PDT 24
Peak memory 204108 kb
Host smart-1147a0dd-af3c-44ef-8d09-4b4ccca3acc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38216
01072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.3821601072
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.685168035
Short name T655
Test name
Test status
Simulation time 28448089 ps
CPU time 0.63 seconds
Started Mar 31 01:48:32 PM PDT 24
Finished Mar 31 01:48:33 PM PDT 24
Peak memory 204112 kb
Host smart-958f88f9-57e7-48ed-a6ac-55ce8b0a1b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68516
8035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.685168035
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.1353977204
Short name T402
Test name
Test status
Simulation time 28924734963 ps
CPU time 55.94 seconds
Started Mar 31 01:48:32 PM PDT 24
Finished Mar 31 01:49:28 PM PDT 24
Peak memory 204404 kb
Host smart-a3b27a05-4805-4211-b074-fb679c5baab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13539
77204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.1353977204
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.2694752962
Short name T964
Test name
Test status
Simulation time 8404297709 ps
CPU time 7.22 seconds
Started Mar 31 01:48:34 PM PDT 24
Finished Mar 31 01:48:42 PM PDT 24
Peak memory 204112 kb
Host smart-6eed2612-1ab8-4f12-82e3-155100984674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26947
52962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2694752962
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.2774601937
Short name T857
Test name
Test status
Simulation time 8442516834 ps
CPU time 7.23 seconds
Started Mar 31 01:48:32 PM PDT 24
Finished Mar 31 01:48:40 PM PDT 24
Peak memory 204128 kb
Host smart-e0454ff1-9419-4f04-bc5d-0f88ac2dfc4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27746
01937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.2774601937
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.4049486714
Short name T585
Test name
Test status
Simulation time 8406307683 ps
CPU time 9.73 seconds
Started Mar 31 01:48:34 PM PDT 24
Finished Mar 31 01:48:44 PM PDT 24
Peak memory 204076 kb
Host smart-2fe9c84d-3046-4999-8308-6e3d9ac86923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40494
86714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.4049486714
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_smoke.406815207
Short name T926
Test name
Test status
Simulation time 8474655104 ps
CPU time 7.34 seconds
Started Mar 31 01:48:27 PM PDT 24
Finished Mar 31 01:48:34 PM PDT 24
Peak memory 204092 kb
Host smart-79ba0993-a10e-412d-9fa5-9520d0adde6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40681
5207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.406815207
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.78000647
Short name T408
Test name
Test status
Simulation time 8398594922 ps
CPU time 10.07 seconds
Started Mar 31 01:48:30 PM PDT 24
Finished Mar 31 01:48:41 PM PDT 24
Peak memory 204068 kb
Host smart-60f48003-0b8c-46f1-969b-0ae0b2fd4701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78000
647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.78000647
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.phy_config_usb_ref_disable.272637061
Short name T617
Test name
Test status
Simulation time 8365594665 ps
CPU time 7.65 seconds
Started Mar 31 01:48:44 PM PDT 24
Finished Mar 31 01:48:52 PM PDT 24
Peak memory 204132 kb
Host smart-d1c838d7-5b95-4628-8dfb-73d8693917ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27263
7061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.phy_config_usb_ref_disable.272637061
Directory /workspace/16.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.1413096906
Short name T638
Test name
Test status
Simulation time 8370117807 ps
CPU time 6.99 seconds
Started Mar 31 01:48:40 PM PDT 24
Finished Mar 31 01:48:48 PM PDT 24
Peak memory 204092 kb
Host smart-3bbf76fa-fb08-4446-94d6-63c0a8e175ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14130
96906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.1413096906
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_enable.2277492637
Short name T934
Test name
Test status
Simulation time 8368170376 ps
CPU time 7.1 seconds
Started Mar 31 01:48:38 PM PDT 24
Finished Mar 31 01:48:46 PM PDT 24
Peak memory 204080 kb
Host smart-aa040c85-953a-4ac7-830f-3c6e9ee00ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22774
92637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.2277492637
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.2890516948
Short name T979
Test name
Test status
Simulation time 66377763 ps
CPU time 1.81 seconds
Started Mar 31 01:48:39 PM PDT 24
Finished Mar 31 01:48:41 PM PDT 24
Peak memory 204232 kb
Host smart-df1a053d-da6d-4f5c-bfff-18979606bd79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28905
16948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.2890516948
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.1967205014
Short name T51
Test name
Test status
Simulation time 8358819616 ps
CPU time 7.05 seconds
Started Mar 31 01:48:51 PM PDT 24
Finished Mar 31 01:48:58 PM PDT 24
Peak memory 203684 kb
Host smart-7b9446c9-d4d6-4e06-83c9-e35780e1e795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19672
05014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.1967205014
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.104060995
Short name T946
Test name
Test status
Simulation time 8458631309 ps
CPU time 7.41 seconds
Started Mar 31 01:48:40 PM PDT 24
Finished Mar 31 01:48:48 PM PDT 24
Peak memory 204096 kb
Host smart-e758ddf7-72ab-410e-924e-54e159f0b1b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10406
0995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.104060995
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.2226315688
Short name T421
Test name
Test status
Simulation time 8413062036 ps
CPU time 7.91 seconds
Started Mar 31 01:48:38 PM PDT 24
Finished Mar 31 01:48:47 PM PDT 24
Peak memory 204020 kb
Host smart-3f168d09-4087-4d20-8061-edd9dee6424b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22263
15688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.2226315688
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.2962078511
Short name T826
Test name
Test status
Simulation time 8363406766 ps
CPU time 8.16 seconds
Started Mar 31 01:48:37 PM PDT 24
Finished Mar 31 01:48:45 PM PDT 24
Peak memory 204104 kb
Host smart-34b375c8-4744-4c2f-a075-0708b7864717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29620
78511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.2962078511
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3679068491
Short name T786
Test name
Test status
Simulation time 8440894501 ps
CPU time 7.33 seconds
Started Mar 31 01:48:39 PM PDT 24
Finished Mar 31 01:48:46 PM PDT 24
Peak memory 204108 kb
Host smart-0ad2ca14-bd4b-44e5-9198-37ed43ba047b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36790
68491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3679068491
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3650291285
Short name T733
Test name
Test status
Simulation time 8371081676 ps
CPU time 7.62 seconds
Started Mar 31 01:48:40 PM PDT 24
Finished Mar 31 01:48:49 PM PDT 24
Peak memory 204088 kb
Host smart-957f45fb-7d75-41cc-8032-00c45c51d153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36502
91285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3650291285
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2427456779
Short name T715
Test name
Test status
Simulation time 8386104875 ps
CPU time 8.15 seconds
Started Mar 31 01:48:38 PM PDT 24
Finished Mar 31 01:48:46 PM PDT 24
Peak memory 204124 kb
Host smart-c9048aa9-db14-4f42-bf2c-11f8b371ad39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24274
56779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2427456779
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.12792436
Short name T526
Test name
Test status
Simulation time 27900730 ps
CPU time 0.64 seconds
Started Mar 31 01:48:45 PM PDT 24
Finished Mar 31 01:48:46 PM PDT 24
Peak memory 204040 kb
Host smart-46c590de-6c91-4994-b3da-b3161ff1978c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12792
436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.12792436
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.3193595764
Short name T956
Test name
Test status
Simulation time 17076884181 ps
CPU time 33.37 seconds
Started Mar 31 01:48:44 PM PDT 24
Finished Mar 31 01:49:18 PM PDT 24
Peak memory 204412 kb
Host smart-203fb5b2-021b-4684-9b0f-742d094b127d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31935
95764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.3193595764
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3458979817
Short name T927
Test name
Test status
Simulation time 8386973956 ps
CPU time 7.29 seconds
Started Mar 31 01:48:51 PM PDT 24
Finished Mar 31 01:48:58 PM PDT 24
Peak memory 203956 kb
Host smart-2257bb08-4410-4d5c-a0b0-06d668c03155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34589
79817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3458979817
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.2525740338
Short name T854
Test name
Test status
Simulation time 8432365311 ps
CPU time 7.56 seconds
Started Mar 31 01:48:45 PM PDT 24
Finished Mar 31 01:48:52 PM PDT 24
Peak memory 204100 kb
Host smart-ed17618a-1393-4ca8-843a-d894f0aa865c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25257
40338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.2525740338
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.2806425463
Short name T795
Test name
Test status
Simulation time 8400015158 ps
CPU time 7.86 seconds
Started Mar 31 01:48:44 PM PDT 24
Finished Mar 31 01:48:52 PM PDT 24
Peak memory 204116 kb
Host smart-76285662-f4d7-4d18-9fa0-d3253231ccbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28064
25463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.2806425463
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.2218813139
Short name T386
Test name
Test status
Simulation time 8361227524 ps
CPU time 8.7 seconds
Started Mar 31 01:48:45 PM PDT 24
Finished Mar 31 01:48:54 PM PDT 24
Peak memory 204148 kb
Host smart-4869eb23-d730-4d5b-9ea3-0c935d8bae46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22188
13139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.2218813139
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.512821905
Short name T162
Test name
Test status
Simulation time 8459643697 ps
CPU time 7.86 seconds
Started Mar 31 01:48:39 PM PDT 24
Finished Mar 31 01:48:48 PM PDT 24
Peak memory 204124 kb
Host smart-623d0895-ee1d-40a2-9721-bf25f2a011f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51282
1905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.512821905
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.3322427022
Short name T504
Test name
Test status
Simulation time 8388747935 ps
CPU time 7.25 seconds
Started Mar 31 01:48:46 PM PDT 24
Finished Mar 31 01:48:54 PM PDT 24
Peak memory 204148 kb
Host smart-be8a68d8-a48f-4329-a938-7a0be557387b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33224
27022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.3322427022
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.in_iso.3877950357
Short name T649
Test name
Test status
Simulation time 8457310056 ps
CPU time 7.5 seconds
Started Mar 31 01:48:55 PM PDT 24
Finished Mar 31 01:49:03 PM PDT 24
Peak memory 204144 kb
Host smart-d109a234-e1a0-40b0-9599-8c048a8e2276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38779
50357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.in_iso.3877950357
Directory /workspace/17.in_iso/latest

Test location /workspace/coverage/default/17.phy_config_usb_ref_disable.4264380332
Short name T456
Test name
Test status
Simulation time 8361651349 ps
CPU time 7.06 seconds
Started Mar 31 01:48:58 PM PDT 24
Finished Mar 31 01:49:05 PM PDT 24
Peak memory 204132 kb
Host smart-f5258d5e-d0c8-4186-83bb-9e2ed3473afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42643
80332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.phy_config_usb_ref_disable.4264380332
Directory /workspace/17.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.3486891182
Short name T308
Test name
Test status
Simulation time 8367929559 ps
CPU time 7.87 seconds
Started Mar 31 01:48:46 PM PDT 24
Finished Mar 31 01:48:54 PM PDT 24
Peak memory 204132 kb
Host smart-85bce4db-0658-4a26-bfed-7f9a12e0888f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34868
91182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3486891182
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_enable.1365330368
Short name T85
Test name
Test status
Simulation time 8368444076 ps
CPU time 8.06 seconds
Started Mar 31 01:48:44 PM PDT 24
Finished Mar 31 01:48:52 PM PDT 24
Peak memory 204120 kb
Host smart-e8c9b1c9-a11c-45d8-98f9-e5e7867e6eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13653
30368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.1365330368
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.1471352537
Short name T647
Test name
Test status
Simulation time 219884045 ps
CPU time 1.85 seconds
Started Mar 31 01:48:44 PM PDT 24
Finished Mar 31 01:48:46 PM PDT 24
Peak memory 204240 kb
Host smart-d44e0124-5f55-4428-bade-fc181a4b8e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14713
52537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.1471352537
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.2329124610
Short name T204
Test name
Test status
Simulation time 8362874813 ps
CPU time 8.02 seconds
Started Mar 31 01:48:59 PM PDT 24
Finished Mar 31 01:49:07 PM PDT 24
Peak memory 204076 kb
Host smart-cd28ba03-4f48-4a90-82ae-c00cbd93362c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23291
24610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2329124610
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.3190038239
Short name T156
Test name
Test status
Simulation time 8409772463 ps
CPU time 7.56 seconds
Started Mar 31 01:48:51 PM PDT 24
Finished Mar 31 01:48:59 PM PDT 24
Peak memory 204076 kb
Host smart-4eb08b68-ca70-4b3e-9f0e-4d665d58a4e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31900
38239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.3190038239
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.555105158
Short name T672
Test name
Test status
Simulation time 8407253652 ps
CPU time 7.34 seconds
Started Mar 31 01:48:52 PM PDT 24
Finished Mar 31 01:49:00 PM PDT 24
Peak memory 204116 kb
Host smart-b11f95f2-6bf4-408a-a335-8ce7545d7edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55510
5158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.555105158
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.1743834505
Short name T359
Test name
Test status
Simulation time 8369521943 ps
CPU time 7.05 seconds
Started Mar 31 01:48:51 PM PDT 24
Finished Mar 31 01:48:58 PM PDT 24
Peak memory 204144 kb
Host smart-dc6684e3-3633-40d0-b613-896e8db3fed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17438
34505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.1743834505
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.374298904
Short name T865
Test name
Test status
Simulation time 8377643830 ps
CPU time 7.08 seconds
Started Mar 31 01:48:52 PM PDT 24
Finished Mar 31 01:48:59 PM PDT 24
Peak memory 204128 kb
Host smart-048c0605-4a5c-4822-ab01-89f39a8a7b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37429
8904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.374298904
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.547994998
Short name T496
Test name
Test status
Simulation time 8371571534 ps
CPU time 7.56 seconds
Started Mar 31 01:48:52 PM PDT 24
Finished Mar 31 01:49:00 PM PDT 24
Peak memory 204152 kb
Host smart-706ecd91-6046-4e5f-a53c-5b133515e30f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54799
4998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.547994998
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.4158952092
Short name T416
Test name
Test status
Simulation time 28788905 ps
CPU time 0.63 seconds
Started Mar 31 01:48:56 PM PDT 24
Finished Mar 31 01:48:56 PM PDT 24
Peak memory 204068 kb
Host smart-c189d83a-9824-42fb-bfd5-3cb021936f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41589
52092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.4158952092
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.1550647764
Short name T215
Test name
Test status
Simulation time 23886818384 ps
CPU time 42.74 seconds
Started Mar 31 01:48:51 PM PDT 24
Finished Mar 31 01:49:34 PM PDT 24
Peak memory 204336 kb
Host smart-76229c0c-9e59-40cf-96fb-1556993ef8f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15506
47764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.1550647764
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.2707831480
Short name T1018
Test name
Test status
Simulation time 8396730207 ps
CPU time 7.33 seconds
Started Mar 31 01:48:51 PM PDT 24
Finished Mar 31 01:48:58 PM PDT 24
Peak memory 204140 kb
Host smart-3f024220-9717-409a-9e23-bb636722ee9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27078
31480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.2707831480
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.3791198019
Short name T898
Test name
Test status
Simulation time 8454307578 ps
CPU time 8.24 seconds
Started Mar 31 01:48:50 PM PDT 24
Finished Mar 31 01:48:59 PM PDT 24
Peak memory 204124 kb
Host smart-914ff5bc-c488-4556-827d-a41e7cf15f66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37911
98019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.3791198019
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.651761435
Short name T1068
Test name
Test status
Simulation time 8409906536 ps
CPU time 8.29 seconds
Started Mar 31 01:48:51 PM PDT 24
Finished Mar 31 01:49:00 PM PDT 24
Peak memory 204096 kb
Host smart-3d0dfdc3-e431-4233-a147-6df33bcc4fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65176
1435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.651761435
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.2320990300
Short name T924
Test name
Test status
Simulation time 8356306709 ps
CPU time 8.45 seconds
Started Mar 31 01:48:52 PM PDT 24
Finished Mar 31 01:49:01 PM PDT 24
Peak memory 204124 kb
Host smart-0dcc5c56-8343-46ee-8202-dee574ead2ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23209
90300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2320990300
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.3531852144
Short name T594
Test name
Test status
Simulation time 8396474181 ps
CPU time 7.31 seconds
Started Mar 31 01:48:57 PM PDT 24
Finished Mar 31 01:49:04 PM PDT 24
Peak memory 204156 kb
Host smart-371720fb-a42c-4f65-9072-1f1011717d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35318
52144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.3531852144
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.in_iso.1219050131
Short name T636
Test name
Test status
Simulation time 8431998185 ps
CPU time 9.86 seconds
Started Mar 31 01:49:04 PM PDT 24
Finished Mar 31 01:49:14 PM PDT 24
Peak memory 204100 kb
Host smart-e89936ee-d62a-403d-9f84-4431dc54f528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12190
50131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.in_iso.1219050131
Directory /workspace/18.in_iso/latest

Test location /workspace/coverage/default/18.phy_config_usb_ref_disable.3273307999
Short name T915
Test name
Test status
Simulation time 8363807382 ps
CPU time 7.22 seconds
Started Mar 31 01:49:04 PM PDT 24
Finished Mar 31 01:49:11 PM PDT 24
Peak memory 204072 kb
Host smart-262f0f2d-5a2b-4df6-af3c-a6aa8b7bbffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32733
07999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.phy_config_usb_ref_disable.3273307999
Directory /workspace/18.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.3537884859
Short name T815
Test name
Test status
Simulation time 8374366382 ps
CPU time 7.03 seconds
Started Mar 31 01:49:00 PM PDT 24
Finished Mar 31 01:49:07 PM PDT 24
Peak memory 204144 kb
Host smart-8789f11b-aa84-4aef-9083-fa542f066021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35378
84859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.3537884859
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_enable.4051111801
Short name T751
Test name
Test status
Simulation time 8371401415 ps
CPU time 7.23 seconds
Started Mar 31 01:48:57 PM PDT 24
Finished Mar 31 01:49:05 PM PDT 24
Peak memory 204176 kb
Host smart-3dc71e4b-8f58-4073-bd02-b5eda5492edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40511
11801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.4051111801
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.484656846
Short name T500
Test name
Test status
Simulation time 141896651 ps
CPU time 1.69 seconds
Started Mar 31 01:48:59 PM PDT 24
Finished Mar 31 01:49:01 PM PDT 24
Peak memory 204304 kb
Host smart-fdc590e7-67ff-4eb0-a312-56897ace3139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48465
6846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.484656846
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.3802940491
Short name T792
Test name
Test status
Simulation time 8361916697 ps
CPU time 7.99 seconds
Started Mar 31 01:49:04 PM PDT 24
Finished Mar 31 01:49:12 PM PDT 24
Peak memory 204076 kb
Host smart-671a05dc-e9ab-4044-bff2-e1685d36d24a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38029
40491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3802940491
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.1564925345
Short name T19
Test name
Test status
Simulation time 8412580691 ps
CPU time 7.72 seconds
Started Mar 31 01:48:59 PM PDT 24
Finished Mar 31 01:49:07 PM PDT 24
Peak memory 204140 kb
Host smart-db005e7a-244b-43d2-91d5-923e031630c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15649
25345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.1564925345
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.2456894740
Short name T705
Test name
Test status
Simulation time 8409969222 ps
CPU time 7.51 seconds
Started Mar 31 01:48:57 PM PDT 24
Finished Mar 31 01:49:05 PM PDT 24
Peak memory 204116 kb
Host smart-f582e277-c79a-40f6-b005-5df50d636e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24568
94740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.2456894740
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.2025179347
Short name T645
Test name
Test status
Simulation time 8366395605 ps
CPU time 7.53 seconds
Started Mar 31 01:48:58 PM PDT 24
Finished Mar 31 01:49:05 PM PDT 24
Peak memory 204136 kb
Host smart-a2911cbd-d0b4-4bc4-a39a-e82dcaff8080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20251
79347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.2025179347
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.2673505709
Short name T114
Test name
Test status
Simulation time 8437806943 ps
CPU time 8.97 seconds
Started Mar 31 01:48:59 PM PDT 24
Finished Mar 31 01:49:08 PM PDT 24
Peak memory 204076 kb
Host smart-bb30d9a4-ae44-406a-899b-46ab5f04c84a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26735
05709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2673505709
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.2741900050
Short name T740
Test name
Test status
Simulation time 8388807088 ps
CPU time 8.25 seconds
Started Mar 31 01:48:58 PM PDT 24
Finished Mar 31 01:49:06 PM PDT 24
Peak memory 204112 kb
Host smart-7cdb9cfd-ece0-43ea-af9b-6b2cc2b235e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27419
00050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.2741900050
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1606785048
Short name T843
Test name
Test status
Simulation time 8396816002 ps
CPU time 7.67 seconds
Started Mar 31 01:48:57 PM PDT 24
Finished Mar 31 01:49:05 PM PDT 24
Peak memory 204380 kb
Host smart-c6cec17b-a600-4858-a17d-596b15516b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16067
85048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1606785048
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.1312551500
Short name T40
Test name
Test status
Simulation time 23125124 ps
CPU time 0.63 seconds
Started Mar 31 01:49:03 PM PDT 24
Finished Mar 31 01:49:04 PM PDT 24
Peak memory 204072 kb
Host smart-f5722a2f-4902-416f-914d-79f286b8d4fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13125
51500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.1312551500
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.599822156
Short name T98
Test name
Test status
Simulation time 21513336028 ps
CPU time 42.44 seconds
Started Mar 31 01:48:58 PM PDT 24
Finished Mar 31 01:49:40 PM PDT 24
Peak memory 204444 kb
Host smart-b5c0d437-fed0-47a1-8223-febc513dc9e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59982
2156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.599822156
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.580200429
Short name T91
Test name
Test status
Simulation time 8399278357 ps
CPU time 7.11 seconds
Started Mar 31 01:48:59 PM PDT 24
Finished Mar 31 01:49:06 PM PDT 24
Peak memory 204104 kb
Host smart-d67deb64-c06b-43ff-8370-643e583bfb1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58020
0429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.580200429
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.3221134517
Short name T1050
Test name
Test status
Simulation time 8417709060 ps
CPU time 8.68 seconds
Started Mar 31 01:49:06 PM PDT 24
Finished Mar 31 01:49:14 PM PDT 24
Peak memory 204100 kb
Host smart-153797a5-71ac-4eff-a605-705dd1ae1102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32211
34517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.3221134517
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.4020769986
Short name T1019
Test name
Test status
Simulation time 8389726602 ps
CPU time 7.17 seconds
Started Mar 31 01:49:04 PM PDT 24
Finished Mar 31 01:49:11 PM PDT 24
Peak memory 204128 kb
Host smart-c10f15cb-ad96-4206-ab8b-86235fe3c7f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40207
69986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.4020769986
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.3555769933
Short name T602
Test name
Test status
Simulation time 8361204878 ps
CPU time 8.03 seconds
Started Mar 31 01:49:04 PM PDT 24
Finished Mar 31 01:49:12 PM PDT 24
Peak memory 204128 kb
Host smart-de274e5c-7b69-4975-8160-a57adea0dde2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35557
69933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.3555769933
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.61826357
Short name T724
Test name
Test status
Simulation time 8437114124 ps
CPU time 7.75 seconds
Started Mar 31 01:48:57 PM PDT 24
Finished Mar 31 01:49:05 PM PDT 24
Peak memory 204104 kb
Host smart-b8be259d-d30e-44fa-a418-d9110f566d37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61826
357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.61826357
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.3000947795
Short name T910
Test name
Test status
Simulation time 8381172784 ps
CPU time 7.46 seconds
Started Mar 31 01:49:03 PM PDT 24
Finished Mar 31 01:49:11 PM PDT 24
Peak memory 204152 kb
Host smart-2caa851b-ad42-40cc-96d1-b9ee90fae688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30009
47795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.3000947795
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.in_iso.3755953115
Short name T630
Test name
Test status
Simulation time 8370505975 ps
CPU time 7.37 seconds
Started Mar 31 01:49:14 PM PDT 24
Finished Mar 31 01:49:21 PM PDT 24
Peak memory 204104 kb
Host smart-0455e168-fecf-422f-98c7-0d2abe2946f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37559
53115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.in_iso.3755953115
Directory /workspace/19.in_iso/latest

Test location /workspace/coverage/default/19.phy_config_usb_ref_disable.3715901682
Short name T777
Test name
Test status
Simulation time 8361794426 ps
CPU time 7.16 seconds
Started Mar 31 01:49:10 PM PDT 24
Finished Mar 31 01:49:17 PM PDT 24
Peak memory 204144 kb
Host smart-9edbfcfa-b7aa-48ab-b44b-e24e6abec933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37159
01682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.phy_config_usb_ref_disable.3715901682
Directory /workspace/19.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.4219737364
Short name T653
Test name
Test status
Simulation time 8373038180 ps
CPU time 8 seconds
Started Mar 31 01:49:02 PM PDT 24
Finished Mar 31 01:49:10 PM PDT 24
Peak memory 204100 kb
Host smart-3bd63ecd-7aaa-44c7-8fc3-25cffaf21f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42197
37364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.4219737364
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_enable.436134294
Short name T1060
Test name
Test status
Simulation time 8372705450 ps
CPU time 7.72 seconds
Started Mar 31 01:49:03 PM PDT 24
Finished Mar 31 01:49:10 PM PDT 24
Peak memory 204128 kb
Host smart-e54f759e-c880-41a7-91a2-057d757fdde8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43613
4294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.436134294
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.735152761
Short name T1039
Test name
Test status
Simulation time 160539463 ps
CPU time 1.59 seconds
Started Mar 31 01:49:01 PM PDT 24
Finished Mar 31 01:49:03 PM PDT 24
Peak memory 204304 kb
Host smart-c761c4b4-7ec3-4870-ab66-ac04ab3bdaaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73515
2761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.735152761
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.1848038550
Short name T220
Test name
Test status
Simulation time 8364084157 ps
CPU time 7.01 seconds
Started Mar 31 01:49:17 PM PDT 24
Finished Mar 31 01:49:24 PM PDT 24
Peak memory 204144 kb
Host smart-d59a7b93-dd34-46d8-92b8-6890f329dff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18480
38550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.1848038550
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.3494171466
Short name T688
Test name
Test status
Simulation time 8393176783 ps
CPU time 9.26 seconds
Started Mar 31 01:49:02 PM PDT 24
Finished Mar 31 01:49:12 PM PDT 24
Peak memory 204104 kb
Host smart-4246ab9b-2a35-45c3-829a-17e00c29be2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34941
71466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.3494171466
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.409036250
Short name T694
Test name
Test status
Simulation time 8412420017 ps
CPU time 7.83 seconds
Started Mar 31 01:49:03 PM PDT 24
Finished Mar 31 01:49:11 PM PDT 24
Peak memory 204156 kb
Host smart-5e5ce988-9ceb-4379-9c1c-285a8f12e2a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40903
6250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.409036250
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.552767457
Short name T933
Test name
Test status
Simulation time 8365991270 ps
CPU time 7.42 seconds
Started Mar 31 01:49:03 PM PDT 24
Finished Mar 31 01:49:10 PM PDT 24
Peak memory 204128 kb
Host smart-a81fb50d-337a-4cbb-b690-4a68695895ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55276
7457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.552767457
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.2004322513
Short name T295
Test name
Test status
Simulation time 8379984330 ps
CPU time 7.72 seconds
Started Mar 31 01:49:10 PM PDT 24
Finished Mar 31 01:49:18 PM PDT 24
Peak memory 204136 kb
Host smart-5a139a80-ad2f-44f4-a3b7-bd4eae27062b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20043
22513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2004322513
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.1648281316
Short name T311
Test name
Test status
Simulation time 8386783873 ps
CPU time 8.55 seconds
Started Mar 31 01:49:09 PM PDT 24
Finished Mar 31 01:49:17 PM PDT 24
Peak memory 204120 kb
Host smart-5324da25-d5f5-480f-a548-bece73a957c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16482
81316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.1648281316
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.931627943
Short name T801
Test name
Test status
Simulation time 28455853 ps
CPU time 0.6 seconds
Started Mar 31 01:49:09 PM PDT 24
Finished Mar 31 01:49:10 PM PDT 24
Peak memory 204048 kb
Host smart-f83eab5c-1973-4735-b9e7-1fe546ad0d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93162
7943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.931627943
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.2963297566
Short name T779
Test name
Test status
Simulation time 25228332945 ps
CPU time 45.37 seconds
Started Mar 31 01:49:10 PM PDT 24
Finished Mar 31 01:49:55 PM PDT 24
Peak memory 204332 kb
Host smart-c1cd069f-2304-4f9b-8496-bd552f4dbc0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29632
97566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.2963297566
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.1009263022
Short name T388
Test name
Test status
Simulation time 8406257424 ps
CPU time 7.23 seconds
Started Mar 31 01:49:09 PM PDT 24
Finished Mar 31 01:49:17 PM PDT 24
Peak memory 204112 kb
Host smart-5129dce4-25a1-42de-9d45-4bda116c53be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10092
63022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.1009263022
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.2311135737
Short name T973
Test name
Test status
Simulation time 8437856489 ps
CPU time 7.44 seconds
Started Mar 31 01:49:11 PM PDT 24
Finished Mar 31 01:49:18 PM PDT 24
Peak memory 204012 kb
Host smart-d3058b49-7eee-4f00-88d4-eb7e5fb5e5a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23111
35737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.2311135737
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.2190309608
Short name T536
Test name
Test status
Simulation time 8408284913 ps
CPU time 9.13 seconds
Started Mar 31 01:49:11 PM PDT 24
Finished Mar 31 01:49:20 PM PDT 24
Peak memory 204084 kb
Host smart-e87ee580-c752-420d-a91c-8b80c9229d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21903
09608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.2190309608
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.27158705
Short name T806
Test name
Test status
Simulation time 8358126292 ps
CPU time 9.41 seconds
Started Mar 31 01:49:08 PM PDT 24
Finished Mar 31 01:49:18 PM PDT 24
Peak memory 204120 kb
Host smart-8ce3788b-de00-41d9-9199-970ec63d6435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27158
705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.27158705
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.2450249536
Short name T794
Test name
Test status
Simulation time 8396448741 ps
CPU time 7.57 seconds
Started Mar 31 01:49:09 PM PDT 24
Finished Mar 31 01:49:17 PM PDT 24
Peak memory 204152 kb
Host smart-ebe12dd7-47f4-497f-9983-7e8e22b236ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24502
49536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.2450249536
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.in_iso.1751607778
Short name T1003
Test name
Test status
Simulation time 8422841200 ps
CPU time 7.59 seconds
Started Mar 31 01:45:40 PM PDT 24
Finished Mar 31 01:45:47 PM PDT 24
Peak memory 204108 kb
Host smart-1e4cd90d-c622-45e7-9256-636b00aaff8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17516
07778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.in_iso.1751607778
Directory /workspace/2.in_iso/latest

Test location /workspace/coverage/default/2.phy_config_usb_ref_disable.573960385
Short name T899
Test name
Test status
Simulation time 8359036310 ps
CPU time 7.56 seconds
Started Mar 31 01:45:30 PM PDT 24
Finished Mar 31 01:45:38 PM PDT 24
Peak memory 204080 kb
Host smart-f036ebcc-da81-46f4-aa80-6fe3d5d55052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57396
0385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.phy_config_usb_ref_disable.573960385
Directory /workspace/2.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.3316960127
Short name T891
Test name
Test status
Simulation time 8370337827 ps
CPU time 7.67 seconds
Started Mar 31 01:45:18 PM PDT 24
Finished Mar 31 01:45:26 PM PDT 24
Peak memory 204064 kb
Host smart-ced9e927-4b1d-435f-a910-c288f6ee5071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33169
60127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.3316960127
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_enable.578591748
Short name T951
Test name
Test status
Simulation time 8371274336 ps
CPU time 7.32 seconds
Started Mar 31 01:45:19 PM PDT 24
Finished Mar 31 01:45:27 PM PDT 24
Peak memory 204108 kb
Host smart-d5485cca-8d6d-4323-aa56-8a6c9cb1be78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57859
1748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.578591748
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.4017170914
Short name T928
Test name
Test status
Simulation time 176188950 ps
CPU time 1.93 seconds
Started Mar 31 01:45:18 PM PDT 24
Finished Mar 31 01:45:21 PM PDT 24
Peak memory 204280 kb
Host smart-9bb03d90-27f3-48f7-b506-28c579ca1d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40171
70914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.4017170914
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.2776862202
Short name T217
Test name
Test status
Simulation time 8357319632 ps
CPU time 7.69 seconds
Started Mar 31 01:45:37 PM PDT 24
Finished Mar 31 01:45:45 PM PDT 24
Peak memory 204108 kb
Host smart-1c5c5f35-3b07-4646-b93c-44050347f0b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27768
62202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2776862202
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.3303302813
Short name T825
Test name
Test status
Simulation time 8392483715 ps
CPU time 9.23 seconds
Started Mar 31 01:45:18 PM PDT 24
Finished Mar 31 01:45:28 PM PDT 24
Peak memory 204132 kb
Host smart-96cbcee6-8200-4586-9d65-e63020acf1ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33033
02813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.3303302813
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.3694548994
Short name T356
Test name
Test status
Simulation time 8404813480 ps
CPU time 7.34 seconds
Started Mar 31 01:45:16 PM PDT 24
Finished Mar 31 01:45:24 PM PDT 24
Peak memory 204152 kb
Host smart-ae37aa4b-ebe2-482c-8b96-37e07d0effcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36945
48994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.3694548994
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.2064519164
Short name T847
Test name
Test status
Simulation time 8365290231 ps
CPU time 7.55 seconds
Started Mar 31 01:45:18 PM PDT 24
Finished Mar 31 01:45:26 PM PDT 24
Peak memory 204080 kb
Host smart-6c99acdf-a41d-4ace-9ac5-a7c404eb376b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20645
19164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.2064519164
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.1064248914
Short name T126
Test name
Test status
Simulation time 8402133129 ps
CPU time 7.46 seconds
Started Mar 31 01:45:19 PM PDT 24
Finished Mar 31 01:45:27 PM PDT 24
Peak memory 204068 kb
Host smart-13f2279b-8570-46ca-943b-2ddbac3e1974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10642
48914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.1064248914
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.2347241466
Short name T614
Test name
Test status
Simulation time 8388590497 ps
CPU time 8.06 seconds
Started Mar 31 01:45:18 PM PDT 24
Finished Mar 31 01:45:27 PM PDT 24
Peak memory 204144 kb
Host smart-b56a5aa5-f6af-4860-a187-596c43db1eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23472
41466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.2347241466
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2818162381
Short name T778
Test name
Test status
Simulation time 8377298053 ps
CPU time 8 seconds
Started Mar 31 01:45:18 PM PDT 24
Finished Mar 31 01:45:26 PM PDT 24
Peak memory 204104 kb
Host smart-8e93ed35-a99c-4d06-b8cb-38c329337bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28181
62381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2818162381
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2111109575
Short name T519
Test name
Test status
Simulation time 25972350 ps
CPU time 0.63 seconds
Started Mar 31 01:45:29 PM PDT 24
Finished Mar 31 01:45:30 PM PDT 24
Peak memory 204076 kb
Host smart-d38ede0f-a712-4f75-bf79-543bbc46a38b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21111
09575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2111109575
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.4111390124
Short name T958
Test name
Test status
Simulation time 14935961943 ps
CPU time 25.5 seconds
Started Mar 31 01:45:26 PM PDT 24
Finished Mar 31 01:45:51 PM PDT 24
Peak memory 204332 kb
Host smart-80d224f4-4696-4a6c-9003-426290a234fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41113
90124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.4111390124
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.822725146
Short name T315
Test name
Test status
Simulation time 8395910912 ps
CPU time 8.18 seconds
Started Mar 31 01:45:25 PM PDT 24
Finished Mar 31 01:45:33 PM PDT 24
Peak memory 204092 kb
Host smart-17831a43-9442-4574-9586-6b0599961f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82272
5146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.822725146
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.2979890109
Short name T1026
Test name
Test status
Simulation time 8418617570 ps
CPU time 7.03 seconds
Started Mar 31 01:45:23 PM PDT 24
Finished Mar 31 01:45:30 PM PDT 24
Peak memory 204136 kb
Host smart-3912c57c-7ca0-4b34-b3be-459318959a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29798
90109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2979890109
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.3175902913
Short name T87
Test name
Test status
Simulation time 8398783682 ps
CPU time 7.76 seconds
Started Mar 31 01:45:24 PM PDT 24
Finished Mar 31 01:45:32 PM PDT 24
Peak memory 204120 kb
Host smart-3d2c3300-028f-4c54-a84d-ba1a7604b271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31759
02913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.3175902913
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.489303904
Short name T77
Test name
Test status
Simulation time 110406053 ps
CPU time 0.93 seconds
Started Mar 31 01:45:44 PM PDT 24
Finished Mar 31 01:45:45 PM PDT 24
Peak memory 220040 kb
Host smart-f27d65ee-ecb8-4a60-92e5-4964f317e445
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=489303904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.489303904
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.497478661
Short name T23
Test name
Test status
Simulation time 8360503886 ps
CPU time 7.52 seconds
Started Mar 31 01:45:24 PM PDT 24
Finished Mar 31 01:45:32 PM PDT 24
Peak memory 204108 kb
Host smart-4ed11bda-3c8a-4394-a176-cd7332c8f1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49747
8661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.497478661
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.1159818083
Short name T329
Test name
Test status
Simulation time 8370434813 ps
CPU time 7.66 seconds
Started Mar 31 01:45:31 PM PDT 24
Finished Mar 31 01:45:39 PM PDT 24
Peak memory 204104 kb
Host smart-f6fa7282-1f87-48d3-ae1d-d66aea7ec6ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11598
18083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.1159818083
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.in_iso.885076065
Short name T966
Test name
Test status
Simulation time 8418400813 ps
CPU time 7.73 seconds
Started Mar 31 01:49:20 PM PDT 24
Finished Mar 31 01:49:28 PM PDT 24
Peak memory 204128 kb
Host smart-e2e63e80-0719-4a84-90c5-b882e0b94525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88507
6065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.in_iso.885076065
Directory /workspace/20.in_iso/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.18507049
Short name T244
Test name
Test status
Simulation time 8371012535 ps
CPU time 7.19 seconds
Started Mar 31 01:49:16 PM PDT 24
Finished Mar 31 01:49:23 PM PDT 24
Peak memory 204096 kb
Host smart-3a7c3cbd-4280-4100-9e3d-522cb11ff07e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18507
049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.18507049
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_enable.1024593741
Short name T959
Test name
Test status
Simulation time 8367969746 ps
CPU time 7.22 seconds
Started Mar 31 01:49:17 PM PDT 24
Finished Mar 31 01:49:24 PM PDT 24
Peak memory 204092 kb
Host smart-dfce6f5f-9e40-47c9-9bf1-8524d6b60fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10245
93741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1024593741
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.3339324679
Short name T430
Test name
Test status
Simulation time 162477465 ps
CPU time 1.49 seconds
Started Mar 31 01:49:14 PM PDT 24
Finished Mar 31 01:49:16 PM PDT 24
Peak memory 204232 kb
Host smart-073b3d0b-ea17-4b86-b00b-b09862a0a97d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33393
24679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.3339324679
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.2136480902
Short name T824
Test name
Test status
Simulation time 8360827298 ps
CPU time 7.27 seconds
Started Mar 31 01:49:20 PM PDT 24
Finished Mar 31 01:49:27 PM PDT 24
Peak memory 204104 kb
Host smart-04d3aafb-4ec7-431b-a7db-1821e46d2529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21364
80902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.2136480902
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.3876688420
Short name T155
Test name
Test status
Simulation time 8387816516 ps
CPU time 8.21 seconds
Started Mar 31 01:49:15 PM PDT 24
Finished Mar 31 01:49:23 PM PDT 24
Peak memory 204100 kb
Host smart-a7dfd9b6-ec1a-4a8b-9ead-2a6f689a09c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38766
88420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.3876688420
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.2761545131
Short name T551
Test name
Test status
Simulation time 8411169101 ps
CPU time 7.21 seconds
Started Mar 31 01:49:15 PM PDT 24
Finished Mar 31 01:49:22 PM PDT 24
Peak memory 204108 kb
Host smart-c54def76-b88d-426c-8023-c3a6492cc16c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27615
45131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.2761545131
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.685480973
Short name T991
Test name
Test status
Simulation time 8367404806 ps
CPU time 7.6 seconds
Started Mar 31 01:49:20 PM PDT 24
Finished Mar 31 01:49:27 PM PDT 24
Peak memory 204100 kb
Host smart-16c606ca-866d-439c-af4f-cf3c6771718f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68548
0973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.685480973
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.545990782
Short name T132
Test name
Test status
Simulation time 8395773999 ps
CPU time 8.21 seconds
Started Mar 31 01:49:20 PM PDT 24
Finished Mar 31 01:49:28 PM PDT 24
Peak memory 204268 kb
Host smart-e8731cae-2c5b-40e3-87a0-e54e226623fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54599
0782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.545990782
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.2761650763
Short name T962
Test name
Test status
Simulation time 8387528394 ps
CPU time 7.56 seconds
Started Mar 31 01:49:21 PM PDT 24
Finished Mar 31 01:49:29 PM PDT 24
Peak memory 204128 kb
Host smart-fa473525-dc7f-462a-9980-a76c46bb21b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27616
50763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.2761650763
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.2146748812
Short name T542
Test name
Test status
Simulation time 8402447532 ps
CPU time 8.17 seconds
Started Mar 31 01:49:22 PM PDT 24
Finished Mar 31 01:49:30 PM PDT 24
Peak memory 204104 kb
Host smart-b316d967-5831-4e64-b3fb-4ed20f27391d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21467
48812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.2146748812
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.2394408378
Short name T482
Test name
Test status
Simulation time 31944907 ps
CPU time 0.67 seconds
Started Mar 31 01:49:22 PM PDT 24
Finished Mar 31 01:49:23 PM PDT 24
Peak memory 204036 kb
Host smart-69a31cd9-1838-4897-a1ff-16e8f3c62fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23944
08378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.2394408378
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.4254219400
Short name T823
Test name
Test status
Simulation time 30484008666 ps
CPU time 68.05 seconds
Started Mar 31 01:49:24 PM PDT 24
Finished Mar 31 01:50:32 PM PDT 24
Peak memory 204408 kb
Host smart-6f1e3960-cbaa-4690-a4f1-641ed457807a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42542
19400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.4254219400
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.3359637386
Short name T1005
Test name
Test status
Simulation time 8369903670 ps
CPU time 7.85 seconds
Started Mar 31 01:49:25 PM PDT 24
Finished Mar 31 01:49:33 PM PDT 24
Peak memory 204128 kb
Host smart-4e48ae9f-e412-49f0-90be-1a4ed81b447c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33596
37386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.3359637386
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.4188954995
Short name T1036
Test name
Test status
Simulation time 8390929680 ps
CPU time 7.57 seconds
Started Mar 31 01:49:22 PM PDT 24
Finished Mar 31 01:49:30 PM PDT 24
Peak memory 204068 kb
Host smart-4e33d9cc-05e7-4087-ab32-04c5a3dedb76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41889
54995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.4188954995
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.4141756010
Short name T997
Test name
Test status
Simulation time 8398265850 ps
CPU time 9.71 seconds
Started Mar 31 01:49:21 PM PDT 24
Finished Mar 31 01:49:31 PM PDT 24
Peak memory 204136 kb
Host smart-a5fb38e4-e66e-44fd-b702-75679e49f951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41417
56010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.4141756010
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.2224809046
Short name T317
Test name
Test status
Simulation time 8357471043 ps
CPU time 9.76 seconds
Started Mar 31 01:49:22 PM PDT 24
Finished Mar 31 01:49:32 PM PDT 24
Peak memory 204104 kb
Host smart-bd1a4e2a-b62c-48aa-9ede-ebf99322ac5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22248
09046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.2224809046
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1186136478
Short name T763
Test name
Test status
Simulation time 8454081411 ps
CPU time 8.92 seconds
Started Mar 31 01:49:14 PM PDT 24
Finished Mar 31 01:49:23 PM PDT 24
Peak memory 204112 kb
Host smart-f878f0d4-764d-42e8-92a4-e8f0ba0191ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11861
36478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1186136478
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.1069965766
Short name T522
Test name
Test status
Simulation time 8379649570 ps
CPU time 7.65 seconds
Started Mar 31 01:49:20 PM PDT 24
Finished Mar 31 01:49:28 PM PDT 24
Peak memory 204084 kb
Host smart-3226ea8f-1713-4bdf-ba8f-e4743bfc1aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10699
65766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.1069965766
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.in_iso.2288144471
Short name T627
Test name
Test status
Simulation time 8375008025 ps
CPU time 7.53 seconds
Started Mar 31 01:49:35 PM PDT 24
Finished Mar 31 01:49:42 PM PDT 24
Peak memory 204128 kb
Host smart-8850af52-a56a-4c6c-ad0f-908f8e153a34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22881
44471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.in_iso.2288144471
Directory /workspace/21.in_iso/latest

Test location /workspace/coverage/default/21.phy_config_usb_ref_disable.3433107652
Short name T1052
Test name
Test status
Simulation time 8361706771 ps
CPU time 8.12 seconds
Started Mar 31 01:49:33 PM PDT 24
Finished Mar 31 01:49:41 PM PDT 24
Peak memory 204116 kb
Host smart-26e6b49e-4dae-4b2b-822f-9831eadca148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34331
07652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.phy_config_usb_ref_disable.3433107652
Directory /workspace/21.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.1756120288
Short name T557
Test name
Test status
Simulation time 8370309191 ps
CPU time 6.94 seconds
Started Mar 31 01:49:19 PM PDT 24
Finished Mar 31 01:49:26 PM PDT 24
Peak memory 204144 kb
Host smart-09b7395c-2b91-414d-9d3f-f658384a5cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17561
20288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.1756120288
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_enable.1175192662
Short name T817
Test name
Test status
Simulation time 8373875301 ps
CPU time 8.35 seconds
Started Mar 31 01:49:23 PM PDT 24
Finished Mar 31 01:49:31 PM PDT 24
Peak memory 204144 kb
Host smart-b3fcf323-9298-403b-9d66-391a6af461d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11751
92662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.1175192662
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.459578003
Short name T988
Test name
Test status
Simulation time 104182541 ps
CPU time 1.32 seconds
Started Mar 31 01:49:28 PM PDT 24
Finished Mar 31 01:49:30 PM PDT 24
Peak memory 204212 kb
Host smart-3a408b33-6c50-44d8-b10e-a8c8def066c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45957
8003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.459578003
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.1194666104
Short name T900
Test name
Test status
Simulation time 8360954857 ps
CPU time 7.83 seconds
Started Mar 31 01:49:35 PM PDT 24
Finished Mar 31 01:49:43 PM PDT 24
Peak memory 204132 kb
Host smart-02120f79-f746-44f9-935a-035929fd2829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11946
66104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.1194666104
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.532296871
Short name T20
Test name
Test status
Simulation time 8403150272 ps
CPU time 8.95 seconds
Started Mar 31 01:49:27 PM PDT 24
Finished Mar 31 01:49:36 PM PDT 24
Peak memory 204092 kb
Host smart-08e04083-b563-4740-a120-8510407a7685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53229
6871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.532296871
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.423754191
Short name T692
Test name
Test status
Simulation time 8406270302 ps
CPU time 7.69 seconds
Started Mar 31 01:49:27 PM PDT 24
Finished Mar 31 01:49:35 PM PDT 24
Peak memory 204136 kb
Host smart-81f3e6c4-0fa7-4bd1-aa62-4a96ac89b453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42375
4191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.423754191
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.799087926
Short name T1079
Test name
Test status
Simulation time 8364587929 ps
CPU time 8.33 seconds
Started Mar 31 01:49:26 PM PDT 24
Finished Mar 31 01:49:35 PM PDT 24
Peak memory 204068 kb
Host smart-b34a9520-5cd7-4106-8be2-a104840696e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79908
7926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.799087926
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3345674567
Short name T134
Test name
Test status
Simulation time 8427257704 ps
CPU time 8.94 seconds
Started Mar 31 01:49:27 PM PDT 24
Finished Mar 31 01:49:36 PM PDT 24
Peak memory 204112 kb
Host smart-90745bc7-2c94-474c-8339-599494ae41a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33456
74567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3345674567
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.301676025
Short name T931
Test name
Test status
Simulation time 8392295585 ps
CPU time 9.45 seconds
Started Mar 31 01:49:32 PM PDT 24
Finished Mar 31 01:49:42 PM PDT 24
Peak memory 204136 kb
Host smart-260b2e3b-986d-46ee-8c9d-41c41cd8eda3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30167
6025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.301676025
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.2848079154
Short name T314
Test name
Test status
Simulation time 8396436683 ps
CPU time 7.46 seconds
Started Mar 31 01:49:27 PM PDT 24
Finished Mar 31 01:49:35 PM PDT 24
Peak memory 204112 kb
Host smart-b024217a-38cb-4509-8b90-e211c8699781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28480
79154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.2848079154
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.1629614754
Short name T44
Test name
Test status
Simulation time 29130800 ps
CPU time 0.69 seconds
Started Mar 31 01:49:34 PM PDT 24
Finished Mar 31 01:49:35 PM PDT 24
Peak memory 204080 kb
Host smart-cd8051d3-64aa-485a-b184-7e1eec9ed6ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16296
14754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.1629614754
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.852476619
Short name T633
Test name
Test status
Simulation time 25434430023 ps
CPU time 47.43 seconds
Started Mar 31 01:49:28 PM PDT 24
Finished Mar 31 01:50:15 PM PDT 24
Peak memory 204296 kb
Host smart-d3690bc1-d8cc-4c6a-902e-6909442009a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85247
6619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.852476619
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.3667225366
Short name T702
Test name
Test status
Simulation time 8396937275 ps
CPU time 7.67 seconds
Started Mar 31 01:49:28 PM PDT 24
Finished Mar 31 01:49:36 PM PDT 24
Peak memory 204172 kb
Host smart-e38d7773-8e8c-4fa4-9441-153e0cb93f02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36672
25366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.3667225366
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.2269861666
Short name T809
Test name
Test status
Simulation time 8433893372 ps
CPU time 7.16 seconds
Started Mar 31 01:49:29 PM PDT 24
Finished Mar 31 01:49:36 PM PDT 24
Peak memory 204012 kb
Host smart-29bdbbaf-42fb-49fd-8318-3b66e4ea6c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22698
61666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.2269861666
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.2688037122
Short name T591
Test name
Test status
Simulation time 8403346382 ps
CPU time 8.47 seconds
Started Mar 31 01:49:26 PM PDT 24
Finished Mar 31 01:49:34 PM PDT 24
Peak memory 204128 kb
Host smart-9d161b88-8867-4f1f-bd4c-279db1ffadff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26880
37122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.2688037122
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1087195357
Short name T589
Test name
Test status
Simulation time 8363987781 ps
CPU time 7.72 seconds
Started Mar 31 01:49:32 PM PDT 24
Finished Mar 31 01:49:40 PM PDT 24
Peak memory 204136 kb
Host smart-680d924f-5085-47b1-8c16-26dfdb9408ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10871
95357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1087195357
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1296790322
Short name T182
Test name
Test status
Simulation time 8443947726 ps
CPU time 7.52 seconds
Started Mar 31 01:49:21 PM PDT 24
Finished Mar 31 01:49:28 PM PDT 24
Peak memory 204124 kb
Host smart-6250dda6-1e89-4a08-85b5-24ba752ef49c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12967
90322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1296790322
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.1645724106
Short name T302
Test name
Test status
Simulation time 8365929617 ps
CPU time 7.6 seconds
Started Mar 31 01:49:33 PM PDT 24
Finished Mar 31 01:49:40 PM PDT 24
Peak memory 204112 kb
Host smart-c4d5edaa-c0f1-4cc1-a72f-f96a4ee0aff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16457
24106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.1645724106
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.in_iso.2777009455
Short name T1062
Test name
Test status
Simulation time 8401047194 ps
CPU time 8.21 seconds
Started Mar 31 01:49:39 PM PDT 24
Finished Mar 31 01:49:47 PM PDT 24
Peak memory 204120 kb
Host smart-ac1e8e20-1a03-4bed-8cb7-b7d74f63ff23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27770
09455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.in_iso.2777009455
Directory /workspace/22.in_iso/latest

Test location /workspace/coverage/default/22.phy_config_usb_ref_disable.2372517066
Short name T28
Test name
Test status
Simulation time 8362422451 ps
CPU time 9.83 seconds
Started Mar 31 01:49:41 PM PDT 24
Finished Mar 31 01:49:51 PM PDT 24
Peak memory 204124 kb
Host smart-a4606f55-120d-4826-8022-342953b2c803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23725
17066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.phy_config_usb_ref_disable.2372517066
Directory /workspace/22.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.4175598724
Short name T773
Test name
Test status
Simulation time 8367998911 ps
CPU time 7.32 seconds
Started Mar 31 01:49:34 PM PDT 24
Finished Mar 31 01:49:41 PM PDT 24
Peak memory 204140 kb
Host smart-9f0a5155-5e8c-40b1-be77-abe38707d356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41755
98724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.4175598724
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_enable.359358730
Short name T447
Test name
Test status
Simulation time 8366208554 ps
CPU time 9.44 seconds
Started Mar 31 01:49:33 PM PDT 24
Finished Mar 31 01:49:43 PM PDT 24
Peak memory 204108 kb
Host smart-beb0a11a-b166-44d8-aac8-f2e86f54b45c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35935
8730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.359358730
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.1727327005
Short name T728
Test name
Test status
Simulation time 166351243 ps
CPU time 1.79 seconds
Started Mar 31 01:49:35 PM PDT 24
Finished Mar 31 01:49:37 PM PDT 24
Peak memory 204312 kb
Host smart-e0b2a4c5-2594-41bc-9a89-457a2b6c98e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17273
27005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1727327005
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.1774539248
Short name T206
Test name
Test status
Simulation time 8358162558 ps
CPU time 7.29 seconds
Started Mar 31 01:49:43 PM PDT 24
Finished Mar 31 01:49:51 PM PDT 24
Peak memory 204104 kb
Host smart-3f9a1a69-18d5-461b-b2be-26464f203dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17745
39248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.1774539248
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.2573192176
Short name T943
Test name
Test status
Simulation time 8409352038 ps
CPU time 8.37 seconds
Started Mar 31 01:49:34 PM PDT 24
Finished Mar 31 01:49:43 PM PDT 24
Peak memory 204120 kb
Host smart-ebfa0e09-f8b3-4976-80e9-2f11c85552fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25731
92176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.2573192176
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.1617134568
Short name T893
Test name
Test status
Simulation time 8407559950 ps
CPU time 7.18 seconds
Started Mar 31 01:49:37 PM PDT 24
Finished Mar 31 01:49:44 PM PDT 24
Peak memory 204156 kb
Host smart-18f79e81-5f9a-4ad4-97d5-d08f3724d2b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16171
34568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.1617134568
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.2952926652
Short name T1081
Test name
Test status
Simulation time 8369012543 ps
CPU time 7.34 seconds
Started Mar 31 01:49:32 PM PDT 24
Finished Mar 31 01:49:40 PM PDT 24
Peak memory 204104 kb
Host smart-3ca019d1-2753-4762-ade5-eb84f2922b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29529
26652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.2952926652
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.2773874438
Short name T1059
Test name
Test status
Simulation time 8430051499 ps
CPU time 8.97 seconds
Started Mar 31 01:49:34 PM PDT 24
Finished Mar 31 01:49:43 PM PDT 24
Peak memory 204116 kb
Host smart-45d3e951-2607-480b-b14f-a251d2874465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27738
74438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.2773874438
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2121861061
Short name T745
Test name
Test status
Simulation time 8364479667 ps
CPU time 9.45 seconds
Started Mar 31 01:49:45 PM PDT 24
Finished Mar 31 01:49:54 PM PDT 24
Peak memory 204100 kb
Host smart-64b40221-b3ed-483f-a5ae-0ac682b74c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21218
61061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2121861061
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.291204459
Short name T759
Test name
Test status
Simulation time 8374610130 ps
CPU time 6.99 seconds
Started Mar 31 01:49:40 PM PDT 24
Finished Mar 31 01:49:47 PM PDT 24
Peak memory 204156 kb
Host smart-77d95f09-d819-40ef-a6d3-620fba062521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29120
4459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.291204459
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.1119116196
Short name T890
Test name
Test status
Simulation time 27567882 ps
CPU time 0.64 seconds
Started Mar 31 01:49:40 PM PDT 24
Finished Mar 31 01:49:40 PM PDT 24
Peak memory 204044 kb
Host smart-f8ca4a92-0ad1-48bd-9537-d74f6e5040c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11191
16196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.1119116196
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.2847892298
Short name T675
Test name
Test status
Simulation time 20870449523 ps
CPU time 38.41 seconds
Started Mar 31 01:49:40 PM PDT 24
Finished Mar 31 01:50:18 PM PDT 24
Peak memory 204420 kb
Host smart-696caa4b-b5d9-4aab-9455-0f4a2c321c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28478
92298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.2847892298
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.17861263
Short name T998
Test name
Test status
Simulation time 8396209268 ps
CPU time 7.15 seconds
Started Mar 31 01:49:40 PM PDT 24
Finished Mar 31 01:49:47 PM PDT 24
Peak memory 204124 kb
Host smart-4a7292a5-05a6-4feb-b4a4-0ba8c8df7be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17861
263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.17861263
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.1532721627
Short name T613
Test name
Test status
Simulation time 8399653239 ps
CPU time 7.55 seconds
Started Mar 31 01:49:40 PM PDT 24
Finished Mar 31 01:49:48 PM PDT 24
Peak memory 204140 kb
Host smart-41956ca6-7231-4346-85b3-b0e980e1578f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15327
21627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1532721627
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.2777740462
Short name T874
Test name
Test status
Simulation time 8402512573 ps
CPU time 9.74 seconds
Started Mar 31 01:49:44 PM PDT 24
Finished Mar 31 01:49:54 PM PDT 24
Peak memory 204112 kb
Host smart-8b623011-a3ab-4e41-9db0-cae768cb437b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27777
40462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.2777740462
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1571000635
Short name T624
Test name
Test status
Simulation time 8361690940 ps
CPU time 8.27 seconds
Started Mar 31 01:49:44 PM PDT 24
Finished Mar 31 01:49:52 PM PDT 24
Peak memory 204136 kb
Host smart-b3459641-2998-4304-9656-074385754fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15710
00635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1571000635
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.18338248
Short name T513
Test name
Test status
Simulation time 8395136596 ps
CPU time 7.71 seconds
Started Mar 31 01:49:39 PM PDT 24
Finished Mar 31 01:49:47 PM PDT 24
Peak memory 204372 kb
Host smart-0bc15ec0-5293-4e07-9ab5-d7e01fe8fd31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18338
248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.18338248
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.in_iso.1188593657
Short name T324
Test name
Test status
Simulation time 8439857492 ps
CPU time 7.66 seconds
Started Mar 31 01:49:48 PM PDT 24
Finished Mar 31 01:49:56 PM PDT 24
Peak memory 204104 kb
Host smart-d5ab8c13-2e01-401a-af53-d2e0b2b64cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11885
93657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.in_iso.1188593657
Directory /workspace/23.in_iso/latest

Test location /workspace/coverage/default/23.phy_config_usb_ref_disable.256317671
Short name T719
Test name
Test status
Simulation time 8361266736 ps
CPU time 7.78 seconds
Started Mar 31 01:49:47 PM PDT 24
Finished Mar 31 01:49:55 PM PDT 24
Peak memory 204132 kb
Host smart-a13f93c6-f176-488d-bef3-017202e82e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25631
7671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.phy_config_usb_ref_disable.256317671
Directory /workspace/23.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.663188137
Short name T888
Test name
Test status
Simulation time 8366477465 ps
CPU time 8.36 seconds
Started Mar 31 01:49:39 PM PDT 24
Finished Mar 31 01:49:48 PM PDT 24
Peak memory 204080 kb
Host smart-494a4317-f682-46f3-afcf-1939a2b01060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66318
8137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.663188137
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_enable.3396516565
Short name T965
Test name
Test status
Simulation time 8369934978 ps
CPU time 8.34 seconds
Started Mar 31 01:49:40 PM PDT 24
Finished Mar 31 01:49:48 PM PDT 24
Peak memory 204176 kb
Host smart-cd06bad7-b408-48aa-8fb9-13ef75edf10e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33965
16565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.3396516565
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3583936433
Short name T494
Test name
Test status
Simulation time 185708809 ps
CPU time 1.68 seconds
Started Mar 31 01:49:41 PM PDT 24
Finished Mar 31 01:49:44 PM PDT 24
Peak memory 204232 kb
Host smart-5923ab7f-d11d-4a28-b088-a602268fecde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35839
36433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3583936433
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.634116171
Short name T584
Test name
Test status
Simulation time 8386710309 ps
CPU time 7.57 seconds
Started Mar 31 01:49:39 PM PDT 24
Finished Mar 31 01:49:47 PM PDT 24
Peak memory 204140 kb
Host smart-47477b1b-2bb1-40b8-ba9a-68d8053cf8ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63411
6171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.634116171
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.2158900468
Short name T1083
Test name
Test status
Simulation time 8409760910 ps
CPU time 7.75 seconds
Started Mar 31 01:49:39 PM PDT 24
Finished Mar 31 01:49:46 PM PDT 24
Peak memory 204152 kb
Host smart-6eb00870-0c50-41da-90ff-9aa55f526d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21589
00468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.2158900468
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3674215965
Short name T391
Test name
Test status
Simulation time 8365189489 ps
CPU time 7.24 seconds
Started Mar 31 01:49:41 PM PDT 24
Finished Mar 31 01:49:48 PM PDT 24
Peak memory 204120 kb
Host smart-879cc779-be9a-4e50-8e9b-6b2a514df829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36742
15965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3674215965
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.4186552781
Short name T1010
Test name
Test status
Simulation time 8412098688 ps
CPU time 7.19 seconds
Started Mar 31 01:49:45 PM PDT 24
Finished Mar 31 01:49:53 PM PDT 24
Peak memory 204016 kb
Host smart-49633a82-8509-4ec7-b5a8-ca50107c80b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41865
52781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.4186552781
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2654331920
Short name T913
Test name
Test status
Simulation time 8385526142 ps
CPU time 7.19 seconds
Started Mar 31 01:49:49 PM PDT 24
Finished Mar 31 01:49:57 PM PDT 24
Peak memory 204080 kb
Host smart-e4f82bc4-4b91-4a36-b1a4-c5b01f2179d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26543
31920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2654331920
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.916582401
Short name T361
Test name
Test status
Simulation time 8386012696 ps
CPU time 7.46 seconds
Started Mar 31 01:49:46 PM PDT 24
Finished Mar 31 01:49:54 PM PDT 24
Peak memory 204128 kb
Host smart-956d8b95-6c10-4359-8055-20430c410a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91658
2401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.916582401
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.1242427452
Short name T338
Test name
Test status
Simulation time 25417815 ps
CPU time 0.69 seconds
Started Mar 31 01:49:49 PM PDT 24
Finished Mar 31 01:49:50 PM PDT 24
Peak memory 204052 kb
Host smart-2e621ff4-8b5e-4dca-ac67-202e3b067356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12424
27452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.1242427452
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.1384167422
Short name T846
Test name
Test status
Simulation time 28814574784 ps
CPU time 57.8 seconds
Started Mar 31 01:49:50 PM PDT 24
Finished Mar 31 01:50:49 PM PDT 24
Peak memory 204368 kb
Host smart-8708e0a7-5407-466f-b295-a2b291ed2bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13841
67422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.1384167422
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.4287528838
Short name T298
Test name
Test status
Simulation time 8367889805 ps
CPU time 9.22 seconds
Started Mar 31 01:49:44 PM PDT 24
Finished Mar 31 01:49:54 PM PDT 24
Peak memory 204132 kb
Host smart-c8a0ae0e-c705-42c4-8343-1ae0b1abaccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42875
28838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.4287528838
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.4165263271
Short name T477
Test name
Test status
Simulation time 8446411138 ps
CPU time 8.53 seconds
Started Mar 31 01:49:50 PM PDT 24
Finished Mar 31 01:49:59 PM PDT 24
Peak memory 204080 kb
Host smart-2d1d5cf8-3a72-47e4-ac54-88f7aa2edbb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41652
63271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.4165263271
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.3817999898
Short name T83
Test name
Test status
Simulation time 8392937266 ps
CPU time 8.26 seconds
Started Mar 31 01:49:48 PM PDT 24
Finished Mar 31 01:49:57 PM PDT 24
Peak memory 204120 kb
Host smart-776fd6b6-6758-4544-8a24-42ece32b6183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38179
99898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.3817999898
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.1164644230
Short name T524
Test name
Test status
Simulation time 8355601041 ps
CPU time 7.39 seconds
Started Mar 31 01:49:46 PM PDT 24
Finished Mar 31 01:49:54 PM PDT 24
Peak memory 204096 kb
Host smart-b0f1815e-09b8-409c-bee4-fb38d78c37ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11646
44230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.1164644230
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.273352875
Short name T95
Test name
Test status
Simulation time 8422202126 ps
CPU time 7.57 seconds
Started Mar 31 01:49:40 PM PDT 24
Finished Mar 31 01:49:48 PM PDT 24
Peak memory 204096 kb
Host smart-ea6dffd3-5289-499e-be0a-c4a3aa5c8af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27335
2875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.273352875
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.931192020
Short name T82
Test name
Test status
Simulation time 8364234280 ps
CPU time 8.45 seconds
Started Mar 31 01:49:45 PM PDT 24
Finished Mar 31 01:49:53 PM PDT 24
Peak memory 204104 kb
Host smart-da34807c-1321-4ad9-89cb-d9276e0a19d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93119
2020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.931192020
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.in_iso.984130515
Short name T985
Test name
Test status
Simulation time 8443002084 ps
CPU time 7.18 seconds
Started Mar 31 01:49:53 PM PDT 24
Finished Mar 31 01:50:01 PM PDT 24
Peak memory 204124 kb
Host smart-e85e204b-0cb5-4e1e-b21a-fdbbb9897a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98413
0515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.in_iso.984130515
Directory /workspace/24.in_iso/latest

Test location /workspace/coverage/default/24.phy_config_usb_ref_disable.3824345648
Short name T996
Test name
Test status
Simulation time 8360380553 ps
CPU time 7.86 seconds
Started Mar 31 01:49:52 PM PDT 24
Finished Mar 31 01:50:00 PM PDT 24
Peak memory 204068 kb
Host smart-4d65509d-66bc-47a1-a717-d5d8c506cb09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38243
45648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.phy_config_usb_ref_disable.3824345648
Directory /workspace/24.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3546072915
Short name T942
Test name
Test status
Simulation time 8370919698 ps
CPU time 7.18 seconds
Started Mar 31 01:49:47 PM PDT 24
Finished Mar 31 01:49:54 PM PDT 24
Peak memory 204136 kb
Host smart-daf64af6-f6b7-4736-a327-6e4bf42237cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35460
72915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3546072915
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.36340817
Short name T358
Test name
Test status
Simulation time 233211487 ps
CPU time 1.94 seconds
Started Mar 31 01:49:44 PM PDT 24
Finished Mar 31 01:49:47 PM PDT 24
Peak memory 204280 kb
Host smart-3bc9c298-48ef-4ffe-a499-8c82984d09ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36340
817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.36340817
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.167794497
Short name T202
Test name
Test status
Simulation time 8361924798 ps
CPU time 7.68 seconds
Started Mar 31 01:49:53 PM PDT 24
Finished Mar 31 01:50:01 PM PDT 24
Peak memory 204164 kb
Host smart-7d34eb77-f0d3-4646-93b3-32518485b85c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16779
4497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.167794497
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.4068004797
Short name T732
Test name
Test status
Simulation time 8423858808 ps
CPU time 8.7 seconds
Started Mar 31 01:49:46 PM PDT 24
Finished Mar 31 01:49:55 PM PDT 24
Peak memory 204128 kb
Host smart-0b23a739-c428-4670-9dd2-1a79f75d50e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40680
04797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.4068004797
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.1271800561
Short name T422
Test name
Test status
Simulation time 8409795956 ps
CPU time 7.26 seconds
Started Mar 31 01:49:48 PM PDT 24
Finished Mar 31 01:49:55 PM PDT 24
Peak memory 204068 kb
Host smart-1897fc7c-0867-46c5-8b01-df410df1e045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12718
00561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.1271800561
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3632555148
Short name T897
Test name
Test status
Simulation time 8365937034 ps
CPU time 6.95 seconds
Started Mar 31 01:49:47 PM PDT 24
Finished Mar 31 01:49:54 PM PDT 24
Peak memory 204080 kb
Host smart-e53591e4-0aa5-4690-a2e7-e19f37cecfb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36325
55148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3632555148
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.2932194884
Short name T706
Test name
Test status
Simulation time 8423482815 ps
CPU time 7.45 seconds
Started Mar 31 01:49:46 PM PDT 24
Finished Mar 31 01:49:54 PM PDT 24
Peak memory 204144 kb
Host smart-7e3f9178-36f7-4dbd-a54b-ef3e80106ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29321
94884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.2932194884
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.154668440
Short name T334
Test name
Test status
Simulation time 8363662187 ps
CPU time 7.64 seconds
Started Mar 31 01:49:46 PM PDT 24
Finished Mar 31 01:49:54 PM PDT 24
Peak memory 204128 kb
Host smart-3b354720-5062-4f98-9b4f-af0e92cf0d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15466
8440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.154668440
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.936172189
Short name T601
Test name
Test status
Simulation time 8393661291 ps
CPU time 7.03 seconds
Started Mar 31 01:49:46 PM PDT 24
Finished Mar 31 01:49:53 PM PDT 24
Peak memory 204168 kb
Host smart-b16c6931-b79e-43b0-a7e5-593125b93541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93617
2189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.936172189
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.1992108688
Short name T490
Test name
Test status
Simulation time 24648987 ps
CPU time 0.64 seconds
Started Mar 31 01:49:53 PM PDT 24
Finished Mar 31 01:49:54 PM PDT 24
Peak memory 204092 kb
Host smart-2267ec86-ac66-4389-a947-af8e8c399d73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19921
08688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.1992108688
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.2399591691
Short name T747
Test name
Test status
Simulation time 14415901354 ps
CPU time 25.57 seconds
Started Mar 31 01:49:52 PM PDT 24
Finished Mar 31 01:50:18 PM PDT 24
Peak memory 204364 kb
Host smart-612839aa-cd14-4a05-bdf2-e9e0556addc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23995
91691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2399591691
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1717918919
Short name T428
Test name
Test status
Simulation time 8411615370 ps
CPU time 7.81 seconds
Started Mar 31 01:49:52 PM PDT 24
Finished Mar 31 01:50:00 PM PDT 24
Peak memory 204148 kb
Host smart-4de60f2e-100f-40c4-8818-67d202f6bb99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17179
18919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1717918919
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.308573752
Short name T141
Test name
Test status
Simulation time 8422257954 ps
CPU time 8.88 seconds
Started Mar 31 01:49:54 PM PDT 24
Finished Mar 31 01:50:03 PM PDT 24
Peak memory 204112 kb
Host smart-9a48f4dd-7580-492e-945a-be53f017d998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30857
3752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.308573752
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.1954184058
Short name T398
Test name
Test status
Simulation time 8411616078 ps
CPU time 8.6 seconds
Started Mar 31 01:49:53 PM PDT 24
Finished Mar 31 01:50:02 PM PDT 24
Peak memory 204044 kb
Host smart-927fac40-cedf-482c-a636-b8bb9b0b169d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19541
84058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.1954184058
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2170546610
Short name T352
Test name
Test status
Simulation time 8355544650 ps
CPU time 7.17 seconds
Started Mar 31 01:49:53 PM PDT 24
Finished Mar 31 01:50:00 PM PDT 24
Peak memory 204140 kb
Host smart-7bd3f052-61a9-4964-bdf2-df6e68b6a997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21705
46610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2170546610
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.33005139
Short name T406
Test name
Test status
Simulation time 8390895403 ps
CPU time 7.35 seconds
Started Mar 31 01:49:53 PM PDT 24
Finished Mar 31 01:50:00 PM PDT 24
Peak memory 204148 kb
Host smart-70f0b982-c33e-4910-9e93-24a50d927241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33005
139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.33005139
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.in_iso.76492088
Short name T683
Test name
Test status
Simulation time 8439059019 ps
CPU time 7.69 seconds
Started Mar 31 01:50:05 PM PDT 24
Finished Mar 31 01:50:13 PM PDT 24
Peak memory 204136 kb
Host smart-f9d31b88-2e65-4130-9625-de78e400639e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76492
088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.in_iso.76492088
Directory /workspace/25.in_iso/latest

Test location /workspace/coverage/default/25.phy_config_usb_ref_disable.3586435343
Short name T949
Test name
Test status
Simulation time 8364033819 ps
CPU time 9.05 seconds
Started Mar 31 01:50:03 PM PDT 24
Finished Mar 31 01:50:13 PM PDT 24
Peak memory 204108 kb
Host smart-43ac4dc7-1336-4adc-8193-a1a268d5f1b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35864
35343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.phy_config_usb_ref_disable.3586435343
Directory /workspace/25.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.1556908051
Short name T925
Test name
Test status
Simulation time 8366431131 ps
CPU time 9.09 seconds
Started Mar 31 01:49:55 PM PDT 24
Finished Mar 31 01:50:04 PM PDT 24
Peak memory 204076 kb
Host smart-044da50c-df28-4a63-ba40-a3af263ddcd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15569
08051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.1556908051
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_enable.3081792347
Short name T1017
Test name
Test status
Simulation time 8368636903 ps
CPU time 7.35 seconds
Started Mar 31 01:50:00 PM PDT 24
Finished Mar 31 01:50:08 PM PDT 24
Peak memory 204140 kb
Host smart-9c3bd82d-c3da-49e4-b5b0-a474ce552959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30817
92347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3081792347
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.3056470645
Short name T908
Test name
Test status
Simulation time 177371391 ps
CPU time 1.63 seconds
Started Mar 31 01:49:58 PM PDT 24
Finished Mar 31 01:50:00 PM PDT 24
Peak memory 204276 kb
Host smart-e28465ec-c1e8-4834-9a44-ca0515878cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30564
70645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.3056470645
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.679522837
Short name T207
Test name
Test status
Simulation time 8362036692 ps
CPU time 7.77 seconds
Started Mar 31 01:50:05 PM PDT 24
Finished Mar 31 01:50:13 PM PDT 24
Peak memory 204132 kb
Host smart-c28dde42-11fa-402e-9e20-27b966f5ce2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67952
2837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.679522837
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3404062395
Short name T628
Test name
Test status
Simulation time 8372403602 ps
CPU time 7.62 seconds
Started Mar 31 01:50:00 PM PDT 24
Finished Mar 31 01:50:08 PM PDT 24
Peak memory 204144 kb
Host smart-58a459bb-6ade-4322-87d2-50eeb6d531fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34040
62395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3404062395
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.752287042
Short name T307
Test name
Test status
Simulation time 8410253428 ps
CPU time 7.78 seconds
Started Mar 31 01:49:59 PM PDT 24
Finished Mar 31 01:50:07 PM PDT 24
Peak memory 204080 kb
Host smart-3bf6cea4-b2a2-4ac4-a919-c81089d12390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75228
7042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.752287042
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.2612159297
Short name T349
Test name
Test status
Simulation time 8367390671 ps
CPU time 9.12 seconds
Started Mar 31 01:50:01 PM PDT 24
Finished Mar 31 01:50:10 PM PDT 24
Peak memory 204068 kb
Host smart-db6a941b-2757-4a26-b181-83b3265f95e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26121
59297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.2612159297
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1745626773
Short name T738
Test name
Test status
Simulation time 8410028875 ps
CPU time 9.07 seconds
Started Mar 31 01:49:58 PM PDT 24
Finished Mar 31 01:50:08 PM PDT 24
Peak memory 204116 kb
Host smart-9de4bb22-9c04-4d8f-bc69-f2db05521495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17456
26773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1745626773
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.3626211020
Short name T827
Test name
Test status
Simulation time 8382323130 ps
CPU time 7.53 seconds
Started Mar 31 01:49:57 PM PDT 24
Finished Mar 31 01:50:05 PM PDT 24
Peak memory 204012 kb
Host smart-a9cc536b-4f1e-4cb5-a5b5-c3db25a445c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36262
11020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.3626211020
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.1815541977
Short name T750
Test name
Test status
Simulation time 8385000859 ps
CPU time 7.66 seconds
Started Mar 31 01:49:58 PM PDT 24
Finished Mar 31 01:50:06 PM PDT 24
Peak memory 204052 kb
Host smart-efc267a3-2c29-400f-b614-a1b104ec3e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18155
41977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.1815541977
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2521447726
Short name T436
Test name
Test status
Simulation time 28905458 ps
CPU time 0.65 seconds
Started Mar 31 01:50:04 PM PDT 24
Finished Mar 31 01:50:05 PM PDT 24
Peak memory 204068 kb
Host smart-a1b60d6e-96f4-4582-9144-7e520d35b071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25214
47726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2521447726
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.3692919529
Short name T205
Test name
Test status
Simulation time 27223716930 ps
CPU time 51.11 seconds
Started Mar 31 01:49:59 PM PDT 24
Finished Mar 31 01:50:50 PM PDT 24
Peak memory 204380 kb
Host smart-743448ac-7684-41a3-aaea-22023c7f229c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36929
19529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.3692919529
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.2898052683
Short name T399
Test name
Test status
Simulation time 8389745212 ps
CPU time 7.83 seconds
Started Mar 31 01:49:59 PM PDT 24
Finished Mar 31 01:50:07 PM PDT 24
Peak memory 204128 kb
Host smart-007b3f07-ad7c-4f80-89e0-138d889e2b26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28980
52683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.2898052683
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.388533791
Short name T667
Test name
Test status
Simulation time 8458085938 ps
CPU time 7.28 seconds
Started Mar 31 01:49:59 PM PDT 24
Finished Mar 31 01:50:07 PM PDT 24
Peak memory 204120 kb
Host smart-a5d05b6d-c9f2-4d88-a4d4-93664a89ba40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38853
3791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.388533791
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.825139806
Short name T353
Test name
Test status
Simulation time 8389284468 ps
CPU time 7.25 seconds
Started Mar 31 01:50:00 PM PDT 24
Finished Mar 31 01:50:08 PM PDT 24
Peak memory 204144 kb
Host smart-482ee54b-059f-486e-9e79-0effcf700ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82513
9806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.825139806
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.2541066968
Short name T1080
Test name
Test status
Simulation time 8357268660 ps
CPU time 7.11 seconds
Started Mar 31 01:49:58 PM PDT 24
Finished Mar 31 01:50:06 PM PDT 24
Peak memory 204124 kb
Host smart-b0cb6838-f457-40d0-aa3c-ff3d291345b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25410
66968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.2541066968
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.1414697660
Short name T861
Test name
Test status
Simulation time 8362235815 ps
CPU time 7.49 seconds
Started Mar 31 01:50:05 PM PDT 24
Finished Mar 31 01:50:13 PM PDT 24
Peak memory 204184 kb
Host smart-5a759eaf-a191-45b4-a6e5-4bbff0dd21e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14146
97660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.1414697660
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.in_iso.3895204922
Short name T157
Test name
Test status
Simulation time 8415351078 ps
CPU time 7.74 seconds
Started Mar 31 01:50:11 PM PDT 24
Finished Mar 31 01:50:19 PM PDT 24
Peak memory 204140 kb
Host smart-9db95e59-8e3e-43b3-8c56-cd8c7f8bf0b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38952
04922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.in_iso.3895204922
Directory /workspace/26.in_iso/latest

Test location /workspace/coverage/default/26.phy_config_usb_ref_disable.3579704920
Short name T968
Test name
Test status
Simulation time 8362874406 ps
CPU time 7 seconds
Started Mar 31 01:50:11 PM PDT 24
Finished Mar 31 01:50:18 PM PDT 24
Peak memory 204100 kb
Host smart-a41e206e-0108-4937-94a0-c903020d64c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35797
04920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.phy_config_usb_ref_disable.3579704920
Directory /workspace/26.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.4135119457
Short name T485
Test name
Test status
Simulation time 8371802996 ps
CPU time 7.77 seconds
Started Mar 31 01:50:06 PM PDT 24
Finished Mar 31 01:50:15 PM PDT 24
Peak memory 204140 kb
Host smart-34e8b5c8-d36d-43df-9e59-d9c7047ffb9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41351
19457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.4135119457
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_enable.272398310
Short name T89
Test name
Test status
Simulation time 8364908530 ps
CPU time 9.55 seconds
Started Mar 31 01:50:05 PM PDT 24
Finished Mar 31 01:50:15 PM PDT 24
Peak memory 204264 kb
Host smart-546a9ba0-5994-46a0-99d3-bda65ef9c9c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27239
8310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.272398310
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.1082769678
Short name T79
Test name
Test status
Simulation time 46681213 ps
CPU time 1.25 seconds
Started Mar 31 01:50:03 PM PDT 24
Finished Mar 31 01:50:04 PM PDT 24
Peak memory 204256 kb
Host smart-3300151d-b788-4ad7-8943-b2bdd5efa7a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10827
69678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.1082769678
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.13385964
Short name T788
Test name
Test status
Simulation time 8358631227 ps
CPU time 7.48 seconds
Started Mar 31 01:50:13 PM PDT 24
Finished Mar 31 01:50:21 PM PDT 24
Peak memory 204168 kb
Host smart-7961499a-0be0-467e-a32c-45b59c253788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13385
964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.13385964
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3433578314
Short name T530
Test name
Test status
Simulation time 8387953676 ps
CPU time 7.24 seconds
Started Mar 31 01:50:05 PM PDT 24
Finished Mar 31 01:50:12 PM PDT 24
Peak memory 204128 kb
Host smart-7e43067c-3225-4118-b053-594d8fa1a1c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34335
78314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3433578314
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.2651611771
Short name T35
Test name
Test status
Simulation time 8409101659 ps
CPU time 7.49 seconds
Started Mar 31 01:50:05 PM PDT 24
Finished Mar 31 01:50:13 PM PDT 24
Peak memory 204088 kb
Host smart-0b7624a4-b5f1-479c-a2be-e3356a963b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26516
11771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.2651611771
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2240267417
Short name T842
Test name
Test status
Simulation time 8366611509 ps
CPU time 7.5 seconds
Started Mar 31 01:50:05 PM PDT 24
Finished Mar 31 01:50:13 PM PDT 24
Peak memory 204128 kb
Host smart-922d0aac-5c84-4410-8ba8-9e1b60a3d881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22402
67417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2240267417
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.1169438324
Short name T110
Test name
Test status
Simulation time 8440315798 ps
CPU time 7.41 seconds
Started Mar 31 01:50:05 PM PDT 24
Finished Mar 31 01:50:13 PM PDT 24
Peak memory 204096 kb
Host smart-8cd3e0d8-9efc-429c-80e5-446e9ed7b277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11694
38324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.1169438324
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.1991993564
Short name T629
Test name
Test status
Simulation time 8384901778 ps
CPU time 7.15 seconds
Started Mar 31 01:50:12 PM PDT 24
Finished Mar 31 01:50:19 PM PDT 24
Peak memory 204068 kb
Host smart-91f64f2a-46e9-49f6-ae54-07e7940ed051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19919
93564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.1991993564
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1404099810
Short name T546
Test name
Test status
Simulation time 8407436965 ps
CPU time 7.64 seconds
Started Mar 31 01:50:15 PM PDT 24
Finished Mar 31 01:50:22 PM PDT 24
Peak memory 204116 kb
Host smart-8830b2e4-d458-4e41-b3cb-6c8a6dbda78d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14040
99810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1404099810
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.2389848483
Short name T377
Test name
Test status
Simulation time 27167267 ps
CPU time 0.65 seconds
Started Mar 31 01:50:12 PM PDT 24
Finished Mar 31 01:50:13 PM PDT 24
Peak memory 203984 kb
Host smart-8c914e66-a542-4e68-a9d9-ead73d91642b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23898
48483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.2389848483
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3867027743
Short name T245
Test name
Test status
Simulation time 20698654749 ps
CPU time 35.03 seconds
Started Mar 31 01:50:11 PM PDT 24
Finished Mar 31 01:50:46 PM PDT 24
Peak memory 204360 kb
Host smart-9e6be8c3-2783-4d57-aea0-ed837c0a749d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38670
27743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3867027743
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.4033079445
Short name T917
Test name
Test status
Simulation time 8379629758 ps
CPU time 8.56 seconds
Started Mar 31 01:50:13 PM PDT 24
Finished Mar 31 01:50:21 PM PDT 24
Peak memory 204148 kb
Host smart-185eddb7-8d89-4e8f-9898-387a19a4dc89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40330
79445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.4033079445
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.1828143076
Short name T790
Test name
Test status
Simulation time 8376940719 ps
CPU time 7.45 seconds
Started Mar 31 01:50:12 PM PDT 24
Finished Mar 31 01:50:19 PM PDT 24
Peak memory 204068 kb
Host smart-631c3a0b-f1fa-455f-8043-46c988cca4f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18281
43076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1828143076
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.2423222168
Short name T1006
Test name
Test status
Simulation time 8365156349 ps
CPU time 7.66 seconds
Started Mar 31 01:50:12 PM PDT 24
Finished Mar 31 01:50:20 PM PDT 24
Peak memory 204084 kb
Host smart-44196224-5c88-4b2d-8410-de89620d6bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24232
22168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.2423222168
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.1282418696
Short name T873
Test name
Test status
Simulation time 8357593445 ps
CPU time 8.17 seconds
Started Mar 31 01:50:10 PM PDT 24
Finished Mar 31 01:50:18 PM PDT 24
Peak memory 204100 kb
Host smart-8be914f2-44e2-4203-840b-a52129bf5561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12824
18696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.1282418696
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.4031056056
Short name T153
Test name
Test status
Simulation time 8420455902 ps
CPU time 7.19 seconds
Started Mar 31 01:50:05 PM PDT 24
Finished Mar 31 01:50:13 PM PDT 24
Peak memory 204104 kb
Host smart-55b46fd0-f143-40de-98fc-88774cede8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40310
56056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.4031056056
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.2244832309
Short name T631
Test name
Test status
Simulation time 8398607582 ps
CPU time 9.58 seconds
Started Mar 31 01:50:12 PM PDT 24
Finished Mar 31 01:50:22 PM PDT 24
Peak memory 204096 kb
Host smart-94468ed7-f8e7-4541-be50-1803d3cda420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22448
32309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.2244832309
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.in_iso.2132876883
Short name T685
Test name
Test status
Simulation time 8445580050 ps
CPU time 7.63 seconds
Started Mar 31 01:50:18 PM PDT 24
Finished Mar 31 01:50:26 PM PDT 24
Peak memory 204140 kb
Host smart-1c977203-72e3-4eba-82f9-bc44b853ddc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21328
76883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.in_iso.2132876883
Directory /workspace/27.in_iso/latest

Test location /workspace/coverage/default/27.phy_config_usb_ref_disable.3617755634
Short name T722
Test name
Test status
Simulation time 8367391985 ps
CPU time 7.46 seconds
Started Mar 31 01:50:19 PM PDT 24
Finished Mar 31 01:50:26 PM PDT 24
Peak memory 204264 kb
Host smart-7eb6ee02-af1e-4bc7-b588-5bfe609d265b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36177
55634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.phy_config_usb_ref_disable.3617755634
Directory /workspace/27.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.939809860
Short name T392
Test name
Test status
Simulation time 8370236866 ps
CPU time 7.64 seconds
Started Mar 31 01:50:15 PM PDT 24
Finished Mar 31 01:50:22 PM PDT 24
Peak memory 204076 kb
Host smart-ca6539a9-f4ae-4042-9cd9-d2febe848cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93980
9860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.939809860
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_enable.3980188095
Short name T616
Test name
Test status
Simulation time 8367694528 ps
CPU time 7.08 seconds
Started Mar 31 01:50:13 PM PDT 24
Finished Mar 31 01:50:20 PM PDT 24
Peak memory 204124 kb
Host smart-95aeee45-ed3c-4990-a6ea-5f3855355e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39801
88095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.3980188095
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.3310711667
Short name T370
Test name
Test status
Simulation time 147890921 ps
CPU time 1.52 seconds
Started Mar 31 01:50:11 PM PDT 24
Finished Mar 31 01:50:13 PM PDT 24
Peak memory 204312 kb
Host smart-950499df-a170-4115-880e-ae189d661eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33107
11667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.3310711667
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.3485765577
Short name T957
Test name
Test status
Simulation time 8364829072 ps
CPU time 7.55 seconds
Started Mar 31 01:50:17 PM PDT 24
Finished Mar 31 01:50:25 PM PDT 24
Peak memory 204132 kb
Host smart-2f098038-4412-4c36-bf23-86e1f0fe0fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34857
65577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.3485765577
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.363361878
Short name T1064
Test name
Test status
Simulation time 8441984402 ps
CPU time 8.62 seconds
Started Mar 31 01:50:18 PM PDT 24
Finished Mar 31 01:50:27 PM PDT 24
Peak memory 204128 kb
Host smart-c39a1ae3-3311-4d6d-bcb9-5ee794520fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36336
1878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.363361878
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2851836457
Short name T365
Test name
Test status
Simulation time 8412414915 ps
CPU time 7.34 seconds
Started Mar 31 01:50:19 PM PDT 24
Finished Mar 31 01:50:27 PM PDT 24
Peak memory 204128 kb
Host smart-b41dbad5-4c2b-466b-a717-8ef919755073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28518
36457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2851836457
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.2674447948
Short name T1070
Test name
Test status
Simulation time 8370014378 ps
CPU time 7.71 seconds
Started Mar 31 01:50:20 PM PDT 24
Finished Mar 31 01:50:28 PM PDT 24
Peak memory 204068 kb
Host smart-cea4ced0-6ac6-46b2-8181-1e58582ed660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26744
47948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.2674447948
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.987478629
Short name T128
Test name
Test status
Simulation time 8421852062 ps
CPU time 7.69 seconds
Started Mar 31 01:50:18 PM PDT 24
Finished Mar 31 01:50:26 PM PDT 24
Peak memory 204104 kb
Host smart-d9995249-d46a-4a50-8fb8-309d3149168c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98747
8629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.987478629
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.444037354
Short name T812
Test name
Test status
Simulation time 8376038560 ps
CPU time 7.39 seconds
Started Mar 31 01:50:20 PM PDT 24
Finished Mar 31 01:50:28 PM PDT 24
Peak memory 204120 kb
Host smart-d84af8c0-2c14-49c2-8013-dc582e269bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44403
7354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.444037354
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.1921267364
Short name T492
Test name
Test status
Simulation time 8368838415 ps
CPU time 9.27 seconds
Started Mar 31 01:50:18 PM PDT 24
Finished Mar 31 01:50:28 PM PDT 24
Peak memory 204116 kb
Host smart-9583b7f0-1c15-4f79-9799-5041d5f3cd6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19212
67364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.1921267364
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.4139625151
Short name T930
Test name
Test status
Simulation time 27576671 ps
CPU time 0.67 seconds
Started Mar 31 01:50:20 PM PDT 24
Finished Mar 31 01:50:21 PM PDT 24
Peak memory 204092 kb
Host smart-30ae6f59-d086-43e9-bfd4-5efdad37a3aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41396
25151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.4139625151
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.2388889118
Short name T11
Test name
Test status
Simulation time 25732611842 ps
CPU time 46.69 seconds
Started Mar 31 01:50:18 PM PDT 24
Finished Mar 31 01:51:05 PM PDT 24
Peak memory 204368 kb
Host smart-d762faee-f23b-40a1-9906-777ad9269b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23888
89118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.2388889118
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.3647698260
Short name T953
Test name
Test status
Simulation time 8373889610 ps
CPU time 7.59 seconds
Started Mar 31 01:50:17 PM PDT 24
Finished Mar 31 01:50:25 PM PDT 24
Peak memory 204140 kb
Host smart-888da629-a1b7-4455-b23d-b93d409f87c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36476
98260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3647698260
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.864776791
Short name T1051
Test name
Test status
Simulation time 8386356938 ps
CPU time 7.51 seconds
Started Mar 31 01:50:19 PM PDT 24
Finished Mar 31 01:50:27 PM PDT 24
Peak memory 204140 kb
Host smart-04f3d24a-3361-47cd-b821-22548a25fbcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86477
6791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.864776791
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.1317156257
Short name T583
Test name
Test status
Simulation time 8370898510 ps
CPU time 9.78 seconds
Started Mar 31 01:50:20 PM PDT 24
Finished Mar 31 01:50:30 PM PDT 24
Peak memory 204152 kb
Host smart-3d46915e-0d17-49a5-882c-45f8fac9b3ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13171
56257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.1317156257
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.1643782717
Short name T397
Test name
Test status
Simulation time 8361729834 ps
CPU time 9.63 seconds
Started Mar 31 01:50:19 PM PDT 24
Finished Mar 31 01:50:28 PM PDT 24
Peak memory 204128 kb
Host smart-b9ee0343-96f7-42ef-b329-ed21f9e57fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16437
82717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.1643782717
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.764410149
Short name T787
Test name
Test status
Simulation time 8445993979 ps
CPU time 7.77 seconds
Started Mar 31 01:50:11 PM PDT 24
Finished Mar 31 01:50:19 PM PDT 24
Peak memory 204128 kb
Host smart-7d73da7c-fcc7-4cd2-96ce-18f3c70be720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76441
0149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.764410149
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.755571571
Short name T895
Test name
Test status
Simulation time 8371639137 ps
CPU time 8.82 seconds
Started Mar 31 01:50:20 PM PDT 24
Finished Mar 31 01:50:29 PM PDT 24
Peak memory 204180 kb
Host smart-2922a37e-af22-4b3a-88d0-3ee357c533c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75557
1571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.755571571
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.in_iso.1183928987
Short name T932
Test name
Test status
Simulation time 8432632284 ps
CPU time 7.77 seconds
Started Mar 31 01:50:27 PM PDT 24
Finished Mar 31 01:50:34 PM PDT 24
Peak memory 204052 kb
Host smart-2103de81-108f-4fd2-b743-f208349cfbd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11839
28987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.in_iso.1183928987
Directory /workspace/28.in_iso/latest

Test location /workspace/coverage/default/28.phy_config_usb_ref_disable.2083784517
Short name T678
Test name
Test status
Simulation time 8361878426 ps
CPU time 7.7 seconds
Started Mar 31 01:50:25 PM PDT 24
Finished Mar 31 01:50:33 PM PDT 24
Peak memory 204132 kb
Host smart-c5b1d8fa-c8ae-4e98-bef3-97a81228894a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20837
84517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.phy_config_usb_ref_disable.2083784517
Directory /workspace/28.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.595170153
Short name T901
Test name
Test status
Simulation time 8373217087 ps
CPU time 8.17 seconds
Started Mar 31 01:50:26 PM PDT 24
Finished Mar 31 01:50:34 PM PDT 24
Peak memory 204096 kb
Host smart-3441242a-a385-4767-a697-1c9d6be6eb0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59517
0153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.595170153
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_enable.554453967
Short name T325
Test name
Test status
Simulation time 8372759695 ps
CPU time 7.85 seconds
Started Mar 31 01:50:24 PM PDT 24
Finished Mar 31 01:50:32 PM PDT 24
Peak memory 204096 kb
Host smart-123583c0-2963-4cf4-9474-1b01a4e0bf2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55445
3967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.554453967
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.1478173087
Short name T497
Test name
Test status
Simulation time 135659133 ps
CPU time 1.3 seconds
Started Mar 31 01:50:25 PM PDT 24
Finished Mar 31 01:50:26 PM PDT 24
Peak memory 204312 kb
Host smart-9d2516b8-6d69-4ced-a631-bc96de8ee94b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14781
73087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.1478173087
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.3564657758
Short name T534
Test name
Test status
Simulation time 8360442183 ps
CPU time 7.15 seconds
Started Mar 31 01:50:26 PM PDT 24
Finished Mar 31 01:50:33 PM PDT 24
Peak memory 204092 kb
Host smart-372f6f33-775c-458a-9a3b-ccdbf58c2b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35646
57758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.3564657758
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3085974807
Short name T704
Test name
Test status
Simulation time 8389589850 ps
CPU time 7.48 seconds
Started Mar 31 01:50:27 PM PDT 24
Finished Mar 31 01:50:35 PM PDT 24
Peak memory 204144 kb
Host smart-21bd5920-721d-43e5-942f-a61c0ddddf38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30859
74807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3085974807
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.779370183
Short name T332
Test name
Test status
Simulation time 8404913225 ps
CPU time 7.83 seconds
Started Mar 31 01:50:26 PM PDT 24
Finished Mar 31 01:50:34 PM PDT 24
Peak memory 204120 kb
Host smart-ce9ec2b0-e66f-4390-8cda-331bd704caca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77937
0183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.779370183
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.2177163197
Short name T595
Test name
Test status
Simulation time 8369475675 ps
CPU time 9.02 seconds
Started Mar 31 01:50:29 PM PDT 24
Finished Mar 31 01:50:38 PM PDT 24
Peak memory 204120 kb
Host smart-bd34091c-5be4-40f7-abdb-9d08ec068cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21771
63197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.2177163197
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.674860351
Short name T1023
Test name
Test status
Simulation time 8375391128 ps
CPU time 7.37 seconds
Started Mar 31 01:50:25 PM PDT 24
Finished Mar 31 01:50:32 PM PDT 24
Peak memory 204100 kb
Host smart-72f0f361-eeff-4890-8fa3-83cd55f126f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67486
0351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.674860351
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.810775885
Short name T444
Test name
Test status
Simulation time 8389714890 ps
CPU time 7.35 seconds
Started Mar 31 01:50:25 PM PDT 24
Finished Mar 31 01:50:33 PM PDT 24
Peak memory 204148 kb
Host smart-8394ebe1-d8d8-4a8c-8e3c-d173e8fe9dd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81077
5885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.810775885
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.892099491
Short name T687
Test name
Test status
Simulation time 24542833 ps
CPU time 0.59 seconds
Started Mar 31 01:50:24 PM PDT 24
Finished Mar 31 01:50:25 PM PDT 24
Peak memory 204044 kb
Host smart-7d09b085-bc3d-4983-8998-92119482a046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89209
9491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.892099491
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.2864650371
Short name T105
Test name
Test status
Simulation time 28413000267 ps
CPU time 50.33 seconds
Started Mar 31 01:50:26 PM PDT 24
Finished Mar 31 01:51:16 PM PDT 24
Peak memory 204312 kb
Host smart-41239367-1f60-492b-9e7f-4ee320bbe687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28646
50371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.2864650371
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.1376690429
Short name T541
Test name
Test status
Simulation time 8371204845 ps
CPU time 8.22 seconds
Started Mar 31 01:50:25 PM PDT 24
Finished Mar 31 01:50:34 PM PDT 24
Peak memory 204128 kb
Host smart-5444bfef-0359-4c9e-85c7-e7002a61006c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13766
90429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.1376690429
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.1250300271
Short name T866
Test name
Test status
Simulation time 8451283908 ps
CPU time 7.57 seconds
Started Mar 31 01:50:28 PM PDT 24
Finished Mar 31 01:50:35 PM PDT 24
Peak memory 204120 kb
Host smart-add6e712-dc23-4de9-ad3e-d5723b4e2eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12503
00271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.1250300271
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.1824130742
Short name T574
Test name
Test status
Simulation time 8377551466 ps
CPU time 7.39 seconds
Started Mar 31 01:50:26 PM PDT 24
Finished Mar 31 01:50:33 PM PDT 24
Peak memory 204152 kb
Host smart-bdbc2cf2-6bc9-47f9-8957-d4ebb397a4db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18241
30742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.1824130742
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.2286885436
Short name T793
Test name
Test status
Simulation time 8356224372 ps
CPU time 8.33 seconds
Started Mar 31 01:50:27 PM PDT 24
Finished Mar 31 01:50:35 PM PDT 24
Peak memory 204108 kb
Host smart-20b79ab8-dc57-4cfd-b969-cdaee3ba4e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22868
85436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.2286885436
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3570507951
Short name T183
Test name
Test status
Simulation time 8433370322 ps
CPU time 8.77 seconds
Started Mar 31 01:50:19 PM PDT 24
Finished Mar 31 01:50:28 PM PDT 24
Peak memory 204140 kb
Host smart-fde66e2b-e716-4e89-923f-ff5deea55f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35705
07951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3570507951
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.3323809170
Short name T1020
Test name
Test status
Simulation time 8382611597 ps
CPU time 7.79 seconds
Started Mar 31 01:50:26 PM PDT 24
Finished Mar 31 01:50:34 PM PDT 24
Peak memory 204124 kb
Host smart-777024ab-a607-4d7d-84b9-51a4e75d5601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33238
09170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.3323809170
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.in_iso.1772758130
Short name T150
Test name
Test status
Simulation time 8417067811 ps
CPU time 7.6 seconds
Started Mar 31 01:50:32 PM PDT 24
Finished Mar 31 01:50:40 PM PDT 24
Peak memory 204104 kb
Host smart-81408ee7-9ab6-48c8-917c-36a361ed2ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17727
58130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.in_iso.1772758130
Directory /workspace/29.in_iso/latest

Test location /workspace/coverage/default/29.phy_config_usb_ref_disable.2965939227
Short name T1043
Test name
Test status
Simulation time 8365831420 ps
CPU time 9.12 seconds
Started Mar 31 01:50:31 PM PDT 24
Finished Mar 31 01:50:40 PM PDT 24
Peak memory 204044 kb
Host smart-7e8b2d79-fbbd-4ff8-909f-a505b20b952d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29659
39227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.phy_config_usb_ref_disable.2965939227
Directory /workspace/29.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.814282853
Short name T450
Test name
Test status
Simulation time 8367491384 ps
CPU time 7.64 seconds
Started Mar 31 01:50:32 PM PDT 24
Finished Mar 31 01:50:40 PM PDT 24
Peak memory 204148 kb
Host smart-512fb875-26ed-4dde-b60e-3ec127713d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81428
2853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.814282853
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_enable.3131629791
Short name T299
Test name
Test status
Simulation time 8367545577 ps
CPU time 7.15 seconds
Started Mar 31 01:50:32 PM PDT 24
Finished Mar 31 01:50:40 PM PDT 24
Peak memory 204028 kb
Host smart-929ae366-e174-4ba2-9ccc-e3d6bcec351b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31316
29791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3131629791
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.3789296531
Short name T670
Test name
Test status
Simulation time 36292520 ps
CPU time 1.13 seconds
Started Mar 31 01:50:33 PM PDT 24
Finished Mar 31 01:50:34 PM PDT 24
Peak memory 204240 kb
Host smart-6b76cb70-a365-4a5f-89fe-f7e83a5317ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37892
96531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.3789296531
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.1768851614
Short name T535
Test name
Test status
Simulation time 8363775548 ps
CPU time 7.21 seconds
Started Mar 31 01:50:34 PM PDT 24
Finished Mar 31 01:50:41 PM PDT 24
Peak memory 204120 kb
Host smart-7be5c2ee-e85b-475f-a49a-e857e080732f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17688
51614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.1768851614
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.3479645750
Short name T911
Test name
Test status
Simulation time 8394445486 ps
CPU time 7.13 seconds
Started Mar 31 01:50:32 PM PDT 24
Finished Mar 31 01:50:39 PM PDT 24
Peak memory 204108 kb
Host smart-eb6f2998-ae34-4daa-aadf-fb006031d6df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34796
45750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3479645750
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.2555562866
Short name T382
Test name
Test status
Simulation time 8413626784 ps
CPU time 9.42 seconds
Started Mar 31 01:50:32 PM PDT 24
Finished Mar 31 01:50:41 PM PDT 24
Peak memory 204068 kb
Host smart-f554aabd-f51d-474f-b3af-54ac2da522fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25555
62866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.2555562866
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.919672495
Short name T753
Test name
Test status
Simulation time 8361706811 ps
CPU time 7.28 seconds
Started Mar 31 01:50:33 PM PDT 24
Finished Mar 31 01:50:40 PM PDT 24
Peak memory 204140 kb
Host smart-5fa64692-f9b9-4608-9dff-29d2208e9bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91967
2495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.919672495
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3287571586
Short name T342
Test name
Test status
Simulation time 8402481109 ps
CPU time 7.5 seconds
Started Mar 31 01:50:31 PM PDT 24
Finished Mar 31 01:50:39 PM PDT 24
Peak memory 204124 kb
Host smart-81450996-9c4a-421f-9513-763e6161570c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32875
71586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3287571586
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.448659592
Short name T426
Test name
Test status
Simulation time 8369582687 ps
CPU time 7.17 seconds
Started Mar 31 01:50:32 PM PDT 24
Finished Mar 31 01:50:39 PM PDT 24
Peak memory 204104 kb
Host smart-54fafd14-599f-4754-b2a5-1be333597a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44865
9592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.448659592
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.1830708860
Short name T341
Test name
Test status
Simulation time 8369123105 ps
CPU time 7.2 seconds
Started Mar 31 01:50:31 PM PDT 24
Finished Mar 31 01:50:38 PM PDT 24
Peak memory 204104 kb
Host smart-e5af749e-81ad-4021-8302-017816319987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18307
08860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.1830708860
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2223741959
Short name T383
Test name
Test status
Simulation time 26870921 ps
CPU time 0.67 seconds
Started Mar 31 01:50:34 PM PDT 24
Finished Mar 31 01:50:35 PM PDT 24
Peak memory 204080 kb
Host smart-9202d188-d737-45df-9b57-46cc68688e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22237
41959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2223741959
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.1235961229
Short name T195
Test name
Test status
Simulation time 22631894727 ps
CPU time 39.05 seconds
Started Mar 31 01:50:32 PM PDT 24
Finished Mar 31 01:51:11 PM PDT 24
Peak memory 204316 kb
Host smart-9f14617b-d9c0-4d73-b6b3-40b50abdb6fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12359
61229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.1235961229
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1230793420
Short name T441
Test name
Test status
Simulation time 8392514307 ps
CPU time 7.4 seconds
Started Mar 31 01:50:34 PM PDT 24
Finished Mar 31 01:50:41 PM PDT 24
Peak memory 204156 kb
Host smart-3cd92aff-104e-4ea7-85b6-ef9d43fcb59e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12307
93420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1230793420
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.3479740278
Short name T410
Test name
Test status
Simulation time 8436739920 ps
CPU time 7.15 seconds
Started Mar 31 01:50:33 PM PDT 24
Finished Mar 31 01:50:40 PM PDT 24
Peak memory 204028 kb
Host smart-1eb363d3-9e55-41b1-a6f1-e56a2e53dba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34797
40278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.3479740278
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.215301801
Short name T385
Test name
Test status
Simulation time 8384124910 ps
CPU time 7.05 seconds
Started Mar 31 01:50:32 PM PDT 24
Finished Mar 31 01:50:39 PM PDT 24
Peak memory 204124 kb
Host smart-9a523c56-e960-4515-b480-97b0ed6b65bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21530
1801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.215301801
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.3314556845
Short name T1056
Test name
Test status
Simulation time 8357236968 ps
CPU time 9.24 seconds
Started Mar 31 01:50:34 PM PDT 24
Finished Mar 31 01:50:43 PM PDT 24
Peak memory 204148 kb
Host smart-6097a3f5-9078-46c2-8630-ef8ab70e767a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33145
56845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3314556845
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.3836570102
Short name T634
Test name
Test status
Simulation time 8426374986 ps
CPU time 8.64 seconds
Started Mar 31 01:50:34 PM PDT 24
Finished Mar 31 01:50:43 PM PDT 24
Peak memory 204136 kb
Host smart-1355f295-c8b0-495f-a044-d68503001cc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38365
70102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.3836570102
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.2175915380
Short name T310
Test name
Test status
Simulation time 8378087927 ps
CPU time 7.49 seconds
Started Mar 31 01:50:33 PM PDT 24
Finished Mar 31 01:50:40 PM PDT 24
Peak memory 204120 kb
Host smart-57444c82-6e05-44f2-8ad7-067840a4bcdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21759
15380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.2175915380
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.in_iso.1230078846
Short name T1030
Test name
Test status
Simulation time 8441128053 ps
CPU time 7.52 seconds
Started Mar 31 01:45:57 PM PDT 24
Finished Mar 31 01:46:04 PM PDT 24
Peak memory 204196 kb
Host smart-3f2b69ea-5c6b-47b3-9cd9-aefd75004abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12300
78846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.in_iso.1230078846
Directory /workspace/3.in_iso/latest

Test location /workspace/coverage/default/3.phy_config_usb_ref_disable.2739223178
Short name T859
Test name
Test status
Simulation time 8358500048 ps
CPU time 8.15 seconds
Started Mar 31 01:46:00 PM PDT 24
Finished Mar 31 01:46:09 PM PDT 24
Peak memory 203916 kb
Host smart-f70030fe-f6da-4cdb-8048-3db964cd3f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27392
23178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.phy_config_usb_ref_disable.2739223178
Directory /workspace/3.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1764369133
Short name T472
Test name
Test status
Simulation time 8369896138 ps
CPU time 7.2 seconds
Started Mar 31 01:45:44 PM PDT 24
Finished Mar 31 01:45:53 PM PDT 24
Peak memory 204148 kb
Host smart-3fb78a02-490d-4124-a84d-73f99811bc10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17643
69133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1764369133
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_enable.1209071623
Short name T337
Test name
Test status
Simulation time 8366970181 ps
CPU time 8.74 seconds
Started Mar 31 01:45:52 PM PDT 24
Finished Mar 31 01:46:01 PM PDT 24
Peak memory 204132 kb
Host smart-a1695bd7-a349-4382-a235-0577a7220ac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12090
71623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1209071623
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.2589080604
Short name T858
Test name
Test status
Simulation time 116582096 ps
CPU time 1.41 seconds
Started Mar 31 01:45:51 PM PDT 24
Finished Mar 31 01:45:52 PM PDT 24
Peak memory 204220 kb
Host smart-1efa4340-2b63-4f74-9c70-c0b7a78d9532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25890
80604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.2589080604
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.2220735174
Short name T798
Test name
Test status
Simulation time 8357765045 ps
CPU time 7.73 seconds
Started Mar 31 01:45:59 PM PDT 24
Finished Mar 31 01:46:07 PM PDT 24
Peak memory 204096 kb
Host smart-d1b55ab1-e1a9-4bf5-b74d-6bf9170b34c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22207
35174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.2220735174
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.4043592264
Short name T701
Test name
Test status
Simulation time 8382310597 ps
CPU time 9.63 seconds
Started Mar 31 01:45:52 PM PDT 24
Finished Mar 31 01:46:01 PM PDT 24
Peak memory 204148 kb
Host smart-0a8b9150-45cd-4dd3-95cb-f20c7a847ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40435
92264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.4043592264
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.3809181227
Short name T36
Test name
Test status
Simulation time 8409355574 ps
CPU time 7.22 seconds
Started Mar 31 01:45:58 PM PDT 24
Finished Mar 31 01:46:05 PM PDT 24
Peak memory 204108 kb
Host smart-7743d2a2-6f31-4e01-ac2b-dc1818394649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38091
81227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.3809181227
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.3662609040
Short name T462
Test name
Test status
Simulation time 8367737316 ps
CPU time 7.88 seconds
Started Mar 31 01:45:50 PM PDT 24
Finished Mar 31 01:45:58 PM PDT 24
Peak memory 204144 kb
Host smart-ce26f765-7b14-44cc-892d-5b772991cec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36626
09040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.3662609040
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.2697598440
Short name T124
Test name
Test status
Simulation time 8404938019 ps
CPU time 7.42 seconds
Started Mar 31 01:45:59 PM PDT 24
Finished Mar 31 01:46:06 PM PDT 24
Peak memory 204100 kb
Host smart-c4128a61-cccd-4a98-94e7-0a746038c14e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26975
98440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.2697598440
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.2163185059
Short name T468
Test name
Test status
Simulation time 8395943181 ps
CPU time 8 seconds
Started Mar 31 01:45:57 PM PDT 24
Finished Mar 31 01:46:05 PM PDT 24
Peak memory 204148 kb
Host smart-82c11b2e-d246-43cb-ad90-8c118adc705e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21631
85059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.2163185059
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.2578786833
Short name T446
Test name
Test status
Simulation time 8373366379 ps
CPU time 7.52 seconds
Started Mar 31 01:45:51 PM PDT 24
Finished Mar 31 01:45:58 PM PDT 24
Peak memory 204152 kb
Host smart-b6abf535-5ecc-4e1f-95da-f845a8097bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25787
86833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.2578786833
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.3695942439
Short name T844
Test name
Test status
Simulation time 33719331 ps
CPU time 0.66 seconds
Started Mar 31 01:45:58 PM PDT 24
Finished Mar 31 01:45:59 PM PDT 24
Peak memory 204044 kb
Host smart-bd64a21e-4b12-4d01-b747-736b428f7198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36959
42439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.3695942439
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.276408302
Short name T810
Test name
Test status
Simulation time 16603795807 ps
CPU time 27.2 seconds
Started Mar 31 01:45:55 PM PDT 24
Finished Mar 31 01:46:23 PM PDT 24
Peak memory 204412 kb
Host smart-0f7dc394-b864-46bd-9c86-b5ceb12d6b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27640
8302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.276408302
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1713056914
Short name T711
Test name
Test status
Simulation time 8394730508 ps
CPU time 8.04 seconds
Started Mar 31 01:45:50 PM PDT 24
Finished Mar 31 01:45:58 PM PDT 24
Peak memory 204120 kb
Host smart-1590f43a-e9a9-41d9-8795-2341c4f9d413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17130
56914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1713056914
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.458618399
Short name T483
Test name
Test status
Simulation time 8426328179 ps
CPU time 7.98 seconds
Started Mar 31 01:45:55 PM PDT 24
Finished Mar 31 01:46:03 PM PDT 24
Peak memory 204096 kb
Host smart-abf585c7-bd35-4068-bc3a-01ef8848fd45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45861
8399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.458618399
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.1834073007
Short name T413
Test name
Test status
Simulation time 8408919016 ps
CPU time 8.43 seconds
Started Mar 31 01:45:56 PM PDT 24
Finished Mar 31 01:46:04 PM PDT 24
Peak memory 204128 kb
Host smart-048e2d1f-be59-4da4-9651-5c040f6026d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18340
73007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.1834073007
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.3981091593
Short name T76
Test name
Test status
Simulation time 83037808 ps
CPU time 0.93 seconds
Started Mar 31 01:46:04 PM PDT 24
Finished Mar 31 01:46:05 PM PDT 24
Peak memory 220104 kb
Host smart-b42f48a6-b310-41db-85e4-8fd4b690afc7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3981091593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3981091593
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.1925926273
Short name T914
Test name
Test status
Simulation time 8360497611 ps
CPU time 7.18 seconds
Started Mar 31 01:45:56 PM PDT 24
Finished Mar 31 01:46:03 PM PDT 24
Peak memory 204156 kb
Host smart-8938c7a8-e0f7-4c0b-a380-439da68ca39e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19259
26273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.1925926273
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.678041042
Short name T167
Test name
Test status
Simulation time 8465486813 ps
CPU time 7.44 seconds
Started Mar 31 01:45:45 PM PDT 24
Finished Mar 31 01:45:53 PM PDT 24
Peak memory 204144 kb
Host smart-538d8486-a24f-47c7-a1c8-605c9f78658a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67804
1042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.678041042
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.4112747558
Short name T746
Test name
Test status
Simulation time 8359888484 ps
CPU time 9.49 seconds
Started Mar 31 01:45:55 PM PDT 24
Finished Mar 31 01:46:05 PM PDT 24
Peak memory 204120 kb
Host smart-7c7999b3-cb71-4074-b79f-03c77195a1b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41127
47558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.4112747558
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.in_iso.2955792282
Short name T581
Test name
Test status
Simulation time 8387473570 ps
CPU time 7.48 seconds
Started Mar 31 01:50:47 PM PDT 24
Finished Mar 31 01:50:54 PM PDT 24
Peak memory 204168 kb
Host smart-55ccee50-e197-430a-8245-c316aaee7ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29557
92282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.in_iso.2955792282
Directory /workspace/30.in_iso/latest

Test location /workspace/coverage/default/30.phy_config_usb_ref_disable.1309367153
Short name T620
Test name
Test status
Simulation time 8357735505 ps
CPU time 7.36 seconds
Started Mar 31 01:50:38 PM PDT 24
Finished Mar 31 01:50:45 PM PDT 24
Peak memory 204112 kb
Host smart-c58ec34f-7c8b-4f70-80c0-ef492624c252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13093
67153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.phy_config_usb_ref_disable.1309367153
Directory /workspace/30.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.4132314919
Short name T455
Test name
Test status
Simulation time 8372299382 ps
CPU time 7.41 seconds
Started Mar 31 01:50:33 PM PDT 24
Finished Mar 31 01:50:41 PM PDT 24
Peak memory 204120 kb
Host smart-9eae7e3f-f3fd-4456-9c7a-ddfeff96fa2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41323
14919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.4132314919
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_enable.2845374700
Short name T481
Test name
Test status
Simulation time 8369141778 ps
CPU time 8.65 seconds
Started Mar 31 01:50:34 PM PDT 24
Finished Mar 31 01:50:43 PM PDT 24
Peak memory 204112 kb
Host smart-c1fdf4bf-57c0-4b3c-aba7-1f6971148e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28453
74700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2845374700
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.4088827539
Short name T488
Test name
Test status
Simulation time 257335754 ps
CPU time 2.16 seconds
Started Mar 31 01:50:31 PM PDT 24
Finished Mar 31 01:50:33 PM PDT 24
Peak memory 204220 kb
Host smart-6dd3cd68-61e8-4981-8379-537e6663f8d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40888
27539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.4088827539
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.2483960655
Short name T975
Test name
Test status
Simulation time 8357793666 ps
CPU time 9.34 seconds
Started Mar 31 01:50:44 PM PDT 24
Finished Mar 31 01:50:53 PM PDT 24
Peak memory 204144 kb
Host smart-91ffc97c-cde9-4c41-a0c3-8ffc5d513f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24839
60655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.2483960655
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.225032997
Short name T34
Test name
Test status
Simulation time 8456741761 ps
CPU time 7.42 seconds
Started Mar 31 01:50:38 PM PDT 24
Finished Mar 31 01:50:46 PM PDT 24
Peak memory 204148 kb
Host smart-3d8a083f-b42c-4e13-9664-c1307a50aa8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22503
2997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.225032997
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.4017024724
Short name T501
Test name
Test status
Simulation time 8406990430 ps
CPU time 7.4 seconds
Started Mar 31 01:50:38 PM PDT 24
Finished Mar 31 01:50:45 PM PDT 24
Peak memory 204108 kb
Host smart-13425f29-6a51-4742-bc04-9c9f8ba9222f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40170
24724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.4017024724
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1231437265
Short name T730
Test name
Test status
Simulation time 8363937603 ps
CPU time 8.03 seconds
Started Mar 31 01:50:37 PM PDT 24
Finished Mar 31 01:50:45 PM PDT 24
Peak memory 204144 kb
Host smart-af3099ca-a9ae-4c52-8fb6-82996f1b32ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12314
37265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1231437265
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3886383252
Short name T983
Test name
Test status
Simulation time 8433146602 ps
CPU time 7.87 seconds
Started Mar 31 01:50:40 PM PDT 24
Finished Mar 31 01:50:48 PM PDT 24
Peak memory 204080 kb
Host smart-087ea291-3769-445f-87df-7a56ed4f6492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38863
83252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3886383252
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.460295038
Short name T1067
Test name
Test status
Simulation time 8371512061 ps
CPU time 7.09 seconds
Started Mar 31 01:50:39 PM PDT 24
Finished Mar 31 01:50:46 PM PDT 24
Peak memory 204136 kb
Host smart-c8b8fef4-19eb-437c-8e5c-b504e02b808f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46029
5038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.460295038
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.619386076
Short name T639
Test name
Test status
Simulation time 8380502181 ps
CPU time 8.39 seconds
Started Mar 31 01:50:39 PM PDT 24
Finished Mar 31 01:50:47 PM PDT 24
Peak memory 204152 kb
Host smart-6c98f807-32bd-4464-b4a9-0134c97e3e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61938
6076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.619386076
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.2075193114
Short name T769
Test name
Test status
Simulation time 24878896672 ps
CPU time 48.35 seconds
Started Mar 31 01:50:38 PM PDT 24
Finished Mar 31 01:51:26 PM PDT 24
Peak memory 204356 kb
Host smart-4b83a335-87b1-4758-861d-9fa65edf328f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20751
93114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.2075193114
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.3774934443
Short name T883
Test name
Test status
Simulation time 8395153915 ps
CPU time 9.56 seconds
Started Mar 31 01:50:40 PM PDT 24
Finished Mar 31 01:50:50 PM PDT 24
Peak memory 204112 kb
Host smart-f3c89526-24df-414c-9888-9052d2af3ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37749
34443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.3774934443
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.2176094582
Short name T892
Test name
Test status
Simulation time 8455892584 ps
CPU time 7.63 seconds
Started Mar 31 01:50:40 PM PDT 24
Finished Mar 31 01:50:47 PM PDT 24
Peak memory 204128 kb
Host smart-566c0f2f-f8fe-4dc6-82c5-eb5e82d8ae7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21760
94582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.2176094582
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.3401799960
Short name T641
Test name
Test status
Simulation time 8361875378 ps
CPU time 7.42 seconds
Started Mar 31 01:50:42 PM PDT 24
Finished Mar 31 01:50:49 PM PDT 24
Peak memory 204120 kb
Host smart-c752f767-6fb5-4680-8f92-46daf3a7bf44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34017
99960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.3401799960
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.3722055422
Short name T451
Test name
Test status
Simulation time 8362996346 ps
CPU time 9.25 seconds
Started Mar 31 01:50:39 PM PDT 24
Finished Mar 31 01:50:48 PM PDT 24
Peak memory 204048 kb
Host smart-2c7261f0-e317-48b5-9ff6-060bd4d90f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37220
55422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.3722055422
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.2610843653
Short name T696
Test name
Test status
Simulation time 8454794922 ps
CPU time 7.89 seconds
Started Mar 31 01:50:32 PM PDT 24
Finished Mar 31 01:50:40 PM PDT 24
Peak memory 204128 kb
Host smart-f2c4458f-4ac0-4f75-81f1-9316cdd8f9d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26108
43653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2610843653
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.3086133314
Short name T306
Test name
Test status
Simulation time 8379357258 ps
CPU time 7.23 seconds
Started Mar 31 01:50:39 PM PDT 24
Finished Mar 31 01:50:46 PM PDT 24
Peak memory 204152 kb
Host smart-ea76ba89-ff5a-4270-a15f-503476f0ddbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30861
33314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.3086133314
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.in_iso.811143418
Short name T42
Test name
Test status
Simulation time 8376892093 ps
CPU time 9.77 seconds
Started Mar 31 01:50:52 PM PDT 24
Finished Mar 31 01:51:02 PM PDT 24
Peak memory 204128 kb
Host smart-7d105176-a0e6-46c1-b408-1f59b1ae546e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81114
3418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.in_iso.811143418
Directory /workspace/31.in_iso/latest

Test location /workspace/coverage/default/31.phy_config_usb_ref_disable.314232887
Short name T828
Test name
Test status
Simulation time 8363180418 ps
CPU time 8.11 seconds
Started Mar 31 01:50:51 PM PDT 24
Finished Mar 31 01:50:59 PM PDT 24
Peak memory 204100 kb
Host smart-edf53808-804c-47dc-91ce-d3c8503f4e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31423
2887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.phy_config_usb_ref_disable.314232887
Directory /workspace/31.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.2785034076
Short name T839
Test name
Test status
Simulation time 8369004829 ps
CPU time 7.66 seconds
Started Mar 31 01:50:44 PM PDT 24
Finished Mar 31 01:50:51 PM PDT 24
Peak memory 204012 kb
Host smart-e9c0e920-55e5-4027-b38b-60ef9cedaad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27850
34076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.2785034076
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_enable.2761505631
Short name T987
Test name
Test status
Simulation time 8365238460 ps
CPU time 7.77 seconds
Started Mar 31 01:50:47 PM PDT 24
Finished Mar 31 01:50:55 PM PDT 24
Peak memory 204132 kb
Host smart-719bfeb4-6839-4863-9045-7ac5d61aac8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27615
05631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.2761505631
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.3722846424
Short name T680
Test name
Test status
Simulation time 52287066 ps
CPU time 1.41 seconds
Started Mar 31 01:50:45 PM PDT 24
Finished Mar 31 01:50:46 PM PDT 24
Peak memory 204244 kb
Host smart-2d6de7fb-4c73-4d8b-aa76-2a0f88fa88f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37228
46424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.3722846424
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.219601271
Short name T548
Test name
Test status
Simulation time 8359805041 ps
CPU time 7.44 seconds
Started Mar 31 01:50:52 PM PDT 24
Finished Mar 31 01:51:00 PM PDT 24
Peak memory 204128 kb
Host smart-86ba8a76-0aca-4e49-ab0b-67999dc3d91b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21960
1271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.219601271
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.1026344675
Short name T431
Test name
Test status
Simulation time 8421936408 ps
CPU time 7.19 seconds
Started Mar 31 01:50:45 PM PDT 24
Finished Mar 31 01:50:53 PM PDT 24
Peak memory 204112 kb
Host smart-9a70e412-eb19-4ee1-bc00-3d9dee467c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10263
44675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.1026344675
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.50293427
Short name T1066
Test name
Test status
Simulation time 8406689735 ps
CPU time 8.84 seconds
Started Mar 31 01:50:45 PM PDT 24
Finished Mar 31 01:50:54 PM PDT 24
Peak memory 204024 kb
Host smart-ce2197da-f97c-46a1-a4a6-163dce232248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50293
427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.50293427
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.2771028691
Short name T918
Test name
Test status
Simulation time 8361269903 ps
CPU time 7.23 seconds
Started Mar 31 01:50:42 PM PDT 24
Finished Mar 31 01:50:49 PM PDT 24
Peak memory 204120 kb
Host smart-c9337b1a-d8a8-4947-8f84-fcddcdc1f173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27710
28691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.2771028691
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.545282698
Short name T113
Test name
Test status
Simulation time 8416733428 ps
CPU time 8.63 seconds
Started Mar 31 01:50:46 PM PDT 24
Finished Mar 31 01:50:54 PM PDT 24
Peak memory 204076 kb
Host smart-6338ff87-30c6-4ded-9435-eebf2b6ec1b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54528
2698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.545282698
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.3472278059
Short name T14
Test name
Test status
Simulation time 8388763937 ps
CPU time 7.38 seconds
Started Mar 31 01:50:45 PM PDT 24
Finished Mar 31 01:50:52 PM PDT 24
Peak memory 204096 kb
Host smart-d466fc93-9a9c-4652-9323-79fc98feaa60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34722
78059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.3472278059
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.2309531779
Short name T1022
Test name
Test status
Simulation time 8391730774 ps
CPU time 7.21 seconds
Started Mar 31 01:50:45 PM PDT 24
Finished Mar 31 01:50:52 PM PDT 24
Peak memory 204132 kb
Host smart-3e9deea2-067c-495c-9b66-ce6bcc683023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23095
31779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.2309531779
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.2846259186
Short name T619
Test name
Test status
Simulation time 30070027 ps
CPU time 0.66 seconds
Started Mar 31 01:50:54 PM PDT 24
Finished Mar 31 01:50:54 PM PDT 24
Peak memory 204080 kb
Host smart-a030e671-a1e3-4c1e-be4d-f3b6ed1eaa74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28462
59186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.2846259186
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1047883262
Short name T100
Test name
Test status
Simulation time 25887145077 ps
CPU time 44.62 seconds
Started Mar 31 01:50:45 PM PDT 24
Finished Mar 31 01:51:30 PM PDT 24
Peak memory 204372 kb
Host smart-62b41abf-ab9f-4700-b5b2-3136cb0a5c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10478
83262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1047883262
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.1862670640
Short name T640
Test name
Test status
Simulation time 8373082680 ps
CPU time 7.94 seconds
Started Mar 31 01:50:43 PM PDT 24
Finished Mar 31 01:50:51 PM PDT 24
Peak memory 204128 kb
Host smart-92e04329-3c54-4a71-87d9-1734a407d581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18626
70640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.1862670640
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.1540472039
Short name T448
Test name
Test status
Simulation time 8433199076 ps
CPU time 7.31 seconds
Started Mar 31 01:50:51 PM PDT 24
Finished Mar 31 01:50:59 PM PDT 24
Peak memory 204112 kb
Host smart-055e19dc-b8c5-47e6-95b9-ca386849a4db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15404
72039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1540472039
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.3934847144
Short name T86
Test name
Test status
Simulation time 8368886443 ps
CPU time 8.75 seconds
Started Mar 31 01:50:52 PM PDT 24
Finished Mar 31 01:51:00 PM PDT 24
Peak memory 204084 kb
Host smart-52d7f4ca-2149-4fce-87a5-c9f99eeeb81d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39348
47144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.3934847144
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.1309590925
Short name T31
Test name
Test status
Simulation time 8358211766 ps
CPU time 9.07 seconds
Started Mar 31 01:50:51 PM PDT 24
Finished Mar 31 01:51:00 PM PDT 24
Peak memory 204096 kb
Host smart-467647cd-37c4-45c2-94b0-186ba979cffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13095
90925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.1309590925
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.1853474189
Short name T170
Test name
Test status
Simulation time 8434528801 ps
CPU time 7.02 seconds
Started Mar 31 01:50:46 PM PDT 24
Finished Mar 31 01:50:53 PM PDT 24
Peak memory 204140 kb
Host smart-78a53d45-28dc-4574-ae8c-2bc05f1172c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18534
74189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.1853474189
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.1079130816
Short name T663
Test name
Test status
Simulation time 8381754385 ps
CPU time 7.29 seconds
Started Mar 31 01:50:53 PM PDT 24
Finished Mar 31 01:51:00 PM PDT 24
Peak memory 204152 kb
Host smart-b3286d89-d66c-4686-8a75-20fa937cd4ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10791
30816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.1079130816
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.in_iso.1391636952
Short name T137
Test name
Test status
Simulation time 8435242811 ps
CPU time 7.52 seconds
Started Mar 31 01:50:59 PM PDT 24
Finished Mar 31 01:51:06 PM PDT 24
Peak memory 204112 kb
Host smart-b157eaf7-8622-4030-ada3-650ce70baec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13916
36952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.in_iso.1391636952
Directory /workspace/32.in_iso/latest

Test location /workspace/coverage/default/32.phy_config_usb_ref_disable.3819076870
Short name T464
Test name
Test status
Simulation time 8362270569 ps
CPU time 6.95 seconds
Started Mar 31 01:51:04 PM PDT 24
Finished Mar 31 01:51:11 PM PDT 24
Peak memory 204100 kb
Host smart-dfeb44c5-e0a0-4309-8942-dbbf02520aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38190
76870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.phy_config_usb_ref_disable.3819076870
Directory /workspace/32.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.3371330833
Short name T1048
Test name
Test status
Simulation time 8368615356 ps
CPU time 7.27 seconds
Started Mar 31 01:50:51 PM PDT 24
Finished Mar 31 01:50:59 PM PDT 24
Peak memory 204016 kb
Host smart-e792a7fe-dcfe-498a-88b8-ffbef3eb7f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33713
30833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.3371330833
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_enable.1500846643
Short name T625
Test name
Test status
Simulation time 8371442680 ps
CPU time 7.52 seconds
Started Mar 31 01:50:51 PM PDT 24
Finished Mar 31 01:50:59 PM PDT 24
Peak memory 204120 kb
Host smart-d91edfa3-4a6f-41e4-8fb1-dc9f7dff761b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15008
46643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.1500846643
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3691462664
Short name T469
Test name
Test status
Simulation time 283024737 ps
CPU time 2.23 seconds
Started Mar 31 01:50:50 PM PDT 24
Finished Mar 31 01:50:52 PM PDT 24
Peak memory 204220 kb
Host smart-171eca47-6097-4bea-8fa6-8f0347abdc96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36914
62664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3691462664
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.3960059975
Short name T669
Test name
Test status
Simulation time 8406271583 ps
CPU time 7.13 seconds
Started Mar 31 01:50:50 PM PDT 24
Finished Mar 31 01:50:57 PM PDT 24
Peak memory 204100 kb
Host smart-639690b8-f10a-4c8d-a31b-df3746a87749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39600
59975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.3960059975
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1377756042
Short name T538
Test name
Test status
Simulation time 8403787342 ps
CPU time 7.69 seconds
Started Mar 31 01:50:51 PM PDT 24
Finished Mar 31 01:50:59 PM PDT 24
Peak memory 204276 kb
Host smart-df18f0bc-8cb2-4b32-9ef7-33f736900cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13777
56042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1377756042
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.303622225
Short name T599
Test name
Test status
Simulation time 8366538949 ps
CPU time 7.97 seconds
Started Mar 31 01:51:02 PM PDT 24
Finished Mar 31 01:51:10 PM PDT 24
Peak memory 204080 kb
Host smart-4298c7ad-b5d7-4ffc-b1fa-ad63f08a51a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30362
2225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.303622225
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.3335104667
Short name T125
Test name
Test status
Simulation time 8385842201 ps
CPU time 7.48 seconds
Started Mar 31 01:51:00 PM PDT 24
Finished Mar 31 01:51:09 PM PDT 24
Peak memory 204140 kb
Host smart-815e6233-b806-480b-944d-7789b7c54cd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33351
04667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.3335104667
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.4249303800
Short name T527
Test name
Test status
Simulation time 8392543496 ps
CPU time 7.31 seconds
Started Mar 31 01:50:58 PM PDT 24
Finished Mar 31 01:51:06 PM PDT 24
Peak memory 204156 kb
Host smart-5413b522-b7fc-47ab-9797-2ea3ea16588d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42493
03800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.4249303800
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.1556063098
Short name T424
Test name
Test status
Simulation time 8383338640 ps
CPU time 7.5 seconds
Started Mar 31 01:51:01 PM PDT 24
Finished Mar 31 01:51:09 PM PDT 24
Peak memory 204156 kb
Host smart-819da6ef-c0ad-4db3-8559-bc502823e497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15560
63098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.1556063098
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.4071036572
Short name T805
Test name
Test status
Simulation time 29374141 ps
CPU time 0.64 seconds
Started Mar 31 01:50:58 PM PDT 24
Finished Mar 31 01:51:00 PM PDT 24
Peak memory 204064 kb
Host smart-50177168-e336-44ba-b68b-dd3def22ff03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40710
36572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.4071036572
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.3891868631
Short name T507
Test name
Test status
Simulation time 18706928688 ps
CPU time 31.12 seconds
Started Mar 31 01:51:00 PM PDT 24
Finished Mar 31 01:51:31 PM PDT 24
Peak memory 204296 kb
Host smart-bd79f3f4-4a6f-4fcb-b46a-68be6c1aaae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38918
68631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.3891868631
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.2329806014
Short name T1025
Test name
Test status
Simulation time 8404253310 ps
CPU time 7.11 seconds
Started Mar 31 01:50:58 PM PDT 24
Finished Mar 31 01:51:06 PM PDT 24
Peak memory 204112 kb
Host smart-4c6ab6f0-c376-42a5-a5f2-bedb5b4f477b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23298
06014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.2329806014
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.416481777
Short name T435
Test name
Test status
Simulation time 8383802220 ps
CPU time 7.47 seconds
Started Mar 31 01:51:04 PM PDT 24
Finished Mar 31 01:51:11 PM PDT 24
Peak memory 204096 kb
Host smart-a85c22e7-e608-4387-9b1c-2d1c12e44bcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41648
1777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.416481777
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.219731744
Short name T782
Test name
Test status
Simulation time 8386766699 ps
CPU time 7.5 seconds
Started Mar 31 01:51:02 PM PDT 24
Finished Mar 31 01:51:09 PM PDT 24
Peak memory 204080 kb
Host smart-7db2314c-12b4-4478-b034-dbf9cf25cc3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21973
1744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.219731744
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2063510896
Short name T870
Test name
Test status
Simulation time 8360677769 ps
CPU time 7.66 seconds
Started Mar 31 01:50:59 PM PDT 24
Finished Mar 31 01:51:07 PM PDT 24
Peak memory 204100 kb
Host smart-36e34a90-f8a3-473a-ba88-b1ab047a0830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20635
10896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2063510896
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.3716991154
Short name T151
Test name
Test status
Simulation time 8429225352 ps
CPU time 9.41 seconds
Started Mar 31 01:50:51 PM PDT 24
Finished Mar 31 01:51:01 PM PDT 24
Peak memory 204116 kb
Host smart-d123d56d-788a-45b5-83ae-fc6f44f5017d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37169
91154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.3716991154
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.963861312
Short name T853
Test name
Test status
Simulation time 8390421578 ps
CPU time 8.29 seconds
Started Mar 31 01:51:07 PM PDT 24
Finished Mar 31 01:51:16 PM PDT 24
Peak memory 204104 kb
Host smart-e33b47d9-cb02-4e47-8abf-85991bb0b13b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96386
1312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.963861312
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.in_iso.549255606
Short name T690
Test name
Test status
Simulation time 8394251308 ps
CPU time 8.45 seconds
Started Mar 31 01:51:04 PM PDT 24
Finished Mar 31 01:51:13 PM PDT 24
Peak memory 204144 kb
Host smart-8ccc711a-1df3-41b6-90d1-27850785c543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54925
5606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.in_iso.549255606
Directory /workspace/33.in_iso/latest

Test location /workspace/coverage/default/33.phy_config_usb_ref_disable.3049457779
Short name T346
Test name
Test status
Simulation time 8357934326 ps
CPU time 7.72 seconds
Started Mar 31 01:51:06 PM PDT 24
Finished Mar 31 01:51:14 PM PDT 24
Peak memory 204128 kb
Host smart-deb541c5-007f-4948-97c5-0dbc9c13d95b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30494
57779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.phy_config_usb_ref_disable.3049457779
Directory /workspace/33.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.1519699484
Short name T369
Test name
Test status
Simulation time 8370533777 ps
CPU time 7.52 seconds
Started Mar 31 01:50:58 PM PDT 24
Finished Mar 31 01:51:05 PM PDT 24
Peak memory 204092 kb
Host smart-36e65146-84f0-4608-8b02-e76868fd9b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15196
99484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1519699484
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_enable.3460400307
Short name T885
Test name
Test status
Simulation time 8372357572 ps
CPU time 9.11 seconds
Started Mar 31 01:50:59 PM PDT 24
Finished Mar 31 01:51:08 PM PDT 24
Peak memory 204060 kb
Host smart-384726a0-7ecc-47a9-ae51-c8648f4b4cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34604
00307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.3460400307
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1832006225
Short name T961
Test name
Test status
Simulation time 249699334 ps
CPU time 1.97 seconds
Started Mar 31 01:51:06 PM PDT 24
Finished Mar 31 01:51:09 PM PDT 24
Peak memory 204232 kb
Host smart-91db92f4-6665-4215-a745-0a731d9dc6dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18320
06225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1832006225
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.1117252136
Short name T5
Test name
Test status
Simulation time 8362435445 ps
CPU time 7.79 seconds
Started Mar 31 01:51:05 PM PDT 24
Finished Mar 31 01:51:14 PM PDT 24
Peak memory 204108 kb
Host smart-8301bc85-a45f-4b2d-bf31-edfeffbe0b3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11172
52136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.1117252136
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.3487746421
Short name T862
Test name
Test status
Simulation time 8380295724 ps
CPU time 7.43 seconds
Started Mar 31 01:51:06 PM PDT 24
Finished Mar 31 01:51:14 PM PDT 24
Peak memory 204144 kb
Host smart-ef7b2429-75ca-47fb-9435-02fedbb9ee35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34877
46421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.3487746421
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.2292906857
Short name T313
Test name
Test status
Simulation time 8412484080 ps
CPU time 8.22 seconds
Started Mar 31 01:51:05 PM PDT 24
Finished Mar 31 01:51:13 PM PDT 24
Peak memory 204108 kb
Host smart-5289b989-84c7-4022-820b-1279c77d4abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22929
06857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.2292906857
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.694689936
Short name T797
Test name
Test status
Simulation time 8364834263 ps
CPU time 7.25 seconds
Started Mar 31 01:51:05 PM PDT 24
Finished Mar 31 01:51:12 PM PDT 24
Peak memory 204136 kb
Host smart-56991a79-a732-4ed5-8721-687f54a62d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69468
9936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.694689936
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3236165372
Short name T1042
Test name
Test status
Simulation time 8418990802 ps
CPU time 7.77 seconds
Started Mar 31 01:51:06 PM PDT 24
Finished Mar 31 01:51:14 PM PDT 24
Peak memory 204180 kb
Host smart-eeba39c4-1f64-4d0e-8e22-3c1ccea96e96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32361
65372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3236165372
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.1325498665
Short name T784
Test name
Test status
Simulation time 8390468699 ps
CPU time 6.99 seconds
Started Mar 31 01:51:06 PM PDT 24
Finished Mar 31 01:51:14 PM PDT 24
Peak memory 204144 kb
Host smart-d119b509-1228-46b8-8fc2-17d4b49956ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13254
98665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.1325498665
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.3205536440
Short name T835
Test name
Test status
Simulation time 8389791109 ps
CPU time 9.15 seconds
Started Mar 31 01:51:07 PM PDT 24
Finished Mar 31 01:51:17 PM PDT 24
Peak memory 204100 kb
Host smart-c9fab788-caf8-4a7e-8df7-246c790322c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32055
36440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.3205536440
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.3040533070
Short name T881
Test name
Test status
Simulation time 32184535 ps
CPU time 0.62 seconds
Started Mar 31 01:51:04 PM PDT 24
Finished Mar 31 01:51:05 PM PDT 24
Peak memory 204040 kb
Host smart-6aac7887-94c4-44ea-853a-b9c9adc4d06b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30405
33070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.3040533070
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.2888577686
Short name T88
Test name
Test status
Simulation time 8385092809 ps
CPU time 8.71 seconds
Started Mar 31 01:51:08 PM PDT 24
Finished Mar 31 01:51:17 PM PDT 24
Peak memory 204112 kb
Host smart-a0a8e627-e974-44dc-94c7-d4a1a00042a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28885
77686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.2888577686
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.819373867
Short name T875
Test name
Test status
Simulation time 8374871739 ps
CPU time 9.51 seconds
Started Mar 31 01:51:08 PM PDT 24
Finished Mar 31 01:51:18 PM PDT 24
Peak memory 204100 kb
Host smart-ff32c8b4-1b60-4c6e-a326-4de043f3b5c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81937
3867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.819373867
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.814613364
Short name T756
Test name
Test status
Simulation time 8391723340 ps
CPU time 7.8 seconds
Started Mar 31 01:51:05 PM PDT 24
Finished Mar 31 01:51:14 PM PDT 24
Peak memory 204252 kb
Host smart-058c17e3-c1fd-46e6-ab69-38b6f329139a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81461
3364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.814613364
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.28074143
Short name T592
Test name
Test status
Simulation time 8359074955 ps
CPU time 8.45 seconds
Started Mar 31 01:51:05 PM PDT 24
Finished Mar 31 01:51:13 PM PDT 24
Peak memory 204148 kb
Host smart-1ee84558-0359-4302-9d97-c56ecb1756b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28074
143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.28074143
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.1451459438
Short name T1041
Test name
Test status
Simulation time 8446003544 ps
CPU time 7.34 seconds
Started Mar 31 01:50:59 PM PDT 24
Finished Mar 31 01:51:06 PM PDT 24
Peak memory 204128 kb
Host smart-cc2ff643-3f46-45b3-b8a7-fe8ab174c08e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14514
59438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1451459438
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.565825359
Short name T400
Test name
Test status
Simulation time 8372473573 ps
CPU time 7.13 seconds
Started Mar 31 01:51:05 PM PDT 24
Finished Mar 31 01:51:12 PM PDT 24
Peak memory 204112 kb
Host smart-4478123b-31f3-489b-bccd-de93072b4dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56582
5359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.565825359
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.in_iso.1746342927
Short name T326
Test name
Test status
Simulation time 8408755784 ps
CPU time 7.13 seconds
Started Mar 31 01:51:12 PM PDT 24
Finished Mar 31 01:51:20 PM PDT 24
Peak memory 204148 kb
Host smart-3d18a6a5-69b8-4dcf-957c-c579fce8f939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17463
42927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.in_iso.1746342927
Directory /workspace/34.in_iso/latest

Test location /workspace/coverage/default/34.phy_config_usb_ref_disable.4106849872
Short name T457
Test name
Test status
Simulation time 8358566116 ps
CPU time 7.16 seconds
Started Mar 31 01:51:11 PM PDT 24
Finished Mar 31 01:51:19 PM PDT 24
Peak memory 204132 kb
Host smart-0235494c-7c77-42d7-b71d-200fc3f24e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41068
49872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.phy_config_usb_ref_disable.4106849872
Directory /workspace/34.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.1963081082
Short name T460
Test name
Test status
Simulation time 8366323918 ps
CPU time 7.11 seconds
Started Mar 31 01:51:11 PM PDT 24
Finished Mar 31 01:51:18 PM PDT 24
Peak memory 204140 kb
Host smart-1054ca7e-4011-480d-ac73-53db1858c191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19630
81082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.1963081082
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_enable.968602117
Short name T532
Test name
Test status
Simulation time 8367744178 ps
CPU time 7.3 seconds
Started Mar 31 01:51:11 PM PDT 24
Finished Mar 31 01:51:18 PM PDT 24
Peak memory 204096 kb
Host smart-8772b613-dace-444d-b2c8-c89382e6d4a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96860
2117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.968602117
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.1052939252
Short name T604
Test name
Test status
Simulation time 73845823 ps
CPU time 1.91 seconds
Started Mar 31 01:51:10 PM PDT 24
Finished Mar 31 01:51:13 PM PDT 24
Peak memory 204216 kb
Host smart-266d30f4-673b-4b5a-b916-c362898abfa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10529
39252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.1052939252
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.850084406
Short name T197
Test name
Test status
Simulation time 8361710631 ps
CPU time 7.4 seconds
Started Mar 31 01:51:15 PM PDT 24
Finished Mar 31 01:51:22 PM PDT 24
Peak memory 204100 kb
Host smart-a915e6a5-b980-4d75-b1ae-62ece1a96fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85008
4406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.850084406
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2274326476
Short name T445
Test name
Test status
Simulation time 8456259071 ps
CPU time 8.65 seconds
Started Mar 31 01:51:11 PM PDT 24
Finished Mar 31 01:51:20 PM PDT 24
Peak memory 204092 kb
Host smart-a7614dea-d6bb-44ab-8522-bc082766d680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22743
26476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2274326476
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.2208711487
Short name T374
Test name
Test status
Simulation time 8415668368 ps
CPU time 7.72 seconds
Started Mar 31 01:51:15 PM PDT 24
Finished Mar 31 01:51:23 PM PDT 24
Peak memory 204156 kb
Host smart-283215bb-d716-400b-b576-582745cf676e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22087
11487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.2208711487
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.45385368
Short name T1046
Test name
Test status
Simulation time 8367743373 ps
CPU time 6.95 seconds
Started Mar 31 01:51:15 PM PDT 24
Finished Mar 31 01:51:22 PM PDT 24
Peak memory 204084 kb
Host smart-a74eec30-02ee-44de-a842-f9eaae71e2ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45385
368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.45385368
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1478809641
Short name T108
Test name
Test status
Simulation time 8396218677 ps
CPU time 8.48 seconds
Started Mar 31 01:51:12 PM PDT 24
Finished Mar 31 01:51:21 PM PDT 24
Peak memory 204108 kb
Host smart-4c73bdb5-16c0-4c8b-9244-e636a1d5740b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14788
09641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1478809641
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.3322782953
Short name T1033
Test name
Test status
Simulation time 8403797295 ps
CPU time 7.41 seconds
Started Mar 31 01:51:12 PM PDT 24
Finished Mar 31 01:51:20 PM PDT 24
Peak memory 204096 kb
Host smart-fc46ba32-259d-4a15-9b9c-560a4cb35b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33227
82953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3322782953
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.540661216
Short name T404
Test name
Test status
Simulation time 8391728716 ps
CPU time 7.39 seconds
Started Mar 31 01:51:13 PM PDT 24
Finished Mar 31 01:51:20 PM PDT 24
Peak memory 204144 kb
Host smart-63a6ef7d-f159-4d6f-b71b-6de309dfb616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54066
1216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.540661216
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.1993200436
Short name T726
Test name
Test status
Simulation time 24249000 ps
CPU time 0.62 seconds
Started Mar 31 01:51:13 PM PDT 24
Finished Mar 31 01:51:13 PM PDT 24
Peak memory 204072 kb
Host smart-73cbce87-4878-451f-8831-3041c472ab08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19932
00436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.1993200436
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.592739019
Short name T802
Test name
Test status
Simulation time 22380426603 ps
CPU time 41.91 seconds
Started Mar 31 01:51:12 PM PDT 24
Finished Mar 31 01:51:55 PM PDT 24
Peak memory 204388 kb
Host smart-50fa2136-5540-45fc-87ca-05984e0f5748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59273
9019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.592739019
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.305285118
Short name T396
Test name
Test status
Simulation time 8381860746 ps
CPU time 7.03 seconds
Started Mar 31 01:51:12 PM PDT 24
Finished Mar 31 01:51:20 PM PDT 24
Peak memory 204128 kb
Host smart-997bae6f-ca4e-410a-b3fe-b11a01f72283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30528
5118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.305285118
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.202150201
Short name T674
Test name
Test status
Simulation time 8376314609 ps
CPU time 7.15 seconds
Started Mar 31 01:51:11 PM PDT 24
Finished Mar 31 01:51:19 PM PDT 24
Peak memory 204168 kb
Host smart-e976dc80-04f1-4310-8bac-01324a9a5cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20215
0201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.202150201
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.698766773
Short name T322
Test name
Test status
Simulation time 8384921001 ps
CPU time 8.28 seconds
Started Mar 31 01:51:11 PM PDT 24
Finished Mar 31 01:51:19 PM PDT 24
Peak memory 204108 kb
Host smart-1802283d-b2b4-4a30-9708-35f9fdba0450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69876
6773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.698766773
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.3086531242
Short name T976
Test name
Test status
Simulation time 8359109248 ps
CPU time 6.96 seconds
Started Mar 31 01:51:13 PM PDT 24
Finished Mar 31 01:51:20 PM PDT 24
Peak memory 204048 kb
Host smart-8f1aa2fa-0001-4f53-885d-8b7be30285a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30865
31242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.3086531242
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1940485299
Short name T166
Test name
Test status
Simulation time 8442680543 ps
CPU time 9.43 seconds
Started Mar 31 01:51:05 PM PDT 24
Finished Mar 31 01:51:15 PM PDT 24
Peak memory 204116 kb
Host smart-4c744724-1614-42e8-94d2-35925f1965a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19404
85299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1940485299
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.1485356835
Short name T896
Test name
Test status
Simulation time 8372832514 ps
CPU time 7.19 seconds
Started Mar 31 01:51:10 PM PDT 24
Finished Mar 31 01:51:18 PM PDT 24
Peak memory 204124 kb
Host smart-b6c0d83a-ef2e-492d-8120-db2387f00461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14853
56835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.1485356835
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.in_iso.1406326735
Short name T523
Test name
Test status
Simulation time 8377771971 ps
CPU time 9.39 seconds
Started Mar 31 01:51:18 PM PDT 24
Finished Mar 31 01:51:27 PM PDT 24
Peak memory 204104 kb
Host smart-a431da10-70ef-432e-b72a-03b8da18a6ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14063
26735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.in_iso.1406326735
Directory /workspace/35.in_iso/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.3579280353
Short name T646
Test name
Test status
Simulation time 8366048020 ps
CPU time 9.15 seconds
Started Mar 31 01:51:11 PM PDT 24
Finished Mar 31 01:51:21 PM PDT 24
Peak memory 204100 kb
Host smart-665d49bb-bd8e-4bd2-9b31-1ae7cb3f8b87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35792
80353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.3579280353
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_enable.1640408569
Short name T775
Test name
Test status
Simulation time 8374364257 ps
CPU time 8.46 seconds
Started Mar 31 01:51:14 PM PDT 24
Finished Mar 31 01:51:22 PM PDT 24
Peak memory 204116 kb
Host smart-eff041b2-d361-4f91-a2c4-b2d5380573a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16404
08569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.1640408569
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1676287345
Short name T822
Test name
Test status
Simulation time 44734383 ps
CPU time 1.21 seconds
Started Mar 31 01:51:12 PM PDT 24
Finished Mar 31 01:51:13 PM PDT 24
Peak memory 204296 kb
Host smart-88b53dba-d485-4c37-b5a0-6427892ca12a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16762
87345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1676287345
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.826687227
Short name T242
Test name
Test status
Simulation time 8360564563 ps
CPU time 7.17 seconds
Started Mar 31 01:51:19 PM PDT 24
Finished Mar 31 01:51:27 PM PDT 24
Peak memory 204132 kb
Host smart-cef6b3d8-679f-474d-8480-aa757441ff42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82668
7227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.826687227
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.3978284924
Short name T461
Test name
Test status
Simulation time 8420423606 ps
CPU time 7.64 seconds
Started Mar 31 01:51:13 PM PDT 24
Finished Mar 31 01:51:20 PM PDT 24
Peak memory 204096 kb
Host smart-8b7a1000-ebf4-433f-a62c-e54f637a6336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39782
84924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.3978284924
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.2889080649
Short name T1061
Test name
Test status
Simulation time 8410754299 ps
CPU time 7.3 seconds
Started Mar 31 01:51:17 PM PDT 24
Finished Mar 31 01:51:24 PM PDT 24
Peak memory 204056 kb
Host smart-df37da4e-d2b8-48d8-a861-c4108d929589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28890
80649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.2889080649
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2215627780
Short name T443
Test name
Test status
Simulation time 8363719821 ps
CPU time 7.08 seconds
Started Mar 31 01:51:19 PM PDT 24
Finished Mar 31 01:51:26 PM PDT 24
Peak memory 204120 kb
Host smart-a20b061d-f9fc-4af2-a8f6-91c1a4d2d592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22156
27780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2215627780
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.1752355770
Short name T632
Test name
Test status
Simulation time 8403703939 ps
CPU time 7.19 seconds
Started Mar 31 01:51:21 PM PDT 24
Finished Mar 31 01:51:28 PM PDT 24
Peak memory 204120 kb
Host smart-8809b6c4-1b60-4ea5-9c5f-22ee51cd8a62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17523
55770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.1752355770
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.2729878415
Short name T432
Test name
Test status
Simulation time 8369189044 ps
CPU time 8.11 seconds
Started Mar 31 01:51:20 PM PDT 24
Finished Mar 31 01:51:29 PM PDT 24
Peak memory 204032 kb
Host smart-2d27c05f-4f87-4429-b98a-614b834883f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27298
78415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.2729878415
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.1458522183
Short name T333
Test name
Test status
Simulation time 8379046482 ps
CPU time 7.36 seconds
Started Mar 31 01:51:19 PM PDT 24
Finished Mar 31 01:51:27 PM PDT 24
Peak memory 204044 kb
Host smart-11e83ed7-d1b5-4023-97e0-70a2c8605718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14585
22183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.1458522183
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.1512561563
Short name T420
Test name
Test status
Simulation time 31121754 ps
CPU time 0.64 seconds
Started Mar 31 01:51:18 PM PDT 24
Finished Mar 31 01:51:19 PM PDT 24
Peak memory 204092 kb
Host smart-ea8c88bb-caef-43ff-9603-423629c01a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15125
61563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.1512561563
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.1117575799
Short name T78
Test name
Test status
Simulation time 8370567969 ps
CPU time 7.57 seconds
Started Mar 31 01:51:22 PM PDT 24
Finished Mar 31 01:51:30 PM PDT 24
Peak memory 203852 kb
Host smart-77af9ea5-353d-4d67-ab4a-42f75840966e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11175
75799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.1117575799
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.631124947
Short name T684
Test name
Test status
Simulation time 8421133596 ps
CPU time 7.45 seconds
Started Mar 31 01:51:19 PM PDT 24
Finished Mar 31 01:51:26 PM PDT 24
Peak memory 204148 kb
Host smart-09758bbc-9037-4122-b922-0f7a6d07d0b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63112
4947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.631124947
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.3423268220
Short name T264
Test name
Test status
Simulation time 8406599724 ps
CPU time 7.54 seconds
Started Mar 31 01:51:19 PM PDT 24
Finished Mar 31 01:51:27 PM PDT 24
Peak memory 204124 kb
Host smart-554e6f36-2b3e-4730-9422-aa525ce14911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34232
68220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.3423268220
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.2507947535
Short name T32
Test name
Test status
Simulation time 8357426615 ps
CPU time 7.55 seconds
Started Mar 31 01:51:18 PM PDT 24
Finished Mar 31 01:51:26 PM PDT 24
Peak memory 204160 kb
Host smart-391bef68-7fe2-405e-8baa-d7c447dd82fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25079
47535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.2507947535
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.253061537
Short name T175
Test name
Test status
Simulation time 8440765420 ps
CPU time 7.54 seconds
Started Mar 31 01:51:12 PM PDT 24
Finished Mar 31 01:51:20 PM PDT 24
Peak memory 204132 kb
Host smart-86d4e4c8-5a10-42cc-822d-aeef80b06c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25306
1537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.253061537
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.438384441
Short name T484
Test name
Test status
Simulation time 8392984603 ps
CPU time 9.2 seconds
Started Mar 31 01:51:19 PM PDT 24
Finished Mar 31 01:51:28 PM PDT 24
Peak memory 204096 kb
Host smart-f38c03da-834f-42c0-8d12-e5d1bd230489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43838
4441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.438384441
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.in_iso.1875162344
Short name T502
Test name
Test status
Simulation time 8446490937 ps
CPU time 8.21 seconds
Started Mar 31 01:51:23 PM PDT 24
Finished Mar 31 01:51:32 PM PDT 24
Peak memory 204092 kb
Host smart-cd35fdb5-4aa6-4973-9f24-d0a7bba7f7b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18751
62344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.in_iso.1875162344
Directory /workspace/36.in_iso/latest

Test location /workspace/coverage/default/36.phy_config_usb_ref_disable.3690334524
Short name T713
Test name
Test status
Simulation time 8357696732 ps
CPU time 8.32 seconds
Started Mar 31 01:51:28 PM PDT 24
Finished Mar 31 01:51:37 PM PDT 24
Peak memory 204108 kb
Host smart-6b168e92-ae54-461c-a684-c59e4a097b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36903
34524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.phy_config_usb_ref_disable.3690334524
Directory /workspace/36.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.1893120362
Short name T478
Test name
Test status
Simulation time 8372723006 ps
CPU time 7.13 seconds
Started Mar 31 01:51:18 PM PDT 24
Finished Mar 31 01:51:25 PM PDT 24
Peak memory 204120 kb
Host smart-61e5941b-24b7-499e-a123-af0b634f7370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18931
20362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1893120362
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_enable.3539469697
Short name T821
Test name
Test status
Simulation time 8366236333 ps
CPU time 8.43 seconds
Started Mar 31 01:51:22 PM PDT 24
Finished Mar 31 01:51:31 PM PDT 24
Peak memory 204100 kb
Host smart-74fafad2-1421-47e0-b80d-3401d8f3b6dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35394
69697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.3539469697
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.3479576754
Short name T765
Test name
Test status
Simulation time 59029805 ps
CPU time 1.6 seconds
Started Mar 31 01:51:18 PM PDT 24
Finished Mar 31 01:51:20 PM PDT 24
Peak memory 204196 kb
Host smart-388fdc08-c647-4443-9f38-03d55224dcbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34795
76754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.3479576754
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.3554281754
Short name T6
Test name
Test status
Simulation time 8357709440 ps
CPU time 7.42 seconds
Started Mar 31 01:51:24 PM PDT 24
Finished Mar 31 01:51:32 PM PDT 24
Peak memory 204136 kb
Host smart-e8ecc6cd-3082-4c9a-97de-f0600f6a9fe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35542
81754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.3554281754
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.3597829249
Short name T868
Test name
Test status
Simulation time 8372689601 ps
CPU time 7.34 seconds
Started Mar 31 01:51:24 PM PDT 24
Finished Mar 31 01:51:31 PM PDT 24
Peak memory 204372 kb
Host smart-3c035a75-63c4-44ca-8432-80815ee01258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35978
29249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.3597829249
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.2231977717
Short name T837
Test name
Test status
Simulation time 8408507589 ps
CPU time 7.43 seconds
Started Mar 31 01:51:22 PM PDT 24
Finished Mar 31 01:51:30 PM PDT 24
Peak memory 204080 kb
Host smart-dad586d5-ab18-4bb0-ad03-57cff70d121b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22319
77717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2231977717
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2226978418
Short name T971
Test name
Test status
Simulation time 8366877059 ps
CPU time 9.81 seconds
Started Mar 31 01:51:22 PM PDT 24
Finished Mar 31 01:51:32 PM PDT 24
Peak memory 204044 kb
Host smart-e02b21c9-2454-4bda-b736-f76181b34998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22269
78418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2226978418
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.2650697296
Short name T130
Test name
Test status
Simulation time 8432443711 ps
CPU time 8.36 seconds
Started Mar 31 01:51:24 PM PDT 24
Finished Mar 31 01:51:32 PM PDT 24
Peak memory 204132 kb
Host smart-80aca0f0-cc89-49f8-aa2d-2ed1abdf14de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26506
97296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.2650697296
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3632472956
Short name T972
Test name
Test status
Simulation time 8366607168 ps
CPU time 9.62 seconds
Started Mar 31 01:51:26 PM PDT 24
Finished Mar 31 01:51:36 PM PDT 24
Peak memory 204120 kb
Host smart-f66c7f5d-a312-414a-9203-b7503423fa9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36324
72956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3632472956
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1941400868
Short name T1087
Test name
Test status
Simulation time 8395461891 ps
CPU time 7.38 seconds
Started Mar 31 01:51:28 PM PDT 24
Finished Mar 31 01:51:36 PM PDT 24
Peak memory 204140 kb
Host smart-5597858d-5d18-483b-9cb7-c69363263dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19414
00868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1941400868
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.1272876091
Short name T46
Test name
Test status
Simulation time 25998636 ps
CPU time 0.65 seconds
Started Mar 31 01:51:26 PM PDT 24
Finished Mar 31 01:51:27 PM PDT 24
Peak memory 204048 kb
Host smart-818d7e95-ddee-4bac-90c0-bb910dd29d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12728
76091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.1272876091
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3232993702
Short name T618
Test name
Test status
Simulation time 26094380761 ps
CPU time 48.98 seconds
Started Mar 31 01:51:25 PM PDT 24
Finished Mar 31 01:52:14 PM PDT 24
Peak memory 204380 kb
Host smart-be84cf92-6828-44fc-a4ef-500afa7b411e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32329
93702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3232993702
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.2588999179
Short name T1002
Test name
Test status
Simulation time 8370340239 ps
CPU time 8.37 seconds
Started Mar 31 01:51:23 PM PDT 24
Finished Mar 31 01:51:31 PM PDT 24
Peak memory 204140 kb
Host smart-d0c8afe0-0320-4960-a2a0-a37f2fabf360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25889
99179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.2588999179
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.2910764321
Short name T379
Test name
Test status
Simulation time 8406128356 ps
CPU time 8.53 seconds
Started Mar 31 01:51:25 PM PDT 24
Finished Mar 31 01:51:34 PM PDT 24
Peak memory 204132 kb
Host smart-6459fed2-0bcd-4ebe-aecf-59c6c292834b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29107
64321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.2910764321
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.3185782127
Short name T676
Test name
Test status
Simulation time 8391360065 ps
CPU time 8.12 seconds
Started Mar 31 01:51:24 PM PDT 24
Finished Mar 31 01:51:32 PM PDT 24
Peak memory 204152 kb
Host smart-875e5fb9-055e-4ef6-b9ca-d327babbd999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31857
82127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.3185782127
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.2097825120
Short name T509
Test name
Test status
Simulation time 8362930303 ps
CPU time 9.76 seconds
Started Mar 31 01:51:24 PM PDT 24
Finished Mar 31 01:51:34 PM PDT 24
Peak memory 204096 kb
Host smart-4083e7d3-4786-4904-bcec-57961c049e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20978
25120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.2097825120
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.73621083
Short name T762
Test name
Test status
Simulation time 8454801543 ps
CPU time 7.77 seconds
Started Mar 31 01:51:18 PM PDT 24
Finished Mar 31 01:51:26 PM PDT 24
Peak memory 204128 kb
Host smart-c715386a-17b6-448a-a040-a50acfbde641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73621
083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.73621083
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.1355409521
Short name T886
Test name
Test status
Simulation time 8381086752 ps
CPU time 7.81 seconds
Started Mar 31 01:51:23 PM PDT 24
Finished Mar 31 01:51:31 PM PDT 24
Peak memory 204120 kb
Host smart-7979450c-1097-4bcf-b3f7-4dbc876dcc6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13554
09521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.1355409521
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.in_iso.1246752383
Short name T729
Test name
Test status
Simulation time 8426089886 ps
CPU time 8.55 seconds
Started Mar 31 01:51:37 PM PDT 24
Finished Mar 31 01:51:46 PM PDT 24
Peak memory 204104 kb
Host smart-a2841e55-0ec3-4f41-ba1a-80683144cf47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12467
52383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.in_iso.1246752383
Directory /workspace/37.in_iso/latest

Test location /workspace/coverage/default/37.phy_config_usb_ref_disable.152531170
Short name T708
Test name
Test status
Simulation time 8362928285 ps
CPU time 8.36 seconds
Started Mar 31 01:51:30 PM PDT 24
Finished Mar 31 01:51:38 PM PDT 24
Peak memory 204132 kb
Host smart-8810e31e-5552-4ac9-ac78-6256294256b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15253
1170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.phy_config_usb_ref_disable.152531170
Directory /workspace/37.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.1724800359
Short name T414
Test name
Test status
Simulation time 8369731979 ps
CPU time 7.3 seconds
Started Mar 31 01:51:24 PM PDT 24
Finished Mar 31 01:51:32 PM PDT 24
Peak memory 204076 kb
Host smart-bb4ebad7-f4fb-42dd-98ef-de643a1ae2b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17248
00359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.1724800359
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_enable.4158954802
Short name T412
Test name
Test status
Simulation time 8367506276 ps
CPU time 7.25 seconds
Started Mar 31 01:51:24 PM PDT 24
Finished Mar 31 01:51:32 PM PDT 24
Peak memory 204120 kb
Host smart-46e10a40-4d77-4dba-988e-62b330502bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41589
54802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.4158954802
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.3333090243
Short name T208
Test name
Test status
Simulation time 8354862823 ps
CPU time 7.47 seconds
Started Mar 31 01:51:31 PM PDT 24
Finished Mar 31 01:51:38 PM PDT 24
Peak memory 204012 kb
Host smart-d8e8d3fd-7edd-475c-b93b-be881a9f8b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33330
90243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.3333090243
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.2618510053
Short name T320
Test name
Test status
Simulation time 8401333378 ps
CPU time 7.4 seconds
Started Mar 31 01:51:24 PM PDT 24
Finished Mar 31 01:51:32 PM PDT 24
Peak memory 204104 kb
Host smart-db062387-e0f3-4c0f-b00c-5899479345c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26185
10053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.2618510053
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.3316843598
Short name T347
Test name
Test status
Simulation time 8409294070 ps
CPU time 9.38 seconds
Started Mar 31 01:51:30 PM PDT 24
Finished Mar 31 01:51:39 PM PDT 24
Peak memory 204116 kb
Host smart-737847f0-1a8d-4f55-b456-12ad1c67c2f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33168
43598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.3316843598
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.4206826566
Short name T350
Test name
Test status
Simulation time 8360850870 ps
CPU time 7.79 seconds
Started Mar 31 01:51:29 PM PDT 24
Finished Mar 31 01:51:37 PM PDT 24
Peak memory 204124 kb
Host smart-32c8e74c-0b0f-4a40-957e-7cafa9b526cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42068
26566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.4206826566
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3510229509
Short name T503
Test name
Test status
Simulation time 8449444069 ps
CPU time 9.01 seconds
Started Mar 31 01:51:29 PM PDT 24
Finished Mar 31 01:51:38 PM PDT 24
Peak memory 204144 kb
Host smart-ebd73dbd-f7e0-4e04-ad3e-5d920eb248d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35102
29509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3510229509
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.2683417153
Short name T1001
Test name
Test status
Simulation time 8386909644 ps
CPU time 8.76 seconds
Started Mar 31 01:51:30 PM PDT 24
Finished Mar 31 01:51:39 PM PDT 24
Peak memory 204096 kb
Host smart-dffd7264-49ce-4c2b-9959-d63eb7e0f7a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26834
17153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.2683417153
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.3079688125
Short name T714
Test name
Test status
Simulation time 8403587362 ps
CPU time 9.14 seconds
Started Mar 31 01:51:32 PM PDT 24
Finished Mar 31 01:51:42 PM PDT 24
Peak memory 204116 kb
Host smart-1e810283-0963-4302-a13d-0ccbd28baf90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30796
88125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.3079688125
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.4115726923
Short name T588
Test name
Test status
Simulation time 32171290 ps
CPU time 0.65 seconds
Started Mar 31 01:51:31 PM PDT 24
Finished Mar 31 01:51:32 PM PDT 24
Peak memory 204064 kb
Host smart-60340fa4-b0c5-48ea-bcbe-14ed7bda0a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41157
26923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.4115726923
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.993785275
Short name T673
Test name
Test status
Simulation time 29260800536 ps
CPU time 63.63 seconds
Started Mar 31 01:51:31 PM PDT 24
Finished Mar 31 01:52:35 PM PDT 24
Peak memory 204432 kb
Host smart-72dde11d-21d6-4306-a182-79df45a21790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99378
5275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.993785275
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3654871282
Short name T772
Test name
Test status
Simulation time 8379147391 ps
CPU time 7.83 seconds
Started Mar 31 01:51:30 PM PDT 24
Finished Mar 31 01:51:38 PM PDT 24
Peak memory 204132 kb
Host smart-4ce92af4-8d29-4f28-954d-65bf7386d25c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36548
71282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3654871282
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.844882166
Short name T480
Test name
Test status
Simulation time 8380560586 ps
CPU time 7.04 seconds
Started Mar 31 01:51:28 PM PDT 24
Finished Mar 31 01:51:36 PM PDT 24
Peak memory 204132 kb
Host smart-6dd19a06-7c0d-446f-9134-5355fae45b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84488
2166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.844882166
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.4106659772
Short name T707
Test name
Test status
Simulation time 8371554043 ps
CPU time 9.79 seconds
Started Mar 31 01:51:31 PM PDT 24
Finished Mar 31 01:51:40 PM PDT 24
Peak memory 204024 kb
Host smart-ba224ef2-3dfe-4a0f-8d12-09a2a381751c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41066
59772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.4106659772
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.3737313767
Short name T833
Test name
Test status
Simulation time 8355772010 ps
CPU time 7.37 seconds
Started Mar 31 01:51:30 PM PDT 24
Finished Mar 31 01:51:38 PM PDT 24
Peak memory 204180 kb
Host smart-a8a6dfa8-d851-40df-97fc-973584d6bb8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37373
13767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.3737313767
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.589150433
Short name T466
Test name
Test status
Simulation time 8366993089 ps
CPU time 7.13 seconds
Started Mar 31 01:51:29 PM PDT 24
Finished Mar 31 01:51:36 PM PDT 24
Peak memory 204124 kb
Host smart-a14462df-844e-4f85-b66c-f34d6147d263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58915
0433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.589150433
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.in_iso.1059187028
Short name T1008
Test name
Test status
Simulation time 8376049665 ps
CPU time 7.28 seconds
Started Mar 31 01:51:49 PM PDT 24
Finished Mar 31 01:51:56 PM PDT 24
Peak memory 204148 kb
Host smart-d6439579-742d-49c1-b8e8-6f0ef2d663b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10591
87028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.in_iso.1059187028
Directory /workspace/38.in_iso/latest

Test location /workspace/coverage/default/38.phy_config_usb_ref_disable.713626896
Short name T419
Test name
Test status
Simulation time 8360506094 ps
CPU time 7.11 seconds
Started Mar 31 01:51:40 PM PDT 24
Finished Mar 31 01:51:48 PM PDT 24
Peak memory 204108 kb
Host smart-0e054e47-9471-4cbf-b023-13035cae3df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71362
6896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.phy_config_usb_ref_disable.713626896
Directory /workspace/38.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.2957295221
Short name T378
Test name
Test status
Simulation time 8368042109 ps
CPU time 7.9 seconds
Started Mar 31 01:51:34 PM PDT 24
Finished Mar 31 01:51:42 PM PDT 24
Peak memory 204104 kb
Host smart-15cd6216-7207-434e-b6de-37c255c70b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29572
95221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.2957295221
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_enable.1438565403
Short name T575
Test name
Test status
Simulation time 8366381534 ps
CPU time 7.02 seconds
Started Mar 31 01:51:35 PM PDT 24
Finished Mar 31 01:51:43 PM PDT 24
Peak memory 204120 kb
Host smart-5713118b-d5bc-4e6b-8d9a-c0e8b1d7b4df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14385
65403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.1438565403
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.4201414120
Short name T596
Test name
Test status
Simulation time 121233645 ps
CPU time 1.29 seconds
Started Mar 31 01:51:37 PM PDT 24
Finished Mar 31 01:51:39 PM PDT 24
Peak memory 204252 kb
Host smart-ecb7d0d9-adcc-4b2e-93f5-0354c0e6d109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42014
14120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.4201414120
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.2890942537
Short name T203
Test name
Test status
Simulation time 8356196816 ps
CPU time 7.69 seconds
Started Mar 31 01:51:41 PM PDT 24
Finished Mar 31 01:51:49 PM PDT 24
Peak memory 204144 kb
Host smart-9715658e-ed0d-4988-958d-135f64b4b3a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28909
42537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.2890942537
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.863129086
Short name T727
Test name
Test status
Simulation time 8392266184 ps
CPU time 9.66 seconds
Started Mar 31 01:51:34 PM PDT 24
Finished Mar 31 01:51:44 PM PDT 24
Peak memory 204040 kb
Host smart-53786cb3-698e-476e-8ee2-fd16e83702ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86312
9086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.863129086
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.4120940601
Short name T516
Test name
Test status
Simulation time 8409418517 ps
CPU time 8.36 seconds
Started Mar 31 01:51:35 PM PDT 24
Finished Mar 31 01:51:44 PM PDT 24
Peak memory 204140 kb
Host smart-13841465-82be-4f50-9f44-ed4a5a0d29f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41209
40601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.4120940601
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.1901790061
Short name T81
Test name
Test status
Simulation time 8362601389 ps
CPU time 7.27 seconds
Started Mar 31 01:51:35 PM PDT 24
Finished Mar 31 01:51:43 PM PDT 24
Peak memory 204100 kb
Host smart-3ff3a9eb-8c38-4418-8c57-cacb936d4ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19017
90061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.1901790061
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.781253570
Short name T109
Test name
Test status
Simulation time 8425547519 ps
CPU time 7.75 seconds
Started Mar 31 01:51:36 PM PDT 24
Finished Mar 31 01:51:44 PM PDT 24
Peak memory 204076 kb
Host smart-0a0a6590-f240-4d81-afd2-d53fd40e688c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78125
3570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.781253570
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.3114712368
Short name T243
Test name
Test status
Simulation time 8371111846 ps
CPU time 8.25 seconds
Started Mar 31 01:51:36 PM PDT 24
Finished Mar 31 01:51:45 PM PDT 24
Peak memory 204064 kb
Host smart-9540b395-da53-418e-a8fd-fee1688804a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31147
12368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.3114712368
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.1077238527
Short name T697
Test name
Test status
Simulation time 8397476738 ps
CPU time 7.9 seconds
Started Mar 31 01:51:34 PM PDT 24
Finished Mar 31 01:51:42 PM PDT 24
Peak memory 204140 kb
Host smart-49676ed7-0b67-40f8-af82-8af7aaa135c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10772
38527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.1077238527
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.1308151178
Short name T642
Test name
Test status
Simulation time 22495735 ps
CPU time 0.62 seconds
Started Mar 31 01:51:41 PM PDT 24
Finished Mar 31 01:51:42 PM PDT 24
Peak memory 204212 kb
Host smart-2ac10187-219d-451b-b304-accd6f345479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13081
51178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.1308151178
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.639531959
Short name T981
Test name
Test status
Simulation time 17250016089 ps
CPU time 32.23 seconds
Started Mar 31 01:51:34 PM PDT 24
Finished Mar 31 01:52:07 PM PDT 24
Peak memory 204388 kb
Host smart-f0ed20e5-1067-42bb-919e-476a0d379f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63953
1959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.639531959
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.812047712
Short name T393
Test name
Test status
Simulation time 8384687859 ps
CPU time 9.33 seconds
Started Mar 31 01:51:41 PM PDT 24
Finished Mar 31 01:51:51 PM PDT 24
Peak memory 204148 kb
Host smart-17fff49e-c45e-4fd8-9859-01f764cdc141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81204
7712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.812047712
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.4044568856
Short name T929
Test name
Test status
Simulation time 8375789442 ps
CPU time 9.8 seconds
Started Mar 31 01:51:36 PM PDT 24
Finished Mar 31 01:51:46 PM PDT 24
Peak memory 204136 kb
Host smart-c65675a7-86e5-41fc-80c8-01e3759809e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40445
68856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.4044568856
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.646942460
Short name T555
Test name
Test status
Simulation time 8388300390 ps
CPU time 7.06 seconds
Started Mar 31 01:51:43 PM PDT 24
Finished Mar 31 01:51:51 PM PDT 24
Peak memory 204144 kb
Host smart-cbb7addb-3175-4162-bd65-e8d1ac0c0ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64694
2460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.646942460
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.2242557681
Short name T780
Test name
Test status
Simulation time 8360212579 ps
CPU time 8.07 seconds
Started Mar 31 01:51:42 PM PDT 24
Finished Mar 31 01:51:51 PM PDT 24
Peak memory 204112 kb
Host smart-8e3faccf-1995-4829-b7a8-dea5197740fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22425
57681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.2242557681
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.1852944190
Short name T554
Test name
Test status
Simulation time 8378795077 ps
CPU time 7.75 seconds
Started Mar 31 01:51:40 PM PDT 24
Finished Mar 31 01:51:48 PM PDT 24
Peak memory 204108 kb
Host smart-ecb5e41f-c1f7-43a7-9524-e40cf1f5bcdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18529
44190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.1852944190
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.in_iso.2037246740
Short name T149
Test name
Test status
Simulation time 8442062493 ps
CPU time 8.09 seconds
Started Mar 31 01:51:53 PM PDT 24
Finished Mar 31 01:52:01 PM PDT 24
Peak memory 204144 kb
Host smart-0ca34bbc-6eaa-46d6-8ecd-624bbbb43280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20372
46740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.in_iso.2037246740
Directory /workspace/39.in_iso/latest

Test location /workspace/coverage/default/39.phy_config_usb_ref_disable.2718932404
Short name T700
Test name
Test status
Simulation time 8362186751 ps
CPU time 7.19 seconds
Started Mar 31 01:51:49 PM PDT 24
Finished Mar 31 01:51:56 PM PDT 24
Peak memory 204112 kb
Host smart-e84817a3-38ec-41c1-96e2-b1049bd5795b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27189
32404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.phy_config_usb_ref_disable.2718932404
Directory /workspace/39.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.542875824
Short name T3
Test name
Test status
Simulation time 8372982530 ps
CPU time 7.93 seconds
Started Mar 31 01:51:41 PM PDT 24
Finished Mar 31 01:51:49 PM PDT 24
Peak memory 204068 kb
Host smart-593a7d49-dca9-4f83-b636-02fbcf8b6f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54287
5824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.542875824
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_enable.4162544576
Short name T1077
Test name
Test status
Simulation time 8367806997 ps
CPU time 8.62 seconds
Started Mar 31 01:51:47 PM PDT 24
Finished Mar 31 01:51:56 PM PDT 24
Peak memory 204140 kb
Host smart-049f66e7-83c9-4169-9a6f-94b913550354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41625
44576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.4162544576
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.1224509731
Short name T836
Test name
Test status
Simulation time 277457978 ps
CPU time 2.08 seconds
Started Mar 31 01:51:47 PM PDT 24
Finished Mar 31 01:51:49 PM PDT 24
Peak memory 204200 kb
Host smart-61137c21-c01c-4442-8cfb-013d8e1e7a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12245
09731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.1224509731
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.3398508788
Short name T210
Test name
Test status
Simulation time 8362429118 ps
CPU time 8.23 seconds
Started Mar 31 01:51:48 PM PDT 24
Finished Mar 31 01:51:56 PM PDT 24
Peak memory 204064 kb
Host smart-3e3f8375-444d-4f58-b583-af3c0dcb310c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33985
08788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.3398508788
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.2056085577
Short name T1011
Test name
Test status
Simulation time 8398092459 ps
CPU time 9.38 seconds
Started Mar 31 01:51:47 PM PDT 24
Finished Mar 31 01:51:56 PM PDT 24
Peak memory 204140 kb
Host smart-a176bc42-6ade-4381-9a50-b8a0fa34fd20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20560
85577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.2056085577
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.1240583771
Short name T612
Test name
Test status
Simulation time 8407473432 ps
CPU time 7.35 seconds
Started Mar 31 01:51:49 PM PDT 24
Finished Mar 31 01:51:56 PM PDT 24
Peak memory 204156 kb
Host smart-56cadfbd-4f5b-4575-a270-9834e8d0b912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12405
83771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.1240583771
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.196621290
Short name T830
Test name
Test status
Simulation time 8365094339 ps
CPU time 7.42 seconds
Started Mar 31 01:51:48 PM PDT 24
Finished Mar 31 01:51:55 PM PDT 24
Peak memory 204140 kb
Host smart-c1414144-d57b-4631-97c7-a2815943283c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19662
1290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.196621290
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.2652810798
Short name T115
Test name
Test status
Simulation time 8416924389 ps
CPU time 9.82 seconds
Started Mar 31 01:51:49 PM PDT 24
Finished Mar 31 01:51:59 PM PDT 24
Peak memory 203912 kb
Host smart-5363e991-db40-45e8-81b0-e187d962b87a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26528
10798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.2652810798
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1765139555
Short name T525
Test name
Test status
Simulation time 8391797841 ps
CPU time 7.11 seconds
Started Mar 31 01:51:47 PM PDT 24
Finished Mar 31 01:51:54 PM PDT 24
Peak memory 204068 kb
Host smart-80dd23bc-65b9-403d-9010-1035c5b614aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17651
39555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1765139555
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.3054468757
Short name T849
Test name
Test status
Simulation time 8404187052 ps
CPU time 7.18 seconds
Started Mar 31 01:51:47 PM PDT 24
Finished Mar 31 01:51:55 PM PDT 24
Peak memory 204156 kb
Host smart-8847c4d6-9d7f-4cba-a87f-3917b3c5345c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30544
68757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.3054468757
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3497514394
Short name T661
Test name
Test status
Simulation time 29709715 ps
CPU time 0.65 seconds
Started Mar 31 01:51:45 PM PDT 24
Finished Mar 31 01:51:46 PM PDT 24
Peak memory 204052 kb
Host smart-946eaf52-f7b6-4d97-bce5-7db6490dd6bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34975
14394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3497514394
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.1451574321
Short name T99
Test name
Test status
Simulation time 22668560672 ps
CPU time 38.88 seconds
Started Mar 31 01:51:49 PM PDT 24
Finished Mar 31 01:52:28 PM PDT 24
Peak memory 204400 kb
Host smart-6b9e2526-e1ea-4777-bd72-800df82b8ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14515
74321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.1451574321
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.521554952
Short name T394
Test name
Test status
Simulation time 8394548689 ps
CPU time 7.54 seconds
Started Mar 31 01:51:49 PM PDT 24
Finished Mar 31 01:51:57 PM PDT 24
Peak memory 204152 kb
Host smart-1f03534b-fa5a-4704-9913-fee63f6e91e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52155
4952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.521554952
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.109686284
Short name T152
Test name
Test status
Simulation time 8404109346 ps
CPU time 9.77 seconds
Started Mar 31 01:51:49 PM PDT 24
Finished Mar 31 01:51:58 PM PDT 24
Peak memory 204132 kb
Host smart-853316d1-af08-4ba8-9921-52b517f39441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10968
6284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.109686284
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.3454658274
Short name T664
Test name
Test status
Simulation time 8380371966 ps
CPU time 7.11 seconds
Started Mar 31 01:51:50 PM PDT 24
Finished Mar 31 01:51:57 PM PDT 24
Peak memory 204080 kb
Host smart-0fd5c17f-84e9-4386-9d5d-543c56951b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34546
58274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.3454658274
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.3011334686
Short name T1044
Test name
Test status
Simulation time 8359358689 ps
CPU time 7.11 seconds
Started Mar 31 01:51:53 PM PDT 24
Finished Mar 31 01:52:00 PM PDT 24
Peak memory 204144 kb
Host smart-1b38a84a-b239-43f4-a273-edbc8dfe23f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30113
34686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.3011334686
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.3668869342
Short name T665
Test name
Test status
Simulation time 8430764165 ps
CPU time 9.58 seconds
Started Mar 31 01:51:51 PM PDT 24
Finished Mar 31 01:52:01 PM PDT 24
Peak memory 204108 kb
Host smart-805292dc-7c3a-48d1-9bdd-20fc190478ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36688
69342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3668869342
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.2981032089
Short name T1075
Test name
Test status
Simulation time 8373909174 ps
CPU time 7.08 seconds
Started Mar 31 01:51:53 PM PDT 24
Finished Mar 31 01:52:00 PM PDT 24
Peak memory 204136 kb
Host smart-bdd76d8c-c54e-4c30-a771-fdb87b578ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29810
32089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.2981032089
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.in_iso.2000843025
Short name T650
Test name
Test status
Simulation time 8427738943 ps
CPU time 8.94 seconds
Started Mar 31 01:46:20 PM PDT 24
Finished Mar 31 01:46:29 PM PDT 24
Peak memory 204132 kb
Host smart-ea59be34-7171-43fd-b632-04cfb876e7ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20008
43025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.in_iso.2000843025
Directory /workspace/4.in_iso/latest

Test location /workspace/coverage/default/4.phy_config_usb_ref_disable.1230016211
Short name T571
Test name
Test status
Simulation time 8358425025 ps
CPU time 7.03 seconds
Started Mar 31 01:46:18 PM PDT 24
Finished Mar 31 01:46:25 PM PDT 24
Peak memory 204136 kb
Host smart-0ebf928e-f222-4c33-8783-8c9e04666ea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12300
16211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.phy_config_usb_ref_disable.1230016211
Directory /workspace/4.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.1956319015
Short name T695
Test name
Test status
Simulation time 8367868122 ps
CPU time 7.36 seconds
Started Mar 31 01:46:07 PM PDT 24
Finished Mar 31 01:46:15 PM PDT 24
Peak memory 204104 kb
Host smart-16148a23-18b7-4b0e-aa46-898fcf031146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19563
19015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.1956319015
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_enable.2052236378
Short name T376
Test name
Test status
Simulation time 8367034399 ps
CPU time 7.67 seconds
Started Mar 31 01:46:04 PM PDT 24
Finished Mar 31 01:46:11 PM PDT 24
Peak memory 204100 kb
Host smart-736658b6-de8c-4720-84f4-06accc623700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20522
36378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.2052236378
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.549384560
Short name T351
Test name
Test status
Simulation time 59794115 ps
CPU time 1.74 seconds
Started Mar 31 01:46:03 PM PDT 24
Finished Mar 31 01:46:05 PM PDT 24
Peak memory 204232 kb
Host smart-539cfe41-2d84-4a44-a3f6-3b3636b21101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54938
4560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.549384560
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.3319472940
Short name T909
Test name
Test status
Simulation time 8362426484 ps
CPU time 7.26 seconds
Started Mar 31 01:46:21 PM PDT 24
Finished Mar 31 01:46:28 PM PDT 24
Peak memory 203908 kb
Host smart-02c9ce48-e44c-48ba-92f3-6c7ec42faf66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33194
72940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.3319472940
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.3823913401
Short name T549
Test name
Test status
Simulation time 8437526293 ps
CPU time 7.37 seconds
Started Mar 31 01:46:04 PM PDT 24
Finished Mar 31 01:46:11 PM PDT 24
Peak memory 204132 kb
Host smart-0191f922-8328-4718-b9d8-0dcf6eda809c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38239
13401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.3823913401
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.3720746671
Short name T294
Test name
Test status
Simulation time 8404795962 ps
CPU time 7.63 seconds
Started Mar 31 01:46:03 PM PDT 24
Finished Mar 31 01:46:11 PM PDT 24
Peak memory 204156 kb
Host smart-783af7ee-66d4-449d-a045-fa934d4f8c28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37207
46671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.3720746671
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1678071109
Short name T993
Test name
Test status
Simulation time 8363710197 ps
CPU time 9.32 seconds
Started Mar 31 01:46:03 PM PDT 24
Finished Mar 31 01:46:12 PM PDT 24
Peak memory 204144 kb
Host smart-94b8acad-ba0f-4133-a24f-ea014a598898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16780
71109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1678071109
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3451188951
Short name T133
Test name
Test status
Simulation time 8412744749 ps
CPU time 7.28 seconds
Started Mar 31 01:46:11 PM PDT 24
Finished Mar 31 01:46:18 PM PDT 24
Peak memory 203912 kb
Host smart-4da7d6af-4a83-4d05-a475-8c4b968db2cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34511
88951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3451188951
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.75670399
Short name T452
Test name
Test status
Simulation time 8400357436 ps
CPU time 7.5 seconds
Started Mar 31 01:46:18 PM PDT 24
Finished Mar 31 01:46:25 PM PDT 24
Peak memory 203912 kb
Host smart-340ec773-ef51-474b-91e7-cca5b55e54d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75670
399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.75670399
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.497845059
Short name T752
Test name
Test status
Simulation time 8369376048 ps
CPU time 7.54 seconds
Started Mar 31 01:46:13 PM PDT 24
Finished Mar 31 01:46:21 PM PDT 24
Peak memory 204148 kb
Host smart-dfcb29f2-def7-459c-ae69-3f0e2387badc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49784
5059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.497845059
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.1812912471
Short name T45
Test name
Test status
Simulation time 27421048 ps
CPU time 0.62 seconds
Started Mar 31 01:46:19 PM PDT 24
Finished Mar 31 01:46:19 PM PDT 24
Peak memory 204048 kb
Host smart-4880f420-0a18-4aed-a248-5943410de2d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18129
12471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.1812912471
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.4256667842
Short name T229
Test name
Test status
Simulation time 27934658177 ps
CPU time 47.06 seconds
Started Mar 31 01:46:18 PM PDT 24
Finished Mar 31 01:47:05 PM PDT 24
Peak memory 204096 kb
Host smart-3eef428a-5665-4ec3-b22b-4fcf274c964f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42566
67842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.4256667842
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.3164293597
Short name T1037
Test name
Test status
Simulation time 8403589104 ps
CPU time 7.43 seconds
Started Mar 31 01:46:11 PM PDT 24
Finished Mar 31 01:46:19 PM PDT 24
Peak memory 204120 kb
Host smart-14c91da3-b78f-4c40-ab9c-cc375ffbeb4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31642
93597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3164293597
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2597017741
Short name T767
Test name
Test status
Simulation time 8422663366 ps
CPU time 8.69 seconds
Started Mar 31 01:46:11 PM PDT 24
Finished Mar 31 01:46:20 PM PDT 24
Peak memory 204128 kb
Host smart-8b9e6092-f9bc-4148-90ae-038f1a3b4b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25970
17741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2597017741
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.4107852640
Short name T774
Test name
Test status
Simulation time 8382227388 ps
CPU time 7.43 seconds
Started Mar 31 01:46:18 PM PDT 24
Finished Mar 31 01:46:26 PM PDT 24
Peak memory 203908 kb
Host smart-b773857f-4097-4143-afb6-510aa4245924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41078
52640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.4107852640
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.4008669712
Short name T59
Test name
Test status
Simulation time 111222839 ps
CPU time 0.91 seconds
Started Mar 31 01:46:19 PM PDT 24
Finished Mar 31 01:46:20 PM PDT 24
Peak memory 220120 kb
Host smart-cb2d5efd-2de8-4a46-b114-2ccc1826443a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4008669712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.4008669712
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.3880746029
Short name T348
Test name
Test status
Simulation time 8359131053 ps
CPU time 8.39 seconds
Started Mar 31 01:46:11 PM PDT 24
Finished Mar 31 01:46:19 PM PDT 24
Peak memory 204100 kb
Host smart-604590c5-4539-4661-8ec1-5641136e91c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38807
46029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.3880746029
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.3792879734
Short name T776
Test name
Test status
Simulation time 8455837091 ps
CPU time 9.66 seconds
Started Mar 31 01:46:03 PM PDT 24
Finished Mar 31 01:46:13 PM PDT 24
Peak memory 204120 kb
Host smart-9827983c-2fa7-4c0a-beb5-e118633c5b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37928
79734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.3792879734
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.678864973
Short name T415
Test name
Test status
Simulation time 8375558377 ps
CPU time 6.92 seconds
Started Mar 31 01:46:11 PM PDT 24
Finished Mar 31 01:46:18 PM PDT 24
Peak memory 204140 kb
Host smart-acfa2770-306a-42c9-8b06-15ab953514ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67886
4973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.678864973
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.in_iso.1775589944
Short name T300
Test name
Test status
Simulation time 8403633682 ps
CPU time 8.45 seconds
Started Mar 31 01:51:54 PM PDT 24
Finished Mar 31 01:52:03 PM PDT 24
Peak memory 204124 kb
Host smart-44dc69b2-8764-43a2-a64d-3f0006967ad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17755
89944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.in_iso.1775589944
Directory /workspace/40.in_iso/latest

Test location /workspace/coverage/default/40.phy_config_usb_ref_disable.1210780980
Short name T615
Test name
Test status
Simulation time 8361139288 ps
CPU time 7.94 seconds
Started Mar 31 01:51:54 PM PDT 24
Finished Mar 31 01:52:02 PM PDT 24
Peak memory 204140 kb
Host smart-ac68a8e1-ab1e-4732-92ce-ae4790e38a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12107
80980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.phy_config_usb_ref_disable.1210780980
Directory /workspace/40.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1266503622
Short name T381
Test name
Test status
Simulation time 8367086713 ps
CPU time 7.39 seconds
Started Mar 31 01:51:50 PM PDT 24
Finished Mar 31 01:51:57 PM PDT 24
Peak memory 204092 kb
Host smart-723266ca-9707-4169-b374-66626e9f8db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12665
03622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1266503622
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_enable.129429083
Short name T811
Test name
Test status
Simulation time 8370880589 ps
CPU time 8.13 seconds
Started Mar 31 01:51:47 PM PDT 24
Finished Mar 31 01:51:55 PM PDT 24
Peak memory 204132 kb
Host smart-b89f1f6a-e24f-4b4a-8eb0-2763696a17f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12942
9083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.129429083
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.2239242009
Short name T96
Test name
Test status
Simulation time 60441974 ps
CPU time 1.51 seconds
Started Mar 31 01:51:49 PM PDT 24
Finished Mar 31 01:51:51 PM PDT 24
Peak memory 204220 kb
Host smart-7d784038-39c2-4a1d-8640-9a553918feea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22392
42009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2239242009
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.2469344101
Short name T84
Test name
Test status
Simulation time 8360662470 ps
CPU time 7.74 seconds
Started Mar 31 01:51:55 PM PDT 24
Finished Mar 31 01:52:03 PM PDT 24
Peak memory 204100 kb
Host smart-e5c8247f-97fa-436e-bc2e-23104521f3ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24693
44101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.2469344101
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.1442319794
Short name T442
Test name
Test status
Simulation time 8444108900 ps
CPU time 7.76 seconds
Started Mar 31 01:51:47 PM PDT 24
Finished Mar 31 01:51:55 PM PDT 24
Peak memory 204096 kb
Host smart-eb3fb1e9-fa12-42d7-99a3-fdea54b52d9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14423
19794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1442319794
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.232026112
Short name T303
Test name
Test status
Simulation time 8411580330 ps
CPU time 9.37 seconds
Started Mar 31 01:51:55 PM PDT 24
Finished Mar 31 01:52:04 PM PDT 24
Peak memory 204116 kb
Host smart-358c000d-e3dc-4c18-ab8b-e12d4c1c53d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23202
6112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.232026112
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2390018184
Short name T610
Test name
Test status
Simulation time 8368411510 ps
CPU time 8.13 seconds
Started Mar 31 01:51:57 PM PDT 24
Finished Mar 31 01:52:05 PM PDT 24
Peak memory 204112 kb
Host smart-08dc37f1-cf3f-47b0-a5f3-f8fa8f4db43e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23900
18184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2390018184
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.1059006726
Short name T832
Test name
Test status
Simulation time 8370468119 ps
CPU time 9.36 seconds
Started Mar 31 01:51:55 PM PDT 24
Finished Mar 31 01:52:04 PM PDT 24
Peak memory 204120 kb
Host smart-44f744f8-dbdb-4068-82a3-4c4a4abaa6c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10590
06726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.1059006726
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.3895509584
Short name T1063
Test name
Test status
Simulation time 8394366519 ps
CPU time 8.57 seconds
Started Mar 31 01:51:53 PM PDT 24
Finished Mar 31 01:52:02 PM PDT 24
Peak memory 204176 kb
Host smart-a32250c1-96ad-4c21-8665-73e6c8dbadee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38955
09584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.3895509584
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.1363195665
Short name T974
Test name
Test status
Simulation time 29230763 ps
CPU time 0.67 seconds
Started Mar 31 01:51:54 PM PDT 24
Finished Mar 31 01:51:54 PM PDT 24
Peak memory 204036 kb
Host smart-8e7ab3ac-426d-40e2-ac1e-bdf8e3b25d60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13631
95665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.1363195665
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.2968793369
Short name T200
Test name
Test status
Simulation time 30957738511 ps
CPU time 64.09 seconds
Started Mar 31 01:51:53 PM PDT 24
Finished Mar 31 01:52:57 PM PDT 24
Peak memory 204320 kb
Host smart-5ffbbcd0-314d-4b22-946e-a68eee483ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29687
93369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.2968793369
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.2320133677
Short name T560
Test name
Test status
Simulation time 8382891923 ps
CPU time 7.11 seconds
Started Mar 31 01:51:55 PM PDT 24
Finished Mar 31 01:52:02 PM PDT 24
Peak memory 204188 kb
Host smart-c59be32e-baca-45e3-8c01-71794a25e6b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23201
33677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.2320133677
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.1548220303
Short name T139
Test name
Test status
Simulation time 8395865384 ps
CPU time 7.36 seconds
Started Mar 31 01:51:54 PM PDT 24
Finished Mar 31 01:52:02 PM PDT 24
Peak memory 204104 kb
Host smart-8414e030-f2db-4190-94df-9c8b2846ce85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15482
20303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.1548220303
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.145604866
Short name T992
Test name
Test status
Simulation time 8408569628 ps
CPU time 8.11 seconds
Started Mar 31 01:51:53 PM PDT 24
Finished Mar 31 01:52:01 PM PDT 24
Peak memory 204096 kb
Host smart-69877a19-95cb-4562-ad67-50a0038459ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14560
4866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.145604866
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.1647119249
Short name T982
Test name
Test status
Simulation time 8362752591 ps
CPU time 7.6 seconds
Started Mar 31 01:51:54 PM PDT 24
Finished Mar 31 01:52:02 PM PDT 24
Peak memory 204104 kb
Host smart-75d7465a-5358-4871-808b-b22cd9e4352e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16471
19249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.1647119249
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.2839257489
Short name T172
Test name
Test status
Simulation time 8430799008 ps
CPU time 7.61 seconds
Started Mar 31 01:51:47 PM PDT 24
Finished Mar 31 01:51:55 PM PDT 24
Peak memory 204128 kb
Host smart-03812890-8a67-4c79-845f-46949553c79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28392
57489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2839257489
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.1096691113
Short name T659
Test name
Test status
Simulation time 8382897081 ps
CPU time 7.65 seconds
Started Mar 31 01:51:55 PM PDT 24
Finished Mar 31 01:52:03 PM PDT 24
Peak memory 204148 kb
Host smart-3845865f-0fcd-45c9-806a-950cca8a86a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10966
91113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.1096691113
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.in_iso.3449525328
Short name T789
Test name
Test status
Simulation time 8381366119 ps
CPU time 8.34 seconds
Started Mar 31 01:51:59 PM PDT 24
Finished Mar 31 01:52:07 PM PDT 24
Peak memory 204124 kb
Host smart-fe2ef7c8-d4a4-45c5-b1e5-8a55a42c7381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34495
25328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.in_iso.3449525328
Directory /workspace/41.in_iso/latest

Test location /workspace/coverage/default/41.phy_config_usb_ref_disable.3472988962
Short name T863
Test name
Test status
Simulation time 8362952322 ps
CPU time 8.92 seconds
Started Mar 31 01:51:59 PM PDT 24
Finished Mar 31 01:52:08 PM PDT 24
Peak memory 204096 kb
Host smart-bb5f6048-f59d-4d1f-ae56-c10df1b4977d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34729
88962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.phy_config_usb_ref_disable.3472988962
Directory /workspace/41.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.1911450422
Short name T564
Test name
Test status
Simulation time 8367856007 ps
CPU time 7.58 seconds
Started Mar 31 01:51:54 PM PDT 24
Finished Mar 31 01:52:02 PM PDT 24
Peak memory 204136 kb
Host smart-876bed5f-f09c-4d59-a7d2-34c08ddeb9f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19114
50422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.1911450422
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_enable.3502574164
Short name T1078
Test name
Test status
Simulation time 8368295704 ps
CPU time 8.9 seconds
Started Mar 31 01:51:54 PM PDT 24
Finished Mar 31 01:52:03 PM PDT 24
Peak memory 204256 kb
Host smart-e2adb7c8-c5c4-4506-9ac1-ff777b7643a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35025
74164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3502574164
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3424790426
Short name T816
Test name
Test status
Simulation time 52529877 ps
CPU time 1.55 seconds
Started Mar 31 01:51:53 PM PDT 24
Finished Mar 31 01:51:55 PM PDT 24
Peak memory 204272 kb
Host smart-0c37fd34-baef-466b-a49e-e7ea01484255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34247
90426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3424790426
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.958027665
Short name T211
Test name
Test status
Simulation time 8359970161 ps
CPU time 9.14 seconds
Started Mar 31 01:51:59 PM PDT 24
Finished Mar 31 01:52:08 PM PDT 24
Peak memory 204108 kb
Host smart-9323b8b3-2c4a-4946-97b3-d3741ef2370b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95802
7665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.958027665
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3623653578
Short name T635
Test name
Test status
Simulation time 8436829053 ps
CPU time 7.17 seconds
Started Mar 31 01:51:55 PM PDT 24
Finished Mar 31 01:52:02 PM PDT 24
Peak memory 204136 kb
Host smart-9e896017-001e-4564-ada7-baca5b3ad34e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36236
53578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3623653578
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.224590224
Short name T465
Test name
Test status
Simulation time 8410060655 ps
CPU time 7.44 seconds
Started Mar 31 01:51:53 PM PDT 24
Finished Mar 31 01:52:01 PM PDT 24
Peak memory 204132 kb
Host smart-0d5a324e-a75b-4dc6-9bbf-309ec5efe5e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22459
0224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.224590224
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.3823235544
Short name T808
Test name
Test status
Simulation time 8359698326 ps
CPU time 7.74 seconds
Started Mar 31 01:51:52 PM PDT 24
Finished Mar 31 01:51:59 PM PDT 24
Peak memory 204136 kb
Host smart-fe2a4d87-b1b3-42bd-be3c-8864897b7495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38232
35544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.3823235544
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.791855096
Short name T107
Test name
Test status
Simulation time 8418004603 ps
CPU time 7.63 seconds
Started Mar 31 01:51:59 PM PDT 24
Finished Mar 31 01:52:07 PM PDT 24
Peak memory 204084 kb
Host smart-0cf92a13-895b-4485-9e9f-a34359a187fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79185
5096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.791855096
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.3148273083
Short name T600
Test name
Test status
Simulation time 8383333556 ps
CPU time 7.02 seconds
Started Mar 31 01:51:59 PM PDT 24
Finished Mar 31 01:52:06 PM PDT 24
Peak memory 204072 kb
Host smart-b67b371e-b040-4736-a489-614886f1e1f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31482
73083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.3148273083
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2127726598
Short name T995
Test name
Test status
Simulation time 8399210512 ps
CPU time 8.03 seconds
Started Mar 31 01:51:59 PM PDT 24
Finished Mar 31 01:52:07 PM PDT 24
Peak memory 204156 kb
Host smart-12acf05e-cc25-47e5-a6c9-3ac648d6626d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21277
26598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2127726598
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2416319336
Short name T1007
Test name
Test status
Simulation time 27595014 ps
CPU time 0.6 seconds
Started Mar 31 01:51:59 PM PDT 24
Finished Mar 31 01:52:00 PM PDT 24
Peak memory 204056 kb
Host smart-09246577-a386-450d-884b-a1ba0de8a36e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24163
19336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2416319336
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.182358244
Short name T190
Test name
Test status
Simulation time 20933717028 ps
CPU time 41.96 seconds
Started Mar 31 01:51:59 PM PDT 24
Finished Mar 31 01:52:41 PM PDT 24
Peak memory 204232 kb
Host smart-34e2d42b-6c40-4c6c-8026-20840bb473ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18235
8244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.182358244
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1472052481
Short name T510
Test name
Test status
Simulation time 8364487226 ps
CPU time 7.41 seconds
Started Mar 31 01:52:03 PM PDT 24
Finished Mar 31 01:52:11 PM PDT 24
Peak memory 204152 kb
Host smart-c3387cef-e0d5-437e-a032-4460ce66f03f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14720
52481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1472052481
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.2501736087
Short name T1029
Test name
Test status
Simulation time 8379167228 ps
CPU time 9.67 seconds
Started Mar 31 01:52:03 PM PDT 24
Finished Mar 31 01:52:13 PM PDT 24
Peak memory 204120 kb
Host smart-662a838f-9fff-4238-8c22-476a46c58a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25017
36087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2501736087
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.3459554540
Short name T944
Test name
Test status
Simulation time 8406049046 ps
CPU time 8.14 seconds
Started Mar 31 01:51:59 PM PDT 24
Finished Mar 31 01:52:07 PM PDT 24
Peak memory 204056 kb
Host smart-bf91bc49-2d99-4efa-88c1-f07bd3739aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34595
54540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.3459554540
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.57187236
Short name T622
Test name
Test status
Simulation time 8360899630 ps
CPU time 7.14 seconds
Started Mar 31 01:51:58 PM PDT 24
Finished Mar 31 01:52:06 PM PDT 24
Peak memory 204112 kb
Host smart-824b9aac-7a25-4df7-8f20-ceb73122a588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57187
236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.57187236
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.612512273
Short name T173
Test name
Test status
Simulation time 8437991233 ps
CPU time 7.97 seconds
Started Mar 31 01:51:54 PM PDT 24
Finished Mar 31 01:52:02 PM PDT 24
Peak memory 204188 kb
Host smart-36fcf29e-fee2-4f70-a357-ea13adf2864f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61251
2273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.612512273
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.3524782450
Short name T952
Test name
Test status
Simulation time 8364913821 ps
CPU time 7.28 seconds
Started Mar 31 01:51:58 PM PDT 24
Finished Mar 31 01:52:06 PM PDT 24
Peak memory 204128 kb
Host smart-611e004c-233d-4024-ab18-36947ba5e22f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35247
82450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.3524782450
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.in_iso.3320259051
Short name T841
Test name
Test status
Simulation time 8443491374 ps
CPU time 8 seconds
Started Mar 31 01:52:12 PM PDT 24
Finished Mar 31 01:52:20 PM PDT 24
Peak memory 204108 kb
Host smart-4d3cfa9d-eb16-4c38-8458-aab436f1b075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33202
59051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.in_iso.3320259051
Directory /workspace/42.in_iso/latest

Test location /workspace/coverage/default/42.phy_config_usb_ref_disable.1474022492
Short name T539
Test name
Test status
Simulation time 8360894630 ps
CPU time 7.92 seconds
Started Mar 31 01:52:14 PM PDT 24
Finished Mar 31 01:52:22 PM PDT 24
Peak memory 204108 kb
Host smart-5ff201a0-e7d2-4606-84ae-00c04d4a2dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14740
22492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.phy_config_usb_ref_disable.1474022492
Directory /workspace/42.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.4261859675
Short name T878
Test name
Test status
Simulation time 8369636940 ps
CPU time 9.73 seconds
Started Mar 31 01:52:00 PM PDT 24
Finished Mar 31 01:52:10 PM PDT 24
Peak memory 204120 kb
Host smart-09d2188d-b0a6-4318-b3e0-df12550c3e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42618
59675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.4261859675
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_enable.1547541072
Short name T433
Test name
Test status
Simulation time 8373067959 ps
CPU time 8.25 seconds
Started Mar 31 01:52:02 PM PDT 24
Finished Mar 31 01:52:10 PM PDT 24
Peak memory 204088 kb
Host smart-085d0ede-ff34-460f-8543-6579eef91701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15475
41072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.1547541072
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3200463382
Short name T807
Test name
Test status
Simulation time 70277848 ps
CPU time 1.04 seconds
Started Mar 31 01:52:01 PM PDT 24
Finished Mar 31 01:52:02 PM PDT 24
Peak memory 204224 kb
Host smart-cd08a57c-8efd-4701-a518-39341d1f14b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32004
63382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3200463382
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.3381624608
Short name T1000
Test name
Test status
Simulation time 8358403607 ps
CPU time 9.19 seconds
Started Mar 31 01:52:06 PM PDT 24
Finished Mar 31 01:52:15 PM PDT 24
Peak memory 204144 kb
Host smart-bd69cb4d-1447-4e9f-a584-020858eedb30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33816
24608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.3381624608
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.908095340
Short name T138
Test name
Test status
Simulation time 8382152989 ps
CPU time 9.01 seconds
Started Mar 31 01:51:58 PM PDT 24
Finished Mar 31 01:52:08 PM PDT 24
Peak memory 204112 kb
Host smart-531bbab2-dea9-4e79-972e-8b52235c1a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90809
5340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.908095340
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.2923898658
Short name T533
Test name
Test status
Simulation time 8411653903 ps
CPU time 9.32 seconds
Started Mar 31 01:52:07 PM PDT 24
Finished Mar 31 01:52:16 PM PDT 24
Peak memory 204128 kb
Host smart-cd339408-d72e-43cb-b79b-3922b9d1fb30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29238
98658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.2923898658
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.3896222940
Short name T1040
Test name
Test status
Simulation time 8361570936 ps
CPU time 7.62 seconds
Started Mar 31 01:52:14 PM PDT 24
Finished Mar 31 01:52:22 PM PDT 24
Peak memory 204104 kb
Host smart-af303315-9f54-4042-b540-f3ced1736907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38962
22940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.3896222940
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.3168729399
Short name T123
Test name
Test status
Simulation time 8408511818 ps
CPU time 7.19 seconds
Started Mar 31 01:52:07 PM PDT 24
Finished Mar 31 01:52:14 PM PDT 24
Peak memory 204080 kb
Host smart-701a9805-4b2b-4130-8f8c-ce48fe1537fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31687
29399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.3168729399
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.3458896920
Short name T572
Test name
Test status
Simulation time 8375528037 ps
CPU time 7.35 seconds
Started Mar 31 01:52:07 PM PDT 24
Finished Mar 31 01:52:14 PM PDT 24
Peak memory 204120 kb
Host smart-0253cd24-e0f8-4d32-9b6e-9cc09195ba73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34588
96920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3458896920
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.925411306
Short name T760
Test name
Test status
Simulation time 8383146211 ps
CPU time 7.17 seconds
Started Mar 31 01:52:12 PM PDT 24
Finished Mar 31 01:52:19 PM PDT 24
Peak memory 204112 kb
Host smart-37393bdc-161b-467b-92bb-8f75f0d675fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92541
1306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.925411306
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.2144255696
Short name T434
Test name
Test status
Simulation time 30067660 ps
CPU time 0.63 seconds
Started Mar 31 01:52:12 PM PDT 24
Finished Mar 31 01:52:12 PM PDT 24
Peak memory 204048 kb
Host smart-c6b7eaf6-6330-499d-9f6d-33c3b953f85f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21442
55696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2144255696
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.2136201785
Short name T1021
Test name
Test status
Simulation time 13952983557 ps
CPU time 21.72 seconds
Started Mar 31 01:52:07 PM PDT 24
Finished Mar 31 01:52:29 PM PDT 24
Peak memory 204292 kb
Host smart-c0f3cdf7-8c3e-4a39-960c-44917773dc46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21362
01785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.2136201785
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.2059221847
Short name T425
Test name
Test status
Simulation time 8375065021 ps
CPU time 7.23 seconds
Started Mar 31 01:52:08 PM PDT 24
Finished Mar 31 01:52:15 PM PDT 24
Peak memory 204152 kb
Host smart-b29f831a-b222-44d4-849a-e97a77bb2350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20592
21847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2059221847
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.2261842910
Short name T654
Test name
Test status
Simulation time 8389853023 ps
CPU time 7.34 seconds
Started Mar 31 01:52:09 PM PDT 24
Finished Mar 31 01:52:16 PM PDT 24
Peak memory 204036 kb
Host smart-08f5e938-3d48-4977-b149-c18e23ba6000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22618
42910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2261842910
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.2891602677
Short name T330
Test name
Test status
Simulation time 8397851195 ps
CPU time 7.51 seconds
Started Mar 31 01:52:09 PM PDT 24
Finished Mar 31 01:52:16 PM PDT 24
Peak memory 204032 kb
Host smart-2695499e-03fb-4ffe-818b-acb6efec70cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28916
02677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.2891602677
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.720743435
Short name T950
Test name
Test status
Simulation time 8357682437 ps
CPU time 7.27 seconds
Started Mar 31 01:52:07 PM PDT 24
Finished Mar 31 01:52:14 PM PDT 24
Peak memory 204136 kb
Host smart-beaff66a-7cbe-4748-9c0f-15cd2ae3ebdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72074
3435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.720743435
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.1115549742
Short name T176
Test name
Test status
Simulation time 8439185244 ps
CPU time 9.37 seconds
Started Mar 31 01:52:01 PM PDT 24
Finished Mar 31 01:52:10 PM PDT 24
Peak memory 204108 kb
Host smart-4eee5a8d-81d2-45d7-ac67-18f8dd03b3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11155
49742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.1115549742
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.3578877653
Short name T869
Test name
Test status
Simulation time 8395812801 ps
CPU time 7.28 seconds
Started Mar 31 01:52:07 PM PDT 24
Finished Mar 31 01:52:15 PM PDT 24
Peak memory 204120 kb
Host smart-49447b4d-73fc-4981-8b20-2295c71ad563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35788
77653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.3578877653
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.in_iso.2922707001
Short name T737
Test name
Test status
Simulation time 8451569379 ps
CPU time 7.43 seconds
Started Mar 31 01:52:14 PM PDT 24
Finished Mar 31 01:52:22 PM PDT 24
Peak memory 204152 kb
Host smart-92dae53a-37cc-4d32-8a37-549805610c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29227
07001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.in_iso.2922707001
Directory /workspace/43.in_iso/latest

Test location /workspace/coverage/default/43.phy_config_usb_ref_disable.2635561187
Short name T327
Test name
Test status
Simulation time 8361516661 ps
CPU time 7.09 seconds
Started Mar 31 01:52:13 PM PDT 24
Finished Mar 31 01:52:21 PM PDT 24
Peak memory 204032 kb
Host smart-b4f9072f-2960-476c-a96e-a41fcc5767e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26355
61187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.phy_config_usb_ref_disable.2635561187
Directory /workspace/43.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.3858340589
Short name T850
Test name
Test status
Simulation time 8372665652 ps
CPU time 7.6 seconds
Started Mar 31 01:52:08 PM PDT 24
Finished Mar 31 01:52:16 PM PDT 24
Peak memory 204120 kb
Host smart-0285263b-13e6-4fae-ba96-c9abce313644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38583
40589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.3858340589
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_enable.1559844497
Short name T626
Test name
Test status
Simulation time 8370866918 ps
CPU time 7.73 seconds
Started Mar 31 01:52:08 PM PDT 24
Finished Mar 31 01:52:16 PM PDT 24
Peak memory 204144 kb
Host smart-ef962c39-32b4-480e-9173-498992ac1527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15598
44497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1559844497
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3267448756
Short name T761
Test name
Test status
Simulation time 214105978 ps
CPU time 1.87 seconds
Started Mar 31 01:52:07 PM PDT 24
Finished Mar 31 01:52:09 PM PDT 24
Peak memory 204240 kb
Host smart-284206ce-48a4-41a6-b136-251b8d8a9376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32674
48756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3267448756
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.1043760957
Short name T545
Test name
Test status
Simulation time 8363547960 ps
CPU time 7.36 seconds
Started Mar 31 01:52:14 PM PDT 24
Finished Mar 31 01:52:22 PM PDT 24
Peak memory 204136 kb
Host smart-71d1abe9-dc38-4063-868e-f69918c5468a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10437
60957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.1043760957
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.28985350
Short name T1058
Test name
Test status
Simulation time 8412288600 ps
CPU time 9.24 seconds
Started Mar 31 01:52:08 PM PDT 24
Finished Mar 31 01:52:18 PM PDT 24
Peak memory 204144 kb
Host smart-06b67125-dff7-464c-a6e4-162ee65cc6da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28985
350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.28985350
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.3531216070
Short name T470
Test name
Test status
Simulation time 8363554004 ps
CPU time 7.22 seconds
Started Mar 31 01:52:07 PM PDT 24
Finished Mar 31 01:52:14 PM PDT 24
Peak memory 204128 kb
Host smart-3f508d3d-ce56-40b2-b2a2-fd6c1073395b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35312
16070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.3531216070
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.2654375018
Short name T118
Test name
Test status
Simulation time 8419977449 ps
CPU time 7.84 seconds
Started Mar 31 01:52:05 PM PDT 24
Finished Mar 31 01:52:13 PM PDT 24
Peak memory 204128 kb
Host smart-1b8ebd7f-09f3-4c2e-bdb1-358a02140095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26543
75018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2654375018
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.1320960797
Short name T362
Test name
Test status
Simulation time 8392280368 ps
CPU time 8.02 seconds
Started Mar 31 01:52:12 PM PDT 24
Finished Mar 31 01:52:20 PM PDT 24
Peak memory 204104 kb
Host smart-2902a35d-078c-4715-a72b-fe6788027bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13209
60797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.1320960797
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.2050826620
Short name T562
Test name
Test status
Simulation time 8398112662 ps
CPU time 7.83 seconds
Started Mar 31 01:52:13 PM PDT 24
Finished Mar 31 01:52:21 PM PDT 24
Peak memory 204112 kb
Host smart-f6fc1d59-12de-431a-a51d-e10146f37c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20508
26620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.2050826620
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.3036722678
Short name T1038
Test name
Test status
Simulation time 25587125 ps
CPU time 0.63 seconds
Started Mar 31 01:52:13 PM PDT 24
Finished Mar 31 01:52:14 PM PDT 24
Peak memory 204040 kb
Host smart-31b40ab3-5a2d-4aac-848f-5761c6295348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30367
22678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.3036722678
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.719019453
Short name T191
Test name
Test status
Simulation time 16003802377 ps
CPU time 26.66 seconds
Started Mar 31 01:52:13 PM PDT 24
Finished Mar 31 01:52:40 PM PDT 24
Peak memory 204324 kb
Host smart-9d22d70d-1995-4b0b-a187-808893420ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71901
9453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.719019453
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.3713852833
Short name T345
Test name
Test status
Simulation time 8370596388 ps
CPU time 9.05 seconds
Started Mar 31 01:52:17 PM PDT 24
Finished Mar 31 01:52:26 PM PDT 24
Peak memory 204132 kb
Host smart-99a12e5f-b453-474a-bf67-9df2467115fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37138
52833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.3713852833
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.453061062
Short name T518
Test name
Test status
Simulation time 8391358495 ps
CPU time 9.63 seconds
Started Mar 31 01:52:15 PM PDT 24
Finished Mar 31 01:52:24 PM PDT 24
Peak memory 204148 kb
Host smart-ad27a3b4-b21b-4c45-a638-166b06f0bc40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45306
1062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.453061062
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.1980374496
Short name T92
Test name
Test status
Simulation time 8387373069 ps
CPU time 7.28 seconds
Started Mar 31 01:52:15 PM PDT 24
Finished Mar 31 01:52:23 PM PDT 24
Peak memory 204116 kb
Host smart-2ce592fa-77d8-42f5-b079-484d10c9fa43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19803
74496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.1980374496
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.60892641
Short name T1035
Test name
Test status
Simulation time 8357973050 ps
CPU time 8.74 seconds
Started Mar 31 01:52:19 PM PDT 24
Finished Mar 31 01:52:28 PM PDT 24
Peak memory 204136 kb
Host smart-06cd4dba-2fa4-4936-a38b-a1a585a1e2df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60892
641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.60892641
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.3931727089
Short name T163
Test name
Test status
Simulation time 8409332152 ps
CPU time 8.79 seconds
Started Mar 31 01:52:07 PM PDT 24
Finished Mar 31 01:52:16 PM PDT 24
Peak memory 204064 kb
Host smart-f4cd770f-c398-46f5-833f-987fabe5b575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39317
27089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.3931727089
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.857491962
Short name T660
Test name
Test status
Simulation time 8401242212 ps
CPU time 8.27 seconds
Started Mar 31 01:52:13 PM PDT 24
Finished Mar 31 01:52:21 PM PDT 24
Peak memory 204120 kb
Host smart-51b59ec6-ddab-4091-b228-47326dcaff52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85749
1962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.857491962
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.in_iso.436989361
Short name T768
Test name
Test status
Simulation time 8398927301 ps
CPU time 7.5 seconds
Started Mar 31 01:52:21 PM PDT 24
Finished Mar 31 01:52:28 PM PDT 24
Peak memory 204136 kb
Host smart-1ee27c31-7388-4782-b959-6ae6fc10f30e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43698
9361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.in_iso.436989361
Directory /workspace/44.in_iso/latest

Test location /workspace/coverage/default/44.phy_config_usb_ref_disable.2533951197
Short name T609
Test name
Test status
Simulation time 8367333259 ps
CPU time 9.72 seconds
Started Mar 31 01:52:21 PM PDT 24
Finished Mar 31 01:52:31 PM PDT 24
Peak memory 204116 kb
Host smart-5eda5464-b956-46c7-a61a-eebc9c37249f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25339
51197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.phy_config_usb_ref_disable.2533951197
Directory /workspace/44.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.2793401544
Short name T316
Test name
Test status
Simulation time 8366797840 ps
CPU time 7.66 seconds
Started Mar 31 01:52:19 PM PDT 24
Finished Mar 31 01:52:26 PM PDT 24
Peak memory 204100 kb
Host smart-178e7c41-6803-4a93-8f2f-b6ec254b04b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27934
01544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.2793401544
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_enable.1840318632
Short name T656
Test name
Test status
Simulation time 8369216159 ps
CPU time 6.99 seconds
Started Mar 31 01:52:12 PM PDT 24
Finished Mar 31 01:52:19 PM PDT 24
Peak memory 204124 kb
Host smart-4e2952a9-e5d5-4d17-a639-f52f836c196a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18403
18632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.1840318632
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.2119910905
Short name T556
Test name
Test status
Simulation time 165123822 ps
CPU time 1.76 seconds
Started Mar 31 01:52:23 PM PDT 24
Finished Mar 31 01:52:25 PM PDT 24
Peak memory 204240 kb
Host smart-aacfa674-4cd9-4659-abd0-528a306ada0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21199
10905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.2119910905
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.1313125788
Short name T219
Test name
Test status
Simulation time 8360928357 ps
CPU time 7.22 seconds
Started Mar 31 01:52:21 PM PDT 24
Finished Mar 31 01:52:28 PM PDT 24
Peak memory 204196 kb
Host smart-273f41ea-522b-4d45-96eb-505bb314a9dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13131
25788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.1313125788
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.2038677691
Short name T147
Test name
Test status
Simulation time 8385443638 ps
CPU time 7.56 seconds
Started Mar 31 01:52:22 PM PDT 24
Finished Mar 31 01:52:30 PM PDT 24
Peak memory 204056 kb
Host smart-2ab91ade-a5b6-48d9-94ce-bdd817c3de63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20386
77691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.2038677691
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.788317293
Short name T941
Test name
Test status
Simulation time 8406866905 ps
CPU time 7.42 seconds
Started Mar 31 01:52:21 PM PDT 24
Finished Mar 31 01:52:29 PM PDT 24
Peak memory 204128 kb
Host smart-1d91f397-b5ea-4497-8247-e5058e8b8623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78831
7293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.788317293
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.1212672713
Short name T904
Test name
Test status
Simulation time 8367833650 ps
CPU time 7.25 seconds
Started Mar 31 01:52:21 PM PDT 24
Finished Mar 31 01:52:29 PM PDT 24
Peak memory 204140 kb
Host smart-7f46bd8e-b9d5-454b-a546-bd457da64520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12126
72713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.1212672713
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.761698468
Short name T894
Test name
Test status
Simulation time 8428892161 ps
CPU time 7.14 seconds
Started Mar 31 01:52:21 PM PDT 24
Finished Mar 31 01:52:28 PM PDT 24
Peak memory 204084 kb
Host smart-4913d61e-abbc-4271-9f53-a8e115393d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76169
8468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.761698468
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.4084130831
Short name T1013
Test name
Test status
Simulation time 8387120525 ps
CPU time 8.25 seconds
Started Mar 31 01:52:22 PM PDT 24
Finished Mar 31 01:52:30 PM PDT 24
Peak memory 204120 kb
Host smart-e7fbd48e-97b3-4762-9145-0028406dd00f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40841
30831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.4084130831
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3915676571
Short name T791
Test name
Test status
Simulation time 8368730151 ps
CPU time 8.35 seconds
Started Mar 31 01:52:22 PM PDT 24
Finished Mar 31 01:52:31 PM PDT 24
Peak memory 204136 kb
Host smart-86e8f826-e6ca-4576-92b7-e550006c028e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39156
76571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3915676571
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.2553232538
Short name T939
Test name
Test status
Simulation time 28335839 ps
CPU time 0.66 seconds
Started Mar 31 01:52:24 PM PDT 24
Finished Mar 31 01:52:25 PM PDT 24
Peak memory 204044 kb
Host smart-5b7d031b-967e-4176-9a0b-1eefe5cc0792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25532
32538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.2553232538
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.3983705721
Short name T47
Test name
Test status
Simulation time 30180207154 ps
CPU time 56.09 seconds
Started Mar 31 01:52:21 PM PDT 24
Finished Mar 31 01:53:17 PM PDT 24
Peak memory 204528 kb
Host smart-59d56eed-588b-4379-84ef-5f056016f4fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39837
05721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.3983705721
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.1464662393
Short name T643
Test name
Test status
Simulation time 8385393160 ps
CPU time 7.97 seconds
Started Mar 31 01:52:24 PM PDT 24
Finished Mar 31 01:52:32 PM PDT 24
Peak memory 204104 kb
Host smart-ed8a9ef2-8afe-4712-96a3-437e65de1385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14646
62393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.1464662393
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.3904118232
Short name T158
Test name
Test status
Simulation time 8377788443 ps
CPU time 7.77 seconds
Started Mar 31 01:52:21 PM PDT 24
Finished Mar 31 01:52:29 PM PDT 24
Peak memory 204104 kb
Host smart-bda024f0-8395-4db3-86f9-30fe5b3fc0dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39041
18232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.3904118232
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.1749666188
Short name T829
Test name
Test status
Simulation time 8371443902 ps
CPU time 9.12 seconds
Started Mar 31 01:52:23 PM PDT 24
Finished Mar 31 01:52:33 PM PDT 24
Peak memory 204068 kb
Host smart-26dabb9c-dadf-41a9-97f4-e0b9ee8767f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17496
66188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.1749666188
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3227011473
Short name T438
Test name
Test status
Simulation time 8360141918 ps
CPU time 7.4 seconds
Started Mar 31 01:52:21 PM PDT 24
Finished Mar 31 01:52:28 PM PDT 24
Peak memory 204140 kb
Host smart-6085d215-fefd-48b7-bbdb-ba076ad52ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32270
11473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3227011473
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.685841010
Short name T30
Test name
Test status
Simulation time 8400632384 ps
CPU time 8.21 seconds
Started Mar 31 01:52:12 PM PDT 24
Finished Mar 31 01:52:20 PM PDT 24
Peak memory 204368 kb
Host smart-6ea214ec-2080-44e0-baa4-b8b341644786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68584
1010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.685841010
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2163011162
Short name T512
Test name
Test status
Simulation time 8409960121 ps
CPU time 7.56 seconds
Started Mar 31 01:52:21 PM PDT 24
Finished Mar 31 01:52:28 PM PDT 24
Peak memory 204116 kb
Host smart-8912ceee-610c-439f-acf3-9dd688326718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21630
11162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.2163011162
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.in_iso.517987921
Short name T80
Test name
Test status
Simulation time 8428231952 ps
CPU time 8.64 seconds
Started Mar 31 01:52:35 PM PDT 24
Finished Mar 31 01:52:44 PM PDT 24
Peak memory 204140 kb
Host smart-3efac448-81d4-44bc-bd2f-5ad7c46e757b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51798
7921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.in_iso.517987921
Directory /workspace/45.in_iso/latest

Test location /workspace/coverage/default/45.phy_config_usb_ref_disable.369832556
Short name T7
Test name
Test status
Simulation time 8360021749 ps
CPU time 7.35 seconds
Started Mar 31 01:52:28 PM PDT 24
Finished Mar 31 01:52:36 PM PDT 24
Peak memory 204068 kb
Host smart-ea82b87f-aa99-4d80-9ba6-21acb39ba841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36983
2556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.phy_config_usb_ref_disable.369832556
Directory /workspace/45.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.2913693478
Short name T90
Test name
Test status
Simulation time 8370228423 ps
CPU time 7.05 seconds
Started Mar 31 01:52:27 PM PDT 24
Finished Mar 31 01:52:34 PM PDT 24
Peak memory 204076 kb
Host smart-6119e238-ad60-4bf1-a0aa-22e26a987871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29136
93478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.2913693478
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_enable.12230628
Short name T879
Test name
Test status
Simulation time 8372612505 ps
CPU time 7.63 seconds
Started Mar 31 01:52:27 PM PDT 24
Finished Mar 31 01:52:34 PM PDT 24
Peak memory 204008 kb
Host smart-548c7048-d56c-45e0-82d6-01bda2d63517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12230
628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.12230628
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.1218812113
Short name T463
Test name
Test status
Simulation time 126968441 ps
CPU time 1.24 seconds
Started Mar 31 01:52:27 PM PDT 24
Finished Mar 31 01:52:28 PM PDT 24
Peak memory 204220 kb
Host smart-fb1eb837-25ff-4fce-b5cb-0484dd14afd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12188
12113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1218812113
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3106607380
Short name T221
Test name
Test status
Simulation time 8361290917 ps
CPU time 8.34 seconds
Started Mar 31 01:52:36 PM PDT 24
Finished Mar 31 01:52:44 PM PDT 24
Peak memory 204100 kb
Host smart-637783bf-2541-452e-acfa-c01acd5f650c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31066
07380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3106607380
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2525464709
Short name T980
Test name
Test status
Simulation time 8449566409 ps
CPU time 8.44 seconds
Started Mar 31 01:52:26 PM PDT 24
Finished Mar 31 01:52:34 PM PDT 24
Peak memory 204112 kb
Host smart-3075098d-60c1-4000-8b9d-8846aa35bfba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25254
64709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2525464709
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.637756142
Short name T1034
Test name
Test status
Simulation time 8413812860 ps
CPU time 7.23 seconds
Started Mar 31 01:52:28 PM PDT 24
Finished Mar 31 01:52:35 PM PDT 24
Peak memory 204144 kb
Host smart-ec3a6dc4-2546-460a-b3ff-722adacf422e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63775
6142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.637756142
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2135429046
Short name T796
Test name
Test status
Simulation time 8363977499 ps
CPU time 7.68 seconds
Started Mar 31 01:52:27 PM PDT 24
Finished Mar 31 01:52:34 PM PDT 24
Peak memory 204108 kb
Host smart-09cf8000-d843-4e19-9dcb-ac02386149f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21354
29046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2135429046
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.3120502589
Short name T129
Test name
Test status
Simulation time 8434658175 ps
CPU time 9.77 seconds
Started Mar 31 01:52:28 PM PDT 24
Finished Mar 31 01:52:38 PM PDT 24
Peak memory 204116 kb
Host smart-2cc3e2a7-4d45-4f29-af46-18912575fb67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31205
02589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3120502589
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.2713796294
Short name T749
Test name
Test status
Simulation time 8366332543 ps
CPU time 7.38 seconds
Started Mar 31 01:52:30 PM PDT 24
Finished Mar 31 01:52:38 PM PDT 24
Peak memory 204096 kb
Host smart-fbb3d01d-901f-467a-92f3-164cc5af3796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27137
96294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.2713796294
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.4237950515
Short name T380
Test name
Test status
Simulation time 8375188025 ps
CPU time 7.08 seconds
Started Mar 31 01:52:26 PM PDT 24
Finished Mar 31 01:52:33 PM PDT 24
Peak memory 204104 kb
Host smart-7e4552dd-2c18-4ad8-8a35-b15a71dbfbf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42379
50515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.4237950515
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.3118497834
Short name T387
Test name
Test status
Simulation time 23887611 ps
CPU time 0.67 seconds
Started Mar 31 01:52:36 PM PDT 24
Finished Mar 31 01:52:37 PM PDT 24
Peak memory 204092 kb
Host smart-be661de2-7e5a-4bb0-a60c-0474d98ad465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31184
97834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.3118497834
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.1235332875
Short name T882
Test name
Test status
Simulation time 19648735944 ps
CPU time 35 seconds
Started Mar 31 01:52:28 PM PDT 24
Finished Mar 31 01:53:03 PM PDT 24
Peak memory 204328 kb
Host smart-9d39081d-f494-4997-a553-52d5ca58f5eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12353
32875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.1235332875
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.4033975218
Short name T820
Test name
Test status
Simulation time 8376886520 ps
CPU time 7.04 seconds
Started Mar 31 01:52:27 PM PDT 24
Finished Mar 31 01:52:35 PM PDT 24
Peak memory 204108 kb
Host smart-275eaab3-4855-4287-bde2-cae486c99e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40339
75218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.4033975218
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.261970399
Short name T144
Test name
Test status
Simulation time 8426554124 ps
CPU time 7.81 seconds
Started Mar 31 01:52:27 PM PDT 24
Finished Mar 31 01:52:35 PM PDT 24
Peak memory 204136 kb
Host smart-7612e2c2-5e02-4697-84df-330683763a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26197
0399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.261970399
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.49207825
Short name T804
Test name
Test status
Simulation time 8385726999 ps
CPU time 8.21 seconds
Started Mar 31 01:52:28 PM PDT 24
Finished Mar 31 01:52:37 PM PDT 24
Peak memory 204084 kb
Host smart-57480ba7-62a8-4b09-b6a8-ccd68c2ca57b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49207
825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.49207825
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.3918669335
Short name T1076
Test name
Test status
Simulation time 8363795346 ps
CPU time 7.22 seconds
Started Mar 31 01:52:31 PM PDT 24
Finished Mar 31 01:52:39 PM PDT 24
Peak memory 204148 kb
Host smart-8bad1480-2a9f-42a3-a0a3-8e7eef7b09d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39186
69335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.3918669335
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.2460550772
Short name T179
Test name
Test status
Simulation time 8409324981 ps
CPU time 7.45 seconds
Started Mar 31 01:52:26 PM PDT 24
Finished Mar 31 01:52:34 PM PDT 24
Peak memory 204140 kb
Host smart-3dce7958-8f09-4aa7-b1e1-82cbfebcda2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24605
50772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.2460550772
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.3730323426
Short name T999
Test name
Test status
Simulation time 8397135767 ps
CPU time 8.07 seconds
Started Mar 31 01:52:30 PM PDT 24
Finished Mar 31 01:52:39 PM PDT 24
Peak memory 204132 kb
Host smart-7c09a00f-5827-4fd1-a0af-5c4eb01e2ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37303
23426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.3730323426
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.in_iso.1729683784
Short name T597
Test name
Test status
Simulation time 8451110990 ps
CPU time 8.94 seconds
Started Mar 31 01:52:37 PM PDT 24
Finished Mar 31 01:52:46 PM PDT 24
Peak memory 204108 kb
Host smart-521ce1bb-ca4e-43d2-877c-efcb36a6c20c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17296
83784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.in_iso.1729683784
Directory /workspace/46.in_iso/latest

Test location /workspace/coverage/default/46.phy_config_usb_ref_disable.3844091738
Short name T517
Test name
Test status
Simulation time 8359318776 ps
CPU time 9.22 seconds
Started Mar 31 01:52:38 PM PDT 24
Finished Mar 31 01:52:47 PM PDT 24
Peak memory 204068 kb
Host smart-26fadd31-3a03-49e8-9cc8-7375a7716ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38440
91738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.phy_config_usb_ref_disable.3844091738
Directory /workspace/46.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3912015723
Short name T954
Test name
Test status
Simulation time 8371483408 ps
CPU time 7.38 seconds
Started Mar 31 01:52:35 PM PDT 24
Finished Mar 31 01:52:43 PM PDT 24
Peak memory 204068 kb
Host smart-1f594fcb-38e2-4c2d-b2fd-24cec92e0bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39120
15723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3912015723
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_enable.3513574322
Short name T923
Test name
Test status
Simulation time 8374181158 ps
CPU time 9 seconds
Started Mar 31 01:52:34 PM PDT 24
Finished Mar 31 01:52:44 PM PDT 24
Peak memory 204092 kb
Host smart-dfde11a8-f8ed-4231-b2bc-b013e1a2b6c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35135
74322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.3513574322
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.966575066
Short name T343
Test name
Test status
Simulation time 309114111 ps
CPU time 2.28 seconds
Started Mar 31 01:52:37 PM PDT 24
Finished Mar 31 01:52:40 PM PDT 24
Peak memory 204212 kb
Host smart-bd8641ef-7ec6-4c13-bd4c-aea9d5ceaf00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96657
5066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.966575066
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.1879803467
Short name T212
Test name
Test status
Simulation time 8361721432 ps
CPU time 7.01 seconds
Started Mar 31 01:52:35 PM PDT 24
Finished Mar 31 01:52:42 PM PDT 24
Peak memory 204108 kb
Host smart-8f1518f8-e37a-4e00-bb35-3bd8d2c95238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18798
03467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.1879803467
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.954744629
Short name T1069
Test name
Test status
Simulation time 8457685510 ps
CPU time 7.66 seconds
Started Mar 31 01:52:38 PM PDT 24
Finished Mar 31 01:52:46 PM PDT 24
Peak memory 204100 kb
Host smart-4937d8bc-02ea-41bb-8e18-4c3358702690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95474
4629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.954744629
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2800665103
Short name T389
Test name
Test status
Simulation time 8407126405 ps
CPU time 8.23 seconds
Started Mar 31 01:52:36 PM PDT 24
Finished Mar 31 01:52:44 PM PDT 24
Peak memory 204020 kb
Host smart-114fb45f-cd87-474b-b6f1-34438cf0b755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28006
65103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2800665103
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.3906462128
Short name T755
Test name
Test status
Simulation time 8367022392 ps
CPU time 8.33 seconds
Started Mar 31 01:52:35 PM PDT 24
Finished Mar 31 01:52:43 PM PDT 24
Peak memory 204136 kb
Host smart-22635893-8d44-4edb-8cf4-06f7388ada8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39064
62128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.3906462128
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.2257993823
Short name T120
Test name
Test status
Simulation time 8417910913 ps
CPU time 7.38 seconds
Started Mar 31 01:52:33 PM PDT 24
Finished Mar 31 01:52:41 PM PDT 24
Peak memory 204148 kb
Host smart-13a8105c-2058-4dd9-a7b8-223bc15161e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22579
93823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.2257993823
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.462139417
Short name T395
Test name
Test status
Simulation time 8381875538 ps
CPU time 8.81 seconds
Started Mar 31 01:52:39 PM PDT 24
Finished Mar 31 01:52:48 PM PDT 24
Peak memory 204112 kb
Host smart-c4fdec1c-0e0b-41e1-84a0-c76487201e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46213
9417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.462139417
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2770778474
Short name T905
Test name
Test status
Simulation time 8398724477 ps
CPU time 9.01 seconds
Started Mar 31 01:52:39 PM PDT 24
Finished Mar 31 01:52:48 PM PDT 24
Peak memory 204144 kb
Host smart-4c860fce-d78e-4de6-a1fc-ee06dca22e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27707
78474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2770778474
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.2713533177
Short name T880
Test name
Test status
Simulation time 30669100 ps
CPU time 0.68 seconds
Started Mar 31 01:52:35 PM PDT 24
Finished Mar 31 01:52:36 PM PDT 24
Peak memory 204108 kb
Host smart-1d6bd869-2cf8-4cab-b37e-acbf5c49f4fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27135
33177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.2713533177
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.2445351282
Short name T783
Test name
Test status
Simulation time 22532056766 ps
CPU time 45.57 seconds
Started Mar 31 01:52:36 PM PDT 24
Finished Mar 31 01:53:22 PM PDT 24
Peak memory 204428 kb
Host smart-b230f19a-651f-4c51-b609-5d6a21620c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24453
51282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.2445351282
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.3235080640
Short name T559
Test name
Test status
Simulation time 8403163251 ps
CPU time 8.65 seconds
Started Mar 31 01:52:37 PM PDT 24
Finished Mar 31 01:52:46 PM PDT 24
Peak memory 204052 kb
Host smart-1bdd79fc-108c-462e-ab02-08c1a78c05fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32350
80640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.3235080640
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.3821821045
Short name T679
Test name
Test status
Simulation time 8425898083 ps
CPU time 7.76 seconds
Started Mar 31 01:52:37 PM PDT 24
Finished Mar 31 01:52:45 PM PDT 24
Peak memory 204076 kb
Host smart-8fbfec4f-57a4-4a76-a5c4-ea071e759e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38218
21045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.3821821045
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.2675942209
Short name T367
Test name
Test status
Simulation time 8367061673 ps
CPU time 7.51 seconds
Started Mar 31 01:52:36 PM PDT 24
Finished Mar 31 01:52:44 PM PDT 24
Peak memory 204124 kb
Host smart-a97c9dab-71d3-4d6c-a127-bc4c74beba30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26759
42209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.2675942209
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.3324089484
Short name T576
Test name
Test status
Simulation time 8362246960 ps
CPU time 7.63 seconds
Started Mar 31 01:52:38 PM PDT 24
Finished Mar 31 01:52:46 PM PDT 24
Peak memory 204104 kb
Host smart-830b1d8e-41f8-4749-9761-52a81a39907b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33240
89484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.3324089484
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.3990664839
Short name T181
Test name
Test status
Simulation time 8407754960 ps
CPU time 7 seconds
Started Mar 31 01:52:34 PM PDT 24
Finished Mar 31 01:52:41 PM PDT 24
Peak memory 204124 kb
Host smart-7740de70-9834-42b2-9b3e-b1ab22b3d249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39906
64839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3990664839
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.2705687622
Short name T493
Test name
Test status
Simulation time 8388892240 ps
CPU time 7.23 seconds
Started Mar 31 01:52:38 PM PDT 24
Finished Mar 31 01:52:45 PM PDT 24
Peak memory 204100 kb
Host smart-25cbc269-5d17-4fb5-bd49-d26a59afded7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27056
87622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.2705687622
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.in_iso.2042172949
Short name T748
Test name
Test status
Simulation time 8434867499 ps
CPU time 7.56 seconds
Started Mar 31 01:52:44 PM PDT 24
Finished Mar 31 01:52:52 PM PDT 24
Peak memory 204140 kb
Host smart-77ef3334-a24f-483f-a84e-4f6e4ba42952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20421
72949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.in_iso.2042172949
Directory /workspace/47.in_iso/latest

Test location /workspace/coverage/default/47.phy_config_usb_ref_disable.319609700
Short name T1028
Test name
Test status
Simulation time 8362866726 ps
CPU time 7.6 seconds
Started Mar 31 01:52:44 PM PDT 24
Finished Mar 31 01:52:52 PM PDT 24
Peak memory 204136 kb
Host smart-65fbf901-4acb-4f8b-adf9-11ca35f19900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31960
9700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.phy_config_usb_ref_disable.319609700
Directory /workspace/47.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2136310364
Short name T785
Test name
Test status
Simulation time 8365598330 ps
CPU time 7.44 seconds
Started Mar 31 01:52:51 PM PDT 24
Finished Mar 31 01:52:59 PM PDT 24
Peak memory 204100 kb
Host smart-c84bb0a1-1dae-43ce-85fe-14dad7391e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21363
10364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2136310364
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_enable.3812840360
Short name T506
Test name
Test status
Simulation time 8365504684 ps
CPU time 7.74 seconds
Started Mar 31 01:52:44 PM PDT 24
Finished Mar 31 01:52:52 PM PDT 24
Peak memory 204132 kb
Host smart-a9b0d0bf-5b28-49cb-9b78-0249a491560a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38128
40360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.3812840360
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.2795538536
Short name T429
Test name
Test status
Simulation time 136412559 ps
CPU time 1.42 seconds
Started Mar 31 01:52:45 PM PDT 24
Finished Mar 31 01:52:46 PM PDT 24
Peak memory 204220 kb
Host smart-552173d7-2ddc-4bc4-88ec-be58a851fafb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27955
38536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.2795538536
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.1220527611
Short name T213
Test name
Test status
Simulation time 8361842936 ps
CPU time 7.75 seconds
Started Mar 31 01:52:45 PM PDT 24
Finished Mar 31 01:52:52 PM PDT 24
Peak memory 204196 kb
Host smart-bbaff4e5-7cb6-4600-a0da-219b5736be2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12205
27611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.1220527611
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.2126172724
Short name T764
Test name
Test status
Simulation time 8422661419 ps
CPU time 7.54 seconds
Started Mar 31 01:52:51 PM PDT 24
Finished Mar 31 01:52:59 PM PDT 24
Peak memory 204100 kb
Host smart-b3951e2a-1ac6-4945-8e09-e5b87912e3d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21261
72724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2126172724
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.1320656079
Short name T734
Test name
Test status
Simulation time 8408213092 ps
CPU time 7.11 seconds
Started Mar 31 01:52:44 PM PDT 24
Finished Mar 31 01:52:51 PM PDT 24
Peak memory 204136 kb
Host smart-bf9d05c5-48f6-41d5-b744-516092ffbe5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13206
56079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.1320656079
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.1511417297
Short name T409
Test name
Test status
Simulation time 8364544438 ps
CPU time 7.23 seconds
Started Mar 31 01:52:43 PM PDT 24
Finished Mar 31 01:52:51 PM PDT 24
Peak memory 204144 kb
Host smart-9eb2e0b5-7b12-465a-82b6-a3eb322a99fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15114
17297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.1511417297
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.3337958990
Short name T529
Test name
Test status
Simulation time 8432054932 ps
CPU time 7.44 seconds
Started Mar 31 01:52:46 PM PDT 24
Finished Mar 31 01:52:53 PM PDT 24
Peak memory 204076 kb
Host smart-677a93e4-0def-4d9e-99e3-06ded1ea853c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33379
58990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.3337958990
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.554129307
Short name T390
Test name
Test status
Simulation time 8375414216 ps
CPU time 7.69 seconds
Started Mar 31 01:52:42 PM PDT 24
Finished Mar 31 01:52:50 PM PDT 24
Peak memory 204088 kb
Host smart-b506c06d-25f0-4b3c-ae3c-3a8bcdb7f1bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55412
9307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.554129307
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1225140304
Short name T33
Test name
Test status
Simulation time 8382832039 ps
CPU time 7.32 seconds
Started Mar 31 01:52:44 PM PDT 24
Finished Mar 31 01:52:52 PM PDT 24
Peak memory 204168 kb
Host smart-61f1b43c-5bc8-423a-9b88-23dc862cfd42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12251
40304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1225140304
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.605579448
Short name T606
Test name
Test status
Simulation time 29603499 ps
CPU time 0.63 seconds
Started Mar 31 01:52:41 PM PDT 24
Finished Mar 31 01:52:42 PM PDT 24
Peak memory 204212 kb
Host smart-03350f40-08db-48f3-aca1-a7f69be0e43b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60557
9448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.605579448
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.2335361501
Short name T1072
Test name
Test status
Simulation time 29656795486 ps
CPU time 54.75 seconds
Started Mar 31 01:52:44 PM PDT 24
Finished Mar 31 01:53:39 PM PDT 24
Peak memory 204328 kb
Host smart-80ec5028-a1fb-4fc2-95e0-3c6c0904e7b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23353
61501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.2335361501
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.654484176
Short name T871
Test name
Test status
Simulation time 8391478584 ps
CPU time 7.72 seconds
Started Mar 31 01:52:43 PM PDT 24
Finished Mar 31 01:52:51 PM PDT 24
Peak memory 204096 kb
Host smart-6c20fca7-3dd8-41f6-843f-3eb4015fc795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65448
4176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.654484176
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.3202486593
Short name T1014
Test name
Test status
Simulation time 8398324641 ps
CPU time 8.04 seconds
Started Mar 31 01:52:44 PM PDT 24
Finished Mar 31 01:52:52 PM PDT 24
Peak memory 204112 kb
Host smart-8977f5f4-64d5-46f8-be27-6f42c626a28a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32024
86593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3202486593
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.915768912
Short name T335
Test name
Test status
Simulation time 8373848882 ps
CPU time 8.69 seconds
Started Mar 31 01:52:43 PM PDT 24
Finished Mar 31 01:52:52 PM PDT 24
Peak memory 204152 kb
Host smart-4b0db798-03cd-4dc7-8e04-3b55b9128b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91576
8912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.915768912
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.129394240
Short name T384
Test name
Test status
Simulation time 8359375157 ps
CPU time 7.75 seconds
Started Mar 31 01:52:43 PM PDT 24
Finished Mar 31 01:52:51 PM PDT 24
Peak memory 204116 kb
Host smart-b494b91f-d9de-4c72-a127-16cdb88daf83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12939
4240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.129394240
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.772582056
Short name T180
Test name
Test status
Simulation time 8449137141 ps
CPU time 8.62 seconds
Started Mar 31 01:52:42 PM PDT 24
Finished Mar 31 01:52:51 PM PDT 24
Peak memory 204132 kb
Host smart-561363a7-8ca8-46b6-8b00-cf1b9fd0a34a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77258
2056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.772582056
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.3701310266
Short name T514
Test name
Test status
Simulation time 8388901327 ps
CPU time 9.75 seconds
Started Mar 31 01:52:42 PM PDT 24
Finished Mar 31 01:52:52 PM PDT 24
Peak memory 204028 kb
Host smart-4dd9238c-e081-443e-96b9-d275c6fe68b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37013
10266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.3701310266
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.in_iso.1767133942
Short name T143
Test name
Test status
Simulation time 8394264851 ps
CPU time 7.48 seconds
Started Mar 31 01:52:49 PM PDT 24
Finished Mar 31 01:52:57 PM PDT 24
Peak memory 204100 kb
Host smart-c19b521d-63d9-4c1e-94bb-e0ebb0d32166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17671
33942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.in_iso.1767133942
Directory /workspace/48.in_iso/latest

Test location /workspace/coverage/default/48.phy_config_usb_ref_disable.1079969909
Short name T947
Test name
Test status
Simulation time 8359842651 ps
CPU time 6.95 seconds
Started Mar 31 01:52:54 PM PDT 24
Finished Mar 31 01:53:01 PM PDT 24
Peak memory 204144 kb
Host smart-a7f60b58-0048-4bad-9890-a86360525aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10799
69909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.phy_config_usb_ref_disable.1079969909
Directory /workspace/48.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.3838061983
Short name T418
Test name
Test status
Simulation time 8372625436 ps
CPU time 7.45 seconds
Started Mar 31 01:52:45 PM PDT 24
Finished Mar 31 01:52:52 PM PDT 24
Peak memory 204140 kb
Host smart-2487d580-8931-4294-8f62-940652c1bdd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38380
61983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.3838061983
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_enable.1671156025
Short name T831
Test name
Test status
Simulation time 8369412208 ps
CPU time 7.75 seconds
Started Mar 31 01:52:45 PM PDT 24
Finished Mar 31 01:52:52 PM PDT 24
Peak memory 204084 kb
Host smart-786e837c-cb2d-4cab-8961-a0926c959dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16711
56025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.1671156025
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.2767649850
Short name T550
Test name
Test status
Simulation time 38721182 ps
CPU time 1.15 seconds
Started Mar 31 01:52:45 PM PDT 24
Finished Mar 31 01:52:46 PM PDT 24
Peak memory 204296 kb
Host smart-b74bb05e-d592-443f-a21a-a6d17e97ca3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27676
49850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.2767649850
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.1072728881
Short name T718
Test name
Test status
Simulation time 8364517836 ps
CPU time 7.31 seconds
Started Mar 31 01:52:49 PM PDT 24
Finished Mar 31 01:52:57 PM PDT 24
Peak memory 204108 kb
Host smart-c13c0dea-9da0-4550-8466-d0587524e096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10727
28881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1072728881
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.3032201672
Short name T743
Test name
Test status
Simulation time 8384583723 ps
CPU time 7.06 seconds
Started Mar 31 01:52:43 PM PDT 24
Finished Mar 31 01:52:50 PM PDT 24
Peak memory 204104 kb
Host smart-45d406f5-1077-405a-b1eb-db1a35dbf97c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30322
01672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.3032201672
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.2657733863
Short name T902
Test name
Test status
Simulation time 8409425598 ps
CPU time 7.98 seconds
Started Mar 31 01:52:43 PM PDT 24
Finished Mar 31 01:52:51 PM PDT 24
Peak memory 204108 kb
Host smart-5186ea1b-ce3b-4c25-a9b8-70df68d0c713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26577
33863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.2657733863
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2564433076
Short name T623
Test name
Test status
Simulation time 8367953359 ps
CPU time 9.23 seconds
Started Mar 31 01:52:44 PM PDT 24
Finished Mar 31 01:52:54 PM PDT 24
Peak memory 204152 kb
Host smart-75a0b8fd-596b-410d-bd81-f606b631edcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25644
33076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2564433076
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.2945859647
Short name T37
Test name
Test status
Simulation time 8377464618 ps
CPU time 7.52 seconds
Started Mar 31 01:52:42 PM PDT 24
Finished Mar 31 01:52:50 PM PDT 24
Peak memory 204076 kb
Host smart-18081863-619e-4c9a-83af-f01125f77ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29458
59647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.2945859647
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.1332076173
Short name T652
Test name
Test status
Simulation time 8392550831 ps
CPU time 8.41 seconds
Started Mar 31 01:52:45 PM PDT 24
Finished Mar 31 01:52:54 PM PDT 24
Peak memory 204164 kb
Host smart-c96d2122-db0c-4002-8364-4bf360c4b2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13320
76173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.1332076173
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1025618353
Short name T355
Test name
Test status
Simulation time 26281129 ps
CPU time 0.64 seconds
Started Mar 31 01:52:49 PM PDT 24
Finished Mar 31 01:52:50 PM PDT 24
Peak memory 204080 kb
Host smart-79bd3704-0544-4f40-90fe-9370212c56fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10256
18353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1025618353
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.2946753874
Short name T1012
Test name
Test status
Simulation time 18305864285 ps
CPU time 31.13 seconds
Started Mar 31 01:52:44 PM PDT 24
Finished Mar 31 01:53:15 PM PDT 24
Peak memory 204360 kb
Host smart-078191c7-25c5-4781-a508-1b97dd315f28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29467
53874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.2946753874
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.797825197
Short name T301
Test name
Test status
Simulation time 8404233387 ps
CPU time 8.5 seconds
Started Mar 31 01:52:46 PM PDT 24
Finished Mar 31 01:52:55 PM PDT 24
Peak memory 204036 kb
Host smart-2cb7fc70-b172-4d05-9efb-c39b083f686b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79782
5197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.797825197
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3295189460
Short name T662
Test name
Test status
Simulation time 8432427973 ps
CPU time 8.81 seconds
Started Mar 31 01:52:45 PM PDT 24
Finished Mar 31 01:52:54 PM PDT 24
Peak memory 204104 kb
Host smart-d1801b14-c724-4918-97eb-ae113516c499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32951
89460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3295189460
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.3410605715
Short name T741
Test name
Test status
Simulation time 8380606811 ps
CPU time 7.9 seconds
Started Mar 31 01:52:51 PM PDT 24
Finished Mar 31 01:52:59 PM PDT 24
Peak memory 204084 kb
Host smart-fb6f2ab0-578e-4b96-820f-b6e453c4efae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34106
05715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.3410605715
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.3700885863
Short name T578
Test name
Test status
Simulation time 8362564698 ps
CPU time 7.4 seconds
Started Mar 31 01:52:54 PM PDT 24
Finished Mar 31 01:53:01 PM PDT 24
Peak memory 204160 kb
Host smart-e5d421d4-fd42-4507-b57f-e38ba5b3a532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37008
85863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.3700885863
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.48848246
Short name T161
Test name
Test status
Simulation time 8463166419 ps
CPU time 8 seconds
Started Mar 31 01:52:46 PM PDT 24
Finished Mar 31 01:52:55 PM PDT 24
Peak memory 204072 kb
Host smart-8a35d959-7a8a-4420-8c80-0ef6896a421c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48848
246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.48848246
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.4099324371
Short name T511
Test name
Test status
Simulation time 8380440857 ps
CPU time 7.84 seconds
Started Mar 31 01:52:52 PM PDT 24
Finished Mar 31 01:53:00 PM PDT 24
Peak memory 204096 kb
Host smart-e81fa41c-bcee-4e36-ac69-a9465986b921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40993
24371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.4099324371
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.in_iso.718941616
Short name T427
Test name
Test status
Simulation time 8412156659 ps
CPU time 7.68 seconds
Started Mar 31 01:52:56 PM PDT 24
Finished Mar 31 01:53:04 PM PDT 24
Peak memory 204140 kb
Host smart-c76c1ffb-94f4-4ec5-add2-b570b1a942c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71894
1616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.in_iso.718941616
Directory /workspace/49.in_iso/latest

Test location /workspace/coverage/default/49.phy_config_usb_ref_disable.2801494467
Short name T889
Test name
Test status
Simulation time 8364687995 ps
CPU time 7.33 seconds
Started Mar 31 01:52:50 PM PDT 24
Finished Mar 31 01:52:58 PM PDT 24
Peak memory 204100 kb
Host smart-d561e934-3621-4932-8935-9d148c93569c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28014
94467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.phy_config_usb_ref_disable.2801494467
Directory /workspace/49.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3306179514
Short name T994
Test name
Test status
Simulation time 8370603518 ps
CPU time 7.61 seconds
Started Mar 31 01:52:54 PM PDT 24
Finished Mar 31 01:53:01 PM PDT 24
Peak memory 204112 kb
Host smart-2e28b7e4-2147-4335-aa72-213bd7e6c243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33061
79514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3306179514
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_enable.295563498
Short name T357
Test name
Test status
Simulation time 8371989588 ps
CPU time 7.32 seconds
Started Mar 31 01:52:50 PM PDT 24
Finished Mar 31 01:52:57 PM PDT 24
Peak memory 204124 kb
Host smart-1782fe7c-8bc1-439d-887c-7023c1285209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29556
3498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.295563498
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.2549451691
Short name T319
Test name
Test status
Simulation time 168700333 ps
CPU time 1.82 seconds
Started Mar 31 01:52:50 PM PDT 24
Finished Mar 31 01:52:52 PM PDT 24
Peak memory 204244 kb
Host smart-433aaa31-6276-4eb7-ab6c-bd3c4877cfda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25494
51691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.2549451691
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.720396492
Short name T193
Test name
Test status
Simulation time 8358895632 ps
CPU time 9.5 seconds
Started Mar 31 01:52:58 PM PDT 24
Finished Mar 31 01:53:09 PM PDT 24
Peak memory 204120 kb
Host smart-c7cd9b82-ce0c-40f9-9d86-4beb2097205f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72039
6492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.720396492
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.3801600881
Short name T1086
Test name
Test status
Simulation time 8387699701 ps
CPU time 8.4 seconds
Started Mar 31 01:52:53 PM PDT 24
Finished Mar 31 01:53:02 PM PDT 24
Peak memory 204148 kb
Host smart-2731b179-96b6-4d30-8c34-26c0cffd4599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38016
00881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.3801600881
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.921698912
Short name T403
Test name
Test status
Simulation time 8407018535 ps
CPU time 8.94 seconds
Started Mar 31 01:52:48 PM PDT 24
Finished Mar 31 01:52:58 PM PDT 24
Peak memory 204120 kb
Host smart-1086c14c-f629-4e59-b74f-522fbb4a78c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92169
8912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.921698912
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1900950966
Short name T305
Test name
Test status
Simulation time 8367384230 ps
CPU time 7.18 seconds
Started Mar 31 01:52:54 PM PDT 24
Finished Mar 31 01:53:01 PM PDT 24
Peak memory 204116 kb
Host smart-268d9cb5-4053-464d-ae44-8fa4aee81a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19009
50966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1900950966
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2497674715
Short name T561
Test name
Test status
Simulation time 8387770833 ps
CPU time 7.4 seconds
Started Mar 31 01:52:54 PM PDT 24
Finished Mar 31 01:53:01 PM PDT 24
Peak memory 204104 kb
Host smart-dea7929b-38fc-480e-a105-edf9585147c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24976
74715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2497674715
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1834086100
Short name T411
Test name
Test status
Simulation time 8383759984 ps
CPU time 7.96 seconds
Started Mar 31 01:52:51 PM PDT 24
Finished Mar 31 01:52:59 PM PDT 24
Peak memory 204084 kb
Host smart-34e79f84-c0c8-4391-befa-41d070e9fb11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18340
86100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1834086100
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.1386137936
Short name T577
Test name
Test status
Simulation time 8386033699 ps
CPU time 7.59 seconds
Started Mar 31 01:52:50 PM PDT 24
Finished Mar 31 01:52:58 PM PDT 24
Peak memory 204120 kb
Host smart-988efe6d-2484-41e6-84cd-baedfe93a128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13861
37936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.1386137936
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.2065918902
Short name T651
Test name
Test status
Simulation time 24737385 ps
CPU time 0.69 seconds
Started Mar 31 01:52:51 PM PDT 24
Finished Mar 31 01:52:52 PM PDT 24
Peak memory 204088 kb
Host smart-35932b90-8df2-437f-8b2a-2fd8586b319b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20659
18902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.2065918902
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.1475627954
Short name T199
Test name
Test status
Simulation time 28738702895 ps
CPU time 52.36 seconds
Started Mar 31 01:52:50 PM PDT 24
Finished Mar 31 01:53:42 PM PDT 24
Peak memory 204288 kb
Host smart-a7573365-db8f-433c-a889-00856f99d0f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14756
27954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.1475627954
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3035412202
Short name T689
Test name
Test status
Simulation time 8379316312 ps
CPU time 9.2 seconds
Started Mar 31 01:52:50 PM PDT 24
Finished Mar 31 01:52:59 PM PDT 24
Peak memory 204128 kb
Host smart-e53bce55-f7ec-44c5-9b18-24994eebfcf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30354
12202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3035412202
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.667652329
Short name T154
Test name
Test status
Simulation time 8419556051 ps
CPU time 7.06 seconds
Started Mar 31 01:52:51 PM PDT 24
Finished Mar 31 01:52:58 PM PDT 24
Peak memory 204132 kb
Host smart-322c2b3e-b1e4-4dbf-bc15-474e51c64c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66765
2329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.667652329
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.4287609087
Short name T318
Test name
Test status
Simulation time 8392460667 ps
CPU time 7.18 seconds
Started Mar 31 01:52:54 PM PDT 24
Finished Mar 31 01:53:01 PM PDT 24
Peak memory 204156 kb
Host smart-05862a56-a31a-4360-8cb1-a0894450e22f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42876
09087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.4287609087
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.2976351631
Short name T682
Test name
Test status
Simulation time 8363300527 ps
CPU time 7.31 seconds
Started Mar 31 01:52:48 PM PDT 24
Finished Mar 31 01:52:56 PM PDT 24
Peak memory 204152 kb
Host smart-e8c6c0ab-5c82-488d-b75f-8b407c17c80e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29763
51631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.2976351631
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.1788413911
Short name T565
Test name
Test status
Simulation time 8436910348 ps
CPU time 8.21 seconds
Started Mar 31 01:52:51 PM PDT 24
Finished Mar 31 01:52:59 PM PDT 24
Peak memory 204096 kb
Host smart-bf8bd4a7-876e-412c-9bee-fce22db3f9a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17884
13911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.1788413911
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.3391208338
Short name T681
Test name
Test status
Simulation time 8372871169 ps
CPU time 7.14 seconds
Started Mar 31 01:52:50 PM PDT 24
Finished Mar 31 01:52:57 PM PDT 24
Peak memory 204140 kb
Host smart-48d264bc-5e36-46fd-b2e1-6c7d1c8145ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33912
08338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.3391208338
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.in_iso.3112558209
Short name T145
Test name
Test status
Simulation time 8409303586 ps
CPU time 8.72 seconds
Started Mar 31 01:46:38 PM PDT 24
Finished Mar 31 01:46:47 PM PDT 24
Peak memory 204124 kb
Host smart-344a2c0b-e64c-4599-b3c3-4890569e4b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31125
58209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.in_iso.3112558209
Directory /workspace/5.in_iso/latest

Test location /workspace/coverage/default/5.phy_config_usb_ref_disable.2006812846
Short name T814
Test name
Test status
Simulation time 8363239930 ps
CPU time 7.31 seconds
Started Mar 31 01:46:39 PM PDT 24
Finished Mar 31 01:46:47 PM PDT 24
Peak memory 204096 kb
Host smart-85b7ddf4-9a55-4353-94cc-3afce2666d9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20068
12846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.phy_config_usb_ref_disable.2006812846
Directory /workspace/5.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.1629717640
Short name T735
Test name
Test status
Simulation time 8372634271 ps
CPU time 7.61 seconds
Started Mar 31 01:46:30 PM PDT 24
Finished Mar 31 01:46:38 PM PDT 24
Peak memory 203912 kb
Host smart-3e90505d-23fb-49ad-aa31-43375211d7cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16297
17640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1629717640
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_enable.1059988004
Short name T605
Test name
Test status
Simulation time 8370914364 ps
CPU time 7.19 seconds
Started Mar 31 01:46:23 PM PDT 24
Finished Mar 31 01:46:30 PM PDT 24
Peak memory 204100 kb
Host smart-c9404883-41e4-432f-a020-57ba30cc11a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10599
88004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.1059988004
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.3675310648
Short name T360
Test name
Test status
Simulation time 65462873 ps
CPU time 1.78 seconds
Started Mar 31 01:46:30 PM PDT 24
Finished Mar 31 01:46:32 PM PDT 24
Peak memory 204084 kb
Host smart-a2db0021-47ba-4a2d-b468-bd5f51914b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36753
10648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.3675310648
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.1437210642
Short name T50
Test name
Test status
Simulation time 8361486487 ps
CPU time 7.2 seconds
Started Mar 31 01:46:40 PM PDT 24
Finished Mar 31 01:46:47 PM PDT 24
Peak memory 204140 kb
Host smart-eb8cdb39-1a37-4c9c-a55d-4fbf267eef24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14372
10642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.1437210642
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.1940499601
Short name T744
Test name
Test status
Simulation time 8387644098 ps
CPU time 8.09 seconds
Started Mar 31 01:46:24 PM PDT 24
Finished Mar 31 01:46:32 PM PDT 24
Peak memory 204140 kb
Host smart-4ab559b9-410c-442f-9d4b-fcfca9cd68e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19404
99601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1940499601
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.401572935
Short name T570
Test name
Test status
Simulation time 8407725175 ps
CPU time 8.43 seconds
Started Mar 31 01:46:25 PM PDT 24
Finished Mar 31 01:46:34 PM PDT 24
Peak memory 204120 kb
Host smart-949c1df1-037d-42aa-9b7f-51022f8bffc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40157
2935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.401572935
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.2931598269
Short name T261
Test name
Test status
Simulation time 8367944753 ps
CPU time 8.14 seconds
Started Mar 31 01:46:25 PM PDT 24
Finished Mar 31 01:46:33 PM PDT 24
Peak memory 204136 kb
Host smart-ee7dd498-fb5f-45eb-a40c-7bb68461d31f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29315
98269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.2931598269
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1287553602
Short name T1031
Test name
Test status
Simulation time 8426932985 ps
CPU time 7.61 seconds
Started Mar 31 01:46:30 PM PDT 24
Finished Mar 31 01:46:37 PM PDT 24
Peak memory 204148 kb
Host smart-1756f6c4-769d-43ba-9283-96a022d30bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12875
53602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1287553602
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.3199786454
Short name T528
Test name
Test status
Simulation time 8389255272 ps
CPU time 7.45 seconds
Started Mar 31 01:46:30 PM PDT 24
Finished Mar 31 01:46:38 PM PDT 24
Peak memory 204144 kb
Host smart-4cbb65df-fb8c-45c7-b0c0-5b5092186a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31997
86454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.3199786454
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.2331775234
Short name T354
Test name
Test status
Simulation time 8370583709 ps
CPU time 6.98 seconds
Started Mar 31 01:46:30 PM PDT 24
Finished Mar 31 01:46:37 PM PDT 24
Peak memory 204136 kb
Host smart-7b8d6687-be38-4e7d-994b-9e1381fc9ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23317
75234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2331775234
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.2332445087
Short name T739
Test name
Test status
Simulation time 23879893 ps
CPU time 0.65 seconds
Started Mar 31 01:46:39 PM PDT 24
Finished Mar 31 01:46:40 PM PDT 24
Peak memory 204080 kb
Host smart-bd0edf14-8e17-4908-8171-a910dbc11f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23324
45087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.2332445087
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.3772518577
Short name T567
Test name
Test status
Simulation time 26058441237 ps
CPU time 46.83 seconds
Started Mar 31 01:46:29 PM PDT 24
Finished Mar 31 01:47:16 PM PDT 24
Peak memory 204232 kb
Host smart-a5eb341e-8c4f-49bb-8534-1f002021473f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37725
18577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.3772518577
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.598044920
Short name T1053
Test name
Test status
Simulation time 8378920213 ps
CPU time 7.68 seconds
Started Mar 31 01:46:29 PM PDT 24
Finished Mar 31 01:46:37 PM PDT 24
Peak memory 204152 kb
Host smart-622f05b6-5db7-4d64-8f52-57ae4296c737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59804
4920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.598044920
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.2435015803
Short name T1045
Test name
Test status
Simulation time 8415196797 ps
CPU time 7.18 seconds
Started Mar 31 01:46:29 PM PDT 24
Finished Mar 31 01:46:37 PM PDT 24
Peak memory 204104 kb
Host smart-d8f47d8a-279c-4c17-a101-29969cdec526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24350
15803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.2435015803
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.1457948929
Short name T855
Test name
Test status
Simulation time 8402184080 ps
CPU time 7.38 seconds
Started Mar 31 01:46:29 PM PDT 24
Finished Mar 31 01:46:37 PM PDT 24
Peak memory 204108 kb
Host smart-57b12383-6cfc-418c-867e-392d975638b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14579
48929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.1457948929
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3433382431
Short name T922
Test name
Test status
Simulation time 8359263674 ps
CPU time 9.56 seconds
Started Mar 31 01:46:38 PM PDT 24
Finished Mar 31 01:46:48 PM PDT 24
Peak memory 204136 kb
Host smart-452656d5-ccc6-45fb-8669-e560e59d8ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34333
82431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3433382431
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1510674645
Short name T1071
Test name
Test status
Simulation time 8449288297 ps
CPU time 8.22 seconds
Started Mar 31 01:46:25 PM PDT 24
Finished Mar 31 01:46:33 PM PDT 24
Peak memory 204100 kb
Host smart-6ac7bd44-fd67-4e10-88fa-2ddb6db2decd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15106
74645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1510674645
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.1767658426
Short name T323
Test name
Test status
Simulation time 8385425169 ps
CPU time 8.02 seconds
Started Mar 31 01:46:37 PM PDT 24
Finished Mar 31 01:46:46 PM PDT 24
Peak memory 204160 kb
Host smart-92e669a3-ffa6-4ae0-a4fe-31d50cda64fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17676
58426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.1767658426
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.in_iso.1022691763
Short name T945
Test name
Test status
Simulation time 8446878114 ps
CPU time 7.19 seconds
Started Mar 31 01:46:49 PM PDT 24
Finished Mar 31 01:46:57 PM PDT 24
Peak memory 204144 kb
Host smart-9f119e0e-1770-4fff-8c80-0c17a15432b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10226
91763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.in_iso.1022691763
Directory /workspace/6.in_iso/latest

Test location /workspace/coverage/default/6.phy_config_usb_ref_disable.2222861106
Short name T876
Test name
Test status
Simulation time 8364657313 ps
CPU time 7.26 seconds
Started Mar 31 01:46:50 PM PDT 24
Finished Mar 31 01:46:58 PM PDT 24
Peak memory 204104 kb
Host smart-60d5efa9-3631-48e3-853c-04f7dcf93437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22228
61106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.phy_config_usb_ref_disable.2222861106
Directory /workspace/6.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2821896491
Short name T471
Test name
Test status
Simulation time 8367714110 ps
CPU time 9.13 seconds
Started Mar 31 01:46:41 PM PDT 24
Finished Mar 31 01:46:50 PM PDT 24
Peak memory 204112 kb
Host smart-596d267c-cc1e-4c6a-9e66-fa1bc91e9ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28218
96491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2821896491
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_enable.1797369771
Short name T1015
Test name
Test status
Simulation time 8368239204 ps
CPU time 8.87 seconds
Started Mar 31 01:46:43 PM PDT 24
Finished Mar 31 01:46:52 PM PDT 24
Peak memory 204132 kb
Host smart-ebd220f1-5842-4dbd-8548-44a9b3cb7883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17973
69771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.1797369771
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.3285500650
Short name T52
Test name
Test status
Simulation time 77294030 ps
CPU time 2.03 seconds
Started Mar 31 01:46:42 PM PDT 24
Finished Mar 31 01:46:44 PM PDT 24
Peak memory 204312 kb
Host smart-a1232e86-ff33-44bd-81ca-b2d5d6fa6580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32855
00650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.3285500650
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.4143906124
Short name T196
Test name
Test status
Simulation time 8356731699 ps
CPU time 8.01 seconds
Started Mar 31 01:46:48 PM PDT 24
Finished Mar 31 01:46:56 PM PDT 24
Peak memory 204112 kb
Host smart-23483e78-e8a1-40b6-b6fc-5dd3eb9b4106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41439
06124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.4143906124
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2963762747
Short name T716
Test name
Test status
Simulation time 8397959155 ps
CPU time 7.38 seconds
Started Mar 31 01:46:46 PM PDT 24
Finished Mar 31 01:46:54 PM PDT 24
Peak memory 204088 kb
Host smart-c4db41e1-f7c9-4853-ac27-1e6ebee23e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29637
62747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2963762747
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.2057106966
Short name T579
Test name
Test status
Simulation time 8411288789 ps
CPU time 7.46 seconds
Started Mar 31 01:46:42 PM PDT 24
Finished Mar 31 01:46:49 PM PDT 24
Peak memory 204176 kb
Host smart-4f8815a6-186e-471a-bad7-468ba92648ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20571
06966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.2057106966
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.1507863599
Short name T709
Test name
Test status
Simulation time 8359991545 ps
CPU time 7.22 seconds
Started Mar 31 01:46:43 PM PDT 24
Finished Mar 31 01:46:51 PM PDT 24
Peak memory 204100 kb
Host smart-474c8375-a42e-4c5b-9e50-0961f123c494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15078
63599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.1507863599
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3568626051
Short name T845
Test name
Test status
Simulation time 8434950636 ps
CPU time 9.14 seconds
Started Mar 31 01:46:43 PM PDT 24
Finished Mar 31 01:46:52 PM PDT 24
Peak memory 204132 kb
Host smart-12063381-158d-4616-af73-76506208ad64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35686
26051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3568626051
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.1418598952
Short name T1073
Test name
Test status
Simulation time 8389227507 ps
CPU time 7.53 seconds
Started Mar 31 01:46:42 PM PDT 24
Finished Mar 31 01:46:50 PM PDT 24
Peak memory 204096 kb
Host smart-7e4080cc-6cf1-4d28-86d4-479e552ba319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14185
98952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.1418598952
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.3470966730
Short name T725
Test name
Test status
Simulation time 8383591428 ps
CPU time 7.77 seconds
Started Mar 31 01:46:43 PM PDT 24
Finished Mar 31 01:46:51 PM PDT 24
Peak memory 204152 kb
Host smart-55e251f0-8235-448e-8eff-c187ed989361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34709
66730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.3470966730
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.1324301575
Short name T476
Test name
Test status
Simulation time 32411243 ps
CPU time 0.63 seconds
Started Mar 31 01:46:49 PM PDT 24
Finished Mar 31 01:46:50 PM PDT 24
Peak memory 204088 kb
Host smart-b261be00-e22e-47a6-bda9-a5cdf1c2d54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13243
01575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.1324301575
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.2140821776
Short name T544
Test name
Test status
Simulation time 27410920925 ps
CPU time 51.65 seconds
Started Mar 31 01:46:46 PM PDT 24
Finished Mar 31 01:47:39 PM PDT 24
Peak memory 204360 kb
Host smart-8c9383bc-dd43-4857-96dc-5cf64f2fea0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21408
21776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.2140821776
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.627274020
Short name T21
Test name
Test status
Simulation time 8372321608 ps
CPU time 7.34 seconds
Started Mar 31 01:46:43 PM PDT 24
Finished Mar 31 01:46:51 PM PDT 24
Peak memory 204124 kb
Host smart-ac626073-2efc-4b5d-90ad-e6d68c5227f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62727
4020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.627274020
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.1389140696
Short name T146
Test name
Test status
Simulation time 8423823283 ps
CPU time 7.19 seconds
Started Mar 31 01:46:45 PM PDT 24
Finished Mar 31 01:46:53 PM PDT 24
Peak memory 203872 kb
Host smart-6969d202-7ad1-4ec2-a918-32170edacaa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13891
40696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1389140696
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.2634113873
Short name T499
Test name
Test status
Simulation time 8361765195 ps
CPU time 7.19 seconds
Started Mar 31 01:46:46 PM PDT 24
Finished Mar 31 01:46:53 PM PDT 24
Peak memory 204100 kb
Host smart-c8e3f1ae-549a-4c57-8f51-ba5716a5560c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26341
13873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.2634113873
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.3171696464
Short name T491
Test name
Test status
Simulation time 8356787222 ps
CPU time 7.46 seconds
Started Mar 31 01:46:43 PM PDT 24
Finished Mar 31 01:46:51 PM PDT 24
Peak memory 204148 kb
Host smart-efea7267-4887-4a0b-a6eb-4f07f505ae9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31716
96464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.3171696464
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.3863766441
Short name T165
Test name
Test status
Simulation time 8412029353 ps
CPU time 7.78 seconds
Started Mar 31 01:46:36 PM PDT 24
Finished Mar 31 01:46:44 PM PDT 24
Peak memory 204144 kb
Host smart-e593531a-515c-4d60-959e-cf49253e5b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38637
66441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3863766441
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.3392017738
Short name T803
Test name
Test status
Simulation time 8364202179 ps
CPU time 7.34 seconds
Started Mar 31 01:46:45 PM PDT 24
Finished Mar 31 01:46:53 PM PDT 24
Peak memory 203868 kb
Host smart-6ce7620d-593e-48af-9c46-82b4c7d1505e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33920
17738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.3392017738
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.in_iso.3153144689
Short name T1065
Test name
Test status
Simulation time 8386696348 ps
CPU time 7.05 seconds
Started Mar 31 01:47:01 PM PDT 24
Finished Mar 31 01:47:08 PM PDT 24
Peak memory 204132 kb
Host smart-d412d664-ddef-4904-8b08-5e8974984060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31531
44689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.in_iso.3153144689
Directory /workspace/7.in_iso/latest

Test location /workspace/coverage/default/7.phy_config_usb_ref_disable.872613863
Short name T498
Test name
Test status
Simulation time 8365226874 ps
CPU time 8 seconds
Started Mar 31 01:47:00 PM PDT 24
Finished Mar 31 01:47:08 PM PDT 24
Peak memory 204112 kb
Host smart-7b5eb1b0-2a0e-4c62-a4cc-dbfe2425ed8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87261
3863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.phy_config_usb_ref_disable.872613863
Directory /workspace/7.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.631984330
Short name T703
Test name
Test status
Simulation time 8372698835 ps
CPU time 7.62 seconds
Started Mar 31 01:46:49 PM PDT 24
Finished Mar 31 01:46:57 PM PDT 24
Peak memory 204064 kb
Host smart-3d6290e7-a518-4db6-9cf6-f398e0455acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63198
4330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.631984330
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_enable.1266223316
Short name T935
Test name
Test status
Simulation time 8372110409 ps
CPU time 7.03 seconds
Started Mar 31 01:46:50 PM PDT 24
Finished Mar 31 01:46:57 PM PDT 24
Peak memory 204064 kb
Host smart-dfb13e5f-c45e-46b9-9c3c-ff116cd7e74c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12662
23316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.1266223316
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.3441513396
Short name T437
Test name
Test status
Simulation time 151259234 ps
CPU time 1.75 seconds
Started Mar 31 01:46:56 PM PDT 24
Finished Mar 31 01:46:58 PM PDT 24
Peak memory 204312 kb
Host smart-54af2596-656a-4073-b9d1-d5e284c10fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34415
13396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.3441513396
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.2734308112
Short name T192
Test name
Test status
Simulation time 8354416133 ps
CPU time 7.41 seconds
Started Mar 31 01:47:02 PM PDT 24
Finished Mar 31 01:47:10 PM PDT 24
Peak memory 204092 kb
Host smart-bf185084-7a37-4c01-8c3f-0394e6662c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27343
08112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.2734308112
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3124624897
Short name T569
Test name
Test status
Simulation time 8402546450 ps
CPU time 7.69 seconds
Started Mar 31 01:46:55 PM PDT 24
Finished Mar 31 01:47:03 PM PDT 24
Peak memory 204116 kb
Host smart-4d582db2-c72b-45fd-b725-7a28fc029569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31246
24897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3124624897
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.1782666276
Short name T479
Test name
Test status
Simulation time 8411042719 ps
CPU time 7.91 seconds
Started Mar 31 01:46:54 PM PDT 24
Finished Mar 31 01:47:02 PM PDT 24
Peak memory 204144 kb
Host smart-1e5f7691-9a96-4075-a5e1-5cfbb71bcd03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17826
66276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.1782666276
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.664042614
Short name T227
Test name
Test status
Simulation time 8362935291 ps
CPU time 7.05 seconds
Started Mar 31 01:46:53 PM PDT 24
Finished Mar 31 01:47:01 PM PDT 24
Peak memory 204104 kb
Host smart-99269b02-0d27-42f0-8432-433816f72000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66404
2614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.664042614
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.3343807494
Short name T16
Test name
Test status
Simulation time 8388622338 ps
CPU time 8.17 seconds
Started Mar 31 01:46:55 PM PDT 24
Finished Mar 31 01:47:03 PM PDT 24
Peak memory 203912 kb
Host smart-d0778526-1ce3-413d-b5ac-5c2e5981284f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33438
07494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.3343807494
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.3243347491
Short name T1057
Test name
Test status
Simulation time 8381675647 ps
CPU time 8.04 seconds
Started Mar 31 01:46:54 PM PDT 24
Finished Mar 31 01:47:02 PM PDT 24
Peak memory 204100 kb
Host smart-78048006-ec83-4ee1-a4c5-7b97d4ddc94b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32433
47491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.3243347491
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.1591893122
Short name T691
Test name
Test status
Simulation time 23956689 ps
CPU time 0.64 seconds
Started Mar 31 01:47:02 PM PDT 24
Finished Mar 31 01:47:03 PM PDT 24
Peak memory 204036 kb
Host smart-43cf2263-615c-49cb-b13e-f6a52c010df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15918
93122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.1591893122
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.191847134
Short name T851
Test name
Test status
Simulation time 27167961798 ps
CPU time 50.07 seconds
Started Mar 31 01:46:54 PM PDT 24
Finished Mar 31 01:47:44 PM PDT 24
Peak memory 204396 kb
Host smart-591a290e-c5b1-4533-a8c8-9a03e78e7118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19184
7134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.191847134
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.3775721429
Short name T717
Test name
Test status
Simulation time 8390053424 ps
CPU time 9.72 seconds
Started Mar 31 01:46:56 PM PDT 24
Finished Mar 31 01:47:05 PM PDT 24
Peak memory 204148 kb
Host smart-d15f6055-2ecd-4e65-9723-f46b7296c193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37757
21429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.3775721429
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.2240421416
Short name T648
Test name
Test status
Simulation time 8435019256 ps
CPU time 7.64 seconds
Started Mar 31 01:46:54 PM PDT 24
Finished Mar 31 01:47:02 PM PDT 24
Peak memory 204132 kb
Host smart-813e0630-244e-45d8-94c5-b331b085a629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22404
21416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.2240421416
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.4194011470
Short name T948
Test name
Test status
Simulation time 8364782880 ps
CPU time 7.36 seconds
Started Mar 31 01:46:56 PM PDT 24
Finished Mar 31 01:47:03 PM PDT 24
Peak memory 204100 kb
Host smart-5ac077b9-2e1c-4b5d-8266-5d5748ba0d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41940
11470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.4194011470
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.508630572
Short name T520
Test name
Test status
Simulation time 8360709755 ps
CPU time 8.06 seconds
Started Mar 31 01:46:55 PM PDT 24
Finished Mar 31 01:47:03 PM PDT 24
Peak memory 204128 kb
Host smart-33542883-1897-42db-b23d-59d2160bf44b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50863
0572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.508630572
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.3428106102
Short name T906
Test name
Test status
Simulation time 8425012390 ps
CPU time 7.21 seconds
Started Mar 31 01:46:49 PM PDT 24
Finished Mar 31 01:46:57 PM PDT 24
Peak memory 203908 kb
Host smart-27f52a17-4782-4dd9-9f30-c761b06048e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34281
06102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.3428106102
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.2828581887
Short name T1009
Test name
Test status
Simulation time 8410665723 ps
CPU time 7.03 seconds
Started Mar 31 01:46:55 PM PDT 24
Finished Mar 31 01:47:03 PM PDT 24
Peak memory 204124 kb
Host smart-81a94ba5-558c-4a92-a22b-150d955bb127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28285
81887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.2828581887
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.in_iso.3365755957
Short name T331
Test name
Test status
Simulation time 8416753962 ps
CPU time 7.75 seconds
Started Mar 31 01:47:13 PM PDT 24
Finished Mar 31 01:47:21 PM PDT 24
Peak memory 204164 kb
Host smart-f1fa279a-179a-408b-87a7-7aafc5a1587d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33657
55957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.in_iso.3365755957
Directory /workspace/8.in_iso/latest

Test location /workspace/coverage/default/8.phy_config_usb_ref_disable.1876991590
Short name T407
Test name
Test status
Simulation time 8364916784 ps
CPU time 7.85 seconds
Started Mar 31 01:47:15 PM PDT 24
Finished Mar 31 01:47:23 PM PDT 24
Peak memory 204152 kb
Host smart-4db013fe-14f2-4774-8575-df29b0db7b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18769
91590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.phy_config_usb_ref_disable.1876991590
Directory /workspace/8.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.593420266
Short name T515
Test name
Test status
Simulation time 8374150529 ps
CPU time 9.37 seconds
Started Mar 31 01:47:07 PM PDT 24
Finished Mar 31 01:47:17 PM PDT 24
Peak memory 204136 kb
Host smart-d9100b55-9739-4c01-b16d-06889ef6b884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59342
0266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.593420266
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_enable.1436255496
Short name T486
Test name
Test status
Simulation time 8371526838 ps
CPU time 9.11 seconds
Started Mar 31 01:47:09 PM PDT 24
Finished Mar 31 01:47:18 PM PDT 24
Peak memory 204072 kb
Host smart-807017e5-d86d-4f59-ad64-99502525e8e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14362
55496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.1436255496
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.4075397920
Short name T938
Test name
Test status
Simulation time 128065824 ps
CPU time 1.5 seconds
Started Mar 31 01:47:09 PM PDT 24
Finished Mar 31 01:47:10 PM PDT 24
Peak memory 204264 kb
Host smart-88eca242-45e9-4bed-85ca-5a217323ffe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40753
97920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.4075397920
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.561538373
Short name T834
Test name
Test status
Simulation time 8361481874 ps
CPU time 7.13 seconds
Started Mar 31 01:47:15 PM PDT 24
Finished Mar 31 01:47:22 PM PDT 24
Peak memory 204144 kb
Host smart-117f13d2-437f-4578-a8ae-983801bd6674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56153
8373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.561538373
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3378910868
Short name T955
Test name
Test status
Simulation time 8371695133 ps
CPU time 7.93 seconds
Started Mar 31 01:47:09 PM PDT 24
Finished Mar 31 01:47:17 PM PDT 24
Peak memory 204104 kb
Host smart-25b5fee8-174d-4ea8-ac96-eb206a46aedf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33789
10868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3378910868
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.4079355799
Short name T637
Test name
Test status
Simulation time 8411753562 ps
CPU time 8.44 seconds
Started Mar 31 01:47:10 PM PDT 24
Finished Mar 31 01:47:19 PM PDT 24
Peak memory 204108 kb
Host smart-7ecb4568-a130-4cbe-ab37-ce94d8dfab7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40793
55799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.4079355799
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.2867460999
Short name T1004
Test name
Test status
Simulation time 8364974691 ps
CPU time 7.7 seconds
Started Mar 31 01:47:06 PM PDT 24
Finished Mar 31 01:47:14 PM PDT 24
Peak memory 204100 kb
Host smart-fed5b832-79e4-4d21-8e7c-efe60d8a6db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28674
60999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.2867460999
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.639372290
Short name T111
Test name
Test status
Simulation time 8454412833 ps
CPU time 7.25 seconds
Started Mar 31 01:47:06 PM PDT 24
Finished Mar 31 01:47:13 PM PDT 24
Peak memory 204128 kb
Host smart-ad0e1ec5-554f-4516-9757-de6f6633ff15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63937
2290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.639372290
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.2989196245
Short name T611
Test name
Test status
Simulation time 8397888951 ps
CPU time 7.03 seconds
Started Mar 31 01:47:06 PM PDT 24
Finished Mar 31 01:47:13 PM PDT 24
Peak memory 204104 kb
Host smart-881875fe-f868-4b41-82b6-3e41f1786e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29891
96245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.2989196245
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.1057221352
Short name T1016
Test name
Test status
Simulation time 8401093455 ps
CPU time 7.09 seconds
Started Mar 31 01:47:07 PM PDT 24
Finished Mar 31 01:47:14 PM PDT 24
Peak memory 204180 kb
Host smart-c0886708-05b3-45d3-90f1-b8a71413e9af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10572
21352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.1057221352
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.543357643
Short name T328
Test name
Test status
Simulation time 21808751 ps
CPU time 0.62 seconds
Started Mar 31 01:47:14 PM PDT 24
Finished Mar 31 01:47:15 PM PDT 24
Peak memory 204100 kb
Host smart-914668f1-8541-447c-a38f-7cdd942baf91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54335
7643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.543357643
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.509583994
Short name T246
Test name
Test status
Simulation time 17250769146 ps
CPU time 27.78 seconds
Started Mar 31 01:47:12 PM PDT 24
Finished Mar 31 01:47:41 PM PDT 24
Peak memory 204340 kb
Host smart-e13e6781-bf4e-462e-807b-d6572dcb708c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50958
3994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.509583994
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.4103056053
Short name T919
Test name
Test status
Simulation time 8408765697 ps
CPU time 8.35 seconds
Started Mar 31 01:47:13 PM PDT 24
Finished Mar 31 01:47:21 PM PDT 24
Peak memory 204116 kb
Host smart-b8ced33a-093f-44a9-b652-fb7c9a9bce59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41030
56053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.4103056053
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.2504262836
Short name T921
Test name
Test status
Simulation time 8371649075 ps
CPU time 9.06 seconds
Started Mar 31 01:47:13 PM PDT 24
Finished Mar 31 01:47:22 PM PDT 24
Peak memory 204140 kb
Host smart-26e7720d-c257-4d1a-9283-68726378f232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25042
62836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.2504262836
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.3667822452
Short name T375
Test name
Test status
Simulation time 8392123325 ps
CPU time 7.2 seconds
Started Mar 31 01:47:12 PM PDT 24
Finished Mar 31 01:47:20 PM PDT 24
Peak memory 204108 kb
Host smart-622923ea-a821-4817-9616-b56074f32613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36678
22452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.3667822452
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2395826634
Short name T799
Test name
Test status
Simulation time 8358221632 ps
CPU time 7.53 seconds
Started Mar 31 01:47:12 PM PDT 24
Finished Mar 31 01:47:20 PM PDT 24
Peak memory 204148 kb
Host smart-d887d1d3-1d66-4024-8bbf-4bf8e71729db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23958
26634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2395826634
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.2592369955
Short name T164
Test name
Test status
Simulation time 8475685711 ps
CPU time 7.23 seconds
Started Mar 31 01:47:09 PM PDT 24
Finished Mar 31 01:47:17 PM PDT 24
Peak memory 204096 kb
Host smart-a5167f3b-a0cb-4538-af1d-43bf5c959914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25923
69955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.2592369955
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.1536223581
Short name T990
Test name
Test status
Simulation time 8378965264 ps
CPU time 8.3 seconds
Started Mar 31 01:47:13 PM PDT 24
Finished Mar 31 01:47:21 PM PDT 24
Peak memory 204104 kb
Host smart-1de1a571-40bd-47eb-a44e-57c3e2971e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15362
23581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.1536223581
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.in_iso.3636640656
Short name T17
Test name
Test status
Simulation time 8391210229 ps
CPU time 7.64 seconds
Started Mar 31 01:47:24 PM PDT 24
Finished Mar 31 01:47:32 PM PDT 24
Peak memory 204200 kb
Host smart-75bfcd88-0c1d-4a6d-9867-8969ae465710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36366
40656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.in_iso.3636640656
Directory /workspace/9.in_iso/latest

Test location /workspace/coverage/default/9.phy_config_usb_ref_disable.445171023
Short name T9
Test name
Test status
Simulation time 8359881042 ps
CPU time 9.65 seconds
Started Mar 31 01:47:26 PM PDT 24
Finished Mar 31 01:47:36 PM PDT 24
Peak memory 204132 kb
Host smart-d2109573-45ba-4219-a538-5aa56493d4cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44517
1023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.phy_config_usb_ref_disable.445171023
Directory /workspace/9.phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.3289723729
Short name T978
Test name
Test status
Simulation time 8370189734 ps
CPU time 9.69 seconds
Started Mar 31 01:47:19 PM PDT 24
Finished Mar 31 01:47:29 PM PDT 24
Peak memory 204136 kb
Host smart-748326c8-4308-4006-8418-20d5c3bbeabe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32897
23729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.3289723729
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_enable.576995136
Short name T920
Test name
Test status
Simulation time 8365719807 ps
CPU time 7.27 seconds
Started Mar 31 01:47:17 PM PDT 24
Finished Mar 31 01:47:25 PM PDT 24
Peak memory 204100 kb
Host smart-f9091fca-6780-4fd6-925f-6583108b2fc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57699
5136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.576995136
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1312094234
Short name T781
Test name
Test status
Simulation time 289312870 ps
CPU time 2.18 seconds
Started Mar 31 01:47:19 PM PDT 24
Finished Mar 31 01:47:22 PM PDT 24
Peak memory 204260 kb
Host smart-e6b0cc95-f85c-42e1-b33d-c33462f494e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13120
94234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1312094234
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.3371701366
Short name T198
Test name
Test status
Simulation time 8357026955 ps
CPU time 9.04 seconds
Started Mar 31 01:47:30 PM PDT 24
Finished Mar 31 01:47:39 PM PDT 24
Peak memory 204144 kb
Host smart-58afe79d-3cad-497d-af10-67601d7fbb99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33717
01366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.3371701366
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.1608805128
Short name T621
Test name
Test status
Simulation time 8443546470 ps
CPU time 9.62 seconds
Started Mar 31 01:47:30 PM PDT 24
Finished Mar 31 01:47:40 PM PDT 24
Peak memory 204144 kb
Host smart-54402248-ad9a-4e10-919f-c799f50ce441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16088
05128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.1608805128
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.598557963
Short name T336
Test name
Test status
Simulation time 8408256784 ps
CPU time 8.02 seconds
Started Mar 31 01:47:24 PM PDT 24
Finished Mar 31 01:47:32 PM PDT 24
Peak memory 204104 kb
Host smart-1e74ef7d-f719-412c-a520-027e0aafccb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59855
7963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.598557963
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.734550310
Short name T986
Test name
Test status
Simulation time 8367716000 ps
CPU time 8.81 seconds
Started Mar 31 01:47:26 PM PDT 24
Finished Mar 31 01:47:34 PM PDT 24
Peak memory 204116 kb
Host smart-54b94828-8d53-460e-b8e9-bf8e205d6561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73455
0310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.734550310
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.131679218
Short name T131
Test name
Test status
Simulation time 8422378682 ps
CPU time 7.78 seconds
Started Mar 31 01:47:25 PM PDT 24
Finished Mar 31 01:47:33 PM PDT 24
Peak memory 204120 kb
Host smart-356984c4-888d-4269-8cc4-9175edb3ebd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13167
9218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.131679218
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.4038956992
Short name T339
Test name
Test status
Simulation time 8400040417 ps
CPU time 7.26 seconds
Started Mar 31 01:47:24 PM PDT 24
Finished Mar 31 01:47:32 PM PDT 24
Peak memory 204140 kb
Host smart-873e0796-7830-47aa-8f58-7d9c3ebd032d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40389
56992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.4038956992
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.3941394662
Short name T598
Test name
Test status
Simulation time 8379269195 ps
CPU time 7.25 seconds
Started Mar 31 01:47:25 PM PDT 24
Finished Mar 31 01:47:32 PM PDT 24
Peak memory 204156 kb
Host smart-33d1a5c6-b98e-4eef-a5d6-3603fc5ce439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39413
94662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.3941394662
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.2663712779
Short name T43
Test name
Test status
Simulation time 26479352 ps
CPU time 0.61 seconds
Started Mar 31 01:47:26 PM PDT 24
Finished Mar 31 01:47:26 PM PDT 24
Peak memory 204100 kb
Host smart-f46fc900-5616-4ce3-88e8-24bb375c3288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26637
12779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.2663712779
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.3934033541
Short name T1027
Test name
Test status
Simulation time 20912607216 ps
CPU time 38.4 seconds
Started Mar 31 01:47:26 PM PDT 24
Finished Mar 31 01:48:04 PM PDT 24
Peak memory 204412 kb
Host smart-8dccfa63-005c-4d30-86b9-a47f219a74e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39340
33541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.3934033541
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.552007387
Short name T1054
Test name
Test status
Simulation time 8375177052 ps
CPU time 7.29 seconds
Started Mar 31 01:47:24 PM PDT 24
Finished Mar 31 01:47:31 PM PDT 24
Peak memory 204120 kb
Host smart-dc384cea-73a1-4b7d-93c0-e105bc2f7d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55200
7387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.552007387
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.858733118
Short name T770
Test name
Test status
Simulation time 8406711145 ps
CPU time 7.31 seconds
Started Mar 31 01:47:30 PM PDT 24
Finished Mar 31 01:47:37 PM PDT 24
Peak memory 204144 kb
Host smart-1200541a-e2d6-485e-876d-c03ff17d9f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85873
3118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.858733118
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.3265585045
Short name T937
Test name
Test status
Simulation time 8392340698 ps
CPU time 7.4 seconds
Started Mar 31 01:47:27 PM PDT 24
Finished Mar 31 01:47:34 PM PDT 24
Peak memory 204100 kb
Host smart-fea24665-c9c9-4a8d-8a8a-0af24bfd5583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32655
85045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.3265585045
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.732550466
Short name T800
Test name
Test status
Simulation time 8361969708 ps
CPU time 8.38 seconds
Started Mar 31 01:47:24 PM PDT 24
Finished Mar 31 01:47:33 PM PDT 24
Peak memory 204132 kb
Host smart-a08d3a72-3e33-439d-b50c-9f5d8fac2d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73255
0466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.732550466
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.2145237885
Short name T48
Test name
Test status
Simulation time 8456372386 ps
CPU time 7.35 seconds
Started Mar 31 01:47:19 PM PDT 24
Finished Mar 31 01:47:27 PM PDT 24
Peak memory 204124 kb
Host smart-97832b07-df35-4dfa-878a-739f6e90d519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21452
37885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2145237885
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.3256055787
Short name T658
Test name
Test status
Simulation time 8401126962 ps
CPU time 8.89 seconds
Started Mar 31 01:47:24 PM PDT 24
Finished Mar 31 01:47:33 PM PDT 24
Peak memory 204132 kb
Host smart-6521ebba-b7a7-4d96-addc-890491636659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32560
55787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.3256055787
Directory /workspace/9.usbdev_stall_priority_over_nak/latest
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