Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	115558	1		T1	2		T2	3		T3	3
all_values[1]	115558	1		T1	2		T2	3		T3	3
all_values[2]	115558	1		T1	2		T2	3		T3	3
all_values[3]	115558	1		T1	2		T2	3		T3	3
all_values[4]	115558	1		T1	2		T2	3		T3	3
all_values[5]	115558	1		T1	2		T2	3		T3	3
all_values[6]	115558	1		T1	2		T2	3		T3	3
all_values[7]	115558	1		T1	2		T2	3		T3	3
all_values[8]	115558	1		T1	2		T2	3		T3	3
all_values[9]	115558	1		T1	2		T2	3		T3	3
all_values[10]	115558	1		T1	2		T2	3		T3	3
all_values[11]	115558	1		T1	2		T2	3		T3	3
all_values[12]	115558	1		T1	2		T2	3		T3	3
all_values[13]	115558	1		T1	2		T2	3		T3	3
all_values[14]	115558	1		T1	2		T2	3		T3	3
all_values[15]	115558	1		T1	2		T2	3		T3	3
all_values[16]	115558	1		T1	2		T2	3		T3	3
all_values[17]	115558	1		T1	2		T2	3		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2075986	1		T1	36		T2	54		T3	51
auto[1]	4058	1		T3	3		T19	3		T15	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2074889	1		T1	36		T2	54		T3	54
auto[1]	5155	1		T63	128		T66	76		T64	132

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	114542	1		T1	2		T2	3		T3	3
all_values[0]	auto[0]	auto[1]	162	1		T63	6		T66	5		T64	6
all_values[0]	auto[1]	auto[0]	728	1		T19	3		T15	3		T36	3
all_values[0]	auto[1]	auto[1]	126	1		T63	2		T64	1		T68	2
all_values[1]	auto[0]	auto[0]	114942	1		T1	2		T2	3		T17	2
all_values[1]	auto[0]	auto[1]	150	1		T63	1		T66	4		T64	5
all_values[1]	auto[1]	auto[0]	332	1		T3	3		T37	3		T39	3
all_values[1]	auto[1]	auto[1]	134	1		T63	6		T66	1		T64	3
all_values[2]	auto[0]	auto[0]	115246	1		T1	2		T2	3		T3	3
all_values[2]	auto[0]	auto[1]	151	1		T63	2		T64	2		T65	1
all_values[2]	auto[1]	auto[0]	23	1		T66	2		T64	3		T253	1
all_values[2]	auto[1]	auto[1]	138	1		T63	6		T64	3		T65	3
all_values[3]	auto[0]	auto[0]	115247	1		T1	2		T2	3		T3	3
all_values[3]	auto[0]	auto[1]	133	1		T63	5		T66	3		T64	4
all_values[3]	auto[1]	auto[0]	32	1		T66	1		T65	1		T262	1
all_values[3]	auto[1]	auto[1]	146	1		T63	3		T66	1		T64	3
all_values[4]	auto[0]	auto[0]	115244	1		T1	2		T2	3		T3	3
all_values[4]	auto[0]	auto[1]	135	1		T63	6		T66	2		T64	5
all_values[4]	auto[1]	auto[0]	31	1		T67	2		T262	1		T252	2
all_values[4]	auto[1]	auto[1]	148	1		T63	2		T66	3		T64	3
all_values[5]	auto[0]	auto[0]	115239	1		T1	2		T2	3		T3	3
all_values[5]	auto[0]	auto[1]	146	1		T63	6		T64	3		T65	4
all_values[5]	auto[1]	auto[0]	28	1		T66	1		T64	2		T262	1
all_values[5]	auto[1]	auto[1]	145	1		T63	1		T66	4		T64	3
all_values[6]	auto[0]	auto[0]	115248	1		T1	2		T2	3		T3	3
all_values[6]	auto[0]	auto[1]	134	1		T63	6		T66	3		T64	6
all_values[6]	auto[1]	auto[0]	29	1		T68	1		T262	1		T263	1
all_values[6]	auto[1]	auto[1]	147	1		T63	2		T66	1		T64	2
all_values[7]	auto[0]	auto[0]	115243	1		T1	2		T2	3		T3	3
all_values[7]	auto[0]	auto[1]	131	1		T63	5		T64	6		T68	2
all_values[7]	auto[1]	auto[0]	25	1		T65	2		T254	2		T264	1
all_values[7]	auto[1]	auto[1]	159	1		T63	3		T66	5		T64	2
all_values[8]	auto[0]	auto[0]	115248	1		T1	2		T2	3		T3	3
all_values[8]	auto[0]	auto[1]	157	1		T63	5		T66	4		T64	2
all_values[8]	auto[1]	auto[0]	25	1		T262	1		T252	2		T253	1
all_values[8]	auto[1]	auto[1]	128	1		T63	2		T66	1		T64	6
all_values[9]	auto[0]	auto[0]	115251	1		T1	2		T2	3		T3	3
all_values[9]	auto[0]	auto[1]	143	1		T63	3		T66	4		T64	4
all_values[9]	auto[1]	auto[0]	18	1		T63	1		T67	1		T252	1
all_values[9]	auto[1]	auto[1]	146	1		T63	4		T66	1		T64	4
all_values[10]	auto[0]	auto[0]	115240	1		T1	2		T2	3		T3	3
all_values[10]	auto[0]	auto[1]	146	1		T63	3		T64	6		T65	5
all_values[10]	auto[1]	auto[0]	18	1		T63	2		T67	1		T265	1
all_values[10]	auto[1]	auto[1]	154	1		T63	2		T66	5		T67	4
all_values[11]	auto[0]	auto[0]	115246	1		T1	2		T2	3		T3	3
all_values[11]	auto[0]	auto[1]	139	1		T63	6		T66	4		T64	5
all_values[11]	auto[1]	auto[0]	28	1		T262	1		T252	2		T253	1
all_values[11]	auto[1]	auto[1]	145	1		T63	2		T66	1		T64	3
all_values[12]	auto[0]	auto[0]	115243	1		T1	2		T2	3		T3	3
all_values[12]	auto[0]	auto[1]	139	1		T63	1		T64	2		T68	1
all_values[12]	auto[1]	auto[0]	22	1		T67	5		T266	1		T264	1
all_values[12]	auto[1]	auto[1]	154	1		T63	7		T66	5		T64	6
all_values[13]	auto[0]	auto[0]	115249	1		T1	2		T2	3		T3	3
all_values[13]	auto[0]	auto[1]	128	1		T63	5		T64	3		T67	4
all_values[13]	auto[1]	auto[0]	44	1		T63	1		T66	1		T64	1
all_values[13]	auto[1]	auto[1]	137	1		T63	2		T64	4		T68	4
all_values[14]	auto[0]	auto[0]	115245	1		T1	2		T2	3		T3	3
all_values[14]	auto[0]	auto[1]	148	1		T63	4		T66	1		T65	3
all_values[14]	auto[1]	auto[0]	34	1		T63	3		T64	2		T252	1
all_values[14]	auto[1]	auto[1]	131	1		T63	1		T66	4		T64	6
all_values[15]	auto[0]	auto[0]	115238	1		T1	2		T2	3		T3	3
all_values[15]	auto[0]	auto[1]	146	1		T63	1		T66	4		T64	5
all_values[15]	auto[1]	auto[0]	35	1		T63	1		T65	1		T262	1
all_values[15]	auto[1]	auto[1]	139	1		T63	5		T66	1		T64	3
all_values[16]	auto[0]	auto[0]	115238	1		T1	2		T2	3		T3	3
all_values[16]	auto[0]	auto[1]	159	1		T63	3		T66	4		T64	4
all_values[16]	auto[1]	auto[0]	23	1		T252	3		T254	1		T267	1
all_values[16]	auto[1]	auto[1]	138	1		T63	3		T66	1		T64	4
all_values[17]	auto[0]	auto[0]	115246	1		T1	2		T2	3		T3	3
all_values[17]	auto[0]	auto[1]	144	1		T63	2		T66	4		T64	3
all_values[17]	auto[1]	auto[0]	19	1		T63	1		T262	1		T268	2
all_values[17]	auto[1]	auto[1]	149	1		T63	5		T64	5		T67	3