Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	115558	1		T1	2		T2	3		T3	3
all_pins[1]	115558	1		T1	2		T2	3		T3	3
all_pins[2]	115558	1		T1	2		T2	3		T3	3
all_pins[3]	115558	1		T1	2		T2	3		T3	3
all_pins[4]	115558	1		T1	2		T2	3		T3	3
all_pins[5]	115558	1		T1	2		T2	3		T3	3
all_pins[6]	115558	1		T1	2		T2	3		T3	3
all_pins[7]	115558	1		T1	2		T2	3		T3	3
all_pins[8]	115558	1		T1	2		T2	3		T3	3
all_pins[9]	115558	1		T1	2		T2	3		T3	3
all_pins[10]	115558	1		T1	2		T2	3		T3	3
all_pins[11]	115558	1		T1	2		T2	3		T3	3
all_pins[12]	115558	1		T1	2		T2	3		T3	3
all_pins[13]	115558	1		T1	2		T2	3		T3	3
all_pins[14]	115558	1		T1	2		T2	3		T3	3
all_pins[15]	115558	1		T1	2		T2	3		T3	3
all_pins[16]	115558	1		T1	2		T2	3		T3	3
all_pins[17]	115558	1		T1	2		T2	3		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2078611	1		T1	36		T2	54		T3	53
values[0x1]	1433	1		T3	1		T37	1		T39	1
transitions[0x0=>0x1]	1079	1		T3	1		T37	1		T39	1
transitions[0x1=>0x0]	1093	1		T3	1		T37	1		T39	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	115397	1		T1	2		T2	3		T3	3
all_pins[0]	values[0x1]	161	1		T51	1		T269	1		T270	1
all_pins[0]	transitions[0x0=>0x1]	139	1		T51	1		T269	1		T270	1
all_pins[0]	transitions[0x1=>0x0]	141	1		T3	1		T37	1		T39	1
all_pins[1]	values[0x0]	115395	1		T1	2		T2	3		T3	2
all_pins[1]	values[0x1]	163	1		T3	1		T37	1		T39	1
all_pins[1]	transitions[0x0=>0x1]	147	1		T3	1		T37	1		T39	1
all_pins[1]	transitions[0x1=>0x0]	54	1		T64	2		T65	2		T67	1
all_pins[2]	values[0x0]	115488	1		T1	2		T2	3		T3	3
all_pins[2]	values[0x1]	70	1		T64	2		T65	2		T67	1
all_pins[2]	transitions[0x0=>0x1]	52	1		T64	2		T68	1		T262	1
all_pins[2]	transitions[0x1=>0x0]	36	1		T63	1		T66	1		T64	1
all_pins[3]	values[0x0]	115504	1		T1	2		T2	3		T3	3
all_pins[3]	values[0x1]	54	1		T63	1		T66	1		T64	1
all_pins[3]	transitions[0x0=>0x1]	35	1		T66	1		T64	1		T67	3
all_pins[3]	transitions[0x1=>0x0]	58	1		T63	1		T66	2		T64	2
all_pins[4]	values[0x0]	115481	1		T1	2		T2	3		T3	3
all_pins[4]	values[0x1]	77	1		T63	2		T66	2		T64	2
all_pins[4]	transitions[0x0=>0x1]	45	1		T63	2		T65	3		T68	2
all_pins[4]	transitions[0x1=>0x0]	51	1		T63	1		T66	1		T67	4
all_pins[5]	values[0x0]	115475	1		T1	2		T2	3		T3	3
all_pins[5]	values[0x1]	83	1		T63	1		T66	3		T64	2
all_pins[5]	transitions[0x0=>0x1]	58	1		T63	1		T66	2		T64	2
all_pins[5]	transitions[0x1=>0x0]	50	1		T63	1		T64	1		T65	3
all_pins[6]	values[0x0]	115483	1		T1	2		T2	3		T3	3
all_pins[6]	values[0x1]	75	1		T63	1		T66	1		T64	1
all_pins[6]	transitions[0x0=>0x1]	58	1		T64	1		T65	2		T68	2
all_pins[6]	transitions[0x1=>0x0]	53	1		T63	2		T66	1		T64	2
all_pins[7]	values[0x0]	115488	1		T1	2		T2	3		T3	3
all_pins[7]	values[0x1]	70	1		T63	3		T66	2		T64	2
all_pins[7]	transitions[0x0=>0x1]	52	1		T63	2		T66	1		T64	1
all_pins[7]	transitions[0x1=>0x0]	34	1		T64	3		T68	1		T253	2
all_pins[8]	values[0x0]	115506	1		T1	2		T2	3		T3	3
all_pins[8]	values[0x1]	52	1		T63	1		T66	1		T64	4
all_pins[8]	transitions[0x0=>0x1]	39	1		T63	1		T66	1		T64	4
all_pins[8]	transitions[0x1=>0x0]	44	1		T63	2		T64	1		T65	1
all_pins[9]	values[0x0]	115501	1		T1	2		T2	3		T3	3
all_pins[9]	values[0x1]	57	1		T63	2		T64	1		T65	1
all_pins[9]	transitions[0x0=>0x1]	40	1		T63	2		T64	1		T65	1
all_pins[9]	transitions[0x1=>0x0]	47	1		T63	2		T66	3		T67	3
all_pins[10]	values[0x0]	115494	1		T1	2		T2	3		T3	3
all_pins[10]	values[0x1]	64	1		T63	2		T66	3		T67	3
all_pins[10]	transitions[0x0=>0x1]	45	1		T63	1		T66	2		T68	2
all_pins[10]	transitions[0x1=>0x0]	56	1		T64	1		T68	3		T262	1
all_pins[11]	values[0x0]	115483	1		T1	2		T2	3		T3	3
all_pins[11]	values[0x1]	75	1		T63	1		T66	1		T64	1
all_pins[11]	transitions[0x0=>0x1]	52	1		T67	3		T68	2		T262	1
all_pins[11]	transitions[0x1=>0x0]	44	1		T63	2		T66	3		T64	3
all_pins[12]	values[0x0]	115491	1		T1	2		T2	3		T3	3
all_pins[12]	values[0x1]	67	1		T63	3		T66	4		T64	4
all_pins[12]	transitions[0x0=>0x1]	49	1		T63	3		T66	4		T64	2
all_pins[12]	transitions[0x1=>0x0]	59	1		T63	1		T64	1		T252	1
all_pins[13]	values[0x0]	115481	1		T1	2		T2	3		T3	3
all_pins[13]	values[0x1]	77	1		T63	1		T64	3		T252	1
all_pins[13]	transitions[0x0=>0x1]	52	1		T63	1		T253	2		T266	1
all_pins[13]	transitions[0x1=>0x0]	55	1		T66	3		T64	1		T65	1
all_pins[14]	values[0x0]	115478	1		T1	2		T2	3		T3	3
all_pins[14]	values[0x1]	80	1		T66	3		T64	4		T65	1
all_pins[14]	transitions[0x0=>0x1]	69	1		T66	3		T64	4		T67	3
all_pins[14]	transitions[0x1=>0x0]	55	1		T63	2		T64	1		T67	1
all_pins[15]	values[0x0]	115492	1		T1	2		T2	3		T3	3
all_pins[15]	values[0x1]	66	1		T63	2		T64	1		T65	1
all_pins[15]	transitions[0x0=>0x1]	47	1		T63	2		T67	1		T262	2
all_pins[15]	transitions[0x1=>0x0]	60	1		T63	2		T64	2		T65	3
all_pins[16]	values[0x0]	115479	1		T1	2		T2	3		T3	3
all_pins[16]	values[0x1]	79	1		T63	2		T64	3		T65	4
all_pins[16]	transitions[0x0=>0x1]	62	1		T63	2		T64	1		T65	4
all_pins[16]	transitions[0x1=>0x0]	46	1		T63	1		T64	1		T68	1
all_pins[17]	values[0x0]	115495	1		T1	2		T2	3		T3	3
all_pins[17]	values[0x1]	63	1		T63	1		T64	3		T68	1
all_pins[17]	transitions[0x0=>0x1]	38	1		T63	1		T64	2		T262	1
all_pins[17]	transitions[0x1=>0x0]	150	1		T51	1		T269	1		T270	1