Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	290	1		T63	7		T66	4		T64	7
all_values[1]	290	1		T63	7		T66	4		T64	7
all_values[2]	290	1		T63	7		T66	4		T64	7
all_values[3]	290	1		T63	7		T66	4		T64	7
all_values[4]	290	1		T63	7		T66	4		T64	7
all_values[5]	290	1		T63	7		T66	4		T64	7
all_values[6]	290	1		T63	7		T66	4		T64	7
all_values[7]	290	1		T63	7		T66	4		T64	7
all_values[8]	290	1		T63	7		T66	4		T64	7
all_values[9]	290	1		T63	7		T66	4		T64	7
all_values[10]	290	1		T63	7		T66	4		T64	7
all_values[11]	290	1		T63	7		T66	4		T64	7
all_values[12]	290	1		T63	7		T66	4		T64	7
all_values[13]	290	1		T63	7		T66	4		T64	7
all_values[14]	290	1		T63	7		T66	4		T64	7
all_values[15]	290	1		T63	7		T66	4		T64	7
all_values[16]	290	1		T63	7		T66	4		T64	7
all_values[17]	290	1		T63	7		T66	4		T64	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2893	1		T63	68		T66	39		T64	62
auto[1]	2327	1		T63	58		T66	33		T64	64

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	906	1		T63	16		T66	12		T64	12
auto[1]	4314	1		T63	110		T66	60		T64	114

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3041	1		T63	67		T66	41		T64	64
auto[1]	2179	1		T63	59		T66	31		T64	62

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	31	1		T64	1		T65	1		T68	1
all_values[0]	auto[0]	auto[0]	auto[1]	75	1		T63	1		T66	1		T64	1
all_values[0]	auto[0]	auto[1]	auto[0]	18	1		T65	3		T67	2		T252	1
all_values[0]	auto[0]	auto[1]	auto[1]	45	1		T63	1		T68	1		T262	1
all_values[0]	auto[1]	auto[0]	auto[1]	74	1		T63	3		T66	3		T64	4
all_values[0]	auto[1]	auto[1]	auto[1]	47	1		T63	2		T64	1		T68	2
all_values[1]	auto[0]	auto[0]	auto[0]	30	1		T63	1		T67	1		T68	4
all_values[1]	auto[0]	auto[0]	auto[1]	61	1		T66	1		T64	2		T65	1
all_values[1]	auto[0]	auto[1]	auto[0]	22	1		T262	1		T271	1		T266	1
all_values[1]	auto[0]	auto[1]	auto[1]	50	1		T63	2		T64	1		T65	2
all_values[1]	auto[1]	auto[0]	auto[1]	66	1		T63	2		T66	2		T64	2
all_values[1]	auto[1]	auto[1]	auto[1]	61	1		T63	2		T66	1		T64	2
all_values[2]	auto[0]	auto[0]	auto[0]	32	1		T66	2		T65	1		T253	1
all_values[2]	auto[0]	auto[0]	auto[1]	65	1		T64	1		T67	2		T68	1
all_values[2]	auto[0]	auto[1]	auto[0]	16	1		T66	2		T64	3		T264	4
all_values[2]	auto[0]	auto[1]	auto[1]	59	1		T63	4		T64	1		T65	1
all_values[2]	auto[1]	auto[0]	auto[1]	71	1		T63	1		T65	1		T68	4
all_values[2]	auto[1]	auto[1]	auto[1]	47	1		T63	2		T64	2		T65	1
all_values[3]	auto[0]	auto[0]	auto[0]	35	1		T64	1		T65	2		T263	2
all_values[3]	auto[0]	auto[0]	auto[1]	67	1		T63	3		T66	2		T64	2
all_values[3]	auto[0]	auto[1]	auto[0]	20	1		T66	1		T262	1		T252	1
all_values[3]	auto[0]	auto[1]	auto[1]	65	1		T63	2		T64	1		T65	1
all_values[3]	auto[1]	auto[0]	auto[1]	55	1		T63	1		T64	2		T68	3
all_values[3]	auto[1]	auto[1]	auto[1]	48	1		T63	1		T66	1		T64	1
all_values[4]	auto[0]	auto[0]	auto[0]	34	1		T263	1		T252	2		T254	2
all_values[4]	auto[0]	auto[0]	auto[1]	52	1		T63	1		T66	1		T64	1
all_values[4]	auto[0]	auto[1]	auto[0]	19	1		T67	2		T262	1		T252	1
all_values[4]	auto[0]	auto[1]	auto[1]	59	1		T66	1		T64	1		T65	1
all_values[4]	auto[1]	auto[0]	auto[1]	71	1		T63	2		T66	1		T64	4
all_values[4]	auto[1]	auto[1]	auto[1]	55	1		T63	4		T66	1		T64	1
all_values[5]	auto[0]	auto[0]	auto[0]	26	1		T63	1		T65	1		T253	1
all_values[5]	auto[0]	auto[0]	auto[1]	58	1		T63	2		T64	1		T65	2
all_values[5]	auto[0]	auto[1]	auto[0]	21	1		T66	1		T64	2		T262	1
all_values[5]	auto[0]	auto[1]	auto[1]	54	1		T63	1		T66	2		T64	1
all_values[5]	auto[1]	auto[0]	auto[1]	61	1		T63	3		T64	2		T65	1
all_values[5]	auto[1]	auto[1]	auto[1]	70	1		T66	1		T64	1		T67	3
all_values[6]	auto[0]	auto[0]	auto[0]	34	1		T66	1		T68	2		T263	1
all_values[6]	auto[0]	auto[0]	auto[1]	55	1		T63	3		T66	2		T64	3
all_values[6]	auto[0]	auto[1]	auto[0]	21	1		T262	1		T263	2		T254	2
all_values[6]	auto[0]	auto[1]	auto[1]	58	1		T65	1		T67	2		T68	2
all_values[6]	auto[1]	auto[0]	auto[1]	64	1		T63	2		T64	1		T65	1
all_values[6]	auto[1]	auto[1]	auto[1]	58	1		T63	2		T66	1		T64	3
all_values[7]	auto[0]	auto[0]	auto[0]	25	1		T65	1		T67	4		T262	1
all_values[7]	auto[0]	auto[0]	auto[1]	57	1		T63	1		T64	3		T68	2
all_values[7]	auto[0]	auto[1]	auto[0]	22	1		T65	1		T254	2		T264	1
all_values[7]	auto[0]	auto[1]	auto[1]	59	1		T63	2		T66	2		T64	1
all_values[7]	auto[1]	auto[0]	auto[1]	69	1		T63	2		T64	1		T68	2
all_values[7]	auto[1]	auto[1]	auto[1]	58	1		T63	2		T66	2		T64	2
all_values[8]	auto[0]	auto[0]	auto[0]	35	1		T63	1		T65	4		T68	1
all_values[8]	auto[0]	auto[0]	auto[1]	64	1		T63	3		T66	1		T64	1
all_values[8]	auto[0]	auto[1]	auto[0]	17	1		T262	1		T252	1		T264	1
all_values[8]	auto[0]	auto[1]	auto[1]	58	1		T64	1		T67	2		T262	3
all_values[8]	auto[1]	auto[0]	auto[1]	64	1		T63	1		T66	2		T64	1
all_values[8]	auto[1]	auto[1]	auto[1]	52	1		T63	2		T66	1		T64	4
all_values[9]	auto[0]	auto[0]	auto[0]	42	1		T63	1		T252	1		T253	1
all_values[9]	auto[0]	auto[0]	auto[1]	61	1		T63	1		T66	2		T64	3
all_values[9]	auto[0]	auto[1]	auto[0]	6	1		T67	1		T271	1		T272	1
all_values[9]	auto[0]	auto[1]	auto[1]	61	1		T63	1		T64	2		T67	2
all_values[9]	auto[1]	auto[0]	auto[1]	79	1		T63	3		T66	1		T64	1
all_values[9]	auto[1]	auto[1]	auto[1]	41	1		T63	1		T66	1		T64	1
all_values[10]	auto[0]	auto[0]	auto[0]	25	1		T63	1		T64	2		T266	1
all_values[10]	auto[0]	auto[0]	auto[1]	63	1		T63	1		T64	3		T65	2
all_values[10]	auto[0]	auto[1]	auto[0]	14	1		T63	2		T67	1		T265	2
all_values[10]	auto[0]	auto[1]	auto[1]	63	1		T63	1		T66	1		T67	1
all_values[10]	auto[1]	auto[0]	auto[1]	81	1		T63	1		T64	2		T65	2
all_values[10]	auto[1]	auto[1]	auto[1]	44	1		T63	1		T66	3		T67	2
all_values[11]	auto[0]	auto[0]	auto[0]	37	1		T65	2		T67	1		T262	2
all_values[11]	auto[0]	auto[0]	auto[1]	58	1		T63	1		T66	2		T64	3
all_values[11]	auto[0]	auto[1]	auto[0]	17	1		T262	1		T252	1		T266	2
all_values[11]	auto[0]	auto[1]	auto[1]	60	1		T63	2		T64	3		T67	1
all_values[11]	auto[1]	auto[0]	auto[1]	58	1		T63	3		T66	1		T65	1
all_values[11]	auto[1]	auto[1]	auto[1]	60	1		T63	1		T66	1		T64	1
all_values[12]	auto[0]	auto[0]	auto[0]	31	1		T68	3		T271	1		T266	4
all_values[12]	auto[0]	auto[0]	auto[1]	58	1		T63	1		T64	1		T263	1
all_values[12]	auto[0]	auto[1]	auto[0]	12	1		T67	4		T267	3		T268	1
all_values[12]	auto[0]	auto[1]	auto[1]	70	1		T63	4		T66	3		T64	2
all_values[12]	auto[1]	auto[0]	auto[1]	64	1		T63	1		T64	1		T65	1
all_values[12]	auto[1]	auto[1]	auto[1]	55	1		T63	1		T66	1		T64	3
all_values[13]	auto[0]	auto[0]	auto[0]	39	1		T63	1		T66	3		T65	4
all_values[13]	auto[0]	auto[0]	auto[1]	58	1		T63	2		T64	1		T67	1
all_values[13]	auto[0]	auto[1]	auto[0]	31	1		T66	1		T64	1		T67	1
all_values[13]	auto[0]	auto[1]	auto[1]	51	1		T63	1		T64	1		T68	2
all_values[13]	auto[1]	auto[0]	auto[1]	62	1		T63	1		T64	2		T67	1
all_values[13]	auto[1]	auto[1]	auto[1]	49	1		T63	2		T64	2		T67	1
all_values[14]	auto[0]	auto[0]	auto[0]	36	1		T63	1		T65	1		T262	1
all_values[14]	auto[0]	auto[0]	auto[1]	61	1		T63	1		T66	1		T65	2
all_values[14]	auto[0]	auto[1]	auto[0]	22	1		T63	2		T64	2		T265	3
all_values[14]	auto[0]	auto[1]	auto[1]	50	1		T63	1		T66	1		T64	1
all_values[14]	auto[1]	auto[0]	auto[1]	65	1		T68	1		T263	2		T252	1
all_values[14]	auto[1]	auto[1]	auto[1]	56	1		T63	2		T66	2		T64	4
all_values[15]	auto[0]	auto[0]	auto[0]	28	1		T63	2		T65	1		T262	2
all_values[15]	auto[0]	auto[0]	auto[1]	57	1		T63	1		T66	1		T64	2
all_values[15]	auto[0]	auto[1]	auto[0]	24	1		T262	1		T264	4		T272	1
all_values[15]	auto[0]	auto[1]	auto[1]	61	1		T63	1		T66	1		T64	1
all_values[15]	auto[1]	auto[0]	auto[1]	70	1		T63	2		T66	2		T64	3
all_values[15]	auto[1]	auto[1]	auto[1]	50	1		T63	1		T64	1		T65	1
all_values[16]	auto[0]	auto[0]	auto[0]	23	1		T63	2		T252	4		T267	1
all_values[16]	auto[0]	auto[0]	auto[1]	68	1		T63	1		T66	2		T64	2
all_values[16]	auto[0]	auto[1]	auto[0]	18	1		T252	3		T254	1		T273	1
all_values[16]	auto[0]	auto[1]	auto[1]	55	1		T63	1		T66	1		T64	2
all_values[16]	auto[1]	auto[0]	auto[1]	76	1		T63	3		T66	1		T65	1
all_values[16]	auto[1]	auto[1]	auto[1]	50	1		T64	3		T65	1		T67	1
all_values[17]	auto[0]	auto[0]	auto[0]	33	1		T63	1		T66	1		T65	1
all_values[17]	auto[0]	auto[0]	auto[1]	54	1		T63	1		T66	1		T64	1
all_values[17]	auto[0]	auto[1]	auto[0]	10	1		T262	1		T268	1		T274	1
all_values[17]	auto[0]	auto[1]	auto[1]	65	1		T63	3		T64	2		T67	2
all_values[17]	auto[1]	auto[0]	auto[1]	75	1		T63	1		T66	2		T64	1
all_values[17]	auto[1]	auto[1]	auto[1]	53	1		T63	1		T64	3		T68	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal