Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.90 96.71 89.46 97.11 50.00 94.66 97.97 96.40


Total test records in report: 1478
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T1329 /workspace/coverage/default/47.usbdev_pkt_buffer.1583469021 Apr 15 03:18:27 PM PDT 24 Apr 15 03:18:59 PM PDT 24 15563573237 ps
T1330 /workspace/coverage/default/10.usbdev_pkt_received.4266313940 Apr 15 03:13:11 PM PDT 24 Apr 15 03:13:20 PM PDT 24 8425460685 ps
T1331 /workspace/coverage/default/46.usbdev_phy_pins_sense.3701951720 Apr 15 03:18:24 PM PDT 24 Apr 15 03:18:26 PM PDT 24 37953929 ps
T1332 /workspace/coverage/default/38.random_length_in_trans.2237791037 Apr 15 03:17:29 PM PDT 24 Apr 15 03:17:38 PM PDT 24 8417396274 ps
T1333 /workspace/coverage/default/5.usbdev_in_stall.2817864375 Apr 15 03:12:12 PM PDT 24 Apr 15 03:12:21 PM PDT 24 8371894028 ps
T1334 /workspace/coverage/default/41.usbdev_enable.3272971682 Apr 15 03:17:57 PM PDT 24 Apr 15 03:18:05 PM PDT 24 8374714426 ps
T70 /workspace/coverage/default/1.usbdev_sec_cm.3720625685 Apr 15 03:10:57 PM PDT 24 Apr 15 03:10:59 PM PDT 24 400520175 ps
T1335 /workspace/coverage/default/28.usbdev_stall_trans.3584100192 Apr 15 03:16:07 PM PDT 24 Apr 15 03:16:16 PM PDT 24 8398851136 ps
T1336 /workspace/coverage/default/0.usbdev_out_stall.876568760 Apr 15 03:09:54 PM PDT 24 Apr 15 03:10:05 PM PDT 24 8387499254 ps
T1337 /workspace/coverage/default/47.usbdev_fifo_rst.2751553155 Apr 15 03:18:27 PM PDT 24 Apr 15 03:18:31 PM PDT 24 88081193 ps
T1338 /workspace/coverage/default/8.usbdev_smoke.3125522709 Apr 15 03:12:40 PM PDT 24 Apr 15 03:12:50 PM PDT 24 8438111516 ps
T1339 /workspace/coverage/default/41.usbdev_pkt_sent.1253033145 Apr 15 03:17:47 PM PDT 24 Apr 15 03:17:58 PM PDT 24 8387801310 ps
T1340 /workspace/coverage/default/18.usbdev_pkt_sent.4156811996 Apr 15 03:14:38 PM PDT 24 Apr 15 03:14:46 PM PDT 24 8471065323 ps
T1341 /workspace/coverage/default/32.max_length_in_transaction.3581073870 Apr 15 03:16:43 PM PDT 24 Apr 15 03:16:53 PM PDT 24 8461343919 ps
T1342 /workspace/coverage/default/26.max_length_in_transaction.3418620435 Apr 15 03:15:58 PM PDT 24 Apr 15 03:16:07 PM PDT 24 8501587056 ps
T1343 /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.3194507412 Apr 15 03:17:34 PM PDT 24 Apr 15 03:17:44 PM PDT 24 8373993330 ps
T1344 /workspace/coverage/default/7.usbdev_av_buffer.2091116423 Apr 15 03:12:31 PM PDT 24 Apr 15 03:12:40 PM PDT 24 8380324264 ps
T1345 /workspace/coverage/default/48.min_length_in_transaction.3264690336 Apr 15 03:18:41 PM PDT 24 Apr 15 03:18:52 PM PDT 24 8474343199 ps
T1346 /workspace/coverage/default/28.usbdev_phy_pins_sense.2579099470 Apr 15 03:16:10 PM PDT 24 Apr 15 03:16:11 PM PDT 24 40680435 ps
T1347 /workspace/coverage/default/1.usbdev_smoke.2901126458 Apr 15 03:10:24 PM PDT 24 Apr 15 03:10:34 PM PDT 24 8493059580 ps
T1348 /workspace/coverage/default/2.usbdev_pkt_sent.2503673818 Apr 15 03:11:04 PM PDT 24 Apr 15 03:11:13 PM PDT 24 8483414564 ps
T1349 /workspace/coverage/default/4.usbdev_random_length_out_trans.1590445611 Apr 15 03:11:49 PM PDT 24 Apr 15 03:11:57 PM PDT 24 8383954946 ps
T1350 /workspace/coverage/default/47.usbdev_in_stall.3465301634 Apr 15 03:18:33 PM PDT 24 Apr 15 03:18:41 PM PDT 24 8366204094 ps
T1351 /workspace/coverage/default/39.max_length_in_transaction.1472468673 Apr 15 03:17:39 PM PDT 24 Apr 15 03:17:48 PM PDT 24 8480022764 ps
T1352 /workspace/coverage/default/16.usbdev_in_iso.1901470089 Apr 15 03:14:23 PM PDT 24 Apr 15 03:14:32 PM PDT 24 8444704451 ps
T1353 /workspace/coverage/default/35.usbdev_setup_stage.1962645695 Apr 15 03:17:07 PM PDT 24 Apr 15 03:17:17 PM PDT 24 8421849401 ps
T1354 /workspace/coverage/default/36.random_length_in_trans.1186268337 Apr 15 03:17:14 PM PDT 24 Apr 15 03:17:23 PM PDT 24 8440612221 ps
T1355 /workspace/coverage/default/4.usbdev_stall_priority_over_nak.585788490 Apr 15 03:11:49 PM PDT 24 Apr 15 03:11:58 PM PDT 24 8395394835 ps
T1356 /workspace/coverage/default/38.usbdev_in_iso.1825558132 Apr 15 03:17:27 PM PDT 24 Apr 15 03:17:36 PM PDT 24 8428175126 ps
T1357 /workspace/coverage/default/43.usbdev_random_length_out_trans.2195883734 Apr 15 03:17:58 PM PDT 24 Apr 15 03:18:07 PM PDT 24 8433473248 ps
T1358 /workspace/coverage/default/18.random_length_in_trans.1230929647 Apr 15 03:14:40 PM PDT 24 Apr 15 03:14:49 PM PDT 24 8427435173 ps
T1359 /workspace/coverage/default/6.usbdev_pkt_sent.588199688 Apr 15 03:12:20 PM PDT 24 Apr 15 03:12:28 PM PDT 24 8423291183 ps
T1360 /workspace/coverage/default/27.usbdev_out_stall.1925094719 Apr 15 03:15:56 PM PDT 24 Apr 15 03:16:05 PM PDT 24 8383350063 ps
T1361 /workspace/coverage/default/44.usbdev_pkt_received.1017293719 Apr 15 03:18:09 PM PDT 24 Apr 15 03:18:18 PM PDT 24 8396558879 ps
T93 /workspace/coverage/default/19.usbdev_nak_trans.214501746 Apr 15 03:14:44 PM PDT 24 Apr 15 03:14:52 PM PDT 24 8446893589 ps
T1362 /workspace/coverage/default/42.usbdev_nak_trans.2704968697 Apr 15 03:17:53 PM PDT 24 Apr 15 03:18:03 PM PDT 24 8427863316 ps
T1363 /workspace/coverage/default/42.max_length_in_transaction.716300331 Apr 15 03:17:53 PM PDT 24 Apr 15 03:18:03 PM PDT 24 8475711503 ps
T1364 /workspace/coverage/default/39.usbdev_max_length_out_transaction.2161503247 Apr 15 03:17:32 PM PDT 24 Apr 15 03:17:41 PM PDT 24 8412206279 ps
T1365 /workspace/coverage/default/48.usbdev_enable.2838781219 Apr 15 03:18:30 PM PDT 24 Apr 15 03:18:39 PM PDT 24 8373116322 ps
T1366 /workspace/coverage/default/17.usbdev_out_trans_nak.1049953426 Apr 15 03:14:30 PM PDT 24 Apr 15 03:14:38 PM PDT 24 8408484902 ps
T1367 /workspace/coverage/default/25.usbdev_fifo_rst.1904739574 Apr 15 03:15:43 PM PDT 24 Apr 15 03:15:45 PM PDT 24 94047153 ps
T1368 /workspace/coverage/default/42.usbdev_phy_pins_sense.4135493751 Apr 15 03:17:57 PM PDT 24 Apr 15 03:17:59 PM PDT 24 31433234 ps
T1369 /workspace/coverage/default/32.usbdev_pending_in_trans.450355509 Apr 15 03:16:44 PM PDT 24 Apr 15 03:16:53 PM PDT 24 8505216850 ps
T1370 /workspace/coverage/default/1.usbdev_min_length_out_transaction.3629769644 Apr 15 03:10:32 PM PDT 24 Apr 15 03:10:41 PM PDT 24 8386359414 ps
T1371 /workspace/coverage/default/13.usbdev_pending_in_trans.4234859617 Apr 15 03:13:52 PM PDT 24 Apr 15 03:14:00 PM PDT 24 8390331973 ps
T1372 /workspace/coverage/default/47.usbdev_setup_stage.3605252529 Apr 15 03:18:30 PM PDT 24 Apr 15 03:18:40 PM PDT 24 8376057625 ps
T1373 /workspace/coverage/default/25.max_length_in_transaction.3006873542 Apr 15 03:15:44 PM PDT 24 Apr 15 03:15:53 PM PDT 24 8464553724 ps
T1374 /workspace/coverage/default/31.usbdev_setup_stage.3606636765 Apr 15 03:16:34 PM PDT 24 Apr 15 03:16:42 PM PDT 24 8377430348 ps
T1375 /workspace/coverage/default/48.max_length_in_transaction.2459652321 Apr 15 03:18:36 PM PDT 24 Apr 15 03:18:45 PM PDT 24 8465379357 ps
T1376 /workspace/coverage/default/48.usbdev_stall_trans.1994681611 Apr 15 03:18:41 PM PDT 24 Apr 15 03:18:51 PM PDT 24 8400935644 ps
T1377 /workspace/coverage/default/5.usbdev_min_length_out_transaction.2071933742 Apr 15 03:11:59 PM PDT 24 Apr 15 03:12:08 PM PDT 24 8370974659 ps
T1378 /workspace/coverage/default/22.usbdev_stall_trans.322704400 Apr 15 03:15:15 PM PDT 24 Apr 15 03:15:24 PM PDT 24 8394028200 ps
T1379 /workspace/coverage/default/9.usbdev_smoke.1985842017 Apr 15 03:12:55 PM PDT 24 Apr 15 03:13:04 PM PDT 24 8456638016 ps
T63 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1985627528 Apr 15 12:31:24 PM PDT 24 Apr 15 12:31:27 PM PDT 24 43608260 ps
T55 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.4170156229 Apr 15 12:31:02 PM PDT 24 Apr 15 12:31:05 PM PDT 24 387816462 ps
T61 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3648552903 Apr 15 12:31:19 PM PDT 24 Apr 15 12:31:22 PM PDT 24 116062423 ps
T66 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2865926812 Apr 15 12:31:23 PM PDT 24 Apr 15 12:31:25 PM PDT 24 25572915 ps
T64 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3438382016 Apr 15 12:31:31 PM PDT 24 Apr 15 12:31:33 PM PDT 24 24333949 ps
T56 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.970333641 Apr 15 12:31:11 PM PDT 24 Apr 15 12:31:14 PM PDT 24 238980783 ps
T57 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4079660988 Apr 15 12:31:21 PM PDT 24 Apr 15 12:31:23 PM PDT 24 111618166 ps
T187 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.301633069 Apr 15 12:31:19 PM PDT 24 Apr 15 12:31:22 PM PDT 24 157937650 ps
T188 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2244445734 Apr 15 12:31:47 PM PDT 24 Apr 15 12:31:50 PM PDT 24 84882558 ps
T189 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1206404788 Apr 15 12:31:24 PM PDT 24 Apr 15 12:31:29 PM PDT 24 533175772 ps
T65 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1727983882 Apr 15 12:31:23 PM PDT 24 Apr 15 12:31:25 PM PDT 24 35889331 ps
T67 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3392721312 Apr 15 12:31:27 PM PDT 24 Apr 15 12:31:30 PM PDT 24 29687460 ps
T190 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3971515028 Apr 15 12:31:19 PM PDT 24 Apr 15 12:31:20 PM PDT 24 36844519 ps
T68 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3820290913 Apr 15 12:31:22 PM PDT 24 Apr 15 12:31:23 PM PDT 24 36008365 ps
T191 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.190665791 Apr 15 12:31:09 PM PDT 24 Apr 15 12:31:13 PM PDT 24 225703990 ps
T262 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1207518115 Apr 15 12:31:23 PM PDT 24 Apr 15 12:31:25 PM PDT 24 32840629 ps
T193 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2292342283 Apr 15 12:30:58 PM PDT 24 Apr 15 12:31:01 PM PDT 24 91224811 ps
T263 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2075568314 Apr 15 12:31:25 PM PDT 24 Apr 15 12:31:27 PM PDT 24 38067048 ps
T192 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.836714803 Apr 15 12:31:25 PM PDT 24 Apr 15 12:31:28 PM PDT 24 35208912 ps
T252 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2595069522 Apr 15 12:31:16 PM PDT 24 Apr 15 12:31:17 PM PDT 24 32071554 ps
T253 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.775902246 Apr 15 12:31:24 PM PDT 24 Apr 15 12:31:26 PM PDT 24 38694838 ps
T199 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2994784515 Apr 15 12:31:26 PM PDT 24 Apr 15 12:31:31 PM PDT 24 257945135 ps
T197 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.4234231799 Apr 15 12:31:27 PM PDT 24 Apr 15 12:31:31 PM PDT 24 67168676 ps
T194 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3440285785 Apr 15 12:31:25 PM PDT 24 Apr 15 12:31:33 PM PDT 24 90634890 ps
T214 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.775148887 Apr 15 12:31:22 PM PDT 24 Apr 15 12:31:25 PM PDT 24 170185891 ps
T254 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.4163607793 Apr 15 12:31:32 PM PDT 24 Apr 15 12:31:34 PM PDT 24 31777511 ps
T198 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.856836722 Apr 15 12:31:17 PM PDT 24 Apr 15 12:31:21 PM PDT 24 308654062 ps
T218 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3321481770 Apr 15 12:31:25 PM PDT 24 Apr 15 12:31:31 PM PDT 24 551866188 ps
T244 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2368108889 Apr 15 12:31:27 PM PDT 24 Apr 15 12:31:30 PM PDT 24 41046672 ps
T219 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.4103936701 Apr 15 12:31:30 PM PDT 24 Apr 15 12:31:32 PM PDT 24 78592045 ps
T1380 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3820116810 Apr 15 12:31:27 PM PDT 24 Apr 15 12:31:33 PM PDT 24 477290911 ps
T271 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3032370232 Apr 15 12:31:20 PM PDT 24 Apr 15 12:31:21 PM PDT 24 28244773 ps
T250 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2420436048 Apr 15 12:31:17 PM PDT 24 Apr 15 12:31:19 PM PDT 24 100612454 ps
T245 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3621794105 Apr 15 12:31:13 PM PDT 24 Apr 15 12:31:15 PM PDT 24 161397494 ps
T246 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3974248648 Apr 15 12:31:23 PM PDT 24 Apr 15 12:31:26 PM PDT 24 97839409 ps
T256 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3488716067 Apr 15 12:31:26 PM PDT 24 Apr 15 12:31:31 PM PDT 24 516045072 ps
T266 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.4136145043 Apr 15 12:31:23 PM PDT 24 Apr 15 12:31:26 PM PDT 24 34485935 ps
T257 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2408146518 Apr 15 12:31:20 PM PDT 24 Apr 15 12:31:24 PM PDT 24 302113395 ps
T264 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.810778426 Apr 15 12:31:55 PM PDT 24 Apr 15 12:31:56 PM PDT 24 43098831 ps
T247 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2040479280 Apr 15 12:31:07 PM PDT 24 Apr 15 12:31:09 PM PDT 24 49861845 ps
T234 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2752349712 Apr 15 12:31:24 PM PDT 24 Apr 15 12:31:27 PM PDT 24 41203945 ps
T267 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3758480453 Apr 15 12:31:18 PM PDT 24 Apr 15 12:31:19 PM PDT 24 40260386 ps
T248 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1533901466 Apr 15 12:31:23 PM PDT 24 Apr 15 12:31:25 PM PDT 24 99109724 ps
T1381 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2046042170 Apr 15 12:31:21 PM PDT 24 Apr 15 12:31:23 PM PDT 24 205211227 ps
T216 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3584268326 Apr 15 12:31:24 PM PDT 24 Apr 15 12:31:27 PM PDT 24 149524676 ps
T1382 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.18756678 Apr 15 12:31:24 PM PDT 24 Apr 15 12:31:27 PM PDT 24 47572922 ps
T251 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2384269812 Apr 15 12:31:21 PM PDT 24 Apr 15 12:31:24 PM PDT 24 162190906 ps
T268 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.576909383 Apr 15 12:31:30 PM PDT 24 Apr 15 12:31:32 PM PDT 24 24682115 ps
T212 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2762391440 Apr 15 12:31:25 PM PDT 24 Apr 15 12:31:29 PM PDT 24 170136665 ps
T1383 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1034919587 Apr 15 12:31:22 PM PDT 24 Apr 15 12:31:25 PM PDT 24 61723931 ps
T235 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2482550569 Apr 15 12:31:13 PM PDT 24 Apr 15 12:31:16 PM PDT 24 192453751 ps
T1384 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3703421326 Apr 15 12:31:19 PM PDT 24 Apr 15 12:31:20 PM PDT 24 103434333 ps
T1385 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3287031036 Apr 15 12:30:58 PM PDT 24 Apr 15 12:31:03 PM PDT 24 719552520 ps
T1386 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.4179125606 Apr 15 12:31:18 PM PDT 24 Apr 15 12:31:23 PM PDT 24 604457091 ps
T210 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2527148334 Apr 15 12:31:20 PM PDT 24 Apr 15 12:31:23 PM PDT 24 101538274 ps
T265 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.830247786 Apr 15 12:31:30 PM PDT 24 Apr 15 12:31:32 PM PDT 24 37335775 ps
T236 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1916087403 Apr 15 12:31:29 PM PDT 24 Apr 15 12:31:32 PM PDT 24 68214476 ps
T213 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3463186636 Apr 15 12:31:22 PM PDT 24 Apr 15 12:31:26 PM PDT 24 333189770 ps
T1387 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.541618212 Apr 15 12:31:05 PM PDT 24 Apr 15 12:31:07 PM PDT 24 133000545 ps
T255 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2855180765 Apr 15 12:31:21 PM PDT 24 Apr 15 12:31:23 PM PDT 24 46644412 ps
T1388 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1394092789 Apr 15 12:31:27 PM PDT 24 Apr 15 12:31:30 PM PDT 24 31175209 ps
T261 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1033346705 Apr 15 12:31:25 PM PDT 24 Apr 15 12:31:30 PM PDT 24 588356935 ps
T237 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2353029032 Apr 15 12:31:21 PM PDT 24 Apr 15 12:31:25 PM PDT 24 187947066 ps
T195 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1159317712 Apr 15 12:31:26 PM PDT 24 Apr 15 12:31:30 PM PDT 24 135625773 ps
T272 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.4146047632 Apr 15 12:31:24 PM PDT 24 Apr 15 12:31:27 PM PDT 24 79665485 ps
T1389 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2307362927 Apr 15 12:31:22 PM PDT 24 Apr 15 12:31:25 PM PDT 24 91965852 ps
T274 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1587589321 Apr 15 12:31:23 PM PDT 24 Apr 15 12:31:26 PM PDT 24 32180876 ps
T273 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3915548511 Apr 15 12:31:26 PM PDT 24 Apr 15 12:31:29 PM PDT 24 34559201 ps
T238 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2047727265 Apr 15 12:31:19 PM PDT 24 Apr 15 12:31:21 PM PDT 24 37131313 ps
T259 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.546230855 Apr 15 12:31:23 PM PDT 24 Apr 15 12:31:27 PM PDT 24 509943853 ps
T1390 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2143977432 Apr 15 12:31:21 PM PDT 24 Apr 15 12:31:24 PM PDT 24 92510665 ps
T239 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3155235762 Apr 15 12:31:21 PM PDT 24 Apr 15 12:31:30 PM PDT 24 747739920 ps
T258 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.271809996 Apr 15 12:31:23 PM PDT 24 Apr 15 12:31:27 PM PDT 24 429995337 ps
T20 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3606912514 Apr 15 12:30:57 PM PDT 24 Apr 15 12:30:58 PM PDT 24 60061017 ps
T1391 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1570452240 Apr 15 12:31:25 PM PDT 24 Apr 15 12:31:28 PM PDT 24 42496263 ps
T1392 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.4164385886 Apr 15 12:31:24 PM PDT 24 Apr 15 12:31:26 PM PDT 24 36478066 ps
T1393 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2858513868 Apr 15 12:31:28 PM PDT 24 Apr 15 12:31:31 PM PDT 24 32152580 ps
T1394 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2290636385 Apr 15 12:31:21 PM PDT 24 Apr 15 12:31:23 PM PDT 24 34063738 ps
T1395 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2932479220 Apr 15 12:31:17 PM PDT 24 Apr 15 12:31:19 PM PDT 24 160979940 ps
T1396 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1777676607 Apr 15 12:31:23 PM PDT 24 Apr 15 12:31:27 PM PDT 24 76235571 ps
T240 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1831581313 Apr 15 12:31:00 PM PDT 24 Apr 15 12:31:09 PM PDT 24 1172850431 ps
T211 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.492482022 Apr 15 12:31:27 PM PDT 24 Apr 15 12:31:31 PM PDT 24 67878186 ps
T1397 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.252814125 Apr 15 12:31:19 PM PDT 24 Apr 15 12:31:21 PM PDT 24 32222009 ps
T1398 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.287393005 Apr 15 12:31:27 PM PDT 24 Apr 15 12:31:30 PM PDT 24 175145517 ps
T1399 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.492415534 Apr 15 12:31:25 PM PDT 24 Apr 15 12:31:29 PM PDT 24 167943290 ps
T1400 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3291375390 Apr 15 12:31:22 PM PDT 24 Apr 15 12:31:25 PM PDT 24 25270995 ps
T21 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3569137492 Apr 15 12:31:23 PM PDT 24 Apr 15 12:31:26 PM PDT 24 72177625 ps
T1401 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1729399801 Apr 15 12:31:22 PM PDT 24 Apr 15 12:31:24 PM PDT 24 204479071 ps
T1402 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3319771029 Apr 15 12:31:23 PM PDT 24 Apr 15 12:31:26 PM PDT 24 33522382 ps
T1403 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3756043449 Apr 15 12:31:21 PM PDT 24 Apr 15 12:31:23 PM PDT 24 47921499 ps
T1404 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2509131527 Apr 15 12:31:21 PM PDT 24 Apr 15 12:31:23 PM PDT 24 154818736 ps
T1405 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2929166719 Apr 15 12:31:28 PM PDT 24 Apr 15 12:31:30 PM PDT 24 28742149 ps
T1406 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2231560754 Apr 15 12:31:15 PM PDT 24 Apr 15 12:31:16 PM PDT 24 37751796 ps
T1407 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1263553913 Apr 15 12:31:23 PM PDT 24 Apr 15 12:31:26 PM PDT 24 44247051 ps
T241 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1609427738 Apr 15 12:31:14 PM PDT 24 Apr 15 12:31:17 PM PDT 24 189592521 ps
T1408 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2089062853 Apr 15 12:31:21 PM PDT 24 Apr 15 12:31:24 PM PDT 24 162762282 ps
T1409 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.778040418 Apr 15 12:31:26 PM PDT 24 Apr 15 12:31:29 PM PDT 24 38082881 ps
T1410 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2915358426 Apr 15 12:31:22 PM PDT 24 Apr 15 12:31:25 PM PDT 24 91065042 ps
T1411 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3121043164 Apr 15 12:31:39 PM PDT 24 Apr 15 12:31:41 PM PDT 24 93402996 ps
T1412 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1712273864 Apr 15 12:31:22 PM PDT 24 Apr 15 12:31:23 PM PDT 24 34031775 ps
T1413 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1732537106 Apr 15 12:31:24 PM PDT 24 Apr 15 12:31:27 PM PDT 24 68255193 ps
T260 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2422008108 Apr 15 12:31:24 PM PDT 24 Apr 15 12:31:28 PM PDT 24 213865943 ps
T1414 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3788678996 Apr 15 12:31:25 PM PDT 24 Apr 15 12:31:33 PM PDT 24 1975855015 ps
T1415 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.453943715 Apr 15 12:31:20 PM PDT 24 Apr 15 12:31:23 PM PDT 24 300156665 ps
T217 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2393076095 Apr 15 12:31:25 PM PDT 24 Apr 15 12:31:29 PM PDT 24 53137548 ps
T275 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1066082847 Apr 15 12:31:05 PM PDT 24 Apr 15 12:31:08 PM PDT 24 316062290 ps
T1416 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1641467397 Apr 15 12:31:21 PM PDT 24 Apr 15 12:31:24 PM PDT 24 188383832 ps
T1417 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1263436550 Apr 15 12:31:25 PM PDT 24 Apr 15 12:31:28 PM PDT 24 29014074 ps
T243 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3946129051 Apr 15 12:31:18 PM PDT 24 Apr 15 12:31:21 PM PDT 24 165290641 ps
T1418 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2314827951 Apr 15 12:31:23 PM PDT 24 Apr 15 12:31:26 PM PDT 24 53554634 ps
T242 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.4104250596 Apr 15 12:31:17 PM PDT 24 Apr 15 12:31:26 PM PDT 24 1442848197 ps
T1419 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3714605541 Apr 15 12:31:21 PM PDT 24 Apr 15 12:31:24 PM PDT 24 146111164 ps
T1420 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2051227567 Apr 15 12:31:15 PM PDT 24 Apr 15 12:31:17 PM PDT 24 69279548 ps
T1421 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.631750298 Apr 15 12:31:27 PM PDT 24 Apr 15 12:31:30 PM PDT 24 82208735 ps
T1422 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1758718840 Apr 15 12:31:09 PM PDT 24 Apr 15 12:31:13 PM PDT 24 171423317 ps
T1423 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1565416027 Apr 15 12:31:15 PM PDT 24 Apr 15 12:31:17 PM PDT 24 87416147 ps
T215 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2333297647 Apr 15 12:31:23 PM PDT 24 Apr 15 12:31:28 PM PDT 24 297147337 ps
T1424 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1995031152 Apr 15 12:31:49 PM PDT 24 Apr 15 12:31:51 PM PDT 24 120898614 ps
T1425 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2822256574 Apr 15 12:31:17 PM PDT 24 Apr 15 12:31:22 PM PDT 24 617135213 ps
T1426 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2348698672 Apr 15 12:31:24 PM PDT 24 Apr 15 12:31:29 PM PDT 24 90304196 ps
T1427 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.880258827 Apr 15 12:31:26 PM PDT 24 Apr 15 12:31:28 PM PDT 24 59572616 ps
T1428 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2398878217 Apr 15 12:31:28 PM PDT 24 Apr 15 12:31:30 PM PDT 24 31233683 ps
T1429 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3208252910 Apr 15 12:31:24 PM PDT 24 Apr 15 12:31:27 PM PDT 24 269501493 ps
T1430 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2002708479 Apr 15 12:31:23 PM PDT 24 Apr 15 12:31:25 PM PDT 24 195175413 ps
T1431 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2540093586 Apr 15 12:31:19 PM PDT 24 Apr 15 12:31:21 PM PDT 24 67633789 ps
T1432 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.548615783 Apr 15 12:31:22 PM PDT 24 Apr 15 12:31:26 PM PDT 24 284648159 ps
T1433 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3533742136 Apr 15 12:31:22 PM PDT 24 Apr 15 12:31:28 PM PDT 24 291356045 ps
T1434 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1879793020 Apr 15 12:31:31 PM PDT 24 Apr 15 12:31:33 PM PDT 24 26250154 ps
T1435 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4230062561 Apr 15 12:31:53 PM PDT 24 Apr 15 12:31:56 PM PDT 24 285884958 ps
T1436 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.203169805 Apr 15 12:31:24 PM PDT 24 Apr 15 12:31:27 PM PDT 24 38460079 ps
T1437 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.859187710 Apr 15 12:31:24 PM PDT 24 Apr 15 12:31:26 PM PDT 24 30690383 ps
T1438 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2496274745 Apr 15 12:31:20 PM PDT 24 Apr 15 12:31:23 PM PDT 24 250977407 ps
T1439 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1764548119 Apr 15 12:31:08 PM PDT 24 Apr 15 12:31:14 PM PDT 24 879466170 ps
T1440 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3829762379 Apr 15 12:31:29 PM PDT 24 Apr 15 12:31:32 PM PDT 24 87899337 ps
T1441 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.125714623 Apr 15 12:31:27 PM PDT 24 Apr 15 12:31:29 PM PDT 24 32612502 ps
T1442 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2316463592 Apr 15 12:31:11 PM PDT 24 Apr 15 12:31:13 PM PDT 24 45896703 ps
T1443 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.98317369 Apr 15 12:31:11 PM PDT 24 Apr 15 12:31:13 PM PDT 24 41030859 ps
T1444 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2759108634 Apr 15 12:31:22 PM PDT 24 Apr 15 12:31:24 PM PDT 24 26136529 ps
T1445 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2682749568 Apr 15 12:31:25 PM PDT 24 Apr 15 12:31:29 PM PDT 24 135949824 ps
T196 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2866545611 Apr 15 12:31:05 PM PDT 24 Apr 15 12:31:10 PM PDT 24 1005439667 ps
T1446 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3721298069 Apr 15 12:31:21 PM PDT 24 Apr 15 12:31:23 PM PDT 24 107231662 ps
T1447 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1750679336 Apr 15 12:31:13 PM PDT 24 Apr 15 12:31:15 PM PDT 24 97610030 ps
T1448 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3353270266 Apr 15 12:31:29 PM PDT 24 Apr 15 12:31:31 PM PDT 24 26867391 ps
T1449 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.914040700 Apr 15 12:31:25 PM PDT 24 Apr 15 12:31:28 PM PDT 24 41837826 ps
T1450 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.711076983 Apr 15 12:31:26 PM PDT 24 Apr 15 12:31:29 PM PDT 24 39246441 ps
T1451 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2167128660 Apr 15 12:31:19 PM PDT 24 Apr 15 12:31:22 PM PDT 24 66145588 ps
T1452 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1763215631 Apr 15 12:31:45 PM PDT 24 Apr 15 12:31:46 PM PDT 24 27478652 ps
T1453 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1748477351 Apr 15 12:31:11 PM PDT 24 Apr 15 12:31:14 PM PDT 24 152295296 ps
T1454 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.286386309 Apr 15 12:31:26 PM PDT 24 Apr 15 12:31:30 PM PDT 24 85222218 ps
T1455 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1089137010 Apr 15 12:31:21 PM PDT 24 Apr 15 12:31:24 PM PDT 24 157626308 ps
T1456 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.199458054 Apr 15 12:31:25 PM PDT 24 Apr 15 12:31:30 PM PDT 24 118440558 ps
T1457 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2243611932 Apr 15 12:30:59 PM PDT 24 Apr 15 12:31:02 PM PDT 24 187880759 ps
T1458 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3345583153 Apr 15 12:31:19 PM PDT 24 Apr 15 12:31:21 PM PDT 24 64003934 ps
T1459 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.4086545405 Apr 15 12:31:21 PM PDT 24 Apr 15 12:31:24 PM PDT 24 128134135 ps
T1460 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1738086164 Apr 15 12:31:26 PM PDT 24 Apr 15 12:31:29 PM PDT 24 31321840 ps
T1461 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2290850371 Apr 15 12:31:28 PM PDT 24 Apr 15 12:31:31 PM PDT 24 44482057 ps
T1462 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.501102993 Apr 15 12:31:24 PM PDT 24 Apr 15 12:31:27 PM PDT 24 65974570 ps
T1463 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2226256054 Apr 15 12:31:33 PM PDT 24 Apr 15 12:31:35 PM PDT 24 206016637 ps
T1464 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2496480139 Apr 15 12:31:00 PM PDT 24 Apr 15 12:31:02 PM PDT 24 118340200 ps
T1465 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1900382129 Apr 15 12:31:23 PM PDT 24 Apr 15 12:31:27 PM PDT 24 309023508 ps
T1466 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2633399265 Apr 15 12:30:57 PM PDT 24 Apr 15 12:30:58 PM PDT 24 61695467 ps
T1467 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.955499314 Apr 15 12:31:22 PM PDT 24 Apr 15 12:31:26 PM PDT 24 153110789 ps
T62 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1013217106 Apr 15 12:31:19 PM PDT 24 Apr 15 12:31:21 PM PDT 24 78330977 ps
T1468 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2394793452 Apr 15 12:31:23 PM PDT 24 Apr 15 12:31:27 PM PDT 24 309746952 ps
T1469 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3300465912 Apr 15 12:31:12 PM PDT 24 Apr 15 12:31:15 PM PDT 24 90289704 ps
T22 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1641556484 Apr 15 12:31:10 PM PDT 24 Apr 15 12:31:12 PM PDT 24 55278528 ps
T1470 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.317810957 Apr 15 12:31:14 PM PDT 24 Apr 15 12:31:16 PM PDT 24 90384897 ps
T1471 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3116206997 Apr 15 12:31:34 PM PDT 24 Apr 15 12:31:35 PM PDT 24 79923182 ps
T1472 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.504023131 Apr 15 12:30:58 PM PDT 24 Apr 15 12:31:00 PM PDT 24 45506352 ps
T1473 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2912533567 Apr 15 12:31:45 PM PDT 24 Apr 15 12:31:47 PM PDT 24 70006467 ps
T1474 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3289332039 Apr 15 12:31:30 PM PDT 24 Apr 15 12:31:34 PM PDT 24 333574910 ps
T1475 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.14129842 Apr 15 12:31:30 PM PDT 24 Apr 15 12:31:32 PM PDT 24 36397112 ps
T1476 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3371389219 Apr 15 12:31:42 PM PDT 24 Apr 15 12:31:43 PM PDT 24 60468261 ps
T1477 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2965140974 Apr 15 12:31:35 PM PDT 24 Apr 15 12:31:36 PM PDT 24 33937074 ps
T1478 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1260716059 Apr 15 12:31:15 PM PDT 24 Apr 15 12:31:17 PM PDT 24 85999341 ps

Test location /workspace/coverage/default/33.usbdev_smoke.3474710889
Short name T19
Test name
Test status
Simulation time 8456757301 ps
CPU time 10.28 seconds
Started Apr 15 03:16:46 PM PDT 24
Finished Apr 15 03:16:57 PM PDT 24
Peak memory 204084 kb
Host smart-5f6effbb-2a2e-4b69-8ea8-2b5d9e500eab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34747
10889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.3474710889
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.926712743
Short name T11
Test name
Test status
Simulation time 22199544219 ps
CPU time 47.39 seconds
Started Apr 15 03:17:10 PM PDT 24
Finished Apr 15 03:17:58 PM PDT 24
Peak memory 204312 kb
Host smart-ed71f173-9e49-40d7-a91a-a43b6ae782f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92671
2743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.926712743
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1985627528
Short name T63
Test name
Test status
Simulation time 43608260 ps
CPU time 0.68 seconds
Started Apr 15 12:31:24 PM PDT 24
Finished Apr 15 12:31:27 PM PDT 24
Peak memory 202820 kb
Host smart-df5d665b-a589-4ddd-bcf2-939d46447c98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1985627528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1985627528
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.4170156229
Short name T55
Test name
Test status
Simulation time 387816462 ps
CPU time 3.03 seconds
Started Apr 15 12:31:02 PM PDT 24
Finished Apr 15 12:31:05 PM PDT 24
Peak memory 203736 kb
Host smart-7f51bc06-d3d2-41ef-953f-ad71f9a8c2ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4170156229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.4170156229
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1207518115
Short name T262
Test name
Test status
Simulation time 32840629 ps
CPU time 0.67 seconds
Started Apr 15 12:31:23 PM PDT 24
Finished Apr 15 12:31:25 PM PDT 24
Peak memory 202840 kb
Host smart-895c2c53-7c0c-49d1-8606-adf4236bd6e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1207518115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.1207518115
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.2840080022
Short name T18
Test name
Test status
Simulation time 8427161310 ps
CPU time 8.54 seconds
Started Apr 15 03:18:35 PM PDT 24
Finished Apr 15 03:18:44 PM PDT 24
Peak memory 204080 kb
Host smart-7a0dc647-2d0e-44f8-bb69-2e9e9d97e36e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28400
80022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.2840080022
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.994082608
Short name T16
Test name
Test status
Simulation time 56063397 ps
CPU time 0.66 seconds
Started Apr 15 03:12:26 PM PDT 24
Finished Apr 15 03:12:27 PM PDT 24
Peak memory 203924 kb
Host smart-73cfc65a-b76b-483b-b349-56ba72f55015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99408
2608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.994082608
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2994784515
Short name T199
Test name
Test status
Simulation time 257945135 ps
CPU time 3.16 seconds
Started Apr 15 12:31:26 PM PDT 24
Finished Apr 15 12:31:31 PM PDT 24
Peak memory 203608 kb
Host smart-c81e2b32-5922-47d4-a3bd-ff6f66f5c855
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2994784515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2994784515
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3606912514
Short name T20
Test name
Test status
Simulation time 60061017 ps
CPU time 0.76 seconds
Started Apr 15 12:30:57 PM PDT 24
Finished Apr 15 12:30:58 PM PDT 24
Peak memory 203280 kb
Host smart-14078868-aab0-4cdb-8ed0-98ae0491b721
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3606912514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3606912514
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.3546875383
Short name T4
Test name
Test status
Simulation time 8445272845 ps
CPU time 7.52 seconds
Started Apr 15 03:14:58 PM PDT 24
Finished Apr 15 03:15:06 PM PDT 24
Peak memory 204072 kb
Host smart-843cca5b-2d6a-40b7-9bde-1eaac00d0fb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35468
75383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.3546875383
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.618705956
Short name T7
Test name
Test status
Simulation time 8371374230 ps
CPU time 10.03 seconds
Started Apr 15 03:10:21 PM PDT 24
Finished Apr 15 03:10:31 PM PDT 24
Peak memory 204056 kb
Host smart-db0f1825-d028-4939-aaaf-117f257aa9c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61870
5956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.618705956
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.1675568530
Short name T31
Test name
Test status
Simulation time 8445227794 ps
CPU time 10.7 seconds
Started Apr 15 03:18:09 PM PDT 24
Finished Apr 15 03:18:21 PM PDT 24
Peak memory 204048 kb
Host smart-7e461c12-a9c7-4d47-91f2-2bf14ad97ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16755
68530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.1675568530
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.363116613
Short name T53
Test name
Test status
Simulation time 63517118 ps
CPU time 1.37 seconds
Started Apr 15 03:16:40 PM PDT 24
Finished Apr 15 03:16:42 PM PDT 24
Peak memory 204124 kb
Host smart-84bd6c0d-c680-490e-a37c-a8bc186442cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36311
6613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.363116613
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2426512389
Short name T59
Test name
Test status
Simulation time 157307395 ps
CPU time 0.97 seconds
Started Apr 15 03:10:23 PM PDT 24
Finished Apr 15 03:10:25 PM PDT 24
Peak memory 220260 kb
Host smart-00a04b8a-b82f-448e-a1e5-16d1a34ad588
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2426512389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2426512389
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.810778426
Short name T264
Test name
Test status
Simulation time 43098831 ps
CPU time 0.65 seconds
Started Apr 15 12:31:55 PM PDT 24
Finished Apr 15 12:31:56 PM PDT 24
Peak memory 202724 kb
Host smart-3534a543-3ed6-4f3c-83cb-df5d8a61dd46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=810778426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.810778426
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3870948229
Short name T39
Test name
Test status
Simulation time 8401126640 ps
CPU time 7.72 seconds
Started Apr 15 03:13:32 PM PDT 24
Finished Apr 15 03:13:41 PM PDT 24
Peak memory 204044 kb
Host smart-6ff4de93-df1a-4592-9be0-21afe6835b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38709
48229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3870948229
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2595069522
Short name T252
Test name
Test status
Simulation time 32071554 ps
CPU time 0.64 seconds
Started Apr 15 12:31:16 PM PDT 24
Finished Apr 15 12:31:17 PM PDT 24
Peak memory 202880 kb
Host smart-7cc88ac9-a315-4ed0-a5a8-dfc558fc6f20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2595069522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.2595069522
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1206404788
Short name T189
Test name
Test status
Simulation time 533175772 ps
CPU time 2.54 seconds
Started Apr 15 12:31:24 PM PDT 24
Finished Apr 15 12:31:29 PM PDT 24
Peak memory 203512 kb
Host smart-4292acef-9192-4b36-954b-0e43b784f3cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1206404788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.1206404788
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1570452240
Short name T1391
Test name
Test status
Simulation time 42496263 ps
CPU time 0.66 seconds
Started Apr 15 12:31:25 PM PDT 24
Finished Apr 15 12:31:28 PM PDT 24
Peak memory 202812 kb
Host smart-2787a7a9-ba7d-415e-a80e-23e958c9736d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1570452240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1570452240
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/default/14.usbdev_enable.2491478435
Short name T51
Test name
Test status
Simulation time 8373208969 ps
CPU time 7.46 seconds
Started Apr 15 03:13:52 PM PDT 24
Finished Apr 15 03:14:00 PM PDT 24
Peak memory 204080 kb
Host smart-c995e58e-0b77-4e67-9610-5b1cd724f850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24914
78435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.2491478435
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3440285785
Short name T194
Test name
Test status
Simulation time 90634890 ps
CPU time 1.39 seconds
Started Apr 15 12:31:25 PM PDT 24
Finished Apr 15 12:31:33 PM PDT 24
Peak memory 203520 kb
Host smart-0a8588a2-0688-4a9f-a6c6-9f8cf2491057
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3440285785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3440285785
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2866545611
Short name T196
Test name
Test status
Simulation time 1005439667 ps
CPU time 4.32 seconds
Started Apr 15 12:31:05 PM PDT 24
Finished Apr 15 12:31:10 PM PDT 24
Peak memory 203640 kb
Host smart-ad93f43a-1890-45e6-9c49-71f12193fddb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2866545611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.2866545611
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.4093580218
Short name T10
Test name
Test status
Simulation time 5102424137 ps
CPU time 139.23 seconds
Started Apr 15 03:09:38 PM PDT 24
Finished Apr 15 03:11:58 PM PDT 24
Peak memory 204312 kb
Host smart-c089ab12-bcc5-4e27-8816-e2fa650c3e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40935
80218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.4093580218
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.344418546
Short name T201
Test name
Test status
Simulation time 23706076348 ps
CPU time 44 seconds
Started Apr 15 03:16:06 PM PDT 24
Finished Apr 15 03:16:51 PM PDT 24
Peak memory 204312 kb
Host smart-485e6b69-aac9-415b-b3b6-50e8d49631da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34441
8546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.344418546
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3788678996
Short name T1414
Test name
Test status
Simulation time 1975855015 ps
CPU time 6.17 seconds
Started Apr 15 12:31:25 PM PDT 24
Finished Apr 15 12:31:33 PM PDT 24
Peak memory 203484 kb
Host smart-1d9c7993-730a-49a9-80f7-0ae1d2f814c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3788678996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.3788678996
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.2162682539
Short name T42
Test name
Test status
Simulation time 27157185 ps
CPU time 0.66 seconds
Started Apr 15 03:16:43 PM PDT 24
Finished Apr 15 03:16:44 PM PDT 24
Peak memory 203908 kb
Host smart-9429d526-15e5-4207-96cf-b03af7f77b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21626
82539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.2162682539
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.3220115820
Short name T137
Test name
Test status
Simulation time 8466332443 ps
CPU time 7.69 seconds
Started Apr 15 03:13:26 PM PDT 24
Finished Apr 15 03:13:34 PM PDT 24
Peak memory 204048 kb
Host smart-2320f018-5b55-4712-b30e-e794d7c8a120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32201
15820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.3220115820
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1995031152
Short name T1424
Test name
Test status
Simulation time 120898614 ps
CPU time 1.53 seconds
Started Apr 15 12:31:49 PM PDT 24
Finished Apr 15 12:31:51 PM PDT 24
Peak memory 203540 kb
Host smart-505b2d59-6bbd-49a3-9d78-1d886ef2efa9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1995031152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1995031152
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.1939770791
Short name T180
Test name
Test status
Simulation time 8395316595 ps
CPU time 8.39 seconds
Started Apr 15 03:10:14 PM PDT 24
Finished Apr 15 03:10:23 PM PDT 24
Peak memory 204012 kb
Host smart-253ef2fe-ddac-4cfc-823a-fe2ddad1ad71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19397
70791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.1939770791
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.1444544870
Short name T171
Test name
Test status
Simulation time 8415059734 ps
CPU time 8.62 seconds
Started Apr 15 03:10:49 PM PDT 24
Finished Apr 15 03:10:57 PM PDT 24
Peak memory 204024 kb
Host smart-e154ed01-74ae-4d14-ad57-5ae2f33821b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14445
44870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.1444544870
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1878463687
Short name T625
Test name
Test status
Simulation time 8402874418 ps
CPU time 10.6 seconds
Started Apr 15 03:13:18 PM PDT 24
Finished Apr 15 03:13:29 PM PDT 24
Peak memory 204072 kb
Host smart-df02224a-048d-4153-b8b9-bf5bf7ca1a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18784
63687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1878463687
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_smoke.379153067
Short name T149
Test name
Test status
Simulation time 8465049585 ps
CPU time 8.78 seconds
Started Apr 15 03:13:41 PM PDT 24
Finished Apr 15 03:13:50 PM PDT 24
Peak memory 204008 kb
Host smart-dc93b0bc-e007-4c55-b101-d41aedc951ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37915
3067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.379153067
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.2273408178
Short name T162
Test name
Test status
Simulation time 8381393246 ps
CPU time 7.48 seconds
Started Apr 15 03:13:59 PM PDT 24
Finished Apr 15 03:14:07 PM PDT 24
Peak memory 204024 kb
Host smart-43c9eed7-9e6d-4d56-872e-23a2494eb54e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22734
08178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.2273408178
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_smoke.1473082733
Short name T918
Test name
Test status
Simulation time 8474430844 ps
CPU time 8.28 seconds
Started Apr 15 03:13:51 PM PDT 24
Finished Apr 15 03:14:00 PM PDT 24
Peak memory 204032 kb
Host smart-d97ac763-cdbe-4848-84d2-5c0a179904bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14730
82733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1473082733
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.3880104177
Short name T183
Test name
Test status
Simulation time 8470316026 ps
CPU time 9.87 seconds
Started Apr 15 03:14:19 PM PDT 24
Finished Apr 15 03:14:30 PM PDT 24
Peak memory 204048 kb
Host smart-59e9a5c7-1eb1-42b7-86de-034bc7e721b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38801
04177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.3880104177
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.524396724
Short name T145
Test name
Test status
Simulation time 8369865799 ps
CPU time 9.11 seconds
Started Apr 15 03:14:45 PM PDT 24
Finished Apr 15 03:14:55 PM PDT 24
Peak memory 204056 kb
Host smart-90d4ac4a-ef11-4b38-ad6a-4d6a182bb922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52439
6724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.524396724
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_smoke.3720175476
Short name T153
Test name
Test status
Simulation time 8458261627 ps
CPU time 9.25 seconds
Started Apr 15 03:10:59 PM PDT 24
Finished Apr 15 03:11:09 PM PDT 24
Peak memory 204020 kb
Host smart-f86522a7-92f4-4e2d-9dd8-16cc6d268c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37201
75476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.3720175476
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_smoke.567596180
Short name T79
Test name
Test status
Simulation time 8482405535 ps
CPU time 8.24 seconds
Started Apr 15 03:15:45 PM PDT 24
Finished Apr 15 03:15:54 PM PDT 24
Peak memory 204028 kb
Host smart-aeb78208-27fc-492e-84db-80df20f84377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56759
6180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.567596180
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.2229342316
Short name T71
Test name
Test status
Simulation time 8400438378 ps
CPU time 8.47 seconds
Started Apr 15 03:14:32 PM PDT 24
Finished Apr 15 03:14:41 PM PDT 24
Peak memory 204024 kb
Host smart-fded73a1-d4f3-4231-86c3-990353f6e1d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22293
42316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.2229342316
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.130684425
Short name T94
Test name
Test status
Simulation time 8423653113 ps
CPU time 8.11 seconds
Started Apr 15 03:09:50 PM PDT 24
Finished Apr 15 03:09:59 PM PDT 24
Peak memory 204044 kb
Host smart-dc2309c0-1c8d-4988-a694-318a5ffb965d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13068
4425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.130684425
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1718411279
Short name T111
Test name
Test status
Simulation time 8415866942 ps
CPU time 8.09 seconds
Started Apr 15 03:10:33 PM PDT 24
Finished Apr 15 03:10:41 PM PDT 24
Peak memory 204056 kb
Host smart-43ba4bb2-ee36-4a24-9ecc-1e2ea55681f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17184
11279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1718411279
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.881576412
Short name T550
Test name
Test status
Simulation time 8369852778 ps
CPU time 10.15 seconds
Started Apr 15 03:13:18 PM PDT 24
Finished Apr 15 03:13:29 PM PDT 24
Peak memory 204024 kb
Host smart-2307ac69-e107-489a-ab2b-075aafae2041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88157
6412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.881576412
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.4183656236
Short name T933
Test name
Test status
Simulation time 8395655390 ps
CPU time 8.61 seconds
Started Apr 15 03:13:16 PM PDT 24
Finished Apr 15 03:13:25 PM PDT 24
Peak memory 204052 kb
Host smart-1790564a-c492-45af-afd4-737193c0bfa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41836
56236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.4183656236
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_smoke.583096829
Short name T155
Test name
Test status
Simulation time 8426421897 ps
CPU time 8.58 seconds
Started Apr 15 03:13:20 PM PDT 24
Finished Apr 15 03:13:29 PM PDT 24
Peak memory 204052 kb
Host smart-f6dcbc83-9c26-471e-99e5-8526a149d459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58309
6829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.583096829
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.2570164667
Short name T598
Test name
Test status
Simulation time 8409577540 ps
CPU time 7.97 seconds
Started Apr 15 03:13:37 PM PDT 24
Finished Apr 15 03:13:45 PM PDT 24
Peak memory 204056 kb
Host smart-c8ec0be2-854e-4c35-916b-b0bfff90e044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25701
64667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.2570164667
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.3281963584
Short name T174
Test name
Test status
Simulation time 8370044457 ps
CPU time 8.2 seconds
Started Apr 15 03:13:36 PM PDT 24
Finished Apr 15 03:13:45 PM PDT 24
Peak memory 204040 kb
Host smart-ecfbb769-f7e5-4066-886e-e6d5e13b3b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32819
63584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.3281963584
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.1662012626
Short name T723
Test name
Test status
Simulation time 8411986418 ps
CPU time 8.28 seconds
Started Apr 15 03:13:28 PM PDT 24
Finished Apr 15 03:13:36 PM PDT 24
Peak memory 203988 kb
Host smart-68423c09-de36-40e0-bd27-25c7b0307742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16620
12626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.1662012626
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.1748744144
Short name T100
Test name
Test status
Simulation time 8416604312 ps
CPU time 7.4 seconds
Started Apr 15 03:13:35 PM PDT 24
Finished Apr 15 03:13:44 PM PDT 24
Peak memory 204028 kb
Host smart-d6575a63-41ae-44bc-a993-f8fdd512af04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17487
44144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.1748744144
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.3328078921
Short name T973
Test name
Test status
Simulation time 8361840346 ps
CPU time 7.19 seconds
Started Apr 15 03:13:50 PM PDT 24
Finished Apr 15 03:13:58 PM PDT 24
Peak memory 204048 kb
Host smart-4c803a92-3d5a-4c86-b9d6-6b1509404726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33280
78921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.3328078921
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.3852309086
Short name T745
Test name
Test status
Simulation time 8426817482 ps
CPU time 7.71 seconds
Started Apr 15 03:13:59 PM PDT 24
Finished Apr 15 03:14:07 PM PDT 24
Peak memory 204048 kb
Host smart-efc4192e-8dee-477a-8a7b-7c0ec7d05469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38523
09086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3852309086
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.623148361
Short name T1070
Test name
Test status
Simulation time 8370137057 ps
CPU time 7.79 seconds
Started Apr 15 03:14:32 PM PDT 24
Finished Apr 15 03:14:40 PM PDT 24
Peak memory 203996 kb
Host smart-4723e3e1-6ff5-452e-acfd-2a87e5f33dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62314
8361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.623148361
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.930234933
Short name T127
Test name
Test status
Simulation time 8410044533 ps
CPU time 7.89 seconds
Started Apr 15 03:14:30 PM PDT 24
Finished Apr 15 03:14:38 PM PDT 24
Peak memory 204060 kb
Host smart-3d895e9c-596e-4f1e-893f-d8cf302310c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93023
4933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.930234933
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.441365837
Short name T370
Test name
Test status
Simulation time 8381104337 ps
CPU time 9.2 seconds
Started Apr 15 03:14:31 PM PDT 24
Finished Apr 15 03:14:41 PM PDT 24
Peak memory 204048 kb
Host smart-285319a0-5873-46d8-8428-f37b8f925cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44136
5837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.441365837
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.3326370376
Short name T84
Test name
Test status
Simulation time 8436547443 ps
CPU time 8.36 seconds
Started Apr 15 03:14:34 PM PDT 24
Finished Apr 15 03:14:42 PM PDT 24
Peak memory 204028 kb
Host smart-db8650a9-c75e-4a7f-950a-e4e62cb221ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33263
70376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.3326370376
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.4197573707
Short name T1174
Test name
Test status
Simulation time 8435697572 ps
CPU time 7.64 seconds
Started Apr 15 03:14:41 PM PDT 24
Finished Apr 15 03:14:49 PM PDT 24
Peak memory 204024 kb
Host smart-7ceb0062-1b59-4be6-a4c5-257ce72a4c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41975
73707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.4197573707
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.214501746
Short name T93
Test name
Test status
Simulation time 8446893589 ps
CPU time 7.99 seconds
Started Apr 15 03:14:44 PM PDT 24
Finished Apr 15 03:14:52 PM PDT 24
Peak memory 204048 kb
Host smart-cdac370f-23a5-45da-b7fb-e034d9cf52c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21450
1746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.214501746
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.34286799
Short name T113
Test name
Test status
Simulation time 8409059052 ps
CPU time 8.08 seconds
Started Apr 15 03:14:52 PM PDT 24
Finished Apr 15 03:15:00 PM PDT 24
Peak memory 204036 kb
Host smart-cd7a060d-b864-40a8-b7a1-85e9c62223f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34286
799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.34286799
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.2341235120
Short name T107
Test name
Test status
Simulation time 8414404706 ps
CPU time 8.02 seconds
Started Apr 15 03:15:05 PM PDT 24
Finished Apr 15 03:15:14 PM PDT 24
Peak memory 204204 kb
Host smart-58c8acaa-f411-4bec-9820-175130c48063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23412
35120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.2341235120
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.2582726320
Short name T97
Test name
Test status
Simulation time 8427237739 ps
CPU time 8.75 seconds
Started Apr 15 03:15:24 PM PDT 24
Finished Apr 15 03:15:33 PM PDT 24
Peak memory 204060 kb
Host smart-e56cca9f-54c6-4062-ad13-2471b4a3b886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25827
26320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2582726320
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2265781946
Short name T108
Test name
Test status
Simulation time 8408402151 ps
CPU time 7.92 seconds
Started Apr 15 03:16:26 PM PDT 24
Finished Apr 15 03:16:34 PM PDT 24
Peak memory 204052 kb
Host smart-f52a14e6-2cc0-4922-af78-671a87651be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22657
81946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2265781946
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.4120417477
Short name T103
Test name
Test status
Simulation time 8444283544 ps
CPU time 10.53 seconds
Started Apr 15 03:18:20 PM PDT 24
Finished Apr 15 03:18:31 PM PDT 24
Peak memory 204044 kb
Host smart-8d4554a2-cc69-481d-b0cf-de2f18550264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41204
17477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.4120417477
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2496480139
Short name T1464
Test name
Test status
Simulation time 118340200 ps
CPU time 2.02 seconds
Started Apr 15 12:31:00 PM PDT 24
Finished Apr 15 12:31:02 PM PDT 24
Peak memory 203532 kb
Host smart-71405b4a-17c8-4dcb-a2f5-f282e4eb7f66
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2496480139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2496480139
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1831581313
Short name T240
Test name
Test status
Simulation time 1172850431 ps
CPU time 8.53 seconds
Started Apr 15 12:31:00 PM PDT 24
Finished Apr 15 12:31:09 PM PDT 24
Peak memory 203644 kb
Host smart-9cbe5b8c-0301-45a4-bd24-d0787bbac2f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1831581313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1831581313
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2420436048
Short name T250
Test name
Test status
Simulation time 100612454 ps
CPU time 1.39 seconds
Started Apr 15 12:31:17 PM PDT 24
Finished Apr 15 12:31:19 PM PDT 24
Peak memory 211812 kb
Host smart-d7960e74-3840-4b7d-8e73-293d5428de08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420436048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.2420436048
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2633399265
Short name T1466
Test name
Test status
Simulation time 61695467 ps
CPU time 0.98 seconds
Started Apr 15 12:30:57 PM PDT 24
Finished Apr 15 12:30:58 PM PDT 24
Peak memory 203556 kb
Host smart-28ac0deb-62fc-431d-92df-751a75fd4dfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2633399265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2633399265
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.504023131
Short name T1472
Test name
Test status
Simulation time 45506352 ps
CPU time 0.69 seconds
Started Apr 15 12:30:58 PM PDT 24
Finished Apr 15 12:31:00 PM PDT 24
Peak memory 202784 kb
Host smart-e7fb10fc-c636-4449-9357-148db51254d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=504023131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.504023131
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2243611932
Short name T1457
Test name
Test status
Simulation time 187880759 ps
CPU time 2.23 seconds
Started Apr 15 12:30:59 PM PDT 24
Finished Apr 15 12:31:02 PM PDT 24
Peak memory 211832 kb
Host smart-22c40d3a-ed3f-4daf-a6bb-c628d0a0601a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2243611932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2243611932
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3287031036
Short name T1385
Test name
Test status
Simulation time 719552520 ps
CPU time 4.58 seconds
Started Apr 15 12:30:58 PM PDT 24
Finished Apr 15 12:31:03 PM PDT 24
Peak memory 203500 kb
Host smart-647e7e72-fcf6-43a9-bfbe-8cd20c167d82
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3287031036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3287031036
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2051227567
Short name T1420
Test name
Test status
Simulation time 69279548 ps
CPU time 1.36 seconds
Started Apr 15 12:31:15 PM PDT 24
Finished Apr 15 12:31:17 PM PDT 24
Peak memory 203560 kb
Host smart-55c97e72-e532-4863-bdc0-bb6f7591c014
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2051227567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.2051227567
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2292342283
Short name T193
Test name
Test status
Simulation time 91224811 ps
CPU time 2.31 seconds
Started Apr 15 12:30:58 PM PDT 24
Finished Apr 15 12:31:01 PM PDT 24
Peak memory 203628 kb
Host smart-cb8c1c32-df3d-4710-b32a-e111abbcbaba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2292342283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2292342283
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1748477351
Short name T1453
Test name
Test status
Simulation time 152295296 ps
CPU time 2.1 seconds
Started Apr 15 12:31:11 PM PDT 24
Finished Apr 15 12:31:14 PM PDT 24
Peak memory 203520 kb
Host smart-e699b126-1373-4ec4-be98-6e7a10997915
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1748477351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1748477351
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1764548119
Short name T1439
Test name
Test status
Simulation time 879466170 ps
CPU time 5.23 seconds
Started Apr 15 12:31:08 PM PDT 24
Finished Apr 15 12:31:14 PM PDT 24
Peak memory 203636 kb
Host smart-1311ba82-5b45-4476-b939-6fd47b631b6e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1764548119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1764548119
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1641556484
Short name T22
Test name
Test status
Simulation time 55278528 ps
CPU time 0.88 seconds
Started Apr 15 12:31:10 PM PDT 24
Finished Apr 15 12:31:12 PM PDT 24
Peak memory 203216 kb
Host smart-33964263-c7ee-4db7-8ccb-cda8e1ba8dfb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1641556484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.1641556484
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3714605541
Short name T1419
Test name
Test status
Simulation time 146111164 ps
CPU time 1.21 seconds
Started Apr 15 12:31:21 PM PDT 24
Finished Apr 15 12:31:24 PM PDT 24
Peak memory 211884 kb
Host smart-8461e596-dada-4ea0-8c7d-a59b6ac6d61e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714605541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.3714605541
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3703421326
Short name T1384
Test name
Test status
Simulation time 103434333 ps
CPU time 0.82 seconds
Started Apr 15 12:31:19 PM PDT 24
Finished Apr 15 12:31:20 PM PDT 24
Peak memory 203364 kb
Host smart-c360258c-8374-414a-9c1f-2cba2b9a46de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3703421326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.3703421326
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2290636385
Short name T1394
Test name
Test status
Simulation time 34063738 ps
CPU time 0.66 seconds
Started Apr 15 12:31:21 PM PDT 24
Finished Apr 15 12:31:23 PM PDT 24
Peak memory 202748 kb
Host smart-d055d680-1796-4860-a482-8e56f45ac96a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2290636385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2290636385
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1609427738
Short name T241
Test name
Test status
Simulation time 189592521 ps
CPU time 2.22 seconds
Started Apr 15 12:31:14 PM PDT 24
Finished Apr 15 12:31:17 PM PDT 24
Peak memory 211812 kb
Host smart-9f09beaf-3600-4d86-a375-8f4bb999ac4d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1609427738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1609427738
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2143977432
Short name T1390
Test name
Test status
Simulation time 92510665 ps
CPU time 2.17 seconds
Started Apr 15 12:31:21 PM PDT 24
Finished Apr 15 12:31:24 PM PDT 24
Peak memory 203540 kb
Host smart-a7fb3361-00af-4d84-8eba-4abda5bdd3df
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2143977432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2143977432
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2040479280
Short name T247
Test name
Test status
Simulation time 49861845 ps
CPU time 1.06 seconds
Started Apr 15 12:31:07 PM PDT 24
Finished Apr 15 12:31:09 PM PDT 24
Peak memory 203628 kb
Host smart-bb7d55d5-d7a1-4729-b5af-10ec54f1b10a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2040479280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2040479280
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.541618212
Short name T1387
Test name
Test status
Simulation time 133000545 ps
CPU time 1.63 seconds
Started Apr 15 12:31:05 PM PDT 24
Finished Apr 15 12:31:07 PM PDT 24
Peak memory 203624 kb
Host smart-516cca37-80f0-4a67-9bad-2edacccb9c8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=541618212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.541618212
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.287393005
Short name T1398
Test name
Test status
Simulation time 175145517 ps
CPU time 1.3 seconds
Started Apr 15 12:31:27 PM PDT 24
Finished Apr 15 12:31:30 PM PDT 24
Peak memory 211872 kb
Host smart-789792d6-4d5c-41d2-af21-797503955726
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287393005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbde
v_csr_mem_rw_with_rand_reset.287393005
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3345583153
Short name T1458
Test name
Test status
Simulation time 64003934 ps
CPU time 0.96 seconds
Started Apr 15 12:31:19 PM PDT 24
Finished Apr 15 12:31:21 PM PDT 24
Peak memory 203576 kb
Host smart-024e30e0-d1e5-44cb-bd47-a238a27abb26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3345583153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3345583153
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3820290913
Short name T68
Test name
Test status
Simulation time 36008365 ps
CPU time 0.68 seconds
Started Apr 15 12:31:22 PM PDT 24
Finished Apr 15 12:31:23 PM PDT 24
Peak memory 202752 kb
Host smart-858a68cb-f6bd-439a-a47d-c4e3d804d3fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3820290913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.3820290913
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2226256054
Short name T1463
Test name
Test status
Simulation time 206016637 ps
CPU time 1.7 seconds
Started Apr 15 12:31:33 PM PDT 24
Finished Apr 15 12:31:35 PM PDT 24
Peak memory 203612 kb
Host smart-6a7ed581-5235-4181-a05e-fd543ddcb9d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2226256054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2226256054
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2394793452
Short name T1468
Test name
Test status
Simulation time 309746952 ps
CPU time 2.68 seconds
Started Apr 15 12:31:23 PM PDT 24
Finished Apr 15 12:31:27 PM PDT 24
Peak memory 203564 kb
Host smart-a1d69ecf-78f9-4acb-be4e-387000f4c0a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2394793452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2394793452
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1159317712
Short name T195
Test name
Test status
Simulation time 135625773 ps
CPU time 2.11 seconds
Started Apr 15 12:31:26 PM PDT 24
Finished Apr 15 12:31:30 PM PDT 24
Peak memory 211780 kb
Host smart-b3beaaff-8310-474a-a3d8-29c6c7c87466
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159317712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.1159317712
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1533901466
Short name T248
Test name
Test status
Simulation time 99109724 ps
CPU time 0.87 seconds
Started Apr 15 12:31:23 PM PDT 24
Finished Apr 15 12:31:25 PM PDT 24
Peak memory 203284 kb
Host smart-80894d11-c25f-49f0-9f57-e335a7a85313
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1533901466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.1533901466
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2759108634
Short name T1444
Test name
Test status
Simulation time 26136529 ps
CPU time 0.68 seconds
Started Apr 15 12:31:22 PM PDT 24
Finished Apr 15 12:31:24 PM PDT 24
Peak memory 202708 kb
Host smart-8b55ecfc-33f3-47ef-ac4e-86ea8edf2412
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2759108634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2759108634
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1034919587
Short name T1383
Test name
Test status
Simulation time 61723931 ps
CPU time 0.96 seconds
Started Apr 15 12:31:22 PM PDT 24
Finished Apr 15 12:31:25 PM PDT 24
Peak memory 203636 kb
Host smart-fe73fbc2-6b82-49f9-80d3-f90cf88ee728
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1034919587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.1034919587
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.4234231799
Short name T197
Test name
Test status
Simulation time 67168676 ps
CPU time 1.86 seconds
Started Apr 15 12:31:27 PM PDT 24
Finished Apr 15 12:31:31 PM PDT 24
Peak memory 203640 kb
Host smart-17645a4b-cb2f-4059-867a-51ffe45bdd1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4234231799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.4234231799
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.271809996
Short name T258
Test name
Test status
Simulation time 429995337 ps
CPU time 2.49 seconds
Started Apr 15 12:31:23 PM PDT 24
Finished Apr 15 12:31:27 PM PDT 24
Peak memory 203648 kb
Host smart-869175bc-a7c4-4706-a623-2395be33f758
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=271809996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.271809996
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4079660988
Short name T57
Test name
Test status
Simulation time 111618166 ps
CPU time 1.3 seconds
Started Apr 15 12:31:21 PM PDT 24
Finished Apr 15 12:31:23 PM PDT 24
Peak memory 213084 kb
Host smart-87077481-31f8-4816-aea4-ba7a18889226
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079660988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.4079660988
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2368108889
Short name T244
Test name
Test status
Simulation time 41046672 ps
CPU time 0.79 seconds
Started Apr 15 12:31:27 PM PDT 24
Finished Apr 15 12:31:30 PM PDT 24
Peak memory 203272 kb
Host smart-56f6eeb5-7c13-42aa-b89f-ae6f7d9a9986
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2368108889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.2368108889
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.18756678
Short name T1382
Test name
Test status
Simulation time 47572922 ps
CPU time 0.68 seconds
Started Apr 15 12:31:24 PM PDT 24
Finished Apr 15 12:31:27 PM PDT 24
Peak memory 202744 kb
Host smart-3bb14f32-ba6a-47ab-92e6-e2c046118180
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=18756678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.18756678
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2682749568
Short name T1445
Test name
Test status
Simulation time 135949824 ps
CPU time 1.64 seconds
Started Apr 15 12:31:25 PM PDT 24
Finished Apr 15 12:31:29 PM PDT 24
Peak memory 203712 kb
Host smart-c994d80a-4704-4689-8330-f1ae00d6dfc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2682749568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2682749568
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.492415534
Short name T1399
Test name
Test status
Simulation time 167943290 ps
CPU time 2.27 seconds
Started Apr 15 12:31:25 PM PDT 24
Finished Apr 15 12:31:29 PM PDT 24
Peak memory 203512 kb
Host smart-69aea12a-1fa9-4c6f-9ddb-ddfcbc3e0178
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=492415534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.492415534
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.955499314
Short name T1467
Test name
Test status
Simulation time 153110789 ps
CPU time 1.84 seconds
Started Apr 15 12:31:22 PM PDT 24
Finished Apr 15 12:31:26 PM PDT 24
Peak memory 211880 kb
Host smart-f6c81497-5824-4a60-be95-055b86037a61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955499314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbde
v_csr_mem_rw_with_rand_reset.955499314
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2047727265
Short name T238
Test name
Test status
Simulation time 37131313 ps
CPU time 0.81 seconds
Started Apr 15 12:31:19 PM PDT 24
Finished Apr 15 12:31:21 PM PDT 24
Peak memory 203312 kb
Host smart-edda50a7-5400-4fbe-842b-ca88a554168e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2047727265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2047727265
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1900382129
Short name T1465
Test name
Test status
Simulation time 309023508 ps
CPU time 1.7 seconds
Started Apr 15 12:31:23 PM PDT 24
Finished Apr 15 12:31:27 PM PDT 24
Peak memory 203584 kb
Host smart-0501901f-1ff9-4e4d-8e14-90e26e37ed27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1900382129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1900382129
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4230062561
Short name T1435
Test name
Test status
Simulation time 285884958 ps
CPU time 2.94 seconds
Started Apr 15 12:31:53 PM PDT 24
Finished Apr 15 12:31:56 PM PDT 24
Peak memory 211756 kb
Host smart-56bc1676-d24f-4bd7-a33c-2af106cfd2c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4230062561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.4230062561
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.546230855
Short name T259
Test name
Test status
Simulation time 509943853 ps
CPU time 2.91 seconds
Started Apr 15 12:31:23 PM PDT 24
Finished Apr 15 12:31:27 PM PDT 24
Peak memory 203644 kb
Host smart-9074004f-7307-4807-9c8b-64ab10171912
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=546230855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.546230855
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3584268326
Short name T216
Test name
Test status
Simulation time 149524676 ps
CPU time 1.79 seconds
Started Apr 15 12:31:24 PM PDT 24
Finished Apr 15 12:31:27 PM PDT 24
Peak memory 214952 kb
Host smart-7b8430ad-14d6-4d9b-9a31-3a5d1af3b98c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584268326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.3584268326
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3971515028
Short name T190
Test name
Test status
Simulation time 36844519 ps
CPU time 0.91 seconds
Started Apr 15 12:31:19 PM PDT 24
Finished Apr 15 12:31:20 PM PDT 24
Peak memory 203468 kb
Host smart-e5531015-b026-43b0-91c6-2c3a5256965a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3971515028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3971515028
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3915548511
Short name T273
Test name
Test status
Simulation time 34559201 ps
CPU time 0.67 seconds
Started Apr 15 12:31:26 PM PDT 24
Finished Apr 15 12:31:29 PM PDT 24
Peak memory 202872 kb
Host smart-75564d8a-9e58-44e2-93b1-5e5e8beef268
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3915548511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3915548511
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3648552903
Short name T61
Test name
Test status
Simulation time 116062423 ps
CPU time 1.53 seconds
Started Apr 15 12:31:19 PM PDT 24
Finished Apr 15 12:31:22 PM PDT 24
Peak memory 203504 kb
Host smart-34dd5931-77c4-4c25-94fb-bde544630f9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3648552903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.3648552903
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3321481770
Short name T218
Test name
Test status
Simulation time 551866188 ps
CPU time 4.37 seconds
Started Apr 15 12:31:25 PM PDT 24
Finished Apr 15 12:31:31 PM PDT 24
Peak memory 203512 kb
Host smart-00fe37bf-be2b-4e2d-ba81-164ef45eca3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3321481770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3321481770
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1732537106
Short name T1413
Test name
Test status
Simulation time 68255193 ps
CPU time 1.14 seconds
Started Apr 15 12:31:24 PM PDT 24
Finished Apr 15 12:31:27 PM PDT 24
Peak memory 211712 kb
Host smart-c11c1935-4dae-4eea-ad86-7e1e656fd997
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732537106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.1732537106
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.914040700
Short name T1449
Test name
Test status
Simulation time 41837826 ps
CPU time 0.8 seconds
Started Apr 15 12:31:25 PM PDT 24
Finished Apr 15 12:31:28 PM PDT 24
Peak memory 203292 kb
Host smart-6ff9bbe1-0cbb-4342-8de2-3ad32b9a12b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=914040700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.914040700
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1263436550
Short name T1417
Test name
Test status
Simulation time 29014074 ps
CPU time 0.69 seconds
Started Apr 15 12:31:25 PM PDT 24
Finished Apr 15 12:31:28 PM PDT 24
Peak memory 202808 kb
Host smart-388dee5e-27a9-4327-9145-cad1f7efd6b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1263436550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1263436550
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3208252910
Short name T1429
Test name
Test status
Simulation time 269501493 ps
CPU time 1.48 seconds
Started Apr 15 12:31:24 PM PDT 24
Finished Apr 15 12:31:27 PM PDT 24
Peak memory 203600 kb
Host smart-2e4df8e8-afc9-44f7-8eb2-d5d13c8a1768
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3208252910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.3208252910
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2393076095
Short name T217
Test name
Test status
Simulation time 53137548 ps
CPU time 1.46 seconds
Started Apr 15 12:31:25 PM PDT 24
Finished Apr 15 12:31:29 PM PDT 24
Peak memory 203692 kb
Host smart-2b8af0b6-5bb5-441b-a99a-f478290d28e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2393076095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2393076095
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3721298069
Short name T1446
Test name
Test status
Simulation time 107231662 ps
CPU time 1.24 seconds
Started Apr 15 12:31:21 PM PDT 24
Finished Apr 15 12:31:23 PM PDT 24
Peak memory 211932 kb
Host smart-a82b96b7-9fb2-4d27-b92a-06de1c82b1ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721298069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.3721298069
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3829762379
Short name T1440
Test name
Test status
Simulation time 87899337 ps
CPU time 1.05 seconds
Started Apr 15 12:31:29 PM PDT 24
Finished Apr 15 12:31:32 PM PDT 24
Peak memory 203536 kb
Host smart-6d9af7d5-0ec0-41e3-b86b-cc3c5abac850
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3829762379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3829762379
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1587589321
Short name T274
Test name
Test status
Simulation time 32180876 ps
CPU time 0.66 seconds
Started Apr 15 12:31:23 PM PDT 24
Finished Apr 15 12:31:26 PM PDT 24
Peak memory 202776 kb
Host smart-c4fe0127-f3ec-41cb-b7f5-04f93c1504eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1587589321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1587589321
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1263553913
Short name T1407
Test name
Test status
Simulation time 44247051 ps
CPU time 0.99 seconds
Started Apr 15 12:31:23 PM PDT 24
Finished Apr 15 12:31:26 PM PDT 24
Peak memory 203540 kb
Host smart-d50a6854-a558-4a3c-80ff-0f9aea9d32a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1263553913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.1263553913
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.199458054
Short name T1456
Test name
Test status
Simulation time 118440558 ps
CPU time 2.9 seconds
Started Apr 15 12:31:25 PM PDT 24
Finished Apr 15 12:31:30 PM PDT 24
Peak memory 203544 kb
Host smart-d00b9572-63eb-4654-a21f-1d7ba05a4bee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=199458054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.199458054
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.775148887
Short name T214
Test name
Test status
Simulation time 170185891 ps
CPU time 1.73 seconds
Started Apr 15 12:31:22 PM PDT 24
Finished Apr 15 12:31:25 PM PDT 24
Peak memory 211924 kb
Host smart-d34f8f57-8832-4e85-b525-7d3388b8a817
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775148887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbde
v_csr_mem_rw_with_rand_reset.775148887
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1394092789
Short name T1388
Test name
Test status
Simulation time 31175209 ps
CPU time 0.94 seconds
Started Apr 15 12:31:27 PM PDT 24
Finished Apr 15 12:31:30 PM PDT 24
Peak memory 203512 kb
Host smart-7e286d66-0f3e-41c8-9df7-12c863ae84e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1394092789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.1394092789
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.4136145043
Short name T266
Test name
Test status
Simulation time 34485935 ps
CPU time 0.64 seconds
Started Apr 15 12:31:23 PM PDT 24
Finished Apr 15 12:31:26 PM PDT 24
Peak memory 202872 kb
Host smart-caa0008f-e284-4aa1-8b37-5c143517333e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4136145043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.4136145043
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2509131527
Short name T1404
Test name
Test status
Simulation time 154818736 ps
CPU time 1.29 seconds
Started Apr 15 12:31:21 PM PDT 24
Finished Apr 15 12:31:23 PM PDT 24
Peak memory 203596 kb
Host smart-e25c8f6e-5ed2-45bf-8432-9d248a5ec3cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2509131527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.2509131527
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3463186636
Short name T213
Test name
Test status
Simulation time 333189770 ps
CPU time 3.11 seconds
Started Apr 15 12:31:22 PM PDT 24
Finished Apr 15 12:31:26 PM PDT 24
Peak memory 203744 kb
Host smart-c8cecedc-96f3-41e3-a7df-441376469e5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3463186636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3463186636
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3488716067
Short name T256
Test name
Test status
Simulation time 516045072 ps
CPU time 2.61 seconds
Started Apr 15 12:31:26 PM PDT 24
Finished Apr 15 12:31:31 PM PDT 24
Peak memory 203648 kb
Host smart-9b34dc48-7c4a-4f7e-af6c-70e99c4466ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3488716067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3488716067
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2244445734
Short name T188
Test name
Test status
Simulation time 84882558 ps
CPU time 2.28 seconds
Started Apr 15 12:31:47 PM PDT 24
Finished Apr 15 12:31:50 PM PDT 24
Peak memory 211852 kb
Host smart-67d3d645-3cd0-4caf-a431-d4ff81e78157
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244445734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2244445734
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3116206997
Short name T1471
Test name
Test status
Simulation time 79923182 ps
CPU time 0.97 seconds
Started Apr 15 12:31:34 PM PDT 24
Finished Apr 15 12:31:35 PM PDT 24
Peak memory 203532 kb
Host smart-c37aa9ca-c59b-43c2-9647-44f043a6a83c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3116206997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3116206997
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2398878217
Short name T1428
Test name
Test status
Simulation time 31233683 ps
CPU time 0.65 seconds
Started Apr 15 12:31:28 PM PDT 24
Finished Apr 15 12:31:30 PM PDT 24
Peak memory 202708 kb
Host smart-3a066d18-04b8-40a9-a042-3fa0e81bc7b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2398878217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.2398878217
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.4086545405
Short name T1459
Test name
Test status
Simulation time 128134135 ps
CPU time 1.48 seconds
Started Apr 15 12:31:21 PM PDT 24
Finished Apr 15 12:31:24 PM PDT 24
Peak memory 203612 kb
Host smart-f7b803fd-a94a-436f-a664-e7bb783f5efe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4086545405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.4086545405
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.492482022
Short name T211
Test name
Test status
Simulation time 67878186 ps
CPU time 1.68 seconds
Started Apr 15 12:31:27 PM PDT 24
Finished Apr 15 12:31:31 PM PDT 24
Peak memory 203572 kb
Host smart-32b19604-9242-4827-8951-7412be7d8e13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=492482022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.492482022
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3289332039
Short name T1474
Test name
Test status
Simulation time 333574910 ps
CPU time 2.39 seconds
Started Apr 15 12:31:30 PM PDT 24
Finished Apr 15 12:31:34 PM PDT 24
Peak memory 203592 kb
Host smart-42efc4cf-ffc7-4581-bc51-9c575850cf3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3289332039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3289332039
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2912533567
Short name T1473
Test name
Test status
Simulation time 70006467 ps
CPU time 1.61 seconds
Started Apr 15 12:31:45 PM PDT 24
Finished Apr 15 12:31:47 PM PDT 24
Peak memory 211864 kb
Host smart-9f2f2726-67d5-403f-968e-c3136999a676
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912533567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.2912533567
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.203169805
Short name T1436
Test name
Test status
Simulation time 38460079 ps
CPU time 0.77 seconds
Started Apr 15 12:31:24 PM PDT 24
Finished Apr 15 12:31:27 PM PDT 24
Peak memory 203328 kb
Host smart-844cdbde-7075-4881-84ef-e7a36496aee1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=203169805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.203169805
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.775902246
Short name T253
Test name
Test status
Simulation time 38694838 ps
CPU time 0.67 seconds
Started Apr 15 12:31:24 PM PDT 24
Finished Apr 15 12:31:26 PM PDT 24
Peak memory 202748 kb
Host smart-2b8b0aa9-c68b-43bd-8727-6f74935b6eef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=775902246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.775902246
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3121043164
Short name T1411
Test name
Test status
Simulation time 93402996 ps
CPU time 1.45 seconds
Started Apr 15 12:31:39 PM PDT 24
Finished Apr 15 12:31:41 PM PDT 24
Peak memory 203600 kb
Host smart-193cfe33-d848-422d-b8aa-3f684540c9fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3121043164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.3121043164
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1641467397
Short name T1416
Test name
Test status
Simulation time 188383832 ps
CPU time 2.45 seconds
Started Apr 15 12:31:21 PM PDT 24
Finished Apr 15 12:31:24 PM PDT 24
Peak memory 211860 kb
Host smart-8185b854-d9d0-4426-9c98-09eff410391d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1641467397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1641467397
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.856836722
Short name T198
Test name
Test status
Simulation time 308654062 ps
CPU time 2.79 seconds
Started Apr 15 12:31:17 PM PDT 24
Finished Apr 15 12:31:21 PM PDT 24
Peak memory 203520 kb
Host smart-6da53db0-73fc-4390-801f-5a3a7074c270
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=856836722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.856836722
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3946129051
Short name T243
Test name
Test status
Simulation time 165290641 ps
CPU time 2.18 seconds
Started Apr 15 12:31:18 PM PDT 24
Finished Apr 15 12:31:21 PM PDT 24
Peak memory 203536 kb
Host smart-8bef9419-b35b-4bce-8d0c-82f1d4ad5d0a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3946129051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3946129051
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.4104250596
Short name T242
Test name
Test status
Simulation time 1442848197 ps
CPU time 8.43 seconds
Started Apr 15 12:31:17 PM PDT 24
Finished Apr 15 12:31:26 PM PDT 24
Peak memory 203532 kb
Host smart-b74be919-f8e2-4027-8eb1-10fec59acb50
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4104250596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.4104250596
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3569137492
Short name T21
Test name
Test status
Simulation time 72177625 ps
CPU time 0.87 seconds
Started Apr 15 12:31:23 PM PDT 24
Finished Apr 15 12:31:26 PM PDT 24
Peak memory 203264 kb
Host smart-e0b3b3f3-be64-4a9f-8df2-be021cf74c86
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3569137492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3569137492
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2384269812
Short name T251
Test name
Test status
Simulation time 162190906 ps
CPU time 1.83 seconds
Started Apr 15 12:31:21 PM PDT 24
Finished Apr 15 12:31:24 PM PDT 24
Peak memory 211868 kb
Host smart-cd786cc7-9b3e-4c42-b7b6-ffbfd7023277
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384269812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.2384269812
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2855180765
Short name T255
Test name
Test status
Simulation time 46644412 ps
CPU time 0.81 seconds
Started Apr 15 12:31:21 PM PDT 24
Finished Apr 15 12:31:23 PM PDT 24
Peak memory 203224 kb
Host smart-84ed2e36-3a23-467a-a299-83f90ada943f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2855180765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2855180765
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3758480453
Short name T267
Test name
Test status
Simulation time 40260386 ps
CPU time 0.64 seconds
Started Apr 15 12:31:18 PM PDT 24
Finished Apr 15 12:31:19 PM PDT 24
Peak memory 202780 kb
Host smart-35c523ba-9a78-40d5-9ae6-38e8501248ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3758480453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3758480453
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2482550569
Short name T235
Test name
Test status
Simulation time 192453751 ps
CPU time 2.38 seconds
Started Apr 15 12:31:13 PM PDT 24
Finished Apr 15 12:31:16 PM PDT 24
Peak memory 211724 kb
Host smart-aeb53d7a-339f-4c0c-a985-c9166554b569
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2482550569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2482550569
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.4179125606
Short name T1386
Test name
Test status
Simulation time 604457091 ps
CPU time 4.37 seconds
Started Apr 15 12:31:18 PM PDT 24
Finished Apr 15 12:31:23 PM PDT 24
Peak memory 203480 kb
Host smart-282c9f0a-8d55-4aa5-93cc-fde90527c83a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4179125606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.4179125606
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3621794105
Short name T245
Test name
Test status
Simulation time 161397494 ps
CPU time 1.58 seconds
Started Apr 15 12:31:13 PM PDT 24
Finished Apr 15 12:31:15 PM PDT 24
Peak memory 203540 kb
Host smart-c36cb002-b717-4464-af09-913f29ac9bf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3621794105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.3621794105
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2527148334
Short name T210
Test name
Test status
Simulation time 101538274 ps
CPU time 2.89 seconds
Started Apr 15 12:31:20 PM PDT 24
Finished Apr 15 12:31:23 PM PDT 24
Peak memory 203564 kb
Host smart-57bcaa60-9b79-46d1-a6a2-30ba90bf5c99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2527148334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2527148334
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.453943715
Short name T1415
Test name
Test status
Simulation time 300156665 ps
CPU time 2.48 seconds
Started Apr 15 12:31:20 PM PDT 24
Finished Apr 15 12:31:23 PM PDT 24
Peak memory 203580 kb
Host smart-bac6fb49-77a7-4fc4-9ba0-0bd9a1a1aecc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=453943715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.453943715
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2231560754
Short name T1406
Test name
Test status
Simulation time 37751796 ps
CPU time 0.63 seconds
Started Apr 15 12:31:15 PM PDT 24
Finished Apr 15 12:31:16 PM PDT 24
Peak memory 202868 kb
Host smart-fcf5fdae-43d1-4e2e-9137-04874b8b849c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2231560754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2231560754
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.125714623
Short name T1441
Test name
Test status
Simulation time 32612502 ps
CPU time 0.7 seconds
Started Apr 15 12:31:27 PM PDT 24
Finished Apr 15 12:31:29 PM PDT 24
Peak memory 202776 kb
Host smart-6f503636-9b90-425a-96e9-40e93ed5cf85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=125714623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.125714623
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2290850371
Short name T1461
Test name
Test status
Simulation time 44482057 ps
CPU time 0.68 seconds
Started Apr 15 12:31:28 PM PDT 24
Finished Apr 15 12:31:31 PM PDT 24
Peak memory 202776 kb
Host smart-710acd98-7376-443c-9b2f-ad9335b52b64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2290850371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2290850371
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.4164385886
Short name T1392
Test name
Test status
Simulation time 36478066 ps
CPU time 0.64 seconds
Started Apr 15 12:31:24 PM PDT 24
Finished Apr 15 12:31:26 PM PDT 24
Peak memory 202836 kb
Host smart-1182b956-4b2d-458b-81d9-76a0f48bb9d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4164385886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.4164385886
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.711076983
Short name T1450
Test name
Test status
Simulation time 39246441 ps
CPU time 0.69 seconds
Started Apr 15 12:31:26 PM PDT 24
Finished Apr 15 12:31:29 PM PDT 24
Peak memory 202848 kb
Host smart-6d11690f-cef8-47c4-95c2-b03ebcdccd39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=711076983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.711076983
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.859187710
Short name T1437
Test name
Test status
Simulation time 30690383 ps
CPU time 0.64 seconds
Started Apr 15 12:31:24 PM PDT 24
Finished Apr 15 12:31:26 PM PDT 24
Peak memory 202748 kb
Host smart-a5a84a4e-ea05-4073-90bd-e2cfe5ea746d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=859187710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.859187710
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.14129842
Short name T1475
Test name
Test status
Simulation time 36397112 ps
CPU time 0.68 seconds
Started Apr 15 12:31:30 PM PDT 24
Finished Apr 15 12:31:32 PM PDT 24
Peak memory 202836 kb
Host smart-9e1f73ec-ff76-4595-a9e1-9f56270b66e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=14129842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.14129842
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2858513868
Short name T1393
Test name
Test status
Simulation time 32152580 ps
CPU time 0.68 seconds
Started Apr 15 12:31:28 PM PDT 24
Finished Apr 15 12:31:31 PM PDT 24
Peak memory 202808 kb
Host smart-95f01785-c23a-40c4-8fa7-35c7e07826f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2858513868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2858513868
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.576909383
Short name T268
Test name
Test status
Simulation time 24682115 ps
CPU time 0.64 seconds
Started Apr 15 12:31:30 PM PDT 24
Finished Apr 15 12:31:32 PM PDT 24
Peak memory 202852 kb
Host smart-03f9e321-a224-4a1c-b222-fabff3a9ba7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=576909383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.576909383
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2089062853
Short name T1408
Test name
Test status
Simulation time 162762282 ps
CPU time 2.01 seconds
Started Apr 15 12:31:21 PM PDT 24
Finished Apr 15 12:31:24 PM PDT 24
Peak memory 203608 kb
Host smart-3e27ac19-1248-4ac9-b45c-dcccdcbff44a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2089062853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2089062853
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3155235762
Short name T239
Test name
Test status
Simulation time 747739920 ps
CPU time 8.44 seconds
Started Apr 15 12:31:21 PM PDT 24
Finished Apr 15 12:31:30 PM PDT 24
Peak memory 203252 kb
Host smart-ccfba8cb-9f2a-48fd-82f5-4c95abd3c2bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3155235762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3155235762
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1013217106
Short name T62
Test name
Test status
Simulation time 78330977 ps
CPU time 0.97 seconds
Started Apr 15 12:31:19 PM PDT 24
Finished Apr 15 12:31:21 PM PDT 24
Peak memory 203216 kb
Host smart-f642ac5c-c6de-48b7-91df-c11f698a1eba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1013217106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1013217106
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2348698672
Short name T1426
Test name
Test status
Simulation time 90304196 ps
CPU time 2.49 seconds
Started Apr 15 12:31:24 PM PDT 24
Finished Apr 15 12:31:29 PM PDT 24
Peak memory 211808 kb
Host smart-0476e60a-cbaf-4c9b-9a7e-d6e45c695a02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348698672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2348698672
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.98317369
Short name T1443
Test name
Test status
Simulation time 41030859 ps
CPU time 0.94 seconds
Started Apr 15 12:31:11 PM PDT 24
Finished Apr 15 12:31:13 PM PDT 24
Peak memory 203492 kb
Host smart-d63a7d02-ed33-49c0-ab0e-3b06f8629241
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=98317369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.98317369
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2865926812
Short name T66
Test name
Test status
Simulation time 25572915 ps
CPU time 0.64 seconds
Started Apr 15 12:31:23 PM PDT 24
Finished Apr 15 12:31:25 PM PDT 24
Peak memory 202748 kb
Host smart-82b0a4fd-46ff-4e57-9dc6-8b0ec1073366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2865926812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.2865926812
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.317810957
Short name T1470
Test name
Test status
Simulation time 90384897 ps
CPU time 1.43 seconds
Started Apr 15 12:31:14 PM PDT 24
Finished Apr 15 12:31:16 PM PDT 24
Peak memory 211804 kb
Host smart-64ce3131-2359-4936-b319-ad2f53a0faee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=317810957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.317810957
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3820116810
Short name T1380
Test name
Test status
Simulation time 477290911 ps
CPU time 4.46 seconds
Started Apr 15 12:31:27 PM PDT 24
Finished Apr 15 12:31:33 PM PDT 24
Peak memory 203460 kb
Host smart-25456949-47ed-4fda-af3c-03a8cdb73da3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3820116810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3820116810
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2002708479
Short name T1430
Test name
Test status
Simulation time 195175413 ps
CPU time 1.13 seconds
Started Apr 15 12:31:23 PM PDT 24
Finished Apr 15 12:31:25 PM PDT 24
Peak memory 203644 kb
Host smart-f16a0b69-4cdc-4535-8435-8739b187c69e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2002708479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.2002708479
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2333297647
Short name T215
Test name
Test status
Simulation time 297147337 ps
CPU time 2.94 seconds
Started Apr 15 12:31:23 PM PDT 24
Finished Apr 15 12:31:28 PM PDT 24
Peak memory 203756 kb
Host smart-1df7e3a0-11a2-487f-bc0f-1d9a8dc24f72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2333297647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2333297647
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2822256574
Short name T1425
Test name
Test status
Simulation time 617135213 ps
CPU time 4.88 seconds
Started Apr 15 12:31:17 PM PDT 24
Finished Apr 15 12:31:22 PM PDT 24
Peak memory 203648 kb
Host smart-a153bf70-d77e-48b0-b909-b901daa33cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2822256574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2822256574
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.4163607793
Short name T254
Test name
Test status
Simulation time 31777511 ps
CPU time 0.65 seconds
Started Apr 15 12:31:32 PM PDT 24
Finished Apr 15 12:31:34 PM PDT 24
Peak memory 202708 kb
Host smart-bd1b4bdf-d5ca-4bc2-af9c-82d5b3f0524a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4163607793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.4163607793
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.4146047632
Short name T272
Test name
Test status
Simulation time 79665485 ps
CPU time 0.68 seconds
Started Apr 15 12:31:24 PM PDT 24
Finished Apr 15 12:31:27 PM PDT 24
Peak memory 202768 kb
Host smart-b5ccf709-5c41-4c15-8a86-39602106f83a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4146047632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.4146047632
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1763215631
Short name T1452
Test name
Test status
Simulation time 27478652 ps
CPU time 0.62 seconds
Started Apr 15 12:31:45 PM PDT 24
Finished Apr 15 12:31:46 PM PDT 24
Peak memory 202784 kb
Host smart-0291ccf9-425f-4765-8343-e0f5111c2a03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1763215631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1763215631
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3353270266
Short name T1448
Test name
Test status
Simulation time 26867391 ps
CPU time 0.65 seconds
Started Apr 15 12:31:29 PM PDT 24
Finished Apr 15 12:31:31 PM PDT 24
Peak memory 202824 kb
Host smart-b827a42f-7747-4a67-b629-998721039f0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3353270266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3353270266
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3291375390
Short name T1400
Test name
Test status
Simulation time 25270995 ps
CPU time 0.66 seconds
Started Apr 15 12:31:22 PM PDT 24
Finished Apr 15 12:31:25 PM PDT 24
Peak memory 202836 kb
Host smart-8dee8400-fab4-411f-b028-91e9a5dfa365
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3291375390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3291375390
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2965140974
Short name T1477
Test name
Test status
Simulation time 33937074 ps
CPU time 0.66 seconds
Started Apr 15 12:31:35 PM PDT 24
Finished Apr 15 12:31:36 PM PDT 24
Peak memory 202824 kb
Host smart-b6f07c3b-d278-454e-865d-a3884e70320e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2965140974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.2965140974
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3438382016
Short name T64
Test name
Test status
Simulation time 24333949 ps
CPU time 0.68 seconds
Started Apr 15 12:31:31 PM PDT 24
Finished Apr 15 12:31:33 PM PDT 24
Peak memory 202772 kb
Host smart-4a1b0390-7317-42ab-9d36-845ef8dcd231
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3438382016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3438382016
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1712273864
Short name T1412
Test name
Test status
Simulation time 34031775 ps
CPU time 0.66 seconds
Started Apr 15 12:31:22 PM PDT 24
Finished Apr 15 12:31:23 PM PDT 24
Peak memory 202856 kb
Host smart-51319b79-f54f-41f6-8b62-6adcb9f69d17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1712273864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1712273864
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3319771029
Short name T1402
Test name
Test status
Simulation time 33522382 ps
CPU time 0.65 seconds
Started Apr 15 12:31:23 PM PDT 24
Finished Apr 15 12:31:26 PM PDT 24
Peak memory 202904 kb
Host smart-aeae1b65-6b91-4ed1-afe9-22df88180727
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3319771029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3319771029
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1738086164
Short name T1460
Test name
Test status
Simulation time 31321840 ps
CPU time 0.65 seconds
Started Apr 15 12:31:26 PM PDT 24
Finished Apr 15 12:31:29 PM PDT 24
Peak memory 202716 kb
Host smart-e8161617-06ea-4a5c-baf8-ab0b415397c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1738086164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1738086164
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2167128660
Short name T1451
Test name
Test status
Simulation time 66145588 ps
CPU time 1.92 seconds
Started Apr 15 12:31:19 PM PDT 24
Finished Apr 15 12:31:22 PM PDT 24
Peak memory 203548 kb
Host smart-9a925724-2f02-42c0-80fd-fd78a9980452
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2167128660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2167128660
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.190665791
Short name T191
Test name
Test status
Simulation time 225703990 ps
CPU time 3.96 seconds
Started Apr 15 12:31:09 PM PDT 24
Finished Apr 15 12:31:13 PM PDT 24
Peak memory 203456 kb
Host smart-948690b9-5482-487b-8d8c-4f433e3e16f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=190665791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.190665791
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1260716059
Short name T1478
Test name
Test status
Simulation time 85999341 ps
CPU time 0.83 seconds
Started Apr 15 12:31:15 PM PDT 24
Finished Apr 15 12:31:17 PM PDT 24
Peak memory 203348 kb
Host smart-012044e9-036a-4679-907b-acfb5db8a2d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1260716059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1260716059
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.301633069
Short name T187
Test name
Test status
Simulation time 157937650 ps
CPU time 2.05 seconds
Started Apr 15 12:31:19 PM PDT 24
Finished Apr 15 12:31:22 PM PDT 24
Peak memory 211856 kb
Host smart-a7ee63b3-aea8-4f43-92a4-99f0dee256b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301633069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev
_csr_mem_rw_with_rand_reset.301633069
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2752349712
Short name T234
Test name
Test status
Simulation time 41203945 ps
CPU time 0.77 seconds
Started Apr 15 12:31:24 PM PDT 24
Finished Apr 15 12:31:27 PM PDT 24
Peak memory 203232 kb
Host smart-64bb23aa-3596-40f4-ad5d-af16d1388517
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2752349712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2752349712
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3032370232
Short name T271
Test name
Test status
Simulation time 28244773 ps
CPU time 0.67 seconds
Started Apr 15 12:31:20 PM PDT 24
Finished Apr 15 12:31:21 PM PDT 24
Peak memory 202752 kb
Host smart-1806c8a8-8ccb-4bf3-9b27-3d36d372c851
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3032370232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3032370232
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2353029032
Short name T237
Test name
Test status
Simulation time 187947066 ps
CPU time 2.33 seconds
Started Apr 15 12:31:21 PM PDT 24
Finished Apr 15 12:31:25 PM PDT 24
Peak memory 211852 kb
Host smart-467c0394-863d-4c22-a658-b00789e279e2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2353029032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2353029032
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2496274745
Short name T1438
Test name
Test status
Simulation time 250977407 ps
CPU time 2.45 seconds
Started Apr 15 12:31:20 PM PDT 24
Finished Apr 15 12:31:23 PM PDT 24
Peak memory 203552 kb
Host smart-5ecf7950-cc35-4b8f-ac89-2a506b19069e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2496274745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.2496274745
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2046042170
Short name T1381
Test name
Test status
Simulation time 205211227 ps
CPU time 1.57 seconds
Started Apr 15 12:31:21 PM PDT 24
Finished Apr 15 12:31:23 PM PDT 24
Peak memory 203616 kb
Host smart-86701947-d058-4e12-8412-c452a9e10c6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2046042170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.2046042170
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3300465912
Short name T1469
Test name
Test status
Simulation time 90289704 ps
CPU time 1.82 seconds
Started Apr 15 12:31:12 PM PDT 24
Finished Apr 15 12:31:15 PM PDT 24
Peak memory 203536 kb
Host smart-1a06cde0-78b6-4381-b45c-e0c6139ac545
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3300465912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3300465912
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1066082847
Short name T275
Test name
Test status
Simulation time 316062290 ps
CPU time 2.64 seconds
Started Apr 15 12:31:05 PM PDT 24
Finished Apr 15 12:31:08 PM PDT 24
Peak memory 203648 kb
Host smart-2069724e-c162-4807-a76c-8ccd1fd9b433
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1066082847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1066082847
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3371389219
Short name T1476
Test name
Test status
Simulation time 60468261 ps
CPU time 0.68 seconds
Started Apr 15 12:31:42 PM PDT 24
Finished Apr 15 12:31:43 PM PDT 24
Peak memory 202772 kb
Host smart-f59ab419-127f-4caf-b238-c698ad8e4d07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3371389219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3371389219
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2929166719
Short name T1405
Test name
Test status
Simulation time 28742149 ps
CPU time 0.66 seconds
Started Apr 15 12:31:28 PM PDT 24
Finished Apr 15 12:31:30 PM PDT 24
Peak memory 202752 kb
Host smart-7214a75f-6532-4ee4-bc2a-55ef0ea24227
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2929166719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2929166719
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2075568314
Short name T263
Test name
Test status
Simulation time 38067048 ps
CPU time 0.66 seconds
Started Apr 15 12:31:25 PM PDT 24
Finished Apr 15 12:31:27 PM PDT 24
Peak memory 202724 kb
Host smart-c87e0dbd-65d3-4542-836f-a46141fe4a24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2075568314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2075568314
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1879793020
Short name T1434
Test name
Test status
Simulation time 26250154 ps
CPU time 0.65 seconds
Started Apr 15 12:31:31 PM PDT 24
Finished Apr 15 12:31:33 PM PDT 24
Peak memory 202772 kb
Host smart-deb63607-714c-41bc-9f5f-096f32a184f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1879793020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.1879793020
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.880258827
Short name T1427
Test name
Test status
Simulation time 59572616 ps
CPU time 0.69 seconds
Started Apr 15 12:31:26 PM PDT 24
Finished Apr 15 12:31:28 PM PDT 24
Peak memory 202860 kb
Host smart-930cbad6-c4bb-4a85-8672-8f6f7a0c630e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=880258827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.880258827
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.778040418
Short name T1409
Test name
Test status
Simulation time 38082881 ps
CPU time 0.64 seconds
Started Apr 15 12:31:26 PM PDT 24
Finished Apr 15 12:31:29 PM PDT 24
Peak memory 202716 kb
Host smart-41d3bbd5-14b5-45b7-8345-4b8bfdf85f2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=778040418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.778040418
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.830247786
Short name T265
Test name
Test status
Simulation time 37335775 ps
CPU time 0.62 seconds
Started Apr 15 12:31:30 PM PDT 24
Finished Apr 15 12:31:32 PM PDT 24
Peak memory 202800 kb
Host smart-8a8aa45d-d0d0-4b0f-81d5-99d1d573750e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=830247786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.830247786
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3392721312
Short name T67
Test name
Test status
Simulation time 29687460 ps
CPU time 0.65 seconds
Started Apr 15 12:31:27 PM PDT 24
Finished Apr 15 12:31:30 PM PDT 24
Peak memory 202808 kb
Host smart-62c5bfa3-2d0b-4819-943c-3f8f7ca4ae0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3392721312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3392721312
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.970333641
Short name T56
Test name
Test status
Simulation time 238980783 ps
CPU time 1.95 seconds
Started Apr 15 12:31:11 PM PDT 24
Finished Apr 15 12:31:14 PM PDT 24
Peak memory 211880 kb
Host smart-33857d67-c088-42a7-9d43-9bb230ed86ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970333641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev
_csr_mem_rw_with_rand_reset.970333641
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.836714803
Short name T192
Test name
Test status
Simulation time 35208912 ps
CPU time 0.78 seconds
Started Apr 15 12:31:25 PM PDT 24
Finished Apr 15 12:31:28 PM PDT 24
Peak memory 203292 kb
Host smart-9f982de2-6535-419a-b8c3-486e198c1a58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=836714803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.836714803
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.252814125
Short name T1397
Test name
Test status
Simulation time 32222009 ps
CPU time 0.65 seconds
Started Apr 15 12:31:19 PM PDT 24
Finished Apr 15 12:31:21 PM PDT 24
Peak memory 202752 kb
Host smart-cb048261-eb76-413e-895a-264dd3c82a61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=252814125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.252814125
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3974248648
Short name T246
Test name
Test status
Simulation time 97839409 ps
CPU time 1.03 seconds
Started Apr 15 12:31:23 PM PDT 24
Finished Apr 15 12:31:26 PM PDT 24
Peak memory 203460 kb
Host smart-f8d9f23a-205f-464a-a91f-f60150c8430a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3974248648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.3974248648
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1777676607
Short name T1396
Test name
Test status
Simulation time 76235571 ps
CPU time 2 seconds
Started Apr 15 12:31:23 PM PDT 24
Finished Apr 15 12:31:27 PM PDT 24
Peak memory 203656 kb
Host smart-ac2dc417-7b4e-4fb0-8689-413ba2792187
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1777676607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1777676607
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2408146518
Short name T257
Test name
Test status
Simulation time 302113395 ps
CPU time 2.43 seconds
Started Apr 15 12:31:20 PM PDT 24
Finished Apr 15 12:31:24 PM PDT 24
Peak memory 203696 kb
Host smart-2000a0e8-db1b-47b1-83c7-05c7dfce9c7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2408146518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2408146518
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1729399801
Short name T1401
Test name
Test status
Simulation time 204479071 ps
CPU time 1.27 seconds
Started Apr 15 12:31:22 PM PDT 24
Finished Apr 15 12:31:24 PM PDT 24
Peak memory 212012 kb
Host smart-f3bcbd45-4d4e-446d-ac36-2bfb2aa2562f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729399801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.1729399801
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2307362927
Short name T1389
Test name
Test status
Simulation time 91965852 ps
CPU time 1.01 seconds
Started Apr 15 12:31:22 PM PDT 24
Finished Apr 15 12:31:25 PM PDT 24
Peak memory 203628 kb
Host smart-c277a1e0-c11b-4b91-91bd-22fff85eb3c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2307362927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2307362927
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2540093586
Short name T1431
Test name
Test status
Simulation time 67633789 ps
CPU time 0.72 seconds
Started Apr 15 12:31:19 PM PDT 24
Finished Apr 15 12:31:21 PM PDT 24
Peak memory 202804 kb
Host smart-c47bf603-76a6-444c-99b1-ecc0f6b38804
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2540093586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2540093586
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1750679336
Short name T1447
Test name
Test status
Simulation time 97610030 ps
CPU time 1.16 seconds
Started Apr 15 12:31:13 PM PDT 24
Finished Apr 15 12:31:15 PM PDT 24
Peak memory 203532 kb
Host smart-2a9ef708-aeb6-44f9-8d6d-623b5abe5e2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1750679336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.1750679336
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.286386309
Short name T1454
Test name
Test status
Simulation time 85222218 ps
CPU time 2.37 seconds
Started Apr 15 12:31:26 PM PDT 24
Finished Apr 15 12:31:30 PM PDT 24
Peak memory 203652 kb
Host smart-abada82b-b773-494a-bbd3-9c2ad00fc9bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=286386309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.286386309
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.548615783
Short name T1432
Test name
Test status
Simulation time 284648159 ps
CPU time 2.46 seconds
Started Apr 15 12:31:22 PM PDT 24
Finished Apr 15 12:31:26 PM PDT 24
Peak memory 203580 kb
Host smart-23e5d288-3cea-4ca7-8190-95ab6e123906
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=548615783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.548615783
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.4103936701
Short name T219
Test name
Test status
Simulation time 78592045 ps
CPU time 1.18 seconds
Started Apr 15 12:31:30 PM PDT 24
Finished Apr 15 12:31:32 PM PDT 24
Peak memory 211940 kb
Host smart-5001d185-b376-4775-878b-b8e8edf150b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103936701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.4103936701
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.501102993
Short name T1462
Test name
Test status
Simulation time 65974570 ps
CPU time 0.99 seconds
Started Apr 15 12:31:24 PM PDT 24
Finished Apr 15 12:31:27 PM PDT 24
Peak memory 203456 kb
Host smart-1c049f45-6dab-4363-8cd8-c90dff5f0797
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=501102993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.501102993
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3756043449
Short name T1403
Test name
Test status
Simulation time 47921499 ps
CPU time 0.74 seconds
Started Apr 15 12:31:21 PM PDT 24
Finished Apr 15 12:31:23 PM PDT 24
Peak memory 202844 kb
Host smart-e74883af-0be5-4d3a-80fa-92ec84fc635a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3756043449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.3756043449
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2932479220
Short name T1395
Test name
Test status
Simulation time 160979940 ps
CPU time 1.24 seconds
Started Apr 15 12:31:17 PM PDT 24
Finished Apr 15 12:31:19 PM PDT 24
Peak memory 203648 kb
Host smart-9611d771-18df-41d7-ae40-9618c2d2d051
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2932479220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2932479220
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1758718840
Short name T1422
Test name
Test status
Simulation time 171423317 ps
CPU time 2.63 seconds
Started Apr 15 12:31:09 PM PDT 24
Finished Apr 15 12:31:13 PM PDT 24
Peak memory 203720 kb
Host smart-51f00211-9c86-47ec-a72f-e6b5e474b8e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1758718840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1758718840
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1033346705
Short name T261
Test name
Test status
Simulation time 588356935 ps
CPU time 3.01 seconds
Started Apr 15 12:31:25 PM PDT 24
Finished Apr 15 12:31:30 PM PDT 24
Peak memory 203696 kb
Host smart-af1d5e03-5370-4e56-ae10-626ae1d47361
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1033346705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1033346705
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.631750298
Short name T1421
Test name
Test status
Simulation time 82208735 ps
CPU time 1.17 seconds
Started Apr 15 12:31:27 PM PDT 24
Finished Apr 15 12:31:30 PM PDT 24
Peak memory 211920 kb
Host smart-4a124460-df05-4197-bcfb-e44906315b38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631750298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev
_csr_mem_rw_with_rand_reset.631750298
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1916087403
Short name T236
Test name
Test status
Simulation time 68214476 ps
CPU time 0.86 seconds
Started Apr 15 12:31:29 PM PDT 24
Finished Apr 15 12:31:32 PM PDT 24
Peak memory 203320 kb
Host smart-44fc62c9-38c9-415a-9549-aafc42bcc934
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1916087403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1916087403
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1727983882
Short name T65
Test name
Test status
Simulation time 35889331 ps
CPU time 0.68 seconds
Started Apr 15 12:31:23 PM PDT 24
Finished Apr 15 12:31:25 PM PDT 24
Peak memory 202712 kb
Host smart-0a33ed1d-3817-44de-bb83-612fd8c89415
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1727983882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1727983882
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2314827951
Short name T1418
Test name
Test status
Simulation time 53554634 ps
CPU time 1.03 seconds
Started Apr 15 12:31:23 PM PDT 24
Finished Apr 15 12:31:26 PM PDT 24
Peak memory 203564 kb
Host smart-8d20f92d-838e-423d-937d-c90c355c9988
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2314827951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.2314827951
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1089137010
Short name T1455
Test name
Test status
Simulation time 157626308 ps
CPU time 2.15 seconds
Started Apr 15 12:31:21 PM PDT 24
Finished Apr 15 12:31:24 PM PDT 24
Peak memory 203620 kb
Host smart-ecc2d4d4-0f3e-4045-be1f-c646fe65c398
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1089137010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1089137010
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2422008108
Short name T260
Test name
Test status
Simulation time 213865943 ps
CPU time 2.24 seconds
Started Apr 15 12:31:24 PM PDT 24
Finished Apr 15 12:31:28 PM PDT 24
Peak memory 203656 kb
Host smart-b3b2e6e7-7008-414a-9141-c5dedb1ad93f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2422008108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.2422008108
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1565416027
Short name T1423
Test name
Test status
Simulation time 87416147 ps
CPU time 1.19 seconds
Started Apr 15 12:31:15 PM PDT 24
Finished Apr 15 12:31:17 PM PDT 24
Peak memory 211868 kb
Host smart-61ad2493-abf5-44f2-a656-612d61a39819
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565416027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.1565416027
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2316463592
Short name T1442
Test name
Test status
Simulation time 45896703 ps
CPU time 0.79 seconds
Started Apr 15 12:31:11 PM PDT 24
Finished Apr 15 12:31:13 PM PDT 24
Peak memory 203376 kb
Host smart-43cda46a-297b-4c96-8717-cf48ea0991f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2316463592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2316463592
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2915358426
Short name T1410
Test name
Test status
Simulation time 91065042 ps
CPU time 1.63 seconds
Started Apr 15 12:31:22 PM PDT 24
Finished Apr 15 12:31:25 PM PDT 24
Peak memory 203592 kb
Host smart-48c2c3bd-512c-4c75-94b2-55bae869467f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2915358426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.2915358426
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2762391440
Short name T212
Test name
Test status
Simulation time 170136665 ps
CPU time 2.17 seconds
Started Apr 15 12:31:25 PM PDT 24
Finished Apr 15 12:31:29 PM PDT 24
Peak memory 203628 kb
Host smart-a95fe3e3-ee89-43fa-b025-7aa8098acc2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2762391440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2762391440
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3533742136
Short name T1433
Test name
Test status
Simulation time 291356045 ps
CPU time 4.07 seconds
Started Apr 15 12:31:22 PM PDT 24
Finished Apr 15 12:31:28 PM PDT 24
Peak memory 203552 kb
Host smart-735aaf84-ce10-434f-b4ba-bba92b4248f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3533742136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3533742136
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.3445571319
Short name T46
Test name
Test status
Simulation time 8464087677 ps
CPU time 8.1 seconds
Started Apr 15 03:10:23 PM PDT 24
Finished Apr 15 03:10:32 PM PDT 24
Peak memory 204064 kb
Host smart-39c11498-2437-445d-8e96-0ad056ca4294
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3445571319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.3445571319
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.2522236024
Short name T1189
Test name
Test status
Simulation time 8376681035 ps
CPU time 9.03 seconds
Started Apr 15 03:10:30 PM PDT 24
Finished Apr 15 03:10:40 PM PDT 24
Peak memory 204056 kb
Host smart-d7467caf-0485-43ef-bd09-ce5ec60f5fee
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2522236024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.2522236024
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.506815365
Short name T1239
Test name
Test status
Simulation time 8442854096 ps
CPU time 7.92 seconds
Started Apr 15 03:10:20 PM PDT 24
Finished Apr 15 03:10:28 PM PDT 24
Peak memory 203984 kb
Host smart-755f1b05-9d08-4953-baf7-1447e2cfa83f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50681
5365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.506815365
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.1871991142
Short name T1084
Test name
Test status
Simulation time 8382205846 ps
CPU time 7.85 seconds
Started Apr 15 03:09:41 PM PDT 24
Finished Apr 15 03:09:50 PM PDT 24
Peak memory 204048 kb
Host smart-991adf48-ab83-4407-b72b-4c8e0a20259b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18719
91142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.1871991142
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_enable.4284548539
Short name T892
Test name
Test status
Simulation time 8384465161 ps
CPU time 7.94 seconds
Started Apr 15 03:09:44 PM PDT 24
Finished Apr 15 03:09:52 PM PDT 24
Peak memory 204040 kb
Host smart-6eab0938-16bb-4513-addd-359bffaf429f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42845
48539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.4284548539
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.3883931035
Short name T422
Test name
Test status
Simulation time 80393215 ps
CPU time 2.01 seconds
Started Apr 15 03:09:44 PM PDT 24
Finished Apr 15 03:09:46 PM PDT 24
Peak memory 204040 kb
Host smart-297476d3-da78-495b-9b87-051594f66c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38839
31035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.3883931035
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.2366055890
Short name T996
Test name
Test status
Simulation time 8385214254 ps
CPU time 8.75 seconds
Started Apr 15 03:10:20 PM PDT 24
Finished Apr 15 03:10:29 PM PDT 24
Peak memory 204044 kb
Host smart-a11bb167-7370-4950-a174-b00ccb8873bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23660
55890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.2366055890
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2861931418
Short name T910
Test name
Test status
Simulation time 8372441092 ps
CPU time 9.95 seconds
Started Apr 15 03:10:20 PM PDT 24
Finished Apr 15 03:10:30 PM PDT 24
Peak memory 204048 kb
Host smart-33792f39-2405-4940-9894-eff0e1a1fd6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28619
31418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2861931418
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2358279630
Short name T789
Test name
Test status
Simulation time 8452345544 ps
CPU time 10 seconds
Started Apr 15 03:09:47 PM PDT 24
Finished Apr 15 03:09:57 PM PDT 24
Peak memory 204024 kb
Host smart-e28ff5fc-0d6b-488a-ba3e-ff7f40829246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23582
79630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2358279630
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.2487458435
Short name T312
Test name
Test status
Simulation time 8417159272 ps
CPU time 8.38 seconds
Started Apr 15 03:09:48 PM PDT 24
Finished Apr 15 03:09:57 PM PDT 24
Peak memory 204080 kb
Host smart-439be60e-4efc-4ee9-973a-f59cc1622f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24874
58435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.2487458435
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.1273114640
Short name T1137
Test name
Test status
Simulation time 8401004242 ps
CPU time 7.59 seconds
Started Apr 15 03:09:48 PM PDT 24
Finished Apr 15 03:09:56 PM PDT 24
Peak memory 204044 kb
Host smart-79dcf158-a2d9-4a0f-9454-ec96146cbbff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12731
14640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.1273114640
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.876568760
Short name T1336
Test name
Test status
Simulation time 8387499254 ps
CPU time 10.67 seconds
Started Apr 15 03:09:54 PM PDT 24
Finished Apr 15 03:10:05 PM PDT 24
Peak memory 204028 kb
Host smart-60c4ba7f-aa9c-48bc-b530-2e149434b865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87656
8760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.876568760
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2936155902
Short name T30
Test name
Test status
Simulation time 8395486548 ps
CPU time 8.51 seconds
Started Apr 15 03:09:59 PM PDT 24
Finished Apr 15 03:10:08 PM PDT 24
Peak memory 203976 kb
Host smart-1dd77c14-5d98-49c8-9a0d-79fee9b6a738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29361
55902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2936155902
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.3380282598
Short name T747
Test name
Test status
Simulation time 166451508 ps
CPU time 0.79 seconds
Started Apr 15 03:10:17 PM PDT 24
Finished Apr 15 03:10:18 PM PDT 24
Peak memory 203932 kb
Host smart-f5918d4f-31c4-489d-8ec1-96157d4990ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33802
82598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.3380282598
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.784772710
Short name T833
Test name
Test status
Simulation time 17602616607 ps
CPU time 34.54 seconds
Started Apr 15 03:09:57 PM PDT 24
Finished Apr 15 03:10:32 PM PDT 24
Peak memory 204312 kb
Host smart-7ce83714-c208-4079-883b-bb66e39fcb65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78477
2710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.784772710
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.184539673
Short name T584
Test name
Test status
Simulation time 8380754807 ps
CPU time 9.41 seconds
Started Apr 15 03:10:00 PM PDT 24
Finished Apr 15 03:10:10 PM PDT 24
Peak memory 204032 kb
Host smart-be37b44b-eb49-4a30-a16f-9f29d71ca5ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18453
9673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.184539673
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.640818538
Short name T513
Test name
Test status
Simulation time 8493839976 ps
CPU time 9.86 seconds
Started Apr 15 03:10:05 PM PDT 24
Finished Apr 15 03:10:15 PM PDT 24
Peak memory 204024 kb
Host smart-232f33b7-a9ea-4e04-be8c-8da12aa069c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64081
8538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.640818538
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.4292675414
Short name T535
Test name
Test status
Simulation time 8387663689 ps
CPU time 8.83 seconds
Started Apr 15 03:10:09 PM PDT 24
Finished Apr 15 03:10:18 PM PDT 24
Peak memory 204056 kb
Host smart-34328194-1a2c-4cff-a978-04356c5502cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42926
75414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.4292675414
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.2954602046
Short name T694
Test name
Test status
Simulation time 8408980314 ps
CPU time 7.72 seconds
Started Apr 15 03:10:15 PM PDT 24
Finished Apr 15 03:10:23 PM PDT 24
Peak memory 204048 kb
Host smart-3b643bde-eb7b-407b-984d-c1cdbb27e441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29546
02046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2954602046
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.3687314238
Short name T1325
Test name
Test status
Simulation time 8377718822 ps
CPU time 10.07 seconds
Started Apr 15 03:10:15 PM PDT 24
Finished Apr 15 03:10:25 PM PDT 24
Peak memory 204052 kb
Host smart-7848b5dd-062c-46c1-9a18-3dccb3c576a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36873
14238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.3687314238
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1557260721
Short name T1099
Test name
Test status
Simulation time 8468338988 ps
CPU time 8.63 seconds
Started Apr 15 03:09:39 PM PDT 24
Finished Apr 15 03:09:49 PM PDT 24
Peak memory 204052 kb
Host smart-7f3f77a7-ab83-45e7-8040-e1fbe28e899c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15572
60721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1557260721
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.3792979959
Short name T555
Test name
Test status
Simulation time 8374756777 ps
CPU time 7.76 seconds
Started Apr 15 03:10:15 PM PDT 24
Finished Apr 15 03:10:23 PM PDT 24
Peak memory 204048 kb
Host smart-e0934b49-a63f-420a-9ad3-c97074dcebbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37929
79959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.3792979959
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.3237277963
Short name T699
Test name
Test status
Simulation time 8389450954 ps
CPU time 10.26 seconds
Started Apr 15 03:10:14 PM PDT 24
Finished Apr 15 03:10:25 PM PDT 24
Peak memory 204060 kb
Host smart-49cfa27f-5d96-4b01-bdce-da3e464daf87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32372
77963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3237277963
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.3255144128
Short name T592
Test name
Test status
Simulation time 8465079795 ps
CPU time 7.96 seconds
Started Apr 15 03:10:57 PM PDT 24
Finished Apr 15 03:11:05 PM PDT 24
Peak memory 204060 kb
Host smart-e4f4f7a0-3dfa-4b84-96de-cfc0259d39c0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3255144128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.3255144128
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.3280396879
Short name T409
Test name
Test status
Simulation time 8388884290 ps
CPU time 9.57 seconds
Started Apr 15 03:10:58 PM PDT 24
Finished Apr 15 03:11:08 PM PDT 24
Peak memory 204008 kb
Host smart-1bad7b33-f54f-40ad-8876-4d88a65c87d1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3280396879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.3280396879
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.53162432
Short name T304
Test name
Test status
Simulation time 8460383645 ps
CPU time 8.6 seconds
Started Apr 15 03:10:52 PM PDT 24
Finished Apr 15 03:11:01 PM PDT 24
Peak memory 204056 kb
Host smart-90d5f303-1767-4742-95da-2cd364b9fde5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53162
432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.53162432
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.2522427121
Short name T1256
Test name
Test status
Simulation time 8377595905 ps
CPU time 8.72 seconds
Started Apr 15 03:10:57 PM PDT 24
Finished Apr 15 03:11:06 PM PDT 24
Peak memory 204068 kb
Host smart-1ac8d307-e6c7-42a1-ab2d-ee05314759d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25224
27121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.2522427121
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_enable.3038596557
Short name T525
Test name
Test status
Simulation time 8380691576 ps
CPU time 8.99 seconds
Started Apr 15 03:10:28 PM PDT 24
Finished Apr 15 03:10:38 PM PDT 24
Peak memory 203992 kb
Host smart-7cf2deae-cb93-428b-9751-d5289c655da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30385
96557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3038596557
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.3003640927
Short name T908
Test name
Test status
Simulation time 52278393 ps
CPU time 1.38 seconds
Started Apr 15 03:10:28 PM PDT 24
Finished Apr 15 03:10:30 PM PDT 24
Peak memory 204100 kb
Host smart-7ea2b21f-8725-4891-8073-2a7d84442d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30036
40927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.3003640927
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.1831329661
Short name T494
Test name
Test status
Simulation time 8394997211 ps
CPU time 9.88 seconds
Started Apr 15 03:10:53 PM PDT 24
Finished Apr 15 03:11:04 PM PDT 24
Peak memory 204048 kb
Host smart-e8a570cb-e233-4526-a98a-63d527dd9692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18313
29661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.1831329661
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.3604612458
Short name T876
Test name
Test status
Simulation time 8382986163 ps
CPU time 8.81 seconds
Started Apr 15 03:10:53 PM PDT 24
Finished Apr 15 03:11:02 PM PDT 24
Peak memory 204020 kb
Host smart-29782ec4-ecc0-4bd5-8758-d26334f96f53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36046
12458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3604612458
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.2080437123
Short name T839
Test name
Test status
Simulation time 8430277736 ps
CPU time 7.78 seconds
Started Apr 15 03:10:27 PM PDT 24
Finished Apr 15 03:10:35 PM PDT 24
Peak memory 204008 kb
Host smart-2f8a29de-c207-4d15-a9f4-9278bb74d5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20804
37123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.2080437123
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.3444022248
Short name T984
Test name
Test status
Simulation time 8519030838 ps
CPU time 7.6 seconds
Started Apr 15 03:10:31 PM PDT 24
Finished Apr 15 03:10:39 PM PDT 24
Peak memory 204048 kb
Host smart-18f644db-f8a8-4f5d-82cc-0bbb0ce4e539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34440
22248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.3444022248
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.3629769644
Short name T1370
Test name
Test status
Simulation time 8386359414 ps
CPU time 8.13 seconds
Started Apr 15 03:10:32 PM PDT 24
Finished Apr 15 03:10:41 PM PDT 24
Peak memory 204052 kb
Host smart-ee6f86bc-e558-4eef-8647-f8f58432f92b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36297
69644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.3629769644
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.2877086154
Short name T401
Test name
Test status
Simulation time 8401855282 ps
CPU time 7.76 seconds
Started Apr 15 03:10:32 PM PDT 24
Finished Apr 15 03:10:41 PM PDT 24
Peak memory 204056 kb
Host smart-5af400b2-49d3-4a57-ae88-48497996b4c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28770
86154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2877086154
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.4111748139
Short name T885
Test name
Test status
Simulation time 8415838943 ps
CPU time 10.19 seconds
Started Apr 15 03:10:30 PM PDT 24
Finished Apr 15 03:10:41 PM PDT 24
Peak memory 204068 kb
Host smart-a42cf7ab-2d61-4053-be9a-1b8c79f1f77b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41117
48139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.4111748139
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.1690947314
Short name T1161
Test name
Test status
Simulation time 8362603540 ps
CPU time 7.85 seconds
Started Apr 15 03:10:51 PM PDT 24
Finished Apr 15 03:10:59 PM PDT 24
Peak memory 204044 kb
Host smart-16554819-b957-4b79-8571-bba31d4c0b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16909
47314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.1690947314
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.48782229
Short name T458
Test name
Test status
Simulation time 130895205 ps
CPU time 0.76 seconds
Started Apr 15 03:10:50 PM PDT 24
Finished Apr 15 03:10:51 PM PDT 24
Peak memory 203844 kb
Host smart-b2edae6b-8c18-4704-ad43-8bc6e14a62a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48782
229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.48782229
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.1093008730
Short name T828
Test name
Test status
Simulation time 32158457816 ps
CPU time 68.23 seconds
Started Apr 15 03:10:34 PM PDT 24
Finished Apr 15 03:11:43 PM PDT 24
Peak memory 204348 kb
Host smart-2fbd43cd-ac6b-43f6-a9b2-1e179907eea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10930
08730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.1093008730
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.215460406
Short name T630
Test name
Test status
Simulation time 8411674271 ps
CPU time 8.31 seconds
Started Apr 15 03:10:33 PM PDT 24
Finished Apr 15 03:10:42 PM PDT 24
Peak memory 204080 kb
Host smart-070189f5-271d-4147-bd6b-e74f3f85693b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21546
0406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.215460406
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.1835369535
Short name T948
Test name
Test status
Simulation time 8465416872 ps
CPU time 8.69 seconds
Started Apr 15 03:10:38 PM PDT 24
Finished Apr 15 03:10:48 PM PDT 24
Peak memory 204052 kb
Host smart-71532019-66a7-4ed6-842a-db436f7bd897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18353
69535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.1835369535
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.1821188721
Short name T1302
Test name
Test status
Simulation time 8396754070 ps
CPU time 9.22 seconds
Started Apr 15 03:10:40 PM PDT 24
Finished Apr 15 03:10:50 PM PDT 24
Peak memory 204056 kb
Host smart-bbd89b03-8115-4b78-9134-4efa6e137e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18211
88721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.1821188721
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.3720625685
Short name T70
Test name
Test status
Simulation time 400520175 ps
CPU time 1.28 seconds
Started Apr 15 03:10:57 PM PDT 24
Finished Apr 15 03:10:59 PM PDT 24
Peak memory 221216 kb
Host smart-a388a7ff-ad9b-4818-90a6-e32e2046a38d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3720625685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.3720625685
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.1660354902
Short name T156
Test name
Test status
Simulation time 8407113571 ps
CPU time 8.44 seconds
Started Apr 15 03:10:49 PM PDT 24
Finished Apr 15 03:10:58 PM PDT 24
Peak memory 203992 kb
Host smart-412bfcf3-6f3a-4b3b-a6a5-4b039b2ce950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16603
54902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.1660354902
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3363207879
Short name T815
Test name
Test status
Simulation time 8370276566 ps
CPU time 8.65 seconds
Started Apr 15 03:10:41 PM PDT 24
Finished Apr 15 03:10:50 PM PDT 24
Peak memory 204028 kb
Host smart-863e7463-ca69-4c3c-a41a-d6bc3fa475b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33632
07879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3363207879
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.2901126458
Short name T1347
Test name
Test status
Simulation time 8493059580 ps
CPU time 9.2 seconds
Started Apr 15 03:10:24 PM PDT 24
Finished Apr 15 03:10:34 PM PDT 24
Peak memory 203992 kb
Host smart-7693b480-50b2-4ab7-b119-80f261de0cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29011
26458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.2901126458
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1935304352
Short name T1287
Test name
Test status
Simulation time 8410519377 ps
CPU time 8.43 seconds
Started Apr 15 03:10:40 PM PDT 24
Finished Apr 15 03:10:49 PM PDT 24
Peak memory 204048 kb
Host smart-b092f3c8-e23a-49a7-9247-54cab1a02b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19353
04352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1935304352
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.3402017559
Short name T670
Test name
Test status
Simulation time 8429222091 ps
CPU time 7.71 seconds
Started Apr 15 03:10:38 PM PDT 24
Finished Apr 15 03:10:47 PM PDT 24
Peak memory 204052 kb
Host smart-1f5695c8-136f-4b24-9212-84db58cc0637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34020
17559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.3402017559
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.3368210817
Short name T396
Test name
Test status
Simulation time 8525631005 ps
CPU time 8.4 seconds
Started Apr 15 03:13:19 PM PDT 24
Finished Apr 15 03:13:28 PM PDT 24
Peak memory 204204 kb
Host smart-848b5efe-461f-4aca-af3e-4e8ee6e1d3d2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3368210817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.3368210817
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.3372105357
Short name T496
Test name
Test status
Simulation time 8371348136 ps
CPU time 8.47 seconds
Started Apr 15 03:13:19 PM PDT 24
Finished Apr 15 03:13:28 PM PDT 24
Peak memory 204064 kb
Host smart-1297cd07-b169-49a3-b5c1-d1126710c61f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3372105357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.3372105357
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.2128128954
Short name T344
Test name
Test status
Simulation time 8439145260 ps
CPU time 8.27 seconds
Started Apr 15 03:13:18 PM PDT 24
Finished Apr 15 03:13:27 PM PDT 24
Peak memory 204068 kb
Host smart-3fd269d8-d555-45ec-9856-87be40af8a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21281
28954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.2128128954
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.4084857104
Short name T608
Test name
Test status
Simulation time 8391973675 ps
CPU time 7.91 seconds
Started Apr 15 03:13:07 PM PDT 24
Finished Apr 15 03:13:15 PM PDT 24
Peak memory 204060 kb
Host smart-22b0dd26-9889-4628-867a-ceea0bd5c890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40848
57104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.4084857104
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_enable.4292708470
Short name T562
Test name
Test status
Simulation time 8373052140 ps
CPU time 8.98 seconds
Started Apr 15 03:13:09 PM PDT 24
Finished Apr 15 03:13:19 PM PDT 24
Peak memory 204048 kb
Host smart-d3220a86-6a43-4204-b1c2-acaa123fb940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42927
08470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.4292708470
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.1721509738
Short name T871
Test name
Test status
Simulation time 154763492 ps
CPU time 1.77 seconds
Started Apr 15 03:13:09 PM PDT 24
Finished Apr 15 03:13:11 PM PDT 24
Peak memory 204104 kb
Host smart-2686b57b-c32f-453a-849b-4893914377fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17215
09738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.1721509738
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.1385471789
Short name T1238
Test name
Test status
Simulation time 8451332413 ps
CPU time 8 seconds
Started Apr 15 03:13:18 PM PDT 24
Finished Apr 15 03:13:26 PM PDT 24
Peak memory 204056 kb
Host smart-dec81cee-540e-4301-8c2f-a042b8169ea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13854
71789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.1385471789
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.393279928
Short name T424
Test name
Test status
Simulation time 8396615060 ps
CPU time 8.11 seconds
Started Apr 15 03:13:11 PM PDT 24
Finished Apr 15 03:13:20 PM PDT 24
Peak memory 204056 kb
Host smart-2551b449-9ce8-421d-a271-4c2722f3a66f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39327
9928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.393279928
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.1132611348
Short name T330
Test name
Test status
Simulation time 8438580574 ps
CPU time 7.69 seconds
Started Apr 15 03:13:09 PM PDT 24
Finished Apr 15 03:13:17 PM PDT 24
Peak memory 203996 kb
Host smart-8dd35000-c8e4-4932-a6fc-7fa00e95feda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11326
11348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.1132611348
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.3376646110
Short name T587
Test name
Test status
Simulation time 8383178845 ps
CPU time 8.43 seconds
Started Apr 15 03:13:13 PM PDT 24
Finished Apr 15 03:13:21 PM PDT 24
Peak memory 204056 kb
Host smart-37721841-869a-40e7-ac73-7de1f9fb1efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33766
46110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.3376646110
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.2262048493
Short name T1230
Test name
Test status
Simulation time 8391292909 ps
CPU time 8.01 seconds
Started Apr 15 03:13:11 PM PDT 24
Finished Apr 15 03:13:20 PM PDT 24
Peak memory 204064 kb
Host smart-f9953d91-8cc0-44f7-b791-df7edf2b9dc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22620
48493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2262048493
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.985474210
Short name T532
Test name
Test status
Simulation time 8492459297 ps
CPU time 8.73 seconds
Started Apr 15 03:13:13 PM PDT 24
Finished Apr 15 03:13:22 PM PDT 24
Peak memory 204056 kb
Host smart-9e01905e-cf74-4e08-b457-548df9f78d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98547
4210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.985474210
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.3027703857
Short name T1305
Test name
Test status
Simulation time 8370415831 ps
CPU time 8.07 seconds
Started Apr 15 03:13:19 PM PDT 24
Finished Apr 15 03:13:28 PM PDT 24
Peak memory 203924 kb
Host smart-c44c2558-7ad3-493f-a771-fce168e1c4c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30277
03857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3027703857
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2336387222
Short name T404
Test name
Test status
Simulation time 110111676 ps
CPU time 0.76 seconds
Started Apr 15 03:13:20 PM PDT 24
Finished Apr 15 03:13:21 PM PDT 24
Peak memory 203924 kb
Host smart-89c8099d-163f-46ae-8a43-aa4d5b877f23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23363
87222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2336387222
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.2353266628
Short name T779
Test name
Test status
Simulation time 20598271317 ps
CPU time 37.76 seconds
Started Apr 15 03:13:10 PM PDT 24
Finished Apr 15 03:13:48 PM PDT 24
Peak memory 204284 kb
Host smart-ec326b46-e831-4e40-b113-9eb6ca33d694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23532
66628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.2353266628
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.4266313940
Short name T1330
Test name
Test status
Simulation time 8425460685 ps
CPU time 7.82 seconds
Started Apr 15 03:13:11 PM PDT 24
Finished Apr 15 03:13:20 PM PDT 24
Peak memory 204044 kb
Host smart-39f7c536-aed2-469f-834f-a745afb766c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42663
13940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.4266313940
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.1013450074
Short name T884
Test name
Test status
Simulation time 8426130051 ps
CPU time 8.06 seconds
Started Apr 15 03:13:10 PM PDT 24
Finished Apr 15 03:13:19 PM PDT 24
Peak memory 204024 kb
Host smart-49804ae6-259a-42a6-bd92-17974fcf54dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10134
50074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.1013450074
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.2225871832
Short name T1272
Test name
Test status
Simulation time 8417698504 ps
CPU time 8.29 seconds
Started Apr 15 03:13:10 PM PDT 24
Finished Apr 15 03:13:18 PM PDT 24
Peak memory 203980 kb
Host smart-1e706341-8566-42a5-8c36-e338ad2fa212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22258
71832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.2225871832
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.3648397415
Short name T806
Test name
Test status
Simulation time 8384239626 ps
CPU time 8.47 seconds
Started Apr 15 03:13:13 PM PDT 24
Finished Apr 15 03:13:22 PM PDT 24
Peak memory 203880 kb
Host smart-f0dff0b1-5ac8-4cd9-8d72-1568d9963b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36483
97415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.3648397415
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.134196631
Short name T506
Test name
Test status
Simulation time 8368567122 ps
CPU time 8.46 seconds
Started Apr 15 03:13:18 PM PDT 24
Finished Apr 15 03:13:27 PM PDT 24
Peak memory 204072 kb
Host smart-c24e65a2-6980-44f8-8663-9eeffe2c4bfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13419
6631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.134196631
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.3980309855
Short name T767
Test name
Test status
Simulation time 8451094553 ps
CPU time 8.36 seconds
Started Apr 15 03:13:07 PM PDT 24
Finished Apr 15 03:13:15 PM PDT 24
Peak memory 204052 kb
Host smart-b6461e9a-4d69-43a7-9d25-f48f9690ea94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39803
09855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.3980309855
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.2042363480
Short name T415
Test name
Test status
Simulation time 8368283665 ps
CPU time 9.76 seconds
Started Apr 15 03:13:21 PM PDT 24
Finished Apr 15 03:13:31 PM PDT 24
Peak memory 203984 kb
Host smart-8e0b2703-8f38-4de8-9630-884cb35ca492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20423
63480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.2042363480
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.3087957421
Short name T992
Test name
Test status
Simulation time 8388869660 ps
CPU time 9.15 seconds
Started Apr 15 03:13:16 PM PDT 24
Finished Apr 15 03:13:26 PM PDT 24
Peak memory 203996 kb
Host smart-ee4d04f3-6e0c-41eb-9ce8-f11c02db6212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30879
57421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.3087957421
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.470708939
Short name T735
Test name
Test status
Simulation time 8465846522 ps
CPU time 8.04 seconds
Started Apr 15 03:13:29 PM PDT 24
Finished Apr 15 03:13:38 PM PDT 24
Peak memory 203980 kb
Host smart-e5ff2064-71b5-46d4-beb6-dfb66cea76f6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=470708939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.470708939
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.2135713906
Short name T1058
Test name
Test status
Simulation time 8386806647 ps
CPU time 8.09 seconds
Started Apr 15 03:13:27 PM PDT 24
Finished Apr 15 03:13:36 PM PDT 24
Peak memory 204056 kb
Host smart-bafdbcb7-c52e-4381-b449-09243a4192f3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2135713906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.2135713906
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.1874089678
Short name T1034
Test name
Test status
Simulation time 8467935580 ps
CPU time 8.29 seconds
Started Apr 15 03:13:30 PM PDT 24
Finished Apr 15 03:13:39 PM PDT 24
Peak memory 204044 kb
Host smart-1aa4d302-64a7-4b90-bcd7-e15ba8b17001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18740
89678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.1874089678
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.3038030321
Short name T749
Test name
Test status
Simulation time 8377939791 ps
CPU time 7.86 seconds
Started Apr 15 03:13:19 PM PDT 24
Finished Apr 15 03:13:28 PM PDT 24
Peak memory 204204 kb
Host smart-563d21a8-73a8-491e-bb77-9360dd4eb4ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30380
30321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.3038030321
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_enable.3403726737
Short name T795
Test name
Test status
Simulation time 8386753511 ps
CPU time 7.94 seconds
Started Apr 15 03:13:19 PM PDT 24
Finished Apr 15 03:13:27 PM PDT 24
Peak memory 204064 kb
Host smart-afa1cd02-99df-4521-8120-6aa343835c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34037
26737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3403726737
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.1112984739
Short name T615
Test name
Test status
Simulation time 287013961 ps
CPU time 2.22 seconds
Started Apr 15 03:13:22 PM PDT 24
Finished Apr 15 03:13:24 PM PDT 24
Peak memory 204096 kb
Host smart-1106bc27-acca-4f04-88b1-d0c7ac547a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11129
84739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.1112984739
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.1167908631
Short name T1178
Test name
Test status
Simulation time 8373141066 ps
CPU time 8.04 seconds
Started Apr 15 03:13:26 PM PDT 24
Finished Apr 15 03:13:34 PM PDT 24
Peak memory 204060 kb
Host smart-a7563819-b54e-40a5-aea6-4a03ca42a643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11679
08631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.1167908631
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.1771664023
Short name T796
Test name
Test status
Simulation time 8453203749 ps
CPU time 8.62 seconds
Started Apr 15 03:13:21 PM PDT 24
Finished Apr 15 03:13:30 PM PDT 24
Peak memory 204044 kb
Host smart-73011e5d-3e54-4749-bf92-15fec1e42458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17716
64023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.1771664023
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.4259796945
Short name T403
Test name
Test status
Simulation time 8414712928 ps
CPU time 8.83 seconds
Started Apr 15 03:13:23 PM PDT 24
Finished Apr 15 03:13:32 PM PDT 24
Peak memory 203992 kb
Host smart-36adfd53-0aaf-40fc-9cfb-da63a0ab5f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42597
96945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.4259796945
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.1574347168
Short name T807
Test name
Test status
Simulation time 8382628893 ps
CPU time 7.89 seconds
Started Apr 15 03:13:22 PM PDT 24
Finished Apr 15 03:13:30 PM PDT 24
Peak memory 204044 kb
Host smart-080af88e-b4a6-42c3-9019-cbaed0e70ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15743
47168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.1574347168
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.4229281725
Short name T96
Test name
Test status
Simulation time 8424526088 ps
CPU time 9.68 seconds
Started Apr 15 03:13:21 PM PDT 24
Finished Apr 15 03:13:31 PM PDT 24
Peak memory 203928 kb
Host smart-ec166eeb-923d-4dfc-866a-e8b21657d58d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42292
81725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.4229281725
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.3918073860
Short name T679
Test name
Test status
Simulation time 8387809777 ps
CPU time 7.97 seconds
Started Apr 15 03:13:23 PM PDT 24
Finished Apr 15 03:13:31 PM PDT 24
Peak memory 204060 kb
Host smart-3e90ddb3-e182-4d16-9ad6-0793d29733f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39180
73860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.3918073860
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.159363589
Short name T663
Test name
Test status
Simulation time 8381646429 ps
CPU time 7.92 seconds
Started Apr 15 03:13:23 PM PDT 24
Finished Apr 15 03:13:32 PM PDT 24
Peak memory 203992 kb
Host smart-5eeafdb9-375b-493f-bc6e-e3c9f6017ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15936
3589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.159363589
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.151380888
Short name T1038
Test name
Test status
Simulation time 8464114926 ps
CPU time 8.25 seconds
Started Apr 15 03:13:25 PM PDT 24
Finished Apr 15 03:13:34 PM PDT 24
Peak memory 204044 kb
Host smart-054489ff-b3fe-4fdb-bd83-51741f8493bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15138
0888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.151380888
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.2548254158
Short name T296
Test name
Test status
Simulation time 8374874061 ps
CPU time 8.13 seconds
Started Apr 15 03:13:25 PM PDT 24
Finished Apr 15 03:13:33 PM PDT 24
Peak memory 204056 kb
Host smart-351e2555-65c1-451b-b9ee-9d56021bce26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25482
54158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.2548254158
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.2521226170
Short name T357
Test name
Test status
Simulation time 77324568 ps
CPU time 0.66 seconds
Started Apr 15 03:13:30 PM PDT 24
Finished Apr 15 03:13:31 PM PDT 24
Peak memory 203900 kb
Host smart-c9fe8993-10e1-4003-9dd4-f801d246557e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25212
26170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.2521226170
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.4075787212
Short name T80
Test name
Test status
Simulation time 30849117223 ps
CPU time 60.72 seconds
Started Apr 15 03:13:22 PM PDT 24
Finished Apr 15 03:14:23 PM PDT 24
Peak memory 204276 kb
Host smart-7eceb80c-ec62-4162-9f1e-88bea3e1edeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40757
87212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.4075787212
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.3175489692
Short name T985
Test name
Test status
Simulation time 8388929941 ps
CPU time 10.5 seconds
Started Apr 15 03:13:20 PM PDT 24
Finished Apr 15 03:13:31 PM PDT 24
Peak memory 204040 kb
Host smart-45edd99d-ee9c-4616-885e-937732c719c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31754
89692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3175489692
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.419436537
Short name T866
Test name
Test status
Simulation time 8418885770 ps
CPU time 8.6 seconds
Started Apr 15 03:13:30 PM PDT 24
Finished Apr 15 03:13:39 PM PDT 24
Peak memory 204024 kb
Host smart-e9bfd6bc-a3fb-4b24-91e9-3649631cb62b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41943
6537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.419436537
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.2543785508
Short name T601
Test name
Test status
Simulation time 8407171143 ps
CPU time 7.88 seconds
Started Apr 15 03:13:26 PM PDT 24
Finished Apr 15 03:13:35 PM PDT 24
Peak memory 204056 kb
Host smart-5a6b4ccf-0793-4c0f-ab61-193167670088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25437
85508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.2543785508
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1564184121
Short name T377
Test name
Test status
Simulation time 8393322800 ps
CPU time 7.57 seconds
Started Apr 15 03:13:24 PM PDT 24
Finished Apr 15 03:13:32 PM PDT 24
Peak memory 203992 kb
Host smart-13f1b39c-3a80-4811-b2bd-c6432f572a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15641
84121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1564184121
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.1184941854
Short name T428
Test name
Test status
Simulation time 8372771547 ps
CPU time 7.89 seconds
Started Apr 15 03:13:28 PM PDT 24
Finished Apr 15 03:13:37 PM PDT 24
Peak memory 204024 kb
Host smart-c33e0dc6-3d06-4e80-94b5-be6c41e8d563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11849
41854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.1184941854
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.3380059194
Short name T1204
Test name
Test status
Simulation time 8400490575 ps
CPU time 8.62 seconds
Started Apr 15 03:13:30 PM PDT 24
Finished Apr 15 03:13:39 PM PDT 24
Peak memory 204020 kb
Host smart-70685140-2a64-4b9a-bd91-94129c94915c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33800
59194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.3380059194
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.142689404
Short name T922
Test name
Test status
Simulation time 8412171916 ps
CPU time 8.31 seconds
Started Apr 15 03:13:26 PM PDT 24
Finished Apr 15 03:13:35 PM PDT 24
Peak memory 203976 kb
Host smart-f4328bfa-b576-4e84-a1a5-08ad471d9d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14268
9404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.142689404
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.2804573389
Short name T879
Test name
Test status
Simulation time 8462833811 ps
CPU time 8.36 seconds
Started Apr 15 03:13:41 PM PDT 24
Finished Apr 15 03:13:50 PM PDT 24
Peak memory 204076 kb
Host smart-731b3b11-6416-4967-bc7f-6dfb2807f7be
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2804573389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.2804573389
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/12.min_length_in_transaction.1013255836
Short name T1213
Test name
Test status
Simulation time 8378672223 ps
CPU time 10.31 seconds
Started Apr 15 03:13:40 PM PDT 24
Finished Apr 15 03:13:51 PM PDT 24
Peak memory 204072 kb
Host smart-986e9bae-3ccf-426a-86f5-46862267b316
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1013255836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.1013255836
Directory /workspace/12.min_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.4023611416
Short name T520
Test name
Test status
Simulation time 8437338754 ps
CPU time 9.34 seconds
Started Apr 15 03:13:44 PM PDT 24
Finished Apr 15 03:13:54 PM PDT 24
Peak memory 204048 kb
Host smart-1329c10f-939f-4f3b-a0b6-762624ce173e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40236
11416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.4023611416
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.3647300669
Short name T685
Test name
Test status
Simulation time 8377715646 ps
CPU time 9.35 seconds
Started Apr 15 03:13:30 PM PDT 24
Finished Apr 15 03:13:40 PM PDT 24
Peak memory 204060 kb
Host smart-0056a0db-fd06-4553-b1da-7b5d868914f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36473
00669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.3647300669
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_enable.3834070922
Short name T1052
Test name
Test status
Simulation time 8421576387 ps
CPU time 7.81 seconds
Started Apr 15 03:14:00 PM PDT 24
Finished Apr 15 03:14:09 PM PDT 24
Peak memory 204048 kb
Host smart-dbb2c9a4-61bc-4dde-9a4f-6da740a90b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38340
70922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.3834070922
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.3553985710
Short name T1024
Test name
Test status
Simulation time 158004119 ps
CPU time 1.46 seconds
Started Apr 15 03:13:33 PM PDT 24
Finished Apr 15 03:13:35 PM PDT 24
Peak memory 204328 kb
Host smart-684fdfe2-b12c-4a4f-8d21-d8dd0ac74d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35539
85710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3553985710
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1329952271
Short name T379
Test name
Test status
Simulation time 8425755827 ps
CPU time 8.42 seconds
Started Apr 15 03:13:28 PM PDT 24
Finished Apr 15 03:13:37 PM PDT 24
Peak memory 204008 kb
Host smart-d878fa1c-5f5e-4cce-b9d4-11f9841a02e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13299
52271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1329952271
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.699355042
Short name T543
Test name
Test status
Simulation time 8380174657 ps
CPU time 8.03 seconds
Started Apr 15 03:13:35 PM PDT 24
Finished Apr 15 03:13:44 PM PDT 24
Peak memory 204020 kb
Host smart-7c36ebd3-64ca-4fc5-b6cd-77533a1ca675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69935
5042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.699355042
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.3312722164
Short name T537
Test name
Test status
Simulation time 8384854072 ps
CPU time 7.56 seconds
Started Apr 15 03:13:36 PM PDT 24
Finished Apr 15 03:13:44 PM PDT 24
Peak memory 204028 kb
Host smart-486959e4-70ba-4eae-9ffd-d06b0563afdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33127
22164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.3312722164
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.233904694
Short name T333
Test name
Test status
Simulation time 8377527101 ps
CPU time 8.09 seconds
Started Apr 15 03:13:32 PM PDT 24
Finished Apr 15 03:13:41 PM PDT 24
Peak memory 204032 kb
Host smart-6d54d321-96c0-401a-8cd7-bc5f14b469b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23390
4694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.233904694
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.867305084
Short name T583
Test name
Test status
Simulation time 8408160487 ps
CPU time 7.96 seconds
Started Apr 15 03:13:37 PM PDT 24
Finished Apr 15 03:13:45 PM PDT 24
Peak memory 204060 kb
Host smart-e7bc706a-2678-46cb-94a7-f6ffd30cca51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86730
5084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.867305084
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.3746563649
Short name T1311
Test name
Test status
Simulation time 8361785101 ps
CPU time 8.28 seconds
Started Apr 15 03:13:36 PM PDT 24
Finished Apr 15 03:13:45 PM PDT 24
Peak memory 204004 kb
Host smart-b461365b-695d-411b-99b7-af6fef9105af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37465
63649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.3746563649
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.3528937366
Short name T1260
Test name
Test status
Simulation time 78277338 ps
CPU time 0.68 seconds
Started Apr 15 03:13:35 PM PDT 24
Finished Apr 15 03:13:36 PM PDT 24
Peak memory 203900 kb
Host smart-0a248b0c-0ba9-4d00-9710-d32c674c5b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35289
37366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.3528937366
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.2317747484
Short name T208
Test name
Test status
Simulation time 14632215198 ps
CPU time 25.29 seconds
Started Apr 15 03:13:33 PM PDT 24
Finished Apr 15 03:13:59 PM PDT 24
Peak memory 204308 kb
Host smart-3041b5e5-9d57-4823-9df9-12781f959598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23177
47484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.2317747484
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.4270279603
Short name T522
Test name
Test status
Simulation time 8399140922 ps
CPU time 9.12 seconds
Started Apr 15 03:13:36 PM PDT 24
Finished Apr 15 03:13:46 PM PDT 24
Peak memory 204028 kb
Host smart-f7705296-fe97-48bf-a640-0785fd7e132c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42702
79603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.4270279603
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.2443924950
Short name T1191
Test name
Test status
Simulation time 8396636512 ps
CPU time 8.41 seconds
Started Apr 15 03:13:35 PM PDT 24
Finished Apr 15 03:13:44 PM PDT 24
Peak memory 204060 kb
Host smart-b95fa03b-66de-484f-8ee9-dc5b2a3f6c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24439
24950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.2443924950
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.2913018255
Short name T523
Test name
Test status
Simulation time 8374120151 ps
CPU time 8.1 seconds
Started Apr 15 03:13:37 PM PDT 24
Finished Apr 15 03:13:46 PM PDT 24
Peak memory 204056 kb
Host smart-d3f448b5-8c09-4058-b6a9-87182855b8eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29130
18255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.2913018255
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.510328970
Short name T891
Test name
Test status
Simulation time 8370860722 ps
CPU time 7.63 seconds
Started Apr 15 03:13:35 PM PDT 24
Finished Apr 15 03:13:44 PM PDT 24
Peak memory 203876 kb
Host smart-ce14964a-dd0e-45be-baf1-338db4c50752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51032
8970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.510328970
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.3146301877
Short name T730
Test name
Test status
Simulation time 8438714530 ps
CPU time 8.26 seconds
Started Apr 15 03:13:31 PM PDT 24
Finished Apr 15 03:13:40 PM PDT 24
Peak memory 203976 kb
Host smart-5c7f71b2-d51c-4d45-a8b5-129fe2ce9121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31463
01877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.3146301877
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.3265968201
Short name T882
Test name
Test status
Simulation time 8394578659 ps
CPU time 7.74 seconds
Started Apr 15 03:13:38 PM PDT 24
Finished Apr 15 03:13:46 PM PDT 24
Peak memory 204040 kb
Host smart-632b5d33-dd3c-4298-81ec-e44bc7b20f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32659
68201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.3265968201
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.1223293483
Short name T1056
Test name
Test status
Simulation time 8412309641 ps
CPU time 9.51 seconds
Started Apr 15 03:13:33 PM PDT 24
Finished Apr 15 03:13:43 PM PDT 24
Peak memory 204052 kb
Host smart-2e8192f3-2d40-4e73-81ee-541f3ac98602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12232
93483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1223293483
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.788922779
Short name T1002
Test name
Test status
Simulation time 8474186552 ps
CPU time 8.33 seconds
Started Apr 15 03:13:48 PM PDT 24
Finished Apr 15 03:13:57 PM PDT 24
Peak memory 204020 kb
Host smart-44dfb2ab-86a4-42eb-a520-d18aa52a922c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=788922779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.788922779
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.4207026263
Short name T440
Test name
Test status
Simulation time 8385169035 ps
CPU time 10.11 seconds
Started Apr 15 03:13:52 PM PDT 24
Finished Apr 15 03:14:03 PM PDT 24
Peak memory 204048 kb
Host smart-f7528bc5-f3a6-4434-87d5-07c649409a74
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4207026263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.4207026263
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.101620507
Short name T420
Test name
Test status
Simulation time 8421672320 ps
CPU time 9.72 seconds
Started Apr 15 03:13:50 PM PDT 24
Finished Apr 15 03:14:00 PM PDT 24
Peak memory 204052 kb
Host smart-8dfdf061-861d-4855-a7e4-2516a21123d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10162
0507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.101620507
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.507500861
Short name T676
Test name
Test status
Simulation time 8379430912 ps
CPU time 8.75 seconds
Started Apr 15 03:13:45 PM PDT 24
Finished Apr 15 03:13:55 PM PDT 24
Peak memory 204044 kb
Host smart-697ff2ac-f357-4122-b91f-b78df1f5c9ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50750
0861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.507500861
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_enable.1545470632
Short name T848
Test name
Test status
Simulation time 8385100821 ps
CPU time 7.34 seconds
Started Apr 15 03:13:44 PM PDT 24
Finished Apr 15 03:13:52 PM PDT 24
Peak memory 203928 kb
Host smart-2bf194dc-cf93-4578-845e-9fe44cecaef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15454
70632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.1545470632
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.3781033326
Short name T324
Test name
Test status
Simulation time 73869380 ps
CPU time 1.8 seconds
Started Apr 15 03:13:51 PM PDT 24
Finished Apr 15 03:13:54 PM PDT 24
Peak memory 204172 kb
Host smart-8f4eea03-5d74-406f-9bd7-a4f47b1599ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37810
33326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.3781033326
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.2648094076
Short name T1159
Test name
Test status
Simulation time 8454388858 ps
CPU time 8.09 seconds
Started Apr 15 03:13:53 PM PDT 24
Finished Apr 15 03:14:02 PM PDT 24
Peak memory 203996 kb
Host smart-9d283472-6ff7-466f-917b-b781343857d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26480
94076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.2648094076
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.244028619
Short name T120
Test name
Test status
Simulation time 8409495061 ps
CPU time 7.87 seconds
Started Apr 15 03:13:46 PM PDT 24
Finished Apr 15 03:13:55 PM PDT 24
Peak memory 203976 kb
Host smart-ecc40f67-e788-40a4-9c7f-82d268b317ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24402
8619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.244028619
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.2059395801
Short name T1108
Test name
Test status
Simulation time 8494998404 ps
CPU time 10.35 seconds
Started Apr 15 03:13:44 PM PDT 24
Finished Apr 15 03:13:56 PM PDT 24
Peak memory 204036 kb
Host smart-fbd5caa7-2b19-4cfa-b202-e4eb5ef6b9b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20593
95801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.2059395801
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.1824041238
Short name T860
Test name
Test status
Simulation time 8376310591 ps
CPU time 8.1 seconds
Started Apr 15 03:13:50 PM PDT 24
Finished Apr 15 03:13:59 PM PDT 24
Peak memory 204044 kb
Host smart-58c3f734-1fea-4336-8d62-b2f08b25e7da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18240
41238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.1824041238
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.338985064
Short name T102
Test name
Test status
Simulation time 8450995701 ps
CPU time 7.45 seconds
Started Apr 15 03:13:50 PM PDT 24
Finished Apr 15 03:13:58 PM PDT 24
Peak memory 204044 kb
Host smart-0ed7111b-5bd1-4046-acce-5da5aa2b4902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33898
5064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.338985064
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1038613876
Short name T1324
Test name
Test status
Simulation time 8422621931 ps
CPU time 7.76 seconds
Started Apr 15 03:13:51 PM PDT 24
Finished Apr 15 03:14:00 PM PDT 24
Peak memory 204044 kb
Host smart-3a633df7-5d2e-4cfb-9f97-52aed854541f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10386
13876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1038613876
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1919782852
Short name T1078
Test name
Test status
Simulation time 8382536883 ps
CPU time 8.14 seconds
Started Apr 15 03:13:51 PM PDT 24
Finished Apr 15 03:14:00 PM PDT 24
Peak memory 204044 kb
Host smart-d1fcfa38-baef-4c92-aa67-17c58da2c5f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19197
82852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1919782852
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.4234859617
Short name T1371
Test name
Test status
Simulation time 8390331973 ps
CPU time 7.83 seconds
Started Apr 15 03:13:52 PM PDT 24
Finished Apr 15 03:14:00 PM PDT 24
Peak memory 204044 kb
Host smart-dcc72850-86fe-4b02-8bf3-52d1e919031e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42348
59617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.4234859617
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.4110699831
Short name T914
Test name
Test status
Simulation time 8374574986 ps
CPU time 7.9 seconds
Started Apr 15 03:13:50 PM PDT 24
Finished Apr 15 03:13:58 PM PDT 24
Peak memory 204048 kb
Host smart-76e7d4a2-8422-41cd-af5d-e0d30a786273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41106
99831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.4110699831
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.2349567215
Short name T412
Test name
Test status
Simulation time 42774319 ps
CPU time 0.65 seconds
Started Apr 15 03:13:48 PM PDT 24
Finished Apr 15 03:13:50 PM PDT 24
Peak memory 203944 kb
Host smart-ea04b4e1-ebac-4e5d-a7b6-bbd2eae0589a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23495
67215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.2349567215
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.339746550
Short name T231
Test name
Test status
Simulation time 18679437246 ps
CPU time 35.74 seconds
Started Apr 15 03:13:45 PM PDT 24
Finished Apr 15 03:14:22 PM PDT 24
Peak memory 204344 kb
Host smart-c8c17728-6548-4cef-bf82-5473a6df1b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33974
6550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.339746550
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.4154087834
Short name T939
Test name
Test status
Simulation time 8418574647 ps
CPU time 8.23 seconds
Started Apr 15 03:13:48 PM PDT 24
Finished Apr 15 03:13:57 PM PDT 24
Peak memory 204028 kb
Host smart-4b8d2df9-d932-4807-92ff-b07889241857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41540
87834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.4154087834
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.1537894477
Short name T830
Test name
Test status
Simulation time 8453062011 ps
CPU time 8.07 seconds
Started Apr 15 03:13:48 PM PDT 24
Finished Apr 15 03:13:57 PM PDT 24
Peak memory 204052 kb
Host smart-357abb00-aa1c-46a2-b925-7eecee7efdd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15378
94477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1537894477
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.1028310191
Short name T998
Test name
Test status
Simulation time 8429350276 ps
CPU time 10.51 seconds
Started Apr 15 03:13:44 PM PDT 24
Finished Apr 15 03:13:56 PM PDT 24
Peak memory 204056 kb
Host smart-99b74c98-a112-4681-a396-43aa1c2b1232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10283
10191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.1028310191
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.1736360805
Short name T829
Test name
Test status
Simulation time 8440031307 ps
CPU time 8.22 seconds
Started Apr 15 03:13:47 PM PDT 24
Finished Apr 15 03:13:56 PM PDT 24
Peak memory 204068 kb
Host smart-f0f90a3c-567e-40b2-adbf-9c0ab544dfab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17363
60805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.1736360805
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.3002508545
Short name T975
Test name
Test status
Simulation time 8374461654 ps
CPU time 7.75 seconds
Started Apr 15 03:13:47 PM PDT 24
Finished Apr 15 03:13:56 PM PDT 24
Peak memory 204020 kb
Host smart-e0fdaef7-8337-4dcc-b443-791270dfceb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30025
08545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.3002508545
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.4293131138
Short name T728
Test name
Test status
Simulation time 8402213482 ps
CPU time 9 seconds
Started Apr 15 03:13:52 PM PDT 24
Finished Apr 15 03:14:02 PM PDT 24
Peak memory 204044 kb
Host smart-40c4cf24-1082-4c9b-a7c6-9ab75a66b844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42931
31138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.4293131138
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.486274379
Short name T660
Test name
Test status
Simulation time 8452660976 ps
CPU time 10.45 seconds
Started Apr 15 03:13:46 PM PDT 24
Finished Apr 15 03:13:58 PM PDT 24
Peak memory 203984 kb
Host smart-341f0a43-442c-467e-bc95-5f750d271b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48627
4379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.486274379
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.max_length_in_transaction.1211975583
Short name T2
Test name
Test status
Simulation time 8467574080 ps
CPU time 8.07 seconds
Started Apr 15 03:14:06 PM PDT 24
Finished Apr 15 03:14:15 PM PDT 24
Peak memory 204028 kb
Host smart-26c83810-45a1-433a-967d-b14a0815fff0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1211975583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.1211975583
Directory /workspace/14.max_length_in_transaction/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.4159867245
Short name T1135
Test name
Test status
Simulation time 8387306985 ps
CPU time 8.88 seconds
Started Apr 15 03:14:03 PM PDT 24
Finished Apr 15 03:14:13 PM PDT 24
Peak memory 204060 kb
Host smart-af88217b-22b6-4031-a57a-43c98b95294d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4159867245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.4159867245
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.1834762706
Short name T709
Test name
Test status
Simulation time 8456727666 ps
CPU time 7.78 seconds
Started Apr 15 03:14:04 PM PDT 24
Finished Apr 15 03:14:13 PM PDT 24
Peak memory 204076 kb
Host smart-d70bdec4-3757-4cec-95b4-c5e20d9a5dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18347
62706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.1834762706
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.678510533
Short name T1152
Test name
Test status
Simulation time 8370013023 ps
CPU time 9.21 seconds
Started Apr 15 03:13:51 PM PDT 24
Finished Apr 15 03:14:01 PM PDT 24
Peak memory 204024 kb
Host smart-444bcbe0-365c-484c-94bc-2ca71e795226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67851
0533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.678510533
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.1116931195
Short name T719
Test name
Test status
Simulation time 153351495 ps
CPU time 1.87 seconds
Started Apr 15 03:13:52 PM PDT 24
Finished Apr 15 03:13:54 PM PDT 24
Peak memory 204172 kb
Host smart-ea7b7681-1a03-49d0-9f90-ea4f240cfadc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11169
31195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.1116931195
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.649755798
Short name T1312
Test name
Test status
Simulation time 8414320333 ps
CPU time 7.94 seconds
Started Apr 15 03:13:58 PM PDT 24
Finished Apr 15 03:14:06 PM PDT 24
Peak memory 204020 kb
Host smart-9c8fc84c-a1be-4a2e-a00e-445d8b5c9bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64975
5798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.649755798
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.296174884
Short name T423
Test name
Test status
Simulation time 8465282760 ps
CPU time 8.26 seconds
Started Apr 15 03:13:52 PM PDT 24
Finished Apr 15 03:14:01 PM PDT 24
Peak memory 204068 kb
Host smart-c25489e4-2d52-40ff-9fda-b3170b8f5469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29617
4884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.296174884
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.2142293295
Short name T226
Test name
Test status
Simulation time 8420416768 ps
CPU time 9.27 seconds
Started Apr 15 03:13:52 PM PDT 24
Finished Apr 15 03:14:02 PM PDT 24
Peak memory 203984 kb
Host smart-a7c56610-5541-4ad5-8fae-bb2b3e7b68f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21422
93295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.2142293295
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.927336618
Short name T326
Test name
Test status
Simulation time 8381997983 ps
CPU time 8.18 seconds
Started Apr 15 03:13:57 PM PDT 24
Finished Apr 15 03:14:05 PM PDT 24
Peak memory 204052 kb
Host smart-f94e2e10-cf6f-4d34-9e75-2fff7f2a979f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92733
6618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.927336618
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.3953191912
Short name T1079
Test name
Test status
Simulation time 8431511635 ps
CPU time 8.22 seconds
Started Apr 15 03:13:59 PM PDT 24
Finished Apr 15 03:14:07 PM PDT 24
Peak memory 204024 kb
Host smart-231b7e57-6e5d-4eac-964f-32adbc7a4a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39531
91912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3953191912
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1481673646
Short name T398
Test name
Test status
Simulation time 8375025133 ps
CPU time 8.19 seconds
Started Apr 15 03:13:55 PM PDT 24
Finished Apr 15 03:14:04 PM PDT 24
Peak memory 204024 kb
Host smart-c57f2e1f-85f4-4ce0-9aaa-97db48d72caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14816
73646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1481673646
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2248972558
Short name T384
Test name
Test status
Simulation time 8415129421 ps
CPU time 7.99 seconds
Started Apr 15 03:13:55 PM PDT 24
Finished Apr 15 03:14:04 PM PDT 24
Peak memory 203984 kb
Host smart-0175a30d-0a0b-4245-91de-948f3da82b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22489
72558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2248972558
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.1791728025
Short name T693
Test name
Test status
Simulation time 8372501060 ps
CPU time 8.11 seconds
Started Apr 15 03:14:00 PM PDT 24
Finished Apr 15 03:14:09 PM PDT 24
Peak memory 204068 kb
Host smart-73c6acd0-91a1-4f06-9323-f7cbd00a234c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17917
28025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.1791728025
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.4239030845
Short name T1289
Test name
Test status
Simulation time 43144535 ps
CPU time 0.68 seconds
Started Apr 15 03:13:59 PM PDT 24
Finished Apr 15 03:14:01 PM PDT 24
Peak memory 203908 kb
Host smart-6e07a33c-a96f-463f-bf0c-bb7e1b1fab04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42390
30845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.4239030845
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.1528696367
Short name T1106
Test name
Test status
Simulation time 14471927787 ps
CPU time 25.34 seconds
Started Apr 15 03:13:55 PM PDT 24
Finished Apr 15 03:14:20 PM PDT 24
Peak memory 204348 kb
Host smart-5a330fbe-4cd8-4bd6-8629-797f3f7508d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15286
96367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.1528696367
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.2257835234
Short name T1268
Test name
Test status
Simulation time 8416698672 ps
CPU time 8.3 seconds
Started Apr 15 03:14:01 PM PDT 24
Finished Apr 15 03:14:10 PM PDT 24
Peak memory 204060 kb
Host smart-82b63fab-fb08-48a7-9852-d0e2e64f6e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22578
35234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.2257835234
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.2278329897
Short name T746
Test name
Test status
Simulation time 8400535479 ps
CPU time 8.95 seconds
Started Apr 15 03:13:59 PM PDT 24
Finished Apr 15 03:14:09 PM PDT 24
Peak memory 204052 kb
Host smart-2019d9b0-a816-40d7-b149-488354f9fe25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22783
29897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.2278329897
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.216529085
Short name T642
Test name
Test status
Simulation time 8409057835 ps
CPU time 9.38 seconds
Started Apr 15 03:14:02 PM PDT 24
Finished Apr 15 03:14:12 PM PDT 24
Peak memory 204064 kb
Host smart-1e515c9d-5295-49f5-b833-32ef687f5e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21652
9085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.216529085
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.3274226334
Short name T1198
Test name
Test status
Simulation time 8376364499 ps
CPU time 8.45 seconds
Started Apr 15 03:13:59 PM PDT 24
Finished Apr 15 03:14:08 PM PDT 24
Peak memory 204080 kb
Host smart-d57066e3-4dcd-407b-aea4-05bfc76c8ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32742
26334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.3274226334
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.157848328
Short name T395
Test name
Test status
Simulation time 8360987629 ps
CPU time 8.32 seconds
Started Apr 15 03:13:59 PM PDT 24
Finished Apr 15 03:14:08 PM PDT 24
Peak memory 204048 kb
Host smart-814539a1-ffac-4045-8d22-36cc0dd9788a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15784
8328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.157848328
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2032338752
Short name T1309
Test name
Test status
Simulation time 8393943850 ps
CPU time 8.05 seconds
Started Apr 15 03:13:58 PM PDT 24
Finished Apr 15 03:14:07 PM PDT 24
Peak memory 203876 kb
Host smart-4d2b4d6f-c72b-475f-8314-463efc5f15b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20323
38752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2032338752
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.1589719060
Short name T869
Test name
Test status
Simulation time 8403794633 ps
CPU time 8.88 seconds
Started Apr 15 03:14:00 PM PDT 24
Finished Apr 15 03:14:10 PM PDT 24
Peak memory 204024 kb
Host smart-d1858437-bcd3-4723-b153-b1edf9020c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15897
19060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.1589719060
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.918348606
Short name T567
Test name
Test status
Simulation time 8463951874 ps
CPU time 8.09 seconds
Started Apr 15 03:14:12 PM PDT 24
Finished Apr 15 03:14:20 PM PDT 24
Peak memory 203968 kb
Host smart-bd590fec-41c0-4c39-b553-3d871caedbeb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=918348606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.918348606
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.3277537743
Short name T750
Test name
Test status
Simulation time 8376740273 ps
CPU time 8.8 seconds
Started Apr 15 03:14:12 PM PDT 24
Finished Apr 15 03:14:22 PM PDT 24
Peak memory 204052 kb
Host smart-03f4a09b-a678-424e-a9f5-f402b22f47ce
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3277537743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.3277537743
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.2994654867
Short name T657
Test name
Test status
Simulation time 8410249763 ps
CPU time 7.89 seconds
Started Apr 15 03:14:12 PM PDT 24
Finished Apr 15 03:14:20 PM PDT 24
Peak memory 204056 kb
Host smart-fc7628a3-29df-442c-88c8-6d275fc515e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29946
54867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.2994654867
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.1300927696
Short name T524
Test name
Test status
Simulation time 8378690961 ps
CPU time 8.35 seconds
Started Apr 15 03:14:08 PM PDT 24
Finished Apr 15 03:14:18 PM PDT 24
Peak memory 204052 kb
Host smart-a8e37387-2eea-4d86-b6d9-23e229e7cfeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13009
27696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.1300927696
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_enable.1631127055
Short name T818
Test name
Test status
Simulation time 8386032003 ps
CPU time 7.53 seconds
Started Apr 15 03:14:07 PM PDT 24
Finished Apr 15 03:14:15 PM PDT 24
Peak memory 204024 kb
Host smart-6fc8d640-794d-4488-8260-0dd4c481ec70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16311
27055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.1631127055
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.519237035
Short name T334
Test name
Test status
Simulation time 267893291 ps
CPU time 2.11 seconds
Started Apr 15 03:14:04 PM PDT 24
Finished Apr 15 03:14:07 PM PDT 24
Peak memory 204132 kb
Host smart-89a6fa5c-c62e-405c-849f-520630cb6305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51923
7035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.519237035
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.1350552192
Short name T451
Test name
Test status
Simulation time 8455084052 ps
CPU time 8.38 seconds
Started Apr 15 03:14:11 PM PDT 24
Finished Apr 15 03:14:19 PM PDT 24
Peak memory 204044 kb
Host smart-f8ea1379-05c4-41e9-b3f5-5b05ae60653f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13505
52192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.1350552192
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.2356251848
Short name T570
Test name
Test status
Simulation time 8366807146 ps
CPU time 8.71 seconds
Started Apr 15 03:14:17 PM PDT 24
Finished Apr 15 03:14:26 PM PDT 24
Peak memory 204200 kb
Host smart-c690d684-b7de-4583-bb08-0648c3a54c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23562
51848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.2356251848
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.4271168926
Short name T1257
Test name
Test status
Simulation time 8424575281 ps
CPU time 9.85 seconds
Started Apr 15 03:14:11 PM PDT 24
Finished Apr 15 03:14:22 PM PDT 24
Peak memory 204012 kb
Host smart-20cbc59f-89f2-480d-9a4e-653fd273597b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42711
68926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.4271168926
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.541775666
Short name T406
Test name
Test status
Simulation time 8432640209 ps
CPU time 8.42 seconds
Started Apr 15 03:14:04 PM PDT 24
Finished Apr 15 03:14:13 PM PDT 24
Peak memory 203976 kb
Host smart-17d3a5ff-0809-4995-bd1d-3173b2c2c3e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54177
5666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.541775666
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.2054776955
Short name T627
Test name
Test status
Simulation time 8455658847 ps
CPU time 8.36 seconds
Started Apr 15 03:14:08 PM PDT 24
Finished Apr 15 03:14:17 PM PDT 24
Peak memory 204056 kb
Host smart-63ac97eb-87e9-4645-a8df-df155a5e494f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20547
76955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.2054776955
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.4234998294
Short name T101
Test name
Test status
Simulation time 8415640002 ps
CPU time 9.34 seconds
Started Apr 15 03:14:08 PM PDT 24
Finished Apr 15 03:14:18 PM PDT 24
Peak memory 204052 kb
Host smart-797a130f-620e-412c-9e68-a24e3bc13d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42349
98294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.4234998294
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.969674064
Short name T1080
Test name
Test status
Simulation time 8406650575 ps
CPU time 8.37 seconds
Started Apr 15 03:14:07 PM PDT 24
Finished Apr 15 03:14:16 PM PDT 24
Peak memory 204024 kb
Host smart-8b5b3f26-59bd-4f4c-9eef-f09f3a20a800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96967
4064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.969674064
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.3994889380
Short name T600
Test name
Test status
Simulation time 8390054854 ps
CPU time 7.78 seconds
Started Apr 15 03:14:06 PM PDT 24
Finished Apr 15 03:14:15 PM PDT 24
Peak memory 204068 kb
Host smart-4e2d5f18-a675-48e2-bffb-39716d5cac4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39948
89380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.3994889380
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.3521411756
Short name T1202
Test name
Test status
Simulation time 8382995084 ps
CPU time 8.42 seconds
Started Apr 15 03:14:08 PM PDT 24
Finished Apr 15 03:14:17 PM PDT 24
Peak memory 204200 kb
Host smart-57d9657c-08e8-44fc-9952-96f8455a748d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35214
11756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.3521411756
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.2425082881
Short name T8
Test name
Test status
Simulation time 8384462937 ps
CPU time 8.5 seconds
Started Apr 15 03:14:07 PM PDT 24
Finished Apr 15 03:14:16 PM PDT 24
Peak memory 204024 kb
Host smart-cfd49176-fdc3-4fd8-bbe0-d55572623d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24250
82881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.2425082881
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3350060965
Short name T929
Test name
Test status
Simulation time 34023614 ps
CPU time 0.66 seconds
Started Apr 15 03:14:11 PM PDT 24
Finished Apr 15 03:14:12 PM PDT 24
Peak memory 203928 kb
Host smart-e2db1740-534b-43e4-8c11-e1ff7fa21562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33500
60965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3350060965
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.3466904990
Short name T707
Test name
Test status
Simulation time 19817187345 ps
CPU time 35.95 seconds
Started Apr 15 03:14:14 PM PDT 24
Finished Apr 15 03:14:50 PM PDT 24
Peak memory 204484 kb
Host smart-3589948e-a15d-4aa8-897f-9277eb4a6602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34669
04990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.3466904990
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.1009056835
Short name T1200
Test name
Test status
Simulation time 8389356758 ps
CPU time 8.74 seconds
Started Apr 15 03:14:07 PM PDT 24
Finished Apr 15 03:14:16 PM PDT 24
Peak memory 204040 kb
Host smart-51a5bd7e-10ed-42bf-9d75-da08f740089e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10090
56835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.1009056835
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.382743065
Short name T477
Test name
Test status
Simulation time 8416133399 ps
CPU time 8.81 seconds
Started Apr 15 03:14:07 PM PDT 24
Finished Apr 15 03:14:17 PM PDT 24
Peak memory 204028 kb
Host smart-2afcead7-12fa-466b-ae9e-7af15b0e59d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38274
3065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.382743065
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.840126033
Short name T572
Test name
Test status
Simulation time 8400231310 ps
CPU time 8.08 seconds
Started Apr 15 03:14:08 PM PDT 24
Finished Apr 15 03:14:17 PM PDT 24
Peak memory 204072 kb
Host smart-0dde9bed-4599-43b5-ab86-81241e2e4d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84012
6033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.840126033
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.1308380443
Short name T1318
Test name
Test status
Simulation time 8378976348 ps
CPU time 7.85 seconds
Started Apr 15 03:14:08 PM PDT 24
Finished Apr 15 03:14:17 PM PDT 24
Peak memory 204072 kb
Host smart-6291dea6-5045-49fc-9053-c317f6845d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13083
80443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.1308380443
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.1909577876
Short name T647
Test name
Test status
Simulation time 8371946958 ps
CPU time 9.09 seconds
Started Apr 15 03:14:08 PM PDT 24
Finished Apr 15 03:14:18 PM PDT 24
Peak memory 203984 kb
Host smart-eed18d56-f464-4b64-a0a3-2d7861f94364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19095
77876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.1909577876
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3778819610
Short name T1216
Test name
Test status
Simulation time 8469335886 ps
CPU time 8.09 seconds
Started Apr 15 03:14:07 PM PDT 24
Finished Apr 15 03:14:16 PM PDT 24
Peak memory 204020 kb
Host smart-eb3ba993-d797-4a12-afd0-27c91f130784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37788
19610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3778819610
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.106737979
Short name T1098
Test name
Test status
Simulation time 8453019497 ps
CPU time 7.98 seconds
Started Apr 15 03:14:07 PM PDT 24
Finished Apr 15 03:14:16 PM PDT 24
Peak memory 204044 kb
Host smart-111cf0da-e546-490f-9ed0-68d72bc1ac70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10673
7979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.106737979
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.755294440
Short name T1218
Test name
Test status
Simulation time 8387914127 ps
CPU time 8.24 seconds
Started Apr 15 03:14:08 PM PDT 24
Finished Apr 15 03:14:17 PM PDT 24
Peak memory 203988 kb
Host smart-c497e54f-3bde-4997-9ab9-7ed4af98f366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75529
4440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.755294440
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.2298261835
Short name T1250
Test name
Test status
Simulation time 8464491437 ps
CPU time 8.38 seconds
Started Apr 15 03:14:23 PM PDT 24
Finished Apr 15 03:14:32 PM PDT 24
Peak memory 204044 kb
Host smart-12c8ae88-51ee-4659-9739-9aed2fee9a29
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2298261835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.2298261835
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.min_length_in_transaction.2045660601
Short name T1012
Test name
Test status
Simulation time 8377158520 ps
CPU time 8.43 seconds
Started Apr 15 03:14:52 PM PDT 24
Finished Apr 15 03:15:01 PM PDT 24
Peak memory 204012 kb
Host smart-32e03096-ebd6-436f-9978-4e485106154b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2045660601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.2045660601
Directory /workspace/16.min_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.2508921087
Short name T1284
Test name
Test status
Simulation time 8431445216 ps
CPU time 9.26 seconds
Started Apr 15 03:14:20 PM PDT 24
Finished Apr 15 03:14:31 PM PDT 24
Peak memory 203880 kb
Host smart-c6aa7be1-ecd3-4b2d-bc4c-5fe4e7c1a42d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25089
21087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.2508921087
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2511546893
Short name T1043
Test name
Test status
Simulation time 8412644566 ps
CPU time 7.58 seconds
Started Apr 15 03:14:14 PM PDT 24
Finished Apr 15 03:14:22 PM PDT 24
Peak memory 204028 kb
Host smart-104e883c-0f0d-445d-b833-593f7e7093fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25115
46893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2511546893
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_enable.1779071410
Short name T1190
Test name
Test status
Simulation time 8370194146 ps
CPU time 8.92 seconds
Started Apr 15 03:14:14 PM PDT 24
Finished Apr 15 03:14:24 PM PDT 24
Peak memory 204048 kb
Host smart-1799b981-5a5f-4538-9ff8-0e66c3545261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17790
71410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1779071410
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.4221414360
Short name T419
Test name
Test status
Simulation time 71484040 ps
CPU time 1.76 seconds
Started Apr 15 03:14:15 PM PDT 24
Finished Apr 15 03:14:17 PM PDT 24
Peak memory 204136 kb
Host smart-d5de1ded-65c2-46f7-ba68-7d1885c1c775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42214
14360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.4221414360
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.1901470089
Short name T1352
Test name
Test status
Simulation time 8444704451 ps
CPU time 7.76 seconds
Started Apr 15 03:14:23 PM PDT 24
Finished Apr 15 03:14:32 PM PDT 24
Peak memory 204044 kb
Host smart-2c8b46f1-35b4-40e1-bf0a-50d828fe8b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19014
70089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.1901470089
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.3882203206
Short name T1077
Test name
Test status
Simulation time 8370227153 ps
CPU time 8.58 seconds
Started Apr 15 03:14:18 PM PDT 24
Finished Apr 15 03:14:28 PM PDT 24
Peak memory 204056 kb
Host smart-497f4e8c-94a6-4c5b-9fb3-c084a6a6da9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38822
03206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.3882203206
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.1402411740
Short name T416
Test name
Test status
Simulation time 8407112395 ps
CPU time 8.18 seconds
Started Apr 15 03:14:19 PM PDT 24
Finished Apr 15 03:14:29 PM PDT 24
Peak memory 204020 kb
Host smart-04f36d51-17e2-4089-94b1-59f0091f7c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14024
11740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.1402411740
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.1912924452
Short name T441
Test name
Test status
Simulation time 8434613225 ps
CPU time 7.64 seconds
Started Apr 15 03:14:15 PM PDT 24
Finished Apr 15 03:14:23 PM PDT 24
Peak memory 203988 kb
Host smart-16919189-c1ec-4c09-b390-8ed765f88424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19129
24452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1912924452
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3317436723
Short name T952
Test name
Test status
Simulation time 8380592236 ps
CPU time 8.13 seconds
Started Apr 15 03:14:15 PM PDT 24
Finished Apr 15 03:14:24 PM PDT 24
Peak memory 204060 kb
Host smart-df5c501c-2e7f-4284-a4e4-1d679b36e67f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33174
36723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3317436723
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.742443892
Short name T609
Test name
Test status
Simulation time 8427770066 ps
CPU time 8.84 seconds
Started Apr 15 03:14:15 PM PDT 24
Finished Apr 15 03:14:24 PM PDT 24
Peak memory 203996 kb
Host smart-870ee8e0-6dd8-436a-9a15-973d816305af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74244
3892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.742443892
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.2501762901
Short name T434
Test name
Test status
Simulation time 8445908661 ps
CPU time 9.61 seconds
Started Apr 15 03:14:16 PM PDT 24
Finished Apr 15 03:14:26 PM PDT 24
Peak memory 203992 kb
Host smart-8cb53200-1b59-4430-b138-496eab7cc9f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25017
62901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.2501762901
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.967449591
Short name T703
Test name
Test status
Simulation time 8374247357 ps
CPU time 8.54 seconds
Started Apr 15 03:14:19 PM PDT 24
Finished Apr 15 03:14:29 PM PDT 24
Peak memory 204028 kb
Host smart-2b1a4aa9-6778-4c61-93f0-5da25b25df6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96744
9591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.967449591
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.1805659131
Short name T982
Test name
Test status
Simulation time 8364430875 ps
CPU time 9.05 seconds
Started Apr 15 03:14:17 PM PDT 24
Finished Apr 15 03:14:27 PM PDT 24
Peak memory 204004 kb
Host smart-20df5dcd-73d5-47f7-a8b6-ce168234aa1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18056
59131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.1805659131
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.4064249656
Short name T553
Test name
Test status
Simulation time 29527159 ps
CPU time 0.66 seconds
Started Apr 15 03:14:17 PM PDT 24
Finished Apr 15 03:14:19 PM PDT 24
Peak memory 203924 kb
Host smart-86330675-e4e8-43ed-98d9-dd2a6865ffe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40642
49656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.4064249656
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.2741159823
Short name T838
Test name
Test status
Simulation time 22286955921 ps
CPU time 48.71 seconds
Started Apr 15 03:14:18 PM PDT 24
Finished Apr 15 03:15:07 PM PDT 24
Peak memory 204276 kb
Host smart-fcf7b3f0-6cbf-4d83-8020-ea7d6b0d5e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27411
59823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.2741159823
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.2582039426
Short name T951
Test name
Test status
Simulation time 8407175576 ps
CPU time 8.04 seconds
Started Apr 15 03:14:18 PM PDT 24
Finished Apr 15 03:14:27 PM PDT 24
Peak memory 204028 kb
Host smart-58be1b9f-0130-4452-abfe-6dc05a986ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25820
39426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.2582039426
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.965232651
Short name T1177
Test name
Test status
Simulation time 8424654733 ps
CPU time 8.2 seconds
Started Apr 15 03:14:20 PM PDT 24
Finished Apr 15 03:14:29 PM PDT 24
Peak memory 203976 kb
Host smart-96efdd2b-6a60-427d-af65-b0c85e8ef96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96523
2651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.965232651
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.3072363271
Short name T545
Test name
Test status
Simulation time 8481847369 ps
CPU time 9.01 seconds
Started Apr 15 03:14:17 PM PDT 24
Finished Apr 15 03:14:27 PM PDT 24
Peak memory 204044 kb
Host smart-cef14f7f-71c5-41cc-9fb3-f317b9b8c46f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30723
63271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.3072363271
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.431552173
Short name T437
Test name
Test status
Simulation time 8372836785 ps
CPU time 7.95 seconds
Started Apr 15 03:14:21 PM PDT 24
Finished Apr 15 03:14:30 PM PDT 24
Peak memory 204040 kb
Host smart-ef4af912-d9da-4aaf-b8fb-afaa88935c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43155
2173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.431552173
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.3672932703
Short name T432
Test name
Test status
Simulation time 8392008795 ps
CPU time 10.38 seconds
Started Apr 15 03:14:21 PM PDT 24
Finished Apr 15 03:14:32 PM PDT 24
Peak memory 204040 kb
Host smart-122b8833-dd93-46d5-a322-a58b1f84a456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36729
32703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.3672932703
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.2920520631
Short name T867
Test name
Test status
Simulation time 8496227469 ps
CPU time 8.24 seconds
Started Apr 15 03:14:10 PM PDT 24
Finished Apr 15 03:14:19 PM PDT 24
Peak memory 204032 kb
Host smart-1cb8311f-3f0c-44f5-a6fd-5dfeed02b37f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29205
20631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2920520631
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.197370798
Short name T950
Test name
Test status
Simulation time 8400187840 ps
CPU time 8.25 seconds
Started Apr 15 03:14:17 PM PDT 24
Finished Apr 15 03:14:26 PM PDT 24
Peak memory 204052 kb
Host smart-2fb14029-47ec-4614-beb6-7cfd6b3bb4a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19737
0798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.197370798
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.3590295639
Short name T1237
Test name
Test status
Simulation time 8392025486 ps
CPU time 8.42 seconds
Started Apr 15 03:14:20 PM PDT 24
Finished Apr 15 03:14:30 PM PDT 24
Peak memory 204028 kb
Host smart-450c8b7c-55fa-496f-9932-ec030b5184b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35902
95639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.3590295639
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.max_length_in_transaction.748057755
Short name T47
Test name
Test status
Simulation time 8469487935 ps
CPU time 8.12 seconds
Started Apr 15 03:14:35 PM PDT 24
Finished Apr 15 03:14:44 PM PDT 24
Peak memory 204064 kb
Host smart-7b219856-2eb3-4e44-914a-621a1f92a469
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=748057755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.748057755
Directory /workspace/17.max_length_in_transaction/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.1826336564
Short name T1013
Test name
Test status
Simulation time 8421925703 ps
CPU time 8.09 seconds
Started Apr 15 03:14:35 PM PDT 24
Finished Apr 15 03:14:44 PM PDT 24
Peak memory 203980 kb
Host smart-c3131484-923d-430e-9571-2c2b7eebc291
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1826336564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.1826336564
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.92707266
Short name T953
Test name
Test status
Simulation time 8481821471 ps
CPU time 8.63 seconds
Started Apr 15 03:14:31 PM PDT 24
Finished Apr 15 03:14:41 PM PDT 24
Peak memory 203984 kb
Host smart-9124aec1-a7ce-4e70-9377-24e71848dbdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92707
266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.92707266
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.2595285603
Short name T808
Test name
Test status
Simulation time 8377486583 ps
CPU time 8.91 seconds
Started Apr 15 03:14:31 PM PDT 24
Finished Apr 15 03:14:40 PM PDT 24
Peak memory 203992 kb
Host smart-f3c5f5c3-bfee-406d-a0e4-a69a795e2419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25952
85603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.2595285603
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_enable.1041832361
Short name T1091
Test name
Test status
Simulation time 8439904790 ps
CPU time 7.82 seconds
Started Apr 15 03:14:26 PM PDT 24
Finished Apr 15 03:14:35 PM PDT 24
Peak memory 204076 kb
Host smart-3c16c0dd-4a2b-4c5f-9a9c-3608917a84dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10418
32361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.1041832361
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.2326885415
Short name T1125
Test name
Test status
Simulation time 46664513 ps
CPU time 1.15 seconds
Started Apr 15 03:14:27 PM PDT 24
Finished Apr 15 03:14:28 PM PDT 24
Peak memory 204180 kb
Host smart-23e17254-c010-4cc0-977a-680054cd6e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23268
85415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.2326885415
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.2148305595
Short name T800
Test name
Test status
Simulation time 8442864266 ps
CPU time 7.92 seconds
Started Apr 15 03:14:31 PM PDT 24
Finished Apr 15 03:14:39 PM PDT 24
Peak memory 204048 kb
Host smart-c7f4fcc3-8ae9-426e-b1df-50c75510e0e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21483
05595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.2148305595
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.3993393244
Short name T1057
Test name
Test status
Simulation time 8422004970 ps
CPU time 8.22 seconds
Started Apr 15 03:14:27 PM PDT 24
Finished Apr 15 03:14:36 PM PDT 24
Peak memory 204000 kb
Host smart-dec98df9-8b0f-44ad-b937-22c3437caf32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39933
93244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.3993393244
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.3738247485
Short name T402
Test name
Test status
Simulation time 8450109827 ps
CPU time 7.41 seconds
Started Apr 15 03:14:31 PM PDT 24
Finished Apr 15 03:14:39 PM PDT 24
Peak memory 203996 kb
Host smart-7be9bd35-69c1-49a4-a0e7-805663c3e4e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37382
47485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.3738247485
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.1678927777
Short name T85
Test name
Test status
Simulation time 8434954210 ps
CPU time 7.57 seconds
Started Apr 15 03:14:27 PM PDT 24
Finished Apr 15 03:14:35 PM PDT 24
Peak memory 204044 kb
Host smart-b0e432aa-e581-4b6e-8cab-bdc38bbd31ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16789
27777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.1678927777
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.2316008909
Short name T1327
Test name
Test status
Simulation time 8393096217 ps
CPU time 8.71 seconds
Started Apr 15 03:14:29 PM PDT 24
Finished Apr 15 03:14:38 PM PDT 24
Peak memory 204068 kb
Host smart-1bef99da-3f02-49d5-b8cc-f1f684943439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23160
08909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2316008909
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1049953426
Short name T1366
Test name
Test status
Simulation time 8408484902 ps
CPU time 8.21 seconds
Started Apr 15 03:14:30 PM PDT 24
Finished Apr 15 03:14:38 PM PDT 24
Peak memory 204048 kb
Host smart-ac64a516-fa69-4bd3-b843-be43606af97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10499
53426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1049953426
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.4070101496
Short name T559
Test name
Test status
Simulation time 8392462474 ps
CPU time 8.84 seconds
Started Apr 15 03:14:32 PM PDT 24
Finished Apr 15 03:14:42 PM PDT 24
Peak memory 203988 kb
Host smart-ecd03195-3a96-4a6d-bf6b-de735f93ecc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40701
01496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.4070101496
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.1968680524
Short name T490
Test name
Test status
Simulation time 8367559142 ps
CPU time 7.65 seconds
Started Apr 15 03:14:32 PM PDT 24
Finished Apr 15 03:14:40 PM PDT 24
Peak memory 203924 kb
Host smart-99fecbb4-c67a-4d1c-8e67-c8e3ef0b44f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19686
80524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.1968680524
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.1104408411
Short name T804
Test name
Test status
Simulation time 35398750 ps
CPU time 0.63 seconds
Started Apr 15 03:14:30 PM PDT 24
Finished Apr 15 03:14:31 PM PDT 24
Peak memory 203920 kb
Host smart-0624e20f-a634-4e7c-88e1-5de92d62ad1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11044
08411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.1104408411
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.1275111257
Short name T1054
Test name
Test status
Simulation time 25783940326 ps
CPU time 46.9 seconds
Started Apr 15 03:14:29 PM PDT 24
Finished Apr 15 03:15:16 PM PDT 24
Peak memory 204284 kb
Host smart-0cafef50-9bac-4b7a-9ab8-558eab8cf2ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12751
11257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.1275111257
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.2508541625
Short name T739
Test name
Test status
Simulation time 8381068871 ps
CPU time 9.24 seconds
Started Apr 15 03:14:32 PM PDT 24
Finished Apr 15 03:14:41 PM PDT 24
Peak memory 204028 kb
Host smart-447d6326-33d5-42e4-aed7-ad6622c4c542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25085
41625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.2508541625
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.2559945078
Short name T128
Test name
Test status
Simulation time 8490903852 ps
CPU time 8.23 seconds
Started Apr 15 03:14:30 PM PDT 24
Finished Apr 15 03:14:39 PM PDT 24
Peak memory 204068 kb
Host smart-018b1b56-112f-43f5-aca6-7163d5117a0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25599
45078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2559945078
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.758815105
Short name T328
Test name
Test status
Simulation time 8377247908 ps
CPU time 7.58 seconds
Started Apr 15 03:14:30 PM PDT 24
Finished Apr 15 03:14:38 PM PDT 24
Peak memory 204012 kb
Host smart-3b8a735b-9b3c-44f5-bfbb-b722f1bfd8b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75881
5105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.758815105
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.2364481888
Short name T544
Test name
Test status
Simulation time 8371973245 ps
CPU time 7.88 seconds
Started Apr 15 03:14:32 PM PDT 24
Finished Apr 15 03:14:40 PM PDT 24
Peak memory 204060 kb
Host smart-2eb0590f-9f2d-4cc3-b006-86e255867adc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23644
81888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.2364481888
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3694445147
Short name T481
Test name
Test status
Simulation time 8434126730 ps
CPU time 8.5 seconds
Started Apr 15 03:14:28 PM PDT 24
Finished Apr 15 03:14:37 PM PDT 24
Peak memory 204060 kb
Host smart-4698fd12-bdc2-4fe7-a796-d1103feb5191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36944
45147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3694445147
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.1108254811
Short name T17
Test name
Test status
Simulation time 8400669139 ps
CPU time 8.12 seconds
Started Apr 15 03:14:32 PM PDT 24
Finished Apr 15 03:14:40 PM PDT 24
Peak memory 204024 kb
Host smart-25957759-e1f8-4e29-b9fb-1d303c1245df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11082
54811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.1108254811
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.685571522
Short name T1128
Test name
Test status
Simulation time 8473625408 ps
CPU time 9.23 seconds
Started Apr 15 03:14:42 PM PDT 24
Finished Apr 15 03:14:51 PM PDT 24
Peak memory 204072 kb
Host smart-8c6ddcaf-3173-44f4-92ce-cae83604a31b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=685571522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.685571522
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.2999734892
Short name T430
Test name
Test status
Simulation time 8381787639 ps
CPU time 10.06 seconds
Started Apr 15 03:14:41 PM PDT 24
Finished Apr 15 03:14:51 PM PDT 24
Peak memory 203980 kb
Host smart-27c0b51e-17b2-4de0-aae0-d8ea6a4bbc42
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2999734892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.2999734892
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.1230929647
Short name T1358
Test name
Test status
Simulation time 8427435173 ps
CPU time 8.53 seconds
Started Apr 15 03:14:40 PM PDT 24
Finished Apr 15 03:14:49 PM PDT 24
Peak memory 204028 kb
Host smart-b64ff1b1-11f0-4ea5-a46b-1616bc7db499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12309
29647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.1230929647
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.3272195339
Short name T534
Test name
Test status
Simulation time 8384008645 ps
CPU time 8.04 seconds
Started Apr 15 03:14:33 PM PDT 24
Finished Apr 15 03:14:41 PM PDT 24
Peak memory 204028 kb
Host smart-72d90084-2d8b-4a9e-8e09-e475cfc19f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32721
95339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.3272195339
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_enable.528280398
Short name T855
Test name
Test status
Simulation time 8391414295 ps
CPU time 8.51 seconds
Started Apr 15 03:14:35 PM PDT 24
Finished Apr 15 03:14:44 PM PDT 24
Peak memory 203984 kb
Host smart-042ccfd9-227b-44a5-8c25-ef8bc370f6fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52828
0398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.528280398
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2842228999
Short name T1000
Test name
Test status
Simulation time 37764838 ps
CPU time 1.15 seconds
Started Apr 15 03:14:34 PM PDT 24
Finished Apr 15 03:14:36 PM PDT 24
Peak memory 204140 kb
Host smart-70f6e585-5374-4dc8-9816-bcd9843e2adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28422
28999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2842228999
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.2668698559
Short name T1132
Test name
Test status
Simulation time 8481449010 ps
CPU time 7.73 seconds
Started Apr 15 03:14:42 PM PDT 24
Finished Apr 15 03:14:51 PM PDT 24
Peak memory 203928 kb
Host smart-8df37f61-9dbd-472e-86dd-07798a4ccb61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26686
98559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.2668698559
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.914281159
Short name T1088
Test name
Test status
Simulation time 8376721345 ps
CPU time 8.32 seconds
Started Apr 15 03:14:41 PM PDT 24
Finished Apr 15 03:14:49 PM PDT 24
Peak memory 204052 kb
Host smart-b8406af9-0633-4158-af55-43be637844b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91428
1159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.914281159
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.2138235788
Short name T318
Test name
Test status
Simulation time 8389108910 ps
CPU time 7.46 seconds
Started Apr 15 03:14:38 PM PDT 24
Finished Apr 15 03:14:46 PM PDT 24
Peak memory 204044 kb
Host smart-7dd7aa00-53ab-4d5f-bd83-7f8d21476fe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21382
35788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.2138235788
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.2447128680
Short name T629
Test name
Test status
Simulation time 8415046390 ps
CPU time 8.52 seconds
Started Apr 15 03:14:38 PM PDT 24
Finished Apr 15 03:14:48 PM PDT 24
Peak memory 204044 kb
Host smart-d10b8da7-f1e4-43ab-8dfb-b3abb7faac29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24471
28680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.2447128680
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.611706966
Short name T417
Test name
Test status
Simulation time 8373169110 ps
CPU time 9.85 seconds
Started Apr 15 03:14:33 PM PDT 24
Finished Apr 15 03:14:43 PM PDT 24
Peak memory 204076 kb
Host smart-5f28612d-fbf2-420e-b7d6-95520a086ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61170
6966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.611706966
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.3235641327
Short name T1283
Test name
Test status
Simulation time 8402223605 ps
CPU time 9.03 seconds
Started Apr 15 03:14:37 PM PDT 24
Finished Apr 15 03:14:47 PM PDT 24
Peak memory 203928 kb
Host smart-fe326153-9dea-4c73-9e5d-46a354726956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32356
41327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.3235641327
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.4248174337
Short name T427
Test name
Test status
Simulation time 8439055025 ps
CPU time 7.7 seconds
Started Apr 15 03:14:35 PM PDT 24
Finished Apr 15 03:14:43 PM PDT 24
Peak memory 204024 kb
Host smart-85ac8cfd-c557-4cf8-8019-ba387188415d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42481
74337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.4248174337
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.4050037089
Short name T845
Test name
Test status
Simulation time 8370661758 ps
CPU time 7.54 seconds
Started Apr 15 03:14:48 PM PDT 24
Finished Apr 15 03:14:56 PM PDT 24
Peak memory 204056 kb
Host smart-4e3cb7c4-a716-4aae-b985-279ad9bbe3a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40500
37089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.4050037089
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.931681042
Short name T360
Test name
Test status
Simulation time 46274268 ps
CPU time 0.67 seconds
Started Apr 15 03:14:40 PM PDT 24
Finished Apr 15 03:14:41 PM PDT 24
Peak memory 203936 kb
Host smart-406509ae-397b-4482-b900-b468fc31f972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93168
1042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.931681042
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.3979430950
Short name T220
Test name
Test status
Simulation time 22698220853 ps
CPU time 42.75 seconds
Started Apr 15 03:14:37 PM PDT 24
Finished Apr 15 03:15:20 PM PDT 24
Peak memory 204252 kb
Host smart-01d7401f-1f64-4e44-b409-63473251cb4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39794
30950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.3979430950
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.4043989263
Short name T538
Test name
Test status
Simulation time 8493190607 ps
CPU time 9.65 seconds
Started Apr 15 03:14:36 PM PDT 24
Finished Apr 15 03:14:46 PM PDT 24
Peak memory 204080 kb
Host smart-1e0cea33-fce0-4eb0-aa48-0aecbc2a552a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40439
89263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.4043989263
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.4156811996
Short name T1340
Test name
Test status
Simulation time 8471065323 ps
CPU time 7.5 seconds
Started Apr 15 03:14:38 PM PDT 24
Finished Apr 15 03:14:46 PM PDT 24
Peak memory 203976 kb
Host smart-6fc6ad0a-2b52-4548-a9db-dee6165a4685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41568
11996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.4156811996
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.267875502
Short name T1076
Test name
Test status
Simulation time 8435636476 ps
CPU time 9.11 seconds
Started Apr 15 03:14:37 PM PDT 24
Finished Apr 15 03:14:47 PM PDT 24
Peak memory 204036 kb
Host smart-737b3824-b19c-4cb6-9f25-88fb077f2f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26787
5502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.267875502
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1734055568
Short name T1119
Test name
Test status
Simulation time 8375817825 ps
CPU time 8.33 seconds
Started Apr 15 03:14:39 PM PDT 24
Finished Apr 15 03:14:48 PM PDT 24
Peak memory 204024 kb
Host smart-bfd1cd4d-fc1a-482e-ac16-332bd3fd6dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17340
55568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1734055568
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.1740406633
Short name T1206
Test name
Test status
Simulation time 8423437598 ps
CPU time 7.58 seconds
Started Apr 15 03:14:35 PM PDT 24
Finished Apr 15 03:14:43 PM PDT 24
Peak memory 204060 kb
Host smart-9aa065e4-4da8-435b-a687-1a5fd26e5f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17404
06633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.1740406633
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.1763417945
Short name T446
Test name
Test status
Simulation time 8396856954 ps
CPU time 8.31 seconds
Started Apr 15 03:14:43 PM PDT 24
Finished Apr 15 03:14:52 PM PDT 24
Peak memory 203924 kb
Host smart-9ce6af76-93e8-4e83-9db8-189e1d1c27d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17634
17945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.1763417945
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.4263627195
Short name T594
Test name
Test status
Simulation time 8410278601 ps
CPU time 10.42 seconds
Started Apr 15 03:14:38 PM PDT 24
Finished Apr 15 03:14:49 PM PDT 24
Peak memory 204028 kb
Host smart-082de6bd-3117-4404-9444-63c66d8c9bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42636
27195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.4263627195
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.3000123001
Short name T1122
Test name
Test status
Simulation time 8476754539 ps
CPU time 8.28 seconds
Started Apr 15 03:14:50 PM PDT 24
Finished Apr 15 03:14:59 PM PDT 24
Peak memory 204052 kb
Host smart-7d3ff652-6cb2-4ce0-a0a6-82b9eae87380
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3000123001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.3000123001
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.3729817062
Short name T456
Test name
Test status
Simulation time 8386551270 ps
CPU time 8.02 seconds
Started Apr 15 03:14:49 PM PDT 24
Finished Apr 15 03:14:58 PM PDT 24
Peak memory 204052 kb
Host smart-bfeb8b52-9687-4928-be9b-bce869f7e806
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3729817062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.3729817062
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.605400148
Short name T438
Test name
Test status
Simulation time 8431239855 ps
CPU time 8.22 seconds
Started Apr 15 03:14:49 PM PDT 24
Finished Apr 15 03:14:58 PM PDT 24
Peak memory 204068 kb
Host smart-69d9f532-eb3a-4fe1-ba0d-af7b4dce36da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60540
0148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.605400148
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.2849005235
Short name T668
Test name
Test status
Simulation time 8376357710 ps
CPU time 8.73 seconds
Started Apr 15 03:14:56 PM PDT 24
Finished Apr 15 03:15:05 PM PDT 24
Peak memory 204024 kb
Host smart-d8fc77b6-9e4f-4471-8f3d-78a374be1031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28490
05235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.2849005235
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_enable.2713311682
Short name T1164
Test name
Test status
Simulation time 8374298562 ps
CPU time 8.42 seconds
Started Apr 15 03:14:45 PM PDT 24
Finished Apr 15 03:14:54 PM PDT 24
Peak memory 204028 kb
Host smart-fbe089b2-bedb-4add-8eda-54f195e56a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27133
11682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.2713311682
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.704217023
Short name T468
Test name
Test status
Simulation time 73884218 ps
CPU time 1.87 seconds
Started Apr 15 03:14:46 PM PDT 24
Finished Apr 15 03:14:48 PM PDT 24
Peak memory 204200 kb
Host smart-136d7211-d4cc-42b2-abcc-846843671034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70421
7023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.704217023
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.2479566620
Short name T1060
Test name
Test status
Simulation time 8395959073 ps
CPU time 7.71 seconds
Started Apr 15 03:15:04 PM PDT 24
Finished Apr 15 03:15:12 PM PDT 24
Peak memory 204044 kb
Host smart-a679a4ca-aeae-4765-9440-948a0d348828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24795
66620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.2479566620
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.1297755634
Short name T1117
Test name
Test status
Simulation time 8366955570 ps
CPU time 8.82 seconds
Started Apr 15 03:14:48 PM PDT 24
Finished Apr 15 03:14:57 PM PDT 24
Peak memory 203872 kb
Host smart-d208456f-0c86-43b8-83a7-e20ce1770144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12977
55634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.1297755634
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.986497746
Short name T942
Test name
Test status
Simulation time 8395278457 ps
CPU time 7.93 seconds
Started Apr 15 03:14:46 PM PDT 24
Finished Apr 15 03:14:55 PM PDT 24
Peak memory 204020 kb
Host smart-7c205eea-509a-4850-859d-517b4a889a96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98649
7746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.986497746
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.3610837221
Short name T1040
Test name
Test status
Simulation time 8429333755 ps
CPU time 9.78 seconds
Started Apr 15 03:14:45 PM PDT 24
Finished Apr 15 03:14:55 PM PDT 24
Peak memory 204064 kb
Host smart-96b391a9-79d2-4e96-9f6b-c7118e5d8cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36108
37221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.3610837221
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.1260093110
Short name T620
Test name
Test status
Simulation time 8472332143 ps
CPU time 9.88 seconds
Started Apr 15 03:14:45 PM PDT 24
Finished Apr 15 03:14:55 PM PDT 24
Peak memory 204048 kb
Host smart-3d25c037-3302-4ebf-9d2a-6ef4817a7cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12600
93110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.1260093110
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.2001009138
Short name T472
Test name
Test status
Simulation time 8383857692 ps
CPU time 9.49 seconds
Started Apr 15 03:14:46 PM PDT 24
Finished Apr 15 03:14:56 PM PDT 24
Peak memory 204024 kb
Host smart-e71fd60d-0800-48e4-a7b3-37fe01d8dc57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20010
09138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2001009138
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.3134377080
Short name T656
Test name
Test status
Simulation time 8402331199 ps
CPU time 8.18 seconds
Started Apr 15 03:14:48 PM PDT 24
Finished Apr 15 03:14:57 PM PDT 24
Peak memory 203992 kb
Host smart-53679329-78d4-491e-9bcc-89119a77fb62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31343
77080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.3134377080
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.2554208675
Short name T1026
Test name
Test status
Simulation time 8445311945 ps
CPU time 8.67 seconds
Started Apr 15 03:14:46 PM PDT 24
Finished Apr 15 03:14:56 PM PDT 24
Peak memory 204048 kb
Host smart-497613f2-d5b0-4568-ad87-e04740d389b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25542
08675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.2554208675
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.3594402355
Short name T852
Test name
Test status
Simulation time 8373224823 ps
CPU time 8.22 seconds
Started Apr 15 03:15:04 PM PDT 24
Finished Apr 15 03:15:13 PM PDT 24
Peak memory 203912 kb
Host smart-353691f5-533a-42f1-989e-e7ce1c47296b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35944
02355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.3594402355
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.2196193780
Short name T1006
Test name
Test status
Simulation time 135931842 ps
CPU time 0.75 seconds
Started Apr 15 03:14:48 PM PDT 24
Finished Apr 15 03:14:49 PM PDT 24
Peak memory 203928 kb
Host smart-7fd2d2ae-167e-4a31-8ca3-05ec852d6b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21961
93780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.2196193780
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.681019975
Short name T435
Test name
Test status
Simulation time 29892913566 ps
CPU time 55.37 seconds
Started Apr 15 03:14:49 PM PDT 24
Finished Apr 15 03:15:45 PM PDT 24
Peak memory 204308 kb
Host smart-8acec2f3-7b74-4923-be5d-8c1d20c22514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68101
9975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.681019975
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.205653849
Short name T348
Test name
Test status
Simulation time 8414261264 ps
CPU time 8.34 seconds
Started Apr 15 03:14:51 PM PDT 24
Finished Apr 15 03:15:00 PM PDT 24
Peak memory 204068 kb
Host smart-f4e890e6-d1a5-402b-9c04-247af5f4547d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20565
3849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.205653849
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1564186881
Short name T990
Test name
Test status
Simulation time 8463452093 ps
CPU time 8.44 seconds
Started Apr 15 03:14:50 PM PDT 24
Finished Apr 15 03:14:59 PM PDT 24
Peak memory 204048 kb
Host smart-6e3be3b6-cecd-41cd-83b0-0b4ae8a5865f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15641
86881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1564186881
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.1414557338
Short name T790
Test name
Test status
Simulation time 8376319109 ps
CPU time 8.18 seconds
Started Apr 15 03:14:51 PM PDT 24
Finished Apr 15 03:15:00 PM PDT 24
Peak memory 204056 kb
Host smart-bb79823c-513c-4dbd-8ff2-143d836fec94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14145
57338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.1414557338
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.858669352
Short name T1062
Test name
Test status
Simulation time 8395339620 ps
CPU time 8.23 seconds
Started Apr 15 03:14:51 PM PDT 24
Finished Apr 15 03:15:00 PM PDT 24
Peak memory 204052 kb
Host smart-e9c3841e-8a20-4fea-b853-ab1b33ce372f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85866
9352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.858669352
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3482517513
Short name T387
Test name
Test status
Simulation time 8367515806 ps
CPU time 8.73 seconds
Started Apr 15 03:15:04 PM PDT 24
Finished Apr 15 03:15:13 PM PDT 24
Peak memory 204044 kb
Host smart-5d95c5a5-a036-42d6-9d40-06c7dbb07ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34825
17513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3482517513
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.2707615909
Short name T560
Test name
Test status
Simulation time 8422859718 ps
CPU time 8.02 seconds
Started Apr 15 03:14:45 PM PDT 24
Finished Apr 15 03:14:53 PM PDT 24
Peak memory 204060 kb
Host smart-49ef5f79-d836-4001-90be-f7fa03d51115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27076
15909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.2707615909
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.1614420403
Short name T1275
Test name
Test status
Simulation time 8413025603 ps
CPU time 8.38 seconds
Started Apr 15 03:15:04 PM PDT 24
Finished Apr 15 03:15:13 PM PDT 24
Peak memory 203944 kb
Host smart-3323133c-3a43-4766-ae53-7d8fe86f378b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16144
20403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.1614420403
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3393905853
Short name T492
Test name
Test status
Simulation time 8413261475 ps
CPU time 7.84 seconds
Started Apr 15 03:14:46 PM PDT 24
Finished Apr 15 03:14:55 PM PDT 24
Peak memory 204064 kb
Host smart-67123d3d-5ee1-44e5-8c23-38683a496b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33939
05853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3393905853
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.3048744337
Short name T323
Test name
Test status
Simulation time 8464512868 ps
CPU time 9.11 seconds
Started Apr 15 03:11:15 PM PDT 24
Finished Apr 15 03:11:25 PM PDT 24
Peak memory 204052 kb
Host smart-6d167abe-4d49-42bd-a73e-2aea61ffe2c6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3048744337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.3048744337
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.4269562652
Short name T222
Test name
Test status
Simulation time 8383368179 ps
CPU time 9.53 seconds
Started Apr 15 03:11:17 PM PDT 24
Finished Apr 15 03:11:27 PM PDT 24
Peak memory 203980 kb
Host smart-58e6e955-71f8-4156-acc9-449f1350a501
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4269562652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.4269562652
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.3467005509
Short name T429
Test name
Test status
Simulation time 8390113492 ps
CPU time 8.01 seconds
Started Apr 15 03:11:12 PM PDT 24
Finished Apr 15 03:11:21 PM PDT 24
Peak memory 204056 kb
Host smart-618ab4c3-acd8-48cb-a1c3-d659d3b791e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34670
05509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.3467005509
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.3178432214
Short name T1316
Test name
Test status
Simulation time 8380939858 ps
CPU time 7.8 seconds
Started Apr 15 03:10:58 PM PDT 24
Finished Apr 15 03:11:06 PM PDT 24
Peak memory 204048 kb
Host smart-a0845e38-4a81-46da-95ee-df4ee16fe706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31784
32214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.3178432214
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_enable.2733469995
Short name T1246
Test name
Test status
Simulation time 8384885593 ps
CPU time 8.69 seconds
Started Apr 15 03:10:58 PM PDT 24
Finished Apr 15 03:11:07 PM PDT 24
Peak memory 204076 kb
Host smart-87647405-5200-4bed-842d-cfdaa12e5bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27334
69995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.2733469995
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.310662148
Short name T1261
Test name
Test status
Simulation time 92978360 ps
CPU time 1.15 seconds
Started Apr 15 03:11:00 PM PDT 24
Finished Apr 15 03:11:01 PM PDT 24
Peak memory 204152 kb
Host smart-1b36da9f-b55e-44fb-aa65-41e43df453f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31066
2148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.310662148
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.211741352
Short name T864
Test name
Test status
Simulation time 8423461580 ps
CPU time 7.87 seconds
Started Apr 15 03:11:13 PM PDT 24
Finished Apr 15 03:11:22 PM PDT 24
Peak memory 204028 kb
Host smart-afeee775-f405-4919-adc9-dab6b1bd4cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21174
1352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.211741352
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.625989319
Short name T994
Test name
Test status
Simulation time 8378800641 ps
CPU time 8.63 seconds
Started Apr 15 03:11:13 PM PDT 24
Finished Apr 15 03:11:22 PM PDT 24
Peak memory 204004 kb
Host smart-78c59b7a-29d3-4f8f-af51-81cfc94b7380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62598
9319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.625989319
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.3956605644
Short name T784
Test name
Test status
Simulation time 8496380448 ps
CPU time 9.58 seconds
Started Apr 15 03:11:02 PM PDT 24
Finished Apr 15 03:11:12 PM PDT 24
Peak memory 203988 kb
Host smart-80e88638-3cf9-46a6-9e67-1e0e14488e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39566
05644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.3956605644
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.778206211
Short name T539
Test name
Test status
Simulation time 8415429217 ps
CPU time 8.4 seconds
Started Apr 15 03:11:03 PM PDT 24
Finished Apr 15 03:11:12 PM PDT 24
Peak memory 203976 kb
Host smart-7dc15c1b-f772-4405-a24f-afba8bacc5f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77820
6211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.778206211
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.876485569
Short name T1055
Test name
Test status
Simulation time 8377396103 ps
CPU time 8.9 seconds
Started Apr 15 03:11:01 PM PDT 24
Finished Apr 15 03:11:11 PM PDT 24
Peak memory 204064 kb
Host smart-60b975a3-8af4-4f57-9325-a0701d7f8261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87648
5569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.876485569
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.1629788376
Short name T92
Test name
Test status
Simulation time 8407814457 ps
CPU time 8.77 seconds
Started Apr 15 03:11:02 PM PDT 24
Finished Apr 15 03:11:11 PM PDT 24
Peak memory 204032 kb
Host smart-baf6661d-0613-42ec-a5c7-e1a21724dd41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16297
88376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.1629788376
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.1530647127
Short name T1323
Test name
Test status
Simulation time 8424634646 ps
CPU time 10.3 seconds
Started Apr 15 03:11:04 PM PDT 24
Finished Apr 15 03:11:15 PM PDT 24
Peak memory 204036 kb
Host smart-fed5367e-1b9f-4b9d-b29d-8cc80be8fac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15306
47127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.1530647127
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.3579604718
Short name T607
Test name
Test status
Simulation time 8383431380 ps
CPU time 9.53 seconds
Started Apr 15 03:11:08 PM PDT 24
Finished Apr 15 03:11:18 PM PDT 24
Peak memory 204056 kb
Host smart-6120ccbe-a1a1-415c-a435-e6ac095b5def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35796
04718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.3579604718
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.3959043160
Short name T147
Test name
Test status
Simulation time 8426503458 ps
CPU time 9.79 seconds
Started Apr 15 03:11:14 PM PDT 24
Finished Apr 15 03:11:24 PM PDT 24
Peak memory 204020 kb
Host smart-9f6cd296-415a-4252-acab-6bf4c6a7f6fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39590
43160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.3959043160
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.3601023098
Short name T346
Test name
Test status
Simulation time 8413047009 ps
CPU time 8.29 seconds
Started Apr 15 03:11:13 PM PDT 24
Finished Apr 15 03:11:22 PM PDT 24
Peak memory 204016 kb
Host smart-e445264d-c5da-45d6-b1ec-34c5464bc8af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36010
23098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.3601023098
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2254233457
Short name T34
Test name
Test status
Simulation time 35992813 ps
CPU time 0.63 seconds
Started Apr 15 03:11:15 PM PDT 24
Finished Apr 15 03:11:16 PM PDT 24
Peak memory 203864 kb
Host smart-06e1ec53-eb97-4998-9ebd-41a0b9890b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22542
33457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2254233457
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.4273118953
Short name T1296
Test name
Test status
Simulation time 31425708223 ps
CPU time 67.12 seconds
Started Apr 15 03:11:09 PM PDT 24
Finished Apr 15 03:12:16 PM PDT 24
Peak memory 204332 kb
Host smart-a2ccbe4c-1d14-424f-8a84-851c8de6f8d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42731
18953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.4273118953
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.2352843896
Short name T916
Test name
Test status
Simulation time 8416674327 ps
CPU time 8.26 seconds
Started Apr 15 03:11:08 PM PDT 24
Finished Apr 15 03:11:17 PM PDT 24
Peak memory 204056 kb
Host smart-7cb9a96b-639e-4f50-bb49-25a61889ba0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23528
43896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.2352843896
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.2503673818
Short name T1348
Test name
Test status
Simulation time 8483414564 ps
CPU time 8.71 seconds
Started Apr 15 03:11:04 PM PDT 24
Finished Apr 15 03:11:13 PM PDT 24
Peak memory 203984 kb
Host smart-9816e227-7226-4fd4-ac4d-c1268cd7a5bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25036
73818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2503673818
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.2723558271
Short name T510
Test name
Test status
Simulation time 8379444704 ps
CPU time 8.24 seconds
Started Apr 15 03:11:05 PM PDT 24
Finished Apr 15 03:11:14 PM PDT 24
Peak memory 204060 kb
Host smart-305c4267-7b77-4db2-8471-f91785d9358b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27235
58271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.2723558271
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.2368641008
Short name T60
Test name
Test status
Simulation time 207561604 ps
CPU time 1.02 seconds
Started Apr 15 03:11:20 PM PDT 24
Finished Apr 15 03:11:21 PM PDT 24
Peak memory 220300 kb
Host smart-05995d7c-84bb-47a4-a90c-6605ef7c0d9c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2368641008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2368641008
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.710167190
Short name T842
Test name
Test status
Simulation time 8378070311 ps
CPU time 8.73 seconds
Started Apr 15 03:11:13 PM PDT 24
Finished Apr 15 03:11:22 PM PDT 24
Peak memory 204028 kb
Host smart-3fb2bd1b-788d-4697-b75c-32e5d5ee32aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71016
7190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.710167190
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3873130559
Short name T820
Test name
Test status
Simulation time 8413457549 ps
CPU time 8.12 seconds
Started Apr 15 03:11:08 PM PDT 24
Finished Apr 15 03:11:16 PM PDT 24
Peak memory 204048 kb
Host smart-be2ae160-e6cf-4942-a3f7-223d58cfc782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38731
30559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3873130559
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.2925917176
Short name T628
Test name
Test status
Simulation time 8371205006 ps
CPU time 8.46 seconds
Started Apr 15 03:11:08 PM PDT 24
Finished Apr 15 03:11:18 PM PDT 24
Peak memory 204052 kb
Host smart-3876c98d-a71d-46da-82c7-9f5a409dc404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29259
17176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.2925917176
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.3198555664
Short name T1049
Test name
Test status
Simulation time 8383637223 ps
CPU time 10.4 seconds
Started Apr 15 03:11:10 PM PDT 24
Finished Apr 15 03:11:21 PM PDT 24
Peak memory 204056 kb
Host smart-9a5f944a-3029-4650-81e4-df8c9d885121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31985
55664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.3198555664
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.1149668879
Short name T1093
Test name
Test status
Simulation time 8462321612 ps
CPU time 8.2 seconds
Started Apr 15 03:14:59 PM PDT 24
Finished Apr 15 03:15:08 PM PDT 24
Peak memory 204068 kb
Host smart-7d6a112e-92e7-4629-beb5-9c3a7f26b22d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1149668879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.1149668879
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.388769787
Short name T588
Test name
Test status
Simulation time 8375427538 ps
CPU time 9.07 seconds
Started Apr 15 03:15:01 PM PDT 24
Finished Apr 15 03:15:11 PM PDT 24
Peak memory 204016 kb
Host smart-17b678b1-c1ab-4218-ac6a-4f994a43bcb7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=388769787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.388769787
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.331862803
Short name T1146
Test name
Test status
Simulation time 8447948891 ps
CPU time 8.34 seconds
Started Apr 15 03:15:07 PM PDT 24
Finished Apr 15 03:15:16 PM PDT 24
Peak memory 204048 kb
Host smart-6f69e2e5-d8f8-4872-990a-1993eb1cd4ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33186
2803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.331862803
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.103875191
Short name T371
Test name
Test status
Simulation time 8377837628 ps
CPU time 7.88 seconds
Started Apr 15 03:14:51 PM PDT 24
Finished Apr 15 03:15:00 PM PDT 24
Peak memory 203996 kb
Host smart-40bfb599-2db6-4dfd-8c60-ba4c56630c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10387
5191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.103875191
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_enable.2051884760
Short name T270
Test name
Test status
Simulation time 8371958068 ps
CPU time 8.22 seconds
Started Apr 15 03:14:52 PM PDT 24
Finished Apr 15 03:15:01 PM PDT 24
Peak memory 204020 kb
Host smart-eeb833b0-1be1-4116-a78e-d4aa1339eba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20518
84760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.2051884760
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.3883434775
Short name T54
Test name
Test status
Simulation time 53981456 ps
CPU time 1.29 seconds
Started Apr 15 03:14:53 PM PDT 24
Finished Apr 15 03:14:55 PM PDT 24
Peak memory 204088 kb
Host smart-79dc1cd4-29a5-4477-8492-cbf9c9dc76e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38834
34775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.3883434775
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.2477330643
Short name T853
Test name
Test status
Simulation time 8462015703 ps
CPU time 7.91 seconds
Started Apr 15 03:15:00 PM PDT 24
Finished Apr 15 03:15:08 PM PDT 24
Peak memory 204060 kb
Host smart-491c1194-5de9-4e75-bb27-566dcdbdc445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24773
30643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.2477330643
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.2995194487
Short name T1265
Test name
Test status
Simulation time 8428601760 ps
CPU time 8.33 seconds
Started Apr 15 03:15:04 PM PDT 24
Finished Apr 15 03:15:13 PM PDT 24
Peak memory 204044 kb
Host smart-90cea226-529d-4a59-9056-12e62169004e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29951
94487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.2995194487
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.3844920208
Short name T1225
Test name
Test status
Simulation time 8432726810 ps
CPU time 7.98 seconds
Started Apr 15 03:15:04 PM PDT 24
Finished Apr 15 03:15:13 PM PDT 24
Peak memory 204044 kb
Host smart-c2914246-f1ce-4f40-ace4-f5bf8904de6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38449
20208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.3844920208
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.510152204
Short name T915
Test name
Test status
Simulation time 8374531045 ps
CPU time 7.94 seconds
Started Apr 15 03:14:52 PM PDT 24
Finished Apr 15 03:15:01 PM PDT 24
Peak memory 204020 kb
Host smart-00feaf6f-8c6c-46b5-8d78-046887b04504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51015
2204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.510152204
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.3399435026
Short name T1229
Test name
Test status
Simulation time 8396395335 ps
CPU time 8.19 seconds
Started Apr 15 03:15:04 PM PDT 24
Finished Apr 15 03:15:13 PM PDT 24
Peak memory 204044 kb
Host smart-338f276c-e404-493b-bfcd-0046b393fddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33994
35026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.3399435026
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.3815567121
Short name T1195
Test name
Test status
Simulation time 8402091997 ps
CPU time 8.47 seconds
Started Apr 15 03:14:51 PM PDT 24
Finished Apr 15 03:15:00 PM PDT 24
Peak memory 204008 kb
Host smart-d6a498a0-ebb7-4d26-91fb-eeed4a0e7915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38155
67121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3815567121
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.377044465
Short name T731
Test name
Test status
Simulation time 8465509968 ps
CPU time 8.21 seconds
Started Apr 15 03:14:59 PM PDT 24
Finished Apr 15 03:15:08 PM PDT 24
Peak memory 204048 kb
Host smart-7be4dbc8-ed7d-4092-80e1-40223060be81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37704
4465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.377044465
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.51382281
Short name T586
Test name
Test status
Simulation time 8393332717 ps
CPU time 8.33 seconds
Started Apr 15 03:14:57 PM PDT 24
Finished Apr 15 03:15:05 PM PDT 24
Peak memory 204060 kb
Host smart-8967a8d5-e7c4-4bbe-89ec-f08841d4e8c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51382
281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.51382281
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.2406493772
Short name T43
Test name
Test status
Simulation time 43952612 ps
CPU time 0.67 seconds
Started Apr 15 03:15:06 PM PDT 24
Finished Apr 15 03:15:07 PM PDT 24
Peak memory 203920 kb
Host smart-2fd62b1d-d447-46a8-b646-ae7707475142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24064
93772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.2406493772
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.1014381548
Short name T232
Test name
Test status
Simulation time 28624793808 ps
CPU time 65.78 seconds
Started Apr 15 03:14:56 PM PDT 24
Finished Apr 15 03:16:02 PM PDT 24
Peak memory 204336 kb
Host smart-6cdb06dc-2901-4f32-9ad4-258356b63e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10143
81548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.1014381548
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.3042630488
Short name T665
Test name
Test status
Simulation time 8381317791 ps
CPU time 8.59 seconds
Started Apr 15 03:14:57 PM PDT 24
Finished Apr 15 03:15:06 PM PDT 24
Peak memory 204052 kb
Host smart-fbd88012-2415-4fab-b2d7-6126c1b95122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30426
30488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.3042630488
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.1169302364
Short name T500
Test name
Test status
Simulation time 8411204857 ps
CPU time 7.8 seconds
Started Apr 15 03:14:56 PM PDT 24
Finished Apr 15 03:15:04 PM PDT 24
Peak memory 203980 kb
Host smart-c14fe52c-a582-4e4a-812d-d227518429e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11693
02364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.1169302364
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.2495216250
Short name T1151
Test name
Test status
Simulation time 8414144704 ps
CPU time 7.89 seconds
Started Apr 15 03:14:56 PM PDT 24
Finished Apr 15 03:15:04 PM PDT 24
Peak memory 204032 kb
Host smart-4f114ead-7148-435b-aa18-28ff803ec456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24952
16250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.2495216250
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.2086815140
Short name T1292
Test name
Test status
Simulation time 8378141540 ps
CPU time 7.71 seconds
Started Apr 15 03:14:55 PM PDT 24
Finished Apr 15 03:15:03 PM PDT 24
Peak memory 204028 kb
Host smart-e57efc16-d707-4359-9f48-5f1d700e1860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20868
15140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2086815140
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.3974813642
Short name T886
Test name
Test status
Simulation time 8406579741 ps
CPU time 9.71 seconds
Started Apr 15 03:14:56 PM PDT 24
Finished Apr 15 03:15:06 PM PDT 24
Peak memory 204060 kb
Host smart-eafe64e7-ca2b-462c-88a7-bf226455644f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39748
13642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.3974813642
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1026246867
Short name T711
Test name
Test status
Simulation time 8478050636 ps
CPU time 8.31 seconds
Started Apr 15 03:14:54 PM PDT 24
Finished Apr 15 03:15:03 PM PDT 24
Peak memory 204068 kb
Host smart-67ac2658-eba9-4263-a339-372913f10610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10262
46867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1026246867
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.4027609699
Short name T983
Test name
Test status
Simulation time 8467318361 ps
CPU time 8.76 seconds
Started Apr 15 03:14:58 PM PDT 24
Finished Apr 15 03:15:07 PM PDT 24
Peak memory 204196 kb
Host smart-70f70aba-68c5-46b1-b6ab-306e6fd2d0d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40276
09699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.4027609699
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.1060707310
Short name T936
Test name
Test status
Simulation time 8375150630 ps
CPU time 7.76 seconds
Started Apr 15 03:14:57 PM PDT 24
Finished Apr 15 03:15:05 PM PDT 24
Peak memory 204056 kb
Host smart-ebaf28b3-9326-435c-86b7-9f9e87df97d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10607
07310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1060707310
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.2479919002
Short name T765
Test name
Test status
Simulation time 8460415680 ps
CPU time 7.96 seconds
Started Apr 15 03:15:19 PM PDT 24
Finished Apr 15 03:15:27 PM PDT 24
Peak memory 204052 kb
Host smart-0f0291a9-528f-4b52-8fe9-5bf818eff308
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2479919002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.2479919002
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.3015744206
Short name T1176
Test name
Test status
Simulation time 8390626537 ps
CPU time 7.94 seconds
Started Apr 15 03:15:15 PM PDT 24
Finished Apr 15 03:15:24 PM PDT 24
Peak memory 204056 kb
Host smart-0b1bf01c-a539-43f2-aeb9-940bf80c4a05
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3015744206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.3015744206
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.228624385
Short name T382
Test name
Test status
Simulation time 8394292722 ps
CPU time 9.03 seconds
Started Apr 15 03:15:11 PM PDT 24
Finished Apr 15 03:15:20 PM PDT 24
Peak memory 204076 kb
Host smart-0117ef67-b717-4564-8ea8-7a82a3f595b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22862
4385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.228624385
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.531394291
Short name T1004
Test name
Test status
Simulation time 8393232587 ps
CPU time 7.64 seconds
Started Apr 15 03:14:59 PM PDT 24
Finished Apr 15 03:15:07 PM PDT 24
Peak memory 204024 kb
Host smart-b65bae89-2f82-4fbe-bd17-c880e8d4ad75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53139
4291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.531394291
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_enable.952295315
Short name T1162
Test name
Test status
Simulation time 8381985446 ps
CPU time 7.71 seconds
Started Apr 15 03:15:02 PM PDT 24
Finished Apr 15 03:15:11 PM PDT 24
Peak memory 204008 kb
Host smart-7cbe0547-fa2e-4b38-83b8-b06e1e9e1dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95229
5315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.952295315
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.2286540725
Short name T861
Test name
Test status
Simulation time 77552913 ps
CPU time 1.59 seconds
Started Apr 15 03:15:06 PM PDT 24
Finished Apr 15 03:15:08 PM PDT 24
Peak memory 204036 kb
Host smart-10db8d6f-8047-4cfb-af05-d3b307536714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22865
40725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.2286540725
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.112679316
Short name T1258
Test name
Test status
Simulation time 8439377566 ps
CPU time 7.9 seconds
Started Apr 15 03:15:17 PM PDT 24
Finished Apr 15 03:15:25 PM PDT 24
Peak memory 204044 kb
Host smart-1c991957-3d5e-408b-8342-854fb35d361d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11267
9316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.112679316
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.3746946953
Short name T683
Test name
Test status
Simulation time 8402485018 ps
CPU time 7.58 seconds
Started Apr 15 03:15:18 PM PDT 24
Finished Apr 15 03:15:27 PM PDT 24
Peak memory 204040 kb
Host smart-a4e6da0b-2f46-48d5-b975-4e68b44d1bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37469
46953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.3746946953
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.2966989934
Short name T635
Test name
Test status
Simulation time 8441473814 ps
CPU time 8.95 seconds
Started Apr 15 03:15:04 PM PDT 24
Finished Apr 15 03:15:14 PM PDT 24
Peak memory 204060 kb
Host smart-7aa36a79-8725-4c02-a706-a49b758b4a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29669
89934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.2966989934
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.1347405629
Short name T682
Test name
Test status
Simulation time 8426104038 ps
CPU time 10.25 seconds
Started Apr 15 03:15:02 PM PDT 24
Finished Apr 15 03:15:12 PM PDT 24
Peak memory 204008 kb
Host smart-57c00119-1bc2-44a3-9ebf-ff4de98c19ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13474
05629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.1347405629
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3231346124
Short name T1188
Test name
Test status
Simulation time 8370299172 ps
CPU time 7.69 seconds
Started Apr 15 03:15:03 PM PDT 24
Finished Apr 15 03:15:11 PM PDT 24
Peak memory 203996 kb
Host smart-66a8285b-7c6f-4fc3-b364-63d965c5f732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32313
46124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3231346124
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.4123671732
Short name T956
Test name
Test status
Simulation time 8382422472 ps
CPU time 7.82 seconds
Started Apr 15 03:15:04 PM PDT 24
Finished Apr 15 03:15:13 PM PDT 24
Peak memory 204024 kb
Host smart-4506447b-c1ff-4948-9142-859ac3462861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41236
71732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.4123671732
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.1045241219
Short name T988
Test name
Test status
Simulation time 8383145410 ps
CPU time 8.15 seconds
Started Apr 15 03:15:03 PM PDT 24
Finished Apr 15 03:15:12 PM PDT 24
Peak memory 204004 kb
Host smart-43f19bc9-4da1-4983-9517-cd99db91f4b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10452
41219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.1045241219
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.2387133135
Short name T881
Test name
Test status
Simulation time 8421386504 ps
CPU time 7.92 seconds
Started Apr 15 03:15:08 PM PDT 24
Finished Apr 15 03:15:16 PM PDT 24
Peak memory 204032 kb
Host smart-e32e0ed8-f032-4fbd-9728-1d62db843c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23871
33135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.2387133135
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.2373007863
Short name T913
Test name
Test status
Simulation time 8366232331 ps
CPU time 7.87 seconds
Started Apr 15 03:15:07 PM PDT 24
Finished Apr 15 03:15:15 PM PDT 24
Peak memory 204040 kb
Host smart-3d2b1a74-21ca-4644-93e0-6077863223fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23730
07863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.2373007863
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.2614369092
Short name T1201
Test name
Test status
Simulation time 41143915 ps
CPU time 0.67 seconds
Started Apr 15 03:15:09 PM PDT 24
Finished Apr 15 03:15:10 PM PDT 24
Peak memory 203932 kb
Host smart-c58529ec-a7f2-4f00-b14b-6eef4753bb1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26143
69092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.2614369092
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.7776766
Short name T1105
Test name
Test status
Simulation time 27278884016 ps
CPU time 50.75 seconds
Started Apr 15 03:15:02 PM PDT 24
Finished Apr 15 03:15:53 PM PDT 24
Peak memory 204340 kb
Host smart-6c104479-dd3d-4cdb-8b51-75116f6e4b4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77767
66 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.7776766
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.1590668824
Short name T778
Test name
Test status
Simulation time 8414756532 ps
CPU time 9.06 seconds
Started Apr 15 03:15:05 PM PDT 24
Finished Apr 15 03:15:14 PM PDT 24
Peak memory 204008 kb
Host smart-8c1c1f4c-39f8-4893-a3c4-d67db504b728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15906
68824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.1590668824
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.3596074987
Short name T142
Test name
Test status
Simulation time 8449065246 ps
CPU time 7.64 seconds
Started Apr 15 03:15:06 PM PDT 24
Finished Apr 15 03:15:14 PM PDT 24
Peak memory 203968 kb
Host smart-be3ac001-8627-410a-856c-c6c4f2c9d844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35960
74987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3596074987
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.2991676181
Short name T75
Test name
Test status
Simulation time 8426029488 ps
CPU time 8.67 seconds
Started Apr 15 03:15:04 PM PDT 24
Finished Apr 15 03:15:14 PM PDT 24
Peak memory 204072 kb
Host smart-8e7a2afd-afae-45db-87bc-3de69124f631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29916
76181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.2991676181
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.3140762725
Short name T940
Test name
Test status
Simulation time 8371409839 ps
CPU time 7.93 seconds
Started Apr 15 03:15:09 PM PDT 24
Finished Apr 15 03:15:17 PM PDT 24
Peak memory 204052 kb
Host smart-369704ce-ef49-4425-8e76-4040fae5c8e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31407
62725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.3140762725
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1671937488
Short name T576
Test name
Test status
Simulation time 8382830428 ps
CPU time 8.61 seconds
Started Apr 15 03:15:07 PM PDT 24
Finished Apr 15 03:15:16 PM PDT 24
Peak memory 203876 kb
Host smart-875ed84a-94f1-4a6a-b30b-c48b3b3c2ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16719
37488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1671937488
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.3190295466
Short name T1139
Test name
Test status
Simulation time 8441755017 ps
CPU time 8.05 seconds
Started Apr 15 03:14:59 PM PDT 24
Finished Apr 15 03:15:07 PM PDT 24
Peak memory 204060 kb
Host smart-f6b7171d-22d4-4f97-8b50-42de1f741936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31902
95466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.3190295466
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.2854749653
Short name T1226
Test name
Test status
Simulation time 8379553439 ps
CPU time 8.3 seconds
Started Apr 15 03:15:07 PM PDT 24
Finished Apr 15 03:15:16 PM PDT 24
Peak memory 204044 kb
Host smart-78713bff-593b-41ac-a10a-741de04b5954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28547
49653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.2854749653
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.2364586844
Short name T1082
Test name
Test status
Simulation time 8375757042 ps
CPU time 8.98 seconds
Started Apr 15 03:15:07 PM PDT 24
Finished Apr 15 03:15:16 PM PDT 24
Peak memory 204044 kb
Host smart-9680e793-5ce9-47a5-b74b-1a5388381848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23645
86844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.2364586844
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.1874708060
Short name T1097
Test name
Test status
Simulation time 8466076516 ps
CPU time 8.4 seconds
Started Apr 15 03:15:20 PM PDT 24
Finished Apr 15 03:15:29 PM PDT 24
Peak memory 204052 kb
Host smart-c067a2ba-344b-4207-90cf-1090e7b0a8f9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1874708060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.1874708060
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.997672996
Short name T595
Test name
Test status
Simulation time 8462639135 ps
CPU time 7.73 seconds
Started Apr 15 03:15:18 PM PDT 24
Finished Apr 15 03:15:27 PM PDT 24
Peak memory 204028 kb
Host smart-32a0b542-070a-4010-ab41-66f9cd562da3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=997672996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.997672996
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.306513315
Short name T1046
Test name
Test status
Simulation time 8458936245 ps
CPU time 9.3 seconds
Started Apr 15 03:15:20 PM PDT 24
Finished Apr 15 03:15:30 PM PDT 24
Peak memory 204052 kb
Host smart-545a0c08-d25d-45c3-9808-09eeb78920f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30651
3315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.306513315
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.340857600
Short name T488
Test name
Test status
Simulation time 8379762860 ps
CPU time 7.78 seconds
Started Apr 15 03:15:10 PM PDT 24
Finished Apr 15 03:15:18 PM PDT 24
Peak memory 204028 kb
Host smart-2ca65af9-9bac-4c67-a3d7-d2a81b0503a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34085
7600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.340857600
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_enable.2356715683
Short name T616
Test name
Test status
Simulation time 8384356721 ps
CPU time 7.66 seconds
Started Apr 15 03:15:13 PM PDT 24
Finished Apr 15 03:15:21 PM PDT 24
Peak memory 204048 kb
Host smart-3cd3b8a6-d734-49ab-a7e6-a436d3dc346e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23567
15683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.2356715683
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.2039790460
Short name T989
Test name
Test status
Simulation time 210824566 ps
CPU time 2.3 seconds
Started Apr 15 03:15:12 PM PDT 24
Finished Apr 15 03:15:15 PM PDT 24
Peak memory 204172 kb
Host smart-ebfcea57-28ae-4c4c-8dc4-26aaceff2db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20397
90460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.2039790460
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1903384234
Short name T125
Test name
Test status
Simulation time 8420781414 ps
CPU time 8.58 seconds
Started Apr 15 03:15:18 PM PDT 24
Finished Apr 15 03:15:27 PM PDT 24
Peak memory 204068 kb
Host smart-bbfe04e5-c547-484f-b26c-902ff95e2397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19033
84234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1903384234
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.4001030377
Short name T167
Test name
Test status
Simulation time 8369031073 ps
CPU time 8.39 seconds
Started Apr 15 03:15:14 PM PDT 24
Finished Apr 15 03:15:22 PM PDT 24
Peak memory 204072 kb
Host smart-2ef9312b-af88-4d46-8e85-ae325624a3ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40010
30377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.4001030377
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.1452401658
Short name T653
Test name
Test status
Simulation time 8412428176 ps
CPU time 7.62 seconds
Started Apr 15 03:15:13 PM PDT 24
Finished Apr 15 03:15:22 PM PDT 24
Peak memory 204000 kb
Host smart-1eec246d-e739-44ee-a1a4-5e9073362e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14524
01658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.1452401658
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.2206940169
Short name T646
Test name
Test status
Simulation time 8429219603 ps
CPU time 8.06 seconds
Started Apr 15 03:15:20 PM PDT 24
Finished Apr 15 03:15:29 PM PDT 24
Peak memory 204044 kb
Host smart-48ca3774-16c0-43b2-8c12-9d10d08a9e6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22069
40169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.2206940169
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.1239504872
Short name T971
Test name
Test status
Simulation time 8377648134 ps
CPU time 8.13 seconds
Started Apr 15 03:15:17 PM PDT 24
Finished Apr 15 03:15:26 PM PDT 24
Peak memory 204056 kb
Host smart-3f5efd54-5aca-4cde-9760-634f62ffea3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12395
04872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.1239504872
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.1116727185
Short name T874
Test name
Test status
Simulation time 8402477616 ps
CPU time 10.08 seconds
Started Apr 15 03:15:21 PM PDT 24
Finished Apr 15 03:15:32 PM PDT 24
Peak memory 203900 kb
Host smart-cf3574ed-3cec-4e8d-aead-67a1ef6abe30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11167
27185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.1116727185
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.589074846
Short name T356
Test name
Test status
Simulation time 8400515575 ps
CPU time 8.34 seconds
Started Apr 15 03:15:17 PM PDT 24
Finished Apr 15 03:15:25 PM PDT 24
Peak memory 204076 kb
Host smart-276c986a-6ae0-487d-9049-e9f9c69387dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58907
4846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.589074846
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.2796572271
Short name T903
Test name
Test status
Simulation time 8407729077 ps
CPU time 7.7 seconds
Started Apr 15 03:15:16 PM PDT 24
Finished Apr 15 03:15:24 PM PDT 24
Peak memory 203996 kb
Host smart-4c359ac3-0b5c-4ade-b12f-669d43e6e3e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27965
72271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2796572271
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.3844182647
Short name T166
Test name
Test status
Simulation time 8381998029 ps
CPU time 8.64 seconds
Started Apr 15 03:15:16 PM PDT 24
Finished Apr 15 03:15:25 PM PDT 24
Peak memory 204072 kb
Host smart-c36ae332-48dd-4f8d-af3a-65675c2a6822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38441
82647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.3844182647
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.2452963509
Short name T383
Test name
Test status
Simulation time 39287160 ps
CPU time 0.7 seconds
Started Apr 15 03:15:17 PM PDT 24
Finished Apr 15 03:15:18 PM PDT 24
Peak memory 203796 kb
Host smart-5b196f48-81f4-4e84-9fda-d70e8748b275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24529
63509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.2452963509
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.301130802
Short name T227
Test name
Test status
Simulation time 15245414759 ps
CPU time 28.89 seconds
Started Apr 15 03:15:21 PM PDT 24
Finished Apr 15 03:15:51 PM PDT 24
Peak memory 204160 kb
Host smart-d11c86c9-b864-48dc-9660-c5cf11e9b6e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30113
0802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.301130802
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.2891150578
Short name T293
Test name
Test status
Simulation time 8405283467 ps
CPU time 8.27 seconds
Started Apr 15 03:15:14 PM PDT 24
Finished Apr 15 03:15:23 PM PDT 24
Peak memory 204052 kb
Host smart-3ad938d2-ec77-435e-9a91-4508083dc020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28911
50578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.2891150578
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.3218688725
Short name T126
Test name
Test status
Simulation time 8444807478 ps
CPU time 7.76 seconds
Started Apr 15 03:15:13 PM PDT 24
Finished Apr 15 03:15:22 PM PDT 24
Peak memory 204072 kb
Host smart-77e0d052-2fa9-40d8-849d-57004bd35f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32186
88725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.3218688725
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.2227954810
Short name T816
Test name
Test status
Simulation time 8392974187 ps
CPU time 8.2 seconds
Started Apr 15 03:15:14 PM PDT 24
Finished Apr 15 03:15:23 PM PDT 24
Peak memory 204068 kb
Host smart-2e93752d-0bc6-453c-ada9-ae6997bf1c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22279
54810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.2227954810
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.998235964
Short name T516
Test name
Test status
Simulation time 8380396388 ps
CPU time 8.07 seconds
Started Apr 15 03:15:21 PM PDT 24
Finished Apr 15 03:15:30 PM PDT 24
Peak memory 203988 kb
Host smart-3041bf6a-641a-45fa-98ea-5aa2e67c3aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99823
5964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.998235964
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.3488312656
Short name T692
Test name
Test status
Simulation time 8388507343 ps
CPU time 8.5 seconds
Started Apr 15 03:15:17 PM PDT 24
Finished Apr 15 03:15:26 PM PDT 24
Peak memory 203988 kb
Host smart-f4a31aa9-fdb4-4dcd-a167-ae15bba4f6df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34883
12656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.3488312656
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.3022568633
Short name T640
Test name
Test status
Simulation time 8424304202 ps
CPU time 8.64 seconds
Started Apr 15 03:15:15 PM PDT 24
Finished Apr 15 03:15:25 PM PDT 24
Peak memory 204052 kb
Host smart-d237c604-33ed-4151-8d00-ffb35abed6cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30225
68633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.3022568633
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.3171654927
Short name T843
Test name
Test status
Simulation time 8400808260 ps
CPU time 9.05 seconds
Started Apr 15 03:15:15 PM PDT 24
Finished Apr 15 03:15:25 PM PDT 24
Peak memory 204040 kb
Host smart-0f7fa7ea-9dec-4f72-a9eb-c17bff4379e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31716
54927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.3171654927
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.322704400
Short name T1378
Test name
Test status
Simulation time 8394028200 ps
CPU time 9.01 seconds
Started Apr 15 03:15:15 PM PDT 24
Finished Apr 15 03:15:24 PM PDT 24
Peak memory 204008 kb
Host smart-d043d06e-677c-4a13-8e08-28f4e158a22a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32270
4400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.322704400
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.4116055968
Short name T277
Test name
Test status
Simulation time 8467069016 ps
CPU time 9.17 seconds
Started Apr 15 03:15:33 PM PDT 24
Finished Apr 15 03:15:43 PM PDT 24
Peak memory 203932 kb
Host smart-ef4fc42e-9468-4c82-a600-050dbdea9e70
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4116055968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.4116055968
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.184019469
Short name T565
Test name
Test status
Simulation time 8383715080 ps
CPU time 8.54 seconds
Started Apr 15 03:15:34 PM PDT 24
Finished Apr 15 03:15:43 PM PDT 24
Peak memory 204064 kb
Host smart-ec020ea2-5051-4cf2-8a12-f72b1b7df022
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=184019469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.184019469
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.859703083
Short name T760
Test name
Test status
Simulation time 8429139391 ps
CPU time 8.06 seconds
Started Apr 15 03:15:29 PM PDT 24
Finished Apr 15 03:15:37 PM PDT 24
Peak memory 204056 kb
Host smart-24baec2a-129e-45c4-a3da-18276e080896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85970
3083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.859703083
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3406276864
Short name T504
Test name
Test status
Simulation time 8385855784 ps
CPU time 8.24 seconds
Started Apr 15 03:15:22 PM PDT 24
Finished Apr 15 03:15:31 PM PDT 24
Peak memory 204052 kb
Host smart-9c15bcba-9265-42a1-a092-6365745330b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34062
76864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3406276864
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_enable.2488346442
Short name T579
Test name
Test status
Simulation time 8416170613 ps
CPU time 9.14 seconds
Started Apr 15 03:15:20 PM PDT 24
Finished Apr 15 03:15:30 PM PDT 24
Peak memory 204052 kb
Host smart-a37e4fdd-fde0-474a-867b-8d89c7efdc86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24883
46442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2488346442
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3480882335
Short name T938
Test name
Test status
Simulation time 184731462 ps
CPU time 1.7 seconds
Started Apr 15 03:15:17 PM PDT 24
Finished Apr 15 03:15:20 PM PDT 24
Peak memory 204124 kb
Host smart-45f24af5-4bae-429c-998e-ad308c0178bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34808
82335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3480882335
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.1098842991
Short name T574
Test name
Test status
Simulation time 8464828406 ps
CPU time 7.75 seconds
Started Apr 15 03:15:27 PM PDT 24
Finished Apr 15 03:15:35 PM PDT 24
Peak memory 204024 kb
Host smart-4e44347f-6c7d-4d9a-a545-32945aaaaa57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10988
42991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.1098842991
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.3503768182
Short name T1032
Test name
Test status
Simulation time 8370545675 ps
CPU time 7.71 seconds
Started Apr 15 03:15:26 PM PDT 24
Finished Apr 15 03:15:35 PM PDT 24
Peak memory 204056 kb
Host smart-399d3c8c-25b2-4d3a-90da-0d5c80bb4c28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35037
68182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.3503768182
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.2936351708
Short name T556
Test name
Test status
Simulation time 8414953620 ps
CPU time 8.25 seconds
Started Apr 15 03:15:19 PM PDT 24
Finished Apr 15 03:15:28 PM PDT 24
Peak memory 204048 kb
Host smart-907aacec-9cb4-4176-ab41-146cdbec929b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29363
51708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.2936351708
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.2335817483
Short name T1086
Test name
Test status
Simulation time 8408970495 ps
CPU time 7.75 seconds
Started Apr 15 03:15:22 PM PDT 24
Finished Apr 15 03:15:30 PM PDT 24
Peak memory 204076 kb
Host smart-b30dd97b-3261-48c4-a051-bc33885948a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23358
17483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.2335817483
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.409850752
Short name T899
Test name
Test status
Simulation time 8386929666 ps
CPU time 8.92 seconds
Started Apr 15 03:15:22 PM PDT 24
Finished Apr 15 03:15:31 PM PDT 24
Peak memory 204036 kb
Host smart-3bbd7a5f-8a08-4529-9470-427016bbe141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40985
0752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.409850752
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2010911717
Short name T955
Test name
Test status
Simulation time 8479334288 ps
CPU time 7.8 seconds
Started Apr 15 03:15:24 PM PDT 24
Finished Apr 15 03:15:32 PM PDT 24
Peak memory 204060 kb
Host smart-ec39dd5a-9986-4f8e-ad08-f3616ee9d146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20109
11717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2010911717
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.3494761614
Short name T690
Test name
Test status
Simulation time 8390702140 ps
CPU time 8.37 seconds
Started Apr 15 03:15:21 PM PDT 24
Finished Apr 15 03:15:30 PM PDT 24
Peak memory 204056 kb
Host smart-83bbd124-1e57-4a73-92b4-0397fd26ff5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34947
61614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.3494761614
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.4131203852
Short name T1090
Test name
Test status
Simulation time 8401610189 ps
CPU time 8.79 seconds
Started Apr 15 03:15:27 PM PDT 24
Finished Apr 15 03:15:36 PM PDT 24
Peak memory 204044 kb
Host smart-8e1cf929-be1b-4941-98f9-a16f7ed5f1ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41312
03852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.4131203852
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.1338669772
Short name T782
Test name
Test status
Simulation time 8362259384 ps
CPU time 7.28 seconds
Started Apr 15 03:15:26 PM PDT 24
Finished Apr 15 03:15:34 PM PDT 24
Peak memory 204068 kb
Host smart-4178ab30-d46a-46e7-b9ce-80d79cbcaf02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13386
69772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.1338669772
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2217215360
Short name T706
Test name
Test status
Simulation time 39981351 ps
CPU time 0.73 seconds
Started Apr 15 03:15:30 PM PDT 24
Finished Apr 15 03:15:31 PM PDT 24
Peak memory 204076 kb
Host smart-554f30dd-f6ba-48f7-b58a-60ebbf3831c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22172
15360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2217215360
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.4137606339
Short name T900
Test name
Test status
Simulation time 28832672939 ps
CPU time 60.56 seconds
Started Apr 15 03:15:27 PM PDT 24
Finished Apr 15 03:16:28 PM PDT 24
Peak memory 204336 kb
Host smart-63e51d24-3020-4919-a182-6d053979c210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41376
06339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.4137606339
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.2321967616
Short name T813
Test name
Test status
Simulation time 8458153774 ps
CPU time 8.3 seconds
Started Apr 15 03:15:22 PM PDT 24
Finished Apr 15 03:15:31 PM PDT 24
Peak memory 203988 kb
Host smart-2ae69514-15ac-405d-9c7d-e54519d435a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23219
67616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.2321967616
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2321661466
Short name T1102
Test name
Test status
Simulation time 8408950647 ps
CPU time 9.24 seconds
Started Apr 15 03:15:21 PM PDT 24
Finished Apr 15 03:15:31 PM PDT 24
Peak memory 204056 kb
Host smart-70d6c570-c60b-4808-bb57-540117d2c53e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23216
61466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2321661466
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.3764556185
Short name T443
Test name
Test status
Simulation time 8387013619 ps
CPU time 8.49 seconds
Started Apr 15 03:15:21 PM PDT 24
Finished Apr 15 03:15:30 PM PDT 24
Peak memory 204080 kb
Host smart-0f8172ef-557e-49a6-b7d3-61546b8baec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37645
56185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.3764556185
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.3913521759
Short name T1243
Test name
Test status
Simulation time 8376874283 ps
CPU time 8.88 seconds
Started Apr 15 03:15:28 PM PDT 24
Finished Apr 15 03:15:38 PM PDT 24
Peak memory 204052 kb
Host smart-66af16c2-1055-4579-8d1b-331c24d4f680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39135
21759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.3913521759
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.1581043975
Short name T593
Test name
Test status
Simulation time 8365175196 ps
CPU time 10.44 seconds
Started Apr 15 03:15:25 PM PDT 24
Finished Apr 15 03:15:36 PM PDT 24
Peak memory 204032 kb
Host smart-d15b14d0-198f-48bd-8c14-0356e467b80a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15810
43975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.1581043975
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.462803849
Short name T123
Test name
Test status
Simulation time 8465888467 ps
CPU time 9.01 seconds
Started Apr 15 03:15:19 PM PDT 24
Finished Apr 15 03:15:29 PM PDT 24
Peak memory 204028 kb
Host smart-35560a78-520e-47c9-ace6-ab081ac0a7ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46280
3849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.462803849
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.3281437341
Short name T621
Test name
Test status
Simulation time 8374709346 ps
CPU time 7.96 seconds
Started Apr 15 03:15:26 PM PDT 24
Finished Apr 15 03:15:34 PM PDT 24
Peak memory 204056 kb
Host smart-a7887953-743f-4664-86a8-389226e8c4c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32814
37341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.3281437341
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.1713102250
Short name T1255
Test name
Test status
Simulation time 8381015220 ps
CPU time 9.58 seconds
Started Apr 15 03:15:33 PM PDT 24
Finished Apr 15 03:15:43 PM PDT 24
Peak memory 204028 kb
Host smart-ae3055d9-9340-4c67-a211-6f91314c3f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17131
02250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.1713102250
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.max_length_in_transaction.2408136325
Short name T224
Test name
Test status
Simulation time 8467012638 ps
CPU time 9.87 seconds
Started Apr 15 03:15:36 PM PDT 24
Finished Apr 15 03:15:47 PM PDT 24
Peak memory 204068 kb
Host smart-b9aa596b-6110-46e1-a925-f19a1f34535c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2408136325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.2408136325
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.177245334
Short name T418
Test name
Test status
Simulation time 8381157304 ps
CPU time 7.63 seconds
Started Apr 15 03:15:37 PM PDT 24
Finished Apr 15 03:15:45 PM PDT 24
Peak memory 204036 kb
Host smart-92fd71d9-c887-4e1c-98f6-a196c28e8322
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=177245334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.177245334
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.693654279
Short name T281
Test name
Test status
Simulation time 8385085976 ps
CPU time 8.27 seconds
Started Apr 15 03:15:43 PM PDT 24
Finished Apr 15 03:15:52 PM PDT 24
Peak memory 203988 kb
Host smart-b39c4e77-e4e3-4253-840d-3ebc563639c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69365
4279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.693654279
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.202985428
Short name T1279
Test name
Test status
Simulation time 8381920782 ps
CPU time 8.17 seconds
Started Apr 15 03:15:33 PM PDT 24
Finished Apr 15 03:15:42 PM PDT 24
Peak memory 203928 kb
Host smart-2dfe75e0-6862-4f9f-a187-1368b569c9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20298
5428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.202985428
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_enable.3010244587
Short name T837
Test name
Test status
Simulation time 8377222410 ps
CPU time 9.42 seconds
Started Apr 15 03:15:36 PM PDT 24
Finished Apr 15 03:15:46 PM PDT 24
Peak memory 204044 kb
Host smart-35e7386d-ab33-48af-a845-78b0418cb63d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30102
44587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.3010244587
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.1994715178
Short name T673
Test name
Test status
Simulation time 57716860 ps
CPU time 1.41 seconds
Started Apr 15 03:15:35 PM PDT 24
Finished Apr 15 03:15:37 PM PDT 24
Peak memory 204112 kb
Host smart-e22abc6b-001d-475b-8a5d-d30acf8434b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19947
15178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1994715178
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.2884425560
Short name T669
Test name
Test status
Simulation time 8450424622 ps
CPU time 8.18 seconds
Started Apr 15 03:15:38 PM PDT 24
Finished Apr 15 03:15:47 PM PDT 24
Peak memory 204044 kb
Host smart-b4f51205-1451-43df-b37e-bb4e4a51eaa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28844
25560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.2884425560
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.1426654191
Short name T1167
Test name
Test status
Simulation time 8372356671 ps
CPU time 9.86 seconds
Started Apr 15 03:15:33 PM PDT 24
Finished Apr 15 03:15:44 PM PDT 24
Peak memory 203872 kb
Host smart-8d425cd7-ccc0-4759-9a20-770de1130167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14266
54191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.1426654191
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.596439156
Short name T1211
Test name
Test status
Simulation time 8396788760 ps
CPU time 8.84 seconds
Started Apr 15 03:15:29 PM PDT 24
Finished Apr 15 03:15:39 PM PDT 24
Peak memory 204036 kb
Host smart-6e6e29ff-b351-4040-b607-d77b6bc2d0f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59643
9156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.596439156
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.3945122582
Short name T349
Test name
Test status
Simulation time 8412822431 ps
CPU time 8.21 seconds
Started Apr 15 03:15:34 PM PDT 24
Finished Apr 15 03:15:42 PM PDT 24
Peak memory 204020 kb
Host smart-8c79adb0-be6e-407b-bbdc-8ea3ca42ea68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39451
22582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.3945122582
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.40533274
Short name T72
Test name
Test status
Simulation time 8370214727 ps
CPU time 8.07 seconds
Started Apr 15 03:15:35 PM PDT 24
Finished Apr 15 03:15:44 PM PDT 24
Peak memory 204060 kb
Host smart-00ffd0ec-49a7-45b7-9dc2-78fad74fd7cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40533
274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.40533274
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.1538778078
Short name T98
Test name
Test status
Simulation time 8405121673 ps
CPU time 10.17 seconds
Started Apr 15 03:15:30 PM PDT 24
Finished Apr 15 03:15:41 PM PDT 24
Peak memory 204048 kb
Host smart-58acc234-e85e-477a-bdbc-bf3b6c755ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15387
78078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.1538778078
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.3989900902
Short name T462
Test name
Test status
Simulation time 8387097022 ps
CPU time 8.45 seconds
Started Apr 15 03:15:31 PM PDT 24
Finished Apr 15 03:15:40 PM PDT 24
Peak memory 204028 kb
Host smart-ae2b4a93-c175-4d2b-a460-cea4b29ab4bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39899
00902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.3989900902
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.3185645329
Short name T873
Test name
Test status
Simulation time 8384794447 ps
CPU time 8.81 seconds
Started Apr 15 03:15:33 PM PDT 24
Finished Apr 15 03:15:42 PM PDT 24
Peak memory 204064 kb
Host smart-d254ff25-bd01-4e36-b95d-202b9b602f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31856
45329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.3185645329
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.3475432907
Short name T713
Test name
Test status
Simulation time 8408688350 ps
CPU time 9.33 seconds
Started Apr 15 03:15:32 PM PDT 24
Finished Apr 15 03:15:41 PM PDT 24
Peak memory 204028 kb
Host smart-402f1531-58bd-457b-b1c0-5b7aae7a2bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34754
32907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.3475432907
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3905714632
Short name T9
Test name
Test status
Simulation time 8379021096 ps
CPU time 9.47 seconds
Started Apr 15 03:15:34 PM PDT 24
Finished Apr 15 03:15:44 PM PDT 24
Peak memory 204052 kb
Host smart-b1b65ee7-fe08-4774-a4c7-c79d818ca074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39057
14632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3905714632
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.64545951
Short name T959
Test name
Test status
Simulation time 39916865 ps
CPU time 0.66 seconds
Started Apr 15 03:15:33 PM PDT 24
Finished Apr 15 03:15:35 PM PDT 24
Peak memory 203892 kb
Host smart-47fe7b52-a3e1-455c-b265-25773aa5c1db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64545
951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.64545951
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.811827709
Short name T233
Test name
Test status
Simulation time 20838519972 ps
CPU time 38.25 seconds
Started Apr 15 03:15:33 PM PDT 24
Finished Apr 15 03:16:12 PM PDT 24
Peak memory 204332 kb
Host smart-538834cb-ed2b-4da7-ac79-32ba2f967eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81182
7709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.811827709
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1177748021
Short name T1322
Test name
Test status
Simulation time 8377054597 ps
CPU time 9.3 seconds
Started Apr 15 03:15:36 PM PDT 24
Finished Apr 15 03:15:46 PM PDT 24
Peak memory 203992 kb
Host smart-e46754dd-f7b8-40a0-827a-7b83ac871685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11777
48021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1177748021
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.1332396126
Short name T775
Test name
Test status
Simulation time 8434901894 ps
CPU time 8.68 seconds
Started Apr 15 03:15:35 PM PDT 24
Finished Apr 15 03:15:45 PM PDT 24
Peak memory 204060 kb
Host smart-23c1c716-4b92-425f-b6c6-849fbe7f137b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13323
96126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.1332396126
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.3454686902
Short name T1103
Test name
Test status
Simulation time 8409872663 ps
CPU time 10.05 seconds
Started Apr 15 03:15:33 PM PDT 24
Finished Apr 15 03:15:44 PM PDT 24
Peak memory 204024 kb
Host smart-a0323487-27d3-4c7a-bb99-a339eb9b3e70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34546
86902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.3454686902
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.2616433039
Short name T1029
Test name
Test status
Simulation time 8376863560 ps
CPU time 9.64 seconds
Started Apr 15 03:15:37 PM PDT 24
Finished Apr 15 03:15:48 PM PDT 24
Peak memory 204044 kb
Host smart-5183a112-fa17-4d97-956b-91a2005aa143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26164
33039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.2616433039
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.3183385694
Short name T1048
Test name
Test status
Simulation time 8369098995 ps
CPU time 8.1 seconds
Started Apr 15 03:15:32 PM PDT 24
Finished Apr 15 03:15:41 PM PDT 24
Peak memory 204060 kb
Host smart-038523c3-6503-4689-a560-d9459cb93b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31833
85694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.3183385694
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.2427350133
Short name T154
Test name
Test status
Simulation time 8417541543 ps
CPU time 9.39 seconds
Started Apr 15 03:15:33 PM PDT 24
Finished Apr 15 03:15:43 PM PDT 24
Peak memory 203928 kb
Host smart-0c407066-b498-4cef-9f01-8256380fa3ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24273
50133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.2427350133
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.1130580058
Short name T768
Test name
Test status
Simulation time 8469350960 ps
CPU time 7.77 seconds
Started Apr 15 03:15:39 PM PDT 24
Finished Apr 15 03:15:48 PM PDT 24
Peak memory 204048 kb
Host smart-fdc1e8f1-1b8e-47d6-98c3-833bb45fe8c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11305
80058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.1130580058
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.3746270129
Short name T1025
Test name
Test status
Simulation time 8403481602 ps
CPU time 7.97 seconds
Started Apr 15 03:15:38 PM PDT 24
Finished Apr 15 03:15:47 PM PDT 24
Peak memory 204044 kb
Host smart-850448c3-4895-48f0-870c-c6ed0ac2fc99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37462
70129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.3746270129
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.max_length_in_transaction.3006873542
Short name T1373
Test name
Test status
Simulation time 8464553724 ps
CPU time 8.71 seconds
Started Apr 15 03:15:44 PM PDT 24
Finished Apr 15 03:15:53 PM PDT 24
Peak memory 204068 kb
Host smart-5e927962-db34-4859-901c-37c15224b40e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3006873542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.3006873542
Directory /workspace/25.max_length_in_transaction/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.909577216
Short name T526
Test name
Test status
Simulation time 8388581827 ps
CPU time 8.43 seconds
Started Apr 15 03:15:45 PM PDT 24
Finished Apr 15 03:15:54 PM PDT 24
Peak memory 204064 kb
Host smart-12af36d4-b8a1-449e-9cf0-81434c8d62dd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=909577216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.909577216
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.2708337145
Short name T612
Test name
Test status
Simulation time 8435396688 ps
CPU time 8.89 seconds
Started Apr 15 03:15:44 PM PDT 24
Finished Apr 15 03:15:54 PM PDT 24
Peak memory 204052 kb
Host smart-5887a8f7-4193-477c-bd84-b81675b2de14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27083
37145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.2708337145
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.3935334054
Short name T689
Test name
Test status
Simulation time 8381015048 ps
CPU time 8.05 seconds
Started Apr 15 03:15:38 PM PDT 24
Finished Apr 15 03:15:47 PM PDT 24
Peak memory 204052 kb
Host smart-be57cee4-46a2-4244-9011-cdaf0210130c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39353
34054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.3935334054
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_enable.111771140
Short name T632
Test name
Test status
Simulation time 8373936579 ps
CPU time 8.56 seconds
Started Apr 15 03:15:42 PM PDT 24
Finished Apr 15 03:15:51 PM PDT 24
Peak memory 204020 kb
Host smart-281d4142-63e6-4eb8-a884-9b7b9bc492bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11177
1140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.111771140
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1904739574
Short name T1367
Test name
Test status
Simulation time 94047153 ps
CPU time 1.17 seconds
Started Apr 15 03:15:43 PM PDT 24
Finished Apr 15 03:15:45 PM PDT 24
Peak memory 204196 kb
Host smart-167d8275-79d4-452c-977b-a5ccd90a4e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19047
39574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1904739574
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.145566902
Short name T785
Test name
Test status
Simulation time 8466519824 ps
CPU time 9.3 seconds
Started Apr 15 03:15:58 PM PDT 24
Finished Apr 15 03:16:08 PM PDT 24
Peak memory 204024 kb
Host smart-156b95e2-de50-485d-8012-284118898d42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14556
6902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.145566902
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.2776975659
Short name T185
Test name
Test status
Simulation time 8407693847 ps
CPU time 8.11 seconds
Started Apr 15 03:15:43 PM PDT 24
Finished Apr 15 03:15:52 PM PDT 24
Peak memory 204044 kb
Host smart-2db41bc2-d4b0-4241-8d93-c1e0bd782d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27769
75659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.2776975659
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.1686723129
Short name T448
Test name
Test status
Simulation time 8477938923 ps
CPU time 7.85 seconds
Started Apr 15 03:15:43 PM PDT 24
Finished Apr 15 03:15:51 PM PDT 24
Peak memory 203976 kb
Host smart-43d6901a-dfdd-4861-9958-b9afd6961918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16867
23129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.1686723129
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1454721577
Short name T307
Test name
Test status
Simulation time 8413437660 ps
CPU time 8.12 seconds
Started Apr 15 03:15:41 PM PDT 24
Finished Apr 15 03:15:49 PM PDT 24
Peak memory 204024 kb
Host smart-930afc80-1b33-44e2-b93b-d9615d61b364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14547
21577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1454721577
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.1299933609
Short name T577
Test name
Test status
Simulation time 8373452723 ps
CPU time 8.58 seconds
Started Apr 15 03:15:43 PM PDT 24
Finished Apr 15 03:15:52 PM PDT 24
Peak memory 203988 kb
Host smart-78b4a35f-96b0-4e6b-9f6e-2229ba16e3d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12999
33609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.1299933609
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.2317971636
Short name T114
Test name
Test status
Simulation time 8450996462 ps
CPU time 8.46 seconds
Started Apr 15 03:15:40 PM PDT 24
Finished Apr 15 03:15:49 PM PDT 24
Peak memory 204032 kb
Host smart-bf88afec-f768-41b2-ab39-519492050fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23179
71636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.2317971636
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.2720167830
Short name T580
Test name
Test status
Simulation time 8409322327 ps
CPU time 7.86 seconds
Started Apr 15 03:15:40 PM PDT 24
Finished Apr 15 03:15:49 PM PDT 24
Peak memory 204008 kb
Host smart-a6d49382-d6f5-4202-a446-f3a687a6f3a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27201
67830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2720167830
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.2761781123
Short name T290
Test name
Test status
Simulation time 8409264491 ps
CPU time 8.23 seconds
Started Apr 15 03:15:41 PM PDT 24
Finished Apr 15 03:15:50 PM PDT 24
Peak memory 204072 kb
Host smart-c108d091-0c5b-4677-8b6d-5b0aba32bf9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27617
81123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.2761781123
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.1375210099
Short name T471
Test name
Test status
Simulation time 8420170495 ps
CPU time 8.04 seconds
Started Apr 15 03:15:44 PM PDT 24
Finished Apr 15 03:15:52 PM PDT 24
Peak memory 204076 kb
Host smart-f43d86a4-96aa-4f3f-89c2-f5e4e7d2937d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13752
10099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.1375210099
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.3058651987
Short name T465
Test name
Test status
Simulation time 8412384605 ps
CPU time 7.74 seconds
Started Apr 15 03:15:44 PM PDT 24
Finished Apr 15 03:15:53 PM PDT 24
Peak memory 204028 kb
Host smart-ac41e6f9-ceef-4d18-9006-fd392a106e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30586
51987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.3058651987
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.3000368284
Short name T1185
Test name
Test status
Simulation time 36155596 ps
CPU time 0.65 seconds
Started Apr 15 03:15:47 PM PDT 24
Finished Apr 15 03:15:49 PM PDT 24
Peak memory 203928 kb
Host smart-d792e8ff-6516-4c74-a5ac-d7e74e385eab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30003
68284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.3000368284
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.778040494
Short name T1273
Test name
Test status
Simulation time 15114901284 ps
CPU time 27.73 seconds
Started Apr 15 03:15:42 PM PDT 24
Finished Apr 15 03:16:11 PM PDT 24
Peak memory 204268 kb
Host smart-b3c5b9e2-c1be-455f-ac52-dbdb4d331716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77804
0494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.778040494
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.1115264989
Short name T308
Test name
Test status
Simulation time 8412018097 ps
CPU time 8.24 seconds
Started Apr 15 03:15:39 PM PDT 24
Finished Apr 15 03:15:48 PM PDT 24
Peak memory 204032 kb
Host smart-05c5407c-9206-4c42-976b-6f6320703165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11152
64989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.1115264989
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.842858373
Short name T139
Test name
Test status
Simulation time 8433426149 ps
CPU time 9.1 seconds
Started Apr 15 03:15:42 PM PDT 24
Finished Apr 15 03:15:52 PM PDT 24
Peak memory 204020 kb
Host smart-84608124-9701-4f4a-b911-de50aa498e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84285
8373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.842858373
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.3628116622
Short name T651
Test name
Test status
Simulation time 8428846343 ps
CPU time 7.63 seconds
Started Apr 15 03:15:42 PM PDT 24
Finished Apr 15 03:15:51 PM PDT 24
Peak memory 203980 kb
Host smart-434b710b-e38d-408b-a14a-78a1b34e07ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36281
16622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.3628116622
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.2658920059
Short name T497
Test name
Test status
Simulation time 8382832128 ps
CPU time 8.32 seconds
Started Apr 15 03:15:44 PM PDT 24
Finished Apr 15 03:15:53 PM PDT 24
Peak memory 203972 kb
Host smart-56051bea-1e5a-417e-95f9-e6d95ad00236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26589
20059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.2658920059
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.2819074210
Short name T1044
Test name
Test status
Simulation time 8370426631 ps
CPU time 7.94 seconds
Started Apr 15 03:15:42 PM PDT 24
Finished Apr 15 03:15:50 PM PDT 24
Peak memory 204024 kb
Host smart-0d24c73c-df37-46ea-8891-935792ee89f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28190
74210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.2819074210
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.1886957372
Short name T773
Test name
Test status
Simulation time 8487679898 ps
CPU time 8.49 seconds
Started Apr 15 03:15:37 PM PDT 24
Finished Apr 15 03:15:46 PM PDT 24
Peak memory 204048 kb
Host smart-4cfd1cac-d6f1-4c0e-923f-2765b6b7b52b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18869
57372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1886957372
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.1947429841
Short name T771
Test name
Test status
Simulation time 8379379717 ps
CPU time 7.96 seconds
Started Apr 15 03:15:58 PM PDT 24
Finished Apr 15 03:16:07 PM PDT 24
Peak memory 204016 kb
Host smart-4684e38e-887f-4301-b5ed-eba0aa38c462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19474
29841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.1947429841
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.517769885
Short name T529
Test name
Test status
Simulation time 8387361180 ps
CPU time 8.12 seconds
Started Apr 15 03:15:40 PM PDT 24
Finished Apr 15 03:15:49 PM PDT 24
Peak memory 204060 kb
Host smart-39e920a4-982a-4a6f-a107-ddb83999233c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51776
9885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.517769885
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.max_length_in_transaction.3418620435
Short name T1342
Test name
Test status
Simulation time 8501587056 ps
CPU time 8.39 seconds
Started Apr 15 03:15:58 PM PDT 24
Finished Apr 15 03:16:07 PM PDT 24
Peak memory 204048 kb
Host smart-d3abdd7e-4f75-463a-a789-e79cd7b08a10
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3418620435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.3418620435
Directory /workspace/26.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.317921480
Short name T1153
Test name
Test status
Simulation time 8402217254 ps
CPU time 7.93 seconds
Started Apr 15 03:15:53 PM PDT 24
Finished Apr 15 03:16:02 PM PDT 24
Peak memory 204012 kb
Host smart-5145bf8d-8f40-4f1e-a5da-83520ba6690b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=317921480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.317921480
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.1052223886
Short name T1130
Test name
Test status
Simulation time 8513842316 ps
CPU time 10.27 seconds
Started Apr 15 03:15:54 PM PDT 24
Finished Apr 15 03:16:05 PM PDT 24
Peak memory 204200 kb
Host smart-f9d3c4b8-7418-4fc5-9213-64676494bddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10522
23886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.1052223886
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1391196079
Short name T76
Test name
Test status
Simulation time 8378249010 ps
CPU time 7.5 seconds
Started Apr 15 03:15:52 PM PDT 24
Finished Apr 15 03:16:00 PM PDT 24
Peak memory 204052 kb
Host smart-65f6c369-ac83-45f2-b26d-5cccffda0857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13911
96079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1391196079
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_enable.318947746
Short name T315
Test name
Test status
Simulation time 8380964019 ps
CPU time 8.29 seconds
Started Apr 15 03:15:58 PM PDT 24
Finished Apr 15 03:16:07 PM PDT 24
Peak memory 204028 kb
Host smart-603829ee-2248-452e-b3a4-e5a6bb9c0c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31894
7746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.318947746
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.4161172235
Short name T712
Test name
Test status
Simulation time 278785867 ps
CPU time 2.31 seconds
Started Apr 15 03:15:50 PM PDT 24
Finished Apr 15 03:15:53 PM PDT 24
Peak memory 204052 kb
Host smart-9621fd09-727b-401c-af64-28ea39d719fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41611
72235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.4161172235
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.1003918765
Short name T960
Test name
Test status
Simulation time 8429724440 ps
CPU time 8.06 seconds
Started Apr 15 03:15:55 PM PDT 24
Finished Apr 15 03:16:04 PM PDT 24
Peak memory 203968 kb
Host smart-446a6f11-320a-4960-a0f6-740c41238b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10039
18765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.1003918765
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.3288827769
Short name T801
Test name
Test status
Simulation time 8380474210 ps
CPU time 8.74 seconds
Started Apr 15 03:15:52 PM PDT 24
Finished Apr 15 03:16:01 PM PDT 24
Peak memory 203872 kb
Host smart-dd35dc5d-71a5-4175-83bc-f8e74cef5dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32888
27769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.3288827769
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3541229518
Short name T37
Test name
Test status
Simulation time 8447789255 ps
CPU time 8.08 seconds
Started Apr 15 03:15:55 PM PDT 24
Finished Apr 15 03:16:04 PM PDT 24
Peak memory 203988 kb
Host smart-3ed2d00b-7f7f-4310-8724-c22a7d23a419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35412
29518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3541229518
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3043324503
Short name T381
Test name
Test status
Simulation time 8422237533 ps
CPU time 8.1 seconds
Started Apr 15 03:15:49 PM PDT 24
Finished Apr 15 03:15:58 PM PDT 24
Peak memory 204060 kb
Host smart-93c8ee44-9727-40cc-a407-f4057afb8eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30433
24503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3043324503
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2170896835
Short name T769
Test name
Test status
Simulation time 8383251900 ps
CPU time 7.47 seconds
Started Apr 15 03:15:47 PM PDT 24
Finished Apr 15 03:15:55 PM PDT 24
Peak memory 204008 kb
Host smart-0dbd76a5-117a-48ed-83e4-87290e222ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21708
96835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2170896835
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.531589757
Short name T87
Test name
Test status
Simulation time 8450097870 ps
CPU time 8.7 seconds
Started Apr 15 03:15:49 PM PDT 24
Finished Apr 15 03:15:59 PM PDT 24
Peak memory 204052 kb
Host smart-4359e5c2-f954-4b69-84d1-f8cb899a2320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53158
9757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.531589757
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.1624295349
Short name T917
Test name
Test status
Simulation time 8404413240 ps
CPU time 8.32 seconds
Started Apr 15 03:15:48 PM PDT 24
Finished Apr 15 03:15:56 PM PDT 24
Peak memory 204008 kb
Host smart-a9a1130f-63c0-4a56-8235-7a17ae94c5d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16242
95349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.1624295349
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1218032006
Short name T832
Test name
Test status
Simulation time 8385794039 ps
CPU time 8.31 seconds
Started Apr 15 03:15:47 PM PDT 24
Finished Apr 15 03:15:56 PM PDT 24
Peak memory 204028 kb
Host smart-03f31f39-18d4-4488-b6c3-9efff1ebf4a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12180
32006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1218032006
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.2869673226
Short name T186
Test name
Test status
Simulation time 8426817167 ps
CPU time 7.64 seconds
Started Apr 15 03:15:55 PM PDT 24
Finished Apr 15 03:16:03 PM PDT 24
Peak memory 204036 kb
Host smart-25c0fa95-f2dc-4d71-9681-b69c3f48fbfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28696
73226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.2869673226
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.822118632
Short name T1317
Test name
Test status
Simulation time 8366010413 ps
CPU time 8.08 seconds
Started Apr 15 03:15:53 PM PDT 24
Finished Apr 15 03:16:02 PM PDT 24
Peak memory 204044 kb
Host smart-f1e21690-cd1a-4712-8a73-7784ea9d4cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82211
8632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.822118632
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.2536533294
Short name T1278
Test name
Test status
Simulation time 40005902 ps
CPU time 0.67 seconds
Started Apr 15 03:15:53 PM PDT 24
Finished Apr 15 03:15:55 PM PDT 24
Peak memory 203876 kb
Host smart-68fc5206-4fbe-4ed5-b5de-5a62c46941f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25365
33294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.2536533294
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.2412647044
Short name T433
Test name
Test status
Simulation time 31358480149 ps
CPU time 63.79 seconds
Started Apr 15 03:15:50 PM PDT 24
Finished Apr 15 03:16:55 PM PDT 24
Peak memory 204488 kb
Host smart-347922c8-00f5-44fa-a7ef-df821c4942f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24126
47044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.2412647044
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.648547454
Short name T850
Test name
Test status
Simulation time 8400881922 ps
CPU time 8.08 seconds
Started Apr 15 03:15:47 PM PDT 24
Finished Apr 15 03:15:56 PM PDT 24
Peak memory 204056 kb
Host smart-3238e349-300d-48e0-99ba-ab63cc33dd34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64854
7454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.648547454
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2222336042
Short name T445
Test name
Test status
Simulation time 8446076624 ps
CPU time 8.13 seconds
Started Apr 15 03:15:58 PM PDT 24
Finished Apr 15 03:16:07 PM PDT 24
Peak memory 204020 kb
Host smart-cc7b7045-24fd-42de-ba83-be1545156184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22223
36042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2222336042
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.2799476112
Short name T1160
Test name
Test status
Simulation time 8412838668 ps
CPU time 8.55 seconds
Started Apr 15 03:15:48 PM PDT 24
Finished Apr 15 03:15:58 PM PDT 24
Peak memory 204068 kb
Host smart-ef703a17-08dd-49ac-92e4-6a1f436582c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27994
76112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.2799476112
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.516655963
Short name T159
Test name
Test status
Simulation time 8374280746 ps
CPU time 8.59 seconds
Started Apr 15 03:15:53 PM PDT 24
Finished Apr 15 03:16:02 PM PDT 24
Peak memory 204016 kb
Host smart-881e61ce-c39d-46fa-b4d3-80eb6d8459a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51665
5963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.516655963
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.958691735
Short name T958
Test name
Test status
Simulation time 8369623353 ps
CPU time 8.53 seconds
Started Apr 15 03:15:55 PM PDT 24
Finished Apr 15 03:16:05 PM PDT 24
Peak memory 203984 kb
Host smart-3dca1fb1-135f-4dd7-aa29-c79e601fac6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95869
1735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.958691735
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.939515167
Short name T1028
Test name
Test status
Simulation time 8389315346 ps
CPU time 7.83 seconds
Started Apr 15 03:15:50 PM PDT 24
Finished Apr 15 03:15:58 PM PDT 24
Peak memory 204196 kb
Host smart-3f288012-79e7-45d7-b351-daf55d903192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93951
5167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.939515167
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.441187435
Short name T1031
Test name
Test status
Simulation time 8410316823 ps
CPU time 8.44 seconds
Started Apr 15 03:15:58 PM PDT 24
Finished Apr 15 03:16:07 PM PDT 24
Peak memory 204024 kb
Host smart-5624b21f-d2f9-4b12-bfdb-2b6659e854a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44118
7435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.441187435
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.39997343
Short name T1023
Test name
Test status
Simulation time 8482568842 ps
CPU time 8.41 seconds
Started Apr 15 03:16:12 PM PDT 24
Finished Apr 15 03:16:21 PM PDT 24
Peak memory 203988 kb
Host smart-0daa884b-935a-46ea-a1c1-05f4b8ac0f84
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=39997343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.39997343
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.2260603642
Short name T724
Test name
Test status
Simulation time 8377485517 ps
CPU time 7.84 seconds
Started Apr 15 03:16:08 PM PDT 24
Finished Apr 15 03:16:16 PM PDT 24
Peak memory 204032 kb
Host smart-be5e4753-f85a-44bb-be78-58c5c3560363
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2260603642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.2260603642
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.718743153
Short name T1286
Test name
Test status
Simulation time 8398824773 ps
CPU time 8.21 seconds
Started Apr 15 03:16:02 PM PDT 24
Finished Apr 15 03:16:11 PM PDT 24
Peak memory 204056 kb
Host smart-9dc6ad44-0cbd-4f90-9770-245aafb8f478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71874
3153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.718743153
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.1433156357
Short name T1065
Test name
Test status
Simulation time 8424773874 ps
CPU time 8.42 seconds
Started Apr 15 03:15:55 PM PDT 24
Finished Apr 15 03:16:05 PM PDT 24
Peak memory 204052 kb
Host smart-acc9c050-a507-4eef-971d-c874d2b1ff56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14331
56357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.1433156357
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_enable.2342808191
Short name T309
Test name
Test status
Simulation time 8393208378 ps
CPU time 8.12 seconds
Started Apr 15 03:15:55 PM PDT 24
Finished Apr 15 03:16:03 PM PDT 24
Peak memory 204048 kb
Host smart-b9ca0387-c392-4870-aff4-8d020263d6fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23428
08191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2342808191
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.3679808386
Short name T835
Test name
Test status
Simulation time 83077443 ps
CPU time 1.75 seconds
Started Apr 15 03:16:10 PM PDT 24
Finished Apr 15 03:16:13 PM PDT 24
Peak memory 204068 kb
Host smart-05db076f-889f-4bea-a5a6-10a8ab480a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36798
08386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.3679808386
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.3450027183
Short name T921
Test name
Test status
Simulation time 8452133551 ps
CPU time 10.16 seconds
Started Apr 15 03:16:13 PM PDT 24
Finished Apr 15 03:16:24 PM PDT 24
Peak memory 203816 kb
Host smart-02e6cbb1-fa77-4cd8-9478-aebf26337c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34500
27183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.3450027183
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2813916833
Short name T1192
Test name
Test status
Simulation time 8392890899 ps
CPU time 8.19 seconds
Started Apr 15 03:16:14 PM PDT 24
Finished Apr 15 03:16:23 PM PDT 24
Peak memory 203984 kb
Host smart-6b4575f0-6b58-4a5e-8045-022e0cff56e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28139
16833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2813916833
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.4199374378
Short name T671
Test name
Test status
Simulation time 8460241303 ps
CPU time 10.15 seconds
Started Apr 15 03:16:00 PM PDT 24
Finished Apr 15 03:16:11 PM PDT 24
Peak memory 203988 kb
Host smart-85d53c47-10d6-47ee-bea3-7890d5c8053d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41993
74378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.4199374378
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.1852636577
Short name T780
Test name
Test status
Simulation time 8412508437 ps
CPU time 7.59 seconds
Started Apr 15 03:15:56 PM PDT 24
Finished Apr 15 03:16:04 PM PDT 24
Peak memory 204008 kb
Host smart-71368e79-bc3b-4353-9047-d8b3998016ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18526
36577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.1852636577
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.1353934316
Short name T997
Test name
Test status
Simulation time 8371090176 ps
CPU time 9.64 seconds
Started Apr 15 03:15:57 PM PDT 24
Finished Apr 15 03:16:07 PM PDT 24
Peak memory 204052 kb
Host smart-6b086a4d-bbbd-4086-8b9a-527b1277dfb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13539
34316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.1353934316
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1468890560
Short name T106
Test name
Test status
Simulation time 8445897874 ps
CPU time 8.61 seconds
Started Apr 15 03:15:54 PM PDT 24
Finished Apr 15 03:16:03 PM PDT 24
Peak memory 204052 kb
Host smart-6dc93362-85d0-42bd-94d8-f79eb4d1cfb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14688
90560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1468890560
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.1925094719
Short name T1360
Test name
Test status
Simulation time 8383350063 ps
CPU time 8.14 seconds
Started Apr 15 03:15:56 PM PDT 24
Finished Apr 15 03:16:05 PM PDT 24
Peak memory 203928 kb
Host smart-33d2f0d9-67cf-45dc-abe5-a911c3b9a6b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19250
94719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1925094719
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.1177007064
Short name T1288
Test name
Test status
Simulation time 8379800576 ps
CPU time 8.77 seconds
Started Apr 15 03:15:58 PM PDT 24
Finished Apr 15 03:16:07 PM PDT 24
Peak memory 204056 kb
Host smart-f6018ccf-a5ed-408f-a48f-77d82924ba76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11770
07064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.1177007064
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.2528937562
Short name T442
Test name
Test status
Simulation time 8396810665 ps
CPU time 8.08 seconds
Started Apr 15 03:16:00 PM PDT 24
Finished Apr 15 03:16:08 PM PDT 24
Peak memory 203968 kb
Host smart-6567eac1-377b-4f9e-b3a1-baa83d859a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25289
37562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.2528937562
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.3239535647
Short name T1267
Test name
Test status
Simulation time 8376139331 ps
CPU time 7.69 seconds
Started Apr 15 03:16:14 PM PDT 24
Finished Apr 15 03:16:22 PM PDT 24
Peak memory 203992 kb
Host smart-c87540bd-66be-4441-b22e-55a528e97a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32395
35647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.3239535647
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3811465616
Short name T1036
Test name
Test status
Simulation time 68784425 ps
CPU time 0.71 seconds
Started Apr 15 03:15:59 PM PDT 24
Finished Apr 15 03:16:01 PM PDT 24
Peak memory 203868 kb
Host smart-64bc8759-1c45-4c74-aaac-e0ac6068495b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38114
65616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3811465616
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.646942867
Short name T82
Test name
Test status
Simulation time 30286934920 ps
CPU time 67.73 seconds
Started Apr 15 03:15:58 PM PDT 24
Finished Apr 15 03:17:07 PM PDT 24
Peak memory 204356 kb
Host smart-af7c006d-5873-4b65-98d8-72f99da1b0d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64694
2867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.646942867
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.2596676188
Short name T740
Test name
Test status
Simulation time 8480048084 ps
CPU time 8.59 seconds
Started Apr 15 03:15:59 PM PDT 24
Finished Apr 15 03:16:08 PM PDT 24
Peak memory 204076 kb
Host smart-2f6ab6e2-4997-4e00-8b2c-28daf253b79d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25966
76188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.2596676188
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.2677983379
Short name T3
Test name
Test status
Simulation time 8448132813 ps
CPU time 8.7 seconds
Started Apr 15 03:15:58 PM PDT 24
Finished Apr 15 03:16:08 PM PDT 24
Peak memory 204068 kb
Host smart-0d7b7992-3247-4c0a-ba5a-83d1f9f47c3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26779
83379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.2677983379
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.2633664036
Short name T748
Test name
Test status
Simulation time 8366957531 ps
CPU time 7.36 seconds
Started Apr 15 03:16:01 PM PDT 24
Finished Apr 15 03:16:09 PM PDT 24
Peak memory 204052 kb
Host smart-d239060b-488b-4df6-a989-c99b9d7d5dc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26336
64036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.2633664036
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.2248019900
Short name T717
Test name
Test status
Simulation time 8400579336 ps
CPU time 7.82 seconds
Started Apr 15 03:15:59 PM PDT 24
Finished Apr 15 03:16:08 PM PDT 24
Peak memory 204028 kb
Host smart-8c24608c-93ef-4008-96e3-6b3c0dc40156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22480
19900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.2248019900
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.4283056897
Short name T786
Test name
Test status
Simulation time 8373199287 ps
CPU time 7.79 seconds
Started Apr 15 03:16:13 PM PDT 24
Finished Apr 15 03:16:21 PM PDT 24
Peak memory 203764 kb
Host smart-bc1a8fcb-dd12-4470-ba40-654aabbadf48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42830
56897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.4283056897
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2214779483
Short name T941
Test name
Test status
Simulation time 8442035943 ps
CPU time 9.49 seconds
Started Apr 15 03:15:56 PM PDT 24
Finished Apr 15 03:16:06 PM PDT 24
Peak memory 204004 kb
Host smart-40c64807-2a87-4539-af1c-1c4db2dbf1ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22147
79483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2214779483
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.884840980
Short name T1021
Test name
Test status
Simulation time 8387429813 ps
CPU time 7.85 seconds
Started Apr 15 03:15:58 PM PDT 24
Finished Apr 15 03:16:07 PM PDT 24
Peak memory 204060 kb
Host smart-34ab081f-4236-4a29-810b-493e94b35498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88484
0980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.884840980
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.4115758113
Short name T1299
Test name
Test status
Simulation time 8411924953 ps
CPU time 9.83 seconds
Started Apr 15 03:16:06 PM PDT 24
Finished Apr 15 03:16:16 PM PDT 24
Peak memory 204028 kb
Host smart-cca1a898-e09e-4692-acfe-00b1aa11f6e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41157
58113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.4115758113
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.1425099381
Short name T476
Test name
Test status
Simulation time 8469786727 ps
CPU time 8.56 seconds
Started Apr 15 03:16:11 PM PDT 24
Finished Apr 15 03:16:20 PM PDT 24
Peak memory 204076 kb
Host smart-1dfa1edf-2bd4-42d6-844d-c1a22e3d9785
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1425099381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.1425099381
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.3463380834
Short name T763
Test name
Test status
Simulation time 8384026892 ps
CPU time 8.76 seconds
Started Apr 15 03:16:10 PM PDT 24
Finished Apr 15 03:16:20 PM PDT 24
Peak memory 204060 kb
Host smart-9e5fdd0c-2e82-46c6-8f75-9320e452953d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3463380834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.3463380834
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.1503550814
Short name T299
Test name
Test status
Simulation time 8441564588 ps
CPU time 8.68 seconds
Started Apr 15 03:16:12 PM PDT 24
Finished Apr 15 03:16:21 PM PDT 24
Peak memory 203972 kb
Host smart-c7a71482-f596-4532-a5a1-0e8d7e263bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15035
50814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.1503550814
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.2657340207
Short name T1187
Test name
Test status
Simulation time 8381889375 ps
CPU time 8.77 seconds
Started Apr 15 03:16:03 PM PDT 24
Finished Apr 15 03:16:12 PM PDT 24
Peak memory 204048 kb
Host smart-085b5207-ea12-4137-b6c8-0a0305d6159b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26573
40207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.2657340207
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_enable.3612072502
Short name T710
Test name
Test status
Simulation time 8379225646 ps
CPU time 8.42 seconds
Started Apr 15 03:16:08 PM PDT 24
Finished Apr 15 03:16:17 PM PDT 24
Peak memory 204028 kb
Host smart-a6b5819a-c7b7-42fc-9007-c701a3227f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36120
72502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3612072502
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.1804554960
Short name T937
Test name
Test status
Simulation time 83926673 ps
CPU time 1.79 seconds
Started Apr 15 03:16:08 PM PDT 24
Finished Apr 15 03:16:11 PM PDT 24
Peak memory 204096 kb
Host smart-30934d9c-10ba-4426-a201-21758119f568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18045
54960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.1804554960
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.211548970
Short name T133
Test name
Test status
Simulation time 8387435642 ps
CPU time 7.89 seconds
Started Apr 15 03:16:10 PM PDT 24
Finished Apr 15 03:16:18 PM PDT 24
Peak memory 204076 kb
Host smart-30f585c6-c2da-486b-ba42-81e49b433b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21154
8970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.211548970
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.2519317442
Short name T182
Test name
Test status
Simulation time 8366134394 ps
CPU time 7.59 seconds
Started Apr 15 03:16:08 PM PDT 24
Finished Apr 15 03:16:17 PM PDT 24
Peak memory 204056 kb
Host smart-0440fff0-f257-45ab-8086-3924dddb5e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25193
17442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.2519317442
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.2500223249
Short name T652
Test name
Test status
Simulation time 8447203711 ps
CPU time 7.58 seconds
Started Apr 15 03:16:03 PM PDT 24
Finished Apr 15 03:16:11 PM PDT 24
Peak memory 204048 kb
Host smart-8f71c917-c96d-4605-9902-602a7f2b772c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25002
23249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.2500223249
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.2785442418
Short name T761
Test name
Test status
Simulation time 8440124961 ps
CPU time 7.94 seconds
Started Apr 15 03:16:02 PM PDT 24
Finished Apr 15 03:16:11 PM PDT 24
Peak memory 204060 kb
Host smart-82e37bf9-0c5d-4ad8-952c-96f0df2bf7b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27854
42418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.2785442418
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.19808713
Short name T1113
Test name
Test status
Simulation time 8401759552 ps
CPU time 7.41 seconds
Started Apr 15 03:16:03 PM PDT 24
Finished Apr 15 03:16:11 PM PDT 24
Peak memory 204048 kb
Host smart-3b32264f-e748-471d-a49a-542c6911e9cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19808
713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.19808713
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.1170688403
Short name T1210
Test name
Test status
Simulation time 8409568446 ps
CPU time 9.85 seconds
Started Apr 15 03:16:06 PM PDT 24
Finished Apr 15 03:16:17 PM PDT 24
Peak memory 204028 kb
Host smart-014a5b64-489b-479c-98eb-12678b56b334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11706
88403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.1170688403
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.1132339935
Short name T352
Test name
Test status
Simulation time 8417771989 ps
CPU time 8.52 seconds
Started Apr 15 03:16:02 PM PDT 24
Finished Apr 15 03:16:11 PM PDT 24
Peak memory 204048 kb
Host smart-c6d018b3-56e2-41f5-acfb-f02a807035d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11323
39935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1132339935
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.3907143196
Short name T1008
Test name
Test status
Simulation time 8375343503 ps
CPU time 9.36 seconds
Started Apr 15 03:16:11 PM PDT 24
Finished Apr 15 03:16:21 PM PDT 24
Peak memory 204048 kb
Host smart-3ae3d242-3544-4b06-bce9-8ccb418da806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39071
43196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.3907143196
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.339509780
Short name T25
Test name
Test status
Simulation time 8407594432 ps
CPU time 8.6 seconds
Started Apr 15 03:16:08 PM PDT 24
Finished Apr 15 03:16:17 PM PDT 24
Peak memory 204044 kb
Host smart-95fcaf61-11ad-4321-8186-ce92513d26a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33950
9780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.339509780
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.2579099470
Short name T1346
Test name
Test status
Simulation time 40680435 ps
CPU time 0.68 seconds
Started Apr 15 03:16:10 PM PDT 24
Finished Apr 15 03:16:11 PM PDT 24
Peak memory 203860 kb
Host smart-cc8e247c-5462-446d-b7a8-1069a12809cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25790
99470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.2579099470
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.4172096042
Short name T697
Test name
Test status
Simulation time 8393138349 ps
CPU time 7.73 seconds
Started Apr 15 03:16:12 PM PDT 24
Finished Apr 15 03:16:20 PM PDT 24
Peak memory 203996 kb
Host smart-bddeccba-72e0-4495-873f-fb8c65bcd293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41720
96042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.4172096042
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.873008076
Short name T825
Test name
Test status
Simulation time 8443692342 ps
CPU time 7.97 seconds
Started Apr 15 03:16:04 PM PDT 24
Finished Apr 15 03:16:13 PM PDT 24
Peak memory 203996 kb
Host smart-ba26c5f6-36bc-42cc-a823-9d622cedcfc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87300
8076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.873008076
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.3734983599
Short name T718
Test name
Test status
Simulation time 8382011906 ps
CPU time 7.77 seconds
Started Apr 15 03:16:06 PM PDT 24
Finished Apr 15 03:16:14 PM PDT 24
Peak memory 204032 kb
Host smart-63e92d63-8380-4d88-a72e-4e69da024b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37349
83599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.3734983599
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2982166704
Short name T408
Test name
Test status
Simulation time 8376243825 ps
CPU time 8.16 seconds
Started Apr 15 03:16:12 PM PDT 24
Finished Apr 15 03:16:20 PM PDT 24
Peak memory 204024 kb
Host smart-f87c0b7c-843f-4ab3-a8dd-1f5afa8d2545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29821
66704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2982166704
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.126393573
Short name T622
Test name
Test status
Simulation time 8382297789 ps
CPU time 7.76 seconds
Started Apr 15 03:16:06 PM PDT 24
Finished Apr 15 03:16:15 PM PDT 24
Peak memory 203976 kb
Host smart-711b7cd9-3694-440a-9cdd-ca5a7c7306e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12639
3573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.126393573
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.1445990848
Short name T840
Test name
Test status
Simulation time 8460811906 ps
CPU time 10.03 seconds
Started Apr 15 03:16:02 PM PDT 24
Finished Apr 15 03:16:12 PM PDT 24
Peak memory 204024 kb
Host smart-a3241baa-f6bd-45b9-9bac-ec0e29a1a590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14459
90848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.1445990848
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.800896144
Short name T552
Test name
Test status
Simulation time 8383048250 ps
CPU time 8.01 seconds
Started Apr 15 03:16:08 PM PDT 24
Finished Apr 15 03:16:17 PM PDT 24
Peak memory 204052 kb
Host smart-65abd42a-8bea-4fec-be52-864fe89a6246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80089
6144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.800896144
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.3584100192
Short name T1335
Test name
Test status
Simulation time 8398851136 ps
CPU time 8.18 seconds
Started Apr 15 03:16:07 PM PDT 24
Finished Apr 15 03:16:16 PM PDT 24
Peak memory 203992 kb
Host smart-09716be4-3879-4603-8507-cfda8e01b07d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35841
00192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.3584100192
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.3209267234
Short name T662
Test name
Test status
Simulation time 8466343221 ps
CPU time 10.27 seconds
Started Apr 15 03:16:23 PM PDT 24
Finished Apr 15 03:16:34 PM PDT 24
Peak memory 203932 kb
Host smart-54320b77-4129-4e0b-b564-578cdd8162fd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3209267234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.3209267234
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.2571936480
Short name T1016
Test name
Test status
Simulation time 8379299091 ps
CPU time 7.97 seconds
Started Apr 15 03:16:22 PM PDT 24
Finished Apr 15 03:16:30 PM PDT 24
Peak memory 203876 kb
Host smart-fb2e305c-cf6e-4021-b681-f3ee04364daf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2571936480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.2571936480
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.55103982
Short name T287
Test name
Test status
Simulation time 8466754637 ps
CPU time 8.16 seconds
Started Apr 15 03:16:19 PM PDT 24
Finished Apr 15 03:16:28 PM PDT 24
Peak memory 204028 kb
Host smart-7330bb3c-8cee-46c4-85b7-9ec91d1c6094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55103
982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.55103982
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.4244848354
Short name T824
Test name
Test status
Simulation time 8411406568 ps
CPU time 7.89 seconds
Started Apr 15 03:16:14 PM PDT 24
Finished Apr 15 03:16:23 PM PDT 24
Peak memory 204052 kb
Host smart-038eea9b-7afb-45df-ba73-e20c3a6d3949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42448
48354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.4244848354
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_enable.263713222
Short name T926
Test name
Test status
Simulation time 8376697235 ps
CPU time 8.31 seconds
Started Apr 15 03:16:16 PM PDT 24
Finished Apr 15 03:16:25 PM PDT 24
Peak memory 204052 kb
Host smart-405614fa-7a14-4e3d-8375-b7f7f902f450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26371
3222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.263713222
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.3788978349
Short name T316
Test name
Test status
Simulation time 85851341 ps
CPU time 1.73 seconds
Started Apr 15 03:16:14 PM PDT 24
Finished Apr 15 03:16:16 PM PDT 24
Peak memory 204092 kb
Host smart-833f2a95-30e1-483f-864a-d16f38ab39c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37889
78349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.3788978349
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.1834628810
Short name T345
Test name
Test status
Simulation time 8454346739 ps
CPU time 10.12 seconds
Started Apr 15 03:16:19 PM PDT 24
Finished Apr 15 03:16:29 PM PDT 24
Peak memory 204076 kb
Host smart-f3ab2993-2285-45ff-b470-77d679d83d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18346
28810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.1834628810
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.2574335321
Short name T181
Test name
Test status
Simulation time 8374138926 ps
CPU time 8.27 seconds
Started Apr 15 03:16:22 PM PDT 24
Finished Apr 15 03:16:31 PM PDT 24
Peak memory 204048 kb
Host smart-1ca92589-32df-40a7-8b53-e7d489851819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25743
35321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.2574335321
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.1810646514
Short name T121
Test name
Test status
Simulation time 8384565003 ps
CPU time 7.54 seconds
Started Apr 15 03:16:16 PM PDT 24
Finished Apr 15 03:16:24 PM PDT 24
Peak memory 204044 kb
Host smart-d4e0ca19-5ce7-4375-bf46-63c606d6969f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18106
46514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.1810646514
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.1156112004
Short name T527
Test name
Test status
Simulation time 8418383252 ps
CPU time 8.01 seconds
Started Apr 15 03:16:28 PM PDT 24
Finished Apr 15 03:16:37 PM PDT 24
Peak memory 204036 kb
Host smart-f4f9eca0-72f8-42a1-8c3f-2b608b5ecebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11561
12004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.1156112004
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2747750798
Short name T391
Test name
Test status
Simulation time 8369470704 ps
CPU time 9.62 seconds
Started Apr 15 03:16:13 PM PDT 24
Finished Apr 15 03:16:24 PM PDT 24
Peak memory 204080 kb
Host smart-fb19f2ce-eb14-41c7-8c42-46d0c3a75981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27477
50798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2747750798
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.863561386
Short name T91
Test name
Test status
Simulation time 8421919214 ps
CPU time 8.56 seconds
Started Apr 15 03:16:14 PM PDT 24
Finished Apr 15 03:16:23 PM PDT 24
Peak memory 204052 kb
Host smart-c597fa4c-384e-4f94-9c6a-4a49174db33c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86356
1386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.863561386
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.3567261343
Short name T772
Test name
Test status
Simulation time 8404767678 ps
CPU time 8.1 seconds
Started Apr 15 03:16:20 PM PDT 24
Finished Apr 15 03:16:28 PM PDT 24
Peak memory 204028 kb
Host smart-5e7d5b45-594b-4d7f-966c-3ac0ca6105a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35672
61343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.3567261343
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.2233788064
Short name T969
Test name
Test status
Simulation time 8416103433 ps
CPU time 7.92 seconds
Started Apr 15 03:16:22 PM PDT 24
Finished Apr 15 03:16:31 PM PDT 24
Peak memory 204048 kb
Host smart-5d4e8db3-1e63-4514-9e5c-1622428dcc14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22337
88064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.2233788064
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.528408159
Short name T170
Test name
Test status
Simulation time 8387679183 ps
CPU time 7.71 seconds
Started Apr 15 03:16:18 PM PDT 24
Finished Apr 15 03:16:27 PM PDT 24
Peak memory 204032 kb
Host smart-8bc4b2ef-4a5b-4f25-b5e8-c6efd7dc35dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52840
8159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.528408159
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.1700997
Short name T1290
Test name
Test status
Simulation time 8367592077 ps
CPU time 8.34 seconds
Started Apr 15 03:16:17 PM PDT 24
Finished Apr 15 03:16:26 PM PDT 24
Peak memory 204060 kb
Host smart-75782984-3766-4c64-ac8c-c01ea568fb0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17009
97 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.1700997
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.705300303
Short name T1300
Test name
Test status
Simulation time 63488981 ps
CPU time 0.69 seconds
Started Apr 15 03:16:17 PM PDT 24
Finished Apr 15 03:16:18 PM PDT 24
Peak memory 203920 kb
Host smart-b7d130f8-422e-4b90-b143-7873cd2e3665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70530
0303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.705300303
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.2370264567
Short name T1166
Test name
Test status
Simulation time 23059302703 ps
CPU time 42.36 seconds
Started Apr 15 03:16:17 PM PDT 24
Finished Apr 15 03:17:00 PM PDT 24
Peak memory 204308 kb
Host smart-614841f5-af79-4e9e-857f-b08c485afd37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23702
64567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.2370264567
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.2144999036
Short name T367
Test name
Test status
Simulation time 8433025280 ps
CPU time 7.91 seconds
Started Apr 15 03:16:19 PM PDT 24
Finished Apr 15 03:16:27 PM PDT 24
Peak memory 203928 kb
Host smart-6d2e2b0e-8ee2-461f-b40a-e7fbc7b9ea29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21449
99036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.2144999036
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.2689245665
Short name T397
Test name
Test status
Simulation time 8460308339 ps
CPU time 8.05 seconds
Started Apr 15 03:16:18 PM PDT 24
Finished Apr 15 03:16:27 PM PDT 24
Peak memory 204076 kb
Host smart-2e9ca7d8-30ff-420b-bd0d-ec530cf76845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26892
45665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.2689245665
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.57262187
Short name T1199
Test name
Test status
Simulation time 8395844519 ps
CPU time 8.1 seconds
Started Apr 15 03:16:17 PM PDT 24
Finished Apr 15 03:16:26 PM PDT 24
Peak memory 204064 kb
Host smart-d404cda8-a23c-4e88-ac1b-05f210dae491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57262
187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.57262187
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.1867516506
Short name T483
Test name
Test status
Simulation time 8397491410 ps
CPU time 8.55 seconds
Started Apr 15 03:16:18 PM PDT 24
Finished Apr 15 03:16:27 PM PDT 24
Peak memory 204016 kb
Host smart-998d811d-1872-47ff-9245-934ca20d3293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18675
16506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.1867516506
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.1582258992
Short name T1083
Test name
Test status
Simulation time 8420777249 ps
CPU time 7.92 seconds
Started Apr 15 03:16:20 PM PDT 24
Finished Apr 15 03:16:28 PM PDT 24
Peak memory 204028 kb
Host smart-e149b8d6-79b5-4d6b-b7d3-f0d25c509941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15822
58992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.1582258992
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1224180369
Short name T783
Test name
Test status
Simulation time 8459794776 ps
CPU time 8.5 seconds
Started Apr 15 03:16:13 PM PDT 24
Finished Apr 15 03:16:22 PM PDT 24
Peak memory 204068 kb
Host smart-348fbcb7-0a1a-4edb-a2e3-a18e376b00b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12241
80369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1224180369
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.4288272473
Short name T485
Test name
Test status
Simulation time 8401662483 ps
CPU time 7.39 seconds
Started Apr 15 03:16:18 PM PDT 24
Finished Apr 15 03:16:26 PM PDT 24
Peak memory 204044 kb
Host smart-a39a2a91-6cfe-4754-849f-bdf9f4d9dd1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42882
72473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.4288272473
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.120318229
Short name T700
Test name
Test status
Simulation time 8421385825 ps
CPU time 8.51 seconds
Started Apr 15 03:16:18 PM PDT 24
Finished Apr 15 03:16:27 PM PDT 24
Peak memory 204024 kb
Host smart-3104e670-a96f-4684-ba57-8b908478429b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12031
8229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.120318229
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.1355390545
Short name T1221
Test name
Test status
Simulation time 8458424903 ps
CPU time 8.31 seconds
Started Apr 15 03:11:38 PM PDT 24
Finished Apr 15 03:11:47 PM PDT 24
Peak memory 204068 kb
Host smart-d5271eb5-123d-4c62-8f51-58dc9c82210e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1355390545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.1355390545
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.460018416
Short name T834
Test name
Test status
Simulation time 8395389634 ps
CPU time 7.93 seconds
Started Apr 15 03:11:39 PM PDT 24
Finished Apr 15 03:11:47 PM PDT 24
Peak memory 204060 kb
Host smart-444428e8-5b02-4f77-b913-7c9de44d75c2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=460018416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.460018416
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.4217929701
Short name T464
Test name
Test status
Simulation time 8444256539 ps
CPU time 8.3 seconds
Started Apr 15 03:11:38 PM PDT 24
Finished Apr 15 03:11:47 PM PDT 24
Peak memory 203980 kb
Host smart-8b1e974e-6262-43fd-9510-98a0b15eeb63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42179
29701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.4217929701
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1618182485
Short name T659
Test name
Test status
Simulation time 8372431233 ps
CPU time 7.52 seconds
Started Apr 15 03:11:25 PM PDT 24
Finished Apr 15 03:11:33 PM PDT 24
Peak memory 204008 kb
Host smart-8335e9c8-c38a-49a9-8fbf-546c24c7e093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16181
82485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1618182485
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_enable.2283488011
Short name T568
Test name
Test status
Simulation time 8383866829 ps
CPU time 8.63 seconds
Started Apr 15 03:11:24 PM PDT 24
Finished Apr 15 03:11:33 PM PDT 24
Peak memory 204052 kb
Host smart-521f2623-ab4a-4ffe-abf1-ecbf461aa7c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22834
88011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.2283488011
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.2940223330
Short name T436
Test name
Test status
Simulation time 168243173 ps
CPU time 2.07 seconds
Started Apr 15 03:11:23 PM PDT 24
Finished Apr 15 03:11:26 PM PDT 24
Peak memory 204180 kb
Host smart-de52d29b-d6dd-4600-92d8-95cfdbe5d994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29402
23330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.2940223330
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1355088863
Short name T509
Test name
Test status
Simulation time 8484147039 ps
CPU time 7.68 seconds
Started Apr 15 03:11:35 PM PDT 24
Finished Apr 15 03:11:43 PM PDT 24
Peak memory 204036 kb
Host smart-5b21d315-125c-415e-ae1d-45c8af042cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13550
88863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1355088863
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.126866337
Short name T819
Test name
Test status
Simulation time 8367076877 ps
CPU time 7.87 seconds
Started Apr 15 03:11:37 PM PDT 24
Finished Apr 15 03:11:46 PM PDT 24
Peak memory 204020 kb
Host smart-d518cd99-6410-4788-be0c-1fc1d0b9c9fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12686
6337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.126866337
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1349852481
Short name T547
Test name
Test status
Simulation time 8424063805 ps
CPU time 7.84 seconds
Started Apr 15 03:11:24 PM PDT 24
Finished Apr 15 03:11:32 PM PDT 24
Peak memory 204000 kb
Host smart-e5dbdc3e-60a5-4a11-8807-b23a2922d0aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13498
52481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1349852481
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1206132866
Short name T380
Test name
Test status
Simulation time 8414958981 ps
CPU time 7.97 seconds
Started Apr 15 03:11:26 PM PDT 24
Finished Apr 15 03:11:35 PM PDT 24
Peak memory 204028 kb
Host smart-62508126-1d3a-492b-8bce-1c511388b81e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12061
32866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1206132866
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2520043041
Short name T906
Test name
Test status
Simulation time 8390521105 ps
CPU time 8.03 seconds
Started Apr 15 03:11:24 PM PDT 24
Finished Apr 15 03:11:32 PM PDT 24
Peak memory 204068 kb
Host smart-09b962f5-c345-48af-98e4-8d40ba4c201a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25200
43041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2520043041
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.3409326980
Short name T1118
Test name
Test status
Simulation time 8403593540 ps
CPU time 7.84 seconds
Started Apr 15 03:11:24 PM PDT 24
Finished Apr 15 03:11:33 PM PDT 24
Peak memory 203984 kb
Host smart-233e410b-f953-49b5-b33d-f393244fc990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34093
26980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.3409326980
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.2144009804
Short name T602
Test name
Test status
Simulation time 8430015149 ps
CPU time 7.57 seconds
Started Apr 15 03:11:27 PM PDT 24
Finished Apr 15 03:11:35 PM PDT 24
Peak memory 204024 kb
Host smart-59bacb72-8b28-4311-800a-f7063b19da18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21440
09804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.2144009804
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.1791629119
Short name T319
Test name
Test status
Simulation time 8385803719 ps
CPU time 8.03 seconds
Started Apr 15 03:11:33 PM PDT 24
Finished Apr 15 03:11:42 PM PDT 24
Peak memory 204024 kb
Host smart-10648af8-d031-4075-89c3-9b1505dcab5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17916
29119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.1791629119
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.1238882541
Short name T157
Test name
Test status
Simulation time 8457186040 ps
CPU time 8.68 seconds
Started Apr 15 03:11:33 PM PDT 24
Finished Apr 15 03:11:42 PM PDT 24
Peak memory 204080 kb
Host smart-3ccd5493-1399-4055-85e6-4f072efd5d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12388
82541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.1238882541
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2831852141
Short name T1269
Test name
Test status
Simulation time 8452286600 ps
CPU time 9.08 seconds
Started Apr 15 03:11:36 PM PDT 24
Finished Apr 15 03:11:46 PM PDT 24
Peak memory 204056 kb
Host smart-6b4fa58b-9212-4b6e-9a6a-46a944d5a5de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28318
52141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2831852141
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2062909062
Short name T880
Test name
Test status
Simulation time 51753439 ps
CPU time 0.66 seconds
Started Apr 15 03:11:39 PM PDT 24
Finished Apr 15 03:11:40 PM PDT 24
Peak memory 203924 kb
Host smart-c38c32a4-8ba4-48b9-89e3-b06ddcb05890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20629
09062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2062909062
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.1042942631
Short name T228
Test name
Test status
Simulation time 15113136935 ps
CPU time 30.14 seconds
Started Apr 15 03:11:30 PM PDT 24
Finished Apr 15 03:12:01 PM PDT 24
Peak memory 204312 kb
Host smart-b2f1f47c-b332-4a02-84f5-7e1089d60a7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10429
42631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.1042942631
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.2886938165
Short name T623
Test name
Test status
Simulation time 8392913901 ps
CPU time 7.59 seconds
Started Apr 15 03:11:37 PM PDT 24
Finished Apr 15 03:11:45 PM PDT 24
Peak memory 203940 kb
Host smart-6d89ecd9-fea8-46d5-988a-81e681db2419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28869
38165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.2886938165
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2764146793
Short name T1075
Test name
Test status
Simulation time 8406910568 ps
CPU time 9.26 seconds
Started Apr 15 03:11:30 PM PDT 24
Finished Apr 15 03:11:39 PM PDT 24
Peak memory 204032 kb
Host smart-1e205269-abf5-48f5-83f6-c490a977611e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27641
46793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2764146793
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.2560958979
Short name T1022
Test name
Test status
Simulation time 8438993490 ps
CPU time 8.14 seconds
Started Apr 15 03:11:30 PM PDT 24
Finished Apr 15 03:11:39 PM PDT 24
Peak memory 204052 kb
Host smart-29215472-0a5f-4eab-91d0-5641480757b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25609
58979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.2560958979
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2708402643
Short name T58
Test name
Test status
Simulation time 163812831 ps
CPU time 0.99 seconds
Started Apr 15 03:11:41 PM PDT 24
Finished Apr 15 03:11:42 PM PDT 24
Peak memory 220132 kb
Host smart-f65c6b82-b06f-4333-a6e6-578cd973e373
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2708402643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2708402643
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.2387866531
Short name T48
Test name
Test status
Simulation time 8392088343 ps
CPU time 8.31 seconds
Started Apr 15 03:11:35 PM PDT 24
Finished Apr 15 03:11:43 PM PDT 24
Peak memory 204044 kb
Host smart-bb9c330a-eb6e-447c-9795-1268948869d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23878
66531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.2387866531
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2134595188
Short name T340
Test name
Test status
Simulation time 8374744772 ps
CPU time 8.28 seconds
Started Apr 15 03:11:30 PM PDT 24
Finished Apr 15 03:11:38 PM PDT 24
Peak memory 203968 kb
Host smart-7498cefc-d4ce-49ae-af5c-51f938bc3cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21345
95188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2134595188
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.809128567
Short name T118
Test name
Test status
Simulation time 8437859359 ps
CPU time 9.48 seconds
Started Apr 15 03:11:19 PM PDT 24
Finished Apr 15 03:11:29 PM PDT 24
Peak memory 204076 kb
Host smart-62e44a39-739b-4428-9e54-e72bf26da0ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80912
8567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.809128567
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.3050239393
Short name T295
Test name
Test status
Simulation time 8384749465 ps
CPU time 8.07 seconds
Started Apr 15 03:11:31 PM PDT 24
Finished Apr 15 03:11:39 PM PDT 24
Peak memory 204020 kb
Host smart-ce3ccdf8-5f3a-41dd-84be-2986f9618e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30502
39393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.3050239393
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.2335276204
Short name T1212
Test name
Test status
Simulation time 8388224079 ps
CPU time 8.69 seconds
Started Apr 15 03:11:30 PM PDT 24
Finished Apr 15 03:11:39 PM PDT 24
Peak memory 204068 kb
Host smart-3a90930b-a8da-41de-b9b9-1c01cc87c283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23352
76204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.2335276204
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.1651502550
Short name T619
Test name
Test status
Simulation time 8474115487 ps
CPU time 7.9 seconds
Started Apr 15 03:16:29 PM PDT 24
Finished Apr 15 03:16:38 PM PDT 24
Peak memory 204056 kb
Host smart-7f688f6d-e000-4f26-8e87-c8d408293b51
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1651502550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.1651502550
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.1060228166
Short name T413
Test name
Test status
Simulation time 8382534470 ps
CPU time 7.82 seconds
Started Apr 15 03:16:26 PM PDT 24
Finished Apr 15 03:16:34 PM PDT 24
Peak memory 204076 kb
Host smart-f0cfb799-97a2-465c-bf86-bfae6ce1dfd0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1060228166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.1060228166
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.331064974
Short name T1066
Test name
Test status
Simulation time 8457501088 ps
CPU time 8.65 seconds
Started Apr 15 03:16:25 PM PDT 24
Finished Apr 15 03:16:35 PM PDT 24
Peak memory 204036 kb
Host smart-b2fe6497-e740-4b8b-b5ca-98b835c7bbe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33106
4974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.331064974
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.869326355
Short name T617
Test name
Test status
Simulation time 8374845007 ps
CPU time 8.09 seconds
Started Apr 15 03:16:21 PM PDT 24
Finished Apr 15 03:16:30 PM PDT 24
Peak memory 204008 kb
Host smart-e0e26bcb-fe84-464c-bb4d-1e187d925e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86932
6355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.869326355
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_enable.754970989
Short name T374
Test name
Test status
Simulation time 8389578642 ps
CPU time 8.08 seconds
Started Apr 15 03:16:24 PM PDT 24
Finished Apr 15 03:16:32 PM PDT 24
Peak memory 204060 kb
Host smart-fbce6d00-88fc-4420-9b7e-2f6553e1dbf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75497
0989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.754970989
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.1485498671
Short name T1120
Test name
Test status
Simulation time 46282911 ps
CPU time 1.11 seconds
Started Apr 15 03:16:26 PM PDT 24
Finished Apr 15 03:16:28 PM PDT 24
Peak memory 204176 kb
Host smart-e03fa0d9-72c5-4449-a7ae-29f871dd5479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14854
98671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.1485498671
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.3010770907
Short name T50
Test name
Test status
Simulation time 8422033223 ps
CPU time 7.91 seconds
Started Apr 15 03:16:25 PM PDT 24
Finished Apr 15 03:16:34 PM PDT 24
Peak memory 204020 kb
Host smart-d32a5c0c-6112-4a23-b6f1-ce232f8988eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30107
70907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.3010770907
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.11721125
Short name T169
Test name
Test status
Simulation time 8368330726 ps
CPU time 9.02 seconds
Started Apr 15 03:16:27 PM PDT 24
Finished Apr 15 03:16:36 PM PDT 24
Peak memory 204056 kb
Host smart-61b06882-d07a-4921-a050-f43b81c5c055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11721
125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.11721125
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.210962981
Short name T1253
Test name
Test status
Simulation time 8394438613 ps
CPU time 7.95 seconds
Started Apr 15 03:16:20 PM PDT 24
Finished Apr 15 03:16:28 PM PDT 24
Peak memory 204048 kb
Host smart-2ff5c8f7-df03-48a6-b467-d0a6911aaa61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21096
2981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.210962981
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.473318160
Short name T611
Test name
Test status
Simulation time 8421529971 ps
CPU time 10.72 seconds
Started Apr 15 03:16:20 PM PDT 24
Finished Apr 15 03:16:31 PM PDT 24
Peak memory 204004 kb
Host smart-a91f3095-641a-4087-ac12-1c10dacdff08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47331
8160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.473318160
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.2796322014
Short name T1319
Test name
Test status
Simulation time 8441302798 ps
CPU time 8.45 seconds
Started Apr 15 03:16:24 PM PDT 24
Finished Apr 15 03:16:33 PM PDT 24
Peak memory 204036 kb
Host smart-5258c9cc-7b1f-4f45-8239-a3597a9838fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27963
22014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.2796322014
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.1408367660
Short name T1138
Test name
Test status
Simulation time 8391713075 ps
CPU time 8.07 seconds
Started Apr 15 03:16:26 PM PDT 24
Finished Apr 15 03:16:35 PM PDT 24
Peak memory 204056 kb
Host smart-12fd9229-366b-4a4a-af46-bf84231bd266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14083
67660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.1408367660
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.4230541697
Short name T486
Test name
Test status
Simulation time 8409427015 ps
CPU time 7.69 seconds
Started Apr 15 03:16:24 PM PDT 24
Finished Apr 15 03:16:33 PM PDT 24
Peak memory 204036 kb
Host smart-c944e4c1-eb5e-4c5c-95c7-cd40be0ffcf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42305
41697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.4230541697
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.3009697030
Short name T1109
Test name
Test status
Simulation time 8386467353 ps
CPU time 8.38 seconds
Started Apr 15 03:16:25 PM PDT 24
Finished Apr 15 03:16:34 PM PDT 24
Peak memory 203980 kb
Host smart-f5dff282-b644-43fc-891e-2b0d6da999e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30096
97030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.3009697030
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.3395829906
Short name T294
Test name
Test status
Simulation time 8400277502 ps
CPU time 7.92 seconds
Started Apr 15 03:16:26 PM PDT 24
Finished Apr 15 03:16:34 PM PDT 24
Peak memory 204028 kb
Host smart-0635ef2d-00f4-4ec7-b5d5-222a2c8b311a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33958
29906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.3395829906
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2224056
Short name T41
Test name
Test status
Simulation time 37992030 ps
CPU time 0.62 seconds
Started Apr 15 03:16:25 PM PDT 24
Finished Apr 15 03:16:26 PM PDT 24
Peak memory 203940 kb
Host smart-e890bdb0-8eef-404f-b2ba-2232f5e9dfa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22240
56 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2224056
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.1339670365
Short name T83
Test name
Test status
Simulation time 20801061600 ps
CPU time 44.31 seconds
Started Apr 15 03:16:20 PM PDT 24
Finished Apr 15 03:17:05 PM PDT 24
Peak memory 204320 kb
Host smart-09232671-1f07-42ea-b592-ea2e02e6074d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13396
70365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.1339670365
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.2330256477
Short name T1144
Test name
Test status
Simulation time 8406410592 ps
CPU time 9.35 seconds
Started Apr 15 03:16:24 PM PDT 24
Finished Apr 15 03:16:33 PM PDT 24
Peak memory 204024 kb
Host smart-6c40bab2-89b4-4d7e-beae-47ba6ecffc96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23302
56477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.2330256477
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.2170372303
Short name T132
Test name
Test status
Simulation time 8450120109 ps
CPU time 8.52 seconds
Started Apr 15 03:16:25 PM PDT 24
Finished Apr 15 03:16:35 PM PDT 24
Peak memory 204008 kb
Host smart-69c59ab3-9b6e-4ebc-bef4-3d98ed4ea7b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21703
72303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.2170372303
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.2093002496
Short name T680
Test name
Test status
Simulation time 8413319575 ps
CPU time 7.63 seconds
Started Apr 15 03:16:25 PM PDT 24
Finished Apr 15 03:16:33 PM PDT 24
Peak memory 204056 kb
Host smart-6a64dcdf-eabd-4808-9d34-527195f3d428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20930
02496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.2093002496
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.4203364018
Short name T643
Test name
Test status
Simulation time 8391025132 ps
CPU time 9.52 seconds
Started Apr 15 03:16:29 PM PDT 24
Finished Apr 15 03:16:39 PM PDT 24
Peak memory 204060 kb
Host smart-49a65cd1-2ca6-4669-b580-806ec54f8bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42033
64018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.4203364018
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.619830694
Short name T474
Test name
Test status
Simulation time 8371349115 ps
CPU time 7.97 seconds
Started Apr 15 03:16:27 PM PDT 24
Finished Apr 15 03:16:36 PM PDT 24
Peak memory 204064 kb
Host smart-adbda844-2907-4b66-97ff-c2443c5804e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61983
0694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.619830694
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.423629906
Short name T935
Test name
Test status
Simulation time 8435329150 ps
CPU time 9.14 seconds
Started Apr 15 03:16:23 PM PDT 24
Finished Apr 15 03:16:33 PM PDT 24
Peak memory 204052 kb
Host smart-3d6250da-3cf1-48bd-9132-dd3b4fb5eae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42362
9906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.423629906
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.4272255582
Short name T473
Test name
Test status
Simulation time 8406469803 ps
CPU time 8.38 seconds
Started Apr 15 03:16:26 PM PDT 24
Finished Apr 15 03:16:35 PM PDT 24
Peak memory 204024 kb
Host smart-095574ae-1e7a-4771-b049-7edeae568048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42722
55582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.4272255582
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.2628214
Short name T883
Test name
Test status
Simulation time 8401381886 ps
CPU time 8.14 seconds
Started Apr 15 03:16:29 PM PDT 24
Finished Apr 15 03:16:38 PM PDT 24
Peak memory 204060 kb
Host smart-ff43a5f1-cea4-4cce-9e87-527b369382e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26282
14 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.2628214
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.1493750507
Short name T489
Test name
Test status
Simulation time 8485322424 ps
CPU time 8.18 seconds
Started Apr 15 03:16:37 PM PDT 24
Finished Apr 15 03:16:45 PM PDT 24
Peak memory 204020 kb
Host smart-876eb720-fabd-479d-a170-f3b91d17e389
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1493750507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.1493750507
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.min_length_in_transaction.2731174425
Short name T1001
Test name
Test status
Simulation time 8382569865 ps
CPU time 10.06 seconds
Started Apr 15 03:16:38 PM PDT 24
Finished Apr 15 03:16:50 PM PDT 24
Peak memory 204004 kb
Host smart-1d4b3849-7d4c-4da6-94ec-add3e2d9e88a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2731174425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.2731174425
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.3450630853
Short name T1154
Test name
Test status
Simulation time 8391661862 ps
CPU time 8.28 seconds
Started Apr 15 03:16:38 PM PDT 24
Finished Apr 15 03:16:48 PM PDT 24
Peak memory 204048 kb
Host smart-57e9a6cb-7929-4923-8d59-be09ec9a36aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34506
30853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.3450630853
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.2011900334
Short name T399
Test name
Test status
Simulation time 8381741521 ps
CPU time 7.87 seconds
Started Apr 15 03:16:29 PM PDT 24
Finished Apr 15 03:16:37 PM PDT 24
Peak memory 203988 kb
Host smart-57eb0afc-69d3-4a10-9b2a-3f2730ddd9ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20119
00334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.2011900334
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_enable.2482817054
Short name T225
Test name
Test status
Simulation time 8388640803 ps
CPU time 9.77 seconds
Started Apr 15 03:16:32 PM PDT 24
Finished Apr 15 03:16:42 PM PDT 24
Peak memory 203968 kb
Host smart-04b8730c-b3aa-4ced-858d-79fffd446e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24828
17054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.2482817054
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.3442415556
Short name T1277
Test name
Test status
Simulation time 109276128 ps
CPU time 1.34 seconds
Started Apr 15 03:16:53 PM PDT 24
Finished Apr 15 03:16:56 PM PDT 24
Peak memory 204112 kb
Host smart-eaccadea-3200-4319-a487-45d466522fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34424
15556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.3442415556
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.436265957
Short name T1193
Test name
Test status
Simulation time 8403269494 ps
CPU time 7.64 seconds
Started Apr 15 03:16:40 PM PDT 24
Finished Apr 15 03:16:48 PM PDT 24
Peak memory 204004 kb
Host smart-dbc2dca5-27a2-4352-9f51-13d16ff779e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43626
5957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.436265957
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.3902690925
Short name T897
Test name
Test status
Simulation time 8384137494 ps
CPU time 7.76 seconds
Started Apr 15 03:16:36 PM PDT 24
Finished Apr 15 03:16:44 PM PDT 24
Peak memory 204064 kb
Host smart-eeead68f-25ad-4156-be0f-3e32ae484788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39026
90925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.3902690925
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.4242756884
Short name T450
Test name
Test status
Simulation time 8419826502 ps
CPU time 9.61 seconds
Started Apr 15 03:16:30 PM PDT 24
Finished Apr 15 03:16:40 PM PDT 24
Peak memory 204028 kb
Host smart-73270dfd-2c12-4cff-9142-190ad336d00f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42427
56884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.4242756884
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.1272847744
Short name T863
Test name
Test status
Simulation time 8419409125 ps
CPU time 10.41 seconds
Started Apr 15 03:16:30 PM PDT 24
Finished Apr 15 03:16:41 PM PDT 24
Peak memory 204064 kb
Host smart-350ff75f-0731-46d6-82f8-c4fea60c7fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12728
47744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.1272847744
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1110238169
Short name T1087
Test name
Test status
Simulation time 8373321460 ps
CPU time 8.28 seconds
Started Apr 15 03:16:30 PM PDT 24
Finished Apr 15 03:16:38 PM PDT 24
Peak memory 204052 kb
Host smart-07717864-a8aa-4132-acff-2819b3d027ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11102
38169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1110238169
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2080322503
Short name T744
Test name
Test status
Simulation time 8429794497 ps
CPU time 9.99 seconds
Started Apr 15 03:16:32 PM PDT 24
Finished Apr 15 03:16:42 PM PDT 24
Peak memory 204060 kb
Host smart-95b634ca-5537-4899-aa60-908766711337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20803
22503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2080322503
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.1324866355
Short name T558
Test name
Test status
Simulation time 8398089554 ps
CPU time 9.32 seconds
Started Apr 15 03:16:31 PM PDT 24
Finished Apr 15 03:16:40 PM PDT 24
Peak memory 204000 kb
Host smart-0650d6c2-ec7f-4f32-83b1-a8f5128da500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13248
66355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1324866355
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.2784486156
Short name T320
Test name
Test status
Simulation time 8401578909 ps
CPU time 10.43 seconds
Started Apr 15 03:16:31 PM PDT 24
Finished Apr 15 03:16:42 PM PDT 24
Peak memory 203988 kb
Host smart-5cbdc568-1244-4620-9ad8-663ffdf0710c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27844
86156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.2784486156
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.2086814737
Short name T26
Test name
Test status
Simulation time 8393527592 ps
CPU time 9.52 seconds
Started Apr 15 03:16:38 PM PDT 24
Finished Apr 15 03:16:49 PM PDT 24
Peak memory 204052 kb
Host smart-7a7e216d-b341-4d66-91d9-9c5464321380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20868
14737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.2086814737
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.2066337495
Short name T977
Test name
Test status
Simulation time 8368995707 ps
CPU time 7.77 seconds
Started Apr 15 03:16:37 PM PDT 24
Finished Apr 15 03:16:45 PM PDT 24
Peak memory 204016 kb
Host smart-3c6ce920-c1b5-4b10-9244-420376cf034c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20663
37495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.2066337495
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.3367238441
Short name T33
Test name
Test status
Simulation time 45565868 ps
CPU time 0.72 seconds
Started Apr 15 03:16:34 PM PDT 24
Finished Apr 15 03:16:35 PM PDT 24
Peak memory 204080 kb
Host smart-bb4d7c78-f871-4e59-b9c0-e96e95dad216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33672
38441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.3367238441
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.4072919804
Short name T205
Test name
Test status
Simulation time 14081550001 ps
CPU time 22.72 seconds
Started Apr 15 03:16:31 PM PDT 24
Finished Apr 15 03:16:54 PM PDT 24
Peak memory 204264 kb
Host smart-5355aeb2-52e7-4345-a22f-9e5aa9f0c10e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40729
19804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.4072919804
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.40805208
Short name T1037
Test name
Test status
Simulation time 8377128631 ps
CPU time 8.55 seconds
Started Apr 15 03:16:40 PM PDT 24
Finished Apr 15 03:16:50 PM PDT 24
Peak memory 204024 kb
Host smart-2c4daa69-fc7e-41f5-a99e-ab04bc08e2eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40805
208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.40805208
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.1438372085
Short name T135
Test name
Test status
Simulation time 8377406429 ps
CPU time 8.44 seconds
Started Apr 15 03:16:34 PM PDT 24
Finished Apr 15 03:16:43 PM PDT 24
Peak memory 203976 kb
Host smart-ad26a086-93ee-4a0d-a695-9c7dc85cc142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14383
72085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1438372085
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.3829290709
Short name T888
Test name
Test status
Simulation time 8384069735 ps
CPU time 8.51 seconds
Started Apr 15 03:16:35 PM PDT 24
Finished Apr 15 03:16:44 PM PDT 24
Peak memory 204056 kb
Host smart-96895a2e-8ee5-4076-adf9-ffd2c81afdc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38292
90709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.3829290709
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.3606636765
Short name T1374
Test name
Test status
Simulation time 8377430348 ps
CPU time 8.33 seconds
Started Apr 15 03:16:34 PM PDT 24
Finished Apr 15 03:16:42 PM PDT 24
Peak memory 204032 kb
Host smart-f6631330-b0b9-459b-8245-5fe46a6bcaf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36066
36765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.3606636765
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3210834633
Short name T654
Test name
Test status
Simulation time 8383361939 ps
CPU time 9.92 seconds
Started Apr 15 03:16:35 PM PDT 24
Finished Apr 15 03:16:45 PM PDT 24
Peak memory 204004 kb
Host smart-29800cf8-ece3-45ab-bfce-80a54cdac788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32108
34633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3210834633
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.2585633912
Short name T136
Test name
Test status
Simulation time 8471662391 ps
CPU time 9.95 seconds
Started Apr 15 03:16:26 PM PDT 24
Finished Apr 15 03:16:36 PM PDT 24
Peak memory 203996 kb
Host smart-ec64a796-0829-4978-b6b5-061bbfd1ff95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25856
33912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2585633912
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.1645676216
Short name T221
Test name
Test status
Simulation time 8382839456 ps
CPU time 8.17 seconds
Started Apr 15 03:16:34 PM PDT 24
Finished Apr 15 03:16:43 PM PDT 24
Peak memory 203976 kb
Host smart-15d4c77b-16a9-4fe9-bb04-60ba011ab04c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16456
76216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.1645676216
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.3037165039
Short name T844
Test name
Test status
Simulation time 8404166629 ps
CPU time 7.59 seconds
Started Apr 15 03:16:37 PM PDT 24
Finished Apr 15 03:16:45 PM PDT 24
Peak memory 204020 kb
Host smart-163ad6c3-d162-4dca-a08b-bdbc1f5831b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30371
65039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.3037165039
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.max_length_in_transaction.3581073870
Short name T1341
Test name
Test status
Simulation time 8461343919 ps
CPU time 8.78 seconds
Started Apr 15 03:16:43 PM PDT 24
Finished Apr 15 03:16:53 PM PDT 24
Peak memory 204056 kb
Host smart-74f5a7ef-6b2b-45f7-b54a-580d21424678
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3581073870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.3581073870
Directory /workspace/32.max_length_in_transaction/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.1289619215
Short name T946
Test name
Test status
Simulation time 8395684786 ps
CPU time 8.43 seconds
Started Apr 15 03:16:43 PM PDT 24
Finished Apr 15 03:16:53 PM PDT 24
Peak memory 204056 kb
Host smart-88db38ed-bc4b-48c0-884c-9ccaaa3c5120
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1289619215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.1289619215
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.random_length_in_trans.282641373
Short name T687
Test name
Test status
Simulation time 8405077364 ps
CPU time 8.2 seconds
Started Apr 15 03:16:40 PM PDT 24
Finished Apr 15 03:16:50 PM PDT 24
Peak memory 204000 kb
Host smart-009b290b-bd86-4944-8be1-bfd42a1cc02b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28264
1373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.282641373
Directory /workspace/32.random_length_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2348626269
Short name T1165
Test name
Test status
Simulation time 8379259010 ps
CPU time 9.61 seconds
Started Apr 15 03:16:38 PM PDT 24
Finished Apr 15 03:16:48 PM PDT 24
Peak memory 204016 kb
Host smart-fedd003b-13e7-4fa0-957c-c2a560cc0192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23486
26269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2348626269
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_enable.767131081
Short name T1009
Test name
Test status
Simulation time 8419390407 ps
CPU time 8.03 seconds
Started Apr 15 03:16:38 PM PDT 24
Finished Apr 15 03:16:48 PM PDT 24
Peak memory 204060 kb
Host smart-1ff829ca-42c3-4150-aad7-12787254be65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76713
1081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.767131081
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.2225751161
Short name T965
Test name
Test status
Simulation time 8475121641 ps
CPU time 8.19 seconds
Started Apr 15 03:16:43 PM PDT 24
Finished Apr 15 03:16:52 PM PDT 24
Peak memory 203968 kb
Host smart-08d74996-0fc0-477d-bc12-d772a875a321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22257
51161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.2225751161
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.32588260
Short name T176
Test name
Test status
Simulation time 8404172898 ps
CPU time 8.52 seconds
Started Apr 15 03:16:44 PM PDT 24
Finished Apr 15 03:16:54 PM PDT 24
Peak memory 204056 kb
Host smart-2bbde972-9ef2-4133-b1a1-6332f1cfbcb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32588
260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.32588260
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.2855265679
Short name T141
Test name
Test status
Simulation time 8412937997 ps
CPU time 7.94 seconds
Started Apr 15 03:16:38 PM PDT 24
Finished Apr 15 03:16:47 PM PDT 24
Peak memory 204052 kb
Host smart-13351c48-2a66-49b3-bf79-56e74a2e1a7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28552
65679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2855265679
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1981432371
Short name T1129
Test name
Test status
Simulation time 8417094195 ps
CPU time 8.08 seconds
Started Apr 15 03:16:38 PM PDT 24
Finished Apr 15 03:16:48 PM PDT 24
Peak memory 203884 kb
Host smart-80191234-80d3-4409-9f8f-633ad8f3af84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19814
32371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1981432371
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.2285541939
Short name T803
Test name
Test status
Simulation time 8379490333 ps
CPU time 8.58 seconds
Started Apr 15 03:16:41 PM PDT 24
Finished Apr 15 03:16:50 PM PDT 24
Peak memory 204012 kb
Host smart-d3125949-e61c-4b85-91d7-e2ba551cb45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22855
41939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.2285541939
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.1541059577
Short name T109
Test name
Test status
Simulation time 8477793974 ps
CPU time 9.49 seconds
Started Apr 15 03:16:41 PM PDT 24
Finished Apr 15 03:16:52 PM PDT 24
Peak memory 204008 kb
Host smart-3d35773f-bf1f-4840-a6a5-413c73706f8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15410
59577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.1541059577
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.2466380342
Short name T932
Test name
Test status
Simulation time 8406528284 ps
CPU time 8.05 seconds
Started Apr 15 03:16:40 PM PDT 24
Finished Apr 15 03:16:49 PM PDT 24
Peak memory 203992 kb
Host smart-fd7e60db-dacc-448e-ae1d-36e64d655518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24663
80342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.2466380342
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.699365380
Short name T569
Test name
Test status
Simulation time 8456791647 ps
CPU time 7.82 seconds
Started Apr 15 03:16:43 PM PDT 24
Finished Apr 15 03:16:51 PM PDT 24
Peak memory 204064 kb
Host smart-55b2c4f6-1fdb-4c79-8846-6ba84335c7ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69936
5380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.699365380
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.450355509
Short name T1369
Test name
Test status
Simulation time 8505216850 ps
CPU time 8.04 seconds
Started Apr 15 03:16:44 PM PDT 24
Finished Apr 15 03:16:53 PM PDT 24
Peak memory 204208 kb
Host smart-b98e5004-d3a7-423d-baa9-0a52a926f29d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45035
5509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.450355509
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.556929456
Short name T862
Test name
Test status
Simulation time 8410666376 ps
CPU time 7.41 seconds
Started Apr 15 03:16:42 PM PDT 24
Finished Apr 15 03:16:50 PM PDT 24
Peak memory 204052 kb
Host smart-eff1d36d-d3aa-4c4a-92be-036c63bd106f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55692
9456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.556929456
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.1734653086
Short name T229
Test name
Test status
Simulation time 17893044757 ps
CPU time 36.32 seconds
Started Apr 15 03:16:47 PM PDT 24
Finished Apr 15 03:17:24 PM PDT 24
Peak memory 204344 kb
Host smart-ebda4854-6047-416f-a724-ef55603d4e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17346
53086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1734653086
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.3871056087
Short name T896
Test name
Test status
Simulation time 8370345507 ps
CPU time 8.61 seconds
Started Apr 15 03:16:45 PM PDT 24
Finished Apr 15 03:16:54 PM PDT 24
Peak memory 204060 kb
Host smart-043c0aaf-902c-4bba-9120-30b2c0f0d1fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38710
56087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3871056087
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.1547335015
Short name T1271
Test name
Test status
Simulation time 8462442222 ps
CPU time 8.41 seconds
Started Apr 15 03:16:44 PM PDT 24
Finished Apr 15 03:16:54 PM PDT 24
Peak memory 204060 kb
Host smart-09dc1c6d-c06a-4f43-ab8c-2a801acdaf78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15473
35015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.1547335015
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.1603706049
Short name T624
Test name
Test status
Simulation time 8413124713 ps
CPU time 8.43 seconds
Started Apr 15 03:16:41 PM PDT 24
Finished Apr 15 03:16:50 PM PDT 24
Peak memory 204076 kb
Host smart-33648c9b-da46-43cc-a58e-b52511a53f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16037
06049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.1603706049
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.1638490819
Short name T49
Test name
Test status
Simulation time 8375057772 ps
CPU time 8.66 seconds
Started Apr 15 03:16:42 PM PDT 24
Finished Apr 15 03:16:51 PM PDT 24
Peak memory 204044 kb
Host smart-40f74c77-d450-489e-bdec-2e666a5494a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16384
90819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.1638490819
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.522126329
Short name T27
Test name
Test status
Simulation time 8374768880 ps
CPU time 8.6 seconds
Started Apr 15 03:16:41 PM PDT 24
Finished Apr 15 03:16:51 PM PDT 24
Peak memory 204040 kb
Host smart-2bd2bff9-2ef0-4da1-a184-6bf92679ed42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52212
6329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.522126329
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2746580951
Short name T904
Test name
Test status
Simulation time 8466147838 ps
CPU time 9.39 seconds
Started Apr 15 03:16:38 PM PDT 24
Finished Apr 15 03:16:49 PM PDT 24
Peak memory 204048 kb
Host smart-1e8ae285-746e-4323-86b7-cd19919aa433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27465
80951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2746580951
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.3543037811
Short name T1281
Test name
Test status
Simulation time 8391618869 ps
CPU time 10.06 seconds
Started Apr 15 03:16:42 PM PDT 24
Finished Apr 15 03:16:53 PM PDT 24
Peak memory 203928 kb
Host smart-c6bd4aab-45e5-48f3-930d-fb49564e0460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35430
37811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.3543037811
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.3053382436
Short name T518
Test name
Test status
Simulation time 8383124931 ps
CPU time 8.32 seconds
Started Apr 15 03:16:46 PM PDT 24
Finished Apr 15 03:16:55 PM PDT 24
Peak memory 204028 kb
Host smart-ac39ebe1-df43-4ccd-ad7f-ae90776d4db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30533
82436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.3053382436
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.15732114
Short name T681
Test name
Test status
Simulation time 8465659808 ps
CPU time 8.2 seconds
Started Apr 15 03:17:00 PM PDT 24
Finished Apr 15 03:17:09 PM PDT 24
Peak memory 204048 kb
Host smart-f3da7605-bd5b-4f61-9118-7fae8ee2be90
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=15732114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.15732114
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.3574164170
Short name T889
Test name
Test status
Simulation time 8378886219 ps
CPU time 8.03 seconds
Started Apr 15 03:16:50 PM PDT 24
Finished Apr 15 03:16:58 PM PDT 24
Peak memory 204052 kb
Host smart-516cfed4-827c-4e37-9e16-dd4c15fc12a2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3574164170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.3574164170
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.515079412
Short name T276
Test name
Test status
Simulation time 8466608485 ps
CPU time 8.13 seconds
Started Apr 15 03:16:51 PM PDT 24
Finished Apr 15 03:16:59 PM PDT 24
Peak memory 204044 kb
Host smart-35380a50-814a-42b5-8d6d-1a6d18a95c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51507
9412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.515079412
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.1580623224
Short name T905
Test name
Test status
Simulation time 8434068366 ps
CPU time 8.52 seconds
Started Apr 15 03:16:48 PM PDT 24
Finished Apr 15 03:16:57 PM PDT 24
Peak memory 204072 kb
Host smart-c3cf5e10-95e6-44b4-8647-bac02fd377a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15806
23224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1580623224
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_enable.1181158446
Short name T444
Test name
Test status
Simulation time 8380403364 ps
CPU time 7.99 seconds
Started Apr 15 03:16:53 PM PDT 24
Finished Apr 15 03:17:02 PM PDT 24
Peak memory 204044 kb
Host smart-92097cc6-5dc9-428f-b8f0-5ae67dd297b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11811
58446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1181158446
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.4089017532
Short name T841
Test name
Test status
Simulation time 331661874 ps
CPU time 2.15 seconds
Started Apr 15 03:16:53 PM PDT 24
Finished Apr 15 03:16:56 PM PDT 24
Peak memory 204172 kb
Host smart-16a12b60-9451-4224-9f1a-4de15926b3f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40890
17532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.4089017532
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.3745988968
Short name T484
Test name
Test status
Simulation time 8406481469 ps
CPU time 8.18 seconds
Started Apr 15 03:16:51 PM PDT 24
Finished Apr 15 03:17:00 PM PDT 24
Peak memory 204024 kb
Host smart-923b2c98-caae-472a-a2bf-1f5d0d3d8f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37459
88968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.3745988968
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.3530097708
Short name T1254
Test name
Test status
Simulation time 8377308440 ps
CPU time 7.28 seconds
Started Apr 15 03:16:52 PM PDT 24
Finished Apr 15 03:17:00 PM PDT 24
Peak memory 204048 kb
Host smart-9360fd40-34c9-40b7-9cab-38802f232485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35300
97708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.3530097708
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.3156509099
Short name T480
Test name
Test status
Simulation time 8463441860 ps
CPU time 8.39 seconds
Started Apr 15 03:16:46 PM PDT 24
Finished Apr 15 03:16:55 PM PDT 24
Peak memory 204048 kb
Host smart-d723c0a9-f3d4-4523-aacf-b71ca67e7eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31565
09099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.3156509099
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1762808215
Short name T909
Test name
Test status
Simulation time 8417300248 ps
CPU time 8.33 seconds
Started Apr 15 03:16:53 PM PDT 24
Finished Apr 15 03:17:02 PM PDT 24
Peak memory 204044 kb
Host smart-fc62070f-14b8-40b2-aeea-23199e2d21e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17628
08215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1762808215
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.265001486
Short name T633
Test name
Test status
Simulation time 8382937750 ps
CPU time 7.49 seconds
Started Apr 15 03:16:45 PM PDT 24
Finished Apr 15 03:16:54 PM PDT 24
Peak memory 204060 kb
Host smart-3f52a4eb-9d8a-4108-9a4c-1fa9475a8c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26500
1486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.265001486
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3275597617
Short name T95
Test name
Test status
Simulation time 8433058402 ps
CPU time 8.01 seconds
Started Apr 15 03:16:52 PM PDT 24
Finished Apr 15 03:17:01 PM PDT 24
Peak memory 204044 kb
Host smart-9915fb27-e2e1-4c57-bb2c-740c9e562083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32755
97617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3275597617
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.1021100519
Short name T405
Test name
Test status
Simulation time 8404914250 ps
CPU time 7.94 seconds
Started Apr 15 03:16:47 PM PDT 24
Finished Apr 15 03:16:56 PM PDT 24
Peak memory 204068 kb
Host smart-2d92b57c-c774-4b6c-9c2d-4c5d7a5dd8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10211
00519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.1021100519
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2712572056
Short name T814
Test name
Test status
Simulation time 8405653401 ps
CPU time 8.65 seconds
Started Apr 15 03:16:46 PM PDT 24
Finished Apr 15 03:16:56 PM PDT 24
Peak memory 203976 kb
Host smart-dba68258-30c4-458f-950b-b71a89ee7f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27125
72056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2712572056
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.1457792109
Short name T78
Test name
Test status
Simulation time 8396138672 ps
CPU time 7.96 seconds
Started Apr 15 03:16:51 PM PDT 24
Finished Apr 15 03:17:00 PM PDT 24
Peak memory 204024 kb
Host smart-17788a5e-d89c-4224-9ce2-fb20f45daef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14577
92109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.1457792109
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.2827404715
Short name T943
Test name
Test status
Simulation time 8369050681 ps
CPU time 7.74 seconds
Started Apr 15 03:16:53 PM PDT 24
Finished Apr 15 03:17:02 PM PDT 24
Peak memory 204068 kb
Host smart-3396d7f3-9b3a-4117-8a4a-8cf92c962f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28274
04715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.2827404715
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1331460223
Short name T1100
Test name
Test status
Simulation time 35091588 ps
CPU time 0.66 seconds
Started Apr 15 03:16:57 PM PDT 24
Finished Apr 15 03:16:59 PM PDT 24
Peak memory 203864 kb
Host smart-7ec9c57f-923d-4092-b59e-51fbea869362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13314
60223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1331460223
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.3874339189
Short name T597
Test name
Test status
Simulation time 25853872429 ps
CPU time 56.85 seconds
Started Apr 15 03:16:45 PM PDT 24
Finished Apr 15 03:17:43 PM PDT 24
Peak memory 204360 kb
Host smart-b63cff47-30c4-44dd-abbe-24f3c2b52cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38743
39189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.3874339189
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.2058788458
Short name T645
Test name
Test status
Simulation time 8412287273 ps
CPU time 9.82 seconds
Started Apr 15 03:16:48 PM PDT 24
Finished Apr 15 03:16:59 PM PDT 24
Peak memory 204072 kb
Host smart-caa10c50-c357-42ae-a330-640e81615607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20587
88458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.2058788458
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.93309730
Short name T410
Test name
Test status
Simulation time 8401428559 ps
CPU time 9.68 seconds
Started Apr 15 03:16:47 PM PDT 24
Finished Apr 15 03:16:58 PM PDT 24
Peak memory 203996 kb
Host smart-cbbb0b6e-c419-42a3-b425-b8e54f06ac04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93309
730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.93309730
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.403265336
Short name T336
Test name
Test status
Simulation time 8397672743 ps
CPU time 9.06 seconds
Started Apr 15 03:16:47 PM PDT 24
Finished Apr 15 03:16:57 PM PDT 24
Peak memory 204056 kb
Host smart-1630adbc-1369-4a58-a84c-7d3a574d6fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40326
5336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.403265336
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.2682507429
Short name T161
Test name
Test status
Simulation time 8383095253 ps
CPU time 8.34 seconds
Started Apr 15 03:16:51 PM PDT 24
Finished Apr 15 03:17:00 PM PDT 24
Peak memory 203996 kb
Host smart-67c10263-1a7e-46f6-aa5b-339f28a47a34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26825
07429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.2682507429
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.4282878384
Short name T812
Test name
Test status
Simulation time 8365959573 ps
CPU time 9.64 seconds
Started Apr 15 03:16:58 PM PDT 24
Finished Apr 15 03:17:09 PM PDT 24
Peak memory 204052 kb
Host smart-81311f01-9ca8-414b-85fc-f04c5f7dbcf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42828
78384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.4282878384
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.2705173823
Short name T202
Test name
Test status
Simulation time 8403831055 ps
CPU time 9.23 seconds
Started Apr 15 03:16:58 PM PDT 24
Finished Apr 15 03:17:09 PM PDT 24
Peak memory 204044 kb
Host smart-20beba3f-a82e-49a0-81f0-e76f921941ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27051
73823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.2705173823
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.3639684620
Short name T805
Test name
Test status
Simulation time 8385329925 ps
CPU time 7.83 seconds
Started Apr 15 03:16:54 PM PDT 24
Finished Apr 15 03:17:02 PM PDT 24
Peak memory 204032 kb
Host smart-d716fad5-7fe2-4248-9d90-62dcd57c42c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36396
84620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.3639684620
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.2113885223
Short name T758
Test name
Test status
Simulation time 8518720040 ps
CPU time 8.03 seconds
Started Apr 15 03:17:02 PM PDT 24
Finished Apr 15 03:17:10 PM PDT 24
Peak memory 204052 kb
Host smart-63762b02-5713-4ed4-8deb-69c6e3d0cd38
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2113885223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.2113885223
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.1836753239
Short name T1069
Test name
Test status
Simulation time 8374334284 ps
CPU time 8.06 seconds
Started Apr 15 03:17:02 PM PDT 24
Finished Apr 15 03:17:10 PM PDT 24
Peak memory 204068 kb
Host smart-90e8e1f3-8730-409b-9714-aca47b520145
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1836753239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.1836753239
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.1264264547
Short name T561
Test name
Test status
Simulation time 8413929496 ps
CPU time 8.26 seconds
Started Apr 15 03:17:06 PM PDT 24
Finished Apr 15 03:17:16 PM PDT 24
Peak memory 204028 kb
Host smart-c7878163-fad2-4973-86fc-22a5eeec0226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12642
64547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.1264264547
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.3308848319
Short name T498
Test name
Test status
Simulation time 8387348720 ps
CPU time 11 seconds
Started Apr 15 03:16:56 PM PDT 24
Finished Apr 15 03:17:09 PM PDT 24
Peak memory 204028 kb
Host smart-c7d3e080-43d8-4933-94a3-c7ee43d4b9ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33088
48319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.3308848319
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_enable.1356477128
Short name T363
Test name
Test status
Simulation time 8396166316 ps
CPU time 8.7 seconds
Started Apr 15 03:16:56 PM PDT 24
Finished Apr 15 03:17:05 PM PDT 24
Peak memory 204060 kb
Host smart-a3fb8fed-a5c4-487a-85d8-59aaea0f2253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13564
77128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.1356477128
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.763359791
Short name T52
Test name
Test status
Simulation time 218448526 ps
CPU time 2.32 seconds
Started Apr 15 03:16:53 PM PDT 24
Finished Apr 15 03:16:56 PM PDT 24
Peak memory 204188 kb
Host smart-7d0cbcdf-369b-4977-9b36-7181d0b133b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76335
9791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.763359791
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.3427290131
Short name T911
Test name
Test status
Simulation time 8445213065 ps
CPU time 10.2 seconds
Started Apr 15 03:16:58 PM PDT 24
Finished Apr 15 03:17:09 PM PDT 24
Peak memory 204052 kb
Host smart-b1d2dd30-d260-47af-8fb3-c975cc51ca69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34272
90131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.3427290131
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.1982381706
Short name T184
Test name
Test status
Simulation time 8368885551 ps
CPU time 8.11 seconds
Started Apr 15 03:16:59 PM PDT 24
Finished Apr 15 03:17:08 PM PDT 24
Peak memory 204040 kb
Host smart-9300df5e-d1e4-486a-858e-adf892ac75ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19823
81706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.1982381706
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.713158501
Short name T734
Test name
Test status
Simulation time 8444736455 ps
CPU time 8.09 seconds
Started Apr 15 03:16:58 PM PDT 24
Finished Apr 15 03:17:07 PM PDT 24
Peak memory 204028 kb
Host smart-4885cd2f-03f8-4706-8c86-c1dd6e15e80a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71315
8501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.713158501
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.1885252613
Short name T1063
Test name
Test status
Simulation time 8431633719 ps
CPU time 7.82 seconds
Started Apr 15 03:16:59 PM PDT 24
Finished Apr 15 03:17:08 PM PDT 24
Peak memory 203992 kb
Host smart-73dcdbf8-5217-4f38-b64a-f4ce28e3ab04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18852
52613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.1885252613
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.1608588512
Short name T970
Test name
Test status
Simulation time 8367312721 ps
CPU time 9.36 seconds
Started Apr 15 03:17:00 PM PDT 24
Finished Apr 15 03:17:11 PM PDT 24
Peak memory 204052 kb
Host smart-ad662ab4-29a2-4925-b74a-a9edcccd9eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16085
88512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.1608588512
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1602235921
Short name T751
Test name
Test status
Simulation time 8456320030 ps
CPU time 7.97 seconds
Started Apr 15 03:16:57 PM PDT 24
Finished Apr 15 03:17:06 PM PDT 24
Peak memory 204048 kb
Host smart-f7199630-0b43-4a25-ad4a-02f4c861f74f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16022
35921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1602235921
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.1382216892
Short name T1005
Test name
Test status
Simulation time 8400093511 ps
CPU time 8.23 seconds
Started Apr 15 03:16:58 PM PDT 24
Finished Apr 15 03:17:07 PM PDT 24
Peak memory 204028 kb
Host smart-567c095c-599e-4a85-9081-7aaf98a2da50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13822
16892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.1382216892
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.2355745574
Short name T1310
Test name
Test status
Simulation time 8376831263 ps
CPU time 8.02 seconds
Started Apr 15 03:16:59 PM PDT 24
Finished Apr 15 03:17:08 PM PDT 24
Peak memory 204036 kb
Host smart-5ca40525-6e7f-465d-a480-77c3551f56f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23557
45574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.2355745574
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.2153563587
Short name T152
Test name
Test status
Simulation time 8413571390 ps
CPU time 8.3 seconds
Started Apr 15 03:17:01 PM PDT 24
Finished Apr 15 03:17:10 PM PDT 24
Peak memory 204048 kb
Host smart-6026c25e-4eb1-42b4-bad2-674511a75792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21535
63587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.2153563587
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.1543880654
Short name T648
Test name
Test status
Simulation time 8400474632 ps
CPU time 9.42 seconds
Started Apr 15 03:16:57 PM PDT 24
Finished Apr 15 03:17:07 PM PDT 24
Peak memory 203972 kb
Host smart-0a4444c9-1a88-425f-afd2-83b89a22832d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15438
80654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.1543880654
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.260157808
Short name T603
Test name
Test status
Simulation time 41885343 ps
CPU time 0.67 seconds
Started Apr 15 03:16:58 PM PDT 24
Finished Apr 15 03:17:00 PM PDT 24
Peak memory 203944 kb
Host smart-c080ee77-3e1c-4598-b63f-15c0c9a08ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26015
7808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.260157808
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.812569923
Short name T206
Test name
Test status
Simulation time 16071473506 ps
CPU time 28.65 seconds
Started Apr 15 03:16:59 PM PDT 24
Finished Apr 15 03:17:29 PM PDT 24
Peak memory 204276 kb
Host smart-d68e37ac-bd53-46ed-9308-45b11d7f1aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81256
9923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.812569923
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.2299246050
Short name T536
Test name
Test status
Simulation time 8418692576 ps
CPU time 8.05 seconds
Started Apr 15 03:17:01 PM PDT 24
Finished Apr 15 03:17:10 PM PDT 24
Peak memory 204056 kb
Host smart-17d46461-f10b-4e3a-88c4-d691bfa8ad28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22992
46050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.2299246050
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.4084065429
Short name T981
Test name
Test status
Simulation time 8457330024 ps
CPU time 7.85 seconds
Started Apr 15 03:16:56 PM PDT 24
Finished Apr 15 03:17:04 PM PDT 24
Peak memory 204068 kb
Host smart-c1fb8cf3-fbf6-4912-831b-efc478f87e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40840
65429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.4084065429
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.2191046857
Short name T279
Test name
Test status
Simulation time 8401149118 ps
CPU time 7.56 seconds
Started Apr 15 03:17:00 PM PDT 24
Finished Apr 15 03:17:09 PM PDT 24
Peak memory 203980 kb
Host smart-382ffbe9-b108-42f6-b183-1e506cc654c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21910
46857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.2191046857
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.3911498854
Short name T666
Test name
Test status
Simulation time 8370237110 ps
CPU time 8.17 seconds
Started Apr 15 03:16:57 PM PDT 24
Finished Apr 15 03:17:06 PM PDT 24
Peak memory 204044 kb
Host smart-d1108b58-c0db-4b3b-9596-9841cc10133b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39114
98854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.3911498854
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.210784836
Short name T341
Test name
Test status
Simulation time 8384165822 ps
CPU time 8.48 seconds
Started Apr 15 03:16:59 PM PDT 24
Finished Apr 15 03:17:09 PM PDT 24
Peak memory 204040 kb
Host smart-bc17ec17-8149-4108-b0c7-9a516413ab7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21078
4836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.210784836
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.2594862884
Short name T530
Test name
Test status
Simulation time 8464524551 ps
CPU time 8.87 seconds
Started Apr 15 03:16:57 PM PDT 24
Finished Apr 15 03:17:07 PM PDT 24
Peak memory 203988 kb
Host smart-60e918db-6227-41cf-a9ec-8a41a75f1e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25948
62884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2594862884
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.858273241
Short name T364
Test name
Test status
Simulation time 8398062277 ps
CPU time 8.94 seconds
Started Apr 15 03:17:00 PM PDT 24
Finished Apr 15 03:17:10 PM PDT 24
Peak memory 203976 kb
Host smart-9456f496-e0b0-498b-b157-b8c78adc8722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85827
3241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.858273241
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.4280773961
Short name T604
Test name
Test status
Simulation time 8376322471 ps
CPU time 8.03 seconds
Started Apr 15 03:16:56 PM PDT 24
Finished Apr 15 03:17:05 PM PDT 24
Peak memory 204056 kb
Host smart-114aee19-98e6-4124-98a6-a8d7c9609e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42807
73961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.4280773961
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.2639339725
Short name T280
Test name
Test status
Simulation time 8554250581 ps
CPU time 9.97 seconds
Started Apr 15 03:17:08 PM PDT 24
Finished Apr 15 03:17:19 PM PDT 24
Peak memory 204008 kb
Host smart-78efbe70-cd82-47b1-8f7f-519ea5c6fe06
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2639339725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.2639339725
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.2723279237
Short name T957
Test name
Test status
Simulation time 8409488262 ps
CPU time 7.98 seconds
Started Apr 15 03:17:09 PM PDT 24
Finished Apr 15 03:17:18 PM PDT 24
Peak memory 204048 kb
Host smart-6cd6909d-e75a-43f7-9ab5-2ee39dff9380
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2723279237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.2723279237
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.730544040
Short name T302
Test name
Test status
Simulation time 8403485976 ps
CPU time 10.34 seconds
Started Apr 15 03:17:08 PM PDT 24
Finished Apr 15 03:17:19 PM PDT 24
Peak memory 204036 kb
Host smart-21c97db7-8f39-4b4f-926a-87e5d342ee1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73054
4040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.730544040
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.1863441152
Short name T284
Test name
Test status
Simulation time 8421644972 ps
CPU time 10.17 seconds
Started Apr 15 03:17:06 PM PDT 24
Finished Apr 15 03:17:16 PM PDT 24
Peak memory 204048 kb
Host smart-2ccb6089-7561-4000-be8f-5ce4eb3662ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18634
41152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1863441152
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_enable.492656926
Short name T521
Test name
Test status
Simulation time 8396485482 ps
CPU time 8.04 seconds
Started Apr 15 03:17:03 PM PDT 24
Finished Apr 15 03:17:12 PM PDT 24
Peak memory 203928 kb
Host smart-4fea785d-392c-4bdc-adc5-e8cb387d9765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49265
6926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.492656926
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.3246197202
Short name T1186
Test name
Test status
Simulation time 178802489 ps
CPU time 1.97 seconds
Started Apr 15 03:17:02 PM PDT 24
Finished Apr 15 03:17:04 PM PDT 24
Peak memory 204192 kb
Host smart-ad207fe3-f67d-4d13-bdf7-af1b19813396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32461
97202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.3246197202
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.3461125498
Short name T331
Test name
Test status
Simulation time 8436650351 ps
CPU time 7.9 seconds
Started Apr 15 03:17:06 PM PDT 24
Finished Apr 15 03:17:15 PM PDT 24
Peak memory 204048 kb
Host smart-38d09d3a-c348-49fe-8b75-7a0afe5f7f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34611
25498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.3461125498
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.147329224
Short name T986
Test name
Test status
Simulation time 8359299718 ps
CPU time 8.04 seconds
Started Apr 15 03:17:06 PM PDT 24
Finished Apr 15 03:17:15 PM PDT 24
Peak memory 204000 kb
Host smart-b1f97dbe-ba90-4009-b1f8-051c4308d285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14732
9224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.147329224
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.666553010
Short name T461
Test name
Test status
Simulation time 8398772966 ps
CPU time 8.45 seconds
Started Apr 15 03:17:07 PM PDT 24
Finished Apr 15 03:17:16 PM PDT 24
Peak memory 204032 kb
Host smart-3d697e12-27df-4351-9fe8-053b422ef8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66655
3010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.666553010
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.3290100449
Short name T1228
Test name
Test status
Simulation time 8420711772 ps
CPU time 8.26 seconds
Started Apr 15 03:17:05 PM PDT 24
Finished Apr 15 03:17:14 PM PDT 24
Peak memory 204044 kb
Host smart-8b009e20-431e-4224-aa8e-27c0a99222c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32901
00449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3290100449
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.1524921262
Short name T766
Test name
Test status
Simulation time 8379046585 ps
CPU time 9.39 seconds
Started Apr 15 03:17:04 PM PDT 24
Finished Apr 15 03:17:14 PM PDT 24
Peak memory 204052 kb
Host smart-d0771663-fbbf-475d-9f3a-1fbcae52a440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15249
21262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.1524921262
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2952613795
Short name T614
Test name
Test status
Simulation time 8419394019 ps
CPU time 7.81 seconds
Started Apr 15 03:17:05 PM PDT 24
Finished Apr 15 03:17:13 PM PDT 24
Peak memory 204052 kb
Host smart-18f69876-ad49-47d5-9ba5-29576b3f152d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29526
13795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2952613795
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.767070702
Short name T455
Test name
Test status
Simulation time 8417125251 ps
CPU time 8.53 seconds
Started Apr 15 03:17:06 PM PDT 24
Finished Apr 15 03:17:15 PM PDT 24
Peak memory 204024 kb
Host smart-f969f08d-21a3-4e21-a383-f18428050092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76707
0702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.767070702
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.3014530507
Short name T725
Test name
Test status
Simulation time 8396532252 ps
CPU time 8.83 seconds
Started Apr 15 03:17:03 PM PDT 24
Finished Apr 15 03:17:12 PM PDT 24
Peak memory 204064 kb
Host smart-4f3d6056-2bad-4297-8e21-7463b42f4420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30145
30507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.3014530507
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.3236339027
Short name T173
Test name
Test status
Simulation time 8416273028 ps
CPU time 8.88 seconds
Started Apr 15 03:17:06 PM PDT 24
Finished Apr 15 03:17:16 PM PDT 24
Peak memory 203928 kb
Host smart-2195217a-a97c-40d8-9c94-c618d4cdd01c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32363
39027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.3236339027
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.1937101815
Short name T1059
Test name
Test status
Simulation time 8372258143 ps
CPU time 7.58 seconds
Started Apr 15 03:17:09 PM PDT 24
Finished Apr 15 03:17:17 PM PDT 24
Peak memory 204040 kb
Host smart-64f3c8ed-3eab-4e3d-ae19-fb0635e9daf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19371
01815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.1937101815
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.278092075
Short name T995
Test name
Test status
Simulation time 37442767 ps
CPU time 0.65 seconds
Started Apr 15 03:17:07 PM PDT 24
Finished Apr 15 03:17:09 PM PDT 24
Peak memory 203876 kb
Host smart-6284398f-5f20-4a1c-aa54-d5af9e8381fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27809
2075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.278092075
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.701891681
Short name T207
Test name
Test status
Simulation time 22583345980 ps
CPU time 40.06 seconds
Started Apr 15 03:17:07 PM PDT 24
Finished Apr 15 03:17:48 PM PDT 24
Peak memory 204340 kb
Host smart-d6fc03b5-2897-4c2c-870d-88f030bb9b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70189
1681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.701891681
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.3436516788
Short name T928
Test name
Test status
Simulation time 8390283237 ps
CPU time 8.11 seconds
Started Apr 15 03:17:00 PM PDT 24
Finished Apr 15 03:17:09 PM PDT 24
Peak memory 204080 kb
Host smart-41e60312-a304-4842-9058-6ed0517ce4e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34365
16788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.3436516788
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.428112885
Short name T1143
Test name
Test status
Simulation time 8439700130 ps
CPU time 8.58 seconds
Started Apr 15 03:17:06 PM PDT 24
Finished Apr 15 03:17:15 PM PDT 24
Peak memory 204056 kb
Host smart-114c0c60-7df3-47e3-ba32-64a355c6932e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42811
2885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.428112885
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.3180242882
Short name T200
Test name
Test status
Simulation time 8395483198 ps
CPU time 7.73 seconds
Started Apr 15 03:17:08 PM PDT 24
Finished Apr 15 03:17:16 PM PDT 24
Peak memory 204016 kb
Host smart-e6b81849-0042-4661-8819-fb0eaa01a5e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31802
42882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.3180242882
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.1962645695
Short name T1353
Test name
Test status
Simulation time 8421849401 ps
CPU time 9.06 seconds
Started Apr 15 03:17:07 PM PDT 24
Finished Apr 15 03:17:17 PM PDT 24
Peak memory 204048 kb
Host smart-2a603279-b5e1-40f9-a8a1-4db60fdbdbd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19626
45695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.1962645695
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.1388876272
Short name T721
Test name
Test status
Simulation time 8405544477 ps
CPU time 9.14 seconds
Started Apr 15 03:17:07 PM PDT 24
Finished Apr 15 03:17:17 PM PDT 24
Peak memory 203972 kb
Host smart-8093fe60-f567-4530-ba13-4ecb2aa54693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13888
76272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.1388876272
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.2487489511
Short name T36
Test name
Test status
Simulation time 8446330190 ps
CPU time 9.95 seconds
Started Apr 15 03:17:00 PM PDT 24
Finished Apr 15 03:17:11 PM PDT 24
Peak memory 204072 kb
Host smart-03a28e19-9ff7-4c8d-91e4-1beefeaf63e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24874
89511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2487489511
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3830936920
Short name T297
Test name
Test status
Simulation time 8390287934 ps
CPU time 9.48 seconds
Started Apr 15 03:17:07 PM PDT 24
Finished Apr 15 03:17:17 PM PDT 24
Peak memory 204060 kb
Host smart-aa3cc034-6899-4565-acbb-dfb441357375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38309
36920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3830936920
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.3230724932
Short name T366
Test name
Test status
Simulation time 8371722490 ps
CPU time 8.26 seconds
Started Apr 15 03:17:09 PM PDT 24
Finished Apr 15 03:17:17 PM PDT 24
Peak memory 204040 kb
Host smart-a0c95642-773b-4c48-b839-e981537616ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32307
24932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.3230724932
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.3769494768
Short name T1163
Test name
Test status
Simulation time 8463465128 ps
CPU time 8.47 seconds
Started Apr 15 03:17:14 PM PDT 24
Finished Apr 15 03:17:23 PM PDT 24
Peak memory 204040 kb
Host smart-68f93baa-977c-427f-b798-396b41cb5c4b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3769494768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.3769494768
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.2339539879
Short name T546
Test name
Test status
Simulation time 8373020102 ps
CPU time 8.24 seconds
Started Apr 15 03:17:17 PM PDT 24
Finished Apr 15 03:17:26 PM PDT 24
Peak memory 204068 kb
Host smart-7caff008-b667-4901-b01d-a9be5d5acc90
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2339539879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.2339539879
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.1186268337
Short name T1354
Test name
Test status
Simulation time 8440612221 ps
CPU time 8.13 seconds
Started Apr 15 03:17:14 PM PDT 24
Finished Apr 15 03:17:23 PM PDT 24
Peak memory 204032 kb
Host smart-6ed0f70a-ca39-4ff0-b06c-80106f16f804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11862
68337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.1186268337
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.3069976186
Short name T431
Test name
Test status
Simulation time 8388247245 ps
CPU time 7.83 seconds
Started Apr 15 03:17:06 PM PDT 24
Finished Apr 15 03:17:15 PM PDT 24
Peak memory 204028 kb
Host smart-0ac9f6a5-0ae9-4f4f-b54b-114943658b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30699
76186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.3069976186
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_enable.758630378
Short name T655
Test name
Test status
Simulation time 8374539906 ps
CPU time 8.9 seconds
Started Apr 15 03:17:06 PM PDT 24
Finished Apr 15 03:17:16 PM PDT 24
Peak memory 204052 kb
Host smart-0d95dcc3-5b07-45e8-b25e-2cb776991fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75863
0378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.758630378
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.519144779
Short name T454
Test name
Test status
Simulation time 44379360 ps
CPU time 1.05 seconds
Started Apr 15 03:17:12 PM PDT 24
Finished Apr 15 03:17:13 PM PDT 24
Peak memory 204100 kb
Host smart-f6966b47-0917-46f6-9b1c-92f611078c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51914
4779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.519144779
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.1541804818
Short name T741
Test name
Test status
Simulation time 8430961613 ps
CPU time 8.06 seconds
Started Apr 15 03:17:18 PM PDT 24
Finished Apr 15 03:17:27 PM PDT 24
Peak memory 204048 kb
Host smart-d06911c9-40e0-4d7d-84d7-1f900c908173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15418
04818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.1541804818
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.3013409382
Short name T1111
Test name
Test status
Simulation time 8377653027 ps
CPU time 9.47 seconds
Started Apr 15 03:17:15 PM PDT 24
Finished Apr 15 03:17:25 PM PDT 24
Peak memory 204060 kb
Host smart-3880afdd-9147-48e5-bf5a-def1135f95b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30134
09382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.3013409382
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.1381350206
Short name T130
Test name
Test status
Simulation time 8413214112 ps
CPU time 7.99 seconds
Started Apr 15 03:17:14 PM PDT 24
Finished Apr 15 03:17:23 PM PDT 24
Peak memory 204076 kb
Host smart-09b9694f-0f97-42c4-81b0-d5c78bef14ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13813
50206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.1381350206
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.2904858893
Short name T963
Test name
Test status
Simulation time 8425542617 ps
CPU time 10.27 seconds
Started Apr 15 03:17:13 PM PDT 24
Finished Apr 15 03:17:24 PM PDT 24
Peak memory 204056 kb
Host smart-8afab638-3642-4d11-90c0-1ed2b4f09725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29048
58893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2904858893
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2368193952
Short name T282
Test name
Test status
Simulation time 8375388329 ps
CPU time 7.91 seconds
Started Apr 15 03:17:11 PM PDT 24
Finished Apr 15 03:17:20 PM PDT 24
Peak memory 204032 kb
Host smart-84ce9c05-7823-40ae-8410-97a402bf8b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23681
93952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2368193952
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.2326836679
Short name T112
Test name
Test status
Simulation time 8455054244 ps
CPU time 8.89 seconds
Started Apr 15 03:17:12 PM PDT 24
Finished Apr 15 03:17:21 PM PDT 24
Peak memory 203988 kb
Host smart-8b84a988-326c-4e5b-a668-8a82ec3c76fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23268
36679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.2326836679
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.2992070083
Short name T722
Test name
Test status
Simulation time 8434242384 ps
CPU time 7.42 seconds
Started Apr 15 03:17:10 PM PDT 24
Finished Apr 15 03:17:18 PM PDT 24
Peak memory 204032 kb
Host smart-fa6a64c5-940e-43ad-9afd-d319aac673cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29920
70083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.2992070083
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.112174979
Short name T1172
Test name
Test status
Simulation time 8421573951 ps
CPU time 8.16 seconds
Started Apr 15 03:17:09 PM PDT 24
Finished Apr 15 03:17:18 PM PDT 24
Peak memory 204052 kb
Host smart-2c504767-e035-4351-9b70-69cc127b8dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11217
4979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.112174979
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.2244682458
Short name T1
Test name
Test status
Simulation time 8414815070 ps
CPU time 10.28 seconds
Started Apr 15 03:17:16 PM PDT 24
Finished Apr 15 03:17:27 PM PDT 24
Peak memory 204060 kb
Host smart-07bcbcb2-5804-4a57-b2ea-c86a5ff96eda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22446
82458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.2244682458
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.3609497738
Short name T286
Test name
Test status
Simulation time 8366974202 ps
CPU time 9.18 seconds
Started Apr 15 03:17:10 PM PDT 24
Finished Apr 15 03:17:20 PM PDT 24
Peak memory 203924 kb
Host smart-718962e4-afcd-400a-9347-01117f28b862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36094
97738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.3609497738
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.2954455901
Short name T453
Test name
Test status
Simulation time 79300207 ps
CPU time 0.69 seconds
Started Apr 15 03:17:15 PM PDT 24
Finished Apr 15 03:17:16 PM PDT 24
Peak memory 203932 kb
Host smart-e7febff2-abe8-4328-8332-bf9333dabef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29544
55901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.2954455901
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3736333978
Short name T799
Test name
Test status
Simulation time 8388278604 ps
CPU time 8.4 seconds
Started Apr 15 03:17:11 PM PDT 24
Finished Apr 15 03:17:20 PM PDT 24
Peak memory 204060 kb
Host smart-02bfa68f-d334-4701-a2ec-d5cfa3290aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37363
33978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3736333978
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.1547598395
Short name T827
Test name
Test status
Simulation time 8454453988 ps
CPU time 7.81 seconds
Started Apr 15 03:17:10 PM PDT 24
Finished Apr 15 03:17:18 PM PDT 24
Peak memory 204068 kb
Host smart-c03773b0-40c7-4821-bed4-413ab4859e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15475
98395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1547598395
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.702609941
Short name T400
Test name
Test status
Simulation time 8417808886 ps
CPU time 9.63 seconds
Started Apr 15 03:17:18 PM PDT 24
Finished Apr 15 03:17:28 PM PDT 24
Peak memory 204052 kb
Host smart-90d99ca5-631d-4709-a4e4-73a49b43ddaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70260
9941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.702609941
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.3172265561
Short name T378
Test name
Test status
Simulation time 8379369616 ps
CPU time 8.45 seconds
Started Apr 15 03:17:19 PM PDT 24
Finished Apr 15 03:17:28 PM PDT 24
Peak memory 204048 kb
Host smart-d2d51f89-eaee-4ce6-93cf-1122c0eefff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31722
65561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.3172265561
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.3570568596
Short name T353
Test name
Test status
Simulation time 8368617501 ps
CPU time 9.01 seconds
Started Apr 15 03:17:11 PM PDT 24
Finished Apr 15 03:17:20 PM PDT 24
Peak memory 204020 kb
Host smart-0f3f9466-8eb1-4463-81db-e0986255574a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35705
68596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.3570568596
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.3678773596
Short name T77
Test name
Test status
Simulation time 8439147668 ps
CPU time 8.44 seconds
Started Apr 15 03:17:05 PM PDT 24
Finished Apr 15 03:17:14 PM PDT 24
Peak memory 203884 kb
Host smart-c43d1708-62fb-450a-9eca-9e69a25be950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36787
73596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.3678773596
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.2657980231
Short name T1124
Test name
Test status
Simulation time 8408326981 ps
CPU time 7.64 seconds
Started Apr 15 03:17:13 PM PDT 24
Finished Apr 15 03:17:21 PM PDT 24
Peak memory 204044 kb
Host smart-3550c230-507e-4dcd-93e9-acd2fb420748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26579
80231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.2657980231
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.3878417277
Short name T1209
Test name
Test status
Simulation time 8405842430 ps
CPU time 7.71 seconds
Started Apr 15 03:17:11 PM PDT 24
Finished Apr 15 03:17:19 PM PDT 24
Peak memory 204032 kb
Host smart-17e65fc2-c285-43e1-8e00-53deb64f22eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38784
17277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.3878417277
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.2234846883
Short name T475
Test name
Test status
Simulation time 8567205436 ps
CPU time 8.24 seconds
Started Apr 15 03:17:26 PM PDT 24
Finished Apr 15 03:17:34 PM PDT 24
Peak memory 204028 kb
Host smart-f764625d-b85b-4566-ac23-633a74153b58
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2234846883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.2234846883
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.1822672092
Short name T1064
Test name
Test status
Simulation time 8410378804 ps
CPU time 8.92 seconds
Started Apr 15 03:17:25 PM PDT 24
Finished Apr 15 03:17:34 PM PDT 24
Peak memory 203980 kb
Host smart-70aee667-49d9-4800-a56b-8d8c0113d2d6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1822672092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.1822672092
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.random_length_in_trans.549678284
Short name T1234
Test name
Test status
Simulation time 8458246283 ps
CPU time 8.99 seconds
Started Apr 15 03:17:25 PM PDT 24
Finished Apr 15 03:17:34 PM PDT 24
Peak memory 204064 kb
Host smart-289cadb2-6ee4-455c-9520-b72a497fdd0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54967
8284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.549678284
Directory /workspace/37.random_length_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.2736570509
Short name T1007
Test name
Test status
Simulation time 8393809177 ps
CPU time 9.01 seconds
Started Apr 15 03:17:17 PM PDT 24
Finished Apr 15 03:17:27 PM PDT 24
Peak memory 204064 kb
Host smart-884f6711-cf28-419e-99cc-485a2bb6c2bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27365
70509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2736570509
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_enable.2276509657
Short name T301
Test name
Test status
Simulation time 8385783942 ps
CPU time 8.25 seconds
Started Apr 15 03:17:15 PM PDT 24
Finished Apr 15 03:17:24 PM PDT 24
Peak memory 203988 kb
Host smart-d16006e6-ee41-49b0-aa4d-0f1f72c7950f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22765
09657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.2276509657
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.190918703
Short name T720
Test name
Test status
Simulation time 107420448 ps
CPU time 1.3 seconds
Started Apr 15 03:17:15 PM PDT 24
Finished Apr 15 03:17:17 PM PDT 24
Peak memory 204164 kb
Host smart-9a23360d-b15b-4980-ac70-da710948d4d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19091
8703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.190918703
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.2521510465
Short name T554
Test name
Test status
Simulation time 8452304392 ps
CPU time 8.91 seconds
Started Apr 15 03:17:23 PM PDT 24
Finished Apr 15 03:17:33 PM PDT 24
Peak memory 204028 kb
Host smart-1b358d74-8fc5-4acc-a024-ef78de98d9ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25215
10465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.2521510465
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.2779708754
Short name T1244
Test name
Test status
Simulation time 8366183292 ps
CPU time 7.95 seconds
Started Apr 15 03:17:23 PM PDT 24
Finished Apr 15 03:17:31 PM PDT 24
Peak memory 204020 kb
Host smart-1961c764-7bf4-4177-a3d2-cdb0ed81fd18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27797
08754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.2779708754
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.1763500777
Short name T1149
Test name
Test status
Simulation time 8495693571 ps
CPU time 8.2 seconds
Started Apr 15 03:17:18 PM PDT 24
Finished Apr 15 03:17:27 PM PDT 24
Peak memory 203984 kb
Host smart-57c7cf08-d395-4fc4-a337-5819b08b752f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17635
00777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.1763500777
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.2012913507
Short name T742
Test name
Test status
Simulation time 8425079212 ps
CPU time 8.87 seconds
Started Apr 15 03:17:21 PM PDT 24
Finished Apr 15 03:17:30 PM PDT 24
Peak memory 204052 kb
Host smart-ba0a7908-2563-4d46-a7f8-9c98fa9036c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20129
13507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.2012913507
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.2615222375
Short name T359
Test name
Test status
Simulation time 8366701734 ps
CPU time 8.44 seconds
Started Apr 15 03:17:19 PM PDT 24
Finished Apr 15 03:17:28 PM PDT 24
Peak memory 204064 kb
Host smart-bf34cc01-a871-41be-967c-e36a814be71b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26152
22375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.2615222375
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.2875482884
Short name T934
Test name
Test status
Simulation time 8418894559 ps
CPU time 8.12 seconds
Started Apr 15 03:17:19 PM PDT 24
Finished Apr 15 03:17:27 PM PDT 24
Peak memory 204056 kb
Host smart-f28b6257-1ec5-4941-abe5-73fad7925d46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28754
82884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.2875482884
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.741967120
Short name T898
Test name
Test status
Simulation time 8444785202 ps
CPU time 7.95 seconds
Started Apr 15 03:17:19 PM PDT 24
Finished Apr 15 03:17:27 PM PDT 24
Peak memory 204056 kb
Host smart-3b5a60b5-3ea3-4ec0-9271-3b9746378ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74196
7120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.741967120
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.2306960528
Short name T907
Test name
Test status
Simulation time 8382361061 ps
CPU time 7.81 seconds
Started Apr 15 03:17:19 PM PDT 24
Finished Apr 15 03:17:28 PM PDT 24
Peak memory 204060 kb
Host smart-b49f3559-804b-4f2d-954b-2bc4c2b0eaec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23069
60528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2306960528
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.1230180607
Short name T158
Test name
Test status
Simulation time 8388617796 ps
CPU time 8.62 seconds
Started Apr 15 03:17:26 PM PDT 24
Finished Apr 15 03:17:35 PM PDT 24
Peak memory 204044 kb
Host smart-ecd479bc-d406-4144-ae90-13d43961870e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12301
80607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.1230180607
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.2747819406
Short name T467
Test name
Test status
Simulation time 8365719888 ps
CPU time 9.76 seconds
Started Apr 15 03:17:23 PM PDT 24
Finished Apr 15 03:17:33 PM PDT 24
Peak memory 204004 kb
Host smart-07e9b6a2-6076-414c-8e6d-33d7d4535850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27478
19406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.2747819406
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.1541848353
Short name T469
Test name
Test status
Simulation time 33364586 ps
CPU time 0.66 seconds
Started Apr 15 03:17:22 PM PDT 24
Finished Apr 15 03:17:23 PM PDT 24
Peak memory 203860 kb
Host smart-50ec3bf3-3b56-4673-aeff-97bccc6b8c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15418
48353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.1541848353
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.460509415
Short name T12
Test name
Test status
Simulation time 21303856403 ps
CPU time 41.42 seconds
Started Apr 15 03:17:19 PM PDT 24
Finished Apr 15 03:18:01 PM PDT 24
Peak memory 204332 kb
Host smart-1951c5d9-e968-4201-b52d-da9e9c3e22fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46050
9415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.460509415
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.2134538342
Short name T551
Test name
Test status
Simulation time 8378851098 ps
CPU time 9.81 seconds
Started Apr 15 03:17:17 PM PDT 24
Finished Apr 15 03:17:27 PM PDT 24
Peak memory 204004 kb
Host smart-82535733-41bf-402d-86a1-2d3458f87259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21345
38342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2134538342
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.3960693837
Short name T704
Test name
Test status
Simulation time 8409052867 ps
CPU time 7.72 seconds
Started Apr 15 03:17:20 PM PDT 24
Finished Apr 15 03:17:28 PM PDT 24
Peak memory 204056 kb
Host smart-1478e863-16c9-417d-a315-7f5b0c661d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39606
93837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.3960693837
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.1404730660
Short name T368
Test name
Test status
Simulation time 8409932316 ps
CPU time 8.91 seconds
Started Apr 15 03:17:19 PM PDT 24
Finished Apr 15 03:17:28 PM PDT 24
Peak memory 204052 kb
Host smart-35fd036b-4016-4cc3-8adb-c809dc905849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14047
30660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.1404730660
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.3478971893
Short name T148
Test name
Test status
Simulation time 8419958851 ps
CPU time 7.95 seconds
Started Apr 15 03:17:26 PM PDT 24
Finished Apr 15 03:17:34 PM PDT 24
Peak memory 204020 kb
Host smart-e47f6c2f-278c-418a-a05a-9e5e218ad5a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34789
71893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.3478971893
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.4181348191
Short name T972
Test name
Test status
Simulation time 8371058713 ps
CPU time 8.32 seconds
Started Apr 15 03:17:26 PM PDT 24
Finished Apr 15 03:17:35 PM PDT 24
Peak memory 204044 kb
Host smart-a56af33f-7780-466d-9055-761804cf4cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41813
48191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.4181348191
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.1690557828
Short name T1196
Test name
Test status
Simulation time 8463226524 ps
CPU time 7.96 seconds
Started Apr 15 03:17:16 PM PDT 24
Finished Apr 15 03:17:24 PM PDT 24
Peak memory 204208 kb
Host smart-e9d380a6-e191-4bcf-aa9d-f80dbb3d1f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16905
57828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.1690557828
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.1016397820
Short name T298
Test name
Test status
Simulation time 8397370826 ps
CPU time 7.68 seconds
Started Apr 15 03:17:26 PM PDT 24
Finished Apr 15 03:17:35 PM PDT 24
Peak memory 204040 kb
Host smart-c6ff8b1f-f5d1-4667-bcb2-c806f436f537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10163
97820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.1016397820
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.944628231
Short name T1194
Test name
Test status
Simulation time 8403786775 ps
CPU time 8.48 seconds
Started Apr 15 03:17:25 PM PDT 24
Finished Apr 15 03:17:34 PM PDT 24
Peak memory 203972 kb
Host smart-03e9dfc3-22b5-4259-8c20-91ab032819cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94462
8231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.944628231
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.3873459182
Short name T817
Test name
Test status
Simulation time 8466854126 ps
CPU time 9.25 seconds
Started Apr 15 03:17:31 PM PDT 24
Finished Apr 15 03:17:41 PM PDT 24
Peak memory 204064 kb
Host smart-e47a569e-2b02-4ee2-b450-05a0fe83b119
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3873459182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.3873459182
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.996235107
Short name T920
Test name
Test status
Simulation time 8386046720 ps
CPU time 8.01 seconds
Started Apr 15 03:17:27 PM PDT 24
Finished Apr 15 03:17:36 PM PDT 24
Peak memory 204056 kb
Host smart-bd80ee7c-b552-47f7-962b-761ef081681a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=996235107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.996235107
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.2237791037
Short name T1332
Test name
Test status
Simulation time 8417396274 ps
CPU time 8.29 seconds
Started Apr 15 03:17:29 PM PDT 24
Finished Apr 15 03:17:38 PM PDT 24
Peak memory 204060 kb
Host smart-da2df1e1-1e55-40b5-92ce-eefe642d86ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22377
91037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.2237791037
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.549120436
Short name T999
Test name
Test status
Simulation time 8414524647 ps
CPU time 10.43 seconds
Started Apr 15 03:17:23 PM PDT 24
Finished Apr 15 03:17:34 PM PDT 24
Peak memory 204008 kb
Host smart-c3de50e9-82ed-4ed3-98de-de3422439953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54912
0436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.549120436
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_enable.3987560382
Short name T1115
Test name
Test status
Simulation time 8375666499 ps
CPU time 8.85 seconds
Started Apr 15 03:17:24 PM PDT 24
Finished Apr 15 03:17:33 PM PDT 24
Peak memory 204060 kb
Host smart-00345df9-5016-425f-853f-134fee30a658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39875
60382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.3987560382
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.2594775874
Short name T890
Test name
Test status
Simulation time 64983998 ps
CPU time 1.44 seconds
Started Apr 15 03:17:26 PM PDT 24
Finished Apr 15 03:17:28 PM PDT 24
Peak memory 204084 kb
Host smart-28a0420e-258e-4dc1-9492-9b27963887e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25947
75874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2594775874
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.1825558132
Short name T1356
Test name
Test status
Simulation time 8428175126 ps
CPU time 8.59 seconds
Started Apr 15 03:17:27 PM PDT 24
Finished Apr 15 03:17:36 PM PDT 24
Peak memory 204048 kb
Host smart-bae246b5-4800-4957-bda1-7debfefab7ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18255
58132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.1825558132
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.971503693
Short name T1184
Test name
Test status
Simulation time 8372824505 ps
CPU time 8.39 seconds
Started Apr 15 03:17:29 PM PDT 24
Finished Apr 15 03:17:38 PM PDT 24
Peak memory 204024 kb
Host smart-aec71183-29b7-440b-88ec-4b53c7f0fa04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97150
3693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.971503693
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.764653917
Short name T902
Test name
Test status
Simulation time 8443682316 ps
CPU time 9.75 seconds
Started Apr 15 03:17:28 PM PDT 24
Finished Apr 15 03:17:38 PM PDT 24
Peak memory 204028 kb
Host smart-ab6d636c-2f56-46a8-a957-7a78e47de365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76465
3917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.764653917
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1644999848
Short name T930
Test name
Test status
Simulation time 8444808122 ps
CPU time 10.09 seconds
Started Apr 15 03:17:28 PM PDT 24
Finished Apr 15 03:17:39 PM PDT 24
Peak memory 204004 kb
Host smart-fafbc72a-b471-44f6-adfa-349acee1853d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16449
99848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1644999848
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3266014142
Short name T478
Test name
Test status
Simulation time 8410288349 ps
CPU time 10.39 seconds
Started Apr 15 03:17:26 PM PDT 24
Finished Apr 15 03:17:37 PM PDT 24
Peak memory 204012 kb
Host smart-ed65d245-3b78-4451-9126-0154db479bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32660
14142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3266014142
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.248452260
Short name T89
Test name
Test status
Simulation time 8487151982 ps
CPU time 8.06 seconds
Started Apr 15 03:17:27 PM PDT 24
Finished Apr 15 03:17:36 PM PDT 24
Peak memory 204060 kb
Host smart-3cac0a90-0123-47ef-a603-3f403d8b469a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24845
2260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.248452260
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2632729535
Short name T342
Test name
Test status
Simulation time 8447196324 ps
CPU time 9.33 seconds
Started Apr 15 03:17:26 PM PDT 24
Finished Apr 15 03:17:37 PM PDT 24
Peak memory 204068 kb
Host smart-82ec990f-816b-413c-a90b-b2d2049e859a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26327
29535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2632729535
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.308681062
Short name T355
Test name
Test status
Simulation time 8414457429 ps
CPU time 8.03 seconds
Started Apr 15 03:17:33 PM PDT 24
Finished Apr 15 03:17:42 PM PDT 24
Peak memory 204052 kb
Host smart-ff040dd0-fb76-464b-993c-e1fda6af2aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30868
1062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.308681062
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.1951904275
Short name T1157
Test name
Test status
Simulation time 8412731227 ps
CPU time 9.85 seconds
Started Apr 15 03:17:33 PM PDT 24
Finished Apr 15 03:17:44 PM PDT 24
Peak memory 204020 kb
Host smart-f7bd5677-e058-4f34-9f97-de7fd12be7f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19519
04275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.1951904275
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.3194507412
Short name T1343
Test name
Test status
Simulation time 8373993330 ps
CPU time 9.44 seconds
Started Apr 15 03:17:34 PM PDT 24
Finished Apr 15 03:17:44 PM PDT 24
Peak memory 203996 kb
Host smart-ed36e012-35bc-4fe7-a2a0-582e314c0f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31945
07412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.3194507412
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.1968835342
Short name T631
Test name
Test status
Simulation time 46369236 ps
CPU time 0.7 seconds
Started Apr 15 03:17:26 PM PDT 24
Finished Apr 15 03:17:28 PM PDT 24
Peak memory 203752 kb
Host smart-13375c5b-2914-4565-ab7d-48a40dfd8d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19688
35342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.1968835342
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.2417831090
Short name T1081
Test name
Test status
Simulation time 24895512099 ps
CPU time 45.76 seconds
Started Apr 15 03:17:27 PM PDT 24
Finished Apr 15 03:18:14 PM PDT 24
Peak memory 204316 kb
Host smart-beaab3e1-5838-47e5-8c55-721265a2c94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24178
31090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.2417831090
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.2397996914
Short name T269
Test name
Test status
Simulation time 8413927060 ps
CPU time 8.21 seconds
Started Apr 15 03:17:28 PM PDT 24
Finished Apr 15 03:17:37 PM PDT 24
Peak memory 204048 kb
Host smart-52f1b79b-0f30-43f9-8754-8b2b81394c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23979
96914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.2397996914
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.1706610229
Short name T636
Test name
Test status
Simulation time 8401074476 ps
CPU time 7.74 seconds
Started Apr 15 03:17:29 PM PDT 24
Finished Apr 15 03:17:38 PM PDT 24
Peak memory 203968 kb
Host smart-0b575bd0-fb43-498d-8dac-617d52f2be75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17066
10229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.1706610229
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.3665627768
Short name T1110
Test name
Test status
Simulation time 8373721103 ps
CPU time 10.03 seconds
Started Apr 15 03:17:28 PM PDT 24
Finished Apr 15 03:17:39 PM PDT 24
Peak memory 204044 kb
Host smart-d8b378ce-debf-4e22-bd07-84b5f7447675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36656
27768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.3665627768
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.3857063316
Short name T1181
Test name
Test status
Simulation time 8386625983 ps
CPU time 8.98 seconds
Started Apr 15 03:17:26 PM PDT 24
Finished Apr 15 03:17:36 PM PDT 24
Peak memory 204060 kb
Host smart-40f00c2c-f4ed-40e2-8a2e-889213f4ab1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38570
63316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.3857063316
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.864566137
Short name T457
Test name
Test status
Simulation time 8371085377 ps
CPU time 7.72 seconds
Started Apr 15 03:17:27 PM PDT 24
Finished Apr 15 03:17:36 PM PDT 24
Peak memory 204076 kb
Host smart-ef1581ba-d9d8-4cba-bd4c-30c511dc35e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86456
6137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.864566137
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3010549227
Short name T528
Test name
Test status
Simulation time 8443011107 ps
CPU time 8.06 seconds
Started Apr 15 03:17:23 PM PDT 24
Finished Apr 15 03:17:31 PM PDT 24
Peak memory 204008 kb
Host smart-309f9a55-c518-44f5-80c8-2fbfc548cb09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30105
49227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3010549227
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.2805830706
Short name T1248
Test name
Test status
Simulation time 8381028257 ps
CPU time 7.55 seconds
Started Apr 15 03:17:28 PM PDT 24
Finished Apr 15 03:17:36 PM PDT 24
Peak memory 204008 kb
Host smart-6deab3d8-a086-49aa-b4ad-37ad6f4ea437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28058
30706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.2805830706
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.3881775175
Short name T1170
Test name
Test status
Simulation time 8384294607 ps
CPU time 7.9 seconds
Started Apr 15 03:17:28 PM PDT 24
Finished Apr 15 03:17:37 PM PDT 24
Peak memory 204016 kb
Host smart-77f86194-7f7c-4234-bd07-dabb11728845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38817
75175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.3881775175
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.1472468673
Short name T1351
Test name
Test status
Simulation time 8480022764 ps
CPU time 8.42 seconds
Started Apr 15 03:17:39 PM PDT 24
Finished Apr 15 03:17:48 PM PDT 24
Peak memory 204036 kb
Host smart-6f10c251-1219-4e9b-bfc1-54c6d8643e67
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1472468673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.1472468673
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.4193435885
Short name T1223
Test name
Test status
Simulation time 8374444439 ps
CPU time 10.31 seconds
Started Apr 15 03:17:41 PM PDT 24
Finished Apr 15 03:17:52 PM PDT 24
Peak memory 204200 kb
Host smart-fe7764cb-b18d-46f9-95eb-528268ce9f2a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4193435885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.4193435885
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.1518183916
Short name T285
Test name
Test status
Simulation time 8467684382 ps
CPU time 11.02 seconds
Started Apr 15 03:17:36 PM PDT 24
Finished Apr 15 03:17:48 PM PDT 24
Peak memory 204044 kb
Host smart-805e3597-1397-4001-bb04-26a94c8646a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15181
83916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.1518183916
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.2368466761
Short name T912
Test name
Test status
Simulation time 8373171489 ps
CPU time 7.51 seconds
Started Apr 15 03:17:31 PM PDT 24
Finished Apr 15 03:17:39 PM PDT 24
Peak memory 203928 kb
Host smart-9cce90bb-e3c0-4d56-940a-908665912efc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23684
66761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.2368466761
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_enable.3723879945
Short name T314
Test name
Test status
Simulation time 8380279184 ps
CPU time 9.08 seconds
Started Apr 15 03:17:31 PM PDT 24
Finished Apr 15 03:17:41 PM PDT 24
Peak memory 204048 kb
Host smart-3703c8c5-bcf9-4ecd-8b06-84f3600f421d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37238
79945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.3723879945
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.1737784084
Short name T1112
Test name
Test status
Simulation time 170749755 ps
CPU time 1.93 seconds
Started Apr 15 03:17:31 PM PDT 24
Finished Apr 15 03:17:34 PM PDT 24
Peak memory 204096 kb
Host smart-7ed3bcce-6f13-415a-ad9e-030b2c4f1b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17377
84084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.1737784084
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.407051665
Short name T351
Test name
Test status
Simulation time 8419004549 ps
CPU time 9.15 seconds
Started Apr 15 03:17:34 PM PDT 24
Finished Apr 15 03:17:44 PM PDT 24
Peak memory 204056 kb
Host smart-2156b965-053c-4f6d-a84b-c6423ce9e110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40705
1665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.407051665
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.1881548996
Short name T179
Test name
Test status
Simulation time 8367155896 ps
CPU time 8.7 seconds
Started Apr 15 03:17:35 PM PDT 24
Finished Apr 15 03:17:44 PM PDT 24
Peak memory 204048 kb
Host smart-e0b6e5aa-32d6-489e-9a10-c938417475db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18815
48996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1881548996
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.3529824237
Short name T1050
Test name
Test status
Simulation time 8386001335 ps
CPU time 7.76 seconds
Started Apr 15 03:17:37 PM PDT 24
Finished Apr 15 03:17:45 PM PDT 24
Peak memory 204020 kb
Host smart-5a6cb588-05fd-48d3-a230-a66834ce1a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35298
24237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3529824237
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2161503247
Short name T1364
Test name
Test status
Simulation time 8412206279 ps
CPU time 8.09 seconds
Started Apr 15 03:17:32 PM PDT 24
Finished Apr 15 03:17:41 PM PDT 24
Peak memory 204052 kb
Host smart-833ccabd-1023-449f-8c54-4c3bf7702af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21615
03247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2161503247
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.2964739308
Short name T836
Test name
Test status
Simulation time 8384735146 ps
CPU time 7.64 seconds
Started Apr 15 03:17:31 PM PDT 24
Finished Apr 15 03:17:39 PM PDT 24
Peak memory 203988 kb
Host smart-c7f5d80f-1f67-411a-a15a-321a9a448598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29647
39308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.2964739308
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1292145373
Short name T1051
Test name
Test status
Simulation time 8426459413 ps
CPU time 8.95 seconds
Started Apr 15 03:17:31 PM PDT 24
Finished Apr 15 03:17:41 PM PDT 24
Peak memory 204048 kb
Host smart-3d5b3cff-1e9b-4fac-8531-78824baaab73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12921
45373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1292145373
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1930035504
Short name T605
Test name
Test status
Simulation time 8390215021 ps
CPU time 7.58 seconds
Started Apr 15 03:17:37 PM PDT 24
Finished Apr 15 03:17:46 PM PDT 24
Peak memory 204024 kb
Host smart-33eb8b6a-d04c-4009-903b-ffdc337a554a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19300
35504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1930035504
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.3488698954
Short name T976
Test name
Test status
Simulation time 8392405934 ps
CPU time 7.89 seconds
Started Apr 15 03:17:36 PM PDT 24
Finished Apr 15 03:17:45 PM PDT 24
Peak memory 204028 kb
Host smart-bd9e4d3a-0b10-492e-8a0a-c989000f2cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34886
98954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.3488698954
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1750831511
Short name T146
Test name
Test status
Simulation time 8380678455 ps
CPU time 8.77 seconds
Started Apr 15 03:17:36 PM PDT 24
Finished Apr 15 03:17:45 PM PDT 24
Peak memory 204048 kb
Host smart-d5b6b3c9-9390-478b-b047-9059b3ba4d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17508
31511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1750831511
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.1561363847
Short name T482
Test name
Test status
Simulation time 8372351436 ps
CPU time 7.69 seconds
Started Apr 15 03:17:39 PM PDT 24
Finished Apr 15 03:17:48 PM PDT 24
Peak memory 204048 kb
Host smart-e7fcb16c-4dc1-4344-93c5-30a6ca65f446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15613
63847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.1561363847
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3133224385
Short name T1264
Test name
Test status
Simulation time 91012447 ps
CPU time 0.69 seconds
Started Apr 15 03:17:35 PM PDT 24
Finished Apr 15 03:17:36 PM PDT 24
Peak memory 203908 kb
Host smart-fe0de601-928e-48f8-9437-f9455d099a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31332
24385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3133224385
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.2352868406
Short name T209
Test name
Test status
Simulation time 31076608950 ps
CPU time 70.33 seconds
Started Apr 15 03:17:32 PM PDT 24
Finished Apr 15 03:18:43 PM PDT 24
Peak memory 204468 kb
Host smart-387c10bc-4b8d-40b6-83b6-a9a5e4e05d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23528
68406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.2352868406
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.46172445
Short name T797
Test name
Test status
Simulation time 8403935137 ps
CPU time 9.19 seconds
Started Apr 15 03:17:32 PM PDT 24
Finished Apr 15 03:17:42 PM PDT 24
Peak memory 204176 kb
Host smart-7229acf3-a5a5-4582-89f9-d1beae947578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46172
445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.46172445
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.825316923
Short name T354
Test name
Test status
Simulation time 8435825245 ps
CPU time 8.98 seconds
Started Apr 15 03:17:32 PM PDT 24
Finished Apr 15 03:17:42 PM PDT 24
Peak memory 204048 kb
Host smart-8be59420-f0e3-400c-be47-177e39781f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82531
6923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.825316923
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.792702763
Short name T764
Test name
Test status
Simulation time 8413660823 ps
CPU time 8.24 seconds
Started Apr 15 03:17:37 PM PDT 24
Finished Apr 15 03:17:46 PM PDT 24
Peak memory 204028 kb
Host smart-f7dc50c6-93fa-4e64-8297-b96deac80a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79270
2763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.792702763
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.1630265640
Short name T150
Test name
Test status
Simulation time 8380729524 ps
CPU time 7.53 seconds
Started Apr 15 03:17:38 PM PDT 24
Finished Apr 15 03:17:46 PM PDT 24
Peak memory 203992 kb
Host smart-ccc5b91b-ef9d-4def-bbf8-9f208e99e0fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16302
65640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.1630265640
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.2799825419
Short name T15
Test name
Test status
Simulation time 8366692243 ps
CPU time 8.01 seconds
Started Apr 15 03:17:38 PM PDT 24
Finished Apr 15 03:17:47 PM PDT 24
Peak memory 204068 kb
Host smart-2bd9bc58-687b-4581-b7e9-3065109f25b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27998
25419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.2799825419
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.1668805250
Short name T502
Test name
Test status
Simulation time 8487275623 ps
CPU time 10.07 seconds
Started Apr 15 03:17:37 PM PDT 24
Finished Apr 15 03:17:48 PM PDT 24
Peak memory 204028 kb
Host smart-8a634e29-6873-4641-9b2d-f771d6364a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16688
05250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1668805250
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.3532975030
Short name T755
Test name
Test status
Simulation time 8417037359 ps
CPU time 7.63 seconds
Started Apr 15 03:17:34 PM PDT 24
Finished Apr 15 03:17:43 PM PDT 24
Peak memory 204048 kb
Host smart-233063bc-6f6e-4835-88ce-a7c0b2d10276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35329
75030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.3532975030
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.2181395134
Short name T810
Test name
Test status
Simulation time 8384214956 ps
CPU time 8.34 seconds
Started Apr 15 03:17:31 PM PDT 24
Finished Apr 15 03:17:39 PM PDT 24
Peak memory 204060 kb
Host smart-07ed6302-3369-49cf-9dad-a384d46528a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21813
95134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.2181395134
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.3866656033
Short name T1219
Test name
Test status
Simulation time 8463798555 ps
CPU time 9.44 seconds
Started Apr 15 03:12:02 PM PDT 24
Finished Apr 15 03:12:12 PM PDT 24
Peak memory 204056 kb
Host smart-f603ee59-9185-4e9d-be9d-6e16d1848cab
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3866656033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.3866656033
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.2617166970
Short name T752
Test name
Test status
Simulation time 8404373649 ps
CPU time 8.46 seconds
Started Apr 15 03:11:55 PM PDT 24
Finished Apr 15 03:12:04 PM PDT 24
Peak memory 204028 kb
Host smart-cfeb240f-84c0-46eb-813d-82188e300db5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2617166970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.2617166970
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.904499704
Short name T375
Test name
Test status
Simulation time 8420842544 ps
CPU time 7.71 seconds
Started Apr 15 03:11:53 PM PDT 24
Finished Apr 15 03:12:01 PM PDT 24
Peak memory 204024 kb
Host smart-ae058370-3b17-43c6-a7e2-ea4d62a67428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90449
9704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.904499704
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.1230784116
Short name T321
Test name
Test status
Simulation time 8375107596 ps
CPU time 7.83 seconds
Started Apr 15 03:11:42 PM PDT 24
Finished Apr 15 03:11:51 PM PDT 24
Peak memory 204024 kb
Host smart-b776e79c-bbc4-4105-b9ab-ba7094ccbf1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12307
84116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.1230784116
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_enable.163073426
Short name T993
Test name
Test status
Simulation time 8378067565 ps
CPU time 9.12 seconds
Started Apr 15 03:11:46 PM PDT 24
Finished Apr 15 03:11:55 PM PDT 24
Peak memory 203996 kb
Host smart-f3baccc6-b51d-4362-aacd-a5555b62bfd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16307
3426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.163073426
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.405105313
Short name T1197
Test name
Test status
Simulation time 88058861 ps
CPU time 1.79 seconds
Started Apr 15 03:11:45 PM PDT 24
Finished Apr 15 03:11:47 PM PDT 24
Peak memory 204180 kb
Host smart-6db6ce95-868c-4be9-b3ec-2ce466f7f34f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40510
5313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.405105313
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.1204209818
Short name T1148
Test name
Test status
Simulation time 8375597544 ps
CPU time 10.06 seconds
Started Apr 15 03:11:55 PM PDT 24
Finished Apr 15 03:12:06 PM PDT 24
Peak memory 204044 kb
Host smart-da234591-b085-43da-85f9-ce0ff15c4da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12042
09818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1204209818
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.673217558
Short name T1003
Test name
Test status
Simulation time 8384471638 ps
CPU time 7.89 seconds
Started Apr 15 03:11:52 PM PDT 24
Finished Apr 15 03:12:00 PM PDT 24
Peak memory 204032 kb
Host smart-74cdd6ce-cfd3-47bf-9faf-f26522e5ee6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67321
7558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.673217558
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.3706629349
Short name T980
Test name
Test status
Simulation time 8480866900 ps
CPU time 7.92 seconds
Started Apr 15 03:11:46 PM PDT 24
Finished Apr 15 03:11:55 PM PDT 24
Peak memory 204016 kb
Host smart-99cf2185-a40b-419e-b26e-d9643de5d5db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37066
29349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.3706629349
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.205305507
Short name T1251
Test name
Test status
Simulation time 8416521215 ps
CPU time 9.5 seconds
Started Apr 15 03:11:45 PM PDT 24
Finished Apr 15 03:11:55 PM PDT 24
Peak memory 204068 kb
Host smart-a529d1dc-ab59-4f96-b818-ce8e624d96c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20530
5507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.205305507
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.110834596
Short name T733
Test name
Test status
Simulation time 8372590253 ps
CPU time 7.52 seconds
Started Apr 15 03:11:46 PM PDT 24
Finished Apr 15 03:11:54 PM PDT 24
Peak memory 203996 kb
Host smart-5c7c85d8-5fa9-447c-8614-c3146bc95037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11083
4596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.110834596
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3062466168
Short name T110
Test name
Test status
Simulation time 8417797126 ps
CPU time 9.65 seconds
Started Apr 15 03:11:46 PM PDT 24
Finished Apr 15 03:11:56 PM PDT 24
Peak memory 204076 kb
Host smart-14fc3a5c-b4f2-4ee6-8d4c-da72294bba8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30624
66168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3062466168
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.194916550
Short name T1182
Test name
Test status
Simulation time 8417979510 ps
CPU time 8.1 seconds
Started Apr 15 03:11:47 PM PDT 24
Finished Apr 15 03:11:55 PM PDT 24
Peak memory 204044 kb
Host smart-700ca29d-deac-4f89-a6b3-9c5973efd0cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19491
6550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.194916550
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.2671413205
Short name T508
Test name
Test status
Simulation time 8410521137 ps
CPU time 8.29 seconds
Started Apr 15 03:11:46 PM PDT 24
Finished Apr 15 03:11:55 PM PDT 24
Peak memory 204020 kb
Host smart-90681f44-023e-4c1f-a433-ee1d2097ed1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26714
13205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.2671413205
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.2050263472
Short name T696
Test name
Test status
Simulation time 8408533009 ps
CPU time 7.93 seconds
Started Apr 15 03:11:49 PM PDT 24
Finished Apr 15 03:11:57 PM PDT 24
Peak memory 204024 kb
Host smart-1bd65e41-e115-4492-9aa3-9f64925a2c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20502
63472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.2050263472
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.60868226
Short name T585
Test name
Test status
Simulation time 8366335612 ps
CPU time 8.32 seconds
Started Apr 15 03:11:50 PM PDT 24
Finished Apr 15 03:11:58 PM PDT 24
Peak memory 203980 kb
Host smart-00a14ccb-01e6-4979-a60a-4be843a03b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60868
226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.60868226
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.996749610
Short name T644
Test name
Test status
Simulation time 32333625 ps
CPU time 0.65 seconds
Started Apr 15 03:11:54 PM PDT 24
Finished Apr 15 03:11:55 PM PDT 24
Peak memory 203932 kb
Host smart-618a7163-8940-4d35-b18e-06bc6d3747a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99674
9610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.996749610
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3361425262
Short name T249
Test name
Test status
Simulation time 29246774354 ps
CPU time 58.18 seconds
Started Apr 15 03:11:44 PM PDT 24
Finished Apr 15 03:12:42 PM PDT 24
Peak memory 204344 kb
Host smart-0ef8731a-6957-4dbc-b3e0-630b987b0622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33614
25262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3361425262
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.2008496805
Short name T726
Test name
Test status
Simulation time 8384645569 ps
CPU time 8.02 seconds
Started Apr 15 03:11:50 PM PDT 24
Finished Apr 15 03:11:58 PM PDT 24
Peak memory 203976 kb
Host smart-20f0ca91-cb62-4ab4-88ae-a04b159935e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20084
96805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.2008496805
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.3157562470
Short name T1061
Test name
Test status
Simulation time 8434991341 ps
CPU time 8.43 seconds
Started Apr 15 03:11:50 PM PDT 24
Finished Apr 15 03:11:59 PM PDT 24
Peak memory 204044 kb
Host smart-d7ea54c3-60de-4699-a7ac-bd986568c1a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31575
62470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.3157562470
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.1590445611
Short name T1349
Test name
Test status
Simulation time 8383954946 ps
CPU time 8 seconds
Started Apr 15 03:11:49 PM PDT 24
Finished Apr 15 03:11:57 PM PDT 24
Peak memory 203984 kb
Host smart-f25b35a3-9e66-4d71-a8f6-48284c58b2aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15904
45611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.1590445611
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.2763142385
Short name T69
Test name
Test status
Simulation time 299353884 ps
CPU time 1.22 seconds
Started Apr 15 03:11:57 PM PDT 24
Finished Apr 15 03:11:59 PM PDT 24
Peak memory 221316 kb
Host smart-18c90ca9-86bb-4945-8944-fa860c30a225
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2763142385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2763142385
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.3349471302
Short name T1096
Test name
Test status
Simulation time 8376274829 ps
CPU time 8.03 seconds
Started Apr 15 03:11:51 PM PDT 24
Finished Apr 15 03:12:00 PM PDT 24
Peak memory 204204 kb
Host smart-2d2bec5f-c04b-4014-a5e1-4a06b1dc035a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33494
71302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.3349471302
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.1349838653
Short name T1320
Test name
Test status
Simulation time 8380876246 ps
CPU time 7.34 seconds
Started Apr 15 03:11:52 PM PDT 24
Finished Apr 15 03:11:59 PM PDT 24
Peak memory 204204 kb
Host smart-f8329ffb-d409-4123-9621-8b66f1655c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13498
38653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.1349838653
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.3319287677
Short name T163
Test name
Test status
Simulation time 8419218143 ps
CPU time 7.99 seconds
Started Apr 15 03:11:41 PM PDT 24
Finished Apr 15 03:11:49 PM PDT 24
Peak memory 204056 kb
Host smart-9c2ec2da-516e-4af3-8aa2-c9690f9fb429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33192
87677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.3319287677
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.585788490
Short name T1355
Test name
Test status
Simulation time 8395394835 ps
CPU time 8.02 seconds
Started Apr 15 03:11:49 PM PDT 24
Finished Apr 15 03:11:58 PM PDT 24
Peak memory 204068 kb
Host smart-9b5dcf74-467f-4842-9602-4262d29e391c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58578
8490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.585788490
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.3118046905
Short name T924
Test name
Test status
Simulation time 8409216155 ps
CPU time 9.99 seconds
Started Apr 15 03:11:54 PM PDT 24
Finished Apr 15 03:12:05 PM PDT 24
Peak memory 204056 kb
Host smart-8dfe0c5e-62e5-449e-8cef-91d6529fa6bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31180
46905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.3118046905
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.4019071496
Short name T1308
Test name
Test status
Simulation time 8468365503 ps
CPU time 8.08 seconds
Started Apr 15 03:17:43 PM PDT 24
Finished Apr 15 03:17:52 PM PDT 24
Peak memory 204052 kb
Host smart-cd5abdfa-40bb-4f00-93eb-9d8d9b81b4ed
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4019071496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.4019071496
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.50473033
Short name T788
Test name
Test status
Simulation time 8378685202 ps
CPU time 8.24 seconds
Started Apr 15 03:17:46 PM PDT 24
Finished Apr 15 03:17:54 PM PDT 24
Peak memory 204048 kb
Host smart-75b8e32b-4c80-4bd7-be55-41b6396d3e0e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=50473033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.50473033
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.3815372077
Short name T991
Test name
Test status
Simulation time 8459793025 ps
CPU time 8.77 seconds
Started Apr 15 03:17:43 PM PDT 24
Finished Apr 15 03:17:53 PM PDT 24
Peak memory 204068 kb
Host smart-70751a2a-d6e9-471a-a0d7-9f21795b772b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38153
72077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.3815372077
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.3138276750
Short name T74
Test name
Test status
Simulation time 8376587757 ps
CPU time 7.78 seconds
Started Apr 15 03:17:40 PM PDT 24
Finished Apr 15 03:17:48 PM PDT 24
Peak memory 203992 kb
Host smart-9f3e365e-518a-476b-aeaf-b7b56ca2fd47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31382
76750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.3138276750
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_enable.812982260
Short name T531
Test name
Test status
Simulation time 8404893109 ps
CPU time 8.78 seconds
Started Apr 15 03:17:39 PM PDT 24
Finished Apr 15 03:17:48 PM PDT 24
Peak memory 204064 kb
Host smart-b3b4a1e2-43ed-47e9-8a45-7b7702e05b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81298
2260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.812982260
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.3566786574
Short name T421
Test name
Test status
Simulation time 207027412 ps
CPU time 2.16 seconds
Started Apr 15 03:17:40 PM PDT 24
Finished Apr 15 03:17:43 PM PDT 24
Peak memory 204204 kb
Host smart-1e3f5a09-88b0-4cb0-9e52-019933b5f6a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35667
86574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.3566786574
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.3983344550
Short name T519
Test name
Test status
Simulation time 8407340251 ps
CPU time 8.18 seconds
Started Apr 15 03:17:57 PM PDT 24
Finished Apr 15 03:18:05 PM PDT 24
Peak memory 203984 kb
Host smart-9c99aee6-5164-4abf-883a-3015632f6259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39833
44550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.3983344550
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.3593347099
Short name T738
Test name
Test status
Simulation time 8367437760 ps
CPU time 7.8 seconds
Started Apr 15 03:17:44 PM PDT 24
Finished Apr 15 03:17:52 PM PDT 24
Peak memory 204032 kb
Host smart-4dba14bd-f220-4a63-a596-57ad4f10c49f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35933
47099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.3593347099
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.758261867
Short name T650
Test name
Test status
Simulation time 8434147325 ps
CPU time 7.68 seconds
Started Apr 15 03:17:43 PM PDT 24
Finished Apr 15 03:17:52 PM PDT 24
Peak memory 204024 kb
Host smart-9cac0698-ad97-4375-8d83-d33d291025d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75826
1867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.758261867
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.1708036608
Short name T322
Test name
Test status
Simulation time 8434062629 ps
CPU time 9.73 seconds
Started Apr 15 03:17:43 PM PDT 24
Finished Apr 15 03:17:54 PM PDT 24
Peak memory 204024 kb
Host smart-a0acdfe4-c648-49f4-961b-bccd1f7b37df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17080
36608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1708036608
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3951303044
Short name T675
Test name
Test status
Simulation time 8367062098 ps
CPU time 9.97 seconds
Started Apr 15 03:17:39 PM PDT 24
Finished Apr 15 03:17:49 PM PDT 24
Peak memory 204036 kb
Host smart-cf55b782-3619-4f6d-bbb4-56f38046d451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39513
03044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3951303044
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.27849897
Short name T99
Test name
Test status
Simulation time 8408573244 ps
CPU time 7.79 seconds
Started Apr 15 03:17:56 PM PDT 24
Finished Apr 15 03:18:05 PM PDT 24
Peak memory 203992 kb
Host smart-efa98500-9e8b-4292-b107-a8fef556625c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27849
897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.27849897
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.1024579564
Short name T73
Test name
Test status
Simulation time 8389234569 ps
CPU time 8.41 seconds
Started Apr 15 03:17:56 PM PDT 24
Finished Apr 15 03:18:05 PM PDT 24
Peak memory 203992 kb
Host smart-2825fec4-0b35-4fbe-ad88-aa401354bede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10245
79564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.1024579564
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.877746430
Short name T566
Test name
Test status
Simulation time 8411554368 ps
CPU time 8.13 seconds
Started Apr 15 03:17:39 PM PDT 24
Finished Apr 15 03:17:48 PM PDT 24
Peak memory 204032 kb
Host smart-9e2bbf21-aa8d-40e6-9e3c-d90c7529bbf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87774
6430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.877746430
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.583287553
Short name T893
Test name
Test status
Simulation time 8401679167 ps
CPU time 8.1 seconds
Started Apr 15 03:17:42 PM PDT 24
Finished Apr 15 03:17:51 PM PDT 24
Peak memory 204024 kb
Host smart-a70aff5e-9482-46cd-a01a-49be95ad1b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58328
7553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.583287553
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.3624435387
Short name T589
Test name
Test status
Simulation time 8372077533 ps
CPU time 7.77 seconds
Started Apr 15 03:17:43 PM PDT 24
Finished Apr 15 03:17:51 PM PDT 24
Peak memory 204024 kb
Host smart-86738329-2c9d-4b7e-914b-b0932aa265ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36244
35387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.3624435387
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.2319125048
Short name T512
Test name
Test status
Simulation time 36596087 ps
CPU time 0.64 seconds
Started Apr 15 03:17:44 PM PDT 24
Finished Apr 15 03:17:45 PM PDT 24
Peak memory 203924 kb
Host smart-28ebf408-683f-4a06-a248-d74e754098a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23191
25048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.2319125048
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.1995287933
Short name T1175
Test name
Test status
Simulation time 29813557470 ps
CPU time 64.97 seconds
Started Apr 15 03:17:38 PM PDT 24
Finished Apr 15 03:18:44 PM PDT 24
Peak memory 204344 kb
Host smart-937d2245-c793-4854-a4b7-5770bdb920bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19952
87933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.1995287933
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.3248569800
Short name T945
Test name
Test status
Simulation time 8401821528 ps
CPU time 7.66 seconds
Started Apr 15 03:17:40 PM PDT 24
Finished Apr 15 03:17:48 PM PDT 24
Peak memory 203996 kb
Host smart-6e3d08e2-cace-4309-bb4d-f7eea461ff5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32485
69800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.3248569800
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.3938258434
Short name T667
Test name
Test status
Simulation time 8460386719 ps
CPU time 9.95 seconds
Started Apr 15 03:17:42 PM PDT 24
Finished Apr 15 03:17:52 PM PDT 24
Peak memory 203984 kb
Host smart-4fef1a0a-e3e0-407f-b1f2-e0b253b0a76d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39382
58434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.3938258434
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.3881581254
Short name T388
Test name
Test status
Simulation time 8438814423 ps
CPU time 9.75 seconds
Started Apr 15 03:17:57 PM PDT 24
Finished Apr 15 03:18:07 PM PDT 24
Peak memory 203992 kb
Host smart-dce5dfc8-cead-4b8c-a5a4-70ea1424d66c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38815
81254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.3881581254
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.1639735387
Short name T1126
Test name
Test status
Simulation time 8373602430 ps
CPU time 8.12 seconds
Started Apr 15 03:17:49 PM PDT 24
Finished Apr 15 03:17:58 PM PDT 24
Peak memory 203976 kb
Host smart-77debeaa-0653-4742-ac4c-4782f98293ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16397
35387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.1639735387
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.2316660722
Short name T966
Test name
Test status
Simulation time 8369847791 ps
CPU time 7.56 seconds
Started Apr 15 03:17:42 PM PDT 24
Finished Apr 15 03:17:50 PM PDT 24
Peak memory 204052 kb
Host smart-e0bf1c1d-815e-4e73-b5e7-639b2501d6b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23166
60722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.2316660722
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.3106716032
Short name T116
Test name
Test status
Simulation time 8519674107 ps
CPU time 8.89 seconds
Started Apr 15 03:17:40 PM PDT 24
Finished Apr 15 03:17:49 PM PDT 24
Peak memory 204068 kb
Host smart-65b2bcae-4e0f-4148-8aa8-8927e6169b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31067
16032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.3106716032
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.899454447
Short name T1215
Test name
Test status
Simulation time 8425868736 ps
CPU time 9.55 seconds
Started Apr 15 03:17:57 PM PDT 24
Finished Apr 15 03:18:07 PM PDT 24
Peak memory 203988 kb
Host smart-9637aeb6-c72b-4ae7-b91a-3f27684735b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89945
4447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.899454447
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.135927232
Short name T695
Test name
Test status
Simulation time 8399927129 ps
CPU time 7.86 seconds
Started Apr 15 03:17:43 PM PDT 24
Finished Apr 15 03:17:52 PM PDT 24
Peak memory 204048 kb
Host smart-c8d23395-08c8-44d2-b1d7-1299132d36db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13592
7232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.135927232
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.3062424323
Short name T1156
Test name
Test status
Simulation time 8468353335 ps
CPU time 9.46 seconds
Started Apr 15 03:17:52 PM PDT 24
Finished Apr 15 03:18:02 PM PDT 24
Peak memory 203932 kb
Host smart-54b2b4be-f41d-4551-9122-04e49a1ce17e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3062424323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.3062424323
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.1184259646
Short name T411
Test name
Test status
Simulation time 8386865755 ps
CPU time 7.89 seconds
Started Apr 15 03:17:51 PM PDT 24
Finished Apr 15 03:18:00 PM PDT 24
Peak memory 204000 kb
Host smart-6f9df582-ed98-4da5-9bce-567da2c808e7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1184259646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.1184259646
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.random_length_in_trans.1829483423
Short name T1321
Test name
Test status
Simulation time 8384411715 ps
CPU time 8.33 seconds
Started Apr 15 03:17:54 PM PDT 24
Finished Apr 15 03:18:03 PM PDT 24
Peak memory 204048 kb
Host smart-7276c302-2d10-47f2-ae5b-6024731d6846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18294
83423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.1829483423
Directory /workspace/41.random_length_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2555745338
Short name T407
Test name
Test status
Simulation time 8436129926 ps
CPU time 8.13 seconds
Started Apr 15 03:17:43 PM PDT 24
Finished Apr 15 03:17:51 PM PDT 24
Peak memory 204028 kb
Host smart-0d460336-0156-41a8-b3b3-b6cbc6c05d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25557
45338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2555745338
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_enable.3272971682
Short name T1334
Test name
Test status
Simulation time 8374714426 ps
CPU time 7.78 seconds
Started Apr 15 03:17:57 PM PDT 24
Finished Apr 15 03:18:05 PM PDT 24
Peak memory 203984 kb
Host smart-978f7b66-6ece-4d45-9299-7283c81ff169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32729
71682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3272971682
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.516475914
Short name T791
Test name
Test status
Simulation time 235539658 ps
CPU time 2.37 seconds
Started Apr 15 03:17:56 PM PDT 24
Finished Apr 15 03:18:00 PM PDT 24
Peak memory 204124 kb
Host smart-3f20fdc1-c55b-428d-b930-c18f7d550dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51647
5914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.516475914
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.648309904
Short name T131
Test name
Test status
Simulation time 8424962346 ps
CPU time 7.8 seconds
Started Apr 15 03:17:54 PM PDT 24
Finished Apr 15 03:18:02 PM PDT 24
Peak memory 204028 kb
Host smart-b79a24b8-2eff-4d63-8d8e-665e637e4f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64830
9904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.648309904
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.3285448368
Short name T1307
Test name
Test status
Simulation time 8415950968 ps
CPU time 8.68 seconds
Started Apr 15 03:17:54 PM PDT 24
Finished Apr 15 03:18:03 PM PDT 24
Peak memory 204068 kb
Host smart-27d5d1d8-5e42-4888-ac1c-3b1188307a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32854
48368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.3285448368
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.979849281
Short name T875
Test name
Test status
Simulation time 8462745442 ps
CPU time 9.14 seconds
Started Apr 15 03:17:56 PM PDT 24
Finished Apr 15 03:18:06 PM PDT 24
Peak memory 203996 kb
Host smart-fc606bf9-da9c-4c13-ad30-25c66c264b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97984
9281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.979849281
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.3135829536
Short name T305
Test name
Test status
Simulation time 8418134369 ps
CPU time 8.21 seconds
Started Apr 15 03:17:44 PM PDT 24
Finished Apr 15 03:17:53 PM PDT 24
Peak memory 204064 kb
Host smart-a26e2a5d-8c58-4555-81e1-fb3997176b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31358
29536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.3135829536
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.715078849
Short name T487
Test name
Test status
Simulation time 8372367369 ps
CPU time 10.11 seconds
Started Apr 15 03:17:43 PM PDT 24
Finished Apr 15 03:17:54 PM PDT 24
Peak memory 204064 kb
Host smart-1cc657e5-e29f-40d4-b65f-8bd49773ce68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71507
8849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.715078849
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.3048800423
Short name T86
Test name
Test status
Simulation time 8400147921 ps
CPU time 8.56 seconds
Started Apr 15 03:17:47 PM PDT 24
Finished Apr 15 03:17:56 PM PDT 24
Peak memory 203928 kb
Host smart-6ae923ac-ff2f-4a2f-ae95-c6af645a23c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30488
00423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3048800423
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.1317665939
Short name T317
Test name
Test status
Simulation time 8443498314 ps
CPU time 10.29 seconds
Started Apr 15 03:17:48 PM PDT 24
Finished Apr 15 03:17:59 PM PDT 24
Peak memory 204068 kb
Host smart-8ea11cac-2981-4c06-a83b-5ac7abd073b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13176
65939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.1317665939
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.1958090092
Short name T29
Test name
Test status
Simulation time 8398521126 ps
CPU time 7.63 seconds
Started Apr 15 03:17:50 PM PDT 24
Finished Apr 15 03:17:58 PM PDT 24
Peak memory 204052 kb
Host smart-9f9c2c7f-9bf3-4ad5-8746-39a8fd2b41bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19580
90092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.1958090092
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.2880460234
Short name T1207
Test name
Test status
Simulation time 8413333795 ps
CPU time 8.16 seconds
Started Apr 15 03:17:54 PM PDT 24
Finished Apr 15 03:18:03 PM PDT 24
Peak memory 204044 kb
Host smart-75c60adf-d5b6-47f6-a27e-8822325081a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28804
60234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.2880460234
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.3310758289
Short name T337
Test name
Test status
Simulation time 8386025677 ps
CPU time 8.94 seconds
Started Apr 15 03:17:48 PM PDT 24
Finished Apr 15 03:17:58 PM PDT 24
Peak memory 203980 kb
Host smart-f5a14aa5-04aa-485d-bee8-312948126af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33107
58289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.3310758289
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3995621506
Short name T736
Test name
Test status
Simulation time 67948327 ps
CPU time 0.7 seconds
Started Apr 15 03:17:55 PM PDT 24
Finished Apr 15 03:17:57 PM PDT 24
Peak memory 203944 kb
Host smart-5d5c1840-eb2c-442e-a269-74e108d746db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39956
21506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3995621506
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.1916925397
Short name T1242
Test name
Test status
Simulation time 26733884625 ps
CPU time 55.66 seconds
Started Apr 15 03:17:49 PM PDT 24
Finished Apr 15 03:18:45 PM PDT 24
Peak memory 204348 kb
Host smart-8845ebcd-8c74-4117-9cdb-4101cf441e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19169
25397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.1916925397
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.4023514495
Short name T223
Test name
Test status
Simulation time 8420339537 ps
CPU time 10.07 seconds
Started Apr 15 03:17:46 PM PDT 24
Finished Apr 15 03:17:56 PM PDT 24
Peak memory 204080 kb
Host smart-318cef25-2e13-4a01-893c-423aad716f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40235
14495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.4023514495
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.1253033145
Short name T1339
Test name
Test status
Simulation time 8387801310 ps
CPU time 10 seconds
Started Apr 15 03:17:47 PM PDT 24
Finished Apr 15 03:17:58 PM PDT 24
Peak memory 204024 kb
Host smart-4d0e80e5-37b6-47fe-97dc-35649b479458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12530
33145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.1253033145
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.216515250
Short name T1053
Test name
Test status
Simulation time 8402304585 ps
CPU time 7.85 seconds
Started Apr 15 03:17:47 PM PDT 24
Finished Apr 15 03:17:56 PM PDT 24
Peak memory 204072 kb
Host smart-cf38dd01-b36e-49ed-a394-5d1c03e86c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21651
5250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.216515250
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.3002057028
Short name T856
Test name
Test status
Simulation time 8382770490 ps
CPU time 7.91 seconds
Started Apr 15 03:17:48 PM PDT 24
Finished Apr 15 03:17:57 PM PDT 24
Peak memory 203980 kb
Host smart-3c9bf631-3430-4497-bcaf-547a2cb0bb2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30020
57028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.3002057028
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3068734177
Short name T626
Test name
Test status
Simulation time 8379449818 ps
CPU time 7.61 seconds
Started Apr 15 03:17:47 PM PDT 24
Finished Apr 15 03:17:56 PM PDT 24
Peak memory 204028 kb
Host smart-a8f6a92e-093e-46a3-936e-2dc4ba74070e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30687
34177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3068734177
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.3988280058
Short name T1158
Test name
Test status
Simulation time 8421177063 ps
CPU time 7.59 seconds
Started Apr 15 03:17:43 PM PDT 24
Finished Apr 15 03:17:52 PM PDT 24
Peak memory 204052 kb
Host smart-a5e89cf6-e452-4534-8781-74b6bc507cc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39882
80058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3988280058
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.193186888
Short name T649
Test name
Test status
Simulation time 8410144098 ps
CPU time 8.31 seconds
Started Apr 15 03:17:47 PM PDT 24
Finished Apr 15 03:17:55 PM PDT 24
Peak memory 204064 kb
Host smart-567c6685-3548-4a14-88f0-3b1176bebb80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19318
6888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.193186888
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.219571403
Short name T798
Test name
Test status
Simulation time 8403499621 ps
CPU time 8.16 seconds
Started Apr 15 03:17:47 PM PDT 24
Finished Apr 15 03:17:56 PM PDT 24
Peak memory 204048 kb
Host smart-ba47fa1e-de5f-4aec-ae8f-458a15a6d483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21957
1403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.219571403
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.716300331
Short name T1363
Test name
Test status
Simulation time 8475711503 ps
CPU time 8.46 seconds
Started Apr 15 03:17:53 PM PDT 24
Finished Apr 15 03:18:03 PM PDT 24
Peak memory 204032 kb
Host smart-81db306e-5046-4802-90ff-d05ac0017fd0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=716300331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.716300331
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.3658678762
Short name T684
Test name
Test status
Simulation time 8376734780 ps
CPU time 8.6 seconds
Started Apr 15 03:17:57 PM PDT 24
Finished Apr 15 03:18:06 PM PDT 24
Peak memory 204068 kb
Host smart-fe1fb8c5-a394-4e76-926c-c421146e659d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3658678762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.3658678762
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.2448184105
Short name T756
Test name
Test status
Simulation time 8400277904 ps
CPU time 8.14 seconds
Started Apr 15 03:17:57 PM PDT 24
Finished Apr 15 03:18:06 PM PDT 24
Peak memory 204064 kb
Host smart-cd342532-b24a-4048-8c32-0ec1aa1d276f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24481
84105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.2448184105
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2765571840
Short name T549
Test name
Test status
Simulation time 8377348770 ps
CPU time 8.19 seconds
Started Apr 15 03:17:54 PM PDT 24
Finished Apr 15 03:18:03 PM PDT 24
Peak memory 204060 kb
Host smart-85f4b32d-0f95-49a8-ac5e-e499ec4bdc13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27655
71840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2765571840
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_enable.3081852697
Short name T691
Test name
Test status
Simulation time 8375183635 ps
CPU time 7.87 seconds
Started Apr 15 03:17:52 PM PDT 24
Finished Apr 15 03:18:00 PM PDT 24
Peak memory 203876 kb
Host smart-ada7579d-a97e-462a-ac28-fb59135cc0f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30818
52697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.3081852697
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3447671482
Short name T1133
Test name
Test status
Simulation time 327580605 ps
CPU time 2.49 seconds
Started Apr 15 03:17:53 PM PDT 24
Finished Apr 15 03:17:56 PM PDT 24
Peak memory 204140 kb
Host smart-a478267c-d1af-451c-9168-1acae27b7298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34476
71482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3447671482
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.668569232
Short name T563
Test name
Test status
Simulation time 8445174305 ps
CPU time 9.42 seconds
Started Apr 15 03:17:56 PM PDT 24
Finished Apr 15 03:18:06 PM PDT 24
Peak memory 204056 kb
Host smart-80340342-1285-4086-b61d-9bd38896d038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66856
9232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.668569232
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.2880641074
Short name T175
Test name
Test status
Simulation time 8371275049 ps
CPU time 8.13 seconds
Started Apr 15 03:17:58 PM PDT 24
Finished Apr 15 03:18:07 PM PDT 24
Peak memory 204048 kb
Host smart-e4700089-4b3a-482f-ab01-20879d14bda0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28806
41074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.2880641074
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.2226420803
Short name T303
Test name
Test status
Simulation time 8469898153 ps
CPU time 7.97 seconds
Started Apr 15 03:17:54 PM PDT 24
Finished Apr 15 03:18:03 PM PDT 24
Peak memory 204060 kb
Host smart-47cbe7bb-cf07-4cf6-b26f-96fb0972976f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22264
20803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.2226420803
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.3122757266
Short name T1285
Test name
Test status
Simulation time 8426222218 ps
CPU time 9.27 seconds
Started Apr 15 03:17:52 PM PDT 24
Finished Apr 15 03:18:02 PM PDT 24
Peak memory 204028 kb
Host smart-a7cd1727-5314-46c5-983f-1464ffe39c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31227
57266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.3122757266
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.2772760463
Short name T1011
Test name
Test status
Simulation time 8405485039 ps
CPU time 7.75 seconds
Started Apr 15 03:17:56 PM PDT 24
Finished Apr 15 03:18:04 PM PDT 24
Peak memory 204032 kb
Host smart-5ef1a5ee-b2db-47df-a325-16c954f9e9d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27727
60463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.2772760463
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.2704968697
Short name T1362
Test name
Test status
Simulation time 8427863316 ps
CPU time 9.97 seconds
Started Apr 15 03:17:53 PM PDT 24
Finished Apr 15 03:18:03 PM PDT 24
Peak memory 204008 kb
Host smart-fc9fd017-7ab0-4209-a3e9-55621727f4e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27049
68697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.2704968697
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.3024448280
Short name T1227
Test name
Test status
Simulation time 8389804600 ps
CPU time 8.16 seconds
Started Apr 15 03:17:58 PM PDT 24
Finished Apr 15 03:18:06 PM PDT 24
Peak memory 204008 kb
Host smart-2b2f5e99-ff8b-4f5a-8169-2984c2ecbae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30244
48280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3024448280
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.2423103522
Short name T376
Test name
Test status
Simulation time 8419104277 ps
CPU time 8.87 seconds
Started Apr 15 03:17:55 PM PDT 24
Finished Apr 15 03:18:04 PM PDT 24
Peak memory 204060 kb
Host smart-e3165bb8-f771-4287-b4d1-a713ebdbe91f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24231
03522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.2423103522
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.2124238064
Short name T1298
Test name
Test status
Simulation time 8382900316 ps
CPU time 8.14 seconds
Started Apr 15 03:17:55 PM PDT 24
Finished Apr 15 03:18:04 PM PDT 24
Peak memory 204008 kb
Host smart-c5c2e2cc-9cbb-40f7-ab3f-6ce5eedfece1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21242
38064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.2124238064
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.1917717898
Short name T753
Test name
Test status
Simulation time 8371859725 ps
CPU time 8.35 seconds
Started Apr 15 03:17:55 PM PDT 24
Finished Apr 15 03:18:04 PM PDT 24
Peak memory 204052 kb
Host smart-82f4dec5-5b6e-494f-9065-50292ef09b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19177
17898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.1917717898
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.4135493751
Short name T1368
Test name
Test status
Simulation time 31433234 ps
CPU time 0.68 seconds
Started Apr 15 03:17:57 PM PDT 24
Finished Apr 15 03:17:59 PM PDT 24
Peak memory 203848 kb
Host smart-8e8d68a3-4dd5-4fde-8a0f-d1ccdc2772b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41354
93751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.4135493751
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.2895590126
Short name T1270
Test name
Test status
Simulation time 29024784017 ps
CPU time 56.3 seconds
Started Apr 15 03:17:53 PM PDT 24
Finished Apr 15 03:18:50 PM PDT 24
Peak memory 204344 kb
Host smart-99fe7aac-96ae-4733-a657-5b42b1035129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28955
90126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.2895590126
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.212095974
Short name T204
Test name
Test status
Simulation time 8392511960 ps
CPU time 9.48 seconds
Started Apr 15 03:17:53 PM PDT 24
Finished Apr 15 03:18:03 PM PDT 24
Peak memory 204032 kb
Host smart-b1bbc295-3a3d-46d8-807c-a5bcbb8bf443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21209
5974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.212095974
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.947501643
Short name T495
Test name
Test status
Simulation time 8423700700 ps
CPU time 7.77 seconds
Started Apr 15 03:17:54 PM PDT 24
Finished Apr 15 03:18:02 PM PDT 24
Peak memory 204056 kb
Host smart-58a12889-1754-464c-a5eb-e99b85322f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94750
1643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.947501643
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.1769381231
Short name T1203
Test name
Test status
Simulation time 8409884057 ps
CPU time 8.42 seconds
Started Apr 15 03:17:52 PM PDT 24
Finished Apr 15 03:18:01 PM PDT 24
Peak memory 204064 kb
Host smart-00c5d16f-f98a-4e73-b928-a75fb19dbde1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17693
81231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.1769381231
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.1045173340
Short name T674
Test name
Test status
Simulation time 8392410084 ps
CPU time 8.27 seconds
Started Apr 15 03:17:55 PM PDT 24
Finished Apr 15 03:18:05 PM PDT 24
Peak memory 204040 kb
Host smart-a1f9e242-8f20-4e18-8b44-b089679b8baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10451
73340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.1045173340
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2820159380
Short name T774
Test name
Test status
Simulation time 8423311280 ps
CPU time 8.05 seconds
Started Apr 15 03:17:56 PM PDT 24
Finished Apr 15 03:18:05 PM PDT 24
Peak memory 204024 kb
Host smart-1c8e1561-762e-42ba-ba8d-260553210aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28201
59380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2820159380
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.1881179758
Short name T1276
Test name
Test status
Simulation time 8438570826 ps
CPU time 8.25 seconds
Started Apr 15 03:17:58 PM PDT 24
Finished Apr 15 03:18:07 PM PDT 24
Peak memory 204008 kb
Host smart-4cb131f7-478f-4a80-8ead-a33dd6a4a16a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18811
79758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.1881179758
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.3410151208
Short name T115
Test name
Test status
Simulation time 8421036210 ps
CPU time 8.85 seconds
Started Apr 15 03:17:58 PM PDT 24
Finished Apr 15 03:18:07 PM PDT 24
Peak memory 204004 kb
Host smart-989298d2-bfa6-474c-8216-964c5ea32f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34101
51208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.3410151208
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.3239666547
Short name T439
Test name
Test status
Simulation time 8400191271 ps
CPU time 8.3 seconds
Started Apr 15 03:17:54 PM PDT 24
Finished Apr 15 03:18:03 PM PDT 24
Peak memory 204060 kb
Host smart-79f9b2f1-1fd7-4386-974c-eabd67fe0b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32396
66547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.3239666547
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.2951843095
Short name T505
Test name
Test status
Simulation time 8463356182 ps
CPU time 7.96 seconds
Started Apr 15 03:18:05 PM PDT 24
Finished Apr 15 03:18:13 PM PDT 24
Peak memory 204072 kb
Host smart-50a7dac4-0de2-47eb-9341-8149dd5b0fae
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2951843095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.2951843095
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.1699925335
Short name T425
Test name
Test status
Simulation time 8449715259 ps
CPU time 8.44 seconds
Started Apr 15 03:18:08 PM PDT 24
Finished Apr 15 03:18:17 PM PDT 24
Peak memory 204048 kb
Host smart-95f5b1ef-78e5-400e-ba8b-43c87ffec572
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1699925335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.1699925335
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.2971311354
Short name T1180
Test name
Test status
Simulation time 8393170050 ps
CPU time 8.87 seconds
Started Apr 15 03:18:02 PM PDT 24
Finished Apr 15 03:18:11 PM PDT 24
Peak memory 204200 kb
Host smart-8f27e15d-0232-4ecb-98ea-ed45fe5e1172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29713
11354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.2971311354
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.3158814426
Short name T1220
Test name
Test status
Simulation time 8375852249 ps
CPU time 8.73 seconds
Started Apr 15 03:17:56 PM PDT 24
Finished Apr 15 03:18:05 PM PDT 24
Peak memory 204024 kb
Host smart-8945f717-a7e1-43ff-bbde-773cd6bfa193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31588
14426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.3158814426
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_enable.1413505156
Short name T1121
Test name
Test status
Simulation time 8386847905 ps
CPU time 7.69 seconds
Started Apr 15 03:18:06 PM PDT 24
Finished Apr 15 03:18:14 PM PDT 24
Peak memory 204048 kb
Host smart-715a763d-9096-43c2-a4d5-8ca5a470dc4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14135
05156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1413505156
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.768475659
Short name T1141
Test name
Test status
Simulation time 209203627 ps
CPU time 2.2 seconds
Started Apr 15 03:18:00 PM PDT 24
Finished Apr 15 03:18:03 PM PDT 24
Peak memory 204204 kb
Host smart-079b5c66-8188-47cc-bce8-866c407e0e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76847
5659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.768475659
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.4042305790
Short name T1072
Test name
Test status
Simulation time 8472909512 ps
CPU time 7.54 seconds
Started Apr 15 03:18:04 PM PDT 24
Finished Apr 15 03:18:12 PM PDT 24
Peak memory 204060 kb
Host smart-2f24a7da-1dc4-45cb-b586-aeae3afb0c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40423
05790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.4042305790
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.1271062593
Short name T794
Test name
Test status
Simulation time 8366879894 ps
CPU time 8.45 seconds
Started Apr 15 03:18:04 PM PDT 24
Finished Apr 15 03:18:13 PM PDT 24
Peak memory 203872 kb
Host smart-7bf24fe7-469c-48cd-9bcf-b942895506e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12710
62593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.1271062593
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1800971117
Short name T1235
Test name
Test status
Simulation time 8439051817 ps
CPU time 8.03 seconds
Started Apr 15 03:18:01 PM PDT 24
Finished Apr 15 03:18:09 PM PDT 24
Peak memory 203928 kb
Host smart-6416c923-dbc9-403c-8020-9fea4fb31b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18009
71117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1800971117
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.3547603994
Short name T1085
Test name
Test status
Simulation time 8412999848 ps
CPU time 8.86 seconds
Started Apr 15 03:18:06 PM PDT 24
Finished Apr 15 03:18:15 PM PDT 24
Peak memory 204056 kb
Host smart-cdd6d323-4dcc-4800-b469-5a8d185393b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35476
03994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.3547603994
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.1318587781
Short name T823
Test name
Test status
Simulation time 8372131115 ps
CPU time 9.84 seconds
Started Apr 15 03:18:01 PM PDT 24
Finished Apr 15 03:18:11 PM PDT 24
Peak memory 204208 kb
Host smart-43b175f4-2cf4-40a4-bea9-6d4ad9078884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13185
87781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1318587781
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.4220826753
Short name T974
Test name
Test status
Simulation time 8435226318 ps
CPU time 8.01 seconds
Started Apr 15 03:17:59 PM PDT 24
Finished Apr 15 03:18:07 PM PDT 24
Peak memory 204044 kb
Host smart-215f67d1-087d-4280-a6be-d4c30c877dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42208
26753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.4220826753
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.112425432
Short name T499
Test name
Test status
Simulation time 8392485164 ps
CPU time 8.35 seconds
Started Apr 15 03:18:03 PM PDT 24
Finished Apr 15 03:18:12 PM PDT 24
Peak memory 204044 kb
Host smart-222d77d9-94a2-4411-80c6-2229e4eef63f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11242
5432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.112425432
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.2779800171
Short name T857
Test name
Test status
Simulation time 8403094597 ps
CPU time 8.04 seconds
Started Apr 15 03:18:03 PM PDT 24
Finished Apr 15 03:18:12 PM PDT 24
Peak memory 204044 kb
Host smart-e6ec8d0f-9dda-449f-8ee5-22cbef642bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27798
00171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.2779800171
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.3546813835
Short name T793
Test name
Test status
Simulation time 8404335124 ps
CPU time 8.02 seconds
Started Apr 15 03:18:02 PM PDT 24
Finished Apr 15 03:18:11 PM PDT 24
Peak memory 203996 kb
Host smart-6ad11ad5-d1d6-4bd7-ad9b-0e633ba3503e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35468
13835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.3546813835
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.4013861075
Short name T809
Test name
Test status
Simulation time 8368679876 ps
CPU time 8.28 seconds
Started Apr 15 03:18:06 PM PDT 24
Finished Apr 15 03:18:15 PM PDT 24
Peak memory 204052 kb
Host smart-c89f4163-0eb3-4be0-a50b-0d8a30fa8838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40138
61075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.4013861075
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.2183789836
Short name T661
Test name
Test status
Simulation time 49542185 ps
CPU time 0.69 seconds
Started Apr 15 03:18:03 PM PDT 24
Finished Apr 15 03:18:04 PM PDT 24
Peak memory 203932 kb
Host smart-3c3a771b-e375-44be-9925-b6c5c8d2e558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21837
89836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.2183789836
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.443448941
Short name T1259
Test name
Test status
Simulation time 26630055952 ps
CPU time 52.87 seconds
Started Apr 15 03:17:58 PM PDT 24
Finished Apr 15 03:18:52 PM PDT 24
Peak memory 204272 kb
Host smart-2a908afc-1f1e-4438-bf8c-6e7f2ca3ec98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44344
8941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.443448941
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.3993150141
Short name T610
Test name
Test status
Simulation time 8394047517 ps
CPU time 8.42 seconds
Started Apr 15 03:18:03 PM PDT 24
Finished Apr 15 03:18:12 PM PDT 24
Peak memory 204044 kb
Host smart-50100025-5a4c-466d-97e2-0ed0bbfb0f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39931
50141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.3993150141
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3271666166
Short name T122
Test name
Test status
Simulation time 8444421967 ps
CPU time 8.51 seconds
Started Apr 15 03:18:01 PM PDT 24
Finished Apr 15 03:18:10 PM PDT 24
Peak memory 204040 kb
Host smart-46f2a58b-a139-4b40-b1e7-4320ac949744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32716
66166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3271666166
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.2195883734
Short name T1357
Test name
Test status
Simulation time 8433473248 ps
CPU time 7.7 seconds
Started Apr 15 03:17:58 PM PDT 24
Finished Apr 15 03:18:07 PM PDT 24
Peak memory 204044 kb
Host smart-f7e7686b-a3cc-4bf1-a18a-e6862f88f9a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21958
83734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.2195883734
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.4172733913
Short name T1301
Test name
Test status
Simulation time 8381714706 ps
CPU time 7.66 seconds
Started Apr 15 03:18:04 PM PDT 24
Finished Apr 15 03:18:12 PM PDT 24
Peak memory 204052 kb
Host smart-a71aeaf1-a1e9-4d0f-9909-6221de66f2cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41727
33913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.4172733913
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3406370967
Short name T1142
Test name
Test status
Simulation time 8374411579 ps
CPU time 8.73 seconds
Started Apr 15 03:18:03 PM PDT 24
Finished Apr 15 03:18:13 PM PDT 24
Peak memory 204040 kb
Host smart-25f8d81a-329c-49d8-8ad6-5fd815720a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34063
70967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3406370967
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1484512315
Short name T129
Test name
Test status
Simulation time 8462651497 ps
CPU time 8.38 seconds
Started Apr 15 03:17:57 PM PDT 24
Finished Apr 15 03:18:06 PM PDT 24
Peak memory 204084 kb
Host smart-3af4c7dd-111b-45e9-926e-fe897f2f1c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14845
12315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1484512315
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.473267470
Short name T1291
Test name
Test status
Simulation time 8380725360 ps
CPU time 10.32 seconds
Started Apr 15 03:18:03 PM PDT 24
Finished Apr 15 03:18:14 PM PDT 24
Peak memory 204060 kb
Host smart-e0dfd007-1140-4ff7-8945-e99a04ea144f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47326
7470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.473267470
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.2516743190
Short name T1214
Test name
Test status
Simulation time 8401816171 ps
CPU time 9.2 seconds
Started Apr 15 03:18:00 PM PDT 24
Finished Apr 15 03:18:09 PM PDT 24
Peak memory 204036 kb
Host smart-91af42ac-9d43-4a28-bee9-cb56e407f19d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25167
43190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.2516743190
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.1426558670
Short name T658
Test name
Test status
Simulation time 8466788861 ps
CPU time 10.36 seconds
Started Apr 15 03:18:14 PM PDT 24
Finished Apr 15 03:18:25 PM PDT 24
Peak memory 204024 kb
Host smart-f85d72be-a324-4d07-82bf-ccf246421379
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1426558670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.1426558670
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.1444767776
Short name T878
Test name
Test status
Simulation time 8378739926 ps
CPU time 8.19 seconds
Started Apr 15 03:18:13 PM PDT 24
Finished Apr 15 03:18:23 PM PDT 24
Peak memory 204016 kb
Host smart-c1823e9e-a237-47b7-9153-3f49ae2cebb0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1444767776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.1444767776
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.3081170899
Short name T698
Test name
Test status
Simulation time 8443156940 ps
CPU time 8.87 seconds
Started Apr 15 03:18:11 PM PDT 24
Finished Apr 15 03:18:21 PM PDT 24
Peak memory 204032 kb
Host smart-b32d4eed-615d-4ad7-975c-876e7ac722d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30811
70899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.3081170899
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.3657426850
Short name T634
Test name
Test status
Simulation time 8372197899 ps
CPU time 7.75 seconds
Started Apr 15 03:18:09 PM PDT 24
Finished Apr 15 03:18:17 PM PDT 24
Peak memory 204016 kb
Host smart-68ca7c63-b69d-46c3-bad1-369c80e819d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36574
26850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.3657426850
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_enable.3303348002
Short name T335
Test name
Test status
Simulation time 8390838267 ps
CPU time 8.23 seconds
Started Apr 15 03:18:20 PM PDT 24
Finished Apr 15 03:18:29 PM PDT 24
Peak memory 203976 kb
Host smart-122aa032-fa9b-458b-ae18-33b631673743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33033
48002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.3303348002
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.1095701804
Short name T392
Test name
Test status
Simulation time 57386715 ps
CPU time 1.53 seconds
Started Apr 15 03:18:12 PM PDT 24
Finished Apr 15 03:18:14 PM PDT 24
Peak memory 204152 kb
Host smart-fa874d1b-c44c-402f-9b42-37de5b481fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10957
01804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.1095701804
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.2976939608
Short name T124
Test name
Test status
Simulation time 8442520019 ps
CPU time 10.04 seconds
Started Apr 15 03:18:11 PM PDT 24
Finished Apr 15 03:18:21 PM PDT 24
Peak memory 204052 kb
Host smart-f67077fb-e212-4b70-8889-26fe13368edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29769
39608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.2976939608
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.928785488
Short name T517
Test name
Test status
Simulation time 8394530645 ps
CPU time 8.17 seconds
Started Apr 15 03:18:11 PM PDT 24
Finished Apr 15 03:18:20 PM PDT 24
Peak memory 204008 kb
Host smart-e72c4c40-7532-49bd-b041-0a067ad918b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92878
5488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.928785488
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3531579698
Short name T414
Test name
Test status
Simulation time 8397159677 ps
CPU time 9.83 seconds
Started Apr 15 03:18:08 PM PDT 24
Finished Apr 15 03:18:19 PM PDT 24
Peak memory 204016 kb
Host smart-96b7198b-38bd-495e-9fc3-3b043af399e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35315
79698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3531579698
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.2615795602
Short name T821
Test name
Test status
Simulation time 8433933779 ps
CPU time 7.74 seconds
Started Apr 15 03:18:09 PM PDT 24
Finished Apr 15 03:18:18 PM PDT 24
Peak memory 203996 kb
Host smart-dcbe2985-b314-4b7e-b2be-fddb9e41c8d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26157
95602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.2615795602
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.1030945476
Short name T987
Test name
Test status
Simulation time 8375681083 ps
CPU time 7.72 seconds
Started Apr 15 03:18:10 PM PDT 24
Finished Apr 15 03:18:18 PM PDT 24
Peak memory 204064 kb
Host smart-e58aff22-29d4-46b6-95d8-85558db0c7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10309
45476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.1030945476
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.2310831126
Short name T300
Test name
Test status
Simulation time 8396407577 ps
CPU time 8.71 seconds
Started Apr 15 03:18:09 PM PDT 24
Finished Apr 15 03:18:19 PM PDT 24
Peak memory 203968 kb
Host smart-cb15abdc-499f-4716-a4e1-a1095f0f8653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23108
31126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.2310831126
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3214179833
Short name T329
Test name
Test status
Simulation time 8396903414 ps
CPU time 8.16 seconds
Started Apr 15 03:18:07 PM PDT 24
Finished Apr 15 03:18:16 PM PDT 24
Peak memory 204028 kb
Host smart-b8699998-dc2f-4ab6-aa54-24afd9a20fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32141
79833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3214179833
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.1362526797
Short name T172
Test name
Test status
Simulation time 8372214914 ps
CPU time 8.78 seconds
Started Apr 15 03:18:14 PM PDT 24
Finished Apr 15 03:18:24 PM PDT 24
Peak memory 204024 kb
Host smart-ca8df156-5d6d-47f3-95a8-cadfdad41c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13625
26797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.1362526797
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1639476155
Short name T1266
Test name
Test status
Simulation time 8392480459 ps
CPU time 8.44 seconds
Started Apr 15 03:18:13 PM PDT 24
Finished Apr 15 03:18:22 PM PDT 24
Peak memory 204032 kb
Host smart-b9f3d07f-9c41-413e-b9c2-dd52ecb26787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16394
76155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1639476155
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.1308524512
Short name T1245
Test name
Test status
Simulation time 43703689 ps
CPU time 0.65 seconds
Started Apr 15 03:18:15 PM PDT 24
Finished Apr 15 03:18:17 PM PDT 24
Peak memory 203876 kb
Host smart-820aa97b-e68a-405a-b958-4f7e19794951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13085
24512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.1308524512
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.1236015492
Short name T533
Test name
Test status
Simulation time 25978413208 ps
CPU time 49.19 seconds
Started Apr 15 03:18:10 PM PDT 24
Finished Apr 15 03:19:00 PM PDT 24
Peak memory 204328 kb
Host smart-e285a2cd-0eea-4719-b845-2d1107960693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12360
15492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.1236015492
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.1017293719
Short name T1361
Test name
Test status
Simulation time 8396558879 ps
CPU time 8.32 seconds
Started Apr 15 03:18:09 PM PDT 24
Finished Apr 15 03:18:18 PM PDT 24
Peak memory 204064 kb
Host smart-9c6bffa8-e974-4eba-bdc5-2429c9032dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10172
93719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.1017293719
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.4057697905
Short name T792
Test name
Test status
Simulation time 8438250711 ps
CPU time 7.86 seconds
Started Apr 15 03:18:08 PM PDT 24
Finished Apr 15 03:18:16 PM PDT 24
Peak memory 204060 kb
Host smart-e8ad04ff-e85d-4766-941a-c18b4ba732ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40576
97905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.4057697905
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.3580683666
Short name T678
Test name
Test status
Simulation time 8415901699 ps
CPU time 7.81 seconds
Started Apr 15 03:18:12 PM PDT 24
Finished Apr 15 03:18:21 PM PDT 24
Peak memory 204028 kb
Host smart-e85aed60-9174-466b-867e-49909386a81e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35806
83666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.3580683666
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.1166608183
Short name T164
Test name
Test status
Simulation time 8387168007 ps
CPU time 9.76 seconds
Started Apr 15 03:18:12 PM PDT 24
Finished Apr 15 03:18:23 PM PDT 24
Peak memory 203996 kb
Host smart-bd1d41d1-4762-4278-9135-36eaac520a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11666
08183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.1166608183
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.1673759508
Short name T762
Test name
Test status
Simulation time 8371081696 ps
CPU time 8.14 seconds
Started Apr 15 03:18:15 PM PDT 24
Finished Apr 15 03:18:24 PM PDT 24
Peak memory 204004 kb
Host smart-d950c73b-a657-4491-be87-f403611b4a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16737
59508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.1673759508
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.2144244683
Short name T1089
Test name
Test status
Simulation time 8407380840 ps
CPU time 8.62 seconds
Started Apr 15 03:18:07 PM PDT 24
Finished Apr 15 03:18:16 PM PDT 24
Peak memory 204036 kb
Host smart-9538481e-a653-48b2-95a3-984527194b0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21442
44683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.2144244683
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.3050851289
Short name T1263
Test name
Test status
Simulation time 8376072371 ps
CPU time 7.8 seconds
Started Apr 15 03:18:17 PM PDT 24
Finished Apr 15 03:18:26 PM PDT 24
Peak memory 203968 kb
Host smart-6d898c54-dee3-4eca-88ed-46d8185f31ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30508
51289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.3050851289
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.1039508514
Short name T1116
Test name
Test status
Simulation time 8382489300 ps
CPU time 8.45 seconds
Started Apr 15 03:18:07 PM PDT 24
Finished Apr 15 03:18:16 PM PDT 24
Peak memory 204052 kb
Host smart-5f878616-1ed0-4d08-8e40-b1ecc2f08cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10395
08514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.1039508514
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.max_length_in_transaction.178601207
Short name T1315
Test name
Test status
Simulation time 8464351355 ps
CPU time 8.51 seconds
Started Apr 15 03:18:19 PM PDT 24
Finished Apr 15 03:18:28 PM PDT 24
Peak memory 204064 kb
Host smart-04307ebb-4b09-4b41-be76-d7f89303f3ff
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=178601207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.178601207
Directory /workspace/45.max_length_in_transaction/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.2560475981
Short name T708
Test name
Test status
Simulation time 8393874362 ps
CPU time 8.65 seconds
Started Apr 15 03:18:18 PM PDT 24
Finished Apr 15 03:18:27 PM PDT 24
Peak memory 203980 kb
Host smart-bd14ed2d-2cf1-4a77-865c-152c47bedf71
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2560475981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.2560475981
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.random_length_in_trans.2043543079
Short name T38
Test name
Test status
Simulation time 8431270410 ps
CPU time 7.49 seconds
Started Apr 15 03:18:19 PM PDT 24
Finished Apr 15 03:18:27 PM PDT 24
Peak memory 204056 kb
Host smart-3b5fb119-3c2f-4822-8544-cc5aa7c85c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20435
43079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.2043543079
Directory /workspace/45.random_length_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.3041834965
Short name T350
Test name
Test status
Simulation time 8372769406 ps
CPU time 7.6 seconds
Started Apr 15 03:18:14 PM PDT 24
Finished Apr 15 03:18:22 PM PDT 24
Peak memory 204016 kb
Host smart-e2601543-777a-4f4e-b32c-c02c5dfd7e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30418
34965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.3041834965
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_enable.4269951256
Short name T581
Test name
Test status
Simulation time 8393496038 ps
CPU time 9.64 seconds
Started Apr 15 03:18:22 PM PDT 24
Finished Apr 15 03:18:32 PM PDT 24
Peak memory 204048 kb
Host smart-9db40b97-9c34-488d-8c0c-ade5b8f1a379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42699
51256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.4269951256
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.1091530570
Short name T1033
Test name
Test status
Simulation time 245485905 ps
CPU time 1.54 seconds
Started Apr 15 03:18:12 PM PDT 24
Finished Apr 15 03:18:14 PM PDT 24
Peak memory 204044 kb
Host smart-491eb4e3-e222-4c82-98ca-6fa0ca79cdcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10915
30570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1091530570
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.3128418128
Short name T949
Test name
Test status
Simulation time 8386180886 ps
CPU time 8.94 seconds
Started Apr 15 03:18:19 PM PDT 24
Finished Apr 15 03:18:29 PM PDT 24
Peak memory 204052 kb
Host smart-81c8571c-17ee-4016-b6dc-037b70e64812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31284
18128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.3128418128
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.4205912102
Short name T5
Test name
Test status
Simulation time 8369348391 ps
CPU time 8.17 seconds
Started Apr 15 03:18:16 PM PDT 24
Finished Apr 15 03:18:25 PM PDT 24
Peak memory 204028 kb
Host smart-5fe2a330-8823-417a-a780-25d6107b567f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42059
12102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.4205912102
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.782830567
Short name T895
Test name
Test status
Simulation time 8454144693 ps
CPU time 9.15 seconds
Started Apr 15 03:18:12 PM PDT 24
Finished Apr 15 03:18:22 PM PDT 24
Peak memory 204076 kb
Host smart-b51083f0-42d4-4c09-8f07-45c9e67d9457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78283
0567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.782830567
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.775993133
Short name T571
Test name
Test status
Simulation time 8411372005 ps
CPU time 7.57 seconds
Started Apr 15 03:18:12 PM PDT 24
Finished Apr 15 03:18:20 PM PDT 24
Peak memory 204060 kb
Host smart-40bcb665-bf23-417f-8b99-5c2d9909b6ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77599
3133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.775993133
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.294276105
Short name T332
Test name
Test status
Simulation time 8381669113 ps
CPU time 8.21 seconds
Started Apr 15 03:18:17 PM PDT 24
Finished Apr 15 03:18:26 PM PDT 24
Peak memory 204064 kb
Host smart-c94a900a-af23-44f3-a867-90e086acfe08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29427
6105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.294276105
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2809043625
Short name T88
Test name
Test status
Simulation time 8416240850 ps
CPU time 8.28 seconds
Started Apr 15 03:18:16 PM PDT 24
Finished Apr 15 03:18:24 PM PDT 24
Peak memory 204048 kb
Host smart-075c8b4f-5be1-4869-bdf3-21fb280d61a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28090
43625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2809043625
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.91356787
Short name T347
Test name
Test status
Simulation time 8372009521 ps
CPU time 10.07 seconds
Started Apr 15 03:18:18 PM PDT 24
Finished Apr 15 03:18:29 PM PDT 24
Peak memory 204056 kb
Host smart-811362be-e054-48f5-b5b3-2f802dda593a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91356
787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.91356787
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.4266014854
Short name T1094
Test name
Test status
Simulation time 8405329338 ps
CPU time 9.51 seconds
Started Apr 15 03:18:16 PM PDT 24
Finished Apr 15 03:18:26 PM PDT 24
Peak memory 203928 kb
Host smart-1f8860e6-fb0d-429a-ab63-5111ca68e20d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42660
14854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.4266014854
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1421579365
Short name T143
Test name
Test status
Simulation time 8422766262 ps
CPU time 8.13 seconds
Started Apr 15 03:18:20 PM PDT 24
Finished Apr 15 03:18:29 PM PDT 24
Peak memory 204048 kb
Host smart-10a7f1ef-9160-4199-8487-00b6acd6bc5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14215
79365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1421579365
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.3686172677
Short name T1107
Test name
Test status
Simulation time 8366792792 ps
CPU time 7.56 seconds
Started Apr 15 03:18:14 PM PDT 24
Finished Apr 15 03:18:23 PM PDT 24
Peak memory 204068 kb
Host smart-f4d93eba-64ca-4c90-944d-0196b1626d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36861
72677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.3686172677
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.2142925593
Short name T759
Test name
Test status
Simulation time 40004378 ps
CPU time 0.63 seconds
Started Apr 15 03:18:16 PM PDT 24
Finished Apr 15 03:18:17 PM PDT 24
Peak memory 203928 kb
Host smart-30b5fb45-daf8-43cf-804f-5b404b60ad8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21429
25593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.2142925593
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.187246397
Short name T230
Test name
Test status
Simulation time 21830864411 ps
CPU time 42.51 seconds
Started Apr 15 03:18:15 PM PDT 24
Finished Apr 15 03:18:58 PM PDT 24
Peak memory 204312 kb
Host smart-0f6c7159-c9a5-47b5-9a06-f2d8f645ba50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18724
6397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.187246397
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.1448804494
Short name T714
Test name
Test status
Simulation time 8392052516 ps
CPU time 9.25 seconds
Started Apr 15 03:18:14 PM PDT 24
Finished Apr 15 03:18:24 PM PDT 24
Peak memory 203988 kb
Host smart-fbc51996-9a8a-4792-b04d-d79948633d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14488
04494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.1448804494
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.908023195
Short name T1155
Test name
Test status
Simulation time 8387623367 ps
CPU time 9.76 seconds
Started Apr 15 03:18:17 PM PDT 24
Finished Apr 15 03:18:28 PM PDT 24
Peak memory 204004 kb
Host smart-7e138f0f-9ed7-4506-80bf-8269e8b5d884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90802
3195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.908023195
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.2263543559
Short name T386
Test name
Test status
Simulation time 8409148321 ps
CPU time 7.91 seconds
Started Apr 15 03:18:14 PM PDT 24
Finished Apr 15 03:18:23 PM PDT 24
Peak memory 203972 kb
Host smart-f352b589-e8af-4b52-bb88-f8368fa19584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22635
43559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.2263543559
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.413778637
Short name T1140
Test name
Test status
Simulation time 8371790838 ps
CPU time 8.02 seconds
Started Apr 15 03:18:20 PM PDT 24
Finished Apr 15 03:18:29 PM PDT 24
Peak memory 204052 kb
Host smart-44cc8a63-2367-4644-9fda-14722b956980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41377
8637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.413778637
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.4175530801
Short name T339
Test name
Test status
Simulation time 8374538878 ps
CPU time 7.89 seconds
Started Apr 15 03:18:20 PM PDT 24
Finished Apr 15 03:18:29 PM PDT 24
Peak memory 204040 kb
Host smart-78dc91a7-406c-4129-919b-50f2a8d32916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41755
30801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.4175530801
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.609546723
Short name T160
Test name
Test status
Simulation time 8429326875 ps
CPU time 8.94 seconds
Started Apr 15 03:18:16 PM PDT 24
Finished Apr 15 03:18:26 PM PDT 24
Peak memory 204032 kb
Host smart-0d83034d-e579-4bd5-b247-63b05fe9b58f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60954
6723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.609546723
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.1975457829
Short name T385
Test name
Test status
Simulation time 8378704355 ps
CPU time 8.19 seconds
Started Apr 15 03:18:19 PM PDT 24
Finished Apr 15 03:18:27 PM PDT 24
Peak memory 204048 kb
Host smart-fa135721-4b0f-497b-9f39-fa950e17eddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19754
57829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.1975457829
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.732740919
Short name T1035
Test name
Test status
Simulation time 8420941363 ps
CPU time 7.63 seconds
Started Apr 15 03:18:20 PM PDT 24
Finished Apr 15 03:18:28 PM PDT 24
Peak memory 204052 kb
Host smart-3c5f16b5-70aa-4284-aae2-d761e5297979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73274
0919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.732740919
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.449960249
Short name T1010
Test name
Test status
Simulation time 8509021015 ps
CPU time 8.49 seconds
Started Apr 15 03:18:24 PM PDT 24
Finished Apr 15 03:18:33 PM PDT 24
Peak memory 204008 kb
Host smart-ebb96041-80fe-4c95-82f4-753803b81f1a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=449960249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.449960249
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.3290644449
Short name T1252
Test name
Test status
Simulation time 8384383764 ps
CPU time 9.24 seconds
Started Apr 15 03:18:25 PM PDT 24
Finished Apr 15 03:18:35 PM PDT 24
Peak memory 204084 kb
Host smart-3e4cff7b-c543-4fb6-a516-0f6b027c61dd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3290644449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.3290644449
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.3232012997
Short name T1217
Test name
Test status
Simulation time 8432756186 ps
CPU time 7.63 seconds
Started Apr 15 03:18:24 PM PDT 24
Finished Apr 15 03:18:33 PM PDT 24
Peak memory 204044 kb
Host smart-40d29464-eac0-4ceb-9f14-8a172f7a365f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32320
12997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.3232012997
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.295109577
Short name T507
Test name
Test status
Simulation time 8386894441 ps
CPU time 7.45 seconds
Started Apr 15 03:18:19 PM PDT 24
Finished Apr 15 03:18:28 PM PDT 24
Peak memory 204072 kb
Host smart-0bba34a2-5f71-4aa5-9d15-0589e51a5132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29510
9577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.295109577
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_enable.1334554734
Short name T373
Test name
Test status
Simulation time 8372077951 ps
CPU time 10.01 seconds
Started Apr 15 03:18:21 PM PDT 24
Finished Apr 15 03:18:32 PM PDT 24
Peak memory 204048 kb
Host smart-36907c06-5e16-48b5-b3d1-d89b98c7b444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13345
54734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.1334554734
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.2579948413
Short name T311
Test name
Test status
Simulation time 108116727 ps
CPU time 1.17 seconds
Started Apr 15 03:18:21 PM PDT 24
Finished Apr 15 03:18:23 PM PDT 24
Peak memory 204116 kb
Host smart-99628ee8-1760-4d2c-88de-71047140cf38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25799
48413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.2579948413
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.125702571
Short name T927
Test name
Test status
Simulation time 8444933885 ps
CPU time 8.08 seconds
Started Apr 15 03:18:24 PM PDT 24
Finished Apr 15 03:18:33 PM PDT 24
Peak memory 204056 kb
Host smart-1a26d356-06dc-47ba-9fea-ac5ba6c66a7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12570
2571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.125702571
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.264062750
Short name T1314
Test name
Test status
Simulation time 8420954535 ps
CPU time 7.65 seconds
Started Apr 15 03:18:23 PM PDT 24
Finished Apr 15 03:18:32 PM PDT 24
Peak memory 204040 kb
Host smart-21d807fd-25c1-4f43-a182-a9cf0acdaad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26406
2750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.264062750
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.2890029138
Short name T672
Test name
Test status
Simulation time 8417945535 ps
CPU time 7.95 seconds
Started Apr 15 03:18:18 PM PDT 24
Finished Apr 15 03:18:27 PM PDT 24
Peak memory 204200 kb
Host smart-9ac3cdc9-02a8-49f3-9162-a3ae703dbf7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28900
29138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.2890029138
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.1630667975
Short name T361
Test name
Test status
Simulation time 8435426749 ps
CPU time 7.55 seconds
Started Apr 15 03:18:20 PM PDT 24
Finished Apr 15 03:18:28 PM PDT 24
Peak memory 204048 kb
Host smart-4321405c-81ca-47c8-9bf1-5254ee01a268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16306
67975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.1630667975
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.2708475155
Short name T754
Test name
Test status
Simulation time 8375173380 ps
CPU time 9.89 seconds
Started Apr 15 03:18:20 PM PDT 24
Finished Apr 15 03:18:31 PM PDT 24
Peak memory 204032 kb
Host smart-46fabed7-513d-43ca-a927-77555b624236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27084
75155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.2708475155
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.3658704216
Short name T925
Test name
Test status
Simulation time 8410312664 ps
CPU time 7.86 seconds
Started Apr 15 03:18:22 PM PDT 24
Finished Apr 15 03:18:30 PM PDT 24
Peak memory 204052 kb
Host smart-f2b95cd0-b237-46fb-85d0-40cfa9218be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36587
04216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.3658704216
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2489344517
Short name T541
Test name
Test status
Simulation time 8414702282 ps
CPU time 8.97 seconds
Started Apr 15 03:18:20 PM PDT 24
Finished Apr 15 03:18:30 PM PDT 24
Peak memory 204044 kb
Host smart-e1622beb-3489-4d38-b183-bae76dcf9961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24893
44517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2489344517
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.1917733666
Short name T968
Test name
Test status
Simulation time 8432957062 ps
CPU time 7.68 seconds
Started Apr 15 03:18:23 PM PDT 24
Finished Apr 15 03:18:32 PM PDT 24
Peak memory 203976 kb
Host smart-1d841792-e3f9-42b0-be1c-145001312619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19177
33666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.1917733666
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.381870551
Short name T859
Test name
Test status
Simulation time 8378309168 ps
CPU time 10.56 seconds
Started Apr 15 03:18:24 PM PDT 24
Finished Apr 15 03:18:35 PM PDT 24
Peak memory 204044 kb
Host smart-ed659031-7c9d-48e5-a3ee-72cefa7a0e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38187
0551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.381870551
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.3701951720
Short name T1331
Test name
Test status
Simulation time 37953929 ps
CPU time 0.66 seconds
Started Apr 15 03:18:24 PM PDT 24
Finished Apr 15 03:18:26 PM PDT 24
Peak memory 203936 kb
Host smart-acd9f3ec-02b2-4aa6-8f13-24937edccb5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37019
51720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.3701951720
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.2153146227
Short name T1224
Test name
Test status
Simulation time 20003805746 ps
CPU time 41.87 seconds
Started Apr 15 03:18:25 PM PDT 24
Finished Apr 15 03:19:08 PM PDT 24
Peak memory 204272 kb
Host smart-23168cdd-0d91-4ac1-96c7-c49c99a4977d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21531
46227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.2153146227
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.1744643506
Short name T743
Test name
Test status
Simulation time 8413030896 ps
CPU time 7.74 seconds
Started Apr 15 03:18:26 PM PDT 24
Finished Apr 15 03:18:35 PM PDT 24
Peak memory 204076 kb
Host smart-f64a37f3-31ba-4b9b-8b86-0a3851c054d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17446
43506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.1744643506
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.1297996771
Short name T596
Test name
Test status
Simulation time 8454775340 ps
CPU time 8.49 seconds
Started Apr 15 03:18:27 PM PDT 24
Finished Apr 15 03:18:37 PM PDT 24
Peak memory 203988 kb
Host smart-30c8200f-4ef1-4e69-84c8-25962cae27ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12979
96771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.1297996771
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.2708918090
Short name T1247
Test name
Test status
Simulation time 8415065798 ps
CPU time 7.81 seconds
Started Apr 15 03:18:24 PM PDT 24
Finished Apr 15 03:18:33 PM PDT 24
Peak memory 204048 kb
Host smart-17e4f3a7-bb41-4973-9a89-cac4d421db8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27089
18090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.2708918090
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.2636271457
Short name T542
Test name
Test status
Simulation time 8383979625 ps
CPU time 8.75 seconds
Started Apr 15 03:18:26 PM PDT 24
Finished Apr 15 03:18:36 PM PDT 24
Peak memory 204052 kb
Host smart-9369371d-601c-49f4-9f69-e9954706b8aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26362
71457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.2636271457
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.144867373
Short name T372
Test name
Test status
Simulation time 8364845081 ps
CPU time 7.72 seconds
Started Apr 15 03:18:25 PM PDT 24
Finished Apr 15 03:18:34 PM PDT 24
Peak memory 204020 kb
Host smart-0a0adc1e-ac69-40da-9ffc-b5f2458519b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14486
7373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.144867373
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.2745850779
Short name T134
Test name
Test status
Simulation time 8514426813 ps
CPU time 10.43 seconds
Started Apr 15 03:18:19 PM PDT 24
Finished Apr 15 03:18:30 PM PDT 24
Peak memory 204028 kb
Host smart-ecee83fb-a829-4006-b0e7-0caabc2aa42b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27458
50779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.2745850779
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.2054601763
Short name T1222
Test name
Test status
Simulation time 8386086087 ps
CPU time 9.09 seconds
Started Apr 15 03:18:23 PM PDT 24
Finished Apr 15 03:18:33 PM PDT 24
Peak memory 204048 kb
Host smart-d2ea53b7-da15-428e-be84-0bf46e5d46de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20546
01763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.2054601763
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.1376318903
Short name T931
Test name
Test status
Simulation time 8397384189 ps
CPU time 8.6 seconds
Started Apr 15 03:18:24 PM PDT 24
Finished Apr 15 03:18:34 PM PDT 24
Peak memory 203996 kb
Host smart-dc4287cc-6f74-43eb-bd5b-b2e8fa803add
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13763
18903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.1376318903
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.2843675036
Short name T1295
Test name
Test status
Simulation time 8468309349 ps
CPU time 9.88 seconds
Started Apr 15 03:18:31 PM PDT 24
Finished Apr 15 03:18:42 PM PDT 24
Peak memory 204032 kb
Host smart-108b6f8e-12a3-466d-b033-9d36c91544ca
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2843675036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.2843675036
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.1372678767
Short name T313
Test name
Test status
Simulation time 8378508170 ps
CPU time 8.97 seconds
Started Apr 15 03:18:32 PM PDT 24
Finished Apr 15 03:18:42 PM PDT 24
Peak memory 204068 kb
Host smart-f724dc8b-e637-491d-97ae-2156e3894726
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1372678767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.1372678767
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.130046545
Short name T557
Test name
Test status
Simulation time 8423304410 ps
CPU time 9.7 seconds
Started Apr 15 03:18:30 PM PDT 24
Finished Apr 15 03:18:41 PM PDT 24
Peak memory 204036 kb
Host smart-bdccf868-e518-49e0-a00f-87c54b1eccb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13004
6545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.130046545
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1163220152
Short name T781
Test name
Test status
Simulation time 8406446730 ps
CPU time 8.06 seconds
Started Apr 15 03:18:27 PM PDT 24
Finished Apr 15 03:18:36 PM PDT 24
Peak memory 204044 kb
Host smart-22d66340-37fb-4dd1-8b05-93fe8a3808d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11632
20152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1163220152
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_enable.1988657078
Short name T677
Test name
Test status
Simulation time 8383837218 ps
CPU time 9.04 seconds
Started Apr 15 03:18:28 PM PDT 24
Finished Apr 15 03:18:38 PM PDT 24
Peak memory 204028 kb
Host smart-b101224b-84a4-4c15-934d-efcc9f9a0f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19886
57078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.1988657078
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.2751553155
Short name T1337
Test name
Test status
Simulation time 88081193 ps
CPU time 2.04 seconds
Started Apr 15 03:18:27 PM PDT 24
Finished Apr 15 03:18:31 PM PDT 24
Peak memory 204124 kb
Host smart-2dc8baec-c395-4b3e-8ce8-a3dd786ffe7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27515
53155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.2751553155
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.3156135925
Short name T119
Test name
Test status
Simulation time 8461020992 ps
CPU time 8.23 seconds
Started Apr 15 03:18:40 PM PDT 24
Finished Apr 15 03:18:50 PM PDT 24
Peak memory 204052 kb
Host smart-52d47202-6438-4831-86a4-e5b472cff0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31561
35925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.3156135925
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.3465301634
Short name T1350
Test name
Test status
Simulation time 8366204094 ps
CPU time 7.98 seconds
Started Apr 15 03:18:33 PM PDT 24
Finished Apr 15 03:18:41 PM PDT 24
Peak memory 204072 kb
Host smart-2018483e-4f5a-46e9-8684-9f34463f1dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34653
01634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.3465301634
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.2523537445
Short name T138
Test name
Test status
Simulation time 8453783002 ps
CPU time 8.84 seconds
Started Apr 15 03:18:28 PM PDT 24
Finished Apr 15 03:18:38 PM PDT 24
Peak memory 204028 kb
Host smart-3e0e7dc2-9110-403a-b6aa-240821153a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25235
37445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2523537445
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.856953584
Short name T954
Test name
Test status
Simulation time 8415128253 ps
CPU time 8.06 seconds
Started Apr 15 03:18:42 PM PDT 24
Finished Apr 15 03:18:52 PM PDT 24
Peak memory 204024 kb
Host smart-f0c6352f-4e93-473d-b13a-0f8815bf84e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85695
3584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.856953584
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.1638131422
Short name T343
Test name
Test status
Simulation time 8370065736 ps
CPU time 10.23 seconds
Started Apr 15 03:18:28 PM PDT 24
Finished Apr 15 03:18:39 PM PDT 24
Peak memory 204064 kb
Host smart-b6ce7eff-ad3c-4572-bb58-35bb3eecec53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16381
31422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.1638131422
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.3208910083
Short name T826
Test name
Test status
Simulation time 8381156795 ps
CPU time 8.15 seconds
Started Apr 15 03:18:29 PM PDT 24
Finished Apr 15 03:18:38 PM PDT 24
Peak memory 204028 kb
Host smart-84e468d2-5f1d-4c53-9142-1c569682ad42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32089
10083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.3208910083
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.2613046346
Short name T292
Test name
Test status
Simulation time 8415133128 ps
CPU time 8.16 seconds
Started Apr 15 03:18:29 PM PDT 24
Finished Apr 15 03:18:37 PM PDT 24
Peak memory 204028 kb
Host smart-8cfdd220-74da-4de7-b042-82daa61da9ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26130
46346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.2613046346
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1692786623
Short name T618
Test name
Test status
Simulation time 8415915496 ps
CPU time 7.67 seconds
Started Apr 15 03:18:28 PM PDT 24
Finished Apr 15 03:18:36 PM PDT 24
Peak memory 204028 kb
Host smart-e684bec2-997d-4027-845e-72b8c9cbfc9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16927
86623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1692786623
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.414588056
Short name T178
Test name
Test status
Simulation time 8382551445 ps
CPU time 8.43 seconds
Started Apr 15 03:18:41 PM PDT 24
Finished Apr 15 03:18:50 PM PDT 24
Peak memory 204052 kb
Host smart-93e7962d-90da-4a43-bb9c-98c04f9aa6ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41458
8056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.414588056
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.645765444
Short name T1015
Test name
Test status
Simulation time 8369021305 ps
CPU time 7.6 seconds
Started Apr 15 03:18:31 PM PDT 24
Finished Apr 15 03:18:39 PM PDT 24
Peak memory 204028 kb
Host smart-06090100-655e-4830-bdd9-689610c9e106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64576
5444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.645765444
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.1139178124
Short name T449
Test name
Test status
Simulation time 47147126 ps
CPU time 0.8 seconds
Started Apr 15 03:18:34 PM PDT 24
Finished Apr 15 03:18:36 PM PDT 24
Peak memory 204076 kb
Host smart-28d24354-a254-45d4-bdbd-ad7ea4d2eaff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11391
78124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.1139178124
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.1583469021
Short name T1329
Test name
Test status
Simulation time 15563573237 ps
CPU time 30.75 seconds
Started Apr 15 03:18:27 PM PDT 24
Finished Apr 15 03:18:59 PM PDT 24
Peak memory 204276 kb
Host smart-93b1e12c-106a-49c9-a803-03a2af0199f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15834
69021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.1583469021
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.1445802467
Short name T390
Test name
Test status
Simulation time 8387610779 ps
CPU time 7.92 seconds
Started Apr 15 03:18:26 PM PDT 24
Finished Apr 15 03:18:35 PM PDT 24
Peak memory 204048 kb
Host smart-01d4b4bc-eda8-4244-8c2b-1b7c12d0865b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14458
02467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1445802467
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2109602982
Short name T877
Test name
Test status
Simulation time 8374479157 ps
CPU time 8.7 seconds
Started Apr 15 03:18:31 PM PDT 24
Finished Apr 15 03:18:40 PM PDT 24
Peak memory 204024 kb
Host smart-0c7126be-4388-4658-8cae-16d601e9ab5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21096
02982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2109602982
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.1233585834
Short name T822
Test name
Test status
Simulation time 8415637293 ps
CPU time 8.4 seconds
Started Apr 15 03:18:26 PM PDT 24
Finished Apr 15 03:18:35 PM PDT 24
Peak memory 204048 kb
Host smart-7376c093-edb7-4dea-bfcf-a1c05b3cfb42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12335
85834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.1233585834
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.3605252529
Short name T1372
Test name
Test status
Simulation time 8376057625 ps
CPU time 8.62 seconds
Started Apr 15 03:18:30 PM PDT 24
Finished Apr 15 03:18:40 PM PDT 24
Peak memory 204056 kb
Host smart-6ea6c416-0d75-4b78-b076-7896e03298cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36052
52529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.3605252529
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.3251560586
Short name T1205
Test name
Test status
Simulation time 8366152222 ps
CPU time 7.98 seconds
Started Apr 15 03:18:29 PM PDT 24
Finished Apr 15 03:18:37 PM PDT 24
Peak memory 204064 kb
Host smart-8b6b7569-31a9-447a-88cf-8d1dca950f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32515
60586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.3251560586
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.518388961
Short name T872
Test name
Test status
Simulation time 8476605536 ps
CPU time 7.77 seconds
Started Apr 15 03:18:30 PM PDT 24
Finished Apr 15 03:18:38 PM PDT 24
Peak memory 203988 kb
Host smart-849a3c68-5559-4779-b167-7d3f4f564655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51838
8961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.518388961
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.2332592341
Short name T1039
Test name
Test status
Simulation time 8393844705 ps
CPU time 7.78 seconds
Started Apr 15 03:18:33 PM PDT 24
Finished Apr 15 03:18:42 PM PDT 24
Peak memory 204040 kb
Host smart-a62dec1c-aa01-4c80-839b-bec87cff3d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23325
92341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.2332592341
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.2245469988
Short name T540
Test name
Test status
Simulation time 8374564461 ps
CPU time 8.79 seconds
Started Apr 15 03:18:31 PM PDT 24
Finished Apr 15 03:18:41 PM PDT 24
Peak memory 204020 kb
Host smart-77b08fe7-198c-403b-94f0-ab0fafa0d20e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22454
69988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2245469988
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.2459652321
Short name T1375
Test name
Test status
Simulation time 8465379357 ps
CPU time 8.02 seconds
Started Apr 15 03:18:36 PM PDT 24
Finished Apr 15 03:18:45 PM PDT 24
Peak memory 204052 kb
Host smart-c31f30fa-00c3-450b-99f5-5cea3e0bb172
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2459652321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.2459652321
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.3264690336
Short name T1345
Test name
Test status
Simulation time 8474343199 ps
CPU time 8.8 seconds
Started Apr 15 03:18:41 PM PDT 24
Finished Apr 15 03:18:52 PM PDT 24
Peak memory 204056 kb
Host smart-b6647156-2f88-4948-9182-3f7fdf166df3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3264690336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.3264690336
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.527076115
Short name T325
Test name
Test status
Simulation time 8427290395 ps
CPU time 9.46 seconds
Started Apr 15 03:18:38 PM PDT 24
Finished Apr 15 03:18:48 PM PDT 24
Peak memory 204048 kb
Host smart-f1d7238f-d389-4da2-93e8-a62eaedcf001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52707
6115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.527076115
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.2378222047
Short name T1095
Test name
Test status
Simulation time 8439595958 ps
CPU time 8.75 seconds
Started Apr 15 03:18:33 PM PDT 24
Finished Apr 15 03:18:42 PM PDT 24
Peak memory 203988 kb
Host smart-64e5ce37-06a7-466a-b1ed-bfe3e5206c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23782
22047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.2378222047
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_enable.2838781219
Short name T1365
Test name
Test status
Simulation time 8373116322 ps
CPU time 7.81 seconds
Started Apr 15 03:18:30 PM PDT 24
Finished Apr 15 03:18:39 PM PDT 24
Peak memory 204044 kb
Host smart-a618a7a3-b0de-408f-82e0-ebf6b67d6f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28387
81219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.2838781219
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.1786687479
Short name T1280
Test name
Test status
Simulation time 65614994 ps
CPU time 1.62 seconds
Started Apr 15 03:18:33 PM PDT 24
Finished Apr 15 03:18:35 PM PDT 24
Peak memory 204200 kb
Host smart-552df08b-4f5b-4fea-85a1-05e1a682fa3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17866
87479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.1786687479
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.475703022
Short name T168
Test name
Test status
Simulation time 8363280608 ps
CPU time 8.93 seconds
Started Apr 15 03:18:35 PM PDT 24
Finished Apr 15 03:18:45 PM PDT 24
Peak memory 204000 kb
Host smart-442f2e39-f01f-48df-aa02-62d12390e740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47570
3022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.475703022
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.4046682182
Short name T573
Test name
Test status
Simulation time 8533236449 ps
CPU time 8.06 seconds
Started Apr 15 03:18:33 PM PDT 24
Finished Apr 15 03:18:41 PM PDT 24
Peak memory 204044 kb
Host smart-a2d7bff0-02db-4ec0-9fdb-a1841a4957e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40466
82182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.4046682182
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.774980865
Short name T777
Test name
Test status
Simulation time 8415900253 ps
CPU time 7.51 seconds
Started Apr 15 03:18:33 PM PDT 24
Finished Apr 15 03:18:41 PM PDT 24
Peak memory 204024 kb
Host smart-ae81a83b-1b8e-4df8-b96e-982505c8c827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77498
0865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.774980865
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.3103460753
Short name T919
Test name
Test status
Simulation time 8370435029 ps
CPU time 9.55 seconds
Started Apr 15 03:18:40 PM PDT 24
Finished Apr 15 03:18:51 PM PDT 24
Peak memory 204032 kb
Host smart-c75ca335-9135-4baf-8b92-bfcb931ff051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31034
60753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.3103460753
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.1602446324
Short name T1249
Test name
Test status
Simulation time 8430363270 ps
CPU time 7.6 seconds
Started Apr 15 03:18:35 PM PDT 24
Finished Apr 15 03:18:44 PM PDT 24
Peak memory 204028 kb
Host smart-fe5713d5-c1ab-4af0-9de0-ef90bc096a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16024
46324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.1602446324
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.2850382837
Short name T1304
Test name
Test status
Simulation time 8459630725 ps
CPU time 7.74 seconds
Started Apr 15 03:18:34 PM PDT 24
Finished Apr 15 03:18:43 PM PDT 24
Peak memory 204016 kb
Host smart-45872ab0-d83f-4e9b-8ccc-97f2ba4a19c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28503
82837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.2850382837
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2561703774
Short name T582
Test name
Test status
Simulation time 8386880412 ps
CPU time 7.62 seconds
Started Apr 15 03:18:36 PM PDT 24
Finished Apr 15 03:18:45 PM PDT 24
Peak memory 203992 kb
Host smart-f9340dd1-fc74-4374-bdf8-527bc4beda69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25617
03774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2561703774
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.3559308782
Short name T944
Test name
Test status
Simulation time 8411014439 ps
CPU time 8.55 seconds
Started Apr 15 03:18:37 PM PDT 24
Finished Apr 15 03:18:46 PM PDT 24
Peak memory 204068 kb
Host smart-8b2f869f-980e-4e51-9c8b-0972e929dca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35593
08782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.3559308782
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.588191677
Short name T846
Test name
Test status
Simulation time 8416057310 ps
CPU time 7.85 seconds
Started Apr 15 03:18:38 PM PDT 24
Finished Apr 15 03:18:46 PM PDT 24
Peak memory 204056 kb
Host smart-06f72a1e-facd-4df1-8772-494cf66c94f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58819
1677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.588191677
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.2917697057
Short name T1303
Test name
Test status
Simulation time 37895982 ps
CPU time 0.68 seconds
Started Apr 15 03:18:36 PM PDT 24
Finished Apr 15 03:18:38 PM PDT 24
Peak memory 203844 kb
Host smart-f3e35379-fae8-4ea3-aa27-962df7c5e49d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29176
97057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.2917697057
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.1432636693
Short name T1136
Test name
Test status
Simulation time 29786264483 ps
CPU time 59.18 seconds
Started Apr 15 03:18:35 PM PDT 24
Finished Apr 15 03:19:35 PM PDT 24
Peak memory 204336 kb
Host smart-04619e36-5343-4ffd-a7aa-766a519732a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14326
36693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.1432636693
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.4082783800
Short name T1274
Test name
Test status
Simulation time 8385925310 ps
CPU time 10.02 seconds
Started Apr 15 03:18:36 PM PDT 24
Finished Apr 15 03:18:47 PM PDT 24
Peak memory 203928 kb
Host smart-61651bbd-b8f2-41f6-9421-5764ea1e7534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40827
83800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.4082783800
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.2933367995
Short name T1173
Test name
Test status
Simulation time 8405251766 ps
CPU time 8.4 seconds
Started Apr 15 03:18:41 PM PDT 24
Finished Apr 15 03:18:51 PM PDT 24
Peak memory 204052 kb
Host smart-d7a5b89c-13d5-4109-9f88-365ab126e992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29333
67995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.2933367995
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.2502819344
Short name T459
Test name
Test status
Simulation time 8395975624 ps
CPU time 8.94 seconds
Started Apr 15 03:18:35 PM PDT 24
Finished Apr 15 03:18:45 PM PDT 24
Peak memory 203880 kb
Host smart-8e0cfa6e-2100-426e-803d-5446c43cb3f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25028
19344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.2502819344
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.3701517758
Short name T664
Test name
Test status
Simulation time 8422860247 ps
CPU time 7.85 seconds
Started Apr 15 03:18:33 PM PDT 24
Finished Apr 15 03:18:42 PM PDT 24
Peak memory 204040 kb
Host smart-a925056a-03c8-4b72-87c9-1817f2adca93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37015
17758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3701517758
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2181428021
Short name T1145
Test name
Test status
Simulation time 8373637590 ps
CPU time 8.84 seconds
Started Apr 15 03:18:41 PM PDT 24
Finished Apr 15 03:18:52 PM PDT 24
Peak memory 204048 kb
Host smart-f0b64980-0da5-4d4b-abd7-11c6ea77abb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21814
28021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2181428021
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.621619072
Short name T514
Test name
Test status
Simulation time 8473846260 ps
CPU time 8.87 seconds
Started Apr 15 03:18:33 PM PDT 24
Finished Apr 15 03:18:43 PM PDT 24
Peak memory 203988 kb
Host smart-2e3dec38-b596-4f33-bf31-4572132ad3fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62161
9072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.621619072
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.3023882780
Short name T501
Test name
Test status
Simulation time 8379845727 ps
CPU time 8.34 seconds
Started Apr 15 03:18:36 PM PDT 24
Finished Apr 15 03:18:45 PM PDT 24
Peak memory 203968 kb
Host smart-a23c7f27-1d03-45dc-9222-42ef0bd4a81d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30238
82780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.3023882780
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.1994681611
Short name T1376
Test name
Test status
Simulation time 8400935644 ps
CPU time 8.41 seconds
Started Apr 15 03:18:41 PM PDT 24
Finished Apr 15 03:18:51 PM PDT 24
Peak memory 204036 kb
Host smart-081c0340-b861-4a66-b977-237902ca3812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19946
81611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.1994681611
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.4197788735
Short name T732
Test name
Test status
Simulation time 8509228607 ps
CPU time 7.99 seconds
Started Apr 15 03:18:48 PM PDT 24
Finished Apr 15 03:18:57 PM PDT 24
Peak memory 204008 kb
Host smart-662912c1-089a-499d-8b7d-d93625cc694a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4197788735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.4197788735
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.2712636278
Short name T1020
Test name
Test status
Simulation time 8379608494 ps
CPU time 9.37 seconds
Started Apr 15 03:18:46 PM PDT 24
Finished Apr 15 03:18:56 PM PDT 24
Peak memory 204064 kb
Host smart-ae734ada-ca57-4cde-9fe0-ee39f01887a9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2712636278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.2712636278
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.2366589525
Short name T894
Test name
Test status
Simulation time 8382307003 ps
CPU time 8.83 seconds
Started Apr 15 03:18:46 PM PDT 24
Finished Apr 15 03:18:55 PM PDT 24
Peak memory 204064 kb
Host smart-1d66191c-c1b0-4795-80b4-9c00d249ebcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23665
89525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.2366589525
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.1971860388
Short name T1168
Test name
Test status
Simulation time 8379763621 ps
CPU time 9.24 seconds
Started Apr 15 03:18:46 PM PDT 24
Finished Apr 15 03:18:56 PM PDT 24
Peak memory 203992 kb
Host smart-707b7426-9421-4d24-9a88-c1bf5804737f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19718
60388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.1971860388
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_enable.1977117711
Short name T463
Test name
Test status
Simulation time 8390420658 ps
CPU time 7.78 seconds
Started Apr 15 03:18:40 PM PDT 24
Finished Apr 15 03:18:48 PM PDT 24
Peak memory 204056 kb
Host smart-f0e7866f-bd5c-4e21-901c-10d8c25eeb62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19771
17711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.1977117711
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.2900174527
Short name T887
Test name
Test status
Simulation time 183829556 ps
CPU time 1.8 seconds
Started Apr 15 03:18:42 PM PDT 24
Finished Apr 15 03:18:45 PM PDT 24
Peak memory 204116 kb
Host smart-ffe5f238-83a2-4857-8c98-22634919b690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29001
74527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.2900174527
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.2534117901
Short name T493
Test name
Test status
Simulation time 8457636537 ps
CPU time 7.58 seconds
Started Apr 15 03:18:45 PM PDT 24
Finished Apr 15 03:18:53 PM PDT 24
Peak memory 204020 kb
Host smart-03f22657-9560-43d8-a208-f43ff706b8d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25341
17901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.2534117901
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.73436299
Short name T1171
Test name
Test status
Simulation time 8372077955 ps
CPU time 9.92 seconds
Started Apr 15 03:18:42 PM PDT 24
Finished Apr 15 03:18:53 PM PDT 24
Peak memory 204028 kb
Host smart-40c082cd-5195-47ec-9f62-e6498b1eb539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73436
299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.73436299
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.2269966730
Short name T460
Test name
Test status
Simulation time 8433079539 ps
CPU time 8.14 seconds
Started Apr 15 03:18:40 PM PDT 24
Finished Apr 15 03:18:49 PM PDT 24
Peak memory 204048 kb
Host smart-e24c6432-0efe-4311-acee-a89f9dd10439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22699
66730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.2269966730
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2473792872
Short name T310
Test name
Test status
Simulation time 8419997036 ps
CPU time 9.44 seconds
Started Apr 15 03:18:46 PM PDT 24
Finished Apr 15 03:18:56 PM PDT 24
Peak memory 203996 kb
Host smart-2b93b7ca-bf9f-43ed-8b15-2cfdf0891145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24737
92872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2473792872
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.762651112
Short name T1297
Test name
Test status
Simulation time 8368514143 ps
CPU time 9.98 seconds
Started Apr 15 03:18:39 PM PDT 24
Finished Apr 15 03:18:49 PM PDT 24
Peak memory 204060 kb
Host smart-7b1c0226-033f-4fa6-ba5a-92e506b455f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76265
1112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.762651112
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.4037613109
Short name T105
Test name
Test status
Simulation time 8442364201 ps
CPU time 8.27 seconds
Started Apr 15 03:18:40 PM PDT 24
Finished Apr 15 03:18:49 PM PDT 24
Peak memory 203928 kb
Host smart-c0d754b5-69dc-410b-9e3a-6a1a13d5e3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40376
13109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.4037613109
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3730441472
Short name T426
Test name
Test status
Simulation time 8404057763 ps
CPU time 8.9 seconds
Started Apr 15 03:18:42 PM PDT 24
Finished Apr 15 03:18:52 PM PDT 24
Peak memory 204028 kb
Host smart-6399e136-f804-4970-b635-b7cb568813c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37304
41472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3730441472
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.1147270775
Short name T1147
Test name
Test status
Simulation time 8412680141 ps
CPU time 8.31 seconds
Started Apr 15 03:18:40 PM PDT 24
Finished Apr 15 03:18:50 PM PDT 24
Peak memory 204044 kb
Host smart-25a6676d-ce8f-41d5-a259-f5fa78981dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11472
70775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.1147270775
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.4162980255
Short name T787
Test name
Test status
Simulation time 8387231018 ps
CPU time 7.76 seconds
Started Apr 15 03:18:42 PM PDT 24
Finished Apr 15 03:18:51 PM PDT 24
Peak memory 204072 kb
Host smart-3a75390a-a7de-47f8-8fd1-ba254ffd9ac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41629
80255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.4162980255
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3653596615
Short name T23
Test name
Test status
Simulation time 8374697154 ps
CPU time 8.02 seconds
Started Apr 15 03:18:44 PM PDT 24
Finished Apr 15 03:18:52 PM PDT 24
Peak memory 204052 kb
Host smart-d09537a9-b7de-40c8-85a7-170f6dcfa5b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36535
96615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3653596615
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.1207736144
Short name T705
Test name
Test status
Simulation time 36684701 ps
CPU time 0.67 seconds
Started Apr 15 03:18:41 PM PDT 24
Finished Apr 15 03:18:43 PM PDT 24
Peak memory 203936 kb
Host smart-4ee3c5f7-97ff-4f8d-b95d-983459137326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12077
36144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.1207736144
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.1267984754
Short name T1294
Test name
Test status
Simulation time 27509662663 ps
CPU time 54.1 seconds
Started Apr 15 03:18:46 PM PDT 24
Finished Apr 15 03:19:41 PM PDT 24
Peak memory 204280 kb
Host smart-ca06c787-f19c-454f-928c-e23de7b9e407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12679
84754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.1267984754
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3584760809
Short name T851
Test name
Test status
Simulation time 8417395261 ps
CPU time 8.19 seconds
Started Apr 15 03:18:40 PM PDT 24
Finished Apr 15 03:18:49 PM PDT 24
Peak memory 204032 kb
Host smart-2deef237-a3dd-4198-ad3f-c8206bd9f054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35847
60809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3584760809
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1638841959
Short name T729
Test name
Test status
Simulation time 8418333161 ps
CPU time 8.21 seconds
Started Apr 15 03:18:41 PM PDT 24
Finished Apr 15 03:18:50 PM PDT 24
Peak memory 204072 kb
Host smart-6d4e8a90-8b2c-45c3-b986-0bb21707d704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16388
41959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1638841959
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.2817112010
Short name T291
Test name
Test status
Simulation time 8436253673 ps
CPU time 8.17 seconds
Started Apr 15 03:18:41 PM PDT 24
Finished Apr 15 03:18:51 PM PDT 24
Peak memory 203980 kb
Host smart-439bad60-cfd9-4ede-923f-586f8f562908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28171
12010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.2817112010
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.216574485
Short name T1114
Test name
Test status
Simulation time 8380035448 ps
CPU time 8.06 seconds
Started Apr 15 03:18:42 PM PDT 24
Finished Apr 15 03:18:51 PM PDT 24
Peak memory 204080 kb
Host smart-5275b8b5-4e4f-495c-baed-e58d79a8048e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21657
4485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.216574485
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.1632239219
Short name T854
Test name
Test status
Simulation time 8397881705 ps
CPU time 8.39 seconds
Started Apr 15 03:18:42 PM PDT 24
Finished Apr 15 03:18:52 PM PDT 24
Peak memory 203984 kb
Host smart-03c7377c-9daf-4d4d-b522-ccc94cacf168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16322
39219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.1632239219
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3035757468
Short name T1123
Test name
Test status
Simulation time 8457055003 ps
CPU time 8.15 seconds
Started Apr 15 03:18:43 PM PDT 24
Finished Apr 15 03:18:52 PM PDT 24
Peak memory 204052 kb
Host smart-edfc7c27-551d-4e09-a0c0-2cab0087af1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30357
57468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3035757468
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.779200135
Short name T288
Test name
Test status
Simulation time 8412933137 ps
CPU time 9.07 seconds
Started Apr 15 03:18:41 PM PDT 24
Finished Apr 15 03:18:52 PM PDT 24
Peak memory 204056 kb
Host smart-9a610e67-3389-4c9b-8815-9cee6e7fd3e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77920
0135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.779200135
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.952969042
Short name T870
Test name
Test status
Simulation time 8408057308 ps
CPU time 8.1 seconds
Started Apr 15 03:18:41 PM PDT 24
Finished Apr 15 03:18:50 PM PDT 24
Peak memory 203984 kb
Host smart-c11b086b-d259-4f22-9db5-0ccfff250211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95296
9042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.952969042
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.1443438391
Short name T338
Test name
Test status
Simulation time 8470398803 ps
CPU time 8.59 seconds
Started Apr 15 03:12:15 PM PDT 24
Finished Apr 15 03:12:24 PM PDT 24
Peak memory 204052 kb
Host smart-60add5b8-5dd4-4866-b1e2-a317b38f767e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1443438391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.1443438391
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.2340543861
Short name T849
Test name
Test status
Simulation time 8424448961 ps
CPU time 8.28 seconds
Started Apr 15 03:12:11 PM PDT 24
Finished Apr 15 03:12:19 PM PDT 24
Peak memory 204020 kb
Host smart-ea1838cf-3281-4d0f-af94-db23acf86627
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2340543861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.2340543861
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.2410275243
Short name T962
Test name
Test status
Simulation time 8428304924 ps
CPU time 7.72 seconds
Started Apr 15 03:12:11 PM PDT 24
Finished Apr 15 03:12:19 PM PDT 24
Peak memory 204052 kb
Host smart-744d5d46-0763-4dd8-8680-6f7d1020234c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24102
75243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.2410275243
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.3196147906
Short name T1326
Test name
Test status
Simulation time 8382060510 ps
CPU time 8.52 seconds
Started Apr 15 03:11:57 PM PDT 24
Finished Apr 15 03:12:07 PM PDT 24
Peak memory 204060 kb
Host smart-4e749f1f-bdea-4293-8c2c-6352f4f562a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31961
47906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.3196147906
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_enable.2156683849
Short name T203
Test name
Test status
Simulation time 8378768411 ps
CPU time 8.48 seconds
Started Apr 15 03:11:55 PM PDT 24
Finished Apr 15 03:12:04 PM PDT 24
Peak memory 204048 kb
Host smart-46f8f8a2-b196-48a5-88a1-e896ae01b1be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21566
83849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2156683849
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.1480026448
Short name T978
Test name
Test status
Simulation time 56327895 ps
CPU time 1.38 seconds
Started Apr 15 03:11:59 PM PDT 24
Finished Apr 15 03:12:00 PM PDT 24
Peak memory 204188 kb
Host smart-b5ca8511-2426-4888-9772-e2a077ab992e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14800
26448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.1480026448
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.477693062
Short name T564
Test name
Test status
Simulation time 8425101931 ps
CPU time 9.27 seconds
Started Apr 15 03:12:11 PM PDT 24
Finished Apr 15 03:12:21 PM PDT 24
Peak memory 204048 kb
Host smart-dd7d5c5d-1c1a-4df4-ae72-617f5a19b823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47769
3062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.477693062
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.2817864375
Short name T1333
Test name
Test status
Simulation time 8371894028 ps
CPU time 7.75 seconds
Started Apr 15 03:12:12 PM PDT 24
Finished Apr 15 03:12:21 PM PDT 24
Peak memory 204024 kb
Host smart-29043517-c97e-44c1-8258-eb464b82c4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28178
64375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.2817864375
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3815750902
Short name T1131
Test name
Test status
Simulation time 8424718502 ps
CPU time 8.51 seconds
Started Apr 15 03:11:57 PM PDT 24
Finished Apr 15 03:12:06 PM PDT 24
Peak memory 204052 kb
Host smart-6f25f930-977f-4e07-a101-fb62f92f3720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38157
50902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3815750902
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.4188468595
Short name T503
Test name
Test status
Simulation time 8441547273 ps
CPU time 7.91 seconds
Started Apr 15 03:12:02 PM PDT 24
Finished Apr 15 03:12:10 PM PDT 24
Peak memory 204052 kb
Host smart-910d67e7-501a-4f5b-b36d-0f98ca596141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41884
68595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.4188468595
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.2071933742
Short name T1377
Test name
Test status
Simulation time 8370974659 ps
CPU time 7.74 seconds
Started Apr 15 03:11:59 PM PDT 24
Finished Apr 15 03:12:08 PM PDT 24
Peak memory 204028 kb
Host smart-7ce56619-6fe0-4bc4-ba94-4fa16f6e93ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20719
33742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.2071933742
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1619511021
Short name T1041
Test name
Test status
Simulation time 8439783965 ps
CPU time 7.89 seconds
Started Apr 15 03:12:03 PM PDT 24
Finished Apr 15 03:12:11 PM PDT 24
Peak memory 203992 kb
Host smart-acfd9833-3900-46c2-840b-bbd72547b328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16195
11021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1619511021
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.3071203601
Short name T479
Test name
Test status
Simulation time 8392424041 ps
CPU time 9.22 seconds
Started Apr 15 03:12:05 PM PDT 24
Finished Apr 15 03:12:14 PM PDT 24
Peak memory 203992 kb
Host smart-1bed16c2-d7ac-4457-8b84-223ad985bd96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30712
03601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.3071203601
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.3218819046
Short name T1047
Test name
Test status
Simulation time 8389818418 ps
CPU time 7.53 seconds
Started Apr 15 03:12:04 PM PDT 24
Finished Apr 15 03:12:12 PM PDT 24
Peak memory 204008 kb
Host smart-61a9b527-cad2-4b06-af70-f5e6c9c7f28d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32188
19046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.3218819046
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.2310319042
Short name T1014
Test name
Test status
Simulation time 8428878335 ps
CPU time 8.2 seconds
Started Apr 15 03:12:10 PM PDT 24
Finished Apr 15 03:12:19 PM PDT 24
Peak memory 204012 kb
Host smart-0abaedda-47f3-4fe7-a9c6-3b281a3b5e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23103
19042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.2310319042
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.1040574583
Short name T1018
Test name
Test status
Simulation time 40009169 ps
CPU time 0.68 seconds
Started Apr 15 03:12:11 PM PDT 24
Finished Apr 15 03:12:13 PM PDT 24
Peak memory 203880 kb
Host smart-ba9534e0-21f2-40a3-bda7-b6c06a7fbca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10405
74583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.1040574583
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.2838358047
Short name T1027
Test name
Test status
Simulation time 27104356607 ps
CPU time 58.33 seconds
Started Apr 15 03:12:05 PM PDT 24
Finished Apr 15 03:13:04 PM PDT 24
Peak memory 204332 kb
Host smart-a7b86c6c-14a4-4d1a-81d0-c36283fac4cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28383
58047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.2838358047
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.2153750672
Short name T1183
Test name
Test status
Simulation time 8410767512 ps
CPU time 10.46 seconds
Started Apr 15 03:12:04 PM PDT 24
Finished Apr 15 03:12:15 PM PDT 24
Peak memory 204032 kb
Host smart-c57c4f12-70e3-4ca6-a35d-ae64fa7e5740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21537
50672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2153750672
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.3964210034
Short name T289
Test name
Test status
Simulation time 8439111229 ps
CPU time 7.69 seconds
Started Apr 15 03:12:04 PM PDT 24
Finished Apr 15 03:12:12 PM PDT 24
Peak memory 204032 kb
Host smart-31b1faf9-5918-419f-8eb2-9df45dc8e2f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39642
10034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.3964210034
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.2987335040
Short name T715
Test name
Test status
Simulation time 8407081552 ps
CPU time 7.69 seconds
Started Apr 15 03:12:05 PM PDT 24
Finished Apr 15 03:12:13 PM PDT 24
Peak memory 204028 kb
Host smart-5cc27e51-eef5-4095-8ab5-180460e71a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29873
35040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.2987335040
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.4284289512
Short name T770
Test name
Test status
Simulation time 8376438511 ps
CPU time 8.67 seconds
Started Apr 15 03:12:12 PM PDT 24
Finished Apr 15 03:12:22 PM PDT 24
Peak memory 204020 kb
Host smart-937b0d0e-feb9-40ae-96bd-efc8d0176ce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42842
89512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.4284289512
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1818696455
Short name T511
Test name
Test status
Simulation time 8383554171 ps
CPU time 8.94 seconds
Started Apr 15 03:12:09 PM PDT 24
Finished Apr 15 03:12:18 PM PDT 24
Peak memory 204064 kb
Host smart-6942831a-48d6-4779-ba57-0e3da2af56b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18186
96455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1818696455
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.4108668249
Short name T447
Test name
Test status
Simulation time 8446858438 ps
CPU time 7.88 seconds
Started Apr 15 03:11:59 PM PDT 24
Finished Apr 15 03:12:07 PM PDT 24
Peak memory 204060 kb
Host smart-391c976a-e343-4c1d-8294-08072302dc6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41086
68249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.4108668249
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.1226130880
Short name T1313
Test name
Test status
Simulation time 8392118729 ps
CPU time 7.73 seconds
Started Apr 15 03:12:07 PM PDT 24
Finished Apr 15 03:12:15 PM PDT 24
Peak memory 204024 kb
Host smart-16d69505-3399-42c8-aebc-93ce3c57a312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12261
30880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.1226130880
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.3790794060
Short name T967
Test name
Test status
Simulation time 8387029477 ps
CPU time 9.73 seconds
Started Apr 15 03:12:08 PM PDT 24
Finished Apr 15 03:12:18 PM PDT 24
Peak memory 204000 kb
Host smart-378b2648-89a9-4644-9525-c889eea0f623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37907
94060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.3790794060
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.3012347552
Short name T327
Test name
Test status
Simulation time 8481607681 ps
CPU time 7.87 seconds
Started Apr 15 03:12:27 PM PDT 24
Finished Apr 15 03:12:35 PM PDT 24
Peak memory 203988 kb
Host smart-db289efa-163b-47ca-be94-1ec19088b9f8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3012347552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.3012347552
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.3517823032
Short name T365
Test name
Test status
Simulation time 8404461251 ps
CPU time 7.82 seconds
Started Apr 15 03:12:30 PM PDT 24
Finished Apr 15 03:12:38 PM PDT 24
Peak memory 204048 kb
Host smart-ee724ee3-8a2b-4b24-b708-080f70e446e9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3517823032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.3517823032
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.1212645281
Short name T1104
Test name
Test status
Simulation time 8463370078 ps
CPU time 8.1 seconds
Started Apr 15 03:12:26 PM PDT 24
Finished Apr 15 03:12:35 PM PDT 24
Peak memory 203996 kb
Host smart-7f799252-72b2-4808-91bc-13bf844e4e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12126
45281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.1212645281
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.34102712
Short name T979
Test name
Test status
Simulation time 8389493158 ps
CPU time 8.71 seconds
Started Apr 15 03:12:24 PM PDT 24
Finished Apr 15 03:12:33 PM PDT 24
Peak memory 204052 kb
Host smart-3ab31b25-7836-415a-883c-2b6167d0ed81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34102
712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.34102712
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_enable.1185179085
Short name T858
Test name
Test status
Simulation time 8373926250 ps
CPU time 9.35 seconds
Started Apr 15 03:12:14 PM PDT 24
Finished Apr 15 03:12:23 PM PDT 24
Peak memory 204072 kb
Host smart-06aaf826-0344-4f89-93d2-ea66b8c1a9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11851
79085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.1185179085
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.3853671956
Short name T1019
Test name
Test status
Simulation time 170860787 ps
CPU time 1.42 seconds
Started Apr 15 03:12:16 PM PDT 24
Finished Apr 15 03:12:18 PM PDT 24
Peak memory 204100 kb
Host smart-58f278f4-dba6-486d-b8d5-2b1a99983dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38536
71956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.3853671956
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.1187460460
Short name T35
Test name
Test status
Simulation time 8387847067 ps
CPU time 8.61 seconds
Started Apr 15 03:12:26 PM PDT 24
Finished Apr 15 03:12:35 PM PDT 24
Peak memory 203880 kb
Host smart-2ac8ddef-9694-4471-81f1-658cd10d28c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11874
60460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.1187460460
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.3078381019
Short name T165
Test name
Test status
Simulation time 8428207615 ps
CPU time 9.04 seconds
Started Apr 15 03:12:25 PM PDT 24
Finished Apr 15 03:12:35 PM PDT 24
Peak memory 204044 kb
Host smart-9c8e6e17-362b-4e66-8660-0e391204545e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30783
81019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.3078381019
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.3112958905
Short name T117
Test name
Test status
Simulation time 8387222365 ps
CPU time 7.43 seconds
Started Apr 15 03:12:16 PM PDT 24
Finished Apr 15 03:12:24 PM PDT 24
Peak memory 204028 kb
Host smart-85878360-0b45-45f3-8bc7-67f57c895acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31129
58905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.3112958905
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.2032652080
Short name T1073
Test name
Test status
Simulation time 8412202223 ps
CPU time 8.07 seconds
Started Apr 15 03:12:19 PM PDT 24
Finished Apr 15 03:12:27 PM PDT 24
Peak memory 204064 kb
Host smart-cc5ccd6d-60c7-4e31-bffd-757ffaec640d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20326
52080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.2032652080
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.1710055166
Short name T802
Test name
Test status
Simulation time 8369439416 ps
CPU time 7.93 seconds
Started Apr 15 03:12:24 PM PDT 24
Finished Apr 15 03:12:33 PM PDT 24
Peak memory 204052 kb
Host smart-7365678f-20cf-43c6-92f1-544335f232ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17100
55166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.1710055166
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3613560655
Short name T104
Test name
Test status
Simulation time 8450834386 ps
CPU time 8.27 seconds
Started Apr 15 03:12:29 PM PDT 24
Finished Apr 15 03:12:37 PM PDT 24
Peak memory 204060 kb
Host smart-1e4a7efe-71a1-4269-aef1-cbf7774c172e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36135
60655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3613560655
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3487421930
Short name T14
Test name
Test status
Simulation time 8388435737 ps
CPU time 9.95 seconds
Started Apr 15 03:12:25 PM PDT 24
Finished Apr 15 03:12:35 PM PDT 24
Peak memory 204052 kb
Host smart-8e2996cd-d160-4809-a34c-44a59766c698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34874
21930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3487421930
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.2732476589
Short name T776
Test name
Test status
Simulation time 8386625541 ps
CPU time 8.13 seconds
Started Apr 15 03:12:18 PM PDT 24
Finished Apr 15 03:12:27 PM PDT 24
Peak memory 203928 kb
Host smart-5b898adf-e558-4abb-a2ad-c3438a9baa40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27324
76589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.2732476589
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.998700758
Short name T144
Test name
Test status
Simulation time 8387221217 ps
CPU time 8.25 seconds
Started Apr 15 03:12:24 PM PDT 24
Finished Apr 15 03:12:33 PM PDT 24
Peak memory 204060 kb
Host smart-c81f6d20-72e2-4e81-b96b-b68c0981a7bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99870
0758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.998700758
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.3205044066
Short name T1208
Test name
Test status
Simulation time 8372091339 ps
CPU time 7.87 seconds
Started Apr 15 03:12:22 PM PDT 24
Finished Apr 15 03:12:30 PM PDT 24
Peak memory 204060 kb
Host smart-f63524c6-0ae5-43e6-a2f5-b207ce038748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32050
44066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.3205044066
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1864682609
Short name T1092
Test name
Test status
Simulation time 21898106053 ps
CPU time 44.81 seconds
Started Apr 15 03:12:17 PM PDT 24
Finished Apr 15 03:13:02 PM PDT 24
Peak memory 204312 kb
Host smart-4a33e0b5-20b6-4987-8f6b-991c789d9d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18646
82609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1864682609
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.4199170798
Short name T575
Test name
Test status
Simulation time 8413236388 ps
CPU time 7.88 seconds
Started Apr 15 03:12:18 PM PDT 24
Finished Apr 15 03:12:27 PM PDT 24
Peak memory 204080 kb
Host smart-861bf4a5-dce6-4f68-90d5-85c2193d2d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41991
70798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.4199170798
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.588199688
Short name T1359
Test name
Test status
Simulation time 8423291183 ps
CPU time 7.81 seconds
Started Apr 15 03:12:20 PM PDT 24
Finished Apr 15 03:12:28 PM PDT 24
Peak memory 204032 kb
Host smart-f355415a-6f6a-4d69-a5f8-de6e27875186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58819
9688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.588199688
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.326967460
Short name T1328
Test name
Test status
Simulation time 8400398986 ps
CPU time 8.34 seconds
Started Apr 15 03:12:24 PM PDT 24
Finished Apr 15 03:12:33 PM PDT 24
Peak memory 204052 kb
Host smart-6aca842c-4945-4402-ad52-13da492ad285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32696
7460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.326967460
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.3989618266
Short name T737
Test name
Test status
Simulation time 8377339848 ps
CPU time 9.4 seconds
Started Apr 15 03:12:24 PM PDT 24
Finished Apr 15 03:12:34 PM PDT 24
Peak memory 203984 kb
Host smart-59275bed-a0f4-4968-80ad-936f759dc4b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39896
18266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.3989618266
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1360345870
Short name T466
Test name
Test status
Simulation time 8376646094 ps
CPU time 8.59 seconds
Started Apr 15 03:12:19 PM PDT 24
Finished Apr 15 03:12:28 PM PDT 24
Peak memory 204020 kb
Host smart-63cfecd7-67c9-4e29-8969-cda975921cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13603
45870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1360345870
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.627348510
Short name T1134
Test name
Test status
Simulation time 8451474045 ps
CPU time 9.37 seconds
Started Apr 15 03:12:15 PM PDT 24
Finished Apr 15 03:12:25 PM PDT 24
Peak memory 203976 kb
Host smart-4c8a6778-0d3e-4ddc-bd6a-cb790603ecf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62734
8510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.627348510
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.4088889279
Short name T701
Test name
Test status
Simulation time 8400867709 ps
CPU time 8.55 seconds
Started Apr 15 03:12:24 PM PDT 24
Finished Apr 15 03:12:33 PM PDT 24
Peak memory 204024 kb
Host smart-158a9c43-f2fe-48cb-8ce3-ad93d0309f93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40888
89279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.4088889279
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.165041751
Short name T1240
Test name
Test status
Simulation time 8421390517 ps
CPU time 9.15 seconds
Started Apr 15 03:12:25 PM PDT 24
Finished Apr 15 03:12:34 PM PDT 24
Peak memory 204048 kb
Host smart-e859c324-306c-4e3f-a3e6-c9af66471b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16504
1751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.165041751
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.1146259881
Short name T686
Test name
Test status
Simulation time 8468568873 ps
CPU time 7.86 seconds
Started Apr 15 03:12:39 PM PDT 24
Finished Apr 15 03:12:48 PM PDT 24
Peak memory 204068 kb
Host smart-288e8a8c-625e-4167-b02c-6abcbf5d2faa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1146259881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.1146259881
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.3652465838
Short name T964
Test name
Test status
Simulation time 8465116800 ps
CPU time 9.46 seconds
Started Apr 15 03:12:46 PM PDT 24
Finished Apr 15 03:12:56 PM PDT 24
Peak memory 204052 kb
Host smart-b8dc2387-08a6-4cfa-932a-0b706aebdc47
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3652465838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.3652465838
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.2760460868
Short name T599
Test name
Test status
Simulation time 8466396759 ps
CPU time 10.06 seconds
Started Apr 15 03:12:40 PM PDT 24
Finished Apr 15 03:12:50 PM PDT 24
Peak memory 204024 kb
Host smart-05221481-289f-42a2-9b7f-16c8b646267d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27604
60868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.2760460868
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2091116423
Short name T1344
Test name
Test status
Simulation time 8380324264 ps
CPU time 8.96 seconds
Started Apr 15 03:12:31 PM PDT 24
Finished Apr 15 03:12:40 PM PDT 24
Peak memory 204060 kb
Host smart-292c4c18-7e3d-470f-b3a5-32f0d08cfca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20911
16423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2091116423
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_enable.1358739982
Short name T389
Test name
Test status
Simulation time 8399056384 ps
CPU time 9.66 seconds
Started Apr 15 03:12:36 PM PDT 24
Finished Apr 15 03:12:47 PM PDT 24
Peak memory 204056 kb
Host smart-b502b402-6ac6-409a-bd80-42d2006144c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13587
39982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.1358739982
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1316460089
Short name T393
Test name
Test status
Simulation time 104690512 ps
CPU time 1.18 seconds
Started Apr 15 03:12:41 PM PDT 24
Finished Apr 15 03:12:43 PM PDT 24
Peak memory 204172 kb
Host smart-d818be88-4fe2-4a99-93fb-b0b63b926963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13164
60089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1316460089
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.2895691639
Short name T140
Test name
Test status
Simulation time 8382881225 ps
CPU time 10.4 seconds
Started Apr 15 03:12:40 PM PDT 24
Finished Apr 15 03:12:51 PM PDT 24
Peak memory 204028 kb
Host smart-24d80a0b-7162-4a55-a63c-2f05fcb451fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28956
91639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.2895691639
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.1723361881
Short name T1017
Test name
Test status
Simulation time 8365417865 ps
CPU time 8.77 seconds
Started Apr 15 03:12:42 PM PDT 24
Finished Apr 15 03:12:51 PM PDT 24
Peak memory 204012 kb
Host smart-b5c6e89e-aa00-4f16-b83d-a8a4fb1781c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17233
61881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.1723361881
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.4047023561
Short name T716
Test name
Test status
Simulation time 8440869618 ps
CPU time 7.67 seconds
Started Apr 15 03:12:35 PM PDT 24
Finished Apr 15 03:12:43 PM PDT 24
Peak memory 204044 kb
Host smart-8e7b0b8c-4b45-4bf8-b0ed-0c7f18925856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40470
23561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.4047023561
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.846064898
Short name T811
Test name
Test status
Simulation time 8436912299 ps
CPU time 8.84 seconds
Started Apr 15 03:12:31 PM PDT 24
Finished Apr 15 03:12:40 PM PDT 24
Peak memory 204068 kb
Host smart-aa2b4c93-2c63-4735-a89f-33477d913caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84606
4898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.846064898
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.3528088420
Short name T1179
Test name
Test status
Simulation time 8376191472 ps
CPU time 7.52 seconds
Started Apr 15 03:12:29 PM PDT 24
Finished Apr 15 03:12:37 PM PDT 24
Peak memory 204072 kb
Host smart-78b88b23-c1ab-4d32-8e59-44c3e8f4185c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35280
88420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.3528088420
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3404992524
Short name T90
Test name
Test status
Simulation time 8463692549 ps
CPU time 8.15 seconds
Started Apr 15 03:12:32 PM PDT 24
Finished Apr 15 03:12:40 PM PDT 24
Peak memory 204052 kb
Host smart-ec93ac32-40ce-4dfd-adae-081375e82498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34049
92524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3404992524
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.4241172728
Short name T283
Test name
Test status
Simulation time 8394319797 ps
CPU time 9.86 seconds
Started Apr 15 03:12:42 PM PDT 24
Finished Apr 15 03:12:52 PM PDT 24
Peak memory 204040 kb
Host smart-cb644e13-4b42-46d1-bdc6-0a5fbe291227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42411
72728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.4241172728
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.1356647568
Short name T923
Test name
Test status
Simulation time 8408742994 ps
CPU time 8.53 seconds
Started Apr 15 03:12:34 PM PDT 24
Finished Apr 15 03:12:44 PM PDT 24
Peak memory 204044 kb
Host smart-9b6973bb-2b7f-43dd-be33-3a6c28cc3f23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13566
47568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.1356647568
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.3685632467
Short name T606
Test name
Test status
Simulation time 8396925037 ps
CPU time 10.27 seconds
Started Apr 15 03:12:36 PM PDT 24
Finished Apr 15 03:12:47 PM PDT 24
Peak memory 204044 kb
Host smart-96d9bd10-cf4f-42bc-b38b-95be2bb83919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36856
32467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.3685632467
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.289379553
Short name T947
Test name
Test status
Simulation time 8368350413 ps
CPU time 8.09 seconds
Started Apr 15 03:12:34 PM PDT 24
Finished Apr 15 03:12:43 PM PDT 24
Peak memory 203972 kb
Host smart-fb1b9450-0da7-4ef0-bdf0-6dcaace6505a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28937
9553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.289379553
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.1471807724
Short name T868
Test name
Test status
Simulation time 53003533 ps
CPU time 0.74 seconds
Started Apr 15 03:12:34 PM PDT 24
Finished Apr 15 03:12:36 PM PDT 24
Peak memory 203932 kb
Host smart-de5944fa-1807-479a-ba22-7d3ac4aefcf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14718
07724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.1471807724
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.513760380
Short name T1101
Test name
Test status
Simulation time 20060665268 ps
CPU time 36.99 seconds
Started Apr 15 03:12:32 PM PDT 24
Finished Apr 15 03:13:09 PM PDT 24
Peak memory 204332 kb
Host smart-cf15f189-3415-4f32-9024-4dc4b7d6eaf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51376
0380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.513760380
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.2725623485
Short name T590
Test name
Test status
Simulation time 8447662006 ps
CPU time 8.85 seconds
Started Apr 15 03:12:41 PM PDT 24
Finished Apr 15 03:12:51 PM PDT 24
Peak memory 204044 kb
Host smart-9a654f41-e7ed-4893-9a9e-8d85bce73e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27256
23485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.2725623485
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.791441100
Short name T548
Test name
Test status
Simulation time 8490796665 ps
CPU time 8.21 seconds
Started Apr 15 03:12:31 PM PDT 24
Finished Apr 15 03:12:39 PM PDT 24
Peak memory 204060 kb
Host smart-bdfec0be-300b-494f-ad3f-b02f4ad39ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79144
1100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.791441100
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.1760114062
Short name T639
Test name
Test status
Simulation time 8421032766 ps
CPU time 8.49 seconds
Started Apr 15 03:12:32 PM PDT 24
Finished Apr 15 03:12:41 PM PDT 24
Peak memory 204204 kb
Host smart-b55c3656-8888-444e-81d0-9be2dca81f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17601
14062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.1760114062
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.3691040768
Short name T1068
Test name
Test status
Simulation time 8383538283 ps
CPU time 8.39 seconds
Started Apr 15 03:12:33 PM PDT 24
Finished Apr 15 03:12:41 PM PDT 24
Peak memory 204076 kb
Host smart-6bc5cd95-d735-482b-af2b-fd3a423730f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36910
40768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.3691040768
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.2478657125
Short name T1030
Test name
Test status
Simulation time 8366154030 ps
CPU time 8.1 seconds
Started Apr 15 03:12:34 PM PDT 24
Finished Apr 15 03:12:42 PM PDT 24
Peak memory 204028 kb
Host smart-616f048f-8e0b-4172-8a8d-6c517a8f482d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24786
57125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.2478657125
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.1570970119
Short name T727
Test name
Test status
Simulation time 8434659306 ps
CPU time 7.87 seconds
Started Apr 15 03:12:28 PM PDT 24
Finished Apr 15 03:12:36 PM PDT 24
Peak memory 204024 kb
Host smart-404bc6c1-a1fd-4120-9049-a84a71ff77e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15709
70119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.1570970119
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.109050744
Short name T32
Test name
Test status
Simulation time 8396272289 ps
CPU time 8.86 seconds
Started Apr 15 03:12:34 PM PDT 24
Finished Apr 15 03:12:44 PM PDT 24
Peak memory 204196 kb
Host smart-013c49ea-ed85-4f3a-85ae-c45b41352a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10905
0744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.109050744
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.2516950752
Short name T1306
Test name
Test status
Simulation time 8380678513 ps
CPU time 8.05 seconds
Started Apr 15 03:12:41 PM PDT 24
Finished Apr 15 03:12:50 PM PDT 24
Peak memory 204044 kb
Host smart-99fe8a6b-2e01-4ab9-a265-78a9da88f46b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25169
50752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.2516950752
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.128867391
Short name T1241
Test name
Test status
Simulation time 8483367264 ps
CPU time 8.53 seconds
Started Apr 15 03:12:50 PM PDT 24
Finished Apr 15 03:12:59 PM PDT 24
Peak memory 204028 kb
Host smart-1e2c4c4d-7249-40a2-b774-39559ccac27e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=128867391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.128867391
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.2674653636
Short name T578
Test name
Test status
Simulation time 8375785047 ps
CPU time 8.63 seconds
Started Apr 15 03:12:51 PM PDT 24
Finished Apr 15 03:13:00 PM PDT 24
Peak memory 204016 kb
Host smart-6bd113f7-0d89-40c4-a33c-2ce16ae0821a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2674653636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.2674653636
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.2005949685
Short name T1127
Test name
Test status
Simulation time 8444938818 ps
CPU time 8.19 seconds
Started Apr 15 03:12:56 PM PDT 24
Finished Apr 15 03:13:04 PM PDT 24
Peak memory 204044 kb
Host smart-f5cf8d9c-0c23-4894-9ca2-41f0874e115e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20059
49685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.2005949685
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.385519327
Short name T847
Test name
Test status
Simulation time 8370541465 ps
CPU time 9.55 seconds
Started Apr 15 03:12:39 PM PDT 24
Finished Apr 15 03:12:49 PM PDT 24
Peak memory 204048 kb
Host smart-5bd338c4-69bc-448c-90aa-023646e45244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38551
9327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.385519327
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_enable.597811139
Short name T637
Test name
Test status
Simulation time 8382753736 ps
CPU time 8.07 seconds
Started Apr 15 03:12:42 PM PDT 24
Finished Apr 15 03:12:51 PM PDT 24
Peak memory 204060 kb
Host smart-ae25d212-99b9-4e6e-a4f4-a006b5bc3567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59781
1139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.597811139
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1262256706
Short name T865
Test name
Test status
Simulation time 142424300 ps
CPU time 1.35 seconds
Started Apr 15 03:12:41 PM PDT 24
Finished Apr 15 03:12:43 PM PDT 24
Peak memory 204100 kb
Host smart-9b10ad6e-e538-41e0-8673-38ba854f7b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12622
56706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1262256706
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.719311696
Short name T358
Test name
Test status
Simulation time 8434455847 ps
CPU time 7.71 seconds
Started Apr 15 03:12:49 PM PDT 24
Finished Apr 15 03:12:58 PM PDT 24
Peak memory 204048 kb
Host smart-ab5f1308-7628-46ad-8183-5e82538c56fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71931
1696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.719311696
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1297624320
Short name T177
Test name
Test status
Simulation time 8364118219 ps
CPU time 8.2 seconds
Started Apr 15 03:12:50 PM PDT 24
Finished Apr 15 03:12:59 PM PDT 24
Peak memory 204048 kb
Host smart-ba384d1e-a75c-4cf1-9744-f8a5440e154a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12976
24320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1297624320
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3128476550
Short name T470
Test name
Test status
Simulation time 8451671393 ps
CPU time 7.79 seconds
Started Apr 15 03:12:42 PM PDT 24
Finished Apr 15 03:12:50 PM PDT 24
Peak memory 203984 kb
Host smart-b4da5f02-74c5-4d47-97a3-f38d7ab3c7e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31284
76550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3128476550
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.647185992
Short name T515
Test name
Test status
Simulation time 8415838041 ps
CPU time 7.75 seconds
Started Apr 15 03:12:43 PM PDT 24
Finished Apr 15 03:12:52 PM PDT 24
Peak memory 203976 kb
Host smart-d6409ff7-ae46-4108-8dbf-082462745d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64718
5992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.647185992
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.3086998432
Short name T278
Test name
Test status
Simulation time 8381961460 ps
CPU time 7.8 seconds
Started Apr 15 03:12:46 PM PDT 24
Finished Apr 15 03:12:54 PM PDT 24
Peak memory 204208 kb
Host smart-7186cb5e-31c4-48c8-abae-31106d8dc87a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30869
98432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3086998432
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.2318228570
Short name T81
Test name
Test status
Simulation time 8503760715 ps
CPU time 8.7 seconds
Started Apr 15 03:12:43 PM PDT 24
Finished Apr 15 03:12:52 PM PDT 24
Peak memory 204048 kb
Host smart-94dba1f7-0f9d-48c1-beae-84407727db73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23182
28570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.2318228570
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.3333023993
Short name T1233
Test name
Test status
Simulation time 8392120032 ps
CPU time 9.38 seconds
Started Apr 15 03:12:47 PM PDT 24
Finished Apr 15 03:12:57 PM PDT 24
Peak memory 203884 kb
Host smart-fdae6588-6622-4ea6-b108-9529702bdeca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33330
23993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.3333023993
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.4123248815
Short name T491
Test name
Test status
Simulation time 8386900666 ps
CPU time 7.75 seconds
Started Apr 15 03:12:47 PM PDT 24
Finished Apr 15 03:12:55 PM PDT 24
Peak memory 204060 kb
Host smart-468e1b75-cd6a-48a5-b6da-2dee4ee0540d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41232
48815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.4123248815
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.3201225617
Short name T1236
Test name
Test status
Simulation time 8417088953 ps
CPU time 8.54 seconds
Started Apr 15 03:12:50 PM PDT 24
Finished Apr 15 03:12:59 PM PDT 24
Peak memory 204012 kb
Host smart-5c2fd394-eb07-4ba0-b663-8d57906f6682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32012
25617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.3201225617
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.3453186287
Short name T702
Test name
Test status
Simulation time 8382956900 ps
CPU time 8.12 seconds
Started Apr 15 03:12:48 PM PDT 24
Finished Apr 15 03:12:57 PM PDT 24
Peak memory 204028 kb
Host smart-02e955fe-7905-4269-8e99-a022b0a03a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34531
86287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.3453186287
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.3217663836
Short name T45
Test name
Test status
Simulation time 43351066 ps
CPU time 0.65 seconds
Started Apr 15 03:12:52 PM PDT 24
Finished Apr 15 03:12:53 PM PDT 24
Peak memory 203896 kb
Host smart-b1c66982-1257-435d-afdc-8de1a1486d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32176
63836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3217663836
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.707321064
Short name T13
Test name
Test status
Simulation time 22638621358 ps
CPU time 45.07 seconds
Started Apr 15 03:12:46 PM PDT 24
Finished Apr 15 03:13:31 PM PDT 24
Peak memory 204344 kb
Host smart-56717d4b-01e8-48f8-b603-3756a42300ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70732
1064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.707321064
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.3299525504
Short name T1232
Test name
Test status
Simulation time 8387284562 ps
CPU time 8.54 seconds
Started Apr 15 03:12:47 PM PDT 24
Finished Apr 15 03:12:56 PM PDT 24
Peak memory 204052 kb
Host smart-729cd6da-9770-47ef-84de-ae4c3d1b5810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32995
25504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.3299525504
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.1808331486
Short name T831
Test name
Test status
Simulation time 8438376760 ps
CPU time 8.82 seconds
Started Apr 15 03:12:48 PM PDT 24
Finished Apr 15 03:12:57 PM PDT 24
Peak memory 204052 kb
Host smart-41b05f3a-b773-454c-8b75-d994c554f1d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18083
31486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1808331486
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.2813131975
Short name T901
Test name
Test status
Simulation time 8373155129 ps
CPU time 7.55 seconds
Started Apr 15 03:12:46 PM PDT 24
Finished Apr 15 03:12:54 PM PDT 24
Peak memory 204024 kb
Host smart-d0fe756a-9410-429b-9ca4-2e172de68c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28131
31975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.2813131975
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.3917199929
Short name T638
Test name
Test status
Simulation time 8384513241 ps
CPU time 9.77 seconds
Started Apr 15 03:12:51 PM PDT 24
Finished Apr 15 03:13:01 PM PDT 24
Peak memory 204004 kb
Host smart-c1ff22e4-fce4-48ad-976b-431a45e4d929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39171
99929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.3917199929
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2640814022
Short name T28
Test name
Test status
Simulation time 8373162912 ps
CPU time 8.08 seconds
Started Apr 15 03:12:55 PM PDT 24
Finished Apr 15 03:13:04 PM PDT 24
Peak memory 204044 kb
Host smart-feb627a6-810f-4abc-bc6f-b7f70781f4f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26408
14022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2640814022
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.3125522709
Short name T1338
Test name
Test status
Simulation time 8438111516 ps
CPU time 8.97 seconds
Started Apr 15 03:12:40 PM PDT 24
Finished Apr 15 03:12:50 PM PDT 24
Peak memory 204052 kb
Host smart-76d5f4c4-8cb8-4b5a-a0c6-c3eefd1a33a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31255
22709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.3125522709
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.3876682505
Short name T1045
Test name
Test status
Simulation time 8407937451 ps
CPU time 8.54 seconds
Started Apr 15 03:12:47 PM PDT 24
Finished Apr 15 03:12:56 PM PDT 24
Peak memory 204044 kb
Host smart-1cc0d526-0ccb-4078-baa8-22c85a8fb279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38766
82505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.3876682505
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.2554909500
Short name T961
Test name
Test status
Simulation time 8415929442 ps
CPU time 7.95 seconds
Started Apr 15 03:12:50 PM PDT 24
Finished Apr 15 03:12:59 PM PDT 24
Peak memory 204028 kb
Host smart-fbe25366-7c14-45b4-8b2c-e59cb86e63b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25549
09500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2554909500
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.max_length_in_transaction.4177745172
Short name T1067
Test name
Test status
Simulation time 8504109599 ps
CPU time 8.56 seconds
Started Apr 15 03:13:07 PM PDT 24
Finished Apr 15 03:13:16 PM PDT 24
Peak memory 204028 kb
Host smart-de8c5dd6-279a-4356-8b33-694af754c600
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4177745172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.4177745172
Directory /workspace/9.max_length_in_transaction/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.3114901128
Short name T452
Test name
Test status
Simulation time 8391881574 ps
CPU time 7.95 seconds
Started Apr 15 03:13:06 PM PDT 24
Finished Apr 15 03:13:14 PM PDT 24
Peak memory 204052 kb
Host smart-603f3c71-a31c-44bd-88c4-babc1cd49495
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3114901128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.3114901128
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.3567511896
Short name T1074
Test name
Test status
Simulation time 8459824800 ps
CPU time 8.01 seconds
Started Apr 15 03:13:08 PM PDT 24
Finished Apr 15 03:13:17 PM PDT 24
Peak memory 204076 kb
Host smart-2ad16e1d-a8e2-481d-a3ea-b081195b4bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35675
11896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.3567511896
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.3861601063
Short name T1042
Test name
Test status
Simulation time 8376242699 ps
CPU time 8.04 seconds
Started Apr 15 03:12:55 PM PDT 24
Finished Apr 15 03:13:03 PM PDT 24
Peak memory 204036 kb
Host smart-83dd4269-3f26-4e03-857e-003331b8f5a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38616
01063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.3861601063
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_enable.965663221
Short name T306
Test name
Test status
Simulation time 8372405020 ps
CPU time 7.84 seconds
Started Apr 15 03:12:53 PM PDT 24
Finished Apr 15 03:13:01 PM PDT 24
Peak memory 204068 kb
Host smart-97744984-032d-45d7-91ae-d881abb28fb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96566
3221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.965663221
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.402563731
Short name T369
Test name
Test status
Simulation time 72715612 ps
CPU time 1.7 seconds
Started Apr 15 03:12:57 PM PDT 24
Finished Apr 15 03:13:00 PM PDT 24
Peak memory 204100 kb
Host smart-d791bda3-33bd-4d60-888b-521ee45f887f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40256
3731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.402563731
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.3270174403
Short name T1071
Test name
Test status
Simulation time 8460018210 ps
CPU time 9.14 seconds
Started Apr 15 03:13:06 PM PDT 24
Finished Apr 15 03:13:16 PM PDT 24
Peak memory 204080 kb
Host smart-04c0d0ff-3733-4ed4-9f52-72e516e52c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32701
74403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.3270174403
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.562045145
Short name T6
Test name
Test status
Simulation time 8362159981 ps
CPU time 7.54 seconds
Started Apr 15 03:13:05 PM PDT 24
Finished Apr 15 03:13:12 PM PDT 24
Peak memory 204048 kb
Host smart-4f020988-7d6a-4f03-9d02-a35906e40427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56204
5145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.562045145
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.3041692503
Short name T688
Test name
Test status
Simulation time 8522312450 ps
CPU time 7.76 seconds
Started Apr 15 03:12:57 PM PDT 24
Finished Apr 15 03:13:05 PM PDT 24
Peak memory 204016 kb
Host smart-c9346aa6-019f-460e-812a-5a3b7749eb65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30416
92503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3041692503
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.1321492719
Short name T1262
Test name
Test status
Simulation time 8413512868 ps
CPU time 9.05 seconds
Started Apr 15 03:12:57 PM PDT 24
Finished Apr 15 03:13:06 PM PDT 24
Peak memory 204032 kb
Host smart-efcdbb10-7eac-4183-b0b5-13681362498e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13214
92719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1321492719
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.1692959704
Short name T1231
Test name
Test status
Simulation time 8370852242 ps
CPU time 8.24 seconds
Started Apr 15 03:12:56 PM PDT 24
Finished Apr 15 03:13:05 PM PDT 24
Peak memory 204076 kb
Host smart-43f2836a-48f9-461f-9db0-34e724905016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16929
59704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.1692959704
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.3586173182
Short name T1293
Test name
Test status
Simulation time 8457762771 ps
CPU time 8.88 seconds
Started Apr 15 03:12:59 PM PDT 24
Finished Apr 15 03:13:09 PM PDT 24
Peak memory 204060 kb
Host smart-1ab21d10-a98b-4a39-aa7e-7a52608467f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35861
73182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.3586173182
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.248409084
Short name T362
Test name
Test status
Simulation time 8394966623 ps
CPU time 9.46 seconds
Started Apr 15 03:12:58 PM PDT 24
Finished Apr 15 03:13:08 PM PDT 24
Peak memory 204056 kb
Host smart-b6d513fa-9848-4026-976d-3a4198ce2daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24840
9084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.248409084
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.935113761
Short name T641
Test name
Test status
Simulation time 8403507308 ps
CPU time 9.45 seconds
Started Apr 15 03:12:58 PM PDT 24
Finished Apr 15 03:13:08 PM PDT 24
Peak memory 204052 kb
Host smart-2a7ebca6-d6a0-44ce-9307-867b9697322c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93511
3761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.935113761
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.3072701393
Short name T151
Test name
Test status
Simulation time 8393268759 ps
CPU time 8.66 seconds
Started Apr 15 03:13:03 PM PDT 24
Finished Apr 15 03:13:12 PM PDT 24
Peak memory 204020 kb
Host smart-a8818b5a-accb-43c1-80c3-e10a7605dc50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30727
01393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.3072701393
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.1963440655
Short name T24
Test name
Test status
Simulation time 8374276402 ps
CPU time 7.63 seconds
Started Apr 15 03:13:03 PM PDT 24
Finished Apr 15 03:13:11 PM PDT 24
Peak memory 204060 kb
Host smart-06be00fc-ef9f-4ed4-963f-65f0a0ba1210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19634
40655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.1963440655
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.2453147271
Short name T44
Test name
Test status
Simulation time 41564375 ps
CPU time 0.67 seconds
Started Apr 15 03:13:06 PM PDT 24
Finished Apr 15 03:13:07 PM PDT 24
Peak memory 203904 kb
Host smart-e61f176b-8dfd-4c48-8b0b-5ad865ba9752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24531
47271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.2453147271
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.39733404
Short name T613
Test name
Test status
Simulation time 25145685353 ps
CPU time 50.33 seconds
Started Apr 15 03:13:04 PM PDT 24
Finished Apr 15 03:13:54 PM PDT 24
Peak memory 204340 kb
Host smart-1755efa2-fb17-4fa4-a251-167b3103f60c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39733
404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.39733404
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.1909996426
Short name T591
Test name
Test status
Simulation time 8404614291 ps
CPU time 9.18 seconds
Started Apr 15 03:13:01 PM PDT 24
Finished Apr 15 03:13:11 PM PDT 24
Peak memory 203984 kb
Host smart-2d661d6c-4875-436c-877a-9953f8a932b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19099
96426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.1909996426
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.2230843972
Short name T1282
Test name
Test status
Simulation time 8446956339 ps
CPU time 8.3 seconds
Started Apr 15 03:13:03 PM PDT 24
Finished Apr 15 03:13:12 PM PDT 24
Peak memory 204076 kb
Host smart-f00f6685-22b6-4013-9564-a796f8c6fe8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22308
43972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.2230843972
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.3980265297
Short name T40
Test name
Test status
Simulation time 8416086793 ps
CPU time 9.2 seconds
Started Apr 15 03:13:06 PM PDT 24
Finished Apr 15 03:13:16 PM PDT 24
Peak memory 204024 kb
Host smart-e809aa46-e491-482f-a0cb-5e105b9cf432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39802
65297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.3980265297
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.2524016393
Short name T757
Test name
Test status
Simulation time 8385802373 ps
CPU time 7.87 seconds
Started Apr 15 03:13:02 PM PDT 24
Finished Apr 15 03:13:10 PM PDT 24
Peak memory 204068 kb
Host smart-27380bf2-293d-41ea-9ec5-eead7980d200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25240
16393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.2524016393
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.368313956
Short name T394
Test name
Test status
Simulation time 8371822114 ps
CPU time 9.34 seconds
Started Apr 15 03:13:02 PM PDT 24
Finished Apr 15 03:13:12 PM PDT 24
Peak memory 204020 kb
Host smart-3d461283-00de-4bbd-b429-e2935978bff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36831
3956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.368313956
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.1985842017
Short name T1379
Test name
Test status
Simulation time 8456638016 ps
CPU time 8.59 seconds
Started Apr 15 03:12:55 PM PDT 24
Finished Apr 15 03:13:04 PM PDT 24
Peak memory 204004 kb
Host smart-c94deeba-9210-443d-a628-4dc43645d7e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19858
42017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.1985842017
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.2237238536
Short name T1150
Test name
Test status
Simulation time 8423769173 ps
CPU time 8.13 seconds
Started Apr 15 03:13:03 PM PDT 24
Finished Apr 15 03:13:12 PM PDT 24
Peak memory 204024 kb
Host smart-1b000211-e944-409e-b0fa-db22a7614302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22372
38536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.2237238536
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.1174318029
Short name T1169
Test name
Test status
Simulation time 8417969788 ps
CPU time 9.09 seconds
Started Apr 15 03:13:03 PM PDT 24
Finished Apr 15 03:13:12 PM PDT 24
Peak memory 204080 kb
Host smart-a0a6f464-ecff-4fcf-be95-5b13f8f87335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11743
18029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.1174318029
Directory /workspace/9.usbdev_stall_trans/latest
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