Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	25450	1		T1	2		T2	3		T3	2
all_pins[1]	25450	1		T1	2		T2	3		T3	2
all_pins[2]	25450	1		T1	2		T2	3		T3	2
all_pins[3]	25450	1		T1	2		T2	3		T3	2
all_pins[4]	25450	1		T1	2		T2	3		T3	2
all_pins[5]	25450	1		T1	2		T2	3		T3	2
all_pins[6]	25450	1		T1	2		T2	3		T3	2
all_pins[7]	25450	1		T1	2		T2	3		T3	2
all_pins[8]	25450	1		T1	2		T2	3		T3	2
all_pins[9]	25450	1		T1	2		T2	3		T3	2
all_pins[10]	25450	1		T1	2		T2	3		T3	2
all_pins[11]	25450	1		T1	2		T2	3		T3	2
all_pins[12]	25450	1		T1	2		T2	3		T3	2
all_pins[13]	25450	1		T1	2		T2	3		T3	2
all_pins[14]	25450	1		T1	2		T2	3		T3	2
all_pins[15]	25450	1		T1	2		T2	3		T3	2
all_pins[16]	25450	1		T1	2		T2	3		T3	2
all_pins[17]	25450	1		T1	2		T2	3		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	456736	1		T1	36		T2	54		T3	36
values[0x1]	1364	1		T10	1		T38	1		T55	1
transitions[0x0=>0x1]	1085	1		T10	1		T38	1		T55	1
transitions[0x1=>0x0]	1098	1		T10	1		T38	1		T55	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	25285	1		T1	2		T2	3		T3	2
all_pins[0]	values[0x1]	165	1		T10	1		T55	1		T89	1
all_pins[0]	transitions[0x0=>0x1]	148	1		T10	1		T55	1		T89	1
all_pins[0]	transitions[0x1=>0x0]	138	1		T38	1		T56	1		T57	1
all_pins[1]	values[0x0]	25295	1		T1	2		T2	3		T3	2
all_pins[1]	values[0x1]	155	1		T38	1		T56	1		T57	1
all_pins[1]	transitions[0x0=>0x1]	143	1		T38	1		T56	1		T57	1
all_pins[1]	transitions[0x1=>0x0]	59	1		T71	1		T72	3		T73	1
all_pins[2]	values[0x0]	25379	1		T1	2		T2	3		T3	2
all_pins[2]	values[0x1]	71	1		T71	1		T72	3		T73	2
all_pins[2]	transitions[0x0=>0x1]	55	1		T71	1		T72	3		T73	2
all_pins[2]	transitions[0x1=>0x0]	62	1		T73	3		T75	2		T259	1
all_pins[3]	values[0x0]	25372	1		T1	2		T2	3		T3	2
all_pins[3]	values[0x1]	78	1		T73	3		T75	2		T259	1
all_pins[3]	transitions[0x0=>0x1]	55	1		T73	3		T75	2		T263	1
all_pins[3]	transitions[0x1=>0x0]	37	1		T72	1		T73	2		T259	4
all_pins[4]	values[0x0]	25390	1		T1	2		T2	3		T3	2
all_pins[4]	values[0x1]	60	1		T72	1		T73	2		T259	5
all_pins[4]	transitions[0x0=>0x1]	46	1		T72	1		T73	2		T259	5
all_pins[4]	transitions[0x1=>0x0]	57	1		T71	1		T74	1		T73	3
all_pins[5]	values[0x0]	25379	1		T1	2		T2	3		T3	2
all_pins[5]	values[0x1]	71	1		T71	1		T74	1		T73	3
all_pins[5]	transitions[0x0=>0x1]	53	1		T71	1		T74	1		T73	2
all_pins[5]	transitions[0x1=>0x0]	35	1		T72	2		T73	1		T262	1
all_pins[6]	values[0x0]	25397	1		T1	2		T2	3		T3	2
all_pins[6]	values[0x1]	53	1		T72	2		T73	2		T75	1
all_pins[6]	transitions[0x0=>0x1]	45	1		T72	2		T73	1		T75	1
all_pins[6]	transitions[0x1=>0x0]	56	1		T71	1		T73	1		T75	1
all_pins[7]	values[0x0]	25386	1		T1	2		T2	3		T3	2
all_pins[7]	values[0x1]	64	1		T71	1		T73	2		T75	1
all_pins[7]	transitions[0x0=>0x1]	54	1		T71	1		T73	2		T262	4
all_pins[7]	transitions[0x1=>0x0]	39	1		T71	1		T74	2		T72	2
all_pins[8]	values[0x0]	25401	1		T1	2		T2	3		T3	2
all_pins[8]	values[0x1]	49	1		T71	1		T74	2		T72	2
all_pins[8]	transitions[0x0=>0x1]	41	1		T71	1		T74	2		T73	2
all_pins[8]	transitions[0x1=>0x0]	59	1		T72	2		T73	3		T259	3
all_pins[9]	values[0x0]	25383	1		T1	2		T2	3		T3	2
all_pins[9]	values[0x1]	67	1		T72	4		T73	3		T259	3
all_pins[9]	transitions[0x0=>0x1]	53	1		T72	4		T73	2		T259	2
all_pins[9]	transitions[0x1=>0x0]	57	1		T73	2		T75	1		T262	1
all_pins[10]	values[0x0]	25379	1		T1	2		T2	3		T3	2
all_pins[10]	values[0x1]	71	1		T73	3		T75	1		T259	1
all_pins[10]	transitions[0x0=>0x1]	60	1		T73	3		T75	1		T259	1
all_pins[10]	transitions[0x1=>0x0]	47	1		T74	1		T259	4		T262	2
all_pins[11]	values[0x0]	25392	1		T1	2		T2	3		T3	2
all_pins[11]	values[0x1]	58	1		T74	1		T259	4		T262	2
all_pins[11]	transitions[0x0=>0x1]	36	1		T74	1		T259	3		T271	1
all_pins[11]	transitions[0x1=>0x0]	51	1		T74	1		T72	3		T73	1
all_pins[12]	values[0x0]	25377	1		T1	2		T2	3		T3	2
all_pins[12]	values[0x1]	73	1		T74	1		T72	3		T73	1
all_pins[12]	transitions[0x0=>0x1]	54	1		T74	1		T72	3		T73	1
all_pins[12]	transitions[0x1=>0x0]	35	1		T73	1		T262	1		T261	1
all_pins[13]	values[0x0]	25396	1		T1	2		T2	3		T3	2
all_pins[13]	values[0x1]	54	1		T73	1		T262	3		T261	3
all_pins[13]	transitions[0x0=>0x1]	44	1		T73	1		T262	3		T261	3
all_pins[13]	transitions[0x1=>0x0]	46	1		T72	1		T73	4		T75	4
all_pins[14]	values[0x0]	25394	1		T1	2		T2	3		T3	2
all_pins[14]	values[0x1]	56	1		T72	1		T73	4		T75	4
all_pins[14]	transitions[0x0=>0x1]	40	1		T72	1		T73	2		T75	3
all_pins[14]	transitions[0x1=>0x0]	63	1		T72	2		T73	3		T75	1
all_pins[15]	values[0x0]	25371	1		T1	2		T2	3		T3	2
all_pins[15]	values[0x1]	79	1		T72	2		T73	5		T75	2
all_pins[15]	transitions[0x0=>0x1]	59	1		T72	2		T73	2		T75	2
all_pins[15]	transitions[0x1=>0x0]	52	1		T74	2		T259	1		T262	2
all_pins[16]	values[0x0]	25378	1		T1	2		T2	3		T3	2
all_pins[16]	values[0x1]	72	1		T74	2		T73	3		T259	2
all_pins[16]	transitions[0x0=>0x1]	54	1		T74	2		T73	1		T259	1
all_pins[16]	transitions[0x1=>0x0]	50	1		T74	1		T73	2		T259	2
all_pins[17]	values[0x0]	25382	1		T1	2		T2	3		T3	2
all_pins[17]	values[0x1]	68	1		T74	1		T73	4		T259	3
all_pins[17]	transitions[0x0=>0x1]	45	1		T74	1		T73	4		T259	1
all_pins[17]	transitions[0x1=>0x0]	155	1		T10	1		T55	1		T89	1