Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1		T71	4		T74	4		T72	4
all_values[1]	281	1		T71	4		T74	4		T72	4
all_values[2]	281	1		T71	4		T74	4		T72	4
all_values[3]	281	1		T71	4		T74	4		T72	4
all_values[4]	281	1		T71	4		T74	4		T72	4
all_values[5]	281	1		T71	4		T74	4		T72	4
all_values[6]	281	1		T71	4		T74	4		T72	4
all_values[7]	281	1		T71	4		T74	4		T72	4
all_values[8]	281	1		T71	4		T74	4		T72	4
all_values[9]	281	1		T71	4		T74	4		T72	4
all_values[10]	281	1		T71	4		T74	4		T72	4
all_values[11]	281	1		T71	4		T74	4		T72	4
all_values[12]	281	1		T71	4		T74	4		T72	4
all_values[13]	281	1		T71	4		T74	4		T72	4
all_values[14]	281	1		T71	4		T74	4		T72	4
all_values[15]	281	1		T71	4		T74	4		T72	4
all_values[16]	281	1		T71	4		T74	4		T72	4
all_values[17]	281	1		T71	4		T74	4		T72	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2734	1		T71	31		T74	59		T72	39
auto[1]	2324	1		T71	41		T74	13		T72	33

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	929	1		T71	14		T74	9		T72	14
auto[1]	4129	1		T71	58		T74	63		T72	58

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2986	1		T71	45		T74	39		T72	49
auto[1]	2072	1		T71	27		T74	33		T72	23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	29	1		T74	1		T261	1		T263	1
all_values[0]	auto[0]	auto[0]	auto[1]	58	1		T71	2		T74	1		T73	1
all_values[0]	auto[0]	auto[1]	auto[0]	14	1		T71	1		T263	1		T270	1
all_values[0]	auto[0]	auto[1]	auto[1]	53	1		T72	2		T73	1		T75	2
all_values[0]	auto[1]	auto[0]	auto[1]	68	1		T74	1		T72	1		T73	4
all_values[0]	auto[1]	auto[1]	auto[1]	59	1		T71	1		T74	1		T72	1
all_values[1]	auto[0]	auto[0]	auto[0]	34	1		T74	2		T75	2		T259	3
all_values[1]	auto[0]	auto[0]	auto[1]	65	1		T71	2		T72	2		T73	1
all_values[1]	auto[0]	auto[1]	auto[0]	22	1		T75	1		T259	2		T260	3
all_values[1]	auto[0]	auto[1]	auto[1]	52	1		T74	1		T72	1		T73	1
all_values[1]	auto[1]	auto[0]	auto[1]	63	1		T71	2		T72	1		T73	4
all_values[1]	auto[1]	auto[1]	auto[1]	45	1		T74	1		T73	1		T75	1
all_values[2]	auto[0]	auto[0]	auto[0]	35	1		T74	1		T72	1		T259	2
all_values[2]	auto[0]	auto[0]	auto[1]	60	1		T71	2		T74	2		T73	3
all_values[2]	auto[0]	auto[1]	auto[0]	21	1		T259	1		T262	1		T263	1
all_values[2]	auto[0]	auto[1]	auto[1]	49	1		T72	2		T73	1		T75	2
all_values[2]	auto[1]	auto[0]	auto[1]	52	1		T71	1		T74	1		T72	1
all_values[2]	auto[1]	auto[1]	auto[1]	64	1		T71	1		T73	1		T75	1
all_values[3]	auto[0]	auto[0]	auto[0]	24	1		T75	3		T259	2		T262	1
all_values[3]	auto[0]	auto[0]	auto[1]	61	1		T74	2		T73	2		T259	1
all_values[3]	auto[0]	auto[1]	auto[0]	18	1		T71	2		T75	1		T260	3
all_values[3]	auto[0]	auto[1]	auto[1]	52	1		T71	1		T74	1		T72	2
all_values[3]	auto[1]	auto[0]	auto[1]	58	1		T74	1		T72	2		T73	2
all_values[3]	auto[1]	auto[1]	auto[1]	68	1		T71	1		T75	1		T259	2
all_values[4]	auto[0]	auto[0]	auto[0]	27	1		T72	1		T73	1		T75	1
all_values[4]	auto[0]	auto[0]	auto[1]	60	1		T71	1		T74	3		T72	1
all_values[4]	auto[0]	auto[1]	auto[0]	28	1		T264	1		T272	1		T273	2
all_values[4]	auto[0]	auto[1]	auto[1]	51	1		T71	1		T72	1		T73	2
all_values[4]	auto[1]	auto[0]	auto[1]	68	1		T71	1		T74	1		T73	3
all_values[4]	auto[1]	auto[1]	auto[1]	47	1		T71	1		T72	1		T73	1
all_values[5]	auto[0]	auto[0]	auto[0]	30	1		T72	1		T73	1		T259	1
all_values[5]	auto[0]	auto[0]	auto[1]	59	1		T71	1		T74	2		T72	1
all_values[5]	auto[0]	auto[1]	auto[0]	13	1		T72	1		T260	3		T270	1
all_values[5]	auto[0]	auto[1]	auto[1]	67	1		T71	1		T73	4		T75	3
all_values[5]	auto[1]	auto[0]	auto[1]	60	1		T74	2		T73	1		T75	3
all_values[5]	auto[1]	auto[1]	auto[1]	52	1		T71	2		T72	1		T73	1
all_values[6]	auto[0]	auto[0]	auto[0]	39	1		T72	1		T75	1		T259	4
all_values[6]	auto[0]	auto[0]	auto[1]	62	1		T74	1		T72	1		T73	2
all_values[6]	auto[0]	auto[1]	auto[0]	22	1		T71	1		T75	1		T260	2
all_values[6]	auto[0]	auto[1]	auto[1]	54	1		T71	2		T72	1		T73	3
all_values[6]	auto[1]	auto[0]	auto[1]	55	1		T71	1		T74	2		T73	2
all_values[6]	auto[1]	auto[1]	auto[1]	49	1		T74	1		T72	1		T75	1
all_values[7]	auto[0]	auto[0]	auto[0]	25	1		T72	1		T73	1		T75	1
all_values[7]	auto[0]	auto[0]	auto[1]	57	1		T74	3		T72	1		T75	1
all_values[7]	auto[0]	auto[1]	auto[0]	19	1		T71	2		T260	1		T263	1
all_values[7]	auto[0]	auto[1]	auto[1]	71	1		T71	1		T72	1		T73	4
all_values[7]	auto[1]	auto[0]	auto[1]	55	1		T74	1		T75	1		T259	1
all_values[7]	auto[1]	auto[1]	auto[1]	54	1		T71	1		T72	1		T73	2
all_values[8]	auto[0]	auto[0]	auto[0]	35	1		T259	1		T274	2		T270	4
all_values[8]	auto[0]	auto[0]	auto[1]	54	1		T74	1		T72	1		T73	1
all_values[8]	auto[0]	auto[1]	auto[0]	28	1		T260	1		T266	1		T264	1
all_values[8]	auto[0]	auto[1]	auto[1]	53	1		T71	3		T73	2		T75	1
all_values[8]	auto[1]	auto[0]	auto[1]	69	1		T74	2		T72	1		T73	2
all_values[8]	auto[1]	auto[1]	auto[1]	42	1		T71	1		T74	1		T72	2
all_values[9]	auto[0]	auto[0]	auto[0]	26	1		T71	3		T73	1		T75	2
all_values[9]	auto[0]	auto[0]	auto[1]	58	1		T74	2		T73	2		T259	2
all_values[9]	auto[0]	auto[1]	auto[0]	15	1		T71	1		T262	1		T263	2
all_values[9]	auto[0]	auto[1]	auto[1]	63	1		T72	3		T73	2		T75	3
all_values[9]	auto[1]	auto[0]	auto[1]	67	1		T74	2		T72	1		T75	1
all_values[9]	auto[1]	auto[1]	auto[1]	52	1		T73	2		T75	1		T259	2
all_values[10]	auto[0]	auto[0]	auto[0]	31	1		T73	1		T75	1		T262	1
all_values[10]	auto[0]	auto[0]	auto[1]	61	1		T71	1		T74	2		T72	1
all_values[10]	auto[0]	auto[1]	auto[0]	19	1		T262	1		T261	2		T275	4
all_values[10]	auto[0]	auto[1]	auto[1]	53	1		T71	1		T72	2		T73	2
all_values[10]	auto[1]	auto[0]	auto[1]	65	1		T71	1		T74	2		T72	1
all_values[10]	auto[1]	auto[1]	auto[1]	52	1		T71	1		T73	3		T75	1
all_values[11]	auto[0]	auto[0]	auto[0]	31	1		T72	1		T260	1		T261	1
all_values[11]	auto[0]	auto[0]	auto[1]	61	1		T74	1		T72	2		T73	4
all_values[11]	auto[0]	auto[1]	auto[0]	16	1		T267	2		T268	1		T269	1
all_values[11]	auto[0]	auto[1]	auto[1]	59	1		T71	3		T75	3		T259	2
all_values[11]	auto[1]	auto[0]	auto[1]	65	1		T74	2		T72	1		T73	3
all_values[11]	auto[1]	auto[1]	auto[1]	49	1		T71	1		T74	1		T259	2
all_values[12]	auto[0]	auto[0]	auto[0]	27	1		T71	1		T73	1		T262	1
all_values[12]	auto[0]	auto[0]	auto[1]	51	1		T74	1		T73	2		T75	1
all_values[12]	auto[0]	auto[1]	auto[0]	18	1		T266	1		T264	2		T270	1
all_values[12]	auto[0]	auto[1]	auto[1]	59	1		T71	1		T72	2		T75	3
all_values[12]	auto[1]	auto[0]	auto[1]	75	1		T74	3		T72	1		T73	2
all_values[12]	auto[1]	auto[1]	auto[1]	51	1		T71	2		T72	1		T73	2
all_values[13]	auto[0]	auto[0]	auto[0]	41	1		T71	1		T74	1		T72	2
all_values[13]	auto[0]	auto[0]	auto[1]	50	1		T71	1		T73	1		T259	3
all_values[13]	auto[0]	auto[1]	auto[0]	27	1		T71	1		T75	1		T260	2
all_values[13]	auto[0]	auto[1]	auto[1]	53	1		T74	2		T72	1		T73	4
all_values[13]	auto[1]	auto[0]	auto[1]	68	1		T71	1		T74	1		T72	1
all_values[13]	auto[1]	auto[1]	auto[1]	42	1		T73	1		T75	1		T259	1
all_values[14]	auto[0]	auto[0]	auto[0]	43	1		T74	1		T72	1		T75	1
all_values[14]	auto[0]	auto[0]	auto[1]	58	1		T74	1		T72	1		T262	2
all_values[14]	auto[0]	auto[1]	auto[0]	22	1		T261	3		T263	2		T272	1
all_values[14]	auto[0]	auto[1]	auto[1]	52	1		T71	2		T72	1		T73	3
all_values[14]	auto[1]	auto[0]	auto[1]	60	1		T71	1		T74	2		T72	1
all_values[14]	auto[1]	auto[1]	auto[1]	46	1		T71	1		T73	3		T75	1
all_values[15]	auto[0]	auto[0]	auto[0]	39	1		T74	1		T72	1		T262	2
all_values[15]	auto[0]	auto[0]	auto[1]	40	1		T71	1		T73	1		T75	2
all_values[15]	auto[0]	auto[1]	auto[0]	23	1		T72	1		T262	1		T266	2
all_values[15]	auto[0]	auto[1]	auto[1]	60	1		T74	2		T72	1		T73	3
all_values[15]	auto[1]	auto[0]	auto[1]	63	1		T71	2		T74	1		T72	1
all_values[15]	auto[1]	auto[1]	auto[1]	56	1		T71	1		T73	2		T75	1
all_values[16]	auto[0]	auto[0]	auto[0]	26	1		T74	1		T75	1		T262	1
all_values[16]	auto[0]	auto[0]	auto[1]	63	1		T71	1		T72	2		T75	1
all_values[16]	auto[0]	auto[1]	auto[0]	27	1		T71	1		T262	1		T260	2
all_values[16]	auto[0]	auto[1]	auto[1]	55	1		T74	1		T72	1		T73	3
all_values[16]	auto[1]	auto[0]	auto[1]	53	1		T71	2		T74	1		T72	1
all_values[16]	auto[1]	auto[1]	auto[1]	57	1		T74	1		T73	2		T75	3
all_values[17]	auto[0]	auto[0]	auto[0]	19	1		T74	1		T72	1		T73	1
all_values[17]	auto[0]	auto[0]	auto[1]	61	1		T71	1		T74	1		T72	1
all_values[17]	auto[0]	auto[1]	auto[0]	16	1		T72	1		T266	2		T274	2
all_values[17]	auto[0]	auto[1]	auto[1]	62	1		T71	2		T73	2		T75	2
all_values[17]	auto[1]	auto[0]	auto[1]	70	1		T71	1		T74	2		T75	2
all_values[17]	auto[1]	auto[1]	auto[1]	53	1		T72	1		T73	4		T259	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal