Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.96 96.71 89.46 97.32 50.00 94.66 97.97 96.58


Total test records in report: 1478
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html
T1326 /workspace/coverage/default/11.usbdev_in_trans.1457038927 Apr 16 01:02:23 PM PDT 24 Apr 16 01:02:31 PM PDT 24 8418947864 ps
T1327 /workspace/coverage/default/44.usbdev_setup_trans_ignored.3212532732 Apr 16 01:05:21 PM PDT 24 Apr 16 01:05:29 PM PDT 24 8374001070 ps
T1328 /workspace/coverage/default/12.usbdev_pkt_sent.3034350798 Apr 16 01:02:29 PM PDT 24 Apr 16 01:02:40 PM PDT 24 8464338869 ps
T1329 /workspace/coverage/default/22.usbdev_out_trans_nak.340437098 Apr 16 01:03:25 PM PDT 24 Apr 16 01:03:34 PM PDT 24 8396826198 ps
T1330 /workspace/coverage/default/8.usbdev_pkt_buffer.1905424007 Apr 16 01:01:59 PM PDT 24 Apr 16 01:02:40 PM PDT 24 21492028056 ps
T1331 /workspace/coverage/default/22.usbdev_nak_trans.3982293075 Apr 16 01:03:25 PM PDT 24 Apr 16 01:03:34 PM PDT 24 8431757620 ps
T1332 /workspace/coverage/default/44.usbdev_out_trans_nak.21888971 Apr 16 01:05:21 PM PDT 24 Apr 16 01:05:31 PM PDT 24 8389605746 ps
T1333 /workspace/coverage/default/15.usbdev_setup_trans_ignored.2698870412 Apr 16 01:02:45 PM PDT 24 Apr 16 01:02:55 PM PDT 24 8368530081 ps
T1334 /workspace/coverage/default/3.usbdev_setup_stage.4059932104 Apr 16 01:01:26 PM PDT 24 Apr 16 01:01:34 PM PDT 24 8378409346 ps
T1335 /workspace/coverage/default/37.usbdev_setup_trans_ignored.2823001382 Apr 16 01:04:45 PM PDT 24 Apr 16 01:04:55 PM PDT 24 8374322092 ps
T1336 /workspace/coverage/default/47.usbdev_in_trans.1132892840 Apr 16 01:05:35 PM PDT 24 Apr 16 01:05:45 PM PDT 24 8450438982 ps
T1337 /workspace/coverage/default/1.usbdev_pkt_buffer.3570996787 Apr 16 01:01:15 PM PDT 24 Apr 16 01:02:06 PM PDT 24 25907477303 ps
T1338 /workspace/coverage/default/46.usbdev_stall_priority_over_nak.597427001 Apr 16 01:05:28 PM PDT 24 Apr 16 01:05:38 PM PDT 24 8411496717 ps
T1339 /workspace/coverage/default/39.usbdev_in_trans.2529780961 Apr 16 01:04:56 PM PDT 24 Apr 16 01:05:07 PM PDT 24 8463493272 ps
T1340 /workspace/coverage/default/4.usbdev_pkt_sent.4086244958 Apr 16 01:01:35 PM PDT 24 Apr 16 01:01:45 PM PDT 24 8424202281 ps
T1341 /workspace/coverage/default/4.usbdev_fifo_rst.483238029 Apr 16 01:01:29 PM PDT 24 Apr 16 01:01:31 PM PDT 24 102384918 ps
T1342 /workspace/coverage/default/20.usbdev_av_buffer.2058291822 Apr 16 01:03:13 PM PDT 24 Apr 16 01:03:23 PM PDT 24 8390739398 ps
T1343 /workspace/coverage/default/32.usbdev_fifo_rst.891844185 Apr 16 01:04:16 PM PDT 24 Apr 16 01:04:18 PM PDT 24 164572798 ps
T1344 /workspace/coverage/default/38.usbdev_phy_pins_sense.636762992 Apr 16 01:04:52 PM PDT 24 Apr 16 01:04:53 PM PDT 24 49848357 ps
T1345 /workspace/coverage/default/24.usbdev_random_length_out_trans.559739759 Apr 16 01:03:38 PM PDT 24 Apr 16 01:03:47 PM PDT 24 8424696038 ps
T1346 /workspace/coverage/default/11.usbdev_nak_trans.3121008673 Apr 16 01:02:22 PM PDT 24 Apr 16 01:02:30 PM PDT 24 8430316660 ps
T1347 /workspace/coverage/default/34.usbdev_in_stall.1121407838 Apr 16 01:04:31 PM PDT 24 Apr 16 01:04:42 PM PDT 24 8372866038 ps
T1348 /workspace/coverage/default/27.usbdev_pending_in_trans.347919911 Apr 16 01:04:02 PM PDT 24 Apr 16 01:04:11 PM PDT 24 8418669756 ps
T121 /workspace/coverage/default/34.usbdev_nak_trans.1700983648 Apr 16 01:04:26 PM PDT 24 Apr 16 01:04:35 PM PDT 24 8415000247 ps
T1349 /workspace/coverage/default/22.usbdev_setup_stage.1969270379 Apr 16 01:03:27 PM PDT 24 Apr 16 01:03:36 PM PDT 24 8376345311 ps
T1350 /workspace/coverage/default/48.usbdev_nak_trans.4288508727 Apr 16 01:05:33 PM PDT 24 Apr 16 01:05:43 PM PDT 24 8411085942 ps
T1351 /workspace/coverage/default/23.usbdev_smoke.3358347014 Apr 16 01:03:25 PM PDT 24 Apr 16 01:03:34 PM PDT 24 8458262486 ps
T1352 /workspace/coverage/default/43.usbdev_in_stall.3895846150 Apr 16 01:05:23 PM PDT 24 Apr 16 01:05:33 PM PDT 24 8376480371 ps
T1353 /workspace/coverage/default/13.usbdev_in_trans.2532941876 Apr 16 01:02:30 PM PDT 24 Apr 16 01:02:40 PM PDT 24 8421537629 ps
T1354 /workspace/coverage/default/38.max_length_in_transaction.656627407 Apr 16 01:04:54 PM PDT 24 Apr 16 01:05:05 PM PDT 24 8469252551 ps
T1355 /workspace/coverage/default/28.usbdev_in_trans.4182288347 Apr 16 01:04:00 PM PDT 24 Apr 16 01:04:09 PM PDT 24 8461119611 ps
T1356 /workspace/coverage/default/3.max_length_in_transaction.1655881606 Apr 16 01:01:29 PM PDT 24 Apr 16 01:01:37 PM PDT 24 8471047490 ps
T1357 /workspace/coverage/default/38.usbdev_in_trans.3348207781 Apr 16 01:04:46 PM PDT 24 Apr 16 01:04:56 PM PDT 24 8384360000 ps
T1358 /workspace/coverage/default/34.usbdev_in_iso.457617121 Apr 16 01:04:30 PM PDT 24 Apr 16 01:04:40 PM PDT 24 8415713698 ps
T1359 /workspace/coverage/default/42.usbdev_in_iso.249880974 Apr 16 01:05:12 PM PDT 24 Apr 16 01:05:21 PM PDT 24 8449410506 ps
T1360 /workspace/coverage/default/49.min_length_in_transaction.3326442155 Apr 16 01:05:35 PM PDT 24 Apr 16 01:05:43 PM PDT 24 8384593985 ps
T1361 /workspace/coverage/default/14.usbdev_in_iso.3490586691 Apr 16 01:02:41 PM PDT 24 Apr 16 01:02:50 PM PDT 24 8374756965 ps
T1362 /workspace/coverage/default/5.usbdev_pkt_received.3774792151 Apr 16 01:01:44 PM PDT 24 Apr 16 01:01:53 PM PDT 24 8399184398 ps
T1363 /workspace/coverage/default/30.usbdev_fifo_rst.4061232013 Apr 16 01:04:08 PM PDT 24 Apr 16 01:04:11 PM PDT 24 146235631 ps
T1364 /workspace/coverage/default/20.usbdev_setup_stage.2177945285 Apr 16 01:03:15 PM PDT 24 Apr 16 01:03:26 PM PDT 24 8431320321 ps
T1365 /workspace/coverage/default/7.usbdev_min_length_out_transaction.3733304202 Apr 16 01:01:53 PM PDT 24 Apr 16 01:02:02 PM PDT 24 8373306269 ps
T1366 /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.2319317533 Apr 16 01:02:45 PM PDT 24 Apr 16 01:02:54 PM PDT 24 8376084203 ps
T1367 /workspace/coverage/default/7.usbdev_max_length_out_transaction.3737073257 Apr 16 01:01:52 PM PDT 24 Apr 16 01:02:02 PM PDT 24 8422161292 ps
T1368 /workspace/coverage/default/20.usbdev_phy_pins_sense.3098308662 Apr 16 01:03:16 PM PDT 24 Apr 16 01:03:18 PM PDT 24 44199950 ps
T1369 /workspace/coverage/default/0.usbdev_phy_pins_sense.938799359 Apr 16 01:01:05 PM PDT 24 Apr 16 01:01:06 PM PDT 24 57217196 ps
T1370 /workspace/coverage/default/3.usbdev_phy_pins_sense.1577482108 Apr 16 01:01:24 PM PDT 24 Apr 16 01:01:25 PM PDT 24 32260648 ps
T1371 /workspace/coverage/default/12.usbdev_out_trans_nak.189633281 Apr 16 01:02:25 PM PDT 24 Apr 16 01:02:35 PM PDT 24 8440344451 ps
T1372 /workspace/coverage/default/27.usbdev_random_length_out_trans.4256440503 Apr 16 01:03:57 PM PDT 24 Apr 16 01:04:08 PM PDT 24 8438041518 ps
T1373 /workspace/coverage/default/19.usbdev_out_trans_nak.2334652475 Apr 16 01:03:10 PM PDT 24 Apr 16 01:03:19 PM PDT 24 8383378442 ps
T1374 /workspace/coverage/default/32.usbdev_min_length_out_transaction.2037757187 Apr 16 01:04:17 PM PDT 24 Apr 16 01:04:28 PM PDT 24 8379637600 ps
T1375 /workspace/coverage/default/29.usbdev_pkt_received.3881013522 Apr 16 01:04:00 PM PDT 24 Apr 16 01:04:11 PM PDT 24 8398486562 ps
T1376 /workspace/coverage/default/25.random_length_in_trans.572215702 Apr 16 01:03:42 PM PDT 24 Apr 16 01:03:51 PM PDT 24 8409485321 ps
T1377 /workspace/coverage/default/47.usbdev_setup_trans_ignored.246439609 Apr 16 01:05:35 PM PDT 24 Apr 16 01:05:45 PM PDT 24 8368857008 ps
T71 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.747670594 Apr 16 12:44:17 PM PDT 24 Apr 16 12:44:19 PM PDT 24 24066558 ps
T68 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.616467788 Apr 16 12:44:17 PM PDT 24 Apr 16 12:44:20 PM PDT 24 76174148 ps
T74 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.695737302 Apr 16 12:44:31 PM PDT 24 Apr 16 12:44:34 PM PDT 24 84244613 ps
T69 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.654281425 Apr 16 12:44:16 PM PDT 24 Apr 16 12:44:18 PM PDT 24 63197294 ps
T72 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3573293957 Apr 16 12:44:43 PM PDT 24 Apr 16 12:44:45 PM PDT 24 48436916 ps
T73 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.938918023 Apr 16 12:44:31 PM PDT 24 Apr 16 12:44:34 PM PDT 24 41647272 ps
T62 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2104645775 Apr 16 12:44:16 PM PDT 24 Apr 16 12:44:19 PM PDT 24 235522068 ps
T63 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3377774322 Apr 16 12:44:38 PM PDT 24 Apr 16 12:44:42 PM PDT 24 110136886 ps
T75 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1329683100 Apr 16 12:44:34 PM PDT 24 Apr 16 12:44:36 PM PDT 24 54040057 ps
T198 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3804526783 Apr 16 12:44:29 PM PDT 24 Apr 16 12:44:33 PM PDT 24 193197682 ps
T259 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1254685498 Apr 16 12:44:40 PM PDT 24 Apr 16 12:44:41 PM PDT 24 39609963 ps
T64 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.479810477 Apr 16 12:45:01 PM PDT 24 Apr 16 12:45:04 PM PDT 24 201787018 ps
T70 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2529935770 Apr 16 12:44:25 PM PDT 24 Apr 16 12:44:28 PM PDT 24 53644562 ps
T199 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.429002608 Apr 16 12:44:29 PM PDT 24 Apr 16 12:44:36 PM PDT 24 825796843 ps
T200 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.435083761 Apr 16 12:44:29 PM PDT 24 Apr 16 12:44:32 PM PDT 24 44474307 ps
T201 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.32436443 Apr 16 12:44:33 PM PDT 24 Apr 16 12:44:36 PM PDT 24 126016774 ps
T202 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.104390635 Apr 16 12:44:35 PM PDT 24 Apr 16 12:44:37 PM PDT 24 54310167 ps
T203 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1023608759 Apr 16 12:44:33 PM PDT 24 Apr 16 12:44:38 PM PDT 24 865800807 ps
T224 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3869351994 Apr 16 12:44:42 PM PDT 24 Apr 16 12:44:47 PM PDT 24 138544066 ps
T240 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1429969267 Apr 16 12:44:31 PM PDT 24 Apr 16 12:44:35 PM PDT 24 201702977 ps
T205 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3137780498 Apr 16 12:44:32 PM PDT 24 Apr 16 12:44:38 PM PDT 24 807583912 ps
T251 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4115717117 Apr 16 12:44:26 PM PDT 24 Apr 16 12:44:30 PM PDT 24 28512844 ps
T225 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3449255568 Apr 16 12:44:14 PM PDT 24 Apr 16 12:44:16 PM PDT 24 158353432 ps
T252 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.116679722 Apr 16 12:44:37 PM PDT 24 Apr 16 12:44:39 PM PDT 24 42086937 ps
T206 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3840518035 Apr 16 12:44:27 PM PDT 24 Apr 16 12:44:32 PM PDT 24 122941178 ps
T262 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2187650113 Apr 16 12:44:46 PM PDT 24 Apr 16 12:44:48 PM PDT 24 24693012 ps
T241 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.67999962 Apr 16 12:44:23 PM PDT 24 Apr 16 12:44:32 PM PDT 24 915571113 ps
T207 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1242799546 Apr 16 12:44:21 PM PDT 24 Apr 16 12:44:25 PM PDT 24 91998183 ps
T253 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.979008409 Apr 16 12:44:21 PM PDT 24 Apr 16 12:44:23 PM PDT 24 43729260 ps
T260 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2902666138 Apr 16 12:44:42 PM PDT 24 Apr 16 12:44:44 PM PDT 24 31210127 ps
T242 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.378538778 Apr 16 12:44:21 PM PDT 24 Apr 16 12:44:33 PM PDT 24 258358655 ps
T261 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1393192666 Apr 16 12:44:24 PM PDT 24 Apr 16 12:44:26 PM PDT 24 77508491 ps
T204 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.605900331 Apr 16 12:44:45 PM PDT 24 Apr 16 12:44:51 PM PDT 24 583915803 ps
T243 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3289747025 Apr 16 12:44:22 PM PDT 24 Apr 16 12:44:24 PM PDT 24 74982395 ps
T208 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2579189529 Apr 16 12:44:28 PM PDT 24 Apr 16 12:44:33 PM PDT 24 187443584 ps
T263 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.148108087 Apr 16 12:44:47 PM PDT 24 Apr 16 12:44:49 PM PDT 24 66493995 ps
T226 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3754859421 Apr 16 12:44:16 PM PDT 24 Apr 16 12:44:21 PM PDT 24 384953716 ps
T222 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3003266222 Apr 16 12:44:22 PM PDT 24 Apr 16 12:44:25 PM PDT 24 77525587 ps
T1378 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2780387260 Apr 16 12:44:17 PM PDT 24 Apr 16 12:44:19 PM PDT 24 77735606 ps
T1379 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1661194693 Apr 16 12:44:41 PM PDT 24 Apr 16 12:44:43 PM PDT 24 55207158 ps
T257 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2016020568 Apr 16 12:44:26 PM PDT 24 Apr 16 12:44:29 PM PDT 24 58765026 ps
T244 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1166826959 Apr 16 12:44:44 PM PDT 24 Apr 16 12:44:47 PM PDT 24 97601661 ps
T271 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.554362838 Apr 16 12:44:50 PM PDT 24 Apr 16 12:44:51 PM PDT 24 38924688 ps
T266 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.378719629 Apr 16 12:45:00 PM PDT 24 Apr 16 12:45:02 PM PDT 24 33602678 ps
T1380 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3316213657 Apr 16 12:44:44 PM PDT 24 Apr 16 12:44:46 PM PDT 24 51651323 ps
T264 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.442673887 Apr 16 12:44:36 PM PDT 24 Apr 16 12:44:38 PM PDT 24 38003145 ps
T220 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2282358355 Apr 16 12:44:17 PM PDT 24 Apr 16 12:44:20 PM PDT 24 60767781 ps
T255 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2474784568 Apr 16 12:44:24 PM PDT 24 Apr 16 12:44:26 PM PDT 24 81238016 ps
T245 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2746752901 Apr 16 12:44:33 PM PDT 24 Apr 16 12:44:36 PM PDT 24 41094056 ps
T274 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.938095098 Apr 16 12:44:42 PM PDT 24 Apr 16 12:44:44 PM PDT 24 35982103 ps
T276 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.305818586 Apr 16 12:44:14 PM PDT 24 Apr 16 12:44:19 PM PDT 24 592323566 ps
T219 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3125584251 Apr 16 12:44:23 PM PDT 24 Apr 16 12:44:28 PM PDT 24 223285320 ps
T1381 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.113698775 Apr 16 12:44:27 PM PDT 24 Apr 16 12:44:31 PM PDT 24 111370483 ps
T1382 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2253360050 Apr 16 12:44:28 PM PDT 24 Apr 16 12:44:33 PM PDT 24 127692559 ps
T1383 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.4230094895 Apr 16 12:44:22 PM PDT 24 Apr 16 12:44:25 PM PDT 24 76788808 ps
T265 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3564394869 Apr 16 12:44:33 PM PDT 24 Apr 16 12:44:36 PM PDT 24 28280780 ps
T270 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2616907565 Apr 16 12:44:45 PM PDT 24 Apr 16 12:44:46 PM PDT 24 43098347 ps
T1384 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2661480630 Apr 16 12:44:16 PM PDT 24 Apr 16 12:44:25 PM PDT 24 303036964 ps
T1385 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1900251698 Apr 16 12:44:30 PM PDT 24 Apr 16 12:44:33 PM PDT 24 26996878 ps
T217 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3339786666 Apr 16 12:44:29 PM PDT 24 Apr 16 12:44:33 PM PDT 24 55114608 ps
T272 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2026352724 Apr 16 12:44:30 PM PDT 24 Apr 16 12:44:33 PM PDT 24 54196195 ps
T279 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.89744578 Apr 16 12:44:26 PM PDT 24 Apr 16 12:44:31 PM PDT 24 452655096 ps
T1386 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.912064778 Apr 16 12:44:17 PM PDT 24 Apr 16 12:44:20 PM PDT 24 59036904 ps
T218 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1738203330 Apr 16 12:44:15 PM PDT 24 Apr 16 12:44:17 PM PDT 24 60163325 ps
T221 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2261715324 Apr 16 12:44:21 PM PDT 24 Apr 16 12:44:26 PM PDT 24 95741254 ps
T273 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.52645405 Apr 16 12:44:31 PM PDT 24 Apr 16 12:44:34 PM PDT 24 31504158 ps
T275 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1086686176 Apr 16 12:44:32 PM PDT 24 Apr 16 12:44:34 PM PDT 24 32053517 ps
T1387 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.820834491 Apr 16 12:44:29 PM PDT 24 Apr 16 12:44:33 PM PDT 24 55553553 ps
T1388 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1733816471 Apr 16 12:44:34 PM PDT 24 Apr 16 12:44:37 PM PDT 24 31346676 ps
T256 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.325368175 Apr 16 12:44:28 PM PDT 24 Apr 16 12:44:35 PM PDT 24 811133023 ps
T1389 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3295296598 Apr 16 12:44:37 PM PDT 24 Apr 16 12:44:40 PM PDT 24 160791430 ps
T1390 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1034095074 Apr 16 12:44:31 PM PDT 24 Apr 16 12:44:34 PM PDT 24 59314136 ps
T1391 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3213271969 Apr 16 12:44:18 PM PDT 24 Apr 16 12:44:27 PM PDT 24 90299408 ps
T1392 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.980717087 Apr 16 12:44:26 PM PDT 24 Apr 16 12:44:29 PM PDT 24 85544378 ps
T246 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2014208247 Apr 16 12:44:28 PM PDT 24 Apr 16 12:44:34 PM PDT 24 285773953 ps
T1393 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3628468459 Apr 16 12:44:46 PM PDT 24 Apr 16 12:44:50 PM PDT 24 201153114 ps
T1394 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.437562257 Apr 16 12:44:26 PM PDT 24 Apr 16 12:44:32 PM PDT 24 155932302 ps
T1395 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.572299047 Apr 16 12:44:28 PM PDT 24 Apr 16 12:44:33 PM PDT 24 82124009 ps
T1396 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.997999083 Apr 16 12:44:37 PM PDT 24 Apr 16 12:44:40 PM PDT 24 90106010 ps
T1397 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1207611644 Apr 16 12:44:33 PM PDT 24 Apr 16 12:44:36 PM PDT 24 154725841 ps
T1398 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3814615706 Apr 16 12:44:24 PM PDT 24 Apr 16 12:44:28 PM PDT 24 102289291 ps
T1399 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.974158577 Apr 16 12:44:26 PM PDT 24 Apr 16 12:44:30 PM PDT 24 110174966 ps
T267 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.940414149 Apr 16 12:44:48 PM PDT 24 Apr 16 12:44:50 PM PDT 24 44003400 ps
T258 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2467668267 Apr 16 12:44:38 PM PDT 24 Apr 16 12:44:42 PM PDT 24 495563672 ps
T1400 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1609555784 Apr 16 12:44:41 PM PDT 24 Apr 16 12:44:42 PM PDT 24 28566591 ps
T268 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3330536265 Apr 16 12:44:17 PM PDT 24 Apr 16 12:44:18 PM PDT 24 28909481 ps
T1401 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1543525461 Apr 16 12:44:37 PM PDT 24 Apr 16 12:44:39 PM PDT 24 284835505 ps
T1402 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.4057922981 Apr 16 12:44:41 PM PDT 24 Apr 16 12:44:43 PM PDT 24 28149583 ps
T269 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2945094219 Apr 16 12:44:27 PM PDT 24 Apr 16 12:44:31 PM PDT 24 48086413 ps
T1403 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2319597704 Apr 16 12:44:17 PM PDT 24 Apr 16 12:44:21 PM PDT 24 316501048 ps
T1404 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.480375995 Apr 16 12:44:29 PM PDT 24 Apr 16 12:44:36 PM PDT 24 720602552 ps
T247 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1816782935 Apr 16 12:44:36 PM PDT 24 Apr 16 12:44:41 PM PDT 24 595862117 ps
T248 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.445509822 Apr 16 12:44:23 PM PDT 24 Apr 16 12:44:30 PM PDT 24 725792811 ps
T1405 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2070983652 Apr 16 12:44:46 PM PDT 24 Apr 16 12:44:48 PM PDT 24 39267214 ps
T1406 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2731954258 Apr 16 12:44:28 PM PDT 24 Apr 16 12:44:31 PM PDT 24 35633512 ps
T1407 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3675109321 Apr 16 12:44:16 PM PDT 24 Apr 16 12:44:19 PM PDT 24 138350352 ps
T1408 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3113393145 Apr 16 12:44:28 PM PDT 24 Apr 16 12:44:32 PM PDT 24 82709615 ps
T1409 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3133764091 Apr 16 12:44:32 PM PDT 24 Apr 16 12:44:36 PM PDT 24 136395501 ps
T1410 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3258176416 Apr 16 12:44:36 PM PDT 24 Apr 16 12:44:38 PM PDT 24 28690394 ps
T1411 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.143828649 Apr 16 12:44:43 PM PDT 24 Apr 16 12:44:45 PM PDT 24 60313258 ps
T1412 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.794332862 Apr 16 12:44:16 PM PDT 24 Apr 16 12:44:20 PM PDT 24 201277482 ps
T1413 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3166881259 Apr 16 12:44:37 PM PDT 24 Apr 16 12:44:39 PM PDT 24 47009300 ps
T249 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2972386948 Apr 16 12:44:21 PM PDT 24 Apr 16 12:44:23 PM PDT 24 90790614 ps
T1414 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1706155242 Apr 16 12:44:27 PM PDT 24 Apr 16 12:44:31 PM PDT 24 90443165 ps
T1415 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1394003731 Apr 16 12:44:41 PM PDT 24 Apr 16 12:44:45 PM PDT 24 341140341 ps
T1416 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1298084345 Apr 16 12:44:29 PM PDT 24 Apr 16 12:44:32 PM PDT 24 90061057 ps
T1417 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.761968709 Apr 16 12:44:15 PM PDT 24 Apr 16 12:44:20 PM PDT 24 158237545 ps
T1418 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.528483466 Apr 16 12:44:23 PM PDT 24 Apr 16 12:44:26 PM PDT 24 88307272 ps
T1419 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3495421115 Apr 16 12:44:25 PM PDT 24 Apr 16 12:44:28 PM PDT 24 75497545 ps
T1420 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2739390657 Apr 16 12:44:13 PM PDT 24 Apr 16 12:44:20 PM PDT 24 106790122 ps
T1421 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2100974903 Apr 16 12:44:53 PM PDT 24 Apr 16 12:45:01 PM PDT 24 37252787 ps
T1422 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1141099832 Apr 16 12:44:49 PM PDT 24 Apr 16 12:44:51 PM PDT 24 39554877 ps
T1423 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1312342124 Apr 16 12:44:45 PM PDT 24 Apr 16 12:44:47 PM PDT 24 49681941 ps
T1424 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.242961612 Apr 16 12:44:16 PM PDT 24 Apr 16 12:44:19 PM PDT 24 320209238 ps
T1425 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3624114421 Apr 16 12:44:39 PM PDT 24 Apr 16 12:44:43 PM PDT 24 94979518 ps
T1426 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1500002369 Apr 16 12:44:18 PM PDT 24 Apr 16 12:44:20 PM PDT 24 39333303 ps
T1427 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2964552779 Apr 16 12:44:39 PM PDT 24 Apr 16 12:44:41 PM PDT 24 30722650 ps
T223 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1739054539 Apr 16 12:44:28 PM PDT 24 Apr 16 12:44:31 PM PDT 24 137692099 ps
T1428 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1647720262 Apr 16 12:44:22 PM PDT 24 Apr 16 12:44:25 PM PDT 24 82603822 ps
T20 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.4289534174 Apr 16 12:44:16 PM PDT 24 Apr 16 12:44:18 PM PDT 24 57462708 ps
T1429 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1295702213 Apr 16 12:44:41 PM PDT 24 Apr 16 12:44:42 PM PDT 24 41316047 ps
T250 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2302650871 Apr 16 12:44:32 PM PDT 24 Apr 16 12:44:37 PM PDT 24 337717847 ps
T277 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2937869228 Apr 16 12:44:24 PM PDT 24 Apr 16 12:44:30 PM PDT 24 1234930747 ps
T1430 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.148076106 Apr 16 12:44:15 PM PDT 24 Apr 16 12:44:18 PM PDT 24 179791878 ps
T1431 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3859446549 Apr 16 12:44:33 PM PDT 24 Apr 16 12:44:36 PM PDT 24 45335028 ps
T1432 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.303286850 Apr 16 12:44:39 PM PDT 24 Apr 16 12:44:41 PM PDT 24 115922871 ps
T1433 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2394504326 Apr 16 12:44:47 PM PDT 24 Apr 16 12:44:49 PM PDT 24 40219407 ps
T1434 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.755356222 Apr 16 12:44:18 PM PDT 24 Apr 16 12:44:20 PM PDT 24 197665914 ps
T1435 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2045950446 Apr 16 12:44:23 PM PDT 24 Apr 16 12:44:25 PM PDT 24 28688459 ps
T1436 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3342941112 Apr 16 12:44:16 PM PDT 24 Apr 16 12:44:18 PM PDT 24 34588659 ps
T1437 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1088055658 Apr 16 12:44:35 PM PDT 24 Apr 16 12:44:38 PM PDT 24 169578798 ps
T1438 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3470725961 Apr 16 12:44:34 PM PDT 24 Apr 16 12:44:37 PM PDT 24 142438283 ps
T1439 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1278556430 Apr 16 12:44:29 PM PDT 24 Apr 16 12:44:33 PM PDT 24 240642582 ps
T1440 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.342111361 Apr 16 12:44:30 PM PDT 24 Apr 16 12:44:38 PM PDT 24 67276329 ps
T1441 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2806529786 Apr 16 12:44:38 PM PDT 24 Apr 16 12:44:41 PM PDT 24 225683451 ps
T1442 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1545569380 Apr 16 12:44:28 PM PDT 24 Apr 16 12:44:31 PM PDT 24 31785873 ps
T1443 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2261177976 Apr 16 12:44:25 PM PDT 24 Apr 16 12:44:29 PM PDT 24 187418050 ps
T1444 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.4090536886 Apr 16 12:44:26 PM PDT 24 Apr 16 12:44:37 PM PDT 24 499869049 ps
T1445 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.4041313940 Apr 16 12:44:28 PM PDT 24 Apr 16 12:44:34 PM PDT 24 939395620 ps
T1446 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1196664629 Apr 16 12:44:35 PM PDT 24 Apr 16 12:44:37 PM PDT 24 31452663 ps
T1447 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3461299561 Apr 16 12:44:35 PM PDT 24 Apr 16 12:44:43 PM PDT 24 112154418 ps
T1448 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3414158763 Apr 16 12:44:29 PM PDT 24 Apr 16 12:44:32 PM PDT 24 44112271 ps
T1449 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3521448555 Apr 16 12:44:37 PM PDT 24 Apr 16 12:44:39 PM PDT 24 57132726 ps
T1450 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1248132216 Apr 16 12:44:33 PM PDT 24 Apr 16 12:44:35 PM PDT 24 55152577 ps
T1451 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3927046089 Apr 16 12:44:21 PM PDT 24 Apr 16 12:44:26 PM PDT 24 394503539 ps
T1452 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2511810590 Apr 16 12:44:32 PM PDT 24 Apr 16 12:44:35 PM PDT 24 39018432 ps
T1453 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1994580289 Apr 16 12:44:18 PM PDT 24 Apr 16 12:44:20 PM PDT 24 44097930 ps
T1454 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3170350 Apr 16 12:44:35 PM PDT 24 Apr 16 12:44:40 PM PDT 24 536919418 ps
T1455 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2655643525 Apr 16 12:45:00 PM PDT 24 Apr 16 12:45:04 PM PDT 24 193197998 ps
T1456 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3043142480 Apr 16 12:44:18 PM PDT 24 Apr 16 12:44:22 PM PDT 24 90554832 ps
T1457 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.4093405057 Apr 16 12:44:18 PM PDT 24 Apr 16 12:44:21 PM PDT 24 92849655 ps
T1458 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.713339063 Apr 16 12:44:26 PM PDT 24 Apr 16 12:44:29 PM PDT 24 66461380 ps
T1459 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3337834192 Apr 16 12:44:28 PM PDT 24 Apr 16 12:44:34 PM PDT 24 353968147 ps
T1460 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1268279316 Apr 16 12:44:47 PM PDT 24 Apr 16 12:44:48 PM PDT 24 35072388 ps
T1461 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.4276086240 Apr 16 12:44:27 PM PDT 24 Apr 16 12:44:30 PM PDT 24 32199735 ps
T1462 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1380755971 Apr 16 12:44:39 PM PDT 24 Apr 16 12:44:41 PM PDT 24 38454615 ps
T1463 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2187186326 Apr 16 12:44:25 PM PDT 24 Apr 16 12:44:34 PM PDT 24 129058929 ps
T1464 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.678890997 Apr 16 12:44:26 PM PDT 24 Apr 16 12:44:30 PM PDT 24 127894079 ps
T1465 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3895231051 Apr 16 12:44:27 PM PDT 24 Apr 16 12:44:33 PM PDT 24 451298726 ps
T1466 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.4135652683 Apr 16 12:44:16 PM PDT 24 Apr 16 12:44:17 PM PDT 24 61940256 ps
T1467 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1520228630 Apr 16 12:44:17 PM PDT 24 Apr 16 12:44:26 PM PDT 24 1226653583 ps
T1468 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3809099278 Apr 16 12:44:25 PM PDT 24 Apr 16 12:44:29 PM PDT 24 87861990 ps
T1469 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3795039767 Apr 16 12:44:47 PM PDT 24 Apr 16 12:44:49 PM PDT 24 45086069 ps
T1470 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2359441182 Apr 16 12:44:26 PM PDT 24 Apr 16 12:44:32 PM PDT 24 1054331614 ps
T1471 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3433259219 Apr 16 12:44:38 PM PDT 24 Apr 16 12:44:41 PM PDT 24 222686311 ps
T1472 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2695711292 Apr 16 12:45:02 PM PDT 24 Apr 16 12:45:04 PM PDT 24 37491536 ps
T21 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1108971722 Apr 16 12:44:43 PM PDT 24 Apr 16 12:44:45 PM PDT 24 96546213 ps
T1473 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.4048628452 Apr 16 12:44:55 PM PDT 24 Apr 16 12:44:56 PM PDT 24 34528775 ps
T1474 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2772461781 Apr 16 12:44:45 PM PDT 24 Apr 16 12:44:47 PM PDT 24 48647703 ps
T1475 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3069568305 Apr 16 12:44:44 PM PDT 24 Apr 16 12:44:46 PM PDT 24 50735909 ps
T280 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1422126667 Apr 16 12:44:22 PM PDT 24 Apr 16 12:44:27 PM PDT 24 401589231 ps
T1476 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2786441502 Apr 16 12:44:37 PM PDT 24 Apr 16 12:44:40 PM PDT 24 59840727 ps
T1477 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1331729820 Apr 16 12:44:34 PM PDT 24 Apr 16 12:44:37 PM PDT 24 78471395 ps
T278 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.721492930 Apr 16 12:44:20 PM PDT 24 Apr 16 12:44:25 PM PDT 24 564338875 ps
T1478 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3314444510 Apr 16 12:44:25 PM PDT 24 Apr 16 12:44:29 PM PDT 24 210148586 ps

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.2009183990
Short name T1
Test name
Test status
Simulation time 17957173132 ps
CPU time 37.61 seconds
Started Apr 16 01:04:15 PM PDT 24
Finished Apr 16 01:04:53 PM PDT 24
Peak memory 204276 kb
Host smart-1aa3dc9a-54f0-4fe5-9973-9cf90655d12b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20091
83990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.2009183990
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2187650113
Short name T262
Test name
Test status
Simulation time 24693012 ps
CPU time 0.7 seconds
Started Apr 16 12:44:46 PM PDT 24
Finished Apr 16 12:44:48 PM PDT 24
Peak memory 202896 kb
Host smart-47d4a277-c521-484f-a24a-f58ab2f4d1e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2187650113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2187650113
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.3034319540
Short name T58
Test name
Test status
Simulation time 132539376 ps
CPU time 1.38 seconds
Started Apr 16 01:04:49 PM PDT 24
Finished Apr 16 01:04:51 PM PDT 24
Peak memory 204088 kb
Host smart-2fc902df-6956-49de-b1d9-6b9ee1cf013d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30343
19540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.3034319540
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.429002608
Short name T199
Test name
Test status
Simulation time 825796843 ps
CPU time 4.55 seconds
Started Apr 16 12:44:29 PM PDT 24
Finished Apr 16 12:44:36 PM PDT 24
Peak memory 203704 kb
Host smart-18d9d53d-5ff2-4039-a531-4f67e7f0e9ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=429002608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.429002608
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/37.usbdev_smoke.131128306
Short name T51
Test name
Test status
Simulation time 8470742397 ps
CPU time 8.74 seconds
Started Apr 16 01:04:45 PM PDT 24
Finished Apr 16 01:04:55 PM PDT 24
Peak memory 203976 kb
Host smart-3d2279a2-c19f-4cbd-8f16-71b6fee7c1e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13112
8306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.131128306
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1337810919
Short name T12
Test name
Test status
Simulation time 28045355607 ps
CPU time 55.45 seconds
Started Apr 16 01:02:35 PM PDT 24
Finished Apr 16 01:03:31 PM PDT 24
Peak memory 204316 kb
Host smart-a325eabe-60c4-4e7d-a447-e02be08aae47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13378
10919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1337810919
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1329683100
Short name T75
Test name
Test status
Simulation time 54040057 ps
CPU time 0.73 seconds
Started Apr 16 12:44:34 PM PDT 24
Finished Apr 16 12:44:36 PM PDT 24
Peak memory 202900 kb
Host smart-23c1a1f8-aad7-4a83-9b66-f79431385853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1329683100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1329683100
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.3387086159
Short name T33
Test name
Test status
Simulation time 105835858 ps
CPU time 0.69 seconds
Started Apr 16 01:04:46 PM PDT 24
Finished Apr 16 01:04:47 PM PDT 24
Peak memory 203816 kb
Host smart-c0f69498-680f-4f4c-b7fa-22b27c680a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33870
86159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.3387086159
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.3100190917
Short name T146
Test name
Test status
Simulation time 8452940498 ps
CPU time 8.5 seconds
Started Apr 16 01:02:30 PM PDT 24
Finished Apr 16 01:02:39 PM PDT 24
Peak memory 204256 kb
Host smart-7010e6f8-26b8-409c-93bb-d533a8daee43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31001
90917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.3100190917
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.1956406645
Short name T5
Test name
Test status
Simulation time 8379987024 ps
CPU time 8.13 seconds
Started Apr 16 01:01:06 PM PDT 24
Finished Apr 16 01:01:15 PM PDT 24
Peak memory 203996 kb
Host smart-51f26cdc-9b5c-4ed9-a98a-1eb93507e694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19564
06645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.1956406645
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.3476546337
Short name T411
Test name
Test status
Simulation time 8367069701 ps
CPU time 9.6 seconds
Started Apr 16 01:01:15 PM PDT 24
Finished Apr 16 01:01:25 PM PDT 24
Peak memory 203960 kb
Host smart-e7e33c7e-02ca-4c30-a3c5-5001c9a63758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34765
46337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.3476546337
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.2136646733
Short name T97
Test name
Test status
Simulation time 8437225091 ps
CPU time 7.83 seconds
Started Apr 16 01:01:07 PM PDT 24
Finished Apr 16 01:01:15 PM PDT 24
Peak memory 204004 kb
Host smart-3a908650-1141-45c0-8332-cf7cad181ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21366
46733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.2136646733
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3449255568
Short name T225
Test name
Test status
Simulation time 158353432 ps
CPU time 1.88 seconds
Started Apr 16 12:44:14 PM PDT 24
Finished Apr 16 12:44:16 PM PDT 24
Peak memory 211896 kb
Host smart-5633276a-8734-446f-9c13-b6d67f48d9e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449255568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.3449255568
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.4289534174
Short name T20
Test name
Test status
Simulation time 57462708 ps
CPU time 0.92 seconds
Started Apr 16 12:44:16 PM PDT 24
Finished Apr 16 12:44:18 PM PDT 24
Peak memory 203256 kb
Host smart-69fd70dc-5558-439f-8ff8-c7701070f2d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4289534174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.4289534174
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.1546099910
Short name T65
Test name
Test status
Simulation time 267651506 ps
CPU time 1.17 seconds
Started Apr 16 01:01:17 PM PDT 24
Finished Apr 16 01:01:19 PM PDT 24
Peak memory 220084 kb
Host smart-a454b86a-05a4-4f7e-88d2-fe949c2795a4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1546099910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1546099910
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2902666138
Short name T260
Test name
Test status
Simulation time 31210127 ps
CPU time 0.62 seconds
Started Apr 16 12:44:42 PM PDT 24
Finished Apr 16 12:44:44 PM PDT 24
Peak memory 202832 kb
Host smart-f1a6305f-73dc-4d0b-9e16-647065a8d865
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2902666138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2902666138
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1785131358
Short name T57
Test name
Test status
Simulation time 8424399939 ps
CPU time 7.52 seconds
Started Apr 16 01:01:00 PM PDT 24
Finished Apr 16 01:01:08 PM PDT 24
Peak memory 204048 kb
Host smart-84a9491f-337f-475b-a038-558d19882212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17851
31358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1785131358
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1429969267
Short name T240
Test name
Test status
Simulation time 201702977 ps
CPU time 2.33 seconds
Started Apr 16 12:44:31 PM PDT 24
Finished Apr 16 12:44:35 PM PDT 24
Peak memory 211864 kb
Host smart-66d864a7-425d-42d9-b858-ce4003fd8ecc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1429969267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1429969267
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3125584251
Short name T219
Test name
Test status
Simulation time 223285320 ps
CPU time 2.98 seconds
Started Apr 16 12:44:23 PM PDT 24
Finished Apr 16 12:44:28 PM PDT 24
Peak memory 203652 kb
Host smart-8ef07a6a-2d17-4d30-82ac-1ad562299647
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3125584251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3125584251
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2945094219
Short name T269
Test name
Test status
Simulation time 48086413 ps
CPU time 0.68 seconds
Started Apr 16 12:44:27 PM PDT 24
Finished Apr 16 12:44:31 PM PDT 24
Peak memory 202836 kb
Host smart-24a62a2b-51bd-4200-85da-13ac39b6a02e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2945094219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2945094219
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2937869228
Short name T277
Test name
Test status
Simulation time 1234930747 ps
CPU time 5.27 seconds
Started Apr 16 12:44:24 PM PDT 24
Finished Apr 16 12:44:30 PM PDT 24
Peak memory 203680 kb
Host smart-7552ee94-b73d-416c-b0a7-e5a1b5b827ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2937869228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.2937869228
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.4057922981
Short name T1402
Test name
Test status
Simulation time 28149583 ps
CPU time 0.67 seconds
Started Apr 16 12:44:41 PM PDT 24
Finished Apr 16 12:44:43 PM PDT 24
Peak memory 202812 kb
Host smart-e25171b0-b013-4ce5-ba08-6a899d348250
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4057922981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.4057922981
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.2832303482
Short name T290
Test name
Test status
Simulation time 8395460003 ps
CPU time 7.97 seconds
Started Apr 16 01:01:02 PM PDT 24
Finished Apr 16 01:01:11 PM PDT 24
Peak memory 204032 kb
Host smart-9956fc3e-2d31-449e-9d5b-b023e695cbf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28323
03482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.2832303482
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.4292918110
Short name T11
Test name
Test status
Simulation time 5104023179 ps
CPU time 31.44 seconds
Started Apr 16 01:00:55 PM PDT 24
Finished Apr 16 01:01:28 PM PDT 24
Peak memory 204224 kb
Host smart-9f5f7998-fd98-4ed0-a0a3-ced1d3bdb86a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42929
18110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.4292918110
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.4099216760
Short name T92
Test name
Test status
Simulation time 26302951724 ps
CPU time 48.15 seconds
Started Apr 16 01:02:27 PM PDT 24
Finished Apr 16 01:03:16 PM PDT 24
Peak memory 204280 kb
Host smart-141c3e60-de85-4593-b6c3-a9d792a40948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40992
16760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.4099216760
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1422126667
Short name T280
Test name
Test status
Simulation time 401589231 ps
CPU time 4.22 seconds
Started Apr 16 12:44:22 PM PDT 24
Finished Apr 16 12:44:27 PM PDT 24
Peak memory 203652 kb
Host smart-36ef5fc9-b220-40ed-a4f1-6ddb50e39783
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1422126667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1422126667
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2045950446
Short name T1435
Test name
Test status
Simulation time 28688459 ps
CPU time 0.65 seconds
Started Apr 16 12:44:23 PM PDT 24
Finished Apr 16 12:44:25 PM PDT 24
Peak memory 202860 kb
Host smart-d7bdbca6-62ae-44fd-b1c2-83dc96d73310
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2045950446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2045950446
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3624114421
Short name T1425
Test name
Test status
Simulation time 94979518 ps
CPU time 2.93 seconds
Started Apr 16 12:44:39 PM PDT 24
Finished Apr 16 12:44:43 PM PDT 24
Peak memory 203676 kb
Host smart-a3adc8a5-9a56-434a-8d0e-35dfcaed314e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3624114421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3624114421
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.67999962
Short name T241
Test name
Test status
Simulation time 915571113 ps
CPU time 7.44 seconds
Started Apr 16 12:44:23 PM PDT 24
Finished Apr 16 12:44:32 PM PDT 24
Peak memory 203460 kb
Host smart-b87c7653-67f4-4240-9e02-10d9ea81c21f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=67999962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.67999962
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.160293310
Short name T42
Test name
Test status
Simulation time 36290806 ps
CPU time 0.63 seconds
Started Apr 16 01:04:56 PM PDT 24
Finished Apr 16 01:04:58 PM PDT 24
Peak memory 203904 kb
Host smart-000e5c75-5322-496f-bd71-aea6423ffc9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16029
3310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.160293310
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.2456584274
Short name T190
Test name
Test status
Simulation time 8391618265 ps
CPU time 8.63 seconds
Started Apr 16 01:01:06 PM PDT 24
Finished Apr 16 01:01:16 PM PDT 24
Peak memory 204004 kb
Host smart-4cc3ba15-7dd6-4db5-a190-286f0a621751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24565
84274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.2456584274
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_smoke.275781246
Short name T174
Test name
Test status
Simulation time 8427338786 ps
CPU time 9.04 seconds
Started Apr 16 01:01:00 PM PDT 24
Finished Apr 16 01:01:10 PM PDT 24
Peak memory 204016 kb
Host smart-06464d48-db0e-495a-8314-547cda895b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27578
1246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.275781246
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1961567873
Short name T90
Test name
Test status
Simulation time 8376596264 ps
CPU time 7.86 seconds
Started Apr 16 01:02:28 PM PDT 24
Finished Apr 16 01:02:37 PM PDT 24
Peak memory 204016 kb
Host smart-7b9fd089-6adf-4667-9716-21e86e8527af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19615
67873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1961567873
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.861775220
Short name T1112
Test name
Test status
Simulation time 8397590033 ps
CPU time 10.36 seconds
Started Apr 16 01:02:29 PM PDT 24
Finished Apr 16 01:02:41 PM PDT 24
Peak memory 204048 kb
Host smart-453d9a9e-3f91-48bf-b374-a381e27812dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86177
5220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.861775220
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.423978587
Short name T553
Test name
Test status
Simulation time 8394413874 ps
CPU time 8.2 seconds
Started Apr 16 01:02:36 PM PDT 24
Finished Apr 16 01:02:45 PM PDT 24
Peak memory 203988 kb
Host smart-12fd27c8-b5cc-49b5-a1c7-028a8ffe6c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42397
8587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.423978587
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.82692458
Short name T134
Test name
Test status
Simulation time 8460504145 ps
CPU time 8.49 seconds
Started Apr 16 01:02:34 PM PDT 24
Finished Apr 16 01:02:43 PM PDT 24
Peak memory 203976 kb
Host smart-7f42ed39-648e-4cea-a810-52e2d8133b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82692
458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.82692458
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.2083535308
Short name T927
Test name
Test status
Simulation time 8379170540 ps
CPU time 8.93 seconds
Started Apr 16 01:02:40 PM PDT 24
Finished Apr 16 01:02:50 PM PDT 24
Peak memory 204012 kb
Host smart-32fa2b6e-3649-4f8a-891c-d31c2f0ec5c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20835
35308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.2083535308
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.2865340287
Short name T188
Test name
Test status
Simulation time 8409161301 ps
CPU time 10.22 seconds
Started Apr 16 01:02:48 PM PDT 24
Finished Apr 16 01:02:59 PM PDT 24
Peak memory 203980 kb
Host smart-de48afa9-7cd8-45e8-a8ba-ac568cf07bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28653
40287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.2865340287
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1288078434
Short name T940
Test name
Test status
Simulation time 8413299483 ps
CPU time 8.29 seconds
Started Apr 16 01:03:25 PM PDT 24
Finished Apr 16 01:03:34 PM PDT 24
Peak memory 203972 kb
Host smart-f9a77c7e-76fd-4789-ae35-f39b8620f409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12880
78434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1288078434
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_smoke.371628779
Short name T658
Test name
Test status
Simulation time 8451123312 ps
CPU time 8.32 seconds
Started Apr 16 01:03:23 PM PDT 24
Finished Apr 16 01:03:32 PM PDT 24
Peak memory 204000 kb
Host smart-77427521-f717-4fe4-a0ac-f93b9ee6f1d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37162
8779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.371628779
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.1200930216
Short name T163
Test name
Test status
Simulation time 8380706727 ps
CPU time 8.31 seconds
Started Apr 16 01:04:56 PM PDT 24
Finished Apr 16 01:05:05 PM PDT 24
Peak memory 204004 kb
Host smart-fc7fff60-987a-41c6-bec8-e63d6895fc23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12009
30216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.1200930216
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.3527835274
Short name T312
Test name
Test status
Simulation time 8409066465 ps
CPU time 10.19 seconds
Started Apr 16 01:02:34 PM PDT 24
Finished Apr 16 01:02:46 PM PDT 24
Peak memory 203936 kb
Host smart-204ca0fe-08be-46f7-b38a-dc51cfe711df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35278
35274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.3527835274
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_smoke.3516790824
Short name T845
Test name
Test status
Simulation time 8480620440 ps
CPU time 8.6 seconds
Started Apr 16 01:03:11 PM PDT 24
Finished Apr 16 01:03:20 PM PDT 24
Peak memory 204020 kb
Host smart-c51d240d-1deb-4103-8d32-fb65d3a49dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35167
90824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.3516790824
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.794332862
Short name T1412
Test name
Test status
Simulation time 201277482 ps
CPU time 2.24 seconds
Started Apr 16 12:44:16 PM PDT 24
Finished Apr 16 12:44:20 PM PDT 24
Peak memory 203756 kb
Host smart-661a3adc-29a0-4f87-ae32-e84984d21407
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=794332862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.794332862
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.2943003399
Short name T370
Test name
Test status
Simulation time 8371575705 ps
CPU time 7.66 seconds
Started Apr 16 01:01:06 PM PDT 24
Finished Apr 16 01:01:15 PM PDT 24
Peak memory 204008 kb
Host smart-e7c494d3-8bcf-4088-8d32-36993b2054b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29430
03399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.2943003399
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.3811401634
Short name T123
Test name
Test status
Simulation time 8471120239 ps
CPU time 8.07 seconds
Started Apr 16 01:01:07 PM PDT 24
Finished Apr 16 01:01:16 PM PDT 24
Peak memory 203984 kb
Host smart-f84be27c-f390-4201-bc15-c37f29842a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38114
01634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.3811401634
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.3018701718
Short name T725
Test name
Test status
Simulation time 8385922371 ps
CPU time 8.91 seconds
Started Apr 16 01:01:14 PM PDT 24
Finished Apr 16 01:01:24 PM PDT 24
Peak memory 204028 kb
Host smart-1476a34a-9e01-4ebb-b119-8b56ab98dca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30187
01718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.3018701718
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.731235178
Short name T466
Test name
Test status
Simulation time 8420902291 ps
CPU time 9.71 seconds
Started Apr 16 01:02:22 PM PDT 24
Finished Apr 16 01:02:33 PM PDT 24
Peak memory 204052 kb
Host smart-20794730-42d2-43ef-936f-e7cf17077f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73123
5178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.731235178
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.570237946
Short name T113
Test name
Test status
Simulation time 8437906683 ps
CPU time 7.89 seconds
Started Apr 16 01:02:11 PM PDT 24
Finished Apr 16 01:02:20 PM PDT 24
Peak memory 204040 kb
Host smart-467ddf53-b169-493b-8136-ed04ad1bf090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57023
7946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.570237946
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.1727385103
Short name T467
Test name
Test status
Simulation time 8366899609 ps
CPU time 8.8 seconds
Started Apr 16 01:02:24 PM PDT 24
Finished Apr 16 01:02:34 PM PDT 24
Peak memory 204020 kb
Host smart-bd0d679f-fe11-4830-8c09-79825c5326d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17273
85103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.1727385103
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3116379554
Short name T35
Test name
Test status
Simulation time 8460252884 ps
CPU time 8.84 seconds
Started Apr 16 01:02:26 PM PDT 24
Finished Apr 16 01:02:36 PM PDT 24
Peak memory 204048 kb
Host smart-d7ec1e71-07b6-43dc-9b04-ed5ab87b0a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31163
79554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3116379554
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2704314754
Short name T575
Test name
Test status
Simulation time 8427012067 ps
CPU time 8.2 seconds
Started Apr 16 01:02:35 PM PDT 24
Finished Apr 16 01:02:44 PM PDT 24
Peak memory 204048 kb
Host smart-c7adc2c3-7327-417c-909f-9e861b50ee87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27043
14754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2704314754
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.3755537933
Short name T110
Test name
Test status
Simulation time 8435509322 ps
CPU time 8.05 seconds
Started Apr 16 01:02:40 PM PDT 24
Finished Apr 16 01:02:49 PM PDT 24
Peak memory 204032 kb
Host smart-0c3a43e5-3263-41a0-a1fb-1dc01001a915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37555
37933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3755537933
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.198817615
Short name T774
Test name
Test status
Simulation time 8388232027 ps
CPU time 7.84 seconds
Started Apr 16 01:02:47 PM PDT 24
Finished Apr 16 01:02:56 PM PDT 24
Peak memory 203980 kb
Host smart-d1d593b2-265e-430f-963f-af3b214f944c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19881
7615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.198817615
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.2668122202
Short name T102
Test name
Test status
Simulation time 8426656384 ps
CPU time 7.94 seconds
Started Apr 16 01:02:43 PM PDT 24
Finished Apr 16 01:02:53 PM PDT 24
Peak memory 204084 kb
Host smart-e0f0d24a-f1cc-4153-8b1b-d958b5dbd816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26681
22202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.2668122202
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.4124073243
Short name T385
Test name
Test status
Simulation time 8463816589 ps
CPU time 8.29 seconds
Started Apr 16 01:03:12 PM PDT 24
Finished Apr 16 01:03:21 PM PDT 24
Peak memory 203936 kb
Host smart-3a7f8e4b-ba10-4d8f-bb02-53185efae7db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41240
73243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.4124073243
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.3815302851
Short name T119
Test name
Test status
Simulation time 8472171019 ps
CPU time 8.12 seconds
Started Apr 16 01:03:07 PM PDT 24
Finished Apr 16 01:03:16 PM PDT 24
Peak memory 203940 kb
Host smart-0c8d4d8a-e3e7-415f-80f0-8854fc97c698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38153
02851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.3815302851
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.3174672757
Short name T116
Test name
Test status
Simulation time 8439141205 ps
CPU time 7.88 seconds
Started Apr 16 01:03:14 PM PDT 24
Finished Apr 16 01:03:23 PM PDT 24
Peak memory 203928 kb
Host smart-5c100826-d74e-47f4-800b-568f160f0448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31746
72757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3174672757
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.1407018630
Short name T1095
Test name
Test status
Simulation time 8363301933 ps
CPU time 8.04 seconds
Started Apr 16 01:03:17 PM PDT 24
Finished Apr 16 01:03:26 PM PDT 24
Peak memory 204036 kb
Host smart-314760ec-ce1e-4d03-b503-0410f7a6b437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14070
18630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.1407018630
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.2097021170
Short name T104
Test name
Test status
Simulation time 8440211042 ps
CPU time 7.68 seconds
Started Apr 16 01:03:47 PM PDT 24
Finished Apr 16 01:03:56 PM PDT 24
Peak memory 204048 kb
Host smart-955d8776-b4e2-4777-b7ec-f5abeff1a7e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20970
21170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2097021170
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.347919911
Short name T1348
Test name
Test status
Simulation time 8418669756 ps
CPU time 8.6 seconds
Started Apr 16 01:04:02 PM PDT 24
Finished Apr 16 01:04:11 PM PDT 24
Peak memory 203948 kb
Host smart-3af9d4f1-c5c7-4681-ac4a-990c48ee5c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34791
9911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.347919911
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.6874910
Short name T25
Test name
Test status
Simulation time 8401562329 ps
CPU time 9.04 seconds
Started Apr 16 01:04:00 PM PDT 24
Finished Apr 16 01:04:10 PM PDT 24
Peak memory 204016 kb
Host smart-4f3c631e-ead6-4a2b-90ac-1bb5dae3c4c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68749
10 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.6874910
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.613396181
Short name T122
Test name
Test status
Simulation time 8420257154 ps
CPU time 8.21 seconds
Started Apr 16 01:04:16 PM PDT 24
Finished Apr 16 01:04:25 PM PDT 24
Peak memory 204016 kb
Host smart-8e9fab83-2168-4d40-8e2f-b5d1ea92fd54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61339
6181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.613396181
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1700983648
Short name T121
Test name
Test status
Simulation time 8415000247 ps
CPU time 7.95 seconds
Started Apr 16 01:04:26 PM PDT 24
Finished Apr 16 01:04:35 PM PDT 24
Peak memory 203996 kb
Host smart-b89ea898-229b-469f-843f-e1bc3d4f366f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17009
83648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1700983648
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.2967566027
Short name T107
Test name
Test status
Simulation time 8427332606 ps
CPU time 9.91 seconds
Started Apr 16 01:05:04 PM PDT 24
Finished Apr 16 01:05:15 PM PDT 24
Peak memory 203984 kb
Host smart-54115dc7-85e7-46d5-8a17-71da096b5dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29675
66027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.2967566027
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.113698775
Short name T1381
Test name
Test status
Simulation time 111370483 ps
CPU time 2.03 seconds
Started Apr 16 12:44:27 PM PDT 24
Finished Apr 16 12:44:31 PM PDT 24
Peak memory 203560 kb
Host smart-fbebab29-2795-4550-9832-ec31d999be9a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=113698775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.113698775
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1739054539
Short name T223
Test name
Test status
Simulation time 137692099 ps
CPU time 0.92 seconds
Started Apr 16 12:44:28 PM PDT 24
Finished Apr 16 12:44:31 PM PDT 24
Peak memory 203260 kb
Host smart-660517f6-2af6-4b1a-91dc-1f8c428b2529
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1739054539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1739054539
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3675109321
Short name T1407
Test name
Test status
Simulation time 138350352 ps
CPU time 1.82 seconds
Started Apr 16 12:44:16 PM PDT 24
Finished Apr 16 12:44:19 PM PDT 24
Peak memory 211884 kb
Host smart-6937d0ca-3fdc-42c9-8e75-8a6c1423a43d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675109321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.3675109321
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2972386948
Short name T249
Test name
Test status
Simulation time 90790614 ps
CPU time 0.99 seconds
Started Apr 16 12:44:21 PM PDT 24
Finished Apr 16 12:44:23 PM PDT 24
Peak memory 203368 kb
Host smart-45363c0b-922a-4c58-928d-6c58f20f567d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2972386948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2972386948
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3342941112
Short name T1436
Test name
Test status
Simulation time 34588659 ps
CPU time 0.7 seconds
Started Apr 16 12:44:16 PM PDT 24
Finished Apr 16 12:44:18 PM PDT 24
Peak memory 203108 kb
Host smart-7e2b6e58-c4df-4c4a-ac07-5d823ecc20ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3342941112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3342941112
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.761968709
Short name T1417
Test name
Test status
Simulation time 158237545 ps
CPU time 3.73 seconds
Started Apr 16 12:44:15 PM PDT 24
Finished Apr 16 12:44:20 PM PDT 24
Peak memory 203608 kb
Host smart-5e9fe366-2e20-4997-be04-d8c538768479
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=761968709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.761968709
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.654281425
Short name T69
Test name
Test status
Simulation time 63197294 ps
CPU time 1.02 seconds
Started Apr 16 12:44:16 PM PDT 24
Finished Apr 16 12:44:18 PM PDT 24
Peak memory 203612 kb
Host smart-886f212d-c41b-4363-831a-4ab5e3ee4a27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=654281425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.654281425
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3754859421
Short name T226
Test name
Test status
Simulation time 384953716 ps
CPU time 3.8 seconds
Started Apr 16 12:44:16 PM PDT 24
Finished Apr 16 12:44:21 PM PDT 24
Peak memory 203720 kb
Host smart-3c85efcd-2a41-4389-85fa-023549d8bb4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3754859421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.3754859421
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3927046089
Short name T1451
Test name
Test status
Simulation time 394503539 ps
CPU time 3.74 seconds
Started Apr 16 12:44:21 PM PDT 24
Finished Apr 16 12:44:26 PM PDT 24
Peak memory 203472 kb
Host smart-d326dcba-f690-4e5e-a565-dbd9b16efa60
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3927046089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3927046089
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.378538778
Short name T242
Test name
Test status
Simulation time 258358655 ps
CPU time 4.19 seconds
Started Apr 16 12:44:21 PM PDT 24
Finished Apr 16 12:44:33 PM PDT 24
Peak memory 203516 kb
Host smart-92a3c691-2042-4798-b904-988ff11985c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=378538778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.378538778
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2016020568
Short name T257
Test name
Test status
Simulation time 58765026 ps
CPU time 0.94 seconds
Started Apr 16 12:44:26 PM PDT 24
Finished Apr 16 12:44:29 PM PDT 24
Peak memory 203596 kb
Host smart-b1f9ae27-d349-44a3-93c3-77abcf7e6ad9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2016020568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2016020568
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1500002369
Short name T1426
Test name
Test status
Simulation time 39333303 ps
CPU time 0.69 seconds
Started Apr 16 12:44:18 PM PDT 24
Finished Apr 16 12:44:20 PM PDT 24
Peak memory 202876 kb
Host smart-7763e6e8-a82a-496e-83eb-2e99e570fa1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1500002369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.1500002369
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.4093405057
Short name T1457
Test name
Test status
Simulation time 92849655 ps
CPU time 1.47 seconds
Started Apr 16 12:44:18 PM PDT 24
Finished Apr 16 12:44:21 PM PDT 24
Peak memory 203580 kb
Host smart-54c40771-6f94-4ae9-9fd7-7532d1e54059
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4093405057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.4093405057
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.437562257
Short name T1394
Test name
Test status
Simulation time 155932302 ps
CPU time 4.16 seconds
Started Apr 16 12:44:26 PM PDT 24
Finished Apr 16 12:44:32 PM PDT 24
Peak memory 203576 kb
Host smart-4af1a0c7-bbc4-4ea0-b95c-3ff3382728df
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=437562257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.437562257
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.32436443
Short name T201
Test name
Test status
Simulation time 126016774 ps
CPU time 1.42 seconds
Started Apr 16 12:44:33 PM PDT 24
Finished Apr 16 12:44:36 PM PDT 24
Peak memory 203644 kb
Host smart-f78fc3d7-69d3-491f-b363-70de001a3a06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=32436443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.32436443
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2104645775
Short name T62
Test name
Test status
Simulation time 235522068 ps
CPU time 2.94 seconds
Started Apr 16 12:44:16 PM PDT 24
Finished Apr 16 12:44:19 PM PDT 24
Peak memory 203732 kb
Host smart-75e64e7e-b28b-4ef8-8319-ee85fb025c02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2104645775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.2104645775
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3840518035
Short name T206
Test name
Test status
Simulation time 122941178 ps
CPU time 2.28 seconds
Started Apr 16 12:44:27 PM PDT 24
Finished Apr 16 12:44:32 PM PDT 24
Peak memory 211944 kb
Host smart-b17866c5-479f-427e-9d8c-acb9b22dbfd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840518035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.3840518035
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3521448555
Short name T1449
Test name
Test status
Simulation time 57132726 ps
CPU time 0.96 seconds
Started Apr 16 12:44:37 PM PDT 24
Finished Apr 16 12:44:39 PM PDT 24
Peak memory 203628 kb
Host smart-0b8dc500-b141-42ce-b930-29b3f0f1a1b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3521448555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3521448555
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.116679722
Short name T252
Test name
Test status
Simulation time 42086937 ps
CPU time 1.01 seconds
Started Apr 16 12:44:37 PM PDT 24
Finished Apr 16 12:44:39 PM PDT 24
Peak memory 203632 kb
Host smart-702bd0a6-b2c4-41f6-b1a3-a54503f1d5bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=116679722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.116679722
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1394003731
Short name T1415
Test name
Test status
Simulation time 341140341 ps
CPU time 2.68 seconds
Started Apr 16 12:44:41 PM PDT 24
Finished Apr 16 12:44:45 PM PDT 24
Peak memory 203648 kb
Host smart-87a0766c-51e7-4eff-a0af-fe9f35284362
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1394003731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1394003731
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2319597704
Short name T1403
Test name
Test status
Simulation time 316501048 ps
CPU time 2.39 seconds
Started Apr 16 12:44:17 PM PDT 24
Finished Apr 16 12:44:21 PM PDT 24
Peak memory 203664 kb
Host smart-f8a61a29-8161-4220-bf62-daa821deb61d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2319597704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2319597704
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3470725961
Short name T1438
Test name
Test status
Simulation time 142438283 ps
CPU time 1.81 seconds
Started Apr 16 12:44:34 PM PDT 24
Finished Apr 16 12:44:37 PM PDT 24
Peak memory 211840 kb
Host smart-042da08d-0e17-4bd4-ac19-6488016a5d16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470725961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.3470725961
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.713339063
Short name T1458
Test name
Test status
Simulation time 66461380 ps
CPU time 1 seconds
Started Apr 16 12:44:26 PM PDT 24
Finished Apr 16 12:44:29 PM PDT 24
Peak memory 203548 kb
Host smart-fad31f2d-eca8-4f70-bb9b-839c207975d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=713339063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.713339063
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1900251698
Short name T1385
Test name
Test status
Simulation time 26996878 ps
CPU time 0.65 seconds
Started Apr 16 12:44:30 PM PDT 24
Finished Apr 16 12:44:33 PM PDT 24
Peak memory 202836 kb
Host smart-431b2db4-ad9f-4c8d-a45a-5c0cb5cc4645
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1900251698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1900251698
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.979008409
Short name T253
Test name
Test status
Simulation time 43729260 ps
CPU time 1 seconds
Started Apr 16 12:44:21 PM PDT 24
Finished Apr 16 12:44:23 PM PDT 24
Peak memory 203620 kb
Host smart-61945ab0-78ce-45c0-9380-c58232d59cc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=979008409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.979008409
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3461299561
Short name T1447
Test name
Test status
Simulation time 112154418 ps
CPU time 1.47 seconds
Started Apr 16 12:44:35 PM PDT 24
Finished Apr 16 12:44:43 PM PDT 24
Peak memory 203680 kb
Host smart-3fe59358-2db9-45e1-adcd-1ddac0237e03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3461299561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3461299561
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2467668267
Short name T258
Test name
Test status
Simulation time 495563672 ps
CPU time 2.73 seconds
Started Apr 16 12:44:38 PM PDT 24
Finished Apr 16 12:44:42 PM PDT 24
Peak memory 203640 kb
Host smart-aea0dbcf-7272-4e30-96a4-5a0b6a5cb198
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2467668267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.2467668267
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.528483466
Short name T1418
Test name
Test status
Simulation time 88307272 ps
CPU time 1.96 seconds
Started Apr 16 12:44:23 PM PDT 24
Finished Apr 16 12:44:26 PM PDT 24
Peak memory 211940 kb
Host smart-3083eb72-a220-4d54-81ef-5e9b5fbee573
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528483466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde
v_csr_mem_rw_with_rand_reset.528483466
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3316213657
Short name T1380
Test name
Test status
Simulation time 51651323 ps
CPU time 0.75 seconds
Started Apr 16 12:44:44 PM PDT 24
Finished Apr 16 12:44:46 PM PDT 24
Peak memory 203328 kb
Host smart-89713ff8-89a3-469f-b90f-5e2fc9ad3afc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3316213657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3316213657
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1545569380
Short name T1442
Test name
Test status
Simulation time 31785873 ps
CPU time 0.71 seconds
Started Apr 16 12:44:28 PM PDT 24
Finished Apr 16 12:44:31 PM PDT 24
Peak memory 202848 kb
Host smart-43a1dba6-5aa4-42c1-a698-a1c812ad7425
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1545569380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1545569380
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.303286850
Short name T1432
Test name
Test status
Simulation time 115922871 ps
CPU time 1.19 seconds
Started Apr 16 12:44:39 PM PDT 24
Finished Apr 16 12:44:41 PM PDT 24
Peak memory 203644 kb
Host smart-74700d57-0748-47a7-9c2b-4c350ec6d7a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=303286850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.303286850
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.678890997
Short name T1464
Test name
Test status
Simulation time 127894079 ps
CPU time 1.66 seconds
Started Apr 16 12:44:26 PM PDT 24
Finished Apr 16 12:44:30 PM PDT 24
Peak memory 203716 kb
Host smart-c5bd8821-2f3d-4635-b88e-65bea3013dbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=678890997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.678890997
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.325368175
Short name T256
Test name
Test status
Simulation time 811133023 ps
CPU time 4.81 seconds
Started Apr 16 12:44:28 PM PDT 24
Finished Apr 16 12:44:35 PM PDT 24
Peak memory 203696 kb
Host smart-37683526-c147-4192-966b-891cd712c892
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=325368175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.325368175
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3377774322
Short name T63
Test name
Test status
Simulation time 110136886 ps
CPU time 2.66 seconds
Started Apr 16 12:44:38 PM PDT 24
Finished Apr 16 12:44:42 PM PDT 24
Peak memory 211824 kb
Host smart-89b5a1d1-7aac-44f3-8be7-504795c8a3ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377774322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.3377774322
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1331729820
Short name T1477
Test name
Test status
Simulation time 78471395 ps
CPU time 1.08 seconds
Started Apr 16 12:44:34 PM PDT 24
Finished Apr 16 12:44:37 PM PDT 24
Peak memory 203648 kb
Host smart-62d2e5ff-5206-4b52-855b-12c8b1d592ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1331729820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1331729820
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1380755971
Short name T1462
Test name
Test status
Simulation time 38454615 ps
CPU time 0.7 seconds
Started Apr 16 12:44:39 PM PDT 24
Finished Apr 16 12:44:41 PM PDT 24
Peak memory 202856 kb
Host smart-175703d9-9d51-4a63-8c43-df2756f7bd0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1380755971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1380755971
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1088055658
Short name T1437
Test name
Test status
Simulation time 169578798 ps
CPU time 1.6 seconds
Started Apr 16 12:44:35 PM PDT 24
Finished Apr 16 12:44:38 PM PDT 24
Peak memory 203648 kb
Host smart-46e1e886-5469-449b-b83d-8d758f5516f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1088055658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1088055658
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3628468459
Short name T1393
Test name
Test status
Simulation time 201153114 ps
CPU time 2.39 seconds
Started Apr 16 12:44:46 PM PDT 24
Finished Apr 16 12:44:50 PM PDT 24
Peak memory 203740 kb
Host smart-0a41f1e5-3d99-4b24-b812-0985a1f1ace3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3628468459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3628468459
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3170350
Short name T1454
Test name
Test status
Simulation time 536919418 ps
CPU time 4.16 seconds
Started Apr 16 12:44:35 PM PDT 24
Finished Apr 16 12:44:40 PM PDT 24
Peak memory 203680 kb
Host smart-119d202c-13e1-47a5-b5e1-e0e43a77a02c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3170350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3170350
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2806529786
Short name T1441
Test name
Test status
Simulation time 225683451 ps
CPU time 1.84 seconds
Started Apr 16 12:44:38 PM PDT 24
Finished Apr 16 12:44:41 PM PDT 24
Peak memory 211828 kb
Host smart-067ea6d9-4fcf-426c-b4ca-51578a591aa6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806529786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2806529786
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4115717117
Short name T251
Test name
Test status
Simulation time 28512844 ps
CPU time 0.81 seconds
Started Apr 16 12:44:26 PM PDT 24
Finished Apr 16 12:44:30 PM PDT 24
Peak memory 203356 kb
Host smart-6d2b79b7-1fb2-4884-a20c-c9aad85f9a05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4115717117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.4115717117
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1086686176
Short name T275
Test name
Test status
Simulation time 32053517 ps
CPU time 0.65 seconds
Started Apr 16 12:44:32 PM PDT 24
Finished Apr 16 12:44:34 PM PDT 24
Peak memory 202760 kb
Host smart-ff44e93d-fbd2-47cb-ab3e-2af1e12afaf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1086686176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1086686176
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1543525461
Short name T1401
Test name
Test status
Simulation time 284835505 ps
CPU time 1.35 seconds
Started Apr 16 12:44:37 PM PDT 24
Finished Apr 16 12:44:39 PM PDT 24
Peak memory 203616 kb
Host smart-af4e9b5c-8d26-4290-8775-87996515623b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1543525461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.1543525461
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.342111361
Short name T1440
Test name
Test status
Simulation time 67276329 ps
CPU time 1.84 seconds
Started Apr 16 12:44:30 PM PDT 24
Finished Apr 16 12:44:38 PM PDT 24
Peak memory 203692 kb
Host smart-0abd527b-5483-4be2-bf54-bc75a8832b07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=342111361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.342111361
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.721492930
Short name T278
Test name
Test status
Simulation time 564338875 ps
CPU time 4.01 seconds
Started Apr 16 12:44:20 PM PDT 24
Finished Apr 16 12:44:25 PM PDT 24
Peak memory 203728 kb
Host smart-b1f091fd-7742-417a-9386-185c3e17149b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=721492930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.721492930
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.479810477
Short name T64
Test name
Test status
Simulation time 201787018 ps
CPU time 1.41 seconds
Started Apr 16 12:45:01 PM PDT 24
Finished Apr 16 12:45:04 PM PDT 24
Peak memory 211920 kb
Host smart-f61f666c-3024-4cb3-991f-dd61fe856f70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479810477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.479810477
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2746752901
Short name T245
Test name
Test status
Simulation time 41094056 ps
CPU time 1.02 seconds
Started Apr 16 12:44:33 PM PDT 24
Finished Apr 16 12:44:36 PM PDT 24
Peak memory 203548 kb
Host smart-2becc865-e0e5-439f-90ec-cce4a1bb13a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2746752901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2746752901
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2026352724
Short name T272
Test name
Test status
Simulation time 54196195 ps
CPU time 0.69 seconds
Started Apr 16 12:44:30 PM PDT 24
Finished Apr 16 12:44:33 PM PDT 24
Peak memory 202844 kb
Host smart-632eda71-108d-4fe2-a0e1-4260e8951209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2026352724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2026352724
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.4230094895
Short name T1383
Test name
Test status
Simulation time 76788808 ps
CPU time 1.5 seconds
Started Apr 16 12:44:22 PM PDT 24
Finished Apr 16 12:44:25 PM PDT 24
Peak memory 203628 kb
Host smart-f039dc9e-c16e-4211-b728-71fff1b9ff61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4230094895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.4230094895
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3137780498
Short name T205
Test name
Test status
Simulation time 807583912 ps
CPU time 4.47 seconds
Started Apr 16 12:44:32 PM PDT 24
Finished Apr 16 12:44:38 PM PDT 24
Peak memory 203668 kb
Host smart-9f3f69ec-0660-4872-a188-c4f36bdc4a33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3137780498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.3137780498
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.997999083
Short name T1396
Test name
Test status
Simulation time 90106010 ps
CPU time 1.36 seconds
Started Apr 16 12:44:37 PM PDT 24
Finished Apr 16 12:44:40 PM PDT 24
Peak memory 211852 kb
Host smart-d557fed5-db1b-4321-b13c-a05e042a6e1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997999083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbde
v_csr_mem_rw_with_rand_reset.997999083
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.435083761
Short name T200
Test name
Test status
Simulation time 44474307 ps
CPU time 0.79 seconds
Started Apr 16 12:44:29 PM PDT 24
Finished Apr 16 12:44:32 PM PDT 24
Peak memory 203264 kb
Host smart-d5c4a051-0cb2-4e6c-ab68-59bf42fd1388
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=435083761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.435083761
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3433259219
Short name T1471
Test name
Test status
Simulation time 222686311 ps
CPU time 1.43 seconds
Started Apr 16 12:44:38 PM PDT 24
Finished Apr 16 12:44:41 PM PDT 24
Peak memory 203632 kb
Host smart-2cef6095-a562-403c-b393-0749a09fbaee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3433259219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3433259219
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3495421115
Short name T1419
Test name
Test status
Simulation time 75497545 ps
CPU time 1.77 seconds
Started Apr 16 12:44:25 PM PDT 24
Finished Apr 16 12:44:28 PM PDT 24
Peak memory 203744 kb
Host smart-ab732dcd-068d-46aa-b572-e603a947b80e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3495421115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3495421115
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.605900331
Short name T204
Test name
Test status
Simulation time 583915803 ps
CPU time 4.65 seconds
Started Apr 16 12:44:45 PM PDT 24
Finished Apr 16 12:44:51 PM PDT 24
Peak memory 203668 kb
Host smart-957ca269-eb7d-4846-a12a-1aee83b28763
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=605900331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.605900331
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.820834491
Short name T1387
Test name
Test status
Simulation time 55553553 ps
CPU time 1.4 seconds
Started Apr 16 12:44:29 PM PDT 24
Finished Apr 16 12:44:33 PM PDT 24
Peak memory 211880 kb
Host smart-880cba55-ff2b-4ae1-9c68-6f8172a98af0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820834491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbde
v_csr_mem_rw_with_rand_reset.820834491
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.104390635
Short name T202
Test name
Test status
Simulation time 54310167 ps
CPU time 0.88 seconds
Started Apr 16 12:44:35 PM PDT 24
Finished Apr 16 12:44:37 PM PDT 24
Peak memory 203376 kb
Host smart-38893842-7310-4bd7-90af-36151ee324cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=104390635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.104390635
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.442673887
Short name T264
Test name
Test status
Simulation time 38003145 ps
CPU time 0.67 seconds
Started Apr 16 12:44:36 PM PDT 24
Finished Apr 16 12:44:38 PM PDT 24
Peak memory 202856 kb
Host smart-67017cd1-aac7-4ae1-9b15-30188038ed1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=442673887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.442673887
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3859446549
Short name T1431
Test name
Test status
Simulation time 45335028 ps
CPU time 0.99 seconds
Started Apr 16 12:44:33 PM PDT 24
Finished Apr 16 12:44:36 PM PDT 24
Peak memory 203632 kb
Host smart-e1cc1736-103f-4c5f-bc11-89732d2323ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3859446549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.3859446549
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2579189529
Short name T208
Test name
Test status
Simulation time 187443584 ps
CPU time 2.21 seconds
Started Apr 16 12:44:28 PM PDT 24
Finished Apr 16 12:44:33 PM PDT 24
Peak memory 203676 kb
Host smart-4bdcfc05-c5bf-4d90-acf4-a9b10d132e85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2579189529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2579189529
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3895231051
Short name T1465
Test name
Test status
Simulation time 451298726 ps
CPU time 2.75 seconds
Started Apr 16 12:44:27 PM PDT 24
Finished Apr 16 12:44:33 PM PDT 24
Peak memory 203628 kb
Host smart-369768de-b1c8-4b01-bc49-331e699aa5e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3895231051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3895231051
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3133764091
Short name T1409
Test name
Test status
Simulation time 136395501 ps
CPU time 1.81 seconds
Started Apr 16 12:44:32 PM PDT 24
Finished Apr 16 12:44:36 PM PDT 24
Peak memory 211796 kb
Host smart-c436b18f-e18c-4dc5-84f5-4cb60586c1ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133764091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.3133764091
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.143828649
Short name T1411
Test name
Test status
Simulation time 60313258 ps
CPU time 0.8 seconds
Started Apr 16 12:44:43 PM PDT 24
Finished Apr 16 12:44:45 PM PDT 24
Peak memory 203316 kb
Host smart-a49dcae4-15cb-4417-9175-16d3e305d466
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=143828649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.143828649
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2511810590
Short name T1452
Test name
Test status
Simulation time 39018432 ps
CPU time 0.66 seconds
Started Apr 16 12:44:32 PM PDT 24
Finished Apr 16 12:44:35 PM PDT 24
Peak memory 202784 kb
Host smart-03a2f97b-dafe-4fa4-a5db-e478e7509e02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2511810590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.2511810590
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3113393145
Short name T1408
Test name
Test status
Simulation time 82709615 ps
CPU time 1.03 seconds
Started Apr 16 12:44:28 PM PDT 24
Finished Apr 16 12:44:32 PM PDT 24
Peak memory 203636 kb
Host smart-750a1523-efe1-4c3c-a6f2-0d59eefa1aed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3113393145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3113393145
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3337834192
Short name T1459
Test name
Test status
Simulation time 353968147 ps
CPU time 3.62 seconds
Started Apr 16 12:44:28 PM PDT 24
Finished Apr 16 12:44:34 PM PDT 24
Peak memory 203624 kb
Host smart-22f3ed4e-5cf3-4774-8306-f1c19e86d11d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3337834192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3337834192
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.89744578
Short name T279
Test name
Test status
Simulation time 452655096 ps
CPU time 2.99 seconds
Started Apr 16 12:44:26 PM PDT 24
Finished Apr 16 12:44:31 PM PDT 24
Peak memory 203740 kb
Host smart-d0efefa5-3c1d-4dd1-9a8a-549dfd63c180
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=89744578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.89744578
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2253360050
Short name T1382
Test name
Test status
Simulation time 127692559 ps
CPU time 2.42 seconds
Started Apr 16 12:44:28 PM PDT 24
Finished Apr 16 12:44:33 PM PDT 24
Peak memory 211848 kb
Host smart-6da2af41-e21d-48d3-8245-bb70baf166ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253360050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.2253360050
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2394504326
Short name T1433
Test name
Test status
Simulation time 40219407 ps
CPU time 0.75 seconds
Started Apr 16 12:44:47 PM PDT 24
Finished Apr 16 12:44:49 PM PDT 24
Peak memory 203324 kb
Host smart-e0be61e8-d7dc-4503-9508-286ffeaa7327
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2394504326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2394504326
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.938918023
Short name T73
Test name
Test status
Simulation time 41647272 ps
CPU time 0.69 seconds
Started Apr 16 12:44:31 PM PDT 24
Finished Apr 16 12:44:34 PM PDT 24
Peak memory 201956 kb
Host smart-94fe76b3-59fd-4889-a59c-93013819917f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=938918023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.938918023
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3295296598
Short name T1389
Test name
Test status
Simulation time 160791430 ps
CPU time 1.65 seconds
Started Apr 16 12:44:37 PM PDT 24
Finished Apr 16 12:44:40 PM PDT 24
Peak memory 203640 kb
Host smart-f385a4e3-e0c0-42ed-a5ae-18742ea92270
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3295296598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.3295296598
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.4041313940
Short name T1445
Test name
Test status
Simulation time 939395620 ps
CPU time 3.66 seconds
Started Apr 16 12:44:28 PM PDT 24
Finished Apr 16 12:44:34 PM PDT 24
Peak memory 203672 kb
Host smart-8cee2b14-09f1-4a22-8712-c71cc8f6ca7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4041313940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.4041313940
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2302650871
Short name T250
Test name
Test status
Simulation time 337717847 ps
CPU time 3.53 seconds
Started Apr 16 12:44:32 PM PDT 24
Finished Apr 16 12:44:37 PM PDT 24
Peak memory 203616 kb
Host smart-ac37e906-fc82-4c03-9227-d5305e0ee5d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2302650871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2302650871
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.445509822
Short name T248
Test name
Test status
Simulation time 725792811 ps
CPU time 4.67 seconds
Started Apr 16 12:44:23 PM PDT 24
Finished Apr 16 12:44:30 PM PDT 24
Peak memory 203636 kb
Host smart-93715a93-c835-487c-a4ba-fa3c5fe2417b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=445509822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.445509822
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3003266222
Short name T222
Test name
Test status
Simulation time 77525587 ps
CPU time 0.89 seconds
Started Apr 16 12:44:22 PM PDT 24
Finished Apr 16 12:44:25 PM PDT 24
Peak memory 203400 kb
Host smart-dca53afe-00ec-4936-b939-92ec1487183a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3003266222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3003266222
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2282358355
Short name T220
Test name
Test status
Simulation time 60767781 ps
CPU time 1.5 seconds
Started Apr 16 12:44:17 PM PDT 24
Finished Apr 16 12:44:20 PM PDT 24
Peak memory 211896 kb
Host smart-df413ad8-7622-4ec2-8838-14b967692532
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282358355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.2282358355
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2780387260
Short name T1378
Test name
Test status
Simulation time 77735606 ps
CPU time 0.88 seconds
Started Apr 16 12:44:17 PM PDT 24
Finished Apr 16 12:44:19 PM PDT 24
Peak memory 203196 kb
Host smart-e5ac984a-7fe6-488c-8ef2-fc42b82ae189
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2780387260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2780387260
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.52645405
Short name T273
Test name
Test status
Simulation time 31504158 ps
CPU time 0.68 seconds
Started Apr 16 12:44:31 PM PDT 24
Finished Apr 16 12:44:34 PM PDT 24
Peak memory 202792 kb
Host smart-8a4be81d-31c0-48eb-a428-d5ad86f42dcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=52645405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.52645405
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.148076106
Short name T1430
Test name
Test status
Simulation time 179791878 ps
CPU time 2.34 seconds
Started Apr 16 12:44:15 PM PDT 24
Finished Apr 16 12:44:18 PM PDT 24
Peak memory 211872 kb
Host smart-be845847-f189-4d10-abff-21caad697542
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=148076106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.148076106
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.480375995
Short name T1404
Test name
Test status
Simulation time 720602552 ps
CPU time 4.84 seconds
Started Apr 16 12:44:29 PM PDT 24
Finished Apr 16 12:44:36 PM PDT 24
Peak memory 203484 kb
Host smart-b4d14c37-e3d1-4377-b1a8-897892e4c8b0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=480375995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.480375995
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2739390657
Short name T1420
Test name
Test status
Simulation time 106790122 ps
CPU time 1.08 seconds
Started Apr 16 12:44:13 PM PDT 24
Finished Apr 16 12:44:20 PM PDT 24
Peak memory 203556 kb
Host smart-95325af5-15ff-4e2a-b926-1c6d751f25e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2739390657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2739390657
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1738203330
Short name T218
Test name
Test status
Simulation time 60163325 ps
CPU time 1.6 seconds
Started Apr 16 12:44:15 PM PDT 24
Finished Apr 16 12:44:17 PM PDT 24
Peak memory 203624 kb
Host smart-d14d43c5-d67a-4ddf-b35e-b65a07414678
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1738203330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1738203330
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2661480630
Short name T1384
Test name
Test status
Simulation time 303036964 ps
CPU time 2.33 seconds
Started Apr 16 12:44:16 PM PDT 24
Finished Apr 16 12:44:25 PM PDT 24
Peak memory 203704 kb
Host smart-cf422427-6edd-422c-987d-fa97c36a785e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2661480630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2661480630
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.4048628452
Short name T1473
Test name
Test status
Simulation time 34528775 ps
CPU time 0.65 seconds
Started Apr 16 12:44:55 PM PDT 24
Finished Apr 16 12:44:56 PM PDT 24
Peak memory 202772 kb
Host smart-af64c34a-e850-4171-91ed-06d73f312774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4048628452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.4048628452
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1196664629
Short name T1446
Test name
Test status
Simulation time 31452663 ps
CPU time 0.68 seconds
Started Apr 16 12:44:35 PM PDT 24
Finished Apr 16 12:44:37 PM PDT 24
Peak memory 202824 kb
Host smart-23202d80-6227-4d1d-83cb-6e2c0efc12d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1196664629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.1196664629
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.695737302
Short name T74
Test name
Test status
Simulation time 84244613 ps
CPU time 0.7 seconds
Started Apr 16 12:44:31 PM PDT 24
Finished Apr 16 12:44:34 PM PDT 24
Peak memory 202828 kb
Host smart-0380e521-a1a1-47b2-9e9e-8927e9497d29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=695737302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.695737302
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3069568305
Short name T1475
Test name
Test status
Simulation time 50735909 ps
CPU time 0.66 seconds
Started Apr 16 12:44:44 PM PDT 24
Finished Apr 16 12:44:46 PM PDT 24
Peak memory 202864 kb
Host smart-0f413503-ee06-4946-9ebe-51a87c39295d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3069568305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.3069568305
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1141099832
Short name T1422
Test name
Test status
Simulation time 39554877 ps
CPU time 0.66 seconds
Started Apr 16 12:44:49 PM PDT 24
Finished Apr 16 12:44:51 PM PDT 24
Peak memory 202848 kb
Host smart-1a93bd6c-224d-4ec5-a9f6-9fbb4c3f48cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1141099832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1141099832
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1268279316
Short name T1460
Test name
Test status
Simulation time 35072388 ps
CPU time 0.65 seconds
Started Apr 16 12:44:47 PM PDT 24
Finished Apr 16 12:44:48 PM PDT 24
Peak memory 202836 kb
Host smart-57846cfd-b3fe-4b78-a3f8-203538a4e2b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1268279316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1268279316
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3166881259
Short name T1413
Test name
Test status
Simulation time 47009300 ps
CPU time 0.69 seconds
Started Apr 16 12:44:37 PM PDT 24
Finished Apr 16 12:44:39 PM PDT 24
Peak memory 202868 kb
Host smart-72fde075-4be6-4222-a7c4-378eaa1158e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3166881259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3166881259
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.148108087
Short name T263
Test name
Test status
Simulation time 66493995 ps
CPU time 0.72 seconds
Started Apr 16 12:44:47 PM PDT 24
Finished Apr 16 12:44:49 PM PDT 24
Peak memory 202876 kb
Host smart-155890a5-36e8-4410-a482-f5686211e4ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=148108087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.148108087
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3804526783
Short name T198
Test name
Test status
Simulation time 193197682 ps
CPU time 2 seconds
Started Apr 16 12:44:29 PM PDT 24
Finished Apr 16 12:44:33 PM PDT 24
Peak memory 203544 kb
Host smart-cf598a7e-6922-4d37-8fa0-3b683c22e738
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3804526783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3804526783
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1520228630
Short name T1467
Test name
Test status
Simulation time 1226653583 ps
CPU time 8.24 seconds
Started Apr 16 12:44:17 PM PDT 24
Finished Apr 16 12:44:26 PM PDT 24
Peak memory 203516 kb
Host smart-ae210d75-cd1c-4a7e-a5c3-feb66abbbe27
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1520228630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1520228630
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1108971722
Short name T21
Test name
Test status
Simulation time 96546213 ps
CPU time 0.95 seconds
Started Apr 16 12:44:43 PM PDT 24
Finished Apr 16 12:44:45 PM PDT 24
Peak memory 203292 kb
Host smart-3412c2ca-4db9-4bb1-a9c1-5e6c9c3bb4de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1108971722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1108971722
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.572299047
Short name T1395
Test name
Test status
Simulation time 82124009 ps
CPU time 2.14 seconds
Started Apr 16 12:44:28 PM PDT 24
Finished Apr 16 12:44:33 PM PDT 24
Peak memory 211920 kb
Host smart-04f2041c-88fc-48ea-969d-78a6da5a4249
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572299047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev
_csr_mem_rw_with_rand_reset.572299047
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3289747025
Short name T243
Test name
Test status
Simulation time 74982395 ps
CPU time 1.02 seconds
Started Apr 16 12:44:22 PM PDT 24
Finished Apr 16 12:44:24 PM PDT 24
Peak memory 203532 kb
Host smart-0aa17d16-90e6-4555-a80b-9836333497d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3289747025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3289747025
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3330536265
Short name T268
Test name
Test status
Simulation time 28909481 ps
CPU time 0.69 seconds
Started Apr 16 12:44:17 PM PDT 24
Finished Apr 16 12:44:18 PM PDT 24
Peak memory 202764 kb
Host smart-c44d6325-360c-43fb-b19b-9c712dfaf807
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3330536265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3330536265
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1166826959
Short name T244
Test name
Test status
Simulation time 97601661 ps
CPU time 1.5 seconds
Started Apr 16 12:44:44 PM PDT 24
Finished Apr 16 12:44:47 PM PDT 24
Peak memory 203680 kb
Host smart-20aae1d3-6c40-469b-90b5-2ee2a2e95276
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1166826959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1166826959
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3043142480
Short name T1456
Test name
Test status
Simulation time 90554832 ps
CPU time 2.32 seconds
Started Apr 16 12:44:18 PM PDT 24
Finished Apr 16 12:44:22 PM PDT 24
Peak memory 203616 kb
Host smart-b3cd3a62-e971-4085-9c0c-e034c442837b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3043142480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3043142480
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1298084345
Short name T1416
Test name
Test status
Simulation time 90061057 ps
CPU time 1.16 seconds
Started Apr 16 12:44:29 PM PDT 24
Finished Apr 16 12:44:32 PM PDT 24
Peak memory 203688 kb
Host smart-5e4de5ce-ad99-41cf-b63b-13a1742196ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1298084345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.1298084345
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1242799546
Short name T207
Test name
Test status
Simulation time 91998183 ps
CPU time 2.69 seconds
Started Apr 16 12:44:21 PM PDT 24
Finished Apr 16 12:44:25 PM PDT 24
Peak memory 203592 kb
Host smart-17be1697-6c5e-42ea-96a5-d36f8457e159
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1242799546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.1242799546
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.305818586
Short name T276
Test name
Test status
Simulation time 592323566 ps
CPU time 4.63 seconds
Started Apr 16 12:44:14 PM PDT 24
Finished Apr 16 12:44:19 PM PDT 24
Peak memory 203664 kb
Host smart-f9494999-5626-47e6-bcb6-b5f7c00e6856
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=305818586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.305818586
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.554362838
Short name T271
Test name
Test status
Simulation time 38924688 ps
CPU time 0.66 seconds
Started Apr 16 12:44:50 PM PDT 24
Finished Apr 16 12:44:51 PM PDT 24
Peak memory 202868 kb
Host smart-20b2642d-578a-4c4a-a5a3-9bf34771c6a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=554362838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.554362838
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3258176416
Short name T1410
Test name
Test status
Simulation time 28690394 ps
CPU time 0.66 seconds
Started Apr 16 12:44:36 PM PDT 24
Finished Apr 16 12:44:38 PM PDT 24
Peak memory 202800 kb
Host smart-e432437a-4b28-492d-b407-455fec00e729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3258176416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3258176416
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1254685498
Short name T259
Test name
Test status
Simulation time 39609963 ps
CPU time 0.69 seconds
Started Apr 16 12:44:40 PM PDT 24
Finished Apr 16 12:44:41 PM PDT 24
Peak memory 202760 kb
Host smart-42692712-f611-4ccc-a156-177c38724e15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1254685498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1254685498
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1609555784
Short name T1400
Test name
Test status
Simulation time 28566591 ps
CPU time 0.65 seconds
Started Apr 16 12:44:41 PM PDT 24
Finished Apr 16 12:44:42 PM PDT 24
Peak memory 202768 kb
Host smart-cde756e6-3d50-45ef-9830-27df257fd0c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1609555784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.1609555784
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1295702213
Short name T1429
Test name
Test status
Simulation time 41316047 ps
CPU time 0.64 seconds
Started Apr 16 12:44:41 PM PDT 24
Finished Apr 16 12:44:42 PM PDT 24
Peak memory 202768 kb
Host smart-51674939-1a54-412f-99f1-39d198ed218c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1295702213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1295702213
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2100974903
Short name T1421
Test name
Test status
Simulation time 37252787 ps
CPU time 0.72 seconds
Started Apr 16 12:44:53 PM PDT 24
Finished Apr 16 12:45:01 PM PDT 24
Peak memory 202820 kb
Host smart-679f74e1-0299-4bd9-8060-84228f6a04d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2100974903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.2100974903
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3564394869
Short name T265
Test name
Test status
Simulation time 28280780 ps
CPU time 0.71 seconds
Started Apr 16 12:44:33 PM PDT 24
Finished Apr 16 12:44:36 PM PDT 24
Peak memory 202876 kb
Host smart-f8bdca0b-6d35-4a98-994d-454153239c32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3564394869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3564394869
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1733816471
Short name T1388
Test name
Test status
Simulation time 31346676 ps
CPU time 0.68 seconds
Started Apr 16 12:44:34 PM PDT 24
Finished Apr 16 12:44:37 PM PDT 24
Peak memory 202924 kb
Host smart-c09263d1-5e1d-45ae-8da0-f96ffd051f00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1733816471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1733816471
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3795039767
Short name T1469
Test name
Test status
Simulation time 45086069 ps
CPU time 0.68 seconds
Started Apr 16 12:44:47 PM PDT 24
Finished Apr 16 12:44:49 PM PDT 24
Peak memory 202780 kb
Host smart-18878e50-b65b-432d-b208-d7b59d96a1d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3795039767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3795039767
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2014208247
Short name T246
Test name
Test status
Simulation time 285773953 ps
CPU time 3.5 seconds
Started Apr 16 12:44:28 PM PDT 24
Finished Apr 16 12:44:34 PM PDT 24
Peak memory 203632 kb
Host smart-3731dfee-265b-4a22-9c6f-adb57f00c71d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2014208247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2014208247
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1816782935
Short name T247
Test name
Test status
Simulation time 595862117 ps
CPU time 4.16 seconds
Started Apr 16 12:44:36 PM PDT 24
Finished Apr 16 12:44:41 PM PDT 24
Peak memory 203512 kb
Host smart-41307320-9f06-4d61-927f-d880e27e2c01
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1816782935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1816782935
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.755356222
Short name T1434
Test name
Test status
Simulation time 197665914 ps
CPU time 0.92 seconds
Started Apr 16 12:44:18 PM PDT 24
Finished Apr 16 12:44:20 PM PDT 24
Peak memory 203308 kb
Host smart-4bf96b2b-37d1-421f-ba30-05c6992b54a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=755356222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.755356222
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3809099278
Short name T1468
Test name
Test status
Simulation time 87861990 ps
CPU time 1.28 seconds
Started Apr 16 12:44:25 PM PDT 24
Finished Apr 16 12:44:29 PM PDT 24
Peak memory 213016 kb
Host smart-f755cad8-2b49-49f9-a260-0a02a3ac4979
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809099278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.3809099278
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1647720262
Short name T1428
Test name
Test status
Simulation time 82603822 ps
CPU time 0.84 seconds
Started Apr 16 12:44:22 PM PDT 24
Finished Apr 16 12:44:25 PM PDT 24
Peak memory 203276 kb
Host smart-3675ffcc-dc36-4238-9a65-1baf15c6a516
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1647720262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.1647720262
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.4276086240
Short name T1461
Test name
Test status
Simulation time 32199735 ps
CPU time 0.64 seconds
Started Apr 16 12:44:27 PM PDT 24
Finished Apr 16 12:44:30 PM PDT 24
Peak memory 202852 kb
Host smart-0d4921ca-d898-45e9-a546-d19effda5190
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4276086240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.4276086240
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2187186326
Short name T1463
Test name
Test status
Simulation time 129058929 ps
CPU time 2.16 seconds
Started Apr 16 12:44:25 PM PDT 24
Finished Apr 16 12:44:34 PM PDT 24
Peak memory 211908 kb
Host smart-92c687ff-1a54-442d-bd0c-6c3799ffa441
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2187186326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2187186326
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3213271969
Short name T1391
Test name
Test status
Simulation time 90299408 ps
CPU time 2.24 seconds
Started Apr 16 12:44:18 PM PDT 24
Finished Apr 16 12:44:27 PM PDT 24
Peak memory 203604 kb
Host smart-759e2608-bfa5-42c5-bcfc-91657207d509
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3213271969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.3213271969
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2474784568
Short name T255
Test name
Test status
Simulation time 81238016 ps
CPU time 1.02 seconds
Started Apr 16 12:44:24 PM PDT 24
Finished Apr 16 12:44:26 PM PDT 24
Peak memory 203652 kb
Host smart-cde934e1-c2c0-4252-8b32-56df443776c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2474784568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.2474784568
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2786441502
Short name T1476
Test name
Test status
Simulation time 59840727 ps
CPU time 1.7 seconds
Started Apr 16 12:44:37 PM PDT 24
Finished Apr 16 12:44:40 PM PDT 24
Peak memory 203684 kb
Host smart-0d719f15-1e07-4b27-842a-bc08639ba790
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2786441502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2786441502
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.4090536886
Short name T1444
Test name
Test status
Simulation time 499869049 ps
CPU time 4.25 seconds
Started Apr 16 12:44:26 PM PDT 24
Finished Apr 16 12:44:37 PM PDT 24
Peak memory 203636 kb
Host smart-83d3d444-294b-4a59-bb88-3adfc7a0e972
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4090536886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.4090536886
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2616907565
Short name T270
Test name
Test status
Simulation time 43098347 ps
CPU time 0.63 seconds
Started Apr 16 12:44:45 PM PDT 24
Finished Apr 16 12:44:46 PM PDT 24
Peak memory 202772 kb
Host smart-2f18fb9a-0051-4e23-bf05-bd22a7a136cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2616907565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2616907565
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1312342124
Short name T1423
Test name
Test status
Simulation time 49681941 ps
CPU time 0.65 seconds
Started Apr 16 12:44:45 PM PDT 24
Finished Apr 16 12:44:47 PM PDT 24
Peak memory 202772 kb
Host smart-ecdd5592-60f8-4a85-a2af-5ed51b2e2c80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1312342124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1312342124
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2731954258
Short name T1406
Test name
Test status
Simulation time 35633512 ps
CPU time 0.65 seconds
Started Apr 16 12:44:28 PM PDT 24
Finished Apr 16 12:44:31 PM PDT 24
Peak memory 202840 kb
Host smart-a8b7367b-9120-4e31-815b-1bd5aed22511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2731954258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2731954258
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.378719629
Short name T266
Test name
Test status
Simulation time 33602678 ps
CPU time 0.67 seconds
Started Apr 16 12:45:00 PM PDT 24
Finished Apr 16 12:45:02 PM PDT 24
Peak memory 202976 kb
Host smart-aaafa060-c6fb-4d5e-b20b-63ffb57fdc73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=378719629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.378719629
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.940414149
Short name T267
Test name
Test status
Simulation time 44003400 ps
CPU time 0.68 seconds
Started Apr 16 12:44:48 PM PDT 24
Finished Apr 16 12:44:50 PM PDT 24
Peak memory 202812 kb
Host smart-c6de0fa4-0f5a-487f-b4a0-792bbb79931c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=940414149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.940414149
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2964552779
Short name T1427
Test name
Test status
Simulation time 30722650 ps
CPU time 0.68 seconds
Started Apr 16 12:44:39 PM PDT 24
Finished Apr 16 12:44:41 PM PDT 24
Peak memory 202924 kb
Host smart-2ed36d16-a2aa-45dd-9dbe-74c5601630ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2964552779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2964552779
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2772461781
Short name T1474
Test name
Test status
Simulation time 48647703 ps
CPU time 0.66 seconds
Started Apr 16 12:44:45 PM PDT 24
Finished Apr 16 12:44:47 PM PDT 24
Peak memory 203004 kb
Host smart-380d0a06-9ef0-48a6-8f64-a09c34a06250
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2772461781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2772461781
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2695711292
Short name T1472
Test name
Test status
Simulation time 37491536 ps
CPU time 0.67 seconds
Started Apr 16 12:45:02 PM PDT 24
Finished Apr 16 12:45:04 PM PDT 24
Peak memory 202960 kb
Host smart-caf10ac4-43a1-42fd-bc3d-570d5bbc7036
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2695711292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2695711292
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3573293957
Short name T72
Test name
Test status
Simulation time 48436916 ps
CPU time 0.68 seconds
Started Apr 16 12:44:43 PM PDT 24
Finished Apr 16 12:44:45 PM PDT 24
Peak memory 202768 kb
Host smart-11a22910-d002-4ccd-a03c-ee112a710da0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3573293957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3573293957
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.980717087
Short name T1392
Test name
Test status
Simulation time 85544378 ps
CPU time 1.39 seconds
Started Apr 16 12:44:26 PM PDT 24
Finished Apr 16 12:44:29 PM PDT 24
Peak memory 211912 kb
Host smart-5a5da5a0-1ff7-457d-9616-2ccb61411783
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980717087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev
_csr_mem_rw_with_rand_reset.980717087
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.974158577
Short name T1399
Test name
Test status
Simulation time 110174966 ps
CPU time 1.06 seconds
Started Apr 16 12:44:26 PM PDT 24
Finished Apr 16 12:44:30 PM PDT 24
Peak memory 203532 kb
Host smart-140811ef-6b77-4f0f-b220-43812812c2c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=974158577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.974158577
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.747670594
Short name T71
Test name
Test status
Simulation time 24066558 ps
CPU time 0.59 seconds
Started Apr 16 12:44:17 PM PDT 24
Finished Apr 16 12:44:19 PM PDT 24
Peak memory 202696 kb
Host smart-7ca1fa4e-ed86-45ae-8fee-99769565fdc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=747670594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.747670594
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1207611644
Short name T1397
Test name
Test status
Simulation time 154725841 ps
CPU time 1.26 seconds
Started Apr 16 12:44:33 PM PDT 24
Finished Apr 16 12:44:36 PM PDT 24
Peak memory 203644 kb
Host smart-ca826f8a-8c64-4f71-a4ce-984962775e43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1207611644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1207611644
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3314444510
Short name T1478
Test name
Test status
Simulation time 210148586 ps
CPU time 2.42 seconds
Started Apr 16 12:44:25 PM PDT 24
Finished Apr 16 12:44:29 PM PDT 24
Peak memory 203708 kb
Host smart-51bcddaf-943d-41ae-9d30-f3f149104146
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3314444510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3314444510
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2261177976
Short name T1443
Test name
Test status
Simulation time 187418050 ps
CPU time 1.99 seconds
Started Apr 16 12:44:25 PM PDT 24
Finished Apr 16 12:44:29 PM PDT 24
Peak memory 211852 kb
Host smart-9975cd87-0ccf-4c0f-a76b-02529e53deff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261177976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.2261177976
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1248132216
Short name T1450
Test name
Test status
Simulation time 55152577 ps
CPU time 0.85 seconds
Started Apr 16 12:44:33 PM PDT 24
Finished Apr 16 12:44:35 PM PDT 24
Peak memory 203356 kb
Host smart-bbab0ed9-bace-4106-9cfe-3d9413a420f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1248132216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1248132216
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1393192666
Short name T261
Test name
Test status
Simulation time 77508491 ps
CPU time 0.74 seconds
Started Apr 16 12:44:24 PM PDT 24
Finished Apr 16 12:44:26 PM PDT 24
Peak memory 202928 kb
Host smart-e488e2a5-f11a-44e0-bf40-1592a62316c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1393192666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1393192666
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.616467788
Short name T68
Test name
Test status
Simulation time 76174148 ps
CPU time 1.41 seconds
Started Apr 16 12:44:17 PM PDT 24
Finished Apr 16 12:44:20 PM PDT 24
Peak memory 203556 kb
Host smart-f5b43d0a-97c4-4949-983c-65b7b1f747e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=616467788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.616467788
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3339786666
Short name T217
Test name
Test status
Simulation time 55114608 ps
CPU time 1.48 seconds
Started Apr 16 12:44:29 PM PDT 24
Finished Apr 16 12:44:33 PM PDT 24
Peak memory 203676 kb
Host smart-eb6742d6-54b1-4dca-bc70-f2484a896aaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3339786666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3339786666
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1023608759
Short name T203
Test name
Test status
Simulation time 865800807 ps
CPU time 3.15 seconds
Started Apr 16 12:44:33 PM PDT 24
Finished Apr 16 12:44:38 PM PDT 24
Peak memory 203776 kb
Host smart-83cf6e93-4520-47bb-9ce2-0cf7782da2e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1023608759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.1023608759
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1278556430
Short name T1439
Test name
Test status
Simulation time 240642582 ps
CPU time 2.03 seconds
Started Apr 16 12:44:29 PM PDT 24
Finished Apr 16 12:44:33 PM PDT 24
Peak memory 214096 kb
Host smart-ed892ae2-36a5-4677-9339-d4169f58967e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278556430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.1278556430
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.4135652683
Short name T1466
Test name
Test status
Simulation time 61940256 ps
CPU time 0.78 seconds
Started Apr 16 12:44:16 PM PDT 24
Finished Apr 16 12:44:17 PM PDT 24
Peak memory 203312 kb
Host smart-502a5e50-45a5-4017-bbe7-c0dc98d11b42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4135652683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.4135652683
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2070983652
Short name T1405
Test name
Test status
Simulation time 39267214 ps
CPU time 0.7 seconds
Started Apr 16 12:44:46 PM PDT 24
Finished Apr 16 12:44:48 PM PDT 24
Peak memory 202948 kb
Host smart-e45e148e-7c0b-48f1-80e6-3ce6bf214b2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2070983652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2070983652
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2529935770
Short name T70
Test name
Test status
Simulation time 53644562 ps
CPU time 1.08 seconds
Started Apr 16 12:44:25 PM PDT 24
Finished Apr 16 12:44:28 PM PDT 24
Peak memory 203680 kb
Host smart-2b34df02-fce6-46ed-b8b5-b6df42dd2a70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2529935770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2529935770
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3814615706
Short name T1398
Test name
Test status
Simulation time 102289291 ps
CPU time 2.99 seconds
Started Apr 16 12:44:24 PM PDT 24
Finished Apr 16 12:44:28 PM PDT 24
Peak memory 203628 kb
Host smart-b4d904db-170d-48cc-9a81-5aced32c7330
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3814615706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3814615706
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2359441182
Short name T1470
Test name
Test status
Simulation time 1054331614 ps
CPU time 3.55 seconds
Started Apr 16 12:44:26 PM PDT 24
Finished Apr 16 12:44:32 PM PDT 24
Peak memory 203660 kb
Host smart-80a2ad89-b89c-45c3-9859-8f0a116f6d46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2359441182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.2359441182
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1706155242
Short name T1414
Test name
Test status
Simulation time 90443165 ps
CPU time 1.26 seconds
Started Apr 16 12:44:27 PM PDT 24
Finished Apr 16 12:44:31 PM PDT 24
Peak memory 211896 kb
Host smart-2f22b34b-8a62-45f8-a644-2364f93059a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706155242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.1706155242
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1994580289
Short name T1453
Test name
Test status
Simulation time 44097930 ps
CPU time 0.82 seconds
Started Apr 16 12:44:18 PM PDT 24
Finished Apr 16 12:44:20 PM PDT 24
Peak memory 203320 kb
Host smart-fae050fa-a6f9-49a9-86de-4dc510c730bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1994580289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1994580289
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.938095098
Short name T274
Test name
Test status
Simulation time 35982103 ps
CPU time 0.67 seconds
Started Apr 16 12:44:42 PM PDT 24
Finished Apr 16 12:44:44 PM PDT 24
Peak memory 202844 kb
Host smart-e7b82074-d7b4-4880-abe3-866c3b3b1783
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=938095098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.938095098
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1661194693
Short name T1379
Test name
Test status
Simulation time 55207158 ps
CPU time 1.03 seconds
Started Apr 16 12:44:41 PM PDT 24
Finished Apr 16 12:44:43 PM PDT 24
Peak memory 203640 kb
Host smart-68f33604-dcea-450e-aaff-144327c6b3b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1661194693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.1661194693
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2261715324
Short name T221
Test name
Test status
Simulation time 95741254 ps
CPU time 2.85 seconds
Started Apr 16 12:44:21 PM PDT 24
Finished Apr 16 12:44:26 PM PDT 24
Peak memory 203736 kb
Host smart-c8c140ac-c238-404a-b0c2-f54b81418026
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2261715324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2261715324
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.242961612
Short name T1424
Test name
Test status
Simulation time 320209238 ps
CPU time 2.46 seconds
Started Apr 16 12:44:16 PM PDT 24
Finished Apr 16 12:44:19 PM PDT 24
Peak memory 203708 kb
Host smart-adefb809-1ecf-4927-996a-7b0f7b9f7a75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=242961612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.242961612
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3869351994
Short name T224
Test name
Test status
Simulation time 138544066 ps
CPU time 2.71 seconds
Started Apr 16 12:44:42 PM PDT 24
Finished Apr 16 12:44:47 PM PDT 24
Peak memory 211916 kb
Host smart-d35eb8b4-85e2-4dd8-825a-eeb662570e01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869351994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.3869351994
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1034095074
Short name T1390
Test name
Test status
Simulation time 59314136 ps
CPU time 1.01 seconds
Started Apr 16 12:44:31 PM PDT 24
Finished Apr 16 12:44:34 PM PDT 24
Peak memory 203628 kb
Host smart-62fe2699-7b25-472a-bdc3-c06189f8aa72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1034095074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1034095074
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3414158763
Short name T1448
Test name
Test status
Simulation time 44112271 ps
CPU time 0.67 seconds
Started Apr 16 12:44:29 PM PDT 24
Finished Apr 16 12:44:32 PM PDT 24
Peak memory 202864 kb
Host smart-5477aabb-851b-4861-88cc-2b5622b7c415
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3414158763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.3414158763
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.912064778
Short name T1386
Test name
Test status
Simulation time 59036904 ps
CPU time 0.96 seconds
Started Apr 16 12:44:17 PM PDT 24
Finished Apr 16 12:44:20 PM PDT 24
Peak memory 203584 kb
Host smart-dfd8aae6-0dcd-4a8b-b5e5-9ada547fc8cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=912064778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.912064778
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2655643525
Short name T1455
Test name
Test status
Simulation time 193197998 ps
CPU time 2.49 seconds
Started Apr 16 12:45:00 PM PDT 24
Finished Apr 16 12:45:04 PM PDT 24
Peak memory 203704 kb
Host smart-08ae2475-acfe-48ec-931b-1a2384c39d2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2655643525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2655643525
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.2262795619
Short name T753
Test name
Test status
Simulation time 8493072402 ps
CPU time 8.34 seconds
Started Apr 16 01:01:07 PM PDT 24
Finished Apr 16 01:01:16 PM PDT 24
Peak memory 204048 kb
Host smart-bbe8246f-6ee7-4a34-9d4d-957a6e0a4d21
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2262795619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.2262795619
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.2238894434
Short name T1193
Test name
Test status
Simulation time 8381123156 ps
CPU time 8.24 seconds
Started Apr 16 01:01:10 PM PDT 24
Finished Apr 16 01:01:19 PM PDT 24
Peak memory 203968 kb
Host smart-d36b1bad-f7ef-463d-b038-0a7c1d527b15
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2238894434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.2238894434
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.3743504161
Short name T537
Test name
Test status
Simulation time 8443246364 ps
CPU time 9.22 seconds
Started Apr 16 01:01:05 PM PDT 24
Finished Apr 16 01:01:15 PM PDT 24
Peak memory 203996 kb
Host smart-d89ffa74-5d71-4551-802a-ab78a01b3eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37435
04161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.3743504161
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.4172779195
Short name T1141
Test name
Test status
Simulation time 8380003422 ps
CPU time 7.44 seconds
Started Apr 16 01:00:58 PM PDT 24
Finished Apr 16 01:01:06 PM PDT 24
Peak memory 203988 kb
Host smart-ed2b97fb-1f97-41d6-81b7-4c7f24507afa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41727
79195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.4172779195
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_enable.449572119
Short name T646
Test name
Test status
Simulation time 8378895539 ps
CPU time 7.45 seconds
Started Apr 16 01:00:58 PM PDT 24
Finished Apr 16 01:01:06 PM PDT 24
Peak memory 204040 kb
Host smart-8187795e-dc55-4ff0-8fa2-d3eb15f5a886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44957
2119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.449572119
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.1399520185
Short name T1223
Test name
Test status
Simulation time 299409397 ps
CPU time 2.51 seconds
Started Apr 16 01:00:59 PM PDT 24
Finished Apr 16 01:01:02 PM PDT 24
Peak memory 204040 kb
Host smart-b096e236-7b21-476d-9084-0c1cba9c5812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13995
20185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.1399520185
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.1956165129
Short name T651
Test name
Test status
Simulation time 8400984828 ps
CPU time 9.46 seconds
Started Apr 16 01:01:00 PM PDT 24
Finished Apr 16 01:01:11 PM PDT 24
Peak memory 204044 kb
Host smart-e507b312-6f16-47f3-b38b-993f2c54d99f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19561
65129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.1956165129
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.1613640766
Short name T922
Test name
Test status
Simulation time 8417468527 ps
CPU time 9.55 seconds
Started Apr 16 01:00:59 PM PDT 24
Finished Apr 16 01:01:09 PM PDT 24
Peak memory 204024 kb
Host smart-44b4a42c-4c22-4429-a4b5-0acefc159a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16136
40766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.1613640766
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.836873518
Short name T719
Test name
Test status
Simulation time 8474264950 ps
CPU time 8.3 seconds
Started Apr 16 01:00:59 PM PDT 24
Finished Apr 16 01:01:08 PM PDT 24
Peak memory 204036 kb
Host smart-f9975f37-5b4d-46ff-ad8c-815f1e18b34c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83687
3518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.836873518
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.336521559
Short name T1014
Test name
Test status
Simulation time 8373669674 ps
CPU time 10.72 seconds
Started Apr 16 01:00:57 PM PDT 24
Finished Apr 16 01:01:08 PM PDT 24
Peak memory 204040 kb
Host smart-0d36a6cf-2e90-4784-9ac4-8929da50313b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33652
1559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.336521559
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3046269039
Short name T402
Test name
Test status
Simulation time 8414095976 ps
CPU time 7.76 seconds
Started Apr 16 01:01:02 PM PDT 24
Finished Apr 16 01:01:10 PM PDT 24
Peak memory 204020 kb
Host smart-930e2c87-fd03-456d-b335-5954c6ffd50e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30462
69039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3046269039
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.302664340
Short name T1109
Test name
Test status
Simulation time 8397942888 ps
CPU time 7.54 seconds
Started Apr 16 01:01:03 PM PDT 24
Finished Apr 16 01:01:11 PM PDT 24
Peak memory 204012 kb
Host smart-305e0ea8-f8e2-4c70-8056-8951d6aa445e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30266
4340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.302664340
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.940238482
Short name T552
Test name
Test status
Simulation time 8370841394 ps
CPU time 9.29 seconds
Started Apr 16 01:01:03 PM PDT 24
Finished Apr 16 01:01:13 PM PDT 24
Peak memory 204016 kb
Host smart-ba6eeb49-033a-493a-bbf4-1f21f69acb34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94023
8482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.940238482
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.938799359
Short name T1369
Test name
Test status
Simulation time 57217196 ps
CPU time 0.66 seconds
Started Apr 16 01:01:05 PM PDT 24
Finished Apr 16 01:01:06 PM PDT 24
Peak memory 203808 kb
Host smart-c8d8506a-8fd4-441c-88b4-159283d32fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93879
9359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.938799359
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.3939542450
Short name T1245
Test name
Test status
Simulation time 25091206629 ps
CPU time 47.35 seconds
Started Apr 16 01:01:07 PM PDT 24
Finished Apr 16 01:01:55 PM PDT 24
Peak memory 204276 kb
Host smart-1190a3e0-e9a2-4b53-b1dc-fabc0e60ae0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39395
42450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.3939542450
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.3967976878
Short name T1321
Test name
Test status
Simulation time 8376815300 ps
CPU time 8.22 seconds
Started Apr 16 01:01:01 PM PDT 24
Finished Apr 16 01:01:10 PM PDT 24
Peak memory 203908 kb
Host smart-61401a96-bb3c-4e52-b397-9bc92f6ba7bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39679
76878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.3967976878
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.1723493550
Short name T76
Test name
Test status
Simulation time 625413639 ps
CPU time 1.46 seconds
Started Apr 16 01:01:09 PM PDT 24
Finished Apr 16 01:01:11 PM PDT 24
Peak memory 220268 kb
Host smart-934551ac-468f-4f37-8e64-8ee39fcc58be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1723493550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1723493550
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.2852422783
Short name T156
Test name
Test status
Simulation time 8372741367 ps
CPU time 7.8 seconds
Started Apr 16 01:01:03 PM PDT 24
Finished Apr 16 01:01:12 PM PDT 24
Peak memory 203960 kb
Host smart-de6544b0-9d5d-40fa-b355-6ae7877411c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28524
22783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2852422783
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.667499438
Short name T343
Test name
Test status
Simulation time 8395106592 ps
CPU time 7.39 seconds
Started Apr 16 01:01:04 PM PDT 24
Finished Apr 16 01:01:12 PM PDT 24
Peak memory 203952 kb
Host smart-7a52d893-4d5f-408d-a205-f30671091947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66749
9438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.667499438
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.3097553229
Short name T357
Test name
Test status
Simulation time 8407377166 ps
CPU time 10.24 seconds
Started Apr 16 01:01:05 PM PDT 24
Finished Apr 16 01:01:16 PM PDT 24
Peak memory 204008 kb
Host smart-92f96e22-aa25-4bb9-9781-2f74a18f0318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30975
53229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3097553229
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.2406857224
Short name T1075
Test name
Test status
Simulation time 8475837597 ps
CPU time 8.72 seconds
Started Apr 16 01:01:18 PM PDT 24
Finished Apr 16 01:01:27 PM PDT 24
Peak memory 203988 kb
Host smart-ccbca186-8866-4a3f-ac1f-2b6fae60b86e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2406857224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.2406857224
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.2778431793
Short name T895
Test name
Test status
Simulation time 8387144130 ps
CPU time 8.77 seconds
Started Apr 16 01:01:14 PM PDT 24
Finished Apr 16 01:01:24 PM PDT 24
Peak memory 203972 kb
Host smart-d64ca76e-edb2-4ba6-9860-38f184446f4c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2778431793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.2778431793
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.3189982911
Short name T974
Test name
Test status
Simulation time 8434080154 ps
CPU time 8 seconds
Started Apr 16 01:01:17 PM PDT 24
Finished Apr 16 01:01:25 PM PDT 24
Peak memory 203980 kb
Host smart-b4ab149b-afdc-49b5-a078-7c3bbf640c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31899
82911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.3189982911
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.250693137
Short name T586
Test name
Test status
Simulation time 8377837489 ps
CPU time 7.71 seconds
Started Apr 16 01:01:09 PM PDT 24
Finished Apr 16 01:01:18 PM PDT 24
Peak memory 204028 kb
Host smart-f6e7d276-e879-42c6-805a-22d3a75eef91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25069
3137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.250693137
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_enable.771105886
Short name T1104
Test name
Test status
Simulation time 8397911950 ps
CPU time 8.11 seconds
Started Apr 16 01:01:09 PM PDT 24
Finished Apr 16 01:01:18 PM PDT 24
Peak memory 204016 kb
Host smart-1c7f4440-abbe-46b7-bb6b-1e57a9b8b55b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77110
5886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.771105886
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.643623979
Short name T1195
Test name
Test status
Simulation time 116482826 ps
CPU time 1.65 seconds
Started Apr 16 01:01:09 PM PDT 24
Finished Apr 16 01:01:11 PM PDT 24
Peak memory 204096 kb
Host smart-fb828a0d-2323-44cb-8715-f9b2b1805612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64362
3979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.643623979
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.2104762334
Short name T133
Test name
Test status
Simulation time 8437995590 ps
CPU time 8.07 seconds
Started Apr 16 01:01:14 PM PDT 24
Finished Apr 16 01:01:22 PM PDT 24
Peak memory 204016 kb
Host smart-59d256e8-573e-43e5-93ab-7133901b092f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21047
62334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2104762334
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.1325976174
Short name T183
Test name
Test status
Simulation time 8375417773 ps
CPU time 7.49 seconds
Started Apr 16 01:01:18 PM PDT 24
Finished Apr 16 01:01:26 PM PDT 24
Peak memory 203980 kb
Host smart-f5f6435f-0eb9-4bde-9c33-d74d01e0903a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13259
76174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.1325976174
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.2932786059
Short name T904
Test name
Test status
Simulation time 8498938989 ps
CPU time 9.08 seconds
Started Apr 16 01:01:10 PM PDT 24
Finished Apr 16 01:01:20 PM PDT 24
Peak memory 204016 kb
Host smart-c5f8c958-00f1-49a5-b7ea-075bc36d0897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29327
86059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.2932786059
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.4047618769
Short name T471
Test name
Test status
Simulation time 8426367122 ps
CPU time 7.79 seconds
Started Apr 16 01:01:09 PM PDT 24
Finished Apr 16 01:01:17 PM PDT 24
Peak memory 203968 kb
Host smart-c0532499-ab94-4edb-a5e0-bd5e273612c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40476
18769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.4047618769
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.3683981914
Short name T984
Test name
Test status
Simulation time 8391432153 ps
CPU time 7.61 seconds
Started Apr 16 01:01:08 PM PDT 24
Finished Apr 16 01:01:17 PM PDT 24
Peak memory 203992 kb
Host smart-aba41e72-e584-45c3-9d6a-045ab90e2353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36839
81914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.3683981914
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.2897503055
Short name T1058
Test name
Test status
Simulation time 8398879117 ps
CPU time 8.91 seconds
Started Apr 16 01:01:08 PM PDT 24
Finished Apr 16 01:01:18 PM PDT 24
Peak memory 203972 kb
Host smart-4cc5b007-cdbe-4f8d-a075-5fad343edcf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28975
03055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2897503055
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.1974710848
Short name T793
Test name
Test status
Simulation time 8389781068 ps
CPU time 7.66 seconds
Started Apr 16 01:01:07 PM PDT 24
Finished Apr 16 01:01:15 PM PDT 24
Peak memory 203948 kb
Host smart-5fa1780b-6d55-4be1-ace7-a8a3fcc23b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19747
10848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.1974710848
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.626035601
Short name T794
Test name
Test status
Simulation time 53417603 ps
CPU time 0.64 seconds
Started Apr 16 01:01:15 PM PDT 24
Finished Apr 16 01:01:16 PM PDT 24
Peak memory 203888 kb
Host smart-bab1f583-a14b-4868-bb1f-7632fa772b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62603
5601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.626035601
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.3570996787
Short name T1337
Test name
Test status
Simulation time 25907477303 ps
CPU time 50.17 seconds
Started Apr 16 01:01:15 PM PDT 24
Finished Apr 16 01:02:06 PM PDT 24
Peak memory 204332 kb
Host smart-4f155f46-f5ac-4c5b-8094-ac09046ff1b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35709
96787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.3570996787
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.466207194
Short name T739
Test name
Test status
Simulation time 8423913923 ps
CPU time 9.29 seconds
Started Apr 16 01:01:16 PM PDT 24
Finished Apr 16 01:01:26 PM PDT 24
Peak memory 204020 kb
Host smart-c45d4cc4-f511-49c2-8d4e-8e400cdcdf91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46620
7194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.466207194
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.1638395667
Short name T533
Test name
Test status
Simulation time 8404013705 ps
CPU time 8.45 seconds
Started Apr 16 01:01:15 PM PDT 24
Finished Apr 16 01:01:24 PM PDT 24
Peak memory 204256 kb
Host smart-003e28c6-27c5-4b68-8c99-eaa3b127cfb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16383
95667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.1638395667
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.3118383205
Short name T956
Test name
Test status
Simulation time 8398541688 ps
CPU time 9.88 seconds
Started Apr 16 01:01:16 PM PDT 24
Finished Apr 16 01:01:27 PM PDT 24
Peak memory 204036 kb
Host smart-0e3ba39e-1143-4f41-96b2-5ad79b0cb70f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31183
83205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.3118383205
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.2708889805
Short name T173
Test name
Test status
Simulation time 8378205491 ps
CPU time 7.98 seconds
Started Apr 16 01:01:15 PM PDT 24
Finished Apr 16 01:01:24 PM PDT 24
Peak memory 204016 kb
Host smart-ee0a44d4-1a39-468a-a3d9-8da3ee27c9ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27088
89805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.2708889805
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.4024825462
Short name T1090
Test name
Test status
Simulation time 8364624595 ps
CPU time 8.71 seconds
Started Apr 16 01:01:13 PM PDT 24
Finished Apr 16 01:01:22 PM PDT 24
Peak memory 203908 kb
Host smart-f4949ba9-83d9-4c3f-ae73-2ddadafd7a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40248
25462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.4024825462
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.393768940
Short name T1023
Test name
Test status
Simulation time 8449364500 ps
CPU time 9.16 seconds
Started Apr 16 01:01:10 PM PDT 24
Finished Apr 16 01:01:20 PM PDT 24
Peak memory 204028 kb
Host smart-e90e7b11-e3a0-4927-97fb-3b95f57c3dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39376
8940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.393768940
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1486490322
Short name T804
Test name
Test status
Simulation time 8492456386 ps
CPU time 9.14 seconds
Started Apr 16 01:01:35 PM PDT 24
Finished Apr 16 01:01:45 PM PDT 24
Peak memory 204000 kb
Host smart-1b5f1dd8-cdca-4b5c-9b5c-70a0bb669d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14864
90322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1486490322
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.593262941
Short name T321
Test name
Test status
Simulation time 8391617529 ps
CPU time 8.69 seconds
Started Apr 16 01:01:14 PM PDT 24
Finished Apr 16 01:01:23 PM PDT 24
Peak memory 204036 kb
Host smart-3d852671-0c53-460f-950c-5845f372ad77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59326
2941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.593262941
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.246700111
Short name T872
Test name
Test status
Simulation time 8510684461 ps
CPU time 7.65 seconds
Started Apr 16 01:02:25 PM PDT 24
Finished Apr 16 01:02:33 PM PDT 24
Peak memory 204020 kb
Host smart-bbdcb9a2-0c39-4e6a-9c29-4758911ecb8f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=246700111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.246700111
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.647578044
Short name T907
Test name
Test status
Simulation time 8375574849 ps
CPU time 8.32 seconds
Started Apr 16 01:02:23 PM PDT 24
Finished Apr 16 01:02:32 PM PDT 24
Peak memory 203976 kb
Host smart-6e8f6ee5-0371-4a7b-a886-118385f54b24
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=647578044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.647578044
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.3608093479
Short name T1240
Test name
Test status
Simulation time 8410346467 ps
CPU time 8.77 seconds
Started Apr 16 01:02:23 PM PDT 24
Finished Apr 16 01:02:33 PM PDT 24
Peak memory 203904 kb
Host smart-3c749368-f6d5-43a5-96b8-43df1b64ddb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36080
93479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.3608093479
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.4098432189
Short name T738
Test name
Test status
Simulation time 8381494291 ps
CPU time 7.81 seconds
Started Apr 16 01:02:12 PM PDT 24
Finished Apr 16 01:02:21 PM PDT 24
Peak memory 203928 kb
Host smart-60b66ff7-19c3-45d8-9b71-adc691eb594c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40984
32189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.4098432189
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_enable.1894030656
Short name T772
Test name
Test status
Simulation time 8405794953 ps
CPU time 10.39 seconds
Started Apr 16 01:02:10 PM PDT 24
Finished Apr 16 01:02:22 PM PDT 24
Peak memory 203980 kb
Host smart-5cb0a4e2-7a37-4029-9ee2-0395cc2ee5ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18940
30656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.1894030656
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.3182031724
Short name T627
Test name
Test status
Simulation time 104944101 ps
CPU time 1.18 seconds
Started Apr 16 01:02:07 PM PDT 24
Finished Apr 16 01:02:09 PM PDT 24
Peak memory 204024 kb
Host smart-b9d11f48-a4c8-4cf7-addf-b47e4a01e341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31820
31724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.3182031724
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.1520833164
Short name T179
Test name
Test status
Simulation time 8369445388 ps
CPU time 10.05 seconds
Started Apr 16 01:02:25 PM PDT 24
Finished Apr 16 01:02:37 PM PDT 24
Peak memory 204012 kb
Host smart-82d0f9b2-3cde-4727-bf00-f8ffca30cb16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15208
33164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.1520833164
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.1674581053
Short name T649
Test name
Test status
Simulation time 8436479904 ps
CPU time 8.79 seconds
Started Apr 16 01:02:11 PM PDT 24
Finished Apr 16 01:02:21 PM PDT 24
Peak memory 204048 kb
Host smart-e74aa8d6-01ca-4f78-8b8c-03f5bd1b5be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16745
81053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.1674581053
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.2726011030
Short name T836
Test name
Test status
Simulation time 8463123178 ps
CPU time 10.38 seconds
Started Apr 16 01:02:10 PM PDT 24
Finished Apr 16 01:02:22 PM PDT 24
Peak memory 204032 kb
Host smart-c129bd66-672a-45c3-8495-d661deb564d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27260
11030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2726011030
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.1687918602
Short name T894
Test name
Test status
Simulation time 8372222571 ps
CPU time 8.48 seconds
Started Apr 16 01:02:09 PM PDT 24
Finished Apr 16 01:02:19 PM PDT 24
Peak memory 203988 kb
Host smart-886836ab-7240-472b-b3ef-86a4d655d6c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16879
18602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.1687918602
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.4267901715
Short name T717
Test name
Test status
Simulation time 8407218197 ps
CPU time 8.28 seconds
Started Apr 16 01:02:11 PM PDT 24
Finished Apr 16 01:02:21 PM PDT 24
Peak memory 204048 kb
Host smart-448c33f4-14e7-4f76-8cd2-57a7c2274166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42679
01715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.4267901715
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1717767707
Short name T983
Test name
Test status
Simulation time 8394735990 ps
CPU time 7.71 seconds
Started Apr 16 01:02:11 PM PDT 24
Finished Apr 16 01:02:20 PM PDT 24
Peak memory 204032 kb
Host smart-dd43160d-2114-46aa-b63a-7847436cd106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17177
67707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1717767707
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.3806332910
Short name T662
Test name
Test status
Simulation time 8423713733 ps
CPU time 8.27 seconds
Started Apr 16 01:02:14 PM PDT 24
Finished Apr 16 01:02:23 PM PDT 24
Peak memory 203968 kb
Host smart-d845f4fa-f5fa-41fb-bc27-43a07d5ca89e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38063
32910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.3806332910
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.1679518759
Short name T630
Test name
Test status
Simulation time 8365671586 ps
CPU time 8.66 seconds
Started Apr 16 01:02:15 PM PDT 24
Finished Apr 16 01:02:25 PM PDT 24
Peak memory 204008 kb
Host smart-95f711e2-0bd0-4268-9978-982ba11a4567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16795
18759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.1679518759
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.3251775937
Short name T1260
Test name
Test status
Simulation time 108461680 ps
CPU time 0.72 seconds
Started Apr 16 01:02:16 PM PDT 24
Finished Apr 16 01:02:18 PM PDT 24
Peak memory 203872 kb
Host smart-b16058c4-05d9-4e4f-bfb8-9e32cbd67477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32517
75937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.3251775937
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.2734506558
Short name T94
Test name
Test status
Simulation time 24141035621 ps
CPU time 45.09 seconds
Started Apr 16 01:02:11 PM PDT 24
Finished Apr 16 01:02:57 PM PDT 24
Peak memory 204308 kb
Host smart-433d39d2-e917-4dc9-b197-bd13fba60d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27345
06558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.2734506558
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.2562095343
Short name T464
Test name
Test status
Simulation time 8411794064 ps
CPU time 7.7 seconds
Started Apr 16 01:02:08 PM PDT 24
Finished Apr 16 01:02:16 PM PDT 24
Peak memory 204008 kb
Host smart-2dfccee0-08b3-4f07-9c74-4f74d94d40e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25620
95343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.2562095343
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.1047088761
Short name T56
Test name
Test status
Simulation time 8416811936 ps
CPU time 9.18 seconds
Started Apr 16 01:02:14 PM PDT 24
Finished Apr 16 01:02:24 PM PDT 24
Peak memory 204016 kb
Host smart-23b27f49-45db-4281-87c7-ca1e6fe216bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10470
88761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.1047088761
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.3443607095
Short name T964
Test name
Test status
Simulation time 8409760625 ps
CPU time 7.76 seconds
Started Apr 16 01:02:14 PM PDT 24
Finished Apr 16 01:02:23 PM PDT 24
Peak memory 203928 kb
Host smart-ed0e57c7-b8ef-4b23-8acf-933498e00d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34436
07095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.3443607095
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.3988829368
Short name T1056
Test name
Test status
Simulation time 8371939942 ps
CPU time 8.08 seconds
Started Apr 16 01:02:12 PM PDT 24
Finished Apr 16 01:02:21 PM PDT 24
Peak memory 204016 kb
Host smart-16be52d4-9156-4f8f-9090-80ef22f9f061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39888
29368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.3988829368
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.3300193102
Short name T1172
Test name
Test status
Simulation time 8365872162 ps
CPU time 8.2 seconds
Started Apr 16 01:02:13 PM PDT 24
Finished Apr 16 01:02:22 PM PDT 24
Peak memory 204044 kb
Host smart-19600647-4eb7-40dd-aef7-866e4039eaf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33001
93102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.3300193102
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.2954041463
Short name T1065
Test name
Test status
Simulation time 8406243757 ps
CPU time 8.02 seconds
Started Apr 16 01:02:07 PM PDT 24
Finished Apr 16 01:02:16 PM PDT 24
Peak memory 204028 kb
Host smart-0f2bf11f-f286-4e38-8d38-eb22ebc8e35e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29540
41463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2954041463
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.3400049651
Short name T443
Test name
Test status
Simulation time 8402257235 ps
CPU time 9.99 seconds
Started Apr 16 01:02:14 PM PDT 24
Finished Apr 16 01:02:25 PM PDT 24
Peak memory 204048 kb
Host smart-876007d7-c7bc-4dcc-9785-9b6759502a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34000
49651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.3400049651
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.2135749291
Short name T1020
Test name
Test status
Simulation time 8396075279 ps
CPU time 7.81 seconds
Started Apr 16 01:02:15 PM PDT 24
Finished Apr 16 01:02:23 PM PDT 24
Peak memory 204020 kb
Host smart-d103dd2d-8a5f-4af2-b4f9-c1f3518151ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21357
49291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.2135749291
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.897704978
Short name T1173
Test name
Test status
Simulation time 8485580663 ps
CPU time 8.83 seconds
Started Apr 16 01:02:29 PM PDT 24
Finished Apr 16 01:02:39 PM PDT 24
Peak memory 203992 kb
Host smart-5c6856c6-9c5d-49c9-8a12-ebce39811d46
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=897704978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.897704978
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.413959696
Short name T1250
Test name
Test status
Simulation time 8381811857 ps
CPU time 9.28 seconds
Started Apr 16 01:02:30 PM PDT 24
Finished Apr 16 01:02:40 PM PDT 24
Peak memory 204024 kb
Host smart-610ed3cb-6328-4d0d-b0e6-e56fb410de55
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=413959696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.413959696
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.261178238
Short name T998
Test name
Test status
Simulation time 8426318867 ps
CPU time 7.91 seconds
Started Apr 16 01:02:27 PM PDT 24
Finished Apr 16 01:02:36 PM PDT 24
Peak memory 203988 kb
Host smart-5459f78f-a31e-487a-8266-e78de5517649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26117
8238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.261178238
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.403844700
Short name T755
Test name
Test status
Simulation time 8403633318 ps
CPU time 8.4 seconds
Started Apr 16 01:02:22 PM PDT 24
Finished Apr 16 01:02:31 PM PDT 24
Peak memory 203968 kb
Host smart-5a51f947-a4f8-499a-bb47-6621df57e122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40384
4700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.403844700
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_enable.1053209426
Short name T96
Test name
Test status
Simulation time 8381043842 ps
CPU time 10.02 seconds
Started Apr 16 01:02:22 PM PDT 24
Finished Apr 16 01:02:32 PM PDT 24
Peak memory 204032 kb
Host smart-668d7abe-5800-47cb-b78a-809c7f3107c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10532
09426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.1053209426
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.169093489
Short name T404
Test name
Test status
Simulation time 83421643 ps
CPU time 1.48 seconds
Started Apr 16 01:02:23 PM PDT 24
Finished Apr 16 01:02:25 PM PDT 24
Peak memory 204096 kb
Host smart-c5e501da-db1d-48e4-9598-a0abeb057eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16909
3489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.169093489
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.537896450
Short name T355
Test name
Test status
Simulation time 8426255402 ps
CPU time 7.71 seconds
Started Apr 16 01:02:27 PM PDT 24
Finished Apr 16 01:02:35 PM PDT 24
Peak memory 203948 kb
Host smart-caf57c9a-22a9-4349-962d-b25eb3c8bb53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53789
6450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.537896450
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.1457038927
Short name T1326
Test name
Test status
Simulation time 8418947864 ps
CPU time 7.76 seconds
Started Apr 16 01:02:23 PM PDT 24
Finished Apr 16 01:02:31 PM PDT 24
Peak memory 204004 kb
Host smart-a347f0e2-0d3d-4b1c-8a7d-35b4cd9ee83f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14570
38927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.1457038927
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.3697323390
Short name T1192
Test name
Test status
Simulation time 8417862304 ps
CPU time 8 seconds
Started Apr 16 01:02:25 PM PDT 24
Finished Apr 16 01:02:33 PM PDT 24
Peak memory 203944 kb
Host smart-fab54dbb-bcf2-44ba-a6e3-cc7d62d57a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36973
23390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.3697323390
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.4108922228
Short name T281
Test name
Test status
Simulation time 8369503163 ps
CPU time 9.97 seconds
Started Apr 16 01:02:25 PM PDT 24
Finished Apr 16 01:02:36 PM PDT 24
Peak memory 204048 kb
Host smart-adc26bc5-7201-4931-9464-419b6b6e5d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41089
22228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.4108922228
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.3121008673
Short name T1346
Test name
Test status
Simulation time 8430316660 ps
CPU time 7.76 seconds
Started Apr 16 01:02:22 PM PDT 24
Finished Apr 16 01:02:30 PM PDT 24
Peak memory 204008 kb
Host smart-d41a2c4b-b2cb-4905-b0ed-b70d38a8c28c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31210
08673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.3121008673
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.3686432059
Short name T543
Test name
Test status
Simulation time 8378467552 ps
CPU time 7.89 seconds
Started Apr 16 01:02:25 PM PDT 24
Finished Apr 16 01:02:34 PM PDT 24
Peak memory 204048 kb
Host smart-75a6a34d-75dc-44fb-a702-df58daf3d3d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36864
32059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.3686432059
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.2267366986
Short name T14
Test name
Test status
Simulation time 8409070545 ps
CPU time 8.92 seconds
Started Apr 16 01:02:30 PM PDT 24
Finished Apr 16 01:02:41 PM PDT 24
Peak memory 204004 kb
Host smart-fe61fdee-51ce-4c8a-b0c4-8a5bf6603726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22673
66986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.2267366986
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.1455251779
Short name T944
Test name
Test status
Simulation time 8416378809 ps
CPU time 9.46 seconds
Started Apr 16 01:02:26 PM PDT 24
Finished Apr 16 01:02:36 PM PDT 24
Peak memory 204012 kb
Host smart-8b4a3770-9e0c-4d53-b6fd-d260847d73ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14552
51779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.1455251779
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.3808224362
Short name T924
Test name
Test status
Simulation time 8364962900 ps
CPU time 7.63 seconds
Started Apr 16 01:02:23 PM PDT 24
Finished Apr 16 01:02:31 PM PDT 24
Peak memory 204016 kb
Host smart-c7b85a9c-f2f3-4107-80d4-47485803f686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38082
24362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.3808224362
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.4054668853
Short name T1057
Test name
Test status
Simulation time 32289972 ps
CPU time 0.66 seconds
Started Apr 16 01:02:25 PM PDT 24
Finished Apr 16 01:02:27 PM PDT 24
Peak memory 203920 kb
Host smart-e3447ef9-babd-4581-87a3-8010e830f3d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40546
68853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.4054668853
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.2465251523
Short name T1194
Test name
Test status
Simulation time 18487254342 ps
CPU time 35.54 seconds
Started Apr 16 01:02:23 PM PDT 24
Finished Apr 16 01:02:59 PM PDT 24
Peak memory 204292 kb
Host smart-216ba688-f6cd-44d3-b859-659f1a531ad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24652
51523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.2465251523
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.2372499515
Short name T401
Test name
Test status
Simulation time 8422246757 ps
CPU time 8.16 seconds
Started Apr 16 01:02:30 PM PDT 24
Finished Apr 16 01:02:40 PM PDT 24
Peak memory 204004 kb
Host smart-de2ceca6-77dd-48b5-96e3-590e04ce62a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23724
99515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.2372499515
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.1946490516
Short name T723
Test name
Test status
Simulation time 8468562308 ps
CPU time 8.64 seconds
Started Apr 16 01:02:28 PM PDT 24
Finished Apr 16 01:02:37 PM PDT 24
Peak memory 203928 kb
Host smart-480dfb7a-9269-4ed8-bd44-05c6f3d72c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19464
90516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.1946490516
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.4209838455
Short name T1079
Test name
Test status
Simulation time 8385523489 ps
CPU time 9.53 seconds
Started Apr 16 01:02:28 PM PDT 24
Finished Apr 16 01:02:38 PM PDT 24
Peak memory 203980 kb
Host smart-8170a9b3-fb0d-44ee-9e8e-29076268f774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42098
38455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.4209838455
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2454809401
Short name T1170
Test name
Test status
Simulation time 8386860691 ps
CPU time 9.84 seconds
Started Apr 16 01:02:28 PM PDT 24
Finished Apr 16 01:02:39 PM PDT 24
Peak memory 204048 kb
Host smart-09a30f22-a989-4892-acff-a1bc095e1de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24548
09401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2454809401
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.3962924754
Short name T1041
Test name
Test status
Simulation time 8487408692 ps
CPU time 8.53 seconds
Started Apr 16 01:02:24 PM PDT 24
Finished Apr 16 01:02:33 PM PDT 24
Peak memory 204012 kb
Host smart-2aeab229-98eb-4a1f-b440-55acfea1e917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39629
24754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.3962924754
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.2206979779
Short name T985
Test name
Test status
Simulation time 8399060390 ps
CPU time 8.07 seconds
Started Apr 16 01:02:22 PM PDT 24
Finished Apr 16 01:02:31 PM PDT 24
Peak memory 203968 kb
Host smart-0a405f43-ce5d-4299-bc60-6fd0783f3989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22069
79779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.2206979779
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.3360996436
Short name T685
Test name
Test status
Simulation time 8372904490 ps
CPU time 8.33 seconds
Started Apr 16 01:02:25 PM PDT 24
Finished Apr 16 01:02:34 PM PDT 24
Peak memory 204016 kb
Host smart-4696ca21-a776-4d79-b1e0-ff261b0b9b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33609
96436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.3360996436
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.584221650
Short name T1116
Test name
Test status
Simulation time 8463210835 ps
CPU time 7.86 seconds
Started Apr 16 01:02:30 PM PDT 24
Finished Apr 16 01:02:38 PM PDT 24
Peak memory 204028 kb
Host smart-932779ac-69ce-4231-8167-56147dc68274
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=584221650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.584221650
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/12.min_length_in_transaction.3413471250
Short name T578
Test name
Test status
Simulation time 8437089216 ps
CPU time 7.95 seconds
Started Apr 16 01:02:28 PM PDT 24
Finished Apr 16 01:02:37 PM PDT 24
Peak memory 204040 kb
Host smart-5fc2faaf-e5c5-40ff-b2d6-a9aaf3eed962
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3413471250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.3413471250
Directory /workspace/12.min_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.3509519340
Short name T1303
Test name
Test status
Simulation time 8420425896 ps
CPU time 9.02 seconds
Started Apr 16 01:02:30 PM PDT 24
Finished Apr 16 01:02:40 PM PDT 24
Peak memory 204036 kb
Host smart-e819ecb3-b019-4b6b-af57-3f17c15b7158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35095
19340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.3509519340
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2672337397
Short name T1126
Test name
Test status
Simulation time 8379040004 ps
CPU time 7.45 seconds
Started Apr 16 01:02:24 PM PDT 24
Finished Apr 16 01:02:33 PM PDT 24
Peak memory 203940 kb
Host smart-c170c5d1-3610-4ce3-93a6-b83416ca7d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26723
37397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2672337397
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_enable.4168746595
Short name T599
Test name
Test status
Simulation time 8425545094 ps
CPU time 8.78 seconds
Started Apr 16 01:02:22 PM PDT 24
Finished Apr 16 01:02:32 PM PDT 24
Peak memory 204032 kb
Host smart-d843c032-efde-4bbc-9c44-c9ab3d13235f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41687
46595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.4168746595
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.2496974754
Short name T758
Test name
Test status
Simulation time 225846351 ps
CPU time 1.86 seconds
Started Apr 16 01:02:24 PM PDT 24
Finished Apr 16 01:02:26 PM PDT 24
Peak memory 204112 kb
Host smart-0aba6ad3-ccc7-4ad7-bddc-17d2844c8825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24969
74754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2496974754
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.2213970733
Short name T180
Test name
Test status
Simulation time 8400981303 ps
CPU time 7.98 seconds
Started Apr 16 01:02:28 PM PDT 24
Finished Apr 16 01:02:37 PM PDT 24
Peak memory 203936 kb
Host smart-834d32ac-aac4-4bd1-ae41-883fab1e7858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22139
70733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.2213970733
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.2043306904
Short name T1234
Test name
Test status
Simulation time 8416774332 ps
CPU time 8.14 seconds
Started Apr 16 01:02:26 PM PDT 24
Finished Apr 16 01:02:35 PM PDT 24
Peak memory 203984 kb
Host smart-90ecb4c9-66f0-4e86-beab-bc61ef15ab92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20433
06904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.2043306904
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.893248481
Short name T830
Test name
Test status
Simulation time 8414902199 ps
CPU time 8.46 seconds
Started Apr 16 01:02:23 PM PDT 24
Finished Apr 16 01:02:32 PM PDT 24
Peak memory 204048 kb
Host smart-9ab78494-13e1-4215-b2a5-a9078fb24b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89324
8481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.893248481
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.1965497225
Short name T509
Test name
Test status
Simulation time 8382785944 ps
CPU time 7.93 seconds
Started Apr 16 01:02:30 PM PDT 24
Finished Apr 16 01:02:39 PM PDT 24
Peak memory 204004 kb
Host smart-d9bc5cb4-0c0f-4730-99f0-d38bb05a3a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19654
97225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.1965497225
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.2524630633
Short name T696
Test name
Test status
Simulation time 8387377595 ps
CPU time 7.86 seconds
Started Apr 16 01:02:29 PM PDT 24
Finished Apr 16 01:02:38 PM PDT 24
Peak memory 203928 kb
Host smart-df34cd88-9063-44a5-8508-ec0e122e461a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25246
30633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.2524630633
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.189633281
Short name T1371
Test name
Test status
Simulation time 8440344451 ps
CPU time 8.23 seconds
Started Apr 16 01:02:25 PM PDT 24
Finished Apr 16 01:02:35 PM PDT 24
Peak memory 204016 kb
Host smart-36d7ed82-dd0d-413e-bbaa-d329e3a63418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18963
3281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.189633281
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.3040778756
Short name T495
Test name
Test status
Simulation time 8377925692 ps
CPU time 8.2 seconds
Started Apr 16 01:02:29 PM PDT 24
Finished Apr 16 01:02:38 PM PDT 24
Peak memory 203964 kb
Host smart-272052cf-3a02-4925-888e-b5f3079f26a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30407
78756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.3040778756
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.1308620033
Short name T1212
Test name
Test status
Simulation time 34431718 ps
CPU time 0.64 seconds
Started Apr 16 01:02:30 PM PDT 24
Finished Apr 16 01:02:32 PM PDT 24
Peak memory 203836 kb
Host smart-be94ac95-32d6-45dc-8cda-db5b4a2cd255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13086
20033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.1308620033
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.3333078292
Short name T549
Test name
Test status
Simulation time 8371763795 ps
CPU time 8.55 seconds
Started Apr 16 01:02:39 PM PDT 24
Finished Apr 16 01:02:48 PM PDT 24
Peak memory 203996 kb
Host smart-dbae3c94-ae18-48cd-8caa-e2e9fc44193c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33330
78292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.3333078292
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3034350798
Short name T1328
Test name
Test status
Simulation time 8464338869 ps
CPU time 9.69 seconds
Started Apr 16 01:02:29 PM PDT 24
Finished Apr 16 01:02:40 PM PDT 24
Peak memory 204024 kb
Host smart-700ec199-bb9c-430e-bfb6-cfbd277cc6f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30343
50798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3034350798
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.3283012650
Short name T1053
Test name
Test status
Simulation time 8453520245 ps
CPU time 8.89 seconds
Started Apr 16 01:02:31 PM PDT 24
Finished Apr 16 01:02:41 PM PDT 24
Peak memory 203976 kb
Host smart-67d1c17f-b204-403a-9d8b-b106c83c3933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32830
12650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.3283012650
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.1335095317
Short name T715
Test name
Test status
Simulation time 8399498823 ps
CPU time 10.39 seconds
Started Apr 16 01:02:29 PM PDT 24
Finished Apr 16 01:02:40 PM PDT 24
Peak memory 203988 kb
Host smart-d31d3ad5-61cd-49e6-be4f-8d401bf97a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13350
95317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.1335095317
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3076483922
Short name T487
Test name
Test status
Simulation time 8369109435 ps
CPU time 10.17 seconds
Started Apr 16 01:02:35 PM PDT 24
Finished Apr 16 01:02:46 PM PDT 24
Peak memory 203976 kb
Host smart-73cf711f-0a08-4c39-a87f-ef6c9e5d07c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30764
83922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3076483922
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.1763382650
Short name T800
Test name
Test status
Simulation time 8434035629 ps
CPU time 8.66 seconds
Started Apr 16 01:02:26 PM PDT 24
Finished Apr 16 01:02:35 PM PDT 24
Peak memory 203992 kb
Host smart-49fd1013-393a-4ac3-a05a-4da1fbe0047a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17633
82650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.1763382650
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.2927863920
Short name T362
Test name
Test status
Simulation time 8405150709 ps
CPU time 7.94 seconds
Started Apr 16 01:02:31 PM PDT 24
Finished Apr 16 01:02:40 PM PDT 24
Peak memory 204044 kb
Host smart-8f7ac85f-f9f9-4f24-8790-0f4d9dce3277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29278
63920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.2927863920
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.472036495
Short name T377
Test name
Test status
Simulation time 8442908779 ps
CPU time 7.75 seconds
Started Apr 16 01:02:35 PM PDT 24
Finished Apr 16 01:02:44 PM PDT 24
Peak memory 203976 kb
Host smart-0ebff20c-f8a8-484a-bb2d-ba8bebe06682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47203
6495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.472036495
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.1385677239
Short name T525
Test name
Test status
Simulation time 8471618962 ps
CPU time 8.9 seconds
Started Apr 16 01:02:35 PM PDT 24
Finished Apr 16 01:02:45 PM PDT 24
Peak memory 204036 kb
Host smart-efcad3da-bd39-494d-a9c3-fe9d96942fb1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1385677239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.1385677239
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.777790461
Short name T1283
Test name
Test status
Simulation time 8381084191 ps
CPU time 7.92 seconds
Started Apr 16 01:02:35 PM PDT 24
Finished Apr 16 01:02:43 PM PDT 24
Peak memory 203964 kb
Host smart-bc78c6f1-29e2-4e85-b18e-f7490ac508ff
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=777790461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.777790461
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.2049767503
Short name T383
Test name
Test status
Simulation time 8401303956 ps
CPU time 8.28 seconds
Started Apr 16 01:02:34 PM PDT 24
Finished Apr 16 01:02:43 PM PDT 24
Peak memory 204028 kb
Host smart-462118f1-e1e6-41d4-9e81-f2c5180fc4dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20497
67503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.2049767503
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.406876230
Short name T573
Test name
Test status
Simulation time 8374852602 ps
CPU time 7.88 seconds
Started Apr 16 01:02:31 PM PDT 24
Finished Apr 16 01:02:40 PM PDT 24
Peak memory 204036 kb
Host smart-8ca3d921-c398-44fa-9d50-345a295d69cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40687
6230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.406876230
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_enable.4058161109
Short name T653
Test name
Test status
Simulation time 8427163254 ps
CPU time 8.27 seconds
Started Apr 16 01:02:31 PM PDT 24
Finished Apr 16 01:02:40 PM PDT 24
Peak memory 204020 kb
Host smart-9ce42e4c-e92c-401f-a0e9-3a10aff3152f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40581
61109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.4058161109
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.3368373408
Short name T862
Test name
Test status
Simulation time 82529067 ps
CPU time 1.08 seconds
Started Apr 16 01:02:34 PM PDT 24
Finished Apr 16 01:02:35 PM PDT 24
Peak memory 204088 kb
Host smart-aaaf3b13-58cb-4076-bb95-370260595273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33683
73408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.3368373408
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.558875393
Short name T1242
Test name
Test status
Simulation time 8427795924 ps
CPU time 7.69 seconds
Started Apr 16 01:02:35 PM PDT 24
Finished Apr 16 01:02:44 PM PDT 24
Peak memory 203968 kb
Host smart-6c271e09-44e5-4391-aa9a-e58135ac5930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55887
5393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.558875393
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.644193564
Short name T608
Test name
Test status
Simulation time 8374003614 ps
CPU time 8.49 seconds
Started Apr 16 01:02:33 PM PDT 24
Finished Apr 16 01:02:43 PM PDT 24
Peak memory 204020 kb
Host smart-cf9e28d8-5b85-43af-aec9-1e36911116cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64419
3564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.644193564
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.2532941876
Short name T1353
Test name
Test status
Simulation time 8421537629 ps
CPU time 8.59 seconds
Started Apr 16 01:02:30 PM PDT 24
Finished Apr 16 01:02:40 PM PDT 24
Peak memory 203992 kb
Host smart-b3f0209c-fd0b-4881-9f0a-98c48caa0db5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25329
41876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.2532941876
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.698855522
Short name T1120
Test name
Test status
Simulation time 8414986724 ps
CPU time 9.43 seconds
Started Apr 16 01:02:30 PM PDT 24
Finished Apr 16 01:02:41 PM PDT 24
Peak memory 204036 kb
Host smart-c0e22cd0-d023-4594-962f-2e25aa8d1c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69885
5522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.698855522
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.1223504492
Short name T743
Test name
Test status
Simulation time 8370072594 ps
CPU time 8.09 seconds
Started Apr 16 01:02:29 PM PDT 24
Finished Apr 16 01:02:38 PM PDT 24
Peak memory 204032 kb
Host smart-771f06af-d8c5-4e6a-bb9d-4c9fc8c23c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12235
04492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.1223504492
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3261750457
Short name T18
Test name
Test status
Simulation time 8393333278 ps
CPU time 9.36 seconds
Started Apr 16 01:02:34 PM PDT 24
Finished Apr 16 01:02:44 PM PDT 24
Peak memory 203972 kb
Host smart-6eddcab3-e754-4f69-8ba4-7bfc20f81670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32617
50457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3261750457
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.3369991033
Short name T611
Test name
Test status
Simulation time 8413656175 ps
CPU time 7.98 seconds
Started Apr 16 01:02:38 PM PDT 24
Finished Apr 16 01:02:46 PM PDT 24
Peak memory 204000 kb
Host smart-8dcdfc7d-62c7-4f42-bacc-b31f4b098700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33699
91033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3369991033
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.2774722230
Short name T969
Test name
Test status
Simulation time 8411873887 ps
CPU time 7.82 seconds
Started Apr 16 01:02:34 PM PDT 24
Finished Apr 16 01:02:42 PM PDT 24
Peak memory 204036 kb
Host smart-836e54d1-937c-4af2-a1a7-8ffcf3ab2f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27747
22230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2774722230
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1375775455
Short name T406
Test name
Test status
Simulation time 8368903400 ps
CPU time 9.95 seconds
Started Apr 16 01:02:34 PM PDT 24
Finished Apr 16 01:02:45 PM PDT 24
Peak memory 204044 kb
Host smart-dd996916-d7fc-4896-9ec6-f22e38584236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13757
75455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1375775455
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.1954738494
Short name T942
Test name
Test status
Simulation time 73648434 ps
CPU time 0.69 seconds
Started Apr 16 01:02:37 PM PDT 24
Finished Apr 16 01:02:38 PM PDT 24
Peak memory 203952 kb
Host smart-d4633a59-da9e-42d8-ab2b-6a2065e2b262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19547
38494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.1954738494
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.4266451547
Short name T490
Test name
Test status
Simulation time 8464373095 ps
CPU time 8.16 seconds
Started Apr 16 01:02:34 PM PDT 24
Finished Apr 16 01:02:43 PM PDT 24
Peak memory 204048 kb
Host smart-d7bd986e-f777-43e4-bc6c-72574f7dbf4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42664
51547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.4266451547
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.1940006860
Short name T61
Test name
Test status
Simulation time 8384726844 ps
CPU time 8.34 seconds
Started Apr 16 01:02:35 PM PDT 24
Finished Apr 16 01:02:45 PM PDT 24
Peak memory 204028 kb
Host smart-c985fc7e-47e9-4007-a9d2-39d975325065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19400
06860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.1940006860
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.1876442289
Short name T446
Test name
Test status
Simulation time 8380011874 ps
CPU time 7.75 seconds
Started Apr 16 01:02:32 PM PDT 24
Finished Apr 16 01:02:41 PM PDT 24
Peak memory 203972 kb
Host smart-e26ffd68-0bf6-4fb1-b38f-921c418a0d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18764
42289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.1876442289
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.1681897461
Short name T829
Test name
Test status
Simulation time 8369597813 ps
CPU time 7.86 seconds
Started Apr 16 01:02:36 PM PDT 24
Finished Apr 16 01:02:45 PM PDT 24
Peak memory 203936 kb
Host smart-e3e0a995-f80e-4488-9802-8b14562309b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16818
97461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.1681897461
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.571349386
Short name T1121
Test name
Test status
Simulation time 8418823060 ps
CPU time 9.21 seconds
Started Apr 16 01:02:31 PM PDT 24
Finished Apr 16 01:02:41 PM PDT 24
Peak memory 204020 kb
Host smart-1031476c-7a41-431b-8b9d-5ec873ddf751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57134
9386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.571349386
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.2630105004
Short name T408
Test name
Test status
Simulation time 8402637656 ps
CPU time 8.23 seconds
Started Apr 16 01:02:34 PM PDT 24
Finished Apr 16 01:02:43 PM PDT 24
Peak memory 204012 kb
Host smart-0607cae1-7951-49ee-8b75-40488f53934f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26301
05004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.2630105004
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.max_length_in_transaction.441986688
Short name T921
Test name
Test status
Simulation time 8465537087 ps
CPU time 7.56 seconds
Started Apr 16 01:02:41 PM PDT 24
Finished Apr 16 01:02:50 PM PDT 24
Peak memory 203956 kb
Host smart-36c5a8af-e3fe-4fc8-b56a-c1ea679c7c29
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=441986688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.441986688
Directory /workspace/14.max_length_in_transaction/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.1398413904
Short name T797
Test name
Test status
Simulation time 8377133679 ps
CPU time 8.36 seconds
Started Apr 16 01:02:45 PM PDT 24
Finished Apr 16 01:02:54 PM PDT 24
Peak memory 204052 kb
Host smart-6fcf239c-9fa0-4ac4-9f37-34daf60d42b3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1398413904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.1398413904
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.4065560839
Short name T619
Test name
Test status
Simulation time 8386877447 ps
CPU time 8.75 seconds
Started Apr 16 01:02:41 PM PDT 24
Finished Apr 16 01:02:50 PM PDT 24
Peak memory 204044 kb
Host smart-525dbf99-2e63-477c-badb-fadd2f4b80f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40655
60839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.4065560839
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2906044098
Short name T485
Test name
Test status
Simulation time 8390659480 ps
CPU time 7.57 seconds
Started Apr 16 01:02:35 PM PDT 24
Finished Apr 16 01:02:44 PM PDT 24
Peak memory 203964 kb
Host smart-95714f7b-8375-4428-b6b6-54e23bc22773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29060
44098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2906044098
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_enable.1456068834
Short name T1009
Test name
Test status
Simulation time 8377900139 ps
CPU time 8.06 seconds
Started Apr 16 01:02:36 PM PDT 24
Finished Apr 16 01:02:45 PM PDT 24
Peak memory 203980 kb
Host smart-4ee1d6e8-16e5-43c5-a764-8978e1e09def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14560
68834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1456068834
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.1580270188
Short name T726
Test name
Test status
Simulation time 109365429 ps
CPU time 1.39 seconds
Started Apr 16 01:02:37 PM PDT 24
Finished Apr 16 01:02:39 PM PDT 24
Peak memory 204108 kb
Host smart-0bdcc8a9-81af-4a9c-9036-5d70ac2f8166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15802
70188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.1580270188
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.3490586691
Short name T1361
Test name
Test status
Simulation time 8374756965 ps
CPU time 8.38 seconds
Started Apr 16 01:02:41 PM PDT 24
Finished Apr 16 01:02:50 PM PDT 24
Peak memory 203956 kb
Host smart-a0387391-8763-4db8-a3a1-4b240fdec405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34905
86691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.3490586691
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.1555319507
Short name T959
Test name
Test status
Simulation time 8382640627 ps
CPU time 9.08 seconds
Started Apr 16 01:02:37 PM PDT 24
Finished Apr 16 01:02:47 PM PDT 24
Peak memory 203936 kb
Host smart-ae18a80d-62b3-408d-8031-37cc01b0383d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15553
19507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1555319507
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.2824259832
Short name T1012
Test name
Test status
Simulation time 8442915961 ps
CPU time 10.11 seconds
Started Apr 16 01:02:35 PM PDT 24
Finished Apr 16 01:02:46 PM PDT 24
Peak memory 204032 kb
Host smart-294c0bf4-310b-4a33-972e-6cd15114609f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28242
59832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.2824259832
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.1482782818
Short name T839
Test name
Test status
Simulation time 8378010040 ps
CPU time 7.79 seconds
Started Apr 16 01:02:33 PM PDT 24
Finished Apr 16 01:02:41 PM PDT 24
Peak memory 203932 kb
Host smart-4ca036e5-01e7-47a7-9ba2-5dc2a5cd3691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14827
82818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.1482782818
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.616752306
Short name T1249
Test name
Test status
Simulation time 8395139471 ps
CPU time 9.74 seconds
Started Apr 16 01:02:39 PM PDT 24
Finished Apr 16 01:02:49 PM PDT 24
Peak memory 204016 kb
Host smart-f555bd8f-2de9-43d8-ab94-25c1b93ccb97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61675
2306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.616752306
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.665747317
Short name T513
Test name
Test status
Simulation time 8407778006 ps
CPU time 10.23 seconds
Started Apr 16 01:02:46 PM PDT 24
Finished Apr 16 01:02:57 PM PDT 24
Peak memory 203980 kb
Host smart-067d2f74-5a21-464a-8111-b3a6dfb5e1bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66574
7317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.665747317
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.3393490928
Short name T740
Test name
Test status
Simulation time 8371117142 ps
CPU time 7.89 seconds
Started Apr 16 01:02:40 PM PDT 24
Finished Apr 16 01:02:49 PM PDT 24
Peak memory 204012 kb
Host smart-3474338c-e383-4001-bec2-16e6174ed3e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33934
90928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.3393490928
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3282192764
Short name T304
Test name
Test status
Simulation time 57992885 ps
CPU time 0.68 seconds
Started Apr 16 01:02:40 PM PDT 24
Finished Apr 16 01:02:42 PM PDT 24
Peak memory 203880 kb
Host smart-79fba94b-a5fb-44d6-a5df-5446fa1f047a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32821
92764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3282192764
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3970393338
Short name T850
Test name
Test status
Simulation time 20460428642 ps
CPU time 40.1 seconds
Started Apr 16 01:02:39 PM PDT 24
Finished Apr 16 01:03:20 PM PDT 24
Peak memory 204268 kb
Host smart-fb848bbe-6df7-46fe-a3ed-a99d6c20fb7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39703
93338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3970393338
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.2179777842
Short name T416
Test name
Test status
Simulation time 8409196616 ps
CPU time 8.1 seconds
Started Apr 16 01:02:40 PM PDT 24
Finished Apr 16 01:02:49 PM PDT 24
Peak memory 203948 kb
Host smart-c3cd569e-aac4-4c0e-8bf4-d8a7bf8aea71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21797
77842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.2179777842
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.1984492299
Short name T910
Test name
Test status
Simulation time 8429867057 ps
CPU time 8.51 seconds
Started Apr 16 01:02:39 PM PDT 24
Finished Apr 16 01:02:48 PM PDT 24
Peak memory 203948 kb
Host smart-eac4ea3a-9984-47de-bcc6-3701b41d5e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19844
92299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.1984492299
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.1990690500
Short name T645
Test name
Test status
Simulation time 8429803491 ps
CPU time 9.18 seconds
Started Apr 16 01:02:41 PM PDT 24
Finished Apr 16 01:02:51 PM PDT 24
Peak memory 204016 kb
Host smart-9a10d342-a688-4bc2-b3a8-f33593949449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19906
90500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.1990690500
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.2446860599
Short name T626
Test name
Test status
Simulation time 8421720561 ps
CPU time 8.22 seconds
Started Apr 16 01:02:38 PM PDT 24
Finished Apr 16 01:02:47 PM PDT 24
Peak memory 204044 kb
Host smart-05aed3e4-01c5-42ac-a302-1aa1dc5eedf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24468
60599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.2446860599
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.3655989341
Short name T433
Test name
Test status
Simulation time 8377465632 ps
CPU time 9.29 seconds
Started Apr 16 01:02:39 PM PDT 24
Finished Apr 16 01:02:50 PM PDT 24
Peak memory 204004 kb
Host smart-12330843-73c8-4c6d-ae67-722cef3781e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36559
89341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.3655989341
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.3367604750
Short name T835
Test name
Test status
Simulation time 8447077184 ps
CPU time 8.64 seconds
Started Apr 16 01:02:37 PM PDT 24
Finished Apr 16 01:02:46 PM PDT 24
Peak memory 204080 kb
Host smart-6039170a-a6fd-41cb-806f-de55b970e671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33676
04750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.3367604750
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.10646985
Short name T212
Test name
Test status
Simulation time 8418771997 ps
CPU time 8.38 seconds
Started Apr 16 01:02:40 PM PDT 24
Finished Apr 16 01:02:49 PM PDT 24
Peak memory 204044 kb
Host smart-d8376dda-35ff-4b69-bad6-bfd585f959ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10646
985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.10646985
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.389344541
Short name T438
Test name
Test status
Simulation time 8424055612 ps
CPU time 7.83 seconds
Started Apr 16 01:02:40 PM PDT 24
Finished Apr 16 01:02:49 PM PDT 24
Peak memory 203984 kb
Host smart-e77169e6-0dc8-4357-aa3e-0696bb2c1b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38934
4541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.389344541
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.1402344425
Short name T329
Test name
Test status
Simulation time 8498249169 ps
CPU time 8.32 seconds
Started Apr 16 01:02:45 PM PDT 24
Finished Apr 16 01:02:54 PM PDT 24
Peak memory 204032 kb
Host smart-8dd6b977-2dcc-4f4b-b731-702a8c4e258f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1402344425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.1402344425
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.1673883723
Short name T130
Test name
Test status
Simulation time 8376180492 ps
CPU time 9 seconds
Started Apr 16 01:02:47 PM PDT 24
Finished Apr 16 01:02:57 PM PDT 24
Peak memory 204092 kb
Host smart-fd266c43-0e2f-4f53-b67f-c29b9355144f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1673883723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.1673883723
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.2113256647
Short name T496
Test name
Test status
Simulation time 8409496289 ps
CPU time 9.4 seconds
Started Apr 16 01:02:45 PM PDT 24
Finished Apr 16 01:02:55 PM PDT 24
Peak memory 204028 kb
Host smart-cdadd458-b70f-405d-b890-78ae7403316a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21132
56647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.2113256647
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.368574565
Short name T842
Test name
Test status
Simulation time 8404319313 ps
CPU time 9.46 seconds
Started Apr 16 01:02:41 PM PDT 24
Finished Apr 16 01:02:51 PM PDT 24
Peak memory 203308 kb
Host smart-05e0aeeb-49d9-4269-a8fd-ef53e4926fb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36857
4565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.368574565
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_enable.2745829615
Short name T1019
Test name
Test status
Simulation time 8375926575 ps
CPU time 9.95 seconds
Started Apr 16 01:02:39 PM PDT 24
Finished Apr 16 01:02:50 PM PDT 24
Peak memory 204048 kb
Host smart-383e2e58-6fc1-487a-bc61-5761bc46510b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27458
29615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.2745829615
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2974573429
Short name T394
Test name
Test status
Simulation time 261527100 ps
CPU time 2.14 seconds
Started Apr 16 01:02:40 PM PDT 24
Finished Apr 16 01:02:43 PM PDT 24
Peak memory 204108 kb
Host smart-33d01099-42ea-4b6f-9bc5-b180c7c33d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29745
73429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2974573429
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.2432491344
Short name T6
Test name
Test status
Simulation time 8367959760 ps
CPU time 9.33 seconds
Started Apr 16 01:02:48 PM PDT 24
Finished Apr 16 01:02:58 PM PDT 24
Peak memory 203976 kb
Host smart-60998448-1578-41dc-85f3-222fb43e9530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24324
91344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.2432491344
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.472876390
Short name T80
Test name
Test status
Simulation time 8453186317 ps
CPU time 8.12 seconds
Started Apr 16 01:02:41 PM PDT 24
Finished Apr 16 01:02:50 PM PDT 24
Peak memory 204016 kb
Host smart-ff3fd35d-8b91-496b-9765-fc31dd65b880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47287
6390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.472876390
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3622506362
Short name T83
Test name
Test status
Simulation time 8418962249 ps
CPU time 8.05 seconds
Started Apr 16 01:02:40 PM PDT 24
Finished Apr 16 01:02:49 PM PDT 24
Peak memory 203948 kb
Host smart-0e9bac00-7e94-4174-98a4-88c2c73248de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36225
06362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3622506362
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.1136242146
Short name T1139
Test name
Test status
Simulation time 8367898862 ps
CPU time 7.84 seconds
Started Apr 16 01:02:44 PM PDT 24
Finished Apr 16 01:02:54 PM PDT 24
Peak memory 204048 kb
Host smart-6aaf2b74-224f-4ac4-b132-87f8cf340fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11362
42146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.1136242146
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.431751411
Short name T768
Test name
Test status
Simulation time 8432678133 ps
CPU time 10.25 seconds
Started Apr 16 01:02:45 PM PDT 24
Finished Apr 16 01:02:56 PM PDT 24
Peak memory 204024 kb
Host smart-a521b4cc-f827-46aa-a06d-89c8618ccd38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43175
1411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.431751411
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.1102626218
Short name T806
Test name
Test status
Simulation time 8433608623 ps
CPU time 7.91 seconds
Started Apr 16 01:02:43 PM PDT 24
Finished Apr 16 01:02:52 PM PDT 24
Peak memory 203984 kb
Host smart-91abc37a-e537-40bd-9ac4-591eb02e2d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11026
26218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.1102626218
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.2319317533
Short name T1366
Test name
Test status
Simulation time 8376084203 ps
CPU time 8.47 seconds
Started Apr 16 01:02:45 PM PDT 24
Finished Apr 16 01:02:54 PM PDT 24
Peak memory 204032 kb
Host smart-89879734-5ff5-48a0-862f-e9565631930f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23193
17533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.2319317533
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.1850217341
Short name T656
Test name
Test status
Simulation time 52863796 ps
CPU time 0.65 seconds
Started Apr 16 01:02:42 PM PDT 24
Finished Apr 16 01:02:45 PM PDT 24
Peak memory 203836 kb
Host smart-d50ea47a-9573-4d5a-9163-6702e1c04262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18502
17341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.1850217341
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.196328633
Short name T234
Test name
Test status
Simulation time 16565970645 ps
CPU time 30.73 seconds
Started Apr 16 01:02:45 PM PDT 24
Finished Apr 16 01:03:17 PM PDT 24
Peak memory 204276 kb
Host smart-af2d95ea-35e5-4216-b859-221672c93492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19632
8633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.196328633
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.3477824678
Short name T372
Test name
Test status
Simulation time 8397593426 ps
CPU time 9.69 seconds
Started Apr 16 01:02:44 PM PDT 24
Finished Apr 16 01:02:55 PM PDT 24
Peak memory 204028 kb
Host smart-220c95d7-0ba8-466a-9e97-da97e6e0a701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34778
24678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.3477824678
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3208665829
Short name T757
Test name
Test status
Simulation time 8401513357 ps
CPU time 9.13 seconds
Started Apr 16 01:02:43 PM PDT 24
Finished Apr 16 01:02:54 PM PDT 24
Peak memory 204032 kb
Host smart-9ee449ed-c361-4ff0-9693-18a1e1a31482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32086
65829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3208665829
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.3287883395
Short name T822
Test name
Test status
Simulation time 8371507638 ps
CPU time 10.38 seconds
Started Apr 16 01:02:44 PM PDT 24
Finished Apr 16 01:02:56 PM PDT 24
Peak memory 204044 kb
Host smart-937cee1b-0623-42c9-9383-8632ea383f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32878
83395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.3287883395
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2049279700
Short name T812
Test name
Test status
Simulation time 8374495731 ps
CPU time 9.16 seconds
Started Apr 16 01:02:43 PM PDT 24
Finished Apr 16 01:02:54 PM PDT 24
Peak memory 203944 kb
Host smart-088af146-4a21-4080-be7d-af3bd1f47864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20492
79700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2049279700
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.2698870412
Short name T1333
Test name
Test status
Simulation time 8368530081 ps
CPU time 8.63 seconds
Started Apr 16 01:02:45 PM PDT 24
Finished Apr 16 01:02:55 PM PDT 24
Peak memory 203984 kb
Host smart-1d0c6bc5-788d-4efc-8bca-932e63e50483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26988
70412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.2698870412
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2721068864
Short name T149
Test name
Test status
Simulation time 8443833389 ps
CPU time 7.85 seconds
Started Apr 16 01:02:40 PM PDT 24
Finished Apr 16 01:02:49 PM PDT 24
Peak memory 204032 kb
Host smart-5c27ae5f-fa10-45e8-b04c-ff33e86a509a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27210
68864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2721068864
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.315043300
Short name T19
Test name
Test status
Simulation time 8400904392 ps
CPU time 8.52 seconds
Started Apr 16 01:02:47 PM PDT 24
Finished Apr 16 01:02:57 PM PDT 24
Peak memory 204084 kb
Host smart-ac2062db-8db0-4072-a935-a928f913d39c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31504
3300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.315043300
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.382644994
Short name T285
Test name
Test status
Simulation time 8402950135 ps
CPU time 7.82 seconds
Started Apr 16 01:02:45 PM PDT 24
Finished Apr 16 01:02:54 PM PDT 24
Peak memory 204024 kb
Host smart-3ab2eff9-9ea3-4344-beab-c700a83baec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38264
4994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.382644994
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.3841608684
Short name T1088
Test name
Test status
Simulation time 8462714443 ps
CPU time 8.06 seconds
Started Apr 16 01:02:54 PM PDT 24
Finished Apr 16 01:03:02 PM PDT 24
Peak memory 204028 kb
Host smart-ef7c9b72-38c5-4a57-be29-0cbebade94a9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3841608684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.3841608684
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.min_length_in_transaction.1034784417
Short name T351
Test name
Test status
Simulation time 8408724741 ps
CPU time 9.81 seconds
Started Apr 16 01:02:49 PM PDT 24
Finished Apr 16 01:03:00 PM PDT 24
Peak memory 204008 kb
Host smart-417bf85d-4d62-4fe1-8cb9-6e0a7a9bd954
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1034784417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.1034784417
Directory /workspace/16.min_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.284276249
Short name T125
Test name
Test status
Simulation time 8439872451 ps
CPU time 8.14 seconds
Started Apr 16 01:02:52 PM PDT 24
Finished Apr 16 01:03:01 PM PDT 24
Peak memory 204012 kb
Host smart-3ae566c3-be48-4d7f-8f72-9695e20511b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28427
6249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.284276249
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.456602646
Short name T331
Test name
Test status
Simulation time 8379431162 ps
CPU time 10.1 seconds
Started Apr 16 01:02:42 PM PDT 24
Finished Apr 16 01:02:53 PM PDT 24
Peak memory 204048 kb
Host smart-ec1cb9c3-b698-4f51-9463-8fccea9de682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45660
2646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.456602646
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_enable.552381372
Short name T1051
Test name
Test status
Simulation time 8404732362 ps
CPU time 9.89 seconds
Started Apr 16 01:02:44 PM PDT 24
Finished Apr 16 01:02:55 PM PDT 24
Peak memory 203976 kb
Host smart-7d507efc-f08f-4586-9c9f-5559e7ba722e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55238
1372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.552381372
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.875773333
Short name T544
Test name
Test status
Simulation time 116374449 ps
CPU time 1.33 seconds
Started Apr 16 01:02:42 PM PDT 24
Finished Apr 16 01:02:44 PM PDT 24
Peak memory 204180 kb
Host smart-6f699871-4820-44a7-9124-7b9bd324de3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87577
3333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.875773333
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.1977932078
Short name T143
Test name
Test status
Simulation time 8417139409 ps
CPU time 8.83 seconds
Started Apr 16 01:02:52 PM PDT 24
Finished Apr 16 01:03:02 PM PDT 24
Peak memory 203980 kb
Host smart-c059c0ea-4ef4-41f5-a96a-0f3c9b859175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19779
32078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.1977932078
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.398634267
Short name T193
Test name
Test status
Simulation time 8363697783 ps
CPU time 7.42 seconds
Started Apr 16 01:02:50 PM PDT 24
Finished Apr 16 01:02:58 PM PDT 24
Peak memory 204024 kb
Host smart-d891ba2c-ade6-4cf9-ae67-c8163add6c9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39863
4267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.398634267
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.2925827853
Short name T577
Test name
Test status
Simulation time 8449933301 ps
CPU time 9.33 seconds
Started Apr 16 01:02:44 PM PDT 24
Finished Apr 16 01:02:55 PM PDT 24
Peak memory 204004 kb
Host smart-4f059d85-99e7-4d7e-8076-9f939f8e6877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29258
27853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.2925827853
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.2121923261
Short name T1198
Test name
Test status
Simulation time 8413433144 ps
CPU time 7.89 seconds
Started Apr 16 01:02:46 PM PDT 24
Finished Apr 16 01:02:54 PM PDT 24
Peak memory 204008 kb
Host smart-73a99d6d-0e4d-4a69-a144-7aa3027bc6a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21219
23261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.2121923261
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.44289897
Short name T876
Test name
Test status
Simulation time 8365133027 ps
CPU time 8.17 seconds
Started Apr 16 01:02:48 PM PDT 24
Finished Apr 16 01:02:57 PM PDT 24
Peak memory 203980 kb
Host smart-4a32c976-06d3-4d23-bc18-31243aec0653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44289
897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.44289897
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.1472222408
Short name T1103
Test name
Test status
Simulation time 8406841240 ps
CPU time 8.32 seconds
Started Apr 16 01:02:44 PM PDT 24
Finished Apr 16 01:02:53 PM PDT 24
Peak memory 203308 kb
Host smart-914d6a46-ec11-4c1d-8288-82a4a702f0d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14722
22408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.1472222408
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3647217192
Short name T1069
Test name
Test status
Simulation time 8376842634 ps
CPU time 10.33 seconds
Started Apr 16 01:02:45 PM PDT 24
Finished Apr 16 01:02:56 PM PDT 24
Peak memory 203308 kb
Host smart-f8e8b724-6020-4788-8f1c-913a74414f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36472
17192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3647217192
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2695536141
Short name T1304
Test name
Test status
Simulation time 8420188286 ps
CPU time 8.53 seconds
Started Apr 16 01:02:45 PM PDT 24
Finished Apr 16 01:02:55 PM PDT 24
Peak memory 204260 kb
Host smart-c9851948-77bd-4932-9ad4-856fafd6e37e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26955
36141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2695536141
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.666444307
Short name T621
Test name
Test status
Simulation time 8406462249 ps
CPU time 7.98 seconds
Started Apr 16 01:02:50 PM PDT 24
Finished Apr 16 01:02:59 PM PDT 24
Peak memory 203984 kb
Host smart-23def861-8ea7-4fe0-901d-0619680cf7cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66644
4307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.666444307
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.3526143397
Short name T934
Test name
Test status
Simulation time 8367945415 ps
CPU time 8.03 seconds
Started Apr 16 01:02:49 PM PDT 24
Finished Apr 16 01:02:58 PM PDT 24
Peak memory 204040 kb
Host smart-c75875e2-1d61-4e30-b077-e67a598dbb1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35261
43397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.3526143397
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.1478734570
Short name T952
Test name
Test status
Simulation time 37943840 ps
CPU time 0.65 seconds
Started Apr 16 01:02:49 PM PDT 24
Finished Apr 16 01:02:50 PM PDT 24
Peak memory 203896 kb
Host smart-83df32c0-7b20-4f2c-a0e7-c97cba90c2ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14787
34570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.1478734570
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.3683658673
Short name T1077
Test name
Test status
Simulation time 30597652910 ps
CPU time 65.02 seconds
Started Apr 16 01:02:50 PM PDT 24
Finished Apr 16 01:03:56 PM PDT 24
Peak memory 204312 kb
Host smart-9b558494-1eeb-44b5-a06a-3106094eb82f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36836
58673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.3683658673
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3407338509
Short name T554
Test name
Test status
Simulation time 8389167878 ps
CPU time 8.3 seconds
Started Apr 16 01:02:52 PM PDT 24
Finished Apr 16 01:03:01 PM PDT 24
Peak memory 203992 kb
Host smart-665c724d-717c-4f48-aea2-34ee7bffc7ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34073
38509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3407338509
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.766992765
Short name T896
Test name
Test status
Simulation time 8474138891 ps
CPU time 7.54 seconds
Started Apr 16 01:02:48 PM PDT 24
Finished Apr 16 01:02:57 PM PDT 24
Peak memory 204028 kb
Host smart-5ebe4c29-42ca-4abe-b560-964f78edf373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76699
2765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.766992765
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.2458236785
Short name T1007
Test name
Test status
Simulation time 8406541012 ps
CPU time 8.45 seconds
Started Apr 16 01:02:51 PM PDT 24
Finished Apr 16 01:03:00 PM PDT 24
Peak memory 203948 kb
Host smart-72ea96c2-48b1-4f5e-8fb7-aadb1acc4200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24582
36785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.2458236785
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.2076584315
Short name T660
Test name
Test status
Simulation time 8375969274 ps
CPU time 9.26 seconds
Started Apr 16 01:02:52 PM PDT 24
Finished Apr 16 01:03:02 PM PDT 24
Peak memory 203976 kb
Host smart-08a82efb-e067-4627-944f-efeef411ae33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20765
84315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.2076584315
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.3219826463
Short name T530
Test name
Test status
Simulation time 8372815120 ps
CPU time 9.87 seconds
Started Apr 16 01:02:50 PM PDT 24
Finished Apr 16 01:03:01 PM PDT 24
Peak memory 203908 kb
Host smart-34d895d9-7cec-41a5-8043-d239796600d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32198
26463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.3219826463
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1319375491
Short name T1130
Test name
Test status
Simulation time 8434472503 ps
CPU time 10.19 seconds
Started Apr 16 01:02:43 PM PDT 24
Finished Apr 16 01:02:55 PM PDT 24
Peak memory 204048 kb
Host smart-fefd0d5b-e636-45f2-ade4-a2c0e4d42e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13193
75491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1319375491
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2102506528
Short name T539
Test name
Test status
Simulation time 8391991078 ps
CPU time 8.42 seconds
Started Apr 16 01:02:49 PM PDT 24
Finished Apr 16 01:02:59 PM PDT 24
Peak memory 204260 kb
Host smart-a99cb7f2-7f24-45ee-86f6-26e0c2abe054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21025
06528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2102506528
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.1231015060
Short name T373
Test name
Test status
Simulation time 8374345472 ps
CPU time 8.48 seconds
Started Apr 16 01:02:50 PM PDT 24
Finished Apr 16 01:02:59 PM PDT 24
Peak memory 203976 kb
Host smart-19ba655c-5a24-4cf0-acc2-e383ebabe665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12310
15060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.1231015060
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.max_length_in_transaction.2512074469
Short name T1118
Test name
Test status
Simulation time 8462819882 ps
CPU time 10.28 seconds
Started Apr 16 01:03:00 PM PDT 24
Finished Apr 16 01:03:12 PM PDT 24
Peak memory 204044 kb
Host smart-8a9c96bf-fb1c-4cbd-8288-d7c6016f8ad5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2512074469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.2512074469
Directory /workspace/17.max_length_in_transaction/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.647247062
Short name T698
Test name
Test status
Simulation time 8373507106 ps
CPU time 8.19 seconds
Started Apr 16 01:03:00 PM PDT 24
Finished Apr 16 01:03:09 PM PDT 24
Peak memory 203988 kb
Host smart-476a4207-5543-4209-b312-23fc5360e76b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=647247062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.647247062
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.2082853417
Short name T450
Test name
Test status
Simulation time 8425243095 ps
CPU time 8.44 seconds
Started Apr 16 01:03:02 PM PDT 24
Finished Apr 16 01:03:11 PM PDT 24
Peak memory 204044 kb
Host smart-7b57620c-1a81-4459-b619-5549b753864f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20828
53417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.2082853417
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.1275301319
Short name T1298
Test name
Test status
Simulation time 8378235548 ps
CPU time 8.14 seconds
Started Apr 16 01:02:49 PM PDT 24
Finished Apr 16 01:02:58 PM PDT 24
Peak memory 203992 kb
Host smart-f45fcac1-a7de-4a7e-b5d3-2334b819d84d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12753
01319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.1275301319
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_enable.530462184
Short name T316
Test name
Test status
Simulation time 8394075346 ps
CPU time 7.94 seconds
Started Apr 16 01:02:50 PM PDT 24
Finished Apr 16 01:02:59 PM PDT 24
Peak memory 204028 kb
Host smart-2c29e7b2-aa18-4896-ad6b-c198b91d90e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53046
2184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.530462184
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.831801214
Short name T60
Test name
Test status
Simulation time 81115552 ps
CPU time 2.06 seconds
Started Apr 16 01:02:53 PM PDT 24
Finished Apr 16 01:02:56 PM PDT 24
Peak memory 204096 kb
Host smart-735749de-b011-426b-bdda-02558edab12c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83180
1214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.831801214
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.3252719371
Short name T135
Test name
Test status
Simulation time 8428310162 ps
CPU time 9.25 seconds
Started Apr 16 01:02:58 PM PDT 24
Finished Apr 16 01:03:08 PM PDT 24
Peak memory 204020 kb
Host smart-d9c4509e-9042-4558-8148-3b53e163df3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32527
19371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.3252719371
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.4109329464
Short name T1185
Test name
Test status
Simulation time 8362390039 ps
CPU time 8.86 seconds
Started Apr 16 01:03:00 PM PDT 24
Finished Apr 16 01:03:10 PM PDT 24
Peak memory 204024 kb
Host smart-1e351f22-e6f4-4892-9173-177febb8e781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41093
29464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.4109329464
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1353370019
Short name T702
Test name
Test status
Simulation time 8442027594 ps
CPU time 7.96 seconds
Started Apr 16 01:02:50 PM PDT 24
Finished Apr 16 01:02:59 PM PDT 24
Peak memory 203992 kb
Host smart-efcf56d8-ecf8-48f9-b7f5-8a1c761f81ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13533
70019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1353370019
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.3569220581
Short name T31
Test name
Test status
Simulation time 8457587490 ps
CPU time 7.88 seconds
Started Apr 16 01:02:50 PM PDT 24
Finished Apr 16 01:02:59 PM PDT 24
Peak memory 204068 kb
Host smart-9986e429-9bd2-493a-bab6-ede989fb5179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35692
20581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.3569220581
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.1807618552
Short name T536
Test name
Test status
Simulation time 8417021170 ps
CPU time 9.3 seconds
Started Apr 16 01:02:55 PM PDT 24
Finished Apr 16 01:03:06 PM PDT 24
Peak memory 203992 kb
Host smart-2f6ff936-7b94-4f9d-bf9b-a881cc90f4fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18076
18552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.1807618552
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.3499632596
Short name T112
Test name
Test status
Simulation time 8449939034 ps
CPU time 8.83 seconds
Started Apr 16 01:02:55 PM PDT 24
Finished Apr 16 01:03:05 PM PDT 24
Peak memory 203980 kb
Host smart-a8ac7a0b-5424-485f-9494-ca9f967bfc68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34996
32596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.3499632596
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.2750198741
Short name T688
Test name
Test status
Simulation time 8382312664 ps
CPU time 7.96 seconds
Started Apr 16 01:02:57 PM PDT 24
Finished Apr 16 01:03:06 PM PDT 24
Peak memory 203968 kb
Host smart-0d9a7db2-ffab-4307-af53-8d4167c09f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27501
98741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2750198741
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.379960837
Short name T841
Test name
Test status
Simulation time 8402488102 ps
CPU time 9.15 seconds
Started Apr 16 01:02:56 PM PDT 24
Finished Apr 16 01:03:07 PM PDT 24
Peak memory 204020 kb
Host smart-d703ef54-efba-423d-bd99-6085a3cd2b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37996
0837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.379960837
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.3895625111
Short name T82
Test name
Test status
Simulation time 8420059790 ps
CPU time 9.5 seconds
Started Apr 16 01:03:01 PM PDT 24
Finished Apr 16 01:03:12 PM PDT 24
Peak memory 203968 kb
Host smart-5aa0b4e9-3ce3-445d-896d-d9f2c3e15e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38956
25111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.3895625111
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.2588756166
Short name T437
Test name
Test status
Simulation time 8373775828 ps
CPU time 8 seconds
Started Apr 16 01:02:54 PM PDT 24
Finished Apr 16 01:03:04 PM PDT 24
Peak memory 203988 kb
Host smart-02a7ecff-4207-45a9-8274-c8d9e0429e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25887
56166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.2588756166
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.3994701914
Short name T489
Test name
Test status
Simulation time 132986056 ps
CPU time 0.72 seconds
Started Apr 16 01:03:00 PM PDT 24
Finished Apr 16 01:03:02 PM PDT 24
Peak memory 203920 kb
Host smart-00906240-3eca-4222-af11-1af98034e913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39947
01914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.3994701914
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3913170923
Short name T93
Test name
Test status
Simulation time 24504070096 ps
CPU time 50.61 seconds
Started Apr 16 01:02:56 PM PDT 24
Finished Apr 16 01:03:48 PM PDT 24
Peak memory 204284 kb
Host smart-fec395cd-ed7d-4a8d-a000-1a96a80fb52a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39131
70923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3913170923
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.1174610905
Short name T676
Test name
Test status
Simulation time 8370698483 ps
CPU time 8.23 seconds
Started Apr 16 01:02:55 PM PDT 24
Finished Apr 16 01:03:04 PM PDT 24
Peak memory 203980 kb
Host smart-700a3b36-9e02-4792-af63-59ddadb4622c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11746
10905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1174610905
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.421108826
Short name T623
Test name
Test status
Simulation time 8445689047 ps
CPU time 7.78 seconds
Started Apr 16 01:02:56 PM PDT 24
Finished Apr 16 01:03:05 PM PDT 24
Peak memory 204032 kb
Host smart-98f4029b-be2b-45f9-8902-bf133bedc81d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42110
8826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.421108826
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.1727568505
Short name T493
Test name
Test status
Simulation time 8416315854 ps
CPU time 9.22 seconds
Started Apr 16 01:02:55 PM PDT 24
Finished Apr 16 01:03:05 PM PDT 24
Peak memory 203960 kb
Host smart-2543d142-eb96-4283-893c-399934cc55a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17275
68505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.1727568505
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.3923291523
Short name T594
Test name
Test status
Simulation time 8398980451 ps
CPU time 8.1 seconds
Started Apr 16 01:02:56 PM PDT 24
Finished Apr 16 01:03:05 PM PDT 24
Peak memory 204028 kb
Host smart-1151e9d4-e04c-4ba8-9def-54535ad496af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39232
91523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.3923291523
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3647360518
Short name T1302
Test name
Test status
Simulation time 8368490703 ps
CPU time 7.85 seconds
Started Apr 16 01:02:55 PM PDT 24
Finished Apr 16 01:03:05 PM PDT 24
Peak memory 203956 kb
Host smart-8f0f4b62-69f2-4ab6-bb8e-c6b2fad7b755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36473
60518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3647360518
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.374374856
Short name T159
Test name
Test status
Simulation time 8402153285 ps
CPU time 7.71 seconds
Started Apr 16 01:02:49 PM PDT 24
Finished Apr 16 01:02:57 PM PDT 24
Peak memory 204032 kb
Host smart-ad75b9a8-493c-4166-9004-ed1c96cf44c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37437
4856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.374374856
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.2678084341
Short name T1188
Test name
Test status
Simulation time 8377634324 ps
CPU time 7.98 seconds
Started Apr 16 01:02:58 PM PDT 24
Finished Apr 16 01:03:07 PM PDT 24
Peak memory 204012 kb
Host smart-a924a4d3-37cb-4c00-9e5e-aa2dd89d3fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26780
84341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.2678084341
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.1002334573
Short name T1155
Test name
Test status
Simulation time 8377812220 ps
CPU time 8.04 seconds
Started Apr 16 01:02:55 PM PDT 24
Finished Apr 16 01:03:04 PM PDT 24
Peak memory 204024 kb
Host smart-c47e64ee-dd4e-431f-b242-137ec4f7ade0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10023
34573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.1002334573
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.2821924671
Short name T912
Test name
Test status
Simulation time 8473227989 ps
CPU time 8.76 seconds
Started Apr 16 01:03:11 PM PDT 24
Finished Apr 16 01:03:20 PM PDT 24
Peak memory 203976 kb
Host smart-72f3b5a1-e575-49fe-86cf-b5877d041963
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2821924671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.2821924671
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.2761970627
Short name T714
Test name
Test status
Simulation time 8390239079 ps
CPU time 8.51 seconds
Started Apr 16 01:03:12 PM PDT 24
Finished Apr 16 01:03:21 PM PDT 24
Peak memory 204024 kb
Host smart-860706d9-5760-4d84-a834-343a4d4c101b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2761970627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.2761970627
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.2366584285
Short name T874
Test name
Test status
Simulation time 8409740822 ps
CPU time 8.92 seconds
Started Apr 16 01:03:13 PM PDT 24
Finished Apr 16 01:03:23 PM PDT 24
Peak memory 204044 kb
Host smart-ba44c3d4-c667-43f0-a617-bad7a3d2ece5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23665
84285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.2366584285
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2249097104
Short name T1316
Test name
Test status
Simulation time 8388837843 ps
CPU time 9.96 seconds
Started Apr 16 01:03:01 PM PDT 24
Finished Apr 16 01:03:12 PM PDT 24
Peak memory 203984 kb
Host smart-4d58df8a-5e61-44e7-95f0-a8bc3722171e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22490
97104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2249097104
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_enable.1804905014
Short name T728
Test name
Test status
Simulation time 8385307856 ps
CPU time 7.87 seconds
Started Apr 16 01:03:02 PM PDT 24
Finished Apr 16 01:03:10 PM PDT 24
Peak memory 204048 kb
Host smart-22f2a8d1-b821-4842-94bd-1f17299c51b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18049
05014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.1804905014
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.411291821
Short name T1037
Test name
Test status
Simulation time 107144007 ps
CPU time 1.16 seconds
Started Apr 16 01:03:00 PM PDT 24
Finished Apr 16 01:03:02 PM PDT 24
Peak memory 204168 kb
Host smart-9f89a7ad-297d-4f60-b994-1b434e83b39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41129
1821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.411291821
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.3863670449
Short name T732
Test name
Test status
Simulation time 8370598192 ps
CPU time 7.89 seconds
Started Apr 16 01:03:11 PM PDT 24
Finished Apr 16 01:03:20 PM PDT 24
Peak memory 204048 kb
Host smart-aa5b2ba0-b30b-47d4-8949-49e064ace2f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38636
70449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3863670449
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.3962054160
Short name T427
Test name
Test status
Simulation time 8464218046 ps
CPU time 10.43 seconds
Started Apr 16 01:03:00 PM PDT 24
Finished Apr 16 01:03:12 PM PDT 24
Peak memory 204024 kb
Host smart-e40e8844-a5d3-459d-9bbd-ef41019b7426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39620
54160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3962054160
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.14837368
Short name T810
Test name
Test status
Simulation time 8421148147 ps
CPU time 8.11 seconds
Started Apr 16 01:03:05 PM PDT 24
Finished Apr 16 01:03:14 PM PDT 24
Peak memory 204016 kb
Host smart-00f8f993-2f98-4982-b198-4af9997fa1b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14837
368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.14837368
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.2808933044
Short name T1071
Test name
Test status
Simulation time 8377041636 ps
CPU time 7.93 seconds
Started Apr 16 01:03:04 PM PDT 24
Finished Apr 16 01:03:12 PM PDT 24
Peak memory 204048 kb
Host smart-e0022ae3-a3a5-4580-bb2e-13db0df7fbce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28089
33044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.2808933044
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.524118525
Short name T1243
Test name
Test status
Simulation time 8395775767 ps
CPU time 9.81 seconds
Started Apr 16 01:03:14 PM PDT 24
Finished Apr 16 01:03:25 PM PDT 24
Peak memory 203960 kb
Host smart-4d3253ff-c884-4a46-80b2-e6cbe75d9b60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52411
8525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.524118525
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1403295120
Short name T428
Test name
Test status
Simulation time 8415594204 ps
CPU time 8.98 seconds
Started Apr 16 01:03:05 PM PDT 24
Finished Apr 16 01:03:15 PM PDT 24
Peak memory 203996 kb
Host smart-2a981b95-5507-47d1-8e99-5b2748ab7e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14032
95120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1403295120
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.3678200282
Short name T414
Test name
Test status
Simulation time 8426853606 ps
CPU time 9.13 seconds
Started Apr 16 01:03:06 PM PDT 24
Finished Apr 16 01:03:16 PM PDT 24
Peak memory 203948 kb
Host smart-ddbb6e4d-28cb-44a3-8626-822ccaac45a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36782
00282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.3678200282
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3900838551
Short name T1119
Test name
Test status
Simulation time 8380550905 ps
CPU time 8.96 seconds
Started Apr 16 01:03:04 PM PDT 24
Finished Apr 16 01:03:14 PM PDT 24
Peak memory 204028 kb
Host smart-4c899bd3-a960-480b-aba5-0de52317fd36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39008
38551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3900838551
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.479295287
Short name T45
Test name
Test status
Simulation time 220331399 ps
CPU time 0.8 seconds
Started Apr 16 01:03:14 PM PDT 24
Finished Apr 16 01:03:16 PM PDT 24
Peak memory 203800 kb
Host smart-728e5cd8-8caf-4dda-9ed0-0745278f76ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47929
5287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.479295287
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.692804993
Short name T678
Test name
Test status
Simulation time 28148561034 ps
CPU time 52.43 seconds
Started Apr 16 01:03:08 PM PDT 24
Finished Apr 16 01:04:01 PM PDT 24
Peak memory 204300 kb
Host smart-9aa118c6-83c4-421a-950a-f31ce9168577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69280
4993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.692804993
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.1652754036
Short name T727
Test name
Test status
Simulation time 8429053647 ps
CPU time 7.95 seconds
Started Apr 16 01:03:06 PM PDT 24
Finished Apr 16 01:03:15 PM PDT 24
Peak memory 204044 kb
Host smart-8fde1e79-505c-474c-94b7-36d9656d9a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16527
54036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.1652754036
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.112505855
Short name T997
Test name
Test status
Simulation time 8447708555 ps
CPU time 7.95 seconds
Started Apr 16 01:03:06 PM PDT 24
Finished Apr 16 01:03:14 PM PDT 24
Peak memory 204028 kb
Host smart-51b849d8-793b-454f-a0f2-092a40a9eb68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11250
5855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.112505855
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.4209616923
Short name T484
Test name
Test status
Simulation time 8411773195 ps
CPU time 9.12 seconds
Started Apr 16 01:03:05 PM PDT 24
Finished Apr 16 01:03:15 PM PDT 24
Peak memory 204028 kb
Host smart-cae15534-cd5c-4114-a024-c144d55d69ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42096
16923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.4209616923
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.4235277754
Short name T165
Test name
Test status
Simulation time 8375571993 ps
CPU time 7.85 seconds
Started Apr 16 01:03:06 PM PDT 24
Finished Apr 16 01:03:14 PM PDT 24
Peak memory 204040 kb
Host smart-dc4c1989-11bc-43a5-a5cd-27ee91182037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42352
77754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.4235277754
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.2590306853
Short name T655
Test name
Test status
Simulation time 8367713995 ps
CPU time 8.08 seconds
Started Apr 16 01:03:07 PM PDT 24
Finished Apr 16 01:03:16 PM PDT 24
Peak memory 203944 kb
Host smart-408eaabc-74e0-4c16-b6b0-b40ed8392415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25903
06853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.2590306853
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.2688339588
Short name T91
Test name
Test status
Simulation time 8450120281 ps
CPU time 8.3 seconds
Started Apr 16 01:02:59 PM PDT 24
Finished Apr 16 01:03:08 PM PDT 24
Peak memory 204016 kb
Host smart-c39e0e3b-b147-405c-a178-92b6381e3fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26883
39588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.2688339588
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.3953682194
Short name T528
Test name
Test status
Simulation time 8398396062 ps
CPU time 8.03 seconds
Started Apr 16 01:03:14 PM PDT 24
Finished Apr 16 01:03:23 PM PDT 24
Peak memory 203960 kb
Host smart-027cf9a5-a766-4349-8ecc-bbfed69f9421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39536
82194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.3953682194
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.1487793716
Short name T472
Test name
Test status
Simulation time 8413693691 ps
CPU time 8.3 seconds
Started Apr 16 01:03:13 PM PDT 24
Finished Apr 16 01:03:22 PM PDT 24
Peak memory 203964 kb
Host smart-6f302dc1-75bf-498b-969e-8062f30ac89e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14877
93716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.1487793716
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.986120578
Short name T541
Test name
Test status
Simulation time 8467261488 ps
CPU time 7.92 seconds
Started Apr 16 01:03:18 PM PDT 24
Finished Apr 16 01:03:27 PM PDT 24
Peak memory 204052 kb
Host smart-1ac68214-faa6-4a27-af59-02ab16c9d743
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=986120578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.986120578
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.2898089218
Short name T1197
Test name
Test status
Simulation time 8375946112 ps
CPU time 7.51 seconds
Started Apr 16 01:03:14 PM PDT 24
Finished Apr 16 01:03:22 PM PDT 24
Peak memory 204040 kb
Host smart-dd353624-4db7-4b41-b7f5-e966486d8321
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2898089218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.2898089218
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.1697298022
Short name T233
Test name
Test status
Simulation time 8428705678 ps
CPU time 9.97 seconds
Started Apr 16 01:03:11 PM PDT 24
Finished Apr 16 01:03:22 PM PDT 24
Peak memory 204044 kb
Host smart-5130690b-3ed3-4a0a-8783-fa713bdd814c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16972
98022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.1697298022
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.291330882
Short name T775
Test name
Test status
Simulation time 8374698292 ps
CPU time 7.83 seconds
Started Apr 16 01:03:12 PM PDT 24
Finished Apr 16 01:03:21 PM PDT 24
Peak memory 203936 kb
Host smart-95131767-49ba-4a80-879f-f665fc085101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29133
0882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.291330882
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_enable.1703855413
Short name T1213
Test name
Test status
Simulation time 8387729951 ps
CPU time 7.96 seconds
Started Apr 16 01:03:10 PM PDT 24
Finished Apr 16 01:03:19 PM PDT 24
Peak memory 204028 kb
Host smart-65b1b61f-91c4-4655-a6c5-88fff3123782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17038
55413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.1703855413
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.919641963
Short name T861
Test name
Test status
Simulation time 183245832 ps
CPU time 1.95 seconds
Started Apr 16 01:03:07 PM PDT 24
Finished Apr 16 01:03:10 PM PDT 24
Peak memory 204120 kb
Host smart-470bdf47-5eb4-4eec-a8fa-10cff91cca29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91964
1963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.919641963
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.133609354
Short name T291
Test name
Test status
Simulation time 8449715984 ps
CPU time 7.63 seconds
Started Apr 16 01:03:10 PM PDT 24
Finished Apr 16 01:03:18 PM PDT 24
Peak memory 204004 kb
Host smart-6908e636-8444-4f48-acce-ac5fc7406bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13360
9354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.133609354
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.1584090101
Short name T458
Test name
Test status
Simulation time 8361122630 ps
CPU time 9.15 seconds
Started Apr 16 01:03:14 PM PDT 24
Finished Apr 16 01:03:24 PM PDT 24
Peak memory 203924 kb
Host smart-810f78f3-5ed4-499d-a093-06fd27949658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15840
90101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.1584090101
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.2990941188
Short name T447
Test name
Test status
Simulation time 8414151764 ps
CPU time 7.9 seconds
Started Apr 16 01:03:14 PM PDT 24
Finished Apr 16 01:03:23 PM PDT 24
Peak memory 203980 kb
Host smart-ef53e6c5-f757-4982-ba3e-72180114954d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29909
41188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.2990941188
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.89709997
Short name T1323
Test name
Test status
Simulation time 8413573528 ps
CPU time 7.98 seconds
Started Apr 16 01:03:13 PM PDT 24
Finished Apr 16 01:03:22 PM PDT 24
Peak memory 204048 kb
Host smart-5e96d394-d514-4fde-8be6-42373d7badbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89709
997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.89709997
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.501350905
Short name T1033
Test name
Test status
Simulation time 8381440760 ps
CPU time 7.61 seconds
Started Apr 16 01:03:13 PM PDT 24
Finished Apr 16 01:03:21 PM PDT 24
Peak memory 204016 kb
Host smart-e77c9cf2-e25f-4a91-9f3d-d462c4cf3919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50135
0905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.501350905
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.4134440659
Short name T527
Test name
Test status
Simulation time 8392458511 ps
CPU time 8.33 seconds
Started Apr 16 01:03:14 PM PDT 24
Finished Apr 16 01:03:24 PM PDT 24
Peak memory 203964 kb
Host smart-895e1e3e-040e-4e0c-9d04-3e2c0fc86115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41344
40659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.4134440659
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2334652475
Short name T1373
Test name
Test status
Simulation time 8383378442 ps
CPU time 8.7 seconds
Started Apr 16 01:03:10 PM PDT 24
Finished Apr 16 01:03:19 PM PDT 24
Peak memory 203976 kb
Host smart-0aab85db-2060-4608-8b89-57cd9f02bb0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23346
52475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2334652475
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.2356768600
Short name T231
Test name
Test status
Simulation time 8391865738 ps
CPU time 8.23 seconds
Started Apr 16 01:03:11 PM PDT 24
Finished Apr 16 01:03:21 PM PDT 24
Peak memory 204016 kb
Host smart-b69b432b-50c5-4f7a-8935-4e11014d2b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23567
68600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.2356768600
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.3259762547
Short name T614
Test name
Test status
Simulation time 8419428904 ps
CPU time 7.57 seconds
Started Apr 16 01:03:17 PM PDT 24
Finished Apr 16 01:03:26 PM PDT 24
Peak memory 203960 kb
Host smart-80990b4d-d26c-4618-948b-cfc431512862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32597
62547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.3259762547
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1436768898
Short name T582
Test name
Test status
Simulation time 44605107 ps
CPU time 0.65 seconds
Started Apr 16 01:03:09 PM PDT 24
Finished Apr 16 01:03:10 PM PDT 24
Peak memory 203912 kb
Host smart-a2b8f894-e3dd-49d8-9a34-3c657f8a5c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14367
68898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1436768898
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.1466798161
Short name T1259
Test name
Test status
Simulation time 14295868079 ps
CPU time 24.53 seconds
Started Apr 16 01:03:10 PM PDT 24
Finished Apr 16 01:03:36 PM PDT 24
Peak memory 204296 kb
Host smart-2d6c70c9-45e1-4150-92eb-601dd59df8be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14667
98161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.1466798161
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.157990120
Short name T629
Test name
Test status
Simulation time 8386453814 ps
CPU time 7.91 seconds
Started Apr 16 01:03:12 PM PDT 24
Finished Apr 16 01:03:21 PM PDT 24
Peak memory 204000 kb
Host smart-16a155d1-e956-443e-b1ff-3d91eaea2362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15799
0120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.157990120
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.4092505077
Short name T1199
Test name
Test status
Simulation time 8437442991 ps
CPU time 9.47 seconds
Started Apr 16 01:03:10 PM PDT 24
Finished Apr 16 01:03:20 PM PDT 24
Peak memory 204012 kb
Host smart-f74733a0-664c-478e-b43e-4936298746f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40925
05077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.4092505077
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.1587993082
Short name T558
Test name
Test status
Simulation time 8379264750 ps
CPU time 7.47 seconds
Started Apr 16 01:03:13 PM PDT 24
Finished Apr 16 01:03:22 PM PDT 24
Peak memory 203924 kb
Host smart-3cff3ccf-91fb-4fb6-9148-c85793feec59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15879
93082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.1587993082
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.1927263701
Short name T691
Test name
Test status
Simulation time 8389947034 ps
CPU time 7.79 seconds
Started Apr 16 01:03:10 PM PDT 24
Finished Apr 16 01:03:18 PM PDT 24
Peak memory 203904 kb
Host smart-8c793a89-1a51-4298-976f-c398fb504e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19272
63701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.1927263701
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.1308609890
Short name T1043
Test name
Test status
Simulation time 8375256130 ps
CPU time 8.35 seconds
Started Apr 16 01:03:10 PM PDT 24
Finished Apr 16 01:03:19 PM PDT 24
Peak memory 204032 kb
Host smart-d852a9a0-cc47-4d14-9a1b-4e37ab995a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13086
09890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.1308609890
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.845103316
Short name T1086
Test name
Test status
Simulation time 8387784470 ps
CPU time 8.57 seconds
Started Apr 16 01:03:21 PM PDT 24
Finished Apr 16 01:03:32 PM PDT 24
Peak memory 204004 kb
Host smart-99b40ab6-c3c5-4e9e-8e15-265ee1653f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84510
3316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.845103316
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.2708276017
Short name T987
Test name
Test status
Simulation time 8446595070 ps
CPU time 7.64 seconds
Started Apr 16 01:03:13 PM PDT 24
Finished Apr 16 01:03:22 PM PDT 24
Peak memory 203980 kb
Host smart-554ddfcd-bfe2-4a4f-af0e-cef6190b52d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27082
76017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.2708276017
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.2702028571
Short name T712
Test name
Test status
Simulation time 8474850283 ps
CPU time 8.82 seconds
Started Apr 16 01:01:19 PM PDT 24
Finished Apr 16 01:01:28 PM PDT 24
Peak memory 204032 kb
Host smart-beb23253-1957-49b7-84e9-7910bc695b15
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2702028571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.2702028571
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.1933004304
Short name T620
Test name
Test status
Simulation time 8373052910 ps
CPU time 8.21 seconds
Started Apr 16 01:01:19 PM PDT 24
Finished Apr 16 01:01:28 PM PDT 24
Peak memory 204256 kb
Host smart-a69fc919-9cb3-4696-b49c-3082372d59a1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1933004304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.1933004304
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.430684024
Short name T470
Test name
Test status
Simulation time 8413062246 ps
CPU time 8.28 seconds
Started Apr 16 01:01:19 PM PDT 24
Finished Apr 16 01:01:28 PM PDT 24
Peak memory 203916 kb
Host smart-b9f011a8-5357-40de-92e8-910881e30dbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43068
4024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.430684024
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.2120632157
Short name T965
Test name
Test status
Simulation time 8393718656 ps
CPU time 7.56 seconds
Started Apr 16 01:01:13 PM PDT 24
Finished Apr 16 01:01:21 PM PDT 24
Peak memory 204028 kb
Host smart-0285341b-d8aa-4e42-a6dc-ed0cc8305f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21206
32157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.2120632157
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_enable.1003017927
Short name T563
Test name
Test status
Simulation time 8377350268 ps
CPU time 9.16 seconds
Started Apr 16 01:01:15 PM PDT 24
Finished Apr 16 01:01:25 PM PDT 24
Peak memory 204048 kb
Host smart-291aa335-8182-4f3f-a8e5-b5914b806ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10030
17927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.1003017927
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2652024097
Short name T287
Test name
Test status
Simulation time 260589189 ps
CPU time 1.96 seconds
Started Apr 16 01:01:15 PM PDT 24
Finished Apr 16 01:01:18 PM PDT 24
Peak memory 204072 kb
Host smart-ae3a1edf-f67f-4960-8407-4c89255ec9ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26520
24097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2652024097
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.1013651197
Short name T871
Test name
Test status
Simulation time 8395508840 ps
CPU time 9.03 seconds
Started Apr 16 01:01:20 PM PDT 24
Finished Apr 16 01:01:30 PM PDT 24
Peak memory 204044 kb
Host smart-e82dbc54-9c59-4977-b7fe-a4992938d2c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10136
51197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.1013651197
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.2033468678
Short name T1135
Test name
Test status
Simulation time 8402918973 ps
CPU time 7.95 seconds
Started Apr 16 01:01:19 PM PDT 24
Finished Apr 16 01:01:28 PM PDT 24
Peak memory 203968 kb
Host smart-229d5059-11e4-422f-a266-a8b12f5c6236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20334
68678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2033468678
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.818995335
Short name T849
Test name
Test status
Simulation time 8426079575 ps
CPU time 7.72 seconds
Started Apr 16 01:01:15 PM PDT 24
Finished Apr 16 01:01:24 PM PDT 24
Peak memory 203944 kb
Host smart-a5dbc31e-b92b-447c-870c-087d27ce96a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81899
5335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.818995335
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.420380019
Short name T353
Test name
Test status
Simulation time 8433144852 ps
CPU time 8.35 seconds
Started Apr 16 01:01:15 PM PDT 24
Finished Apr 16 01:01:24 PM PDT 24
Peak memory 204016 kb
Host smart-81c0b1f9-85bc-4dae-b376-bb2ed342b20f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42038
0019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.420380019
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.1563731134
Short name T941
Test name
Test status
Simulation time 8375262020 ps
CPU time 7.67 seconds
Started Apr 16 01:01:16 PM PDT 24
Finished Apr 16 01:01:24 PM PDT 24
Peak memory 203980 kb
Host smart-8a8d00af-b762-479c-b606-252b2afdaf6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15637
31134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.1563731134
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.61446835
Short name T111
Test name
Test status
Simulation time 8427280344 ps
CPU time 7.58 seconds
Started Apr 16 01:01:13 PM PDT 24
Finished Apr 16 01:01:21 PM PDT 24
Peak memory 203992 kb
Host smart-d229f524-b1fb-4918-bcaf-eebff7ab9b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61446
835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.61446835
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.4256728499
Short name T1229
Test name
Test status
Simulation time 8399976859 ps
CPU time 7.51 seconds
Started Apr 16 01:01:12 PM PDT 24
Finished Apr 16 01:01:20 PM PDT 24
Peak memory 204052 kb
Host smart-69feaa28-841d-4724-834b-24309a603f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42567
28499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.4256728499
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.359214130
Short name T391
Test name
Test status
Simulation time 8440158821 ps
CPU time 9.62 seconds
Started Apr 16 01:01:21 PM PDT 24
Finished Apr 16 01:01:31 PM PDT 24
Peak memory 204056 kb
Host smart-070c7326-f852-4f8c-b298-10ba329aabba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35921
4130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.359214130
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.1440252722
Short name T511
Test name
Test status
Simulation time 8395149770 ps
CPU time 7.55 seconds
Started Apr 16 01:01:21 PM PDT 24
Finished Apr 16 01:01:29 PM PDT 24
Peak memory 204024 kb
Host smart-b4f120f1-2c6a-43d3-a431-b1df97dc9629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14402
52722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.1440252722
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.2949642992
Short name T7
Test name
Test status
Simulation time 8412340252 ps
CPU time 8.74 seconds
Started Apr 16 01:01:21 PM PDT 24
Finished Apr 16 01:01:31 PM PDT 24
Peak memory 204004 kb
Host smart-366cbc97-3749-4702-a424-054e1766a67f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29496
42992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.2949642992
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.4109531692
Short name T46
Test name
Test status
Simulation time 72183287 ps
CPU time 0.69 seconds
Started Apr 16 01:01:20 PM PDT 24
Finished Apr 16 01:01:21 PM PDT 24
Peak memory 203868 kb
Host smart-09d85c3b-86c4-4ae1-9d11-674f50e13a85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41095
31692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.4109531692
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.3511331981
Short name T1202
Test name
Test status
Simulation time 23159496115 ps
CPU time 42.59 seconds
Started Apr 16 01:01:18 PM PDT 24
Finished Apr 16 01:02:02 PM PDT 24
Peak memory 204332 kb
Host smart-4f8d65fb-fe5b-4904-b3d2-4d429ad3bd2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35113
31981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.3511331981
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.4223795856
Short name T1239
Test name
Test status
Simulation time 8415756817 ps
CPU time 8.58 seconds
Started Apr 16 01:01:18 PM PDT 24
Finished Apr 16 01:01:28 PM PDT 24
Peak memory 204028 kb
Host smart-793d70f7-4483-4b86-8041-d8062320de04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42237
95856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.4223795856
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.1436927081
Short name T148
Test name
Test status
Simulation time 8417250892 ps
CPU time 8.52 seconds
Started Apr 16 01:01:20 PM PDT 24
Finished Apr 16 01:01:29 PM PDT 24
Peak memory 203984 kb
Host smart-92879592-1e4a-44db-b6f2-db5da6c7003b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14369
27081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.1436927081
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.3948743796
Short name T395
Test name
Test status
Simulation time 8426066840 ps
CPU time 8.47 seconds
Started Apr 16 01:01:19 PM PDT 24
Finished Apr 16 01:01:28 PM PDT 24
Peak memory 204048 kb
Host smart-ecd23409-0c89-4090-87c3-e065291a6be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39487
43796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.3948743796
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.356474185
Short name T67
Test name
Test status
Simulation time 385039783 ps
CPU time 1.29 seconds
Started Apr 16 01:01:18 PM PDT 24
Finished Apr 16 01:01:20 PM PDT 24
Peak memory 221256 kb
Host smart-3a201fc9-2aeb-4b78-aedf-5ab849fe8308
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=356474185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.356474185
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.2419777614
Short name T22
Test name
Test status
Simulation time 8372630562 ps
CPU time 7.34 seconds
Started Apr 16 01:01:18 PM PDT 24
Finished Apr 16 01:01:26 PM PDT 24
Peak memory 204032 kb
Host smart-a97300c6-51d2-4846-8382-32093254843d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24197
77614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.2419777614
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.2677492720
Short name T1144
Test name
Test status
Simulation time 8374976337 ps
CPU time 7.74 seconds
Started Apr 16 01:01:22 PM PDT 24
Finished Apr 16 01:01:31 PM PDT 24
Peak memory 204024 kb
Host smart-2574fc3e-3f83-49bf-9ca6-838ce5fcdbe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26774
92720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.2677492720
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.3716495484
Short name T825
Test name
Test status
Simulation time 8457056639 ps
CPU time 8.93 seconds
Started Apr 16 01:01:18 PM PDT 24
Finished Apr 16 01:01:27 PM PDT 24
Peak memory 203968 kb
Host smart-40c62bd1-b095-4f9d-b789-1b437ca599f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37164
95484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.3716495484
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.265052485
Short name T877
Test name
Test status
Simulation time 8379344114 ps
CPU time 9.17 seconds
Started Apr 16 01:01:19 PM PDT 24
Finished Apr 16 01:01:29 PM PDT 24
Peak memory 204024 kb
Host smart-71daf385-3306-4031-8eb9-e2e0188820f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26505
2485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.265052485
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.3612769281
Short name T679
Test name
Test status
Simulation time 8389727649 ps
CPU time 7.55 seconds
Started Apr 16 01:01:18 PM PDT 24
Finished Apr 16 01:01:27 PM PDT 24
Peak memory 204028 kb
Host smart-8905a6c5-cbf2-4582-a802-532ae47bb17b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36127
69281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.3612769281
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.419887780
Short name T1309
Test name
Test status
Simulation time 8472148108 ps
CPU time 7.63 seconds
Started Apr 16 01:03:15 PM PDT 24
Finished Apr 16 01:03:24 PM PDT 24
Peak memory 204052 kb
Host smart-6f0bd59f-7bff-4533-94a5-ae16415eea7b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=419887780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.419887780
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.2608580819
Short name T722
Test name
Test status
Simulation time 8406823465 ps
CPU time 10.28 seconds
Started Apr 16 01:03:17 PM PDT 24
Finished Apr 16 01:03:28 PM PDT 24
Peak memory 204028 kb
Host smart-f4a53f9d-fdc4-4f06-87ce-9ad3f4045aa9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2608580819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.2608580819
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.668132129
Short name T610
Test name
Test status
Simulation time 8400262893 ps
CPU time 8.17 seconds
Started Apr 16 01:03:16 PM PDT 24
Finished Apr 16 01:03:25 PM PDT 24
Peak memory 204012 kb
Host smart-04773ec4-4b86-417d-b7e3-bf824fec2eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66813
2129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.668132129
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.2058291822
Short name T1342
Test name
Test status
Simulation time 8390739398 ps
CPU time 9 seconds
Started Apr 16 01:03:13 PM PDT 24
Finished Apr 16 01:03:23 PM PDT 24
Peak memory 204016 kb
Host smart-5ba2122b-9dae-4301-bac6-d3e8fd3f95d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20582
91822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2058291822
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_enable.3761942566
Short name T634
Test name
Test status
Simulation time 8377806363 ps
CPU time 7.54 seconds
Started Apr 16 01:03:22 PM PDT 24
Finished Apr 16 01:03:31 PM PDT 24
Peak memory 204000 kb
Host smart-7a0807cb-8dd2-4cfd-add2-9c74358f1d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37619
42566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.3761942566
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.201334988
Short name T1091
Test name
Test status
Simulation time 96028436 ps
CPU time 1.19 seconds
Started Apr 16 01:03:19 PM PDT 24
Finished Apr 16 01:03:22 PM PDT 24
Peak memory 204056 kb
Host smart-64b7595c-3a29-477c-b831-8e36aee7e258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20133
4988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.201334988
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.874121971
Short name T636
Test name
Test status
Simulation time 8440399960 ps
CPU time 8.08 seconds
Started Apr 16 01:03:22 PM PDT 24
Finished Apr 16 01:03:31 PM PDT 24
Peak memory 204004 kb
Host smart-dddde1ac-431b-4805-9ae2-c3f8f32f3a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87412
1971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.874121971
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.4071864117
Short name T1307
Test name
Test status
Simulation time 8453767385 ps
CPU time 7.98 seconds
Started Apr 16 01:03:18 PM PDT 24
Finished Apr 16 01:03:27 PM PDT 24
Peak memory 203996 kb
Host smart-f41c4007-cc39-4bd3-b7f2-4a06e6be4974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40718
64117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.4071864117
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1670597918
Short name T1117
Test name
Test status
Simulation time 8415342096 ps
CPU time 8.52 seconds
Started Apr 16 01:03:14 PM PDT 24
Finished Apr 16 01:03:24 PM PDT 24
Peak memory 204012 kb
Host smart-22e1c113-5487-4bdd-8087-ceba034a5cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16705
97918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1670597918
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.3969157605
Short name T846
Test name
Test status
Simulation time 8370934436 ps
CPU time 8.33 seconds
Started Apr 16 01:03:19 PM PDT 24
Finished Apr 16 01:03:28 PM PDT 24
Peak memory 203992 kb
Host smart-a6f7b0ab-9e2a-48a3-994e-4fd137e232ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39691
57605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.3969157605
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.2771699787
Short name T923
Test name
Test status
Simulation time 8439731910 ps
CPU time 8.75 seconds
Started Apr 16 01:03:19 PM PDT 24
Finished Apr 16 01:03:29 PM PDT 24
Peak memory 203928 kb
Host smart-8b3057d0-1e79-4e14-8393-ce8d3dec990f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27716
99787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.2771699787
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.2004479430
Short name T1032
Test name
Test status
Simulation time 8385693515 ps
CPU time 8.4 seconds
Started Apr 16 01:03:15 PM PDT 24
Finished Apr 16 01:03:24 PM PDT 24
Peak memory 204028 kb
Host smart-8088b559-9995-4f29-b6c1-51f2d98c4469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20044
79430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.2004479430
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.1342202637
Short name T1022
Test name
Test status
Simulation time 8404435275 ps
CPU time 10.02 seconds
Started Apr 16 01:03:16 PM PDT 24
Finished Apr 16 01:03:27 PM PDT 24
Peak memory 204048 kb
Host smart-a002df84-2ce9-41fc-b79e-9d4c1de5ffd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13422
02637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.1342202637
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.943004306
Short name T171
Test name
Test status
Simulation time 8406347983 ps
CPU time 7.82 seconds
Started Apr 16 01:03:14 PM PDT 24
Finished Apr 16 01:03:23 PM PDT 24
Peak memory 204032 kb
Host smart-0145ca79-9e84-4905-bb99-1eeb1fcdd382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94300
4306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.943004306
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.3936786871
Short name T1168
Test name
Test status
Simulation time 8371097531 ps
CPU time 7.43 seconds
Started Apr 16 01:03:14 PM PDT 24
Finished Apr 16 01:03:23 PM PDT 24
Peak memory 203964 kb
Host smart-cba1a4a6-d48d-482d-8494-80cfb2c63c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39367
86871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.3936786871
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.3098308662
Short name T1368
Test name
Test status
Simulation time 44199950 ps
CPU time 0.64 seconds
Started Apr 16 01:03:16 PM PDT 24
Finished Apr 16 01:03:18 PM PDT 24
Peak memory 203848 kb
Host smart-3eecbb8b-9f98-4625-adc3-6b3818544c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30983
08662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.3098308662
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.1797916276
Short name T906
Test name
Test status
Simulation time 26029967088 ps
CPU time 50.24 seconds
Started Apr 16 01:03:15 PM PDT 24
Finished Apr 16 01:04:06 PM PDT 24
Peak memory 204368 kb
Host smart-22590505-15dd-47f7-b666-d47fbf6f07ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17979
16276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.1797916276
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.2038416308
Short name T1040
Test name
Test status
Simulation time 8391334518 ps
CPU time 8.21 seconds
Started Apr 16 01:03:16 PM PDT 24
Finished Apr 16 01:03:25 PM PDT 24
Peak memory 204016 kb
Host smart-abd789ab-72be-45f9-b2b4-9561529dd9a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20384
16308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.2038416308
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.673016819
Short name T869
Test name
Test status
Simulation time 8400500047 ps
CPU time 9.73 seconds
Started Apr 16 01:03:15 PM PDT 24
Finished Apr 16 01:03:26 PM PDT 24
Peak memory 203948 kb
Host smart-e017c68e-7d2b-40df-83bf-2eda01125299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67301
6819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.673016819
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.3808875124
Short name T642
Test name
Test status
Simulation time 8378330664 ps
CPU time 8.29 seconds
Started Apr 16 01:03:22 PM PDT 24
Finished Apr 16 01:03:32 PM PDT 24
Peak memory 204000 kb
Host smart-05da6687-ae7c-4a3c-87ed-15b374a97396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38088
75124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.3808875124
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.2177945285
Short name T1364
Test name
Test status
Simulation time 8431320321 ps
CPU time 9.75 seconds
Started Apr 16 01:03:15 PM PDT 24
Finished Apr 16 01:03:26 PM PDT 24
Peak memory 204012 kb
Host smart-a185e4e8-efdc-46b5-b77e-5756c28f8fff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21779
45285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2177945285
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1222994647
Short name T1273
Test name
Test status
Simulation time 8372217504 ps
CPU time 7.71 seconds
Started Apr 16 01:03:18 PM PDT 24
Finished Apr 16 01:03:27 PM PDT 24
Peak memory 203984 kb
Host smart-7bb41a4f-adaa-41e9-8df5-442e075936ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12229
94647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1222994647
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.2272829378
Short name T154
Test name
Test status
Simulation time 8467587450 ps
CPU time 8.68 seconds
Started Apr 16 01:03:14 PM PDT 24
Finished Apr 16 01:03:24 PM PDT 24
Peak memory 204012 kb
Host smart-ccd7d70f-78fd-4fdc-b71b-7b5c26d1befc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22728
29378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.2272829378
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.3080514258
Short name T520
Test name
Test status
Simulation time 8401681367 ps
CPU time 8.01 seconds
Started Apr 16 01:03:12 PM PDT 24
Finished Apr 16 01:03:21 PM PDT 24
Peak memory 203976 kb
Host smart-9634ff1c-7d78-4bb6-92a4-46417df9416e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30805
14258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.3080514258
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.3519683232
Short name T382
Test name
Test status
Simulation time 8452944171 ps
CPU time 8.56 seconds
Started Apr 16 01:03:18 PM PDT 24
Finished Apr 16 01:03:27 PM PDT 24
Peak memory 204004 kb
Host smart-88955be6-3977-401e-8887-3dbe632ba7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35196
83232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.3519683232
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.3805539738
Short name T49
Test name
Test status
Simulation time 8465280297 ps
CPU time 10.37 seconds
Started Apr 16 01:03:19 PM PDT 24
Finished Apr 16 01:03:30 PM PDT 24
Peak memory 203984 kb
Host smart-6e992bd8-c753-49cf-8f75-34f8a3278c5f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3805539738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.3805539738
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.743979310
Short name T647
Test name
Test status
Simulation time 8378547944 ps
CPU time 8.36 seconds
Started Apr 16 01:03:22 PM PDT 24
Finished Apr 16 01:03:32 PM PDT 24
Peak memory 203984 kb
Host smart-3e22b4ad-adde-4fc6-91dc-e0f848afc15e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=743979310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.743979310
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.2684609378
Short name T996
Test name
Test status
Simulation time 8389534496 ps
CPU time 8.91 seconds
Started Apr 16 01:03:20 PM PDT 24
Finished Apr 16 01:03:30 PM PDT 24
Peak memory 203976 kb
Host smart-5006407c-348e-4935-9002-aac13c8fb436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26846
09378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.2684609378
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2129307002
Short name T592
Test name
Test status
Simulation time 8380073006 ps
CPU time 8.02 seconds
Started Apr 16 01:03:18 PM PDT 24
Finished Apr 16 01:03:27 PM PDT 24
Peak memory 203988 kb
Host smart-a6c02932-ecd5-497b-9384-5fecedf416f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21293
07002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2129307002
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_enable.297677756
Short name T707
Test name
Test status
Simulation time 8400465159 ps
CPU time 7.63 seconds
Started Apr 16 01:03:23 PM PDT 24
Finished Apr 16 01:03:32 PM PDT 24
Peak memory 204040 kb
Host smart-8f7b6a8b-1ea6-44bd-9d42-caabd62301e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29767
7756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.297677756
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.924649849
Short name T637
Test name
Test status
Simulation time 146625759 ps
CPU time 1.49 seconds
Started Apr 16 01:03:20 PM PDT 24
Finished Apr 16 01:03:23 PM PDT 24
Peak memory 204152 kb
Host smart-487a4a96-c7bf-4a98-84ce-93c8e80729b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92464
9849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.924649849
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.3097882755
Short name T141
Test name
Test status
Simulation time 8407935279 ps
CPU time 7.96 seconds
Started Apr 16 01:03:19 PM PDT 24
Finished Apr 16 01:03:28 PM PDT 24
Peak memory 204032 kb
Host smart-a6d6c27f-ebf0-45c2-b5e3-e8000e9de238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30978
82755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.3097882755
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.3434676809
Short name T595
Test name
Test status
Simulation time 8370016783 ps
CPU time 7.61 seconds
Started Apr 16 01:03:21 PM PDT 24
Finished Apr 16 01:03:30 PM PDT 24
Peak memory 203968 kb
Host smart-395e348f-dfc0-43c8-92d0-71682abbd3d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34346
76809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.3434676809
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.819078671
Short name T805
Test name
Test status
Simulation time 8402001611 ps
CPU time 7.72 seconds
Started Apr 16 01:03:20 PM PDT 24
Finished Apr 16 01:03:29 PM PDT 24
Peak memory 204260 kb
Host smart-1a0746e4-52da-4264-b6a2-dabc55a0b090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81907
8671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.819078671
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.2845594498
Short name T1322
Test name
Test status
Simulation time 8456749103 ps
CPU time 7.95 seconds
Started Apr 16 01:03:27 PM PDT 24
Finished Apr 16 01:03:36 PM PDT 24
Peak memory 204048 kb
Host smart-94768e50-11aa-4728-bbd5-5a12886fc781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28455
94498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.2845594498
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.350500243
Short name T1290
Test name
Test status
Simulation time 8387570940 ps
CPU time 7.72 seconds
Started Apr 16 01:03:27 PM PDT 24
Finished Apr 16 01:03:36 PM PDT 24
Peak memory 204040 kb
Host smart-cb43618b-d867-4345-9422-33768b04dd5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35050
0243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.350500243
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.2655994404
Short name T108
Test name
Test status
Simulation time 8402498665 ps
CPU time 7.97 seconds
Started Apr 16 01:03:21 PM PDT 24
Finished Apr 16 01:03:31 PM PDT 24
Peak memory 204032 kb
Host smart-0db7b108-beb4-42b6-aa29-5480a80c9426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26559
94404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.2655994404
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.3960549681
Short name T292
Test name
Test status
Simulation time 8425164468 ps
CPU time 7.62 seconds
Started Apr 16 01:03:21 PM PDT 24
Finished Apr 16 01:03:30 PM PDT 24
Peak memory 203944 kb
Host smart-074ac4d8-74eb-4b5e-80c8-5fa34b7148a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39605
49681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.3960549681
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3331140267
Short name T309
Test name
Test status
Simulation time 8410297099 ps
CPU time 7.83 seconds
Started Apr 16 01:03:22 PM PDT 24
Finished Apr 16 01:03:31 PM PDT 24
Peak memory 204000 kb
Host smart-f27841f5-a593-4b34-a537-fc15370127cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33311
40267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3331140267
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.720506284
Short name T1025
Test name
Test status
Simulation time 8411017660 ps
CPU time 8.06 seconds
Started Apr 16 01:03:23 PM PDT 24
Finished Apr 16 01:03:32 PM PDT 24
Peak memory 203996 kb
Host smart-9c7368c8-993d-403e-8931-6d4c54a99fee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72050
6284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.720506284
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.2807770987
Short name T666
Test name
Test status
Simulation time 8367727310 ps
CPU time 8.74 seconds
Started Apr 16 01:03:18 PM PDT 24
Finished Apr 16 01:03:28 PM PDT 24
Peak memory 203992 kb
Host smart-34f313ba-eccc-4f35-b443-79da91be3888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28077
70987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.2807770987
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.2056399047
Short name T1286
Test name
Test status
Simulation time 59873264 ps
CPU time 0.65 seconds
Started Apr 16 01:03:21 PM PDT 24
Finished Apr 16 01:03:23 PM PDT 24
Peak memory 203884 kb
Host smart-376d17ac-776d-4bdf-ad27-97cf490b5b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20563
99047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.2056399047
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.2194320573
Short name T832
Test name
Test status
Simulation time 20446295423 ps
CPU time 39.55 seconds
Started Apr 16 01:03:18 PM PDT 24
Finished Apr 16 01:03:59 PM PDT 24
Peak memory 204296 kb
Host smart-7351102a-980b-41d9-9bb6-53db963278fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21943
20573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.2194320573
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.3912788703
Short name T1132
Test name
Test status
Simulation time 8448229465 ps
CPU time 7.66 seconds
Started Apr 16 01:03:19 PM PDT 24
Finished Apr 16 01:03:28 PM PDT 24
Peak memory 204036 kb
Host smart-6ae2c4ac-ef56-4062-8cc1-af06d8f68dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39127
88703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.3912788703
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.3346182802
Short name T752
Test name
Test status
Simulation time 8377401770 ps
CPU time 10.03 seconds
Started Apr 16 01:03:19 PM PDT 24
Finished Apr 16 01:03:30 PM PDT 24
Peak memory 204048 kb
Host smart-bacbcbca-9824-4c56-9f91-fd04978bd810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33461
82802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3346182802
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.1030608659
Short name T902
Test name
Test status
Simulation time 8388533952 ps
CPU time 9.37 seconds
Started Apr 16 01:03:20 PM PDT 24
Finished Apr 16 01:03:30 PM PDT 24
Peak memory 203988 kb
Host smart-d5016b3b-62bc-4d1e-87d0-d61700200e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10306
08659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.1030608659
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.1267316763
Short name T735
Test name
Test status
Simulation time 8378996992 ps
CPU time 8.17 seconds
Started Apr 16 01:03:27 PM PDT 24
Finished Apr 16 01:03:36 PM PDT 24
Peak memory 204044 kb
Host smart-7862636d-3383-447c-b311-f5f8b0e35f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12673
16763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.1267316763
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.3078291995
Short name T378
Test name
Test status
Simulation time 8370764808 ps
CPU time 8.63 seconds
Started Apr 16 01:03:24 PM PDT 24
Finished Apr 16 01:03:34 PM PDT 24
Peak memory 204016 kb
Host smart-f1bf2ea2-a279-439c-8ac0-3ad461465147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30782
91995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.3078291995
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.399128908
Short name T1134
Test name
Test status
Simulation time 8472046424 ps
CPU time 7.67 seconds
Started Apr 16 01:03:17 PM PDT 24
Finished Apr 16 01:03:26 PM PDT 24
Peak memory 203980 kb
Host smart-9f43d612-8076-4b0d-85c9-80c71a6f309f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39912
8908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.399128908
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.2246770270
Short name T1148
Test name
Test status
Simulation time 8390980902 ps
CPU time 10.5 seconds
Started Apr 16 01:03:21 PM PDT 24
Finished Apr 16 01:03:32 PM PDT 24
Peak memory 204020 kb
Host smart-80eadef2-b82c-4949-aef9-6cb86ebd9b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22467
70270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.2246770270
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.4071051452
Short name T1305
Test name
Test status
Simulation time 8415805653 ps
CPU time 7.54 seconds
Started Apr 16 01:03:27 PM PDT 24
Finished Apr 16 01:03:36 PM PDT 24
Peak memory 204040 kb
Host smart-c30c12ef-22df-48da-b5e1-a8ce24f89f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40710
51452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.4071051452
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.2754509040
Short name T548
Test name
Test status
Simulation time 8460876255 ps
CPU time 8.34 seconds
Started Apr 16 01:03:26 PM PDT 24
Finished Apr 16 01:03:36 PM PDT 24
Peak memory 204056 kb
Host smart-24c90010-2920-418a-a1de-8848b86130be
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2754509040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.2754509040
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.3810000273
Short name T1010
Test name
Test status
Simulation time 8382800565 ps
CPU time 7.68 seconds
Started Apr 16 01:03:30 PM PDT 24
Finished Apr 16 01:03:38 PM PDT 24
Peak memory 203956 kb
Host smart-d707fb3b-3e49-4a16-913e-f073fe82e7e4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3810000273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.3810000273
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.3718931261
Short name T928
Test name
Test status
Simulation time 8381792583 ps
CPU time 10.03 seconds
Started Apr 16 01:03:25 PM PDT 24
Finished Apr 16 01:03:36 PM PDT 24
Peak memory 204012 kb
Host smart-b17edd2e-f4a2-46bb-b27f-2e32969d6056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37189
31261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.3718931261
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.1166308299
Short name T1122
Test name
Test status
Simulation time 8429406825 ps
CPU time 9.69 seconds
Started Apr 16 01:03:24 PM PDT 24
Finished Apr 16 01:03:35 PM PDT 24
Peak memory 204020 kb
Host smart-d5b4eea3-dde4-4e37-afbb-27fc9c8f453a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11663
08299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.1166308299
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_enable.3082460347
Short name T1161
Test name
Test status
Simulation time 8376321368 ps
CPU time 7.78 seconds
Started Apr 16 01:03:19 PM PDT 24
Finished Apr 16 01:03:28 PM PDT 24
Peak memory 203908 kb
Host smart-e1599414-4fcc-4868-9d89-d2b67b226df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30824
60347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.3082460347
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.813464269
Short name T1248
Test name
Test status
Simulation time 192798066 ps
CPU time 1.62 seconds
Started Apr 16 01:03:20 PM PDT 24
Finished Apr 16 01:03:23 PM PDT 24
Peak memory 204076 kb
Host smart-2970040a-3b68-4531-9bfc-8e6ce49f65b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81346
4269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.813464269
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1542930973
Short name T625
Test name
Test status
Simulation time 8417938937 ps
CPU time 8.03 seconds
Started Apr 16 01:03:28 PM PDT 24
Finished Apr 16 01:03:37 PM PDT 24
Peak memory 204044 kb
Host smart-f9c2a133-3cfb-45a3-9595-279727224600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15429
30973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1542930973
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.1131453489
Short name T176
Test name
Test status
Simulation time 8369636907 ps
CPU time 7.43 seconds
Started Apr 16 01:03:29 PM PDT 24
Finished Apr 16 01:03:37 PM PDT 24
Peak memory 204044 kb
Host smart-ea29485c-0ed4-42e1-9276-b41382957ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11314
53489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.1131453489
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.1847506757
Short name T126
Test name
Test status
Simulation time 8439507219 ps
CPU time 8.32 seconds
Started Apr 16 01:03:20 PM PDT 24
Finished Apr 16 01:03:29 PM PDT 24
Peak memory 204048 kb
Host smart-383d0472-a0eb-4eb4-8e4b-9ec85fca61e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18475
06757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.1847506757
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.2764552887
Short name T865
Test name
Test status
Simulation time 8415472667 ps
CPU time 8.62 seconds
Started Apr 16 01:03:18 PM PDT 24
Finished Apr 16 01:03:28 PM PDT 24
Peak memory 204052 kb
Host smart-7ef74bbc-2390-4728-831e-5b25883497c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27645
52887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.2764552887
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.712622931
Short name T663
Test name
Test status
Simulation time 8371961877 ps
CPU time 7.69 seconds
Started Apr 16 01:03:30 PM PDT 24
Finished Apr 16 01:03:39 PM PDT 24
Peak memory 203964 kb
Host smart-d6ab4f41-e9a0-403d-b64b-12efb5eab42f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71262
2931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.712622931
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.3982293075
Short name T1331
Test name
Test status
Simulation time 8431757620 ps
CPU time 7.76 seconds
Started Apr 16 01:03:25 PM PDT 24
Finished Apr 16 01:03:34 PM PDT 24
Peak memory 204048 kb
Host smart-dde11836-9468-4efc-8702-b6e7d00b1b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39822
93075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.3982293075
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.251531876
Short name T831
Test name
Test status
Simulation time 8370840890 ps
CPU time 8.64 seconds
Started Apr 16 01:03:24 PM PDT 24
Finished Apr 16 01:03:33 PM PDT 24
Peak memory 204024 kb
Host smart-5d4febed-4c1a-49a3-a8e0-0a2a28696d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25153
1876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.251531876
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.340437098
Short name T1329
Test name
Test status
Simulation time 8396826198 ps
CPU time 8.7 seconds
Started Apr 16 01:03:25 PM PDT 24
Finished Apr 16 01:03:34 PM PDT 24
Peak memory 203980 kb
Host smart-36bbf56a-58ae-474f-950c-b365df0ad88e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34043
7098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.340437098
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.1890040456
Short name T1292
Test name
Test status
Simulation time 8387895180 ps
CPU time 9.42 seconds
Started Apr 16 01:03:30 PM PDT 24
Finished Apr 16 01:03:40 PM PDT 24
Peak memory 203960 kb
Host smart-9d154004-623c-4a26-8d9e-de55b9af2931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18900
40456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.1890040456
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.4119572350
Short name T811
Test name
Test status
Simulation time 61159847 ps
CPU time 0.68 seconds
Started Apr 16 01:03:24 PM PDT 24
Finished Apr 16 01:03:26 PM PDT 24
Peak memory 203856 kb
Host smart-c07a6790-d932-4137-92b4-df7caff09e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41195
72350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.4119572350
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.3272478418
Short name T589
Test name
Test status
Simulation time 19639970894 ps
CPU time 37.06 seconds
Started Apr 16 01:03:25 PM PDT 24
Finished Apr 16 01:04:03 PM PDT 24
Peak memory 204368 kb
Host smart-7656d307-733e-473d-9a57-797c4f2e581a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32724
78418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.3272478418
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.3239140839
Short name T682
Test name
Test status
Simulation time 8425499171 ps
CPU time 8 seconds
Started Apr 16 01:03:26 PM PDT 24
Finished Apr 16 01:03:35 PM PDT 24
Peak memory 204016 kb
Host smart-974963de-56c6-4119-8b17-1ec493354be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32391
40839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.3239140839
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.1768927179
Short name T1208
Test name
Test status
Simulation time 8420919766 ps
CPU time 8.9 seconds
Started Apr 16 01:03:25 PM PDT 24
Finished Apr 16 01:03:35 PM PDT 24
Peak memory 203948 kb
Host smart-00bc0bc1-9563-4e5e-9418-ea82b2251fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17689
27179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1768927179
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.2090480009
Short name T1029
Test name
Test status
Simulation time 8391718499 ps
CPU time 7.68 seconds
Started Apr 16 01:03:25 PM PDT 24
Finished Apr 16 01:03:34 PM PDT 24
Peak memory 204016 kb
Host smart-c2064218-dba4-4cce-9772-2ac876590b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20904
80009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.2090480009
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.1969270379
Short name T1349
Test name
Test status
Simulation time 8376345311 ps
CPU time 8.05 seconds
Started Apr 16 01:03:27 PM PDT 24
Finished Apr 16 01:03:36 PM PDT 24
Peak memory 203976 kb
Host smart-a8fd7175-8c92-4954-9ae1-a22bce13d69c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19692
70379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.1969270379
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1966593849
Short name T966
Test name
Test status
Simulation time 8377957569 ps
CPU time 9.14 seconds
Started Apr 16 01:03:26 PM PDT 24
Finished Apr 16 01:03:36 PM PDT 24
Peak memory 203940 kb
Host smart-1e120a97-066a-49f9-aaf0-0633573ac494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19665
93849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1966593849
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.882098816
Short name T761
Test name
Test status
Simulation time 8435728754 ps
CPU time 8.09 seconds
Started Apr 16 01:03:27 PM PDT 24
Finished Apr 16 01:03:37 PM PDT 24
Peak memory 203992 kb
Host smart-1b534907-66e1-4ebd-9b9a-a59a55a1b413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88209
8816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.882098816
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2004371556
Short name T1176
Test name
Test status
Simulation time 8406848015 ps
CPU time 8.68 seconds
Started Apr 16 01:03:25 PM PDT 24
Finished Apr 16 01:03:35 PM PDT 24
Peak memory 203940 kb
Host smart-a854d8c5-5a4c-41bd-876e-091490677b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20043
71556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2004371556
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.272320562
Short name T886
Test name
Test status
Simulation time 8469628309 ps
CPU time 9.44 seconds
Started Apr 16 01:03:32 PM PDT 24
Finished Apr 16 01:03:42 PM PDT 24
Peak memory 203984 kb
Host smart-c10faad2-2188-41df-8a67-87383ee0f4fc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=272320562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.272320562
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.3366552967
Short name T1317
Test name
Test status
Simulation time 8383739670 ps
CPU time 8.28 seconds
Started Apr 16 01:03:35 PM PDT 24
Finished Apr 16 01:03:45 PM PDT 24
Peak memory 203964 kb
Host smart-c862d63a-c8c1-43cd-9712-9af9d2512236
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3366552967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.3366552967
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.2156224277
Short name T1210
Test name
Test status
Simulation time 8436130810 ps
CPU time 8.25 seconds
Started Apr 16 01:03:35 PM PDT 24
Finished Apr 16 01:03:44 PM PDT 24
Peak memory 203964 kb
Host smart-6e722038-8237-4cdb-b072-e812dc321626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21562
24277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.2156224277
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.572039884
Short name T327
Test name
Test status
Simulation time 8388803488 ps
CPU time 7.9 seconds
Started Apr 16 01:03:27 PM PDT 24
Finished Apr 16 01:03:36 PM PDT 24
Peak memory 204024 kb
Host smart-dd67885d-ed6a-4900-96ea-0587d6dd9288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57203
9884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.572039884
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_enable.4125721738
Short name T442
Test name
Test status
Simulation time 8429250896 ps
CPU time 8.27 seconds
Started Apr 16 01:03:26 PM PDT 24
Finished Apr 16 01:03:36 PM PDT 24
Peak memory 204024 kb
Host smart-1479ff9f-4f27-46fa-8e31-8f987ea7a249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41257
21738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.4125721738
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.292059735
Short name T600
Test name
Test status
Simulation time 171365220 ps
CPU time 1.82 seconds
Started Apr 16 01:03:25 PM PDT 24
Finished Apr 16 01:03:28 PM PDT 24
Peak memory 204012 kb
Host smart-d335bf16-cdfc-4465-9042-714c3b136077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29205
9735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.292059735
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.3552473641
Short name T988
Test name
Test status
Simulation time 8467664622 ps
CPU time 7.78 seconds
Started Apr 16 01:03:29 PM PDT 24
Finished Apr 16 01:03:37 PM PDT 24
Peak memory 203984 kb
Host smart-1f850e3d-ec7d-42c8-b969-827350b25031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35524
73641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.3552473641
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.3134187215
Short name T184
Test name
Test status
Simulation time 8381093512 ps
CPU time 10.45 seconds
Started Apr 16 01:03:38 PM PDT 24
Finished Apr 16 01:03:49 PM PDT 24
Peak memory 204000 kb
Host smart-eba36ccb-85ec-4bbd-b837-ad95462b83df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31341
87215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.3134187215
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.3710963824
Short name T499
Test name
Test status
Simulation time 8450608906 ps
CPU time 8.25 seconds
Started Apr 16 01:03:24 PM PDT 24
Finished Apr 16 01:03:33 PM PDT 24
Peak memory 204048 kb
Host smart-0f887ff8-6e92-4d2d-9b74-0d967c98f569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37109
63824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.3710963824
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.2765848407
Short name T1231
Test name
Test status
Simulation time 8414975141 ps
CPU time 8.24 seconds
Started Apr 16 01:03:36 PM PDT 24
Finished Apr 16 01:03:46 PM PDT 24
Peak memory 204020 kb
Host smart-715a329f-384b-4e53-9041-373a9e876fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27658
48407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.2765848407
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3276560760
Short name T418
Test name
Test status
Simulation time 8382608585 ps
CPU time 8.06 seconds
Started Apr 16 01:03:31 PM PDT 24
Finished Apr 16 01:03:40 PM PDT 24
Peak memory 204040 kb
Host smart-1c4406af-a9a3-462a-8bc7-2129e325a16b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32765
60760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3276560760
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.1800688372
Short name T101
Test name
Test status
Simulation time 8420966943 ps
CPU time 7.72 seconds
Started Apr 16 01:03:30 PM PDT 24
Finished Apr 16 01:03:39 PM PDT 24
Peak memory 204048 kb
Host smart-d4011720-065d-431b-b7f3-18d8fff20a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18006
88372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.1800688372
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.3178807139
Short name T1310
Test name
Test status
Simulation time 8388466813 ps
CPU time 8.51 seconds
Started Apr 16 01:03:30 PM PDT 24
Finished Apr 16 01:03:39 PM PDT 24
Peak memory 204024 kb
Host smart-a57c436f-465f-47a8-8992-31c031533021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31788
07139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.3178807139
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.3089106753
Short name T898
Test name
Test status
Simulation time 8403040699 ps
CPU time 8.91 seconds
Started Apr 16 01:03:31 PM PDT 24
Finished Apr 16 01:03:41 PM PDT 24
Peak memory 204028 kb
Host smart-161fc0e0-0d59-4af8-b7f0-f2c3d47f98b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30891
06753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.3089106753
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.4187586388
Short name T769
Test name
Test status
Simulation time 8447114785 ps
CPU time 9.07 seconds
Started Apr 16 01:03:29 PM PDT 24
Finished Apr 16 01:03:39 PM PDT 24
Peak memory 204048 kb
Host smart-4169d01c-126e-4b36-9a24-0b40c7c7b3cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41875
86388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.4187586388
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.2114024948
Short name T1167
Test name
Test status
Simulation time 8369896266 ps
CPU time 8.08 seconds
Started Apr 16 01:03:36 PM PDT 24
Finished Apr 16 01:03:46 PM PDT 24
Peak memory 204016 kb
Host smart-faa5ac39-a808-421e-ad52-f82f4cb0b0cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21140
24948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.2114024948
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.1482298408
Short name T1068
Test name
Test status
Simulation time 66232711 ps
CPU time 0.7 seconds
Started Apr 16 01:03:30 PM PDT 24
Finished Apr 16 01:03:32 PM PDT 24
Peak memory 203900 kb
Host smart-c5e725c8-fd38-4b87-a1a1-e446a68ae377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14822
98408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.1482298408
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.3086523816
Short name T901
Test name
Test status
Simulation time 15478553285 ps
CPU time 24.81 seconds
Started Apr 16 01:03:33 PM PDT 24
Finished Apr 16 01:03:59 PM PDT 24
Peak memory 204280 kb
Host smart-7a7f4f8b-a411-41c4-8926-42c211bd414d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30865
23816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.3086523816
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.506642786
Short name T848
Test name
Test status
Simulation time 8385747779 ps
CPU time 7.83 seconds
Started Apr 16 01:03:31 PM PDT 24
Finished Apr 16 01:03:40 PM PDT 24
Peak memory 203872 kb
Host smart-cb7f5e61-fbea-4c4c-ad7b-0531aa7f0bb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50664
2786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.506642786
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.1914907645
Short name T782
Test name
Test status
Simulation time 8437411670 ps
CPU time 8.53 seconds
Started Apr 16 01:03:30 PM PDT 24
Finished Apr 16 01:03:39 PM PDT 24
Peak memory 203940 kb
Host smart-26247724-99d7-48eb-8462-20c9b8ad4dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19149
07645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.1914907645
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.36079843
Short name T358
Test name
Test status
Simulation time 8378398456 ps
CPU time 9.52 seconds
Started Apr 16 01:03:30 PM PDT 24
Finished Apr 16 01:03:41 PM PDT 24
Peak memory 204048 kb
Host smart-5986532d-fa74-422b-8c3e-eb9360ad55ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36079
843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.36079843
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.6325632
Short name T85
Test name
Test status
Simulation time 8383714762 ps
CPU time 10.26 seconds
Started Apr 16 01:03:32 PM PDT 24
Finished Apr 16 01:03:43 PM PDT 24
Peak memory 203928 kb
Host smart-c76389fd-3245-4fdd-93b2-7e5793196e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63256
32 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.6325632
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2956893357
Short name T2
Test name
Test status
Simulation time 8369739429 ps
CPU time 7.85 seconds
Started Apr 16 01:03:29 PM PDT 24
Finished Apr 16 01:03:38 PM PDT 24
Peak memory 204032 kb
Host smart-d59049cf-275c-4617-ba2a-1f135b75dc9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29568
93357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2956893357
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3358347014
Short name T1351
Test name
Test status
Simulation time 8458262486 ps
CPU time 7.73 seconds
Started Apr 16 01:03:25 PM PDT 24
Finished Apr 16 01:03:34 PM PDT 24
Peak memory 204032 kb
Host smart-8e3a7075-b80d-4565-961b-1947301091c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33583
47014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3358347014
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.2071314735
Short name T900
Test name
Test status
Simulation time 8461385003 ps
CPU time 8.32 seconds
Started Apr 16 01:03:34 PM PDT 24
Finished Apr 16 01:03:43 PM PDT 24
Peak memory 204260 kb
Host smart-ee72a9f2-e8f9-4725-b20e-9ceede70f02f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20713
14735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.2071314735
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.2470031299
Short name T638
Test name
Test status
Simulation time 8405807840 ps
CPU time 10.04 seconds
Started Apr 16 01:03:32 PM PDT 24
Finished Apr 16 01:03:43 PM PDT 24
Peak memory 204084 kb
Host smart-6f1b28da-5b05-4ceb-a86b-9fc2b27b1803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24700
31299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.2470031299
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.max_length_in_transaction.431248719
Short name T491
Test name
Test status
Simulation time 8473549756 ps
CPU time 8.83 seconds
Started Apr 16 01:03:37 PM PDT 24
Finished Apr 16 01:03:47 PM PDT 24
Peak memory 204016 kb
Host smart-34469948-d993-4d9b-9ed4-b6c53e404d87
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=431248719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.431248719
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.1356708606
Short name T346
Test name
Test status
Simulation time 8394835788 ps
CPU time 10.14 seconds
Started Apr 16 01:03:36 PM PDT 24
Finished Apr 16 01:03:48 PM PDT 24
Peak memory 203976 kb
Host smart-9ffb1c02-c9d9-486a-8e59-c3fea3d2f7f4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1356708606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.1356708606
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.1993768117
Short name T498
Test name
Test status
Simulation time 8397762815 ps
CPU time 10.1 seconds
Started Apr 16 01:03:36 PM PDT 24
Finished Apr 16 01:03:48 PM PDT 24
Peak memory 204040 kb
Host smart-d502f881-2cbd-409c-8c77-6a27c33b5d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19937
68117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.1993768117
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3289381164
Short name T1165
Test name
Test status
Simulation time 8375801909 ps
CPU time 7.68 seconds
Started Apr 16 01:03:36 PM PDT 24
Finished Apr 16 01:03:45 PM PDT 24
Peak memory 203964 kb
Host smart-e3bf42ca-1b4b-42b0-9f8a-3a4049dd09eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32893
81164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3289381164
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_enable.2869094268
Short name T413
Test name
Test status
Simulation time 8444508037 ps
CPU time 8.46 seconds
Started Apr 16 01:03:35 PM PDT 24
Finished Apr 16 01:03:46 PM PDT 24
Peak memory 203980 kb
Host smart-9ef0dc12-c576-4818-b506-049827138e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28690
94268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.2869094268
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2642174762
Short name T384
Test name
Test status
Simulation time 303755718 ps
CPU time 2.21 seconds
Started Apr 16 01:03:30 PM PDT 24
Finished Apr 16 01:03:33 PM PDT 24
Peak memory 204112 kb
Host smart-c03a0576-83ce-41b2-9de7-8d85488cdd3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26421
74762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2642174762
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.118091380
Short name T54
Test name
Test status
Simulation time 8445093951 ps
CPU time 8.29 seconds
Started Apr 16 01:03:35 PM PDT 24
Finished Apr 16 01:03:45 PM PDT 24
Peak memory 204044 kb
Host smart-7f265774-4728-452c-8867-3f1cf75f5130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11809
1380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.118091380
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.2515804565
Short name T182
Test name
Test status
Simulation time 8413655364 ps
CPU time 8.47 seconds
Started Apr 16 01:03:35 PM PDT 24
Finished Apr 16 01:03:45 PM PDT 24
Peak memory 204012 kb
Host smart-4abab296-0d80-4978-8bfa-c45134f099de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25158
04565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.2515804565
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.3778327306
Short name T147
Test name
Test status
Simulation time 8444834378 ps
CPU time 7.49 seconds
Started Apr 16 01:03:36 PM PDT 24
Finished Apr 16 01:03:45 PM PDT 24
Peak memory 204020 kb
Host smart-a5f5cf43-8d06-4a00-97b7-6a614b735791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37783
27306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3778327306
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.3195395876
Short name T799
Test name
Test status
Simulation time 8437000290 ps
CPU time 7.82 seconds
Started Apr 16 01:03:31 PM PDT 24
Finished Apr 16 01:03:40 PM PDT 24
Peak memory 204028 kb
Host smart-7acbd460-ced6-47d0-ae8e-0b3b95596847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31953
95876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.3195395876
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.1418141782
Short name T555
Test name
Test status
Simulation time 8382506027 ps
CPU time 7.87 seconds
Started Apr 16 01:03:31 PM PDT 24
Finished Apr 16 01:03:40 PM PDT 24
Peak memory 204016 kb
Host smart-afc0b1ab-d647-42b0-845b-ed35bba5336a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14181
41782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.1418141782
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.2161579858
Short name T1236
Test name
Test status
Simulation time 8419638639 ps
CPU time 8.73 seconds
Started Apr 16 01:03:32 PM PDT 24
Finished Apr 16 01:03:42 PM PDT 24
Peak memory 203928 kb
Host smart-5225e053-7019-4178-a982-53833cbf29f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21615
79858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.2161579858
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.433028843
Short name T1268
Test name
Test status
Simulation time 8419576274 ps
CPU time 7.93 seconds
Started Apr 16 01:03:31 PM PDT 24
Finished Apr 16 01:03:40 PM PDT 24
Peak memory 204016 kb
Host smart-4cde4713-1f90-4188-a03b-c8e3b016a0fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43302
8843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.433028843
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.1848048003
Short name T1050
Test name
Test status
Simulation time 8445660017 ps
CPU time 7.98 seconds
Started Apr 16 01:03:35 PM PDT 24
Finished Apr 16 01:03:45 PM PDT 24
Peak memory 203988 kb
Host smart-7c6f055a-bdf8-4c33-b513-2da2ea250cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18480
48003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.1848048003
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.4051134809
Short name T641
Test name
Test status
Simulation time 8401034194 ps
CPU time 7.54 seconds
Started Apr 16 01:03:35 PM PDT 24
Finished Apr 16 01:03:43 PM PDT 24
Peak memory 204028 kb
Host smart-55eb2e5d-7e81-4254-bf30-c7fa98712a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40511
34809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.4051134809
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.1798755415
Short name T3
Test name
Test status
Simulation time 8373928926 ps
CPU time 7.95 seconds
Started Apr 16 01:03:37 PM PDT 24
Finished Apr 16 01:03:46 PM PDT 24
Peak memory 203896 kb
Host smart-93bacd10-b8f3-48a4-b55b-2ff69f941701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17987
55415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.1798755415
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.2157443517
Short name T975
Test name
Test status
Simulation time 51801032 ps
CPU time 0.65 seconds
Started Apr 16 01:03:35 PM PDT 24
Finished Apr 16 01:03:38 PM PDT 24
Peak memory 203900 kb
Host smart-f329d415-4c26-4e67-994a-edd36e5a1bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21574
43517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.2157443517
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.4126656180
Short name T1306
Test name
Test status
Simulation time 26448755901 ps
CPU time 48.02 seconds
Started Apr 16 01:03:31 PM PDT 24
Finished Apr 16 01:04:20 PM PDT 24
Peak memory 204164 kb
Host smart-59731a24-8a96-4979-acd9-eb17f13946a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41266
56180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.4126656180
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.278985165
Short name T1207
Test name
Test status
Simulation time 8410549964 ps
CPU time 7.83 seconds
Started Apr 16 01:03:36 PM PDT 24
Finished Apr 16 01:03:45 PM PDT 24
Peak memory 203976 kb
Host smart-c484f3a1-6645-40bd-a0bd-8e7c2cccdfc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27898
5165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.278985165
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.975838888
Short name T808
Test name
Test status
Simulation time 8461186838 ps
CPU time 10.23 seconds
Started Apr 16 01:03:38 PM PDT 24
Finished Apr 16 01:03:49 PM PDT 24
Peak memory 204260 kb
Host smart-1d176d56-1264-47b8-8056-c6a642c87103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97583
8888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.975838888
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.559739759
Short name T1345
Test name
Test status
Simulation time 8424696038 ps
CPU time 7.93 seconds
Started Apr 16 01:03:38 PM PDT 24
Finished Apr 16 01:03:47 PM PDT 24
Peak memory 204260 kb
Host smart-d49a05c3-db39-4a1f-937a-2b67c7b5ba63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55973
9759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.559739759
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.3740974904
Short name T708
Test name
Test status
Simulation time 8411638605 ps
CPU time 7.69 seconds
Started Apr 16 01:03:36 PM PDT 24
Finished Apr 16 01:03:45 PM PDT 24
Peak memory 204044 kb
Host smart-dcfc8f96-4839-46c9-8451-0d66eb5fb2b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37409
74904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.3740974904
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.3244924674
Short name T339
Test name
Test status
Simulation time 8364519038 ps
CPU time 7.91 seconds
Started Apr 16 01:03:35 PM PDT 24
Finished Apr 16 01:03:44 PM PDT 24
Peak memory 204020 kb
Host smart-2d62bab7-8f18-4c42-a291-79a55eb0eac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32449
24674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.3244924674
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.295926253
Short name T837
Test name
Test status
Simulation time 8466393104 ps
CPU time 10.19 seconds
Started Apr 16 01:03:36 PM PDT 24
Finished Apr 16 01:03:47 PM PDT 24
Peak memory 204028 kb
Host smart-b57306b1-a03a-49c1-91b0-df4e63858b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29592
6253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.295926253
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.1973004823
Short name T970
Test name
Test status
Simulation time 8384230548 ps
CPU time 10.25 seconds
Started Apr 16 01:03:36 PM PDT 24
Finished Apr 16 01:03:48 PM PDT 24
Peak memory 203984 kb
Host smart-e07b60d1-a061-44df-acc3-035b75d9e416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19730
04823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.1973004823
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.1010796395
Short name T1016
Test name
Test status
Simulation time 8393164048 ps
CPU time 9.74 seconds
Started Apr 16 01:03:35 PM PDT 24
Finished Apr 16 01:03:45 PM PDT 24
Peak memory 204024 kb
Host smart-c41f98f3-117e-41c7-b62b-cb2f20c70045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10107
96395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.1010796395
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.max_length_in_transaction.3054410299
Short name T1230
Test name
Test status
Simulation time 8464898491 ps
CPU time 7.72 seconds
Started Apr 16 01:03:48 PM PDT 24
Finished Apr 16 01:03:58 PM PDT 24
Peak memory 204056 kb
Host smart-a96c2dd1-48f4-40a7-99c9-ffa198c3d49f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3054410299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.3054410299
Directory /workspace/25.max_length_in_transaction/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.63695889
Short name T770
Test name
Test status
Simulation time 8392923008 ps
CPU time 8.01 seconds
Started Apr 16 01:03:43 PM PDT 24
Finished Apr 16 01:03:52 PM PDT 24
Peak memory 204056 kb
Host smart-eb877355-11cd-47f5-9d51-ab58ca9ab232
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=63695889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.63695889
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.572215702
Short name T1376
Test name
Test status
Simulation time 8409485321 ps
CPU time 7.83 seconds
Started Apr 16 01:03:42 PM PDT 24
Finished Apr 16 01:03:51 PM PDT 24
Peak memory 204024 kb
Host smart-d9959195-07ed-4b32-935e-2a12a2c5a50f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57221
5702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.572215702
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.889754687
Short name T465
Test name
Test status
Simulation time 8374778324 ps
CPU time 10.04 seconds
Started Apr 16 01:03:37 PM PDT 24
Finished Apr 16 01:03:48 PM PDT 24
Peak memory 203936 kb
Host smart-49a3c382-d86c-4b11-8981-fdc9ac7ba3b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88975
4687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.889754687
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_enable.2466676685
Short name T591
Test name
Test status
Simulation time 8375042002 ps
CPU time 9.1 seconds
Started Apr 16 01:03:36 PM PDT 24
Finished Apr 16 01:03:47 PM PDT 24
Peak memory 204020 kb
Host smart-e6d8aa0c-b53d-4a6a-8f8e-b4429b2d4609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24666
76685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.2466676685
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.3489616787
Short name T366
Test name
Test status
Simulation time 137482378 ps
CPU time 1.61 seconds
Started Apr 16 01:03:41 PM PDT 24
Finished Apr 16 01:03:43 PM PDT 24
Peak memory 204176 kb
Host smart-2b9764fe-d173-49ad-bdc7-b8aad3969ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34896
16787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.3489616787
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.2249447429
Short name T729
Test name
Test status
Simulation time 8385089958 ps
CPU time 8 seconds
Started Apr 16 01:03:43 PM PDT 24
Finished Apr 16 01:03:52 PM PDT 24
Peak memory 203976 kb
Host smart-94ad1133-3102-49e0-9448-a04e8b5f0a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22494
47429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.2249447429
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.2162317502
Short name T814
Test name
Test status
Simulation time 8368856845 ps
CPU time 7.89 seconds
Started Apr 16 01:03:41 PM PDT 24
Finished Apr 16 01:03:50 PM PDT 24
Peak memory 204008 kb
Host smart-613c43b1-37b6-40e8-a674-52fa450f8b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21623
17502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.2162317502
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.1444578964
Short name T1296
Test name
Test status
Simulation time 8400846391 ps
CPU time 8.36 seconds
Started Apr 16 01:03:33 PM PDT 24
Finished Apr 16 01:03:42 PM PDT 24
Peak memory 204004 kb
Host smart-abf7543e-23aa-417d-a483-e668544c5dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14445
78964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.1444578964
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1635958309
Short name T557
Test name
Test status
Simulation time 8426136167 ps
CPU time 8.72 seconds
Started Apr 16 01:03:37 PM PDT 24
Finished Apr 16 01:03:47 PM PDT 24
Peak memory 204032 kb
Host smart-88bca5dc-abbe-4c83-a686-109549b729e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16359
58309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1635958309
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.157481855
Short name T764
Test name
Test status
Simulation time 8380271407 ps
CPU time 7.97 seconds
Started Apr 16 01:03:36 PM PDT 24
Finished Apr 16 01:03:46 PM PDT 24
Peak memory 204012 kb
Host smart-e014d200-d5ad-40b7-bf00-a8a7d7d68f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15748
1855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.157481855
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1977096485
Short name T118
Test name
Test status
Simulation time 8414540276 ps
CPU time 7.79 seconds
Started Apr 16 01:03:35 PM PDT 24
Finished Apr 16 01:03:45 PM PDT 24
Peak memory 203996 kb
Host smart-3754bd77-dc84-45c9-90b1-8c15c17db94a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19770
96485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1977096485
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.889359071
Short name T750
Test name
Test status
Simulation time 8393689345 ps
CPU time 8.46 seconds
Started Apr 16 01:03:36 PM PDT 24
Finished Apr 16 01:03:46 PM PDT 24
Peak memory 204028 kb
Host smart-862913ff-c0f7-4db5-9f8e-34cbe4440841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88935
9071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.889359071
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.2314631355
Short name T1061
Test name
Test status
Simulation time 8398181863 ps
CPU time 10.17 seconds
Started Apr 16 01:03:41 PM PDT 24
Finished Apr 16 01:03:53 PM PDT 24
Peak memory 203920 kb
Host smart-b733ba88-e8e2-43a7-9a67-24100476bc8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23146
31355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.2314631355
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.929238655
Short name T181
Test name
Test status
Simulation time 8405513115 ps
CPU time 7.78 seconds
Started Apr 16 01:03:45 PM PDT 24
Finished Apr 16 01:03:54 PM PDT 24
Peak memory 203944 kb
Host smart-3f7035be-efdd-4849-a465-f4aaf90ef5f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92923
8655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.929238655
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.1844623453
Short name T371
Test name
Test status
Simulation time 8379126574 ps
CPU time 7.83 seconds
Started Apr 16 01:03:40 PM PDT 24
Finished Apr 16 01:03:49 PM PDT 24
Peak memory 204036 kb
Host smart-a55d4139-78ca-4f39-908b-9a03301874a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18446
23453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.1844623453
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.3848613362
Short name T843
Test name
Test status
Simulation time 33765115 ps
CPU time 0.64 seconds
Started Apr 16 01:03:42 PM PDT 24
Finished Apr 16 01:03:44 PM PDT 24
Peak memory 203920 kb
Host smart-8e834b4b-155b-41f4-bd6e-c7d39b158993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38486
13362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.3848613362
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.1670666353
Short name T840
Test name
Test status
Simulation time 24483935568 ps
CPU time 46.14 seconds
Started Apr 16 01:03:42 PM PDT 24
Finished Apr 16 01:04:29 PM PDT 24
Peak memory 204296 kb
Host smart-de3de65b-69e6-494a-ba28-9da7c926225a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16706
66353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.1670666353
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.2889380106
Short name T860
Test name
Test status
Simulation time 8458336941 ps
CPU time 8.19 seconds
Started Apr 16 01:03:41 PM PDT 24
Finished Apr 16 01:03:50 PM PDT 24
Peak memory 203980 kb
Host smart-5f442008-dd69-48ae-ae95-681ba5a4e072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28893
80106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.2889380106
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.3284807504
Short name T1049
Test name
Test status
Simulation time 8461368280 ps
CPU time 10.03 seconds
Started Apr 16 01:03:40 PM PDT 24
Finished Apr 16 01:03:51 PM PDT 24
Peak memory 204028 kb
Host smart-ef017eb7-50f2-4562-aad1-246bec8331a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32848
07504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.3284807504
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.563147638
Short name T295
Test name
Test status
Simulation time 8429841683 ps
CPU time 8.62 seconds
Started Apr 16 01:03:41 PM PDT 24
Finished Apr 16 01:03:51 PM PDT 24
Peak memory 204016 kb
Host smart-a0751a70-1f9a-4275-86cf-090e9400b640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56314
7638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.563147638
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.3469949493
Short name T1072
Test name
Test status
Simulation time 8404671325 ps
CPU time 7.99 seconds
Started Apr 16 01:03:40 PM PDT 24
Finished Apr 16 01:03:49 PM PDT 24
Peak memory 204012 kb
Host smart-953ad068-f453-4ed2-9d75-29ae77c2d7e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34699
49493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.3469949493
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.1630193904
Short name T1156
Test name
Test status
Simulation time 8374346168 ps
CPU time 7.61 seconds
Started Apr 16 01:03:41 PM PDT 24
Finished Apr 16 01:03:50 PM PDT 24
Peak memory 204032 kb
Host smart-6bf1d820-7f31-4ba6-a329-8478d6a71933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16301
93904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.1630193904
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.3321781260
Short name T972
Test name
Test status
Simulation time 8463833873 ps
CPU time 7.84 seconds
Started Apr 16 01:03:36 PM PDT 24
Finished Apr 16 01:03:45 PM PDT 24
Peak memory 204004 kb
Host smart-673f9a8e-61a5-419f-b570-f0705b545322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33217
81260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.3321781260
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3506244947
Short name T866
Test name
Test status
Simulation time 8402467427 ps
CPU time 9.99 seconds
Started Apr 16 01:03:42 PM PDT 24
Finished Apr 16 01:03:53 PM PDT 24
Peak memory 203956 kb
Host smart-8de2a228-fd9b-4d8e-beb4-6aea8dd66257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35062
44947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3506244947
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.2430307162
Short name T721
Test name
Test status
Simulation time 8391116639 ps
CPU time 8.86 seconds
Started Apr 16 01:03:41 PM PDT 24
Finished Apr 16 01:03:51 PM PDT 24
Peak memory 203988 kb
Host smart-2b805ab5-1f95-452e-b7fe-b40781d6f309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24303
07162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.2430307162
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.max_length_in_transaction.3631324268
Short name T990
Test name
Test status
Simulation time 8479183661 ps
CPU time 7.88 seconds
Started Apr 16 01:03:50 PM PDT 24
Finished Apr 16 01:03:59 PM PDT 24
Peak memory 204032 kb
Host smart-d6eb11f7-0688-456b-946f-fd6c83bbd09f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3631324268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.3631324268
Directory /workspace/26.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.4254346803
Short name T864
Test name
Test status
Simulation time 8385371847 ps
CPU time 8.25 seconds
Started Apr 16 01:03:52 PM PDT 24
Finished Apr 16 01:04:02 PM PDT 24
Peak memory 203968 kb
Host smart-b18cbb1c-aa60-4835-b8f9-d203a1e67a9e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4254346803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.4254346803
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.773798471
Short name T607
Test name
Test status
Simulation time 8433326706 ps
CPU time 8.11 seconds
Started Apr 16 01:03:52 PM PDT 24
Finished Apr 16 01:04:01 PM PDT 24
Peak memory 204036 kb
Host smart-eac8cea2-2dd9-410b-abc9-d440c590874b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77379
8471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.773798471
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.2288473566
Short name T821
Test name
Test status
Simulation time 8391841281 ps
CPU time 9.15 seconds
Started Apr 16 01:03:49 PM PDT 24
Finished Apr 16 01:04:00 PM PDT 24
Peak memory 203984 kb
Host smart-78bf9cc8-bac4-4705-b50b-02f99c2a69ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22884
73566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.2288473566
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_enable.2182169135
Short name T1225
Test name
Test status
Simulation time 8390773693 ps
CPU time 7.92 seconds
Started Apr 16 01:03:46 PM PDT 24
Finished Apr 16 01:03:56 PM PDT 24
Peak memory 204016 kb
Host smart-c523b669-91ed-49cc-b8fd-e2f952b54ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21821
69135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.2182169135
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.1460646187
Short name T1201
Test name
Test status
Simulation time 329936969 ps
CPU time 2.34 seconds
Started Apr 16 01:03:49 PM PDT 24
Finished Apr 16 01:03:53 PM PDT 24
Peak memory 204152 kb
Host smart-4ed1b8d3-f73f-4a96-9398-ace6a1c318fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14606
46187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.1460646187
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.3752226527
Short name T1186
Test name
Test status
Simulation time 8478787559 ps
CPU time 9.21 seconds
Started Apr 16 01:03:51 PM PDT 24
Finished Apr 16 01:04:01 PM PDT 24
Peak memory 204028 kb
Host smart-9f054ee9-f19e-4c74-afd5-90ca067caa16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37522
26527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.3752226527
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.1843956866
Short name T1011
Test name
Test status
Simulation time 8389460254 ps
CPU time 10.02 seconds
Started Apr 16 01:03:55 PM PDT 24
Finished Apr 16 01:04:06 PM PDT 24
Peak memory 204020 kb
Host smart-827dcd48-3ceb-47d0-8e98-93ab3ef3d1ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18439
56866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1843956866
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.382767627
Short name T880
Test name
Test status
Simulation time 8460966637 ps
CPU time 7.94 seconds
Started Apr 16 01:03:48 PM PDT 24
Finished Apr 16 01:03:57 PM PDT 24
Peak memory 204024 kb
Host smart-b48cb473-9dff-4afe-aedc-d7ffcd663f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38276
7627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.382767627
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3387207775
Short name T396
Test name
Test status
Simulation time 8418449213 ps
CPU time 9.27 seconds
Started Apr 16 01:03:50 PM PDT 24
Finished Apr 16 01:04:01 PM PDT 24
Peak memory 204068 kb
Host smart-4d8d3ee4-6ca8-42ca-a3c3-74135a0f0583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33872
07775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3387207775
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2024097237
Short name T992
Test name
Test status
Simulation time 8366320993 ps
CPU time 7.91 seconds
Started Apr 16 01:03:45 PM PDT 24
Finished Apr 16 01:03:54 PM PDT 24
Peak memory 203996 kb
Host smart-5f5a11f0-79dc-48fe-91d6-35356be7a865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20240
97237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2024097237
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.4126293706
Short name T1277
Test name
Test status
Simulation time 8417194824 ps
CPU time 7.99 seconds
Started Apr 16 01:03:47 PM PDT 24
Finished Apr 16 01:03:57 PM PDT 24
Peak memory 204016 kb
Host smart-a901e8e4-e33a-4dae-aaa6-9bce75f73110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41262
93706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.4126293706
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.349335967
Short name T1078
Test name
Test status
Simulation time 8402167809 ps
CPU time 9.91 seconds
Started Apr 16 01:03:44 PM PDT 24
Finished Apr 16 01:03:56 PM PDT 24
Peak memory 204052 kb
Host smart-fe4e280a-cf0a-405e-98dd-604817dab85c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34933
5967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.349335967
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.1714420844
Short name T710
Test name
Test status
Simulation time 8412478335 ps
CPU time 8.42 seconds
Started Apr 16 01:03:59 PM PDT 24
Finished Apr 16 01:04:08 PM PDT 24
Peak memory 203980 kb
Host smart-8fec7275-5743-42bb-a6f3-f53ee9ed956e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17144
20844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.1714420844
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.1357745187
Short name T933
Test name
Test status
Simulation time 8370319404 ps
CPU time 8.97 seconds
Started Apr 16 01:03:55 PM PDT 24
Finished Apr 16 01:04:04 PM PDT 24
Peak memory 204028 kb
Host smart-f85fd62d-d452-40b5-a9f7-5d8e4999d2c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13577
45187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.1357745187
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1912875447
Short name T856
Test name
Test status
Simulation time 42149747 ps
CPU time 0.67 seconds
Started Apr 16 01:03:52 PM PDT 24
Finished Apr 16 01:03:54 PM PDT 24
Peak memory 203884 kb
Host smart-df5da339-9189-4b7d-961c-ea26887120e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19128
75447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1912875447
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3042537863
Short name T238
Test name
Test status
Simulation time 15638637609 ps
CPU time 27.96 seconds
Started Apr 16 01:03:45 PM PDT 24
Finished Apr 16 01:04:14 PM PDT 24
Peak memory 204320 kb
Host smart-61916d7e-2ae8-4935-8863-039972f7cc10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30425
37863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3042537863
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.2358521244
Short name T1031
Test name
Test status
Simulation time 8403364113 ps
CPU time 8.39 seconds
Started Apr 16 01:03:48 PM PDT 24
Finished Apr 16 01:03:58 PM PDT 24
Peak memory 204028 kb
Host smart-d3e89911-f76c-464f-a09e-fc0f6a0c2965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23585
21244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.2358521244
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.1400231707
Short name T128
Test name
Test status
Simulation time 8438867284 ps
CPU time 8.58 seconds
Started Apr 16 01:03:47 PM PDT 24
Finished Apr 16 01:03:58 PM PDT 24
Peak memory 203908 kb
Host smart-874cb00a-4c5e-4f8c-92d8-cfb88a3bb14f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14002
31707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1400231707
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.45720622
Short name T838
Test name
Test status
Simulation time 8401778458 ps
CPU time 8.21 seconds
Started Apr 16 01:03:50 PM PDT 24
Finished Apr 16 01:04:00 PM PDT 24
Peak memory 204080 kb
Host smart-934a8e8d-0fd4-438b-9582-3a01756f0565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45720
622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.45720622
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.2747604223
Short name T885
Test name
Test status
Simulation time 8379299401 ps
CPU time 7.69 seconds
Started Apr 16 01:03:53 PM PDT 24
Finished Apr 16 01:04:02 PM PDT 24
Peak memory 204028 kb
Host smart-5d304497-f91d-4097-8146-4e93f3de9ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27476
04223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.2747604223
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.1690854752
Short name T1046
Test name
Test status
Simulation time 8366358018 ps
CPU time 8.63 seconds
Started Apr 16 01:03:51 PM PDT 24
Finished Apr 16 01:04:01 PM PDT 24
Peak memory 204080 kb
Host smart-6acf0f29-f153-4ce1-93ca-12504828883e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16908
54752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.1690854752
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.861800407
Short name T1293
Test name
Test status
Simulation time 8451191096 ps
CPU time 10.22 seconds
Started Apr 16 01:03:50 PM PDT 24
Finished Apr 16 01:04:02 PM PDT 24
Peak memory 203948 kb
Host smart-51e7b741-f8b5-414c-8eed-cac63723d5bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86180
0407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.861800407
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1979797369
Short name T993
Test name
Test status
Simulation time 8399252491 ps
CPU time 9.37 seconds
Started Apr 16 01:03:52 PM PDT 24
Finished Apr 16 01:04:03 PM PDT 24
Peak memory 203976 kb
Host smart-ec58b5d8-a245-41db-a663-062adb857057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19797
97369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.1979797369
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.1809837929
Short name T451
Test name
Test status
Simulation time 8419776449 ps
CPU time 8.35 seconds
Started Apr 16 01:03:53 PM PDT 24
Finished Apr 16 01:04:03 PM PDT 24
Peak memory 204032 kb
Host smart-94c8c206-fc56-472b-b127-b19fb2fb67f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18098
37929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.1809837929
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.3522659227
Short name T817
Test name
Test status
Simulation time 8470951473 ps
CPU time 7.82 seconds
Started Apr 16 01:04:02 PM PDT 24
Finished Apr 16 01:04:11 PM PDT 24
Peak memory 203984 kb
Host smart-7c911bb1-604e-4d9f-8a56-b92abdcf1e79
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3522659227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.3522659227
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.669764374
Short name T788
Test name
Test status
Simulation time 8383121439 ps
CPU time 8.14 seconds
Started Apr 16 01:03:57 PM PDT 24
Finished Apr 16 01:04:06 PM PDT 24
Peak memory 203984 kb
Host smart-fd6309e5-8af9-491e-a719-dde14575583e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=669764374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.669764374
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.161679267
Short name T1006
Test name
Test status
Simulation time 8412382185 ps
CPU time 9.04 seconds
Started Apr 16 01:04:02 PM PDT 24
Finished Apr 16 01:04:12 PM PDT 24
Peak memory 203976 kb
Host smart-6cca8a7b-7d09-4fb1-82cc-b9c99035f195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16167
9267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.161679267
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.384914038
Short name T867
Test name
Test status
Simulation time 8383517231 ps
CPU time 7.8 seconds
Started Apr 16 01:03:52 PM PDT 24
Finished Apr 16 01:04:02 PM PDT 24
Peak memory 204024 kb
Host smart-601d950a-540d-468a-8947-76dd123171d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38491
4038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.384914038
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_enable.3508304363
Short name T648
Test name
Test status
Simulation time 8392701686 ps
CPU time 7.72 seconds
Started Apr 16 01:03:51 PM PDT 24
Finished Apr 16 01:03:59 PM PDT 24
Peak memory 203988 kb
Host smart-1e5e5f7e-d9a8-4a28-818f-198bb4584e2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35083
04363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.3508304363
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.2925894225
Short name T731
Test name
Test status
Simulation time 193317300 ps
CPU time 1.54 seconds
Started Apr 16 01:03:52 PM PDT 24
Finished Apr 16 01:03:54 PM PDT 24
Peak memory 204172 kb
Host smart-ebeb67d1-9050-412b-95db-3ec21a5c47eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29258
94225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2925894225
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.1932833529
Short name T1044
Test name
Test status
Simulation time 8463455483 ps
CPU time 10.12 seconds
Started Apr 16 01:04:02 PM PDT 24
Finished Apr 16 01:04:14 PM PDT 24
Peak memory 203984 kb
Host smart-e79447af-86a4-4f71-9383-ed4ab2cc6256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19328
33529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.1932833529
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.3265242931
Short name T197
Test name
Test status
Simulation time 8418004135 ps
CPU time 7.5 seconds
Started Apr 16 01:03:55 PM PDT 24
Finished Apr 16 01:04:03 PM PDT 24
Peak memory 203936 kb
Host smart-72e07f22-7291-4d7e-918a-ba022b86b882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32652
42931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.3265242931
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.3817867185
Short name T415
Test name
Test status
Simulation time 8417498798 ps
CPU time 7.74 seconds
Started Apr 16 01:03:50 PM PDT 24
Finished Apr 16 01:03:59 PM PDT 24
Peak memory 204048 kb
Host smart-4ddf5301-18b4-4f2b-952e-5d4898a10469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38178
67185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.3817867185
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.3790102024
Short name T606
Test name
Test status
Simulation time 8420243551 ps
CPU time 10.57 seconds
Started Apr 16 01:03:51 PM PDT 24
Finished Apr 16 01:04:03 PM PDT 24
Peak memory 204032 kb
Host smart-97a69127-342e-4786-a390-bab7b36f007b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37901
02024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.3790102024
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.4220935454
Short name T306
Test name
Test status
Simulation time 8438326269 ps
CPU time 8.72 seconds
Started Apr 16 01:03:54 PM PDT 24
Finished Apr 16 01:04:03 PM PDT 24
Peak memory 203976 kb
Host smart-1d0eba4f-7b9e-4414-a82d-fc45f5ee3314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42209
35454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.4220935454
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1888008879
Short name T1102
Test name
Test status
Simulation time 8463487399 ps
CPU time 9.09 seconds
Started Apr 16 01:03:58 PM PDT 24
Finished Apr 16 01:04:08 PM PDT 24
Peak memory 204024 kb
Host smart-499edade-6d13-4b2b-a180-48a13dd493e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18880
08879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1888008879
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.4144689281
Short name T995
Test name
Test status
Simulation time 8388882842 ps
CPU time 7.77 seconds
Started Apr 16 01:03:58 PM PDT 24
Finished Apr 16 01:04:07 PM PDT 24
Peak memory 204028 kb
Host smart-9a717d12-59dc-4404-8fd4-b56ad3dfc364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41446
89281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.4144689281
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.2582687381
Short name T1034
Test name
Test status
Simulation time 8399243387 ps
CPU time 10.27 seconds
Started Apr 16 01:03:56 PM PDT 24
Finished Apr 16 01:04:07 PM PDT 24
Peak memory 203908 kb
Host smart-3fcb8279-bb4a-4101-9a47-f962ce2e065f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25826
87381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.2582687381
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3112809639
Short name T390
Test name
Test status
Simulation time 65727032 ps
CPU time 0.65 seconds
Started Apr 16 01:03:54 PM PDT 24
Finished Apr 16 01:03:56 PM PDT 24
Peak memory 203876 kb
Host smart-48d9d0ce-e84a-43b0-bb35-acbab16837e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31128
09639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3112809639
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.3553785100
Short name T746
Test name
Test status
Simulation time 28465224321 ps
CPU time 53.27 seconds
Started Apr 16 01:03:56 PM PDT 24
Finished Apr 16 01:04:50 PM PDT 24
Peak memory 204256 kb
Host smart-5b436307-9c4e-4a4b-991c-7438434bbc35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35537
85100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.3553785100
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.3749658081
Short name T332
Test name
Test status
Simulation time 8422784149 ps
CPU time 9.28 seconds
Started Apr 16 01:03:56 PM PDT 24
Finished Apr 16 01:04:06 PM PDT 24
Peak memory 203996 kb
Host smart-a7c48c5f-d77c-4d4b-9851-3d814b1bb031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37496
58081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3749658081
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3670132030
Short name T760
Test name
Test status
Simulation time 8474371104 ps
CPU time 8.33 seconds
Started Apr 16 01:03:55 PM PDT 24
Finished Apr 16 01:04:04 PM PDT 24
Peak memory 204036 kb
Host smart-b378f8a5-fdda-4ffe-88c1-757b01e100a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36701
32030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3670132030
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.4256440503
Short name T1372
Test name
Test status
Simulation time 8438041518 ps
CPU time 10.08 seconds
Started Apr 16 01:03:57 PM PDT 24
Finished Apr 16 01:04:08 PM PDT 24
Peak memory 203952 kb
Host smart-7affb57a-5d9a-444e-a6c6-ab35b4652bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42564
40503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.4256440503
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.493582934
Short name T989
Test name
Test status
Simulation time 8393074758 ps
CPU time 8.46 seconds
Started Apr 16 01:03:56 PM PDT 24
Finished Apr 16 01:04:06 PM PDT 24
Peak memory 204044 kb
Host smart-f2395c41-f78e-497f-8e9c-87a5cc7f19fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49358
2934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.493582934
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.2274190016
Short name T569
Test name
Test status
Simulation time 8371669431 ps
CPU time 9.2 seconds
Started Apr 16 01:03:57 PM PDT 24
Finished Apr 16 01:04:07 PM PDT 24
Peak memory 203940 kb
Host smart-060d1290-92e6-4973-9698-3b5cff0fb56d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22741
90016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.2274190016
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.831897946
Short name T1179
Test name
Test status
Simulation time 8506792471 ps
CPU time 8.02 seconds
Started Apr 16 01:03:53 PM PDT 24
Finished Apr 16 01:04:02 PM PDT 24
Peak memory 204044 kb
Host smart-783cf772-1e83-4157-bdad-64d6cdccb683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83189
7946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.831897946
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.2632267724
Short name T852
Test name
Test status
Simulation time 8413090267 ps
CPU time 8.15 seconds
Started Apr 16 01:03:56 PM PDT 24
Finished Apr 16 01:04:05 PM PDT 24
Peak memory 204028 kb
Host smart-859d7084-c724-4dfe-8d73-654aaf036b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26322
67724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.2632267724
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.3811040515
Short name T341
Test name
Test status
Simulation time 8405343410 ps
CPU time 7.91 seconds
Started Apr 16 01:03:57 PM PDT 24
Finished Apr 16 01:04:06 PM PDT 24
Peak memory 204044 kb
Host smart-63b5f2b0-df2b-4434-9f3c-bbc50ab03e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38110
40515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.3811040515
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.3748075494
Short name T47
Test name
Test status
Simulation time 8533987994 ps
CPU time 9.19 seconds
Started Apr 16 01:04:03 PM PDT 24
Finished Apr 16 01:04:13 PM PDT 24
Peak memory 204020 kb
Host smart-a65631ff-38b0-44d1-9f3c-21c73d007a6f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3748075494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.3748075494
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.1868512176
Short name T706
Test name
Test status
Simulation time 8392770982 ps
CPU time 7.88 seconds
Started Apr 16 01:04:02 PM PDT 24
Finished Apr 16 01:04:11 PM PDT 24
Peak memory 204032 kb
Host smart-9f2c7cd3-ae44-4724-8de4-07016ce60fff
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1868512176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.1868512176
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.2766986670
Short name T482
Test name
Test status
Simulation time 8398863952 ps
CPU time 8.65 seconds
Started Apr 16 01:04:02 PM PDT 24
Finished Apr 16 01:04:12 PM PDT 24
Peak memory 203944 kb
Host smart-15ceeb34-d5b3-4a7d-93ea-2b6412551c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27669
86670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.2766986670
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.292976883
Short name T574
Test name
Test status
Simulation time 8388554165 ps
CPU time 7.92 seconds
Started Apr 16 01:03:55 PM PDT 24
Finished Apr 16 01:04:04 PM PDT 24
Peak memory 203984 kb
Host smart-88349e60-e97b-474a-923f-6550d1d6d93a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29297
6883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.292976883
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_enable.3078534935
Short name T716
Test name
Test status
Simulation time 8375274893 ps
CPU time 7.54 seconds
Started Apr 16 01:03:58 PM PDT 24
Finished Apr 16 01:04:06 PM PDT 24
Peak memory 203976 kb
Host smart-a97a0485-3b18-499e-8230-dc1fa4a31637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30785
34935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3078534935
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.3267376965
Short name T590
Test name
Test status
Simulation time 82756664 ps
CPU time 1.69 seconds
Started Apr 16 01:03:55 PM PDT 24
Finished Apr 16 01:03:57 PM PDT 24
Peak memory 204160 kb
Host smart-97182e83-dbe0-4b08-b0ae-34c486741eda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32673
76965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.3267376965
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.3096165866
Short name T1021
Test name
Test status
Simulation time 8459442825 ps
CPU time 8.13 seconds
Started Apr 16 01:04:05 PM PDT 24
Finished Apr 16 01:04:14 PM PDT 24
Peak memory 204048 kb
Host smart-1be21ccc-c399-41c6-bf19-295905204f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30961
65866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.3096165866
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.1857133841
Short name T1324
Test name
Test status
Simulation time 8374037654 ps
CPU time 7.66 seconds
Started Apr 16 01:04:02 PM PDT 24
Finished Apr 16 01:04:10 PM PDT 24
Peak memory 203896 kb
Host smart-4c9d4578-3596-4119-84dd-8aa25e3c6a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18571
33841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.1857133841
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.4182288347
Short name T1355
Test name
Test status
Simulation time 8461119611 ps
CPU time 7.87 seconds
Started Apr 16 01:04:00 PM PDT 24
Finished Apr 16 01:04:09 PM PDT 24
Peak memory 203984 kb
Host smart-2b620004-bd97-4ca0-824c-8291156cc905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41822
88347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.4182288347
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.1889597294
Short name T1003
Test name
Test status
Simulation time 8414535789 ps
CPU time 9.12 seconds
Started Apr 16 01:03:57 PM PDT 24
Finished Apr 16 01:04:07 PM PDT 24
Peak memory 203984 kb
Host smart-cf7de590-cba3-4724-8832-e6cae30d1e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18895
97294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.1889597294
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.1211559854
Short name T337
Test name
Test status
Simulation time 8367750163 ps
CPU time 7.69 seconds
Started Apr 16 01:03:56 PM PDT 24
Finished Apr 16 01:04:04 PM PDT 24
Peak memory 204012 kb
Host smart-a3c0c374-74db-434a-9cf3-9bbf34306756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12115
59854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.1211559854
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.1958986333
Short name T30
Test name
Test status
Simulation time 8429599990 ps
CPU time 9.03 seconds
Started Apr 16 01:03:56 PM PDT 24
Finished Apr 16 01:04:06 PM PDT 24
Peak memory 203976 kb
Host smart-de3f4481-36a0-402d-8582-66748b8a74d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19589
86333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.1958986333
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3118980914
Short name T908
Test name
Test status
Simulation time 8398488247 ps
CPU time 9.89 seconds
Started Apr 16 01:04:00 PM PDT 24
Finished Apr 16 01:04:10 PM PDT 24
Peak memory 204048 kb
Host smart-33b44363-7eb6-427a-9a01-77c648446ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31189
80914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3118980914
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2395120667
Short name T1142
Test name
Test status
Simulation time 8470440367 ps
CPU time 8.5 seconds
Started Apr 16 01:04:01 PM PDT 24
Finished Apr 16 01:04:11 PM PDT 24
Peak memory 203980 kb
Host smart-15fd17d2-85c3-4a61-9e24-85ef693c5998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23951
20667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2395120667
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1643720637
Short name T161
Test name
Test status
Simulation time 8409640130 ps
CPU time 8.83 seconds
Started Apr 16 01:04:00 PM PDT 24
Finished Apr 16 01:04:10 PM PDT 24
Peak memory 204020 kb
Host smart-fa834ccc-cbde-48fd-8708-ee247177ce87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16437
20637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1643720637
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.1094380362
Short name T26
Test name
Test status
Simulation time 8370431277 ps
CPU time 8.92 seconds
Started Apr 16 01:04:05 PM PDT 24
Finished Apr 16 01:04:15 PM PDT 24
Peak memory 203924 kb
Host smart-f02e4f63-b3d9-4f7f-852b-af1bcc1ea89f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10943
80362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1094380362
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.4078337390
Short name T792
Test name
Test status
Simulation time 81899074 ps
CPU time 0.69 seconds
Started Apr 16 01:04:02 PM PDT 24
Finished Apr 16 01:04:04 PM PDT 24
Peak memory 203852 kb
Host smart-0c1df89e-9e4b-42dd-8594-e9609646edb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40783
37390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.4078337390
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.3897648035
Short name T254
Test name
Test status
Simulation time 23277955263 ps
CPU time 44.07 seconds
Started Apr 16 01:04:00 PM PDT 24
Finished Apr 16 01:04:45 PM PDT 24
Peak memory 204272 kb
Host smart-a1c105d2-124f-4489-83e6-625e24699dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38976
48035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.3897648035
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.3654435818
Short name T89
Test name
Test status
Simulation time 8392287792 ps
CPU time 9.92 seconds
Started Apr 16 01:04:02 PM PDT 24
Finished Apr 16 01:04:13 PM PDT 24
Peak memory 203976 kb
Host smart-23e2d836-1485-416f-8208-2d16a73098e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36544
35818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.3654435818
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.1726581541
Short name T379
Test name
Test status
Simulation time 8479812273 ps
CPU time 7.7 seconds
Started Apr 16 01:03:58 PM PDT 24
Finished Apr 16 01:04:06 PM PDT 24
Peak memory 203980 kb
Host smart-23bec312-9d9f-40aa-852a-f67db7daa8e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17265
81541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.1726581541
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.4019000002
Short name T1110
Test name
Test status
Simulation time 8388910536 ps
CPU time 7.68 seconds
Started Apr 16 01:04:00 PM PDT 24
Finished Apr 16 01:04:08 PM PDT 24
Peak memory 203988 kb
Host smart-ae7b8a53-8914-41f0-8d2d-4d92a5832f8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40190
00002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.4019000002
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.1633062651
Short name T1115
Test name
Test status
Simulation time 8372414178 ps
CPU time 8.31 seconds
Started Apr 16 01:04:06 PM PDT 24
Finished Apr 16 01:04:15 PM PDT 24
Peak memory 203948 kb
Host smart-804a53d7-c194-4e68-9f74-f4e8f4d499c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16330
62651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.1633062651
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.2397376970
Short name T288
Test name
Test status
Simulation time 8373289958 ps
CPU time 9.38 seconds
Started Apr 16 01:03:58 PM PDT 24
Finished Apr 16 01:04:08 PM PDT 24
Peak memory 203936 kb
Host smart-60bfcb3e-bd75-4f44-b6de-eabe2415bfb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23973
76970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.2397376970
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3603898973
Short name T1241
Test name
Test status
Simulation time 8425484927 ps
CPU time 8.15 seconds
Started Apr 16 01:03:56 PM PDT 24
Finished Apr 16 01:04:05 PM PDT 24
Peak memory 204020 kb
Host smart-5bc8567f-6166-441e-88ce-92e87f589b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36038
98973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3603898973
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.3937149651
Short name T497
Test name
Test status
Simulation time 8376779141 ps
CPU time 9.67 seconds
Started Apr 16 01:04:05 PM PDT 24
Finished Apr 16 01:04:16 PM PDT 24
Peak memory 203924 kb
Host smart-fe0247e5-fd43-4258-abf8-c22aa50a9012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39371
49651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.3937149651
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.1027377427
Short name T399
Test name
Test status
Simulation time 8385408956 ps
CPU time 7.65 seconds
Started Apr 16 01:03:57 PM PDT 24
Finished Apr 16 01:04:05 PM PDT 24
Peak memory 204008 kb
Host smart-f073d4ba-b4ac-4797-921e-fb2dea74ca11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10273
77427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.1027377427
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.3597299682
Short name T412
Test name
Test status
Simulation time 8463598734 ps
CPU time 8.26 seconds
Started Apr 16 01:04:07 PM PDT 24
Finished Apr 16 01:04:16 PM PDT 24
Peak memory 203992 kb
Host smart-94833e84-fe68-41d3-b487-e42315446780
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3597299682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.3597299682
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.3292868155
Short name T16
Test name
Test status
Simulation time 8376693297 ps
CPU time 8.97 seconds
Started Apr 16 01:04:04 PM PDT 24
Finished Apr 16 01:04:14 PM PDT 24
Peak memory 204040 kb
Host smart-82cd093d-4c5f-4f3f-a677-a975f6b266a6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3292868155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.3292868155
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.2228514755
Short name T81
Test name
Test status
Simulation time 8397446770 ps
CPU time 8.39 seconds
Started Apr 16 01:04:06 PM PDT 24
Finished Apr 16 01:04:16 PM PDT 24
Peak memory 203924 kb
Host smart-ff4f4a87-0ecb-4859-887c-aafb7344d080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22285
14755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.2228514755
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.3660505790
Short name T330
Test name
Test status
Simulation time 8385168418 ps
CPU time 8.2 seconds
Started Apr 16 01:04:07 PM PDT 24
Finished Apr 16 01:04:17 PM PDT 24
Peak memory 203964 kb
Host smart-603229fe-aa93-4aec-bbe5-b4ed1984cfda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36605
05790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.3660505790
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_enable.3177388218
Short name T695
Test name
Test status
Simulation time 8371399524 ps
CPU time 8.07 seconds
Started Apr 16 01:04:01 PM PDT 24
Finished Apr 16 01:04:10 PM PDT 24
Peak memory 204012 kb
Host smart-c66f387e-232f-4d05-a979-808f455e8da8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31773
88218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3177388218
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.2868473572
Short name T214
Test name
Test status
Simulation time 75543198 ps
CPU time 1.88 seconds
Started Apr 16 01:04:02 PM PDT 24
Finished Apr 16 01:04:05 PM PDT 24
Peak memory 203968 kb
Host smart-5207d024-0f6e-4471-b3dd-dac1c8b0b3e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28684
73572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.2868473572
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.1204520384
Short name T946
Test name
Test status
Simulation time 8392759835 ps
CPU time 8.02 seconds
Started Apr 16 01:04:00 PM PDT 24
Finished Apr 16 01:04:08 PM PDT 24
Peak memory 204048 kb
Host smart-fd7e60df-b4cd-4130-be03-2bf0ba918cd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12045
20384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.1204520384
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.274559373
Short name T1147
Test name
Test status
Simulation time 8364893586 ps
CPU time 7.51 seconds
Started Apr 16 01:04:07 PM PDT 24
Finished Apr 16 01:04:16 PM PDT 24
Peak memory 203968 kb
Host smart-2dc0302e-f49f-44b2-aabe-3468c4ff3a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27455
9373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.274559373
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.1538035250
Short name T137
Test name
Test status
Simulation time 8399978690 ps
CPU time 9.02 seconds
Started Apr 16 01:04:02 PM PDT 24
Finished Apr 16 01:04:12 PM PDT 24
Peak memory 203900 kb
Host smart-36c452ce-271c-4376-9376-9b1f8527dc1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15380
35250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.1538035250
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.3006701710
Short name T919
Test name
Test status
Simulation time 8439709398 ps
CPU time 7.69 seconds
Started Apr 16 01:04:00 PM PDT 24
Finished Apr 16 01:04:09 PM PDT 24
Peak memory 203932 kb
Host smart-ff73fc27-6362-4a26-bbfc-dd12154a24dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30067
01710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.3006701710
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.164339742
Short name T670
Test name
Test status
Simulation time 8376337987 ps
CPU time 8.93 seconds
Started Apr 16 01:04:00 PM PDT 24
Finished Apr 16 01:04:10 PM PDT 24
Peak memory 204024 kb
Host smart-077f6f29-5b0c-43d2-a5e5-b422b7cb570f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16433
9742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.164339742
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.424436118
Short name T461
Test name
Test status
Simulation time 8430113283 ps
CPU time 8.38 seconds
Started Apr 16 01:04:02 PM PDT 24
Finished Apr 16 01:04:11 PM PDT 24
Peak memory 204004 kb
Host smart-a5c346a5-12a0-4c6c-9569-f8bb4c0cb833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42443
6118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.424436118
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.3502112186
Short name T953
Test name
Test status
Simulation time 8426234731 ps
CPU time 9.21 seconds
Started Apr 16 01:03:59 PM PDT 24
Finished Apr 16 01:04:09 PM PDT 24
Peak memory 204032 kb
Host smart-56fcc54b-4a11-4182-ac92-9043236e12ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35021
12186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.3502112186
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.2223832504
Short name T763
Test name
Test status
Simulation time 8422773540 ps
CPU time 8.52 seconds
Started Apr 16 01:04:06 PM PDT 24
Finished Apr 16 01:04:16 PM PDT 24
Peak memory 203944 kb
Host smart-34c7e98c-efa7-4dab-83e7-92b926f3ea47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22238
32504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.2223832504
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.2099698471
Short name T824
Test name
Test status
Simulation time 8390712630 ps
CPU time 9.46 seconds
Started Apr 16 01:04:01 PM PDT 24
Finished Apr 16 01:04:11 PM PDT 24
Peak memory 204036 kb
Host smart-66b8debe-4053-4598-b370-e489202b100e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20996
98471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.2099698471
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.1384675276
Short name T342
Test name
Test status
Simulation time 8397942978 ps
CPU time 7.63 seconds
Started Apr 16 01:04:06 PM PDT 24
Finished Apr 16 01:04:15 PM PDT 24
Peak memory 203964 kb
Host smart-0e7aaa58-6a36-4b96-9439-961a10963c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13846
75276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.1384675276
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.832118077
Short name T431
Test name
Test status
Simulation time 79575768 ps
CPU time 0.77 seconds
Started Apr 16 01:04:06 PM PDT 24
Finished Apr 16 01:04:08 PM PDT 24
Peak memory 203816 kb
Host smart-dd9c9841-26a7-4d06-9625-13f822d41b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83211
8077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.832118077
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.7873058
Short name T1002
Test name
Test status
Simulation time 21415556654 ps
CPU time 39.71 seconds
Started Apr 16 01:04:06 PM PDT 24
Finished Apr 16 01:04:47 PM PDT 24
Peak memory 204248 kb
Host smart-04483a6e-37ab-4e2a-9b29-b3f6f4aaad46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78730
58 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.7873058
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.3881013522
Short name T1375
Test name
Test status
Simulation time 8398486562 ps
CPU time 10.22 seconds
Started Apr 16 01:04:00 PM PDT 24
Finished Apr 16 01:04:11 PM PDT 24
Peak memory 203968 kb
Host smart-6aa01596-f82b-4205-bca7-0e4a070d62ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38810
13522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.3881013522
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.123002664
Short name T870
Test name
Test status
Simulation time 8415677816 ps
CPU time 7.5 seconds
Started Apr 16 01:04:02 PM PDT 24
Finished Apr 16 01:04:10 PM PDT 24
Peak memory 204016 kb
Host smart-2d351262-8c7a-4df0-85c3-08f8c588f48d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12300
2664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.123002664
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.1886402494
Short name T615
Test name
Test status
Simulation time 8419578483 ps
CPU time 8.09 seconds
Started Apr 16 01:04:04 PM PDT 24
Finished Apr 16 01:04:13 PM PDT 24
Peak memory 203976 kb
Host smart-52af2888-18f9-4b0a-b0a6-c3136b0d21fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18864
02494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.1886402494
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.2892306951
Short name T756
Test name
Test status
Simulation time 8373876764 ps
CPU time 8.33 seconds
Started Apr 16 01:04:05 PM PDT 24
Finished Apr 16 01:04:14 PM PDT 24
Peak memory 204028 kb
Host smart-83aaca85-b75e-41f0-9c98-5709047ae328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28923
06951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.2892306951
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.207215498
Short name T1028
Test name
Test status
Simulation time 8373269146 ps
CPU time 9.32 seconds
Started Apr 16 01:04:04 PM PDT 24
Finished Apr 16 01:04:14 PM PDT 24
Peak memory 204012 kb
Host smart-178fe6d6-a658-4c98-99d0-32a7d701ea74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20721
5498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.207215498
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.302121630
Short name T816
Test name
Test status
Simulation time 8453210360 ps
CPU time 7.84 seconds
Started Apr 16 01:04:05 PM PDT 24
Finished Apr 16 01:04:14 PM PDT 24
Peak memory 203928 kb
Host smart-c082bb84-7483-49b9-a61c-43e5afe664f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30212
1630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.302121630
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.2799320012
Short name T322
Test name
Test status
Simulation time 8421977712 ps
CPU time 8.83 seconds
Started Apr 16 01:04:01 PM PDT 24
Finished Apr 16 01:04:11 PM PDT 24
Peak memory 204012 kb
Host smart-3533ba76-7a6a-4011-87a5-e3ea23d8c3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27993
20012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.2799320012
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.554200538
Short name T1042
Test name
Test status
Simulation time 8406762978 ps
CPU time 10.36 seconds
Started Apr 16 01:04:04 PM PDT 24
Finished Apr 16 01:04:15 PM PDT 24
Peak memory 203976 kb
Host smart-64a2b6cb-fbba-48b5-af7e-9a830ebecc3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55420
0538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.554200538
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.1655881606
Short name T1356
Test name
Test status
Simulation time 8471047490 ps
CPU time 7.76 seconds
Started Apr 16 01:01:29 PM PDT 24
Finished Apr 16 01:01:37 PM PDT 24
Peak memory 203984 kb
Host smart-b4a63d00-545a-43a6-97ab-d4912af67d42
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1655881606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.1655881606
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.2404390295
Short name T1265
Test name
Test status
Simulation time 8373866946 ps
CPU time 7.66 seconds
Started Apr 16 01:01:34 PM PDT 24
Finished Apr 16 01:01:42 PM PDT 24
Peak memory 203984 kb
Host smart-6e3eb128-4476-4d15-aa66-41edc4534ec8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2404390295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.2404390295
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.20033804
Short name T949
Test name
Test status
Simulation time 8435549847 ps
CPU time 8.68 seconds
Started Apr 16 01:01:32 PM PDT 24
Finished Apr 16 01:01:41 PM PDT 24
Peak memory 204016 kb
Host smart-00b8ccd9-9d5b-4fbd-882d-c74cdef216b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20033
804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.20033804
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.894155644
Short name T545
Test name
Test status
Simulation time 8383573544 ps
CPU time 8.26 seconds
Started Apr 16 01:01:22 PM PDT 24
Finished Apr 16 01:01:31 PM PDT 24
Peak memory 204028 kb
Host smart-f8551c61-7762-4297-8576-e36b762b2fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89415
5644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.894155644
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_enable.1749041941
Short name T10
Test name
Test status
Simulation time 8409869779 ps
CPU time 10.18 seconds
Started Apr 16 01:01:25 PM PDT 24
Finished Apr 16 01:01:36 PM PDT 24
Peak memory 204028 kb
Host smart-f57c74f1-66cf-44c0-97c0-0d68b60c46d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17490
41941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1749041941
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3680571728
Short name T588
Test name
Test status
Simulation time 55381790 ps
CPU time 1.32 seconds
Started Apr 16 01:01:23 PM PDT 24
Finished Apr 16 01:01:25 PM PDT 24
Peak memory 204116 kb
Host smart-cafa6bd3-35c2-48d5-b637-3bbfc5c16cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36805
71728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3680571728
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.267578293
Short name T665
Test name
Test status
Simulation time 8377146961 ps
CPU time 8.84 seconds
Started Apr 16 01:01:31 PM PDT 24
Finished Apr 16 01:01:40 PM PDT 24
Peak memory 203928 kb
Host smart-d5b7ad51-ca9c-4981-b471-f5eae48f766e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26757
8293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.267578293
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.2006834056
Short name T883
Test name
Test status
Simulation time 8408503791 ps
CPU time 8.34 seconds
Started Apr 16 01:01:26 PM PDT 24
Finished Apr 16 01:01:35 PM PDT 24
Peak memory 204012 kb
Host smart-26819502-0180-4870-b4d2-817d551f196b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20068
34056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.2006834056
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.3283971695
Short name T50
Test name
Test status
Simulation time 8470417126 ps
CPU time 7.77 seconds
Started Apr 16 01:01:23 PM PDT 24
Finished Apr 16 01:01:32 PM PDT 24
Peak memory 203984 kb
Host smart-898c29a0-b8aa-4903-acd7-6010e8ed06ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32839
71695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.3283971695
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1545344306
Short name T501
Test name
Test status
Simulation time 8415448774 ps
CPU time 9.14 seconds
Started Apr 16 01:01:25 PM PDT 24
Finished Apr 16 01:01:35 PM PDT 24
Peak memory 204024 kb
Host smart-490b02c3-e12b-4862-8a32-518daa975eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15453
44306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1545344306
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.1519479529
Short name T419
Test name
Test status
Simulation time 8375945385 ps
CPU time 7.69 seconds
Started Apr 16 01:01:36 PM PDT 24
Finished Apr 16 01:01:44 PM PDT 24
Peak memory 203928 kb
Host smart-a1e76bcf-9912-4a73-8638-712f5fd4f257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15194
79529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.1519479529
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.2433901758
Short name T99
Test name
Test status
Simulation time 8472702129 ps
CPU time 8.12 seconds
Started Apr 16 01:01:26 PM PDT 24
Finished Apr 16 01:01:35 PM PDT 24
Peak memory 204016 kb
Host smart-3ea6a44c-3cbc-41a2-91f4-1573461b5035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24339
01758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.2433901758
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.890679017
Short name T1214
Test name
Test status
Simulation time 8369817459 ps
CPU time 7.57 seconds
Started Apr 16 01:01:24 PM PDT 24
Finished Apr 16 01:01:33 PM PDT 24
Peak memory 203988 kb
Host smart-467bc44b-0c33-4b4b-89f7-66ba20f00f4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89067
9017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.890679017
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.1363591544
Short name T617
Test name
Test status
Simulation time 8418803144 ps
CPU time 9.01 seconds
Started Apr 16 01:01:25 PM PDT 24
Finished Apr 16 01:01:35 PM PDT 24
Peak memory 204000 kb
Host smart-9ecedbfa-1ecc-4870-a446-cbdb26e56d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13635
91544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.1363591544
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.3217671492
Short name T186
Test name
Test status
Simulation time 8378838762 ps
CPU time 9.6 seconds
Started Apr 16 01:01:24 PM PDT 24
Finished Apr 16 01:01:35 PM PDT 24
Peak memory 204048 kb
Host smart-9c805bd2-0edb-4ca6-9edf-dae06e8d634b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32176
71492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.3217671492
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2069663465
Short name T8
Test name
Test status
Simulation time 8428163751 ps
CPU time 9.25 seconds
Started Apr 16 01:01:29 PM PDT 24
Finished Apr 16 01:01:39 PM PDT 24
Peak memory 203928 kb
Host smart-16234a1f-6505-4e09-986b-f1ab3f5cc66c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20696
63465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2069663465
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.1577482108
Short name T1370
Test name
Test status
Simulation time 32260648 ps
CPU time 0.64 seconds
Started Apr 16 01:01:24 PM PDT 24
Finished Apr 16 01:01:25 PM PDT 24
Peak memory 203816 kb
Host smart-e5771ff8-9621-4a0f-9044-d054c2387681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15774
82108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1577482108
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.2057329882
Short name T95
Test name
Test status
Simulation time 19513191675 ps
CPU time 38.32 seconds
Started Apr 16 01:01:24 PM PDT 24
Finished Apr 16 01:02:03 PM PDT 24
Peak memory 204296 kb
Host smart-f2449619-8bb2-48c7-ae10-9de955678846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20573
29882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.2057329882
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1121139791
Short name T1311
Test name
Test status
Simulation time 8378695282 ps
CPU time 8.7 seconds
Started Apr 16 01:01:27 PM PDT 24
Finished Apr 16 01:01:37 PM PDT 24
Peak memory 204008 kb
Host smart-9786b15f-628c-47cb-b76d-0af459a20cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11211
39791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1121139791
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2458485985
Short name T1258
Test name
Test status
Simulation time 8400119926 ps
CPU time 8.26 seconds
Started Apr 16 01:01:26 PM PDT 24
Finished Apr 16 01:01:35 PM PDT 24
Peak memory 203988 kb
Host smart-a7e0ce43-2cfe-4624-820c-ddd349b7f8ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24584
85985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2458485985
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.4078476767
Short name T571
Test name
Test status
Simulation time 8400826836 ps
CPU time 8.75 seconds
Started Apr 16 01:01:24 PM PDT 24
Finished Apr 16 01:01:33 PM PDT 24
Peak memory 203976 kb
Host smart-6e94233b-2262-45ad-bd27-37766c7e8411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40784
76767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.4078476767
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.1223374344
Short name T77
Test name
Test status
Simulation time 611285606 ps
CPU time 1.41 seconds
Started Apr 16 01:01:30 PM PDT 24
Finished Apr 16 01:01:32 PM PDT 24
Peak memory 220112 kb
Host smart-8deb1f94-f599-4b1d-b809-a5ad87664ca9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1223374344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.1223374344
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.4059932104
Short name T1334
Test name
Test status
Simulation time 8378409346 ps
CPU time 7.65 seconds
Started Apr 16 01:01:26 PM PDT 24
Finished Apr 16 01:01:34 PM PDT 24
Peak memory 203988 kb
Host smart-fa0c389f-882f-41e2-967f-e84747bce9af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40599
32104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.4059932104
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2508221870
Short name T879
Test name
Test status
Simulation time 8365874152 ps
CPU time 8.53 seconds
Started Apr 16 01:01:25 PM PDT 24
Finished Apr 16 01:01:34 PM PDT 24
Peak memory 204016 kb
Host smart-ce61bce6-44e2-4062-b063-df8af0470c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25082
21870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2508221870
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.70641801
Short name T1314
Test name
Test status
Simulation time 8431218987 ps
CPU time 7.62 seconds
Started Apr 16 01:01:38 PM PDT 24
Finished Apr 16 01:01:46 PM PDT 24
Peak memory 203928 kb
Host smart-6b7cfd70-abb3-46d6-810a-2fff3e187f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70641
801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.70641801
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.244984198
Short name T633
Test name
Test status
Simulation time 8416380333 ps
CPU time 7.51 seconds
Started Apr 16 01:01:27 PM PDT 24
Finished Apr 16 01:01:35 PM PDT 24
Peak memory 203984 kb
Host smart-1a194680-f57a-480c-ae25-a1b1765254a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24498
4198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.244984198
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.2195654660
Short name T938
Test name
Test status
Simulation time 8409936975 ps
CPU time 7.92 seconds
Started Apr 16 01:01:23 PM PDT 24
Finished Apr 16 01:01:32 PM PDT 24
Peak memory 204040 kb
Host smart-3ff58ebf-80c4-4787-8910-7ad9cbe1c050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21956
54660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.2195654660
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.2401215341
Short name T1105
Test name
Test status
Simulation time 8475851878 ps
CPU time 8.85 seconds
Started Apr 16 01:04:12 PM PDT 24
Finished Apr 16 01:04:21 PM PDT 24
Peak memory 204052 kb
Host smart-ad0f2cab-5d8e-45a0-89d3-f755be5c9f63
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2401215341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.2401215341
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.3798820399
Short name T1247
Test name
Test status
Simulation time 8427982846 ps
CPU time 8.25 seconds
Started Apr 16 01:04:18 PM PDT 24
Finished Apr 16 01:04:27 PM PDT 24
Peak memory 203988 kb
Host smart-7ffc39cb-29cb-405c-a747-28a48c9cca73
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3798820399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.3798820399
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.4006469412
Short name T456
Test name
Test status
Simulation time 8428997707 ps
CPU time 8.26 seconds
Started Apr 16 01:04:10 PM PDT 24
Finished Apr 16 01:04:19 PM PDT 24
Peak memory 204016 kb
Host smart-1c52140e-6d79-4bc5-b577-0eb41767b59a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40064
69412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.4006469412
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.1899033741
Short name T803
Test name
Test status
Simulation time 8414120982 ps
CPU time 8.91 seconds
Started Apr 16 01:04:05 PM PDT 24
Finished Apr 16 01:04:16 PM PDT 24
Peak memory 203960 kb
Host smart-7ee6bd73-a6b5-4b2d-bbc0-438432b93186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18990
33741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.1899033741
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_enable.2052173160
Short name T1163
Test name
Test status
Simulation time 8376625842 ps
CPU time 9.72 seconds
Started Apr 16 01:04:05 PM PDT 24
Finished Apr 16 01:04:16 PM PDT 24
Peak memory 204256 kb
Host smart-d1ef9179-019f-4bed-bdfd-ea0fe6a7f674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20521
73160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2052173160
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.4061232013
Short name T1363
Test name
Test status
Simulation time 146235631 ps
CPU time 1.73 seconds
Started Apr 16 01:04:08 PM PDT 24
Finished Apr 16 01:04:11 PM PDT 24
Peak memory 204172 kb
Host smart-4f3b0afc-bcf9-4496-8fb8-b0e6db9beb20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40612
32013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.4061232013
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.1317290106
Short name T1070
Test name
Test status
Simulation time 8451618045 ps
CPU time 9.08 seconds
Started Apr 16 01:04:10 PM PDT 24
Finished Apr 16 01:04:20 PM PDT 24
Peak memory 203968 kb
Host smart-100f5d57-d008-4925-b649-83f1d5571487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13172
90106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.1317290106
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.984271546
Short name T1271
Test name
Test status
Simulation time 8368429284 ps
CPU time 8.95 seconds
Started Apr 16 01:04:10 PM PDT 24
Finished Apr 16 01:04:20 PM PDT 24
Peak memory 204012 kb
Host smart-732ad88f-a269-4806-8881-c7da475ccbd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98427
1546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.984271546
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1342856432
Short name T1318
Test name
Test status
Simulation time 8512669400 ps
CPU time 8.1 seconds
Started Apr 16 01:04:08 PM PDT 24
Finished Apr 16 01:04:17 PM PDT 24
Peak memory 203940 kb
Host smart-3a885d2a-4b56-4979-8d79-b5230485c60e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13428
56432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1342856432
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.880250358
Short name T352
Test name
Test status
Simulation time 8414949547 ps
CPU time 10.48 seconds
Started Apr 16 01:04:08 PM PDT 24
Finished Apr 16 01:04:20 PM PDT 24
Peak memory 204012 kb
Host smart-be3a1bd5-d77e-47e8-8de6-9c02f1c58e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88025
0358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.880250358
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1882133558
Short name T616
Test name
Test status
Simulation time 8393161822 ps
CPU time 8.28 seconds
Started Apr 16 01:04:05 PM PDT 24
Finished Apr 16 01:04:15 PM PDT 24
Peak memory 204036 kb
Host smart-92c3e750-dfeb-4ea5-a360-58754042befe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18821
33558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1882133558
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3290443869
Short name T1308
Test name
Test status
Simulation time 8423457302 ps
CPU time 8.3 seconds
Started Apr 16 01:04:07 PM PDT 24
Finished Apr 16 01:04:17 PM PDT 24
Peak memory 204048 kb
Host smart-8f46201d-5b82-4747-ba01-a4b335a4a140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32904
43869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3290443869
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.3723896858
Short name T1004
Test name
Test status
Simulation time 8373792809 ps
CPU time 9.49 seconds
Started Apr 16 01:04:04 PM PDT 24
Finished Apr 16 01:04:14 PM PDT 24
Peak memory 203996 kb
Host smart-fd023ef2-8f1d-4259-84a6-cafbecd8e249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37238
96858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.3723896858
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.3093891878
Short name T957
Test name
Test status
Simulation time 8468770888 ps
CPU time 8.12 seconds
Started Apr 16 01:04:10 PM PDT 24
Finished Apr 16 01:04:19 PM PDT 24
Peak memory 204032 kb
Host smart-dc2d9947-f819-4aa4-ab13-a7389f2682d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30938
91878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.3093891878
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.2267256005
Short name T185
Test name
Test status
Simulation time 8426333714 ps
CPU time 8.16 seconds
Started Apr 16 01:04:06 PM PDT 24
Finished Apr 16 01:04:15 PM PDT 24
Peak memory 203908 kb
Host smart-a6f88f2f-39a8-4c47-b7b1-f00a7f52f3e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22672
56005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.2267256005
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.3088235354
Short name T1085
Test name
Test status
Simulation time 8403036893 ps
CPU time 7.6 seconds
Started Apr 16 01:04:09 PM PDT 24
Finished Apr 16 01:04:17 PM PDT 24
Peak memory 203972 kb
Host smart-e01c5007-d3a6-40c0-ba0f-791981f5d3b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30882
35354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.3088235354
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.3734126762
Short name T44
Test name
Test status
Simulation time 43449548 ps
CPU time 0.64 seconds
Started Apr 16 01:04:05 PM PDT 24
Finished Apr 16 01:04:06 PM PDT 24
Peak memory 203820 kb
Host smart-e207ae02-01a6-4ad3-9bb2-c78b9129f581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37341
26762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.3734126762
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.659694919
Short name T1180
Test name
Test status
Simulation time 15332188777 ps
CPU time 26.84 seconds
Started Apr 16 01:04:07 PM PDT 24
Finished Apr 16 01:04:35 PM PDT 24
Peak memory 204284 kb
Host smart-5faf2324-b9e2-4e0d-88a0-de10232316f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65969
4919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.659694919
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.2690334211
Short name T694
Test name
Test status
Simulation time 8406209302 ps
CPU time 7.71 seconds
Started Apr 16 01:04:06 PM PDT 24
Finished Apr 16 01:04:15 PM PDT 24
Peak memory 204028 kb
Host smart-d72d213d-1a91-4665-9aba-7b95135e4858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26903
34211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.2690334211
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.917100007
Short name T1294
Test name
Test status
Simulation time 8390792393 ps
CPU time 8 seconds
Started Apr 16 01:04:06 PM PDT 24
Finished Apr 16 01:04:16 PM PDT 24
Peak memory 204044 kb
Host smart-0efcdc25-2b2d-480a-816d-5bd9eb5529e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91710
0007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.917100007
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.758541974
Short name T1183
Test name
Test status
Simulation time 8375018542 ps
CPU time 7.79 seconds
Started Apr 16 01:04:07 PM PDT 24
Finished Apr 16 01:04:16 PM PDT 24
Peak memory 204040 kb
Host smart-57a27724-c2c3-4cce-8658-4c80a3fd71f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75854
1974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.758541974
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.2885890551
Short name T531
Test name
Test status
Simulation time 8390627855 ps
CPU time 7.73 seconds
Started Apr 16 01:04:05 PM PDT 24
Finished Apr 16 01:04:14 PM PDT 24
Peak memory 204052 kb
Host smart-91d109c2-ef9b-4bbe-b897-005867371b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28858
90551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.2885890551
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.2637739935
Short name T79
Test name
Test status
Simulation time 8375561050 ps
CPU time 7.74 seconds
Started Apr 16 01:04:09 PM PDT 24
Finished Apr 16 01:04:17 PM PDT 24
Peak memory 203976 kb
Host smart-c67ace1c-3f1e-4274-b593-5b9e42eddb2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26377
39935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.2637739935
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.3587018196
Short name T542
Test name
Test status
Simulation time 8417084715 ps
CPU time 7.96 seconds
Started Apr 16 01:04:07 PM PDT 24
Finished Apr 16 01:04:16 PM PDT 24
Peak memory 204048 kb
Host smart-95078d5f-cdbb-4675-9ced-756d7fc59ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35870
18196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3587018196
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.2520517412
Short name T1174
Test name
Test status
Simulation time 8447254346 ps
CPU time 8.95 seconds
Started Apr 16 01:04:07 PM PDT 24
Finished Apr 16 01:04:17 PM PDT 24
Peak memory 204028 kb
Host smart-3fe9bb18-ea15-4e67-8335-0aaf485b79ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25205
17412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.2520517412
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.350465987
Short name T580
Test name
Test status
Simulation time 8409827691 ps
CPU time 8.14 seconds
Started Apr 16 01:04:09 PM PDT 24
Finished Apr 16 01:04:18 PM PDT 24
Peak memory 204044 kb
Host smart-cce51daf-f9cf-4891-9a6b-22b9745c5f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35046
5987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.350465987
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.1867389807
Short name T376
Test name
Test status
Simulation time 8466825740 ps
CPU time 8.47 seconds
Started Apr 16 01:04:14 PM PDT 24
Finished Apr 16 01:04:24 PM PDT 24
Peak memory 204044 kb
Host smart-dba2430a-b531-4245-96da-539c25200b28
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1867389807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.1867389807
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.min_length_in_transaction.4038334375
Short name T1181
Test name
Test status
Simulation time 8396966770 ps
CPU time 7.46 seconds
Started Apr 16 01:04:10 PM PDT 24
Finished Apr 16 01:04:18 PM PDT 24
Peak memory 204040 kb
Host smart-30cfbbd6-f001-4d1e-af32-8826d27f710f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4038334375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.4038334375
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.81394756
Short name T393
Test name
Test status
Simulation time 8455957344 ps
CPU time 8.74 seconds
Started Apr 16 01:04:12 PM PDT 24
Finished Apr 16 01:04:21 PM PDT 24
Peak memory 204012 kb
Host smart-62eabbb0-b3a8-4b9a-bf45-8b1f65de5ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81394
756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.81394756
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.2096703831
Short name T1153
Test name
Test status
Simulation time 8442930783 ps
CPU time 9.48 seconds
Started Apr 16 01:04:12 PM PDT 24
Finished Apr 16 01:04:23 PM PDT 24
Peak memory 203744 kb
Host smart-ede3e11f-65d5-4df7-84ae-6afe96bd5ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20967
03831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.2096703831
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_enable.1550605889
Short name T791
Test name
Test status
Simulation time 8377819725 ps
CPU time 8.03 seconds
Started Apr 16 01:04:09 PM PDT 24
Finished Apr 16 01:04:18 PM PDT 24
Peak memory 204040 kb
Host smart-3f1364b4-bf56-4d80-8337-2fb78411def4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15506
05889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.1550605889
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.2530525365
Short name T1036
Test name
Test status
Simulation time 115025305 ps
CPU time 1.41 seconds
Started Apr 16 01:04:18 PM PDT 24
Finished Apr 16 01:04:20 PM PDT 24
Peak memory 204112 kb
Host smart-b9ecca9c-5816-42b7-a87c-b7247baa5ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25305
25365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.2530525365
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.1582045349
Short name T1145
Test name
Test status
Simulation time 8421637846 ps
CPU time 8.06 seconds
Started Apr 16 01:04:11 PM PDT 24
Finished Apr 16 01:04:20 PM PDT 24
Peak memory 204024 kb
Host smart-cd9ef81e-58ca-4f31-b629-94545c1ee007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15820
45349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.1582045349
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.1307183131
Short name T1189
Test name
Test status
Simulation time 8392639042 ps
CPU time 10.1 seconds
Started Apr 16 01:04:12 PM PDT 24
Finished Apr 16 01:04:23 PM PDT 24
Peak memory 203304 kb
Host smart-37c748a7-1784-44cb-8ae6-52674af1e3b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13071
83131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.1307183131
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.1218306594
Short name T138
Test name
Test status
Simulation time 8414866701 ps
CPU time 8.31 seconds
Started Apr 16 01:04:12 PM PDT 24
Finished Apr 16 01:04:21 PM PDT 24
Peak memory 204024 kb
Host smart-ec077d75-0827-403d-a761-243d71f82c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12183
06594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.1218306594
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.1909568144
Short name T1133
Test name
Test status
Simulation time 8420949453 ps
CPU time 7.76 seconds
Started Apr 16 01:04:09 PM PDT 24
Finished Apr 16 01:04:18 PM PDT 24
Peak memory 204020 kb
Host smart-00745f99-d9c2-4ec1-96e0-f9f2667813e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19095
68144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.1909568144
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.2363454536
Short name T640
Test name
Test status
Simulation time 8373196483 ps
CPU time 8.86 seconds
Started Apr 16 01:04:12 PM PDT 24
Finished Apr 16 01:04:22 PM PDT 24
Peak memory 203792 kb
Host smart-ed299acb-f5e4-45b2-801e-87d90007ca42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23634
54536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.2363454536
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2415194815
Short name T115
Test name
Test status
Simulation time 8429736363 ps
CPU time 9.38 seconds
Started Apr 16 01:04:12 PM PDT 24
Finished Apr 16 01:04:22 PM PDT 24
Peak memory 204024 kb
Host smart-2beabbd4-7794-4f49-8c15-7680f94dffac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24151
94815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2415194815
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.4241856501
Short name T434
Test name
Test status
Simulation time 8452022652 ps
CPU time 7.78 seconds
Started Apr 16 01:04:13 PM PDT 24
Finished Apr 16 01:04:22 PM PDT 24
Peak memory 203308 kb
Host smart-3bf7d48c-025a-4788-b7db-1d6d65bfca66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42418
56501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.4241856501
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.3002064033
Short name T227
Test name
Test status
Simulation time 8403136452 ps
CPU time 9.27 seconds
Started Apr 16 01:04:12 PM PDT 24
Finished Apr 16 01:04:23 PM PDT 24
Peak memory 203992 kb
Host smart-2e5033d8-f171-4adc-a6b7-915c943e78d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30020
64033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.3002064033
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3618658252
Short name T169
Test name
Test status
Simulation time 8417663338 ps
CPU time 8.4 seconds
Started Apr 16 01:04:10 PM PDT 24
Finished Apr 16 01:04:19 PM PDT 24
Peak memory 204044 kb
Host smart-afea9a71-1a96-4655-8913-4df79689172b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36186
58252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3618658252
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.1028020316
Short name T420
Test name
Test status
Simulation time 8369768199 ps
CPU time 7.83 seconds
Started Apr 16 01:04:11 PM PDT 24
Finished Apr 16 01:04:20 PM PDT 24
Peak memory 203988 kb
Host smart-6c15d4d4-34cb-4662-93b2-dabf498e0459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10280
20316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.1028020316
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.2336698621
Short name T947
Test name
Test status
Simulation time 42075712 ps
CPU time 0.67 seconds
Started Apr 16 01:04:13 PM PDT 24
Finished Apr 16 01:04:15 PM PDT 24
Peak memory 203904 kb
Host smart-e88c708f-bbba-4324-9253-3d0d589a2500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23366
98621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.2336698621
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.3994218020
Short name T300
Test name
Test status
Simulation time 8403957934 ps
CPU time 9.55 seconds
Started Apr 16 01:04:10 PM PDT 24
Finished Apr 16 01:04:20 PM PDT 24
Peak memory 204020 kb
Host smart-2da71614-bb08-4800-8d2f-57ab0e85a40d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39942
18020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.3994218020
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.656675057
Short name T365
Test name
Test status
Simulation time 8506943796 ps
CPU time 9.26 seconds
Started Apr 16 01:04:11 PM PDT 24
Finished Apr 16 01:04:21 PM PDT 24
Peak memory 203956 kb
Host smart-c3d89f68-f063-45ed-9e77-434b76f3634a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65667
5057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.656675057
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.3219372910
Short name T1099
Test name
Test status
Simulation time 8391322625 ps
CPU time 7.58 seconds
Started Apr 16 01:04:09 PM PDT 24
Finished Apr 16 01:04:17 PM PDT 24
Peak memory 204048 kb
Host smart-188080c7-bbdc-4e0e-9cca-9c28752ce850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32193
72910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.3219372910
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.2633717307
Short name T23
Test name
Test status
Simulation time 8377829400 ps
CPU time 7.58 seconds
Started Apr 16 01:04:11 PM PDT 24
Finished Apr 16 01:04:19 PM PDT 24
Peak memory 203988 kb
Host smart-463edf95-ad4c-4203-9d2f-7b8d93611188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26337
17307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.2633717307
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3811838274
Short name T596
Test name
Test status
Simulation time 8366774530 ps
CPU time 8.63 seconds
Started Apr 16 01:04:12 PM PDT 24
Finished Apr 16 01:04:22 PM PDT 24
Peak memory 203300 kb
Host smart-75ffbd78-f839-4852-bc4b-92f935abaf3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38118
38274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3811838274
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.2480628808
Short name T52
Test name
Test status
Simulation time 8411210130 ps
CPU time 7.69 seconds
Started Apr 16 01:04:13 PM PDT 24
Finished Apr 16 01:04:21 PM PDT 24
Peak memory 203980 kb
Host smart-5a6ba6fa-1674-4103-8b04-6449ded34e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24806
28808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2480628808
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.1045809034
Short name T700
Test name
Test status
Simulation time 8373581979 ps
CPU time 8.51 seconds
Started Apr 16 01:04:18 PM PDT 24
Finished Apr 16 01:04:28 PM PDT 24
Peak memory 203980 kb
Host smart-554fb119-d1cc-48f4-9a00-5550c9ab45cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10458
09034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.1045809034
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.2936009866
Short name T1154
Test name
Test status
Simulation time 8404185101 ps
CPU time 10.66 seconds
Started Apr 16 01:04:13 PM PDT 24
Finished Apr 16 01:04:24 PM PDT 24
Peak memory 203992 kb
Host smart-b2e5862b-e200-483b-802c-fbb52866e822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29360
09866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.2936009866
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.max_length_in_transaction.1160231647
Short name T711
Test name
Test status
Simulation time 8488015888 ps
CPU time 9.5 seconds
Started Apr 16 01:04:29 PM PDT 24
Finished Apr 16 01:04:39 PM PDT 24
Peak memory 203988 kb
Host smart-62ab847a-ff1b-4e99-89c8-a3a93aedc258
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1160231647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.1160231647
Directory /workspace/32.max_length_in_transaction/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.3220197020
Short name T1257
Test name
Test status
Simulation time 8386432504 ps
CPU time 10.06 seconds
Started Apr 16 01:04:21 PM PDT 24
Finished Apr 16 01:04:32 PM PDT 24
Peak memory 203940 kb
Host smart-4d6f1796-b83b-4107-a29d-0e739a3168d2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3220197020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.3220197020
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.40402601
Short name T409
Test name
Test status
Simulation time 8384405388 ps
CPU time 7.57 seconds
Started Apr 16 01:04:16 PM PDT 24
Finished Apr 16 01:04:24 PM PDT 24
Peak memory 204044 kb
Host smart-072089e8-ee54-4bb2-a42a-178de95663b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40402
601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.40402601
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_enable.2823982769
Short name T1076
Test name
Test status
Simulation time 8462232997 ps
CPU time 10.34 seconds
Started Apr 16 01:04:15 PM PDT 24
Finished Apr 16 01:04:26 PM PDT 24
Peak memory 204004 kb
Host smart-ec72718b-50cc-4bf1-94eb-902bf5953f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28239
82769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2823982769
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.891844185
Short name T1343
Test name
Test status
Simulation time 164572798 ps
CPU time 1.95 seconds
Started Apr 16 01:04:16 PM PDT 24
Finished Apr 16 01:04:18 PM PDT 24
Peak memory 204068 kb
Host smart-0c989c8f-9691-421a-b997-8b3d9e2a01e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89184
4185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.891844185
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.4163788726
Short name T1038
Test name
Test status
Simulation time 8447119792 ps
CPU time 8.11 seconds
Started Apr 16 01:04:20 PM PDT 24
Finished Apr 16 01:04:29 PM PDT 24
Peak memory 203988 kb
Host smart-c21e298e-e074-4d6c-aa8f-d21be375774c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41637
88726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.4163788726
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.738320185
Short name T189
Test name
Test status
Simulation time 8380295024 ps
CPU time 9.43 seconds
Started Apr 16 01:04:28 PM PDT 24
Finished Apr 16 01:04:38 PM PDT 24
Peak memory 203984 kb
Host smart-9d49d29a-f31f-4e37-a9b9-863a82ecee11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73832
0185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.738320185
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.1802457555
Short name T881
Test name
Test status
Simulation time 8472143925 ps
CPU time 9.72 seconds
Started Apr 16 01:04:16 PM PDT 24
Finished Apr 16 01:04:27 PM PDT 24
Peak memory 204016 kb
Host smart-d6c116ed-6ecd-4ecf-b3ca-10db62f1c48c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18024
57555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.1802457555
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.2275450324
Short name T1237
Test name
Test status
Simulation time 8420441116 ps
CPU time 10.45 seconds
Started Apr 16 01:04:17 PM PDT 24
Finished Apr 16 01:04:28 PM PDT 24
Peak memory 203992 kb
Host smart-90366f41-740c-42f5-8101-a6968f847ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22754
50324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.2275450324
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.2037757187
Short name T1374
Test name
Test status
Simulation time 8379637600 ps
CPU time 10.27 seconds
Started Apr 16 01:04:17 PM PDT 24
Finished Apr 16 01:04:28 PM PDT 24
Peak memory 203992 kb
Host smart-ea16e729-76c7-4c65-8920-153506515b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20377
57187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.2037757187
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1105459914
Short name T526
Test name
Test status
Simulation time 8414244878 ps
CPU time 9.21 seconds
Started Apr 16 01:04:17 PM PDT 24
Finished Apr 16 01:04:27 PM PDT 24
Peak memory 204048 kb
Host smart-d690dcb9-2ad6-477f-b928-430cd577d04f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11054
59914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1105459914
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.1667813436
Short name T1062
Test name
Test status
Simulation time 8394630490 ps
CPU time 8.5 seconds
Started Apr 16 01:04:15 PM PDT 24
Finished Apr 16 01:04:25 PM PDT 24
Peak memory 204036 kb
Host smart-0f1b9238-e849-467b-a801-b4b1f2e7004b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16678
13436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.1667813436
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.1010873493
Short name T1030
Test name
Test status
Simulation time 8413365084 ps
CPU time 8.39 seconds
Started Apr 16 01:04:26 PM PDT 24
Finished Apr 16 01:04:35 PM PDT 24
Peak memory 203944 kb
Host smart-d8b8a87f-9d3d-4d67-94d2-fd4345f8ffa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10108
73493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.1010873493
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.3151263968
Short name T918
Test name
Test status
Simulation time 41585107 ps
CPU time 0.69 seconds
Started Apr 16 01:04:28 PM PDT 24
Finished Apr 16 01:04:29 PM PDT 24
Peak memory 203852 kb
Host smart-2156f796-dc8a-4773-9fdc-284c954f67aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31512
63968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.3151263968
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.96690604
Short name T1152
Test name
Test status
Simulation time 14782659562 ps
CPU time 25.24 seconds
Started Apr 16 01:04:16 PM PDT 24
Finished Apr 16 01:04:42 PM PDT 24
Peak memory 204304 kb
Host smart-4c335ebe-76c2-4602-a261-b565bb8b087f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96690
604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.96690604
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.2749922293
Short name T381
Test name
Test status
Simulation time 8417538266 ps
CPU time 7.81 seconds
Started Apr 16 01:04:14 PM PDT 24
Finished Apr 16 01:04:23 PM PDT 24
Peak memory 203948 kb
Host smart-90710da7-36f0-41d8-9ede-87492fedfa43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27499
22293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.2749922293
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.378073890
Short name T690
Test name
Test status
Simulation time 8438723494 ps
CPU time 10.02 seconds
Started Apr 16 01:04:17 PM PDT 24
Finished Apr 16 01:04:28 PM PDT 24
Peak memory 203992 kb
Host smart-e385b711-026c-4cbd-8561-0c03c4e7f619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37807
3890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.378073890
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.393030741
Short name T1291
Test name
Test status
Simulation time 8447785456 ps
CPU time 8.47 seconds
Started Apr 16 01:04:17 PM PDT 24
Finished Apr 16 01:04:26 PM PDT 24
Peak memory 204016 kb
Host smart-eb814eaf-ddd1-49cd-ae8b-72d79c7ada1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39303
0741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.393030741
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.283562933
Short name T994
Test name
Test status
Simulation time 8377386221 ps
CPU time 8.22 seconds
Started Apr 16 01:04:18 PM PDT 24
Finished Apr 16 01:04:27 PM PDT 24
Peak memory 204012 kb
Host smart-027c022d-be62-43d5-b43e-25ac7ef2ab3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28356
2933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.283562933
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2767791652
Short name T909
Test name
Test status
Simulation time 8363439069 ps
CPU time 8.78 seconds
Started Apr 16 01:04:17 PM PDT 24
Finished Apr 16 01:04:26 PM PDT 24
Peak memory 203976 kb
Host smart-d81638e7-cab8-4cb5-acee-1d750bb9b915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27677
91652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2767791652
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.3873879896
Short name T1275
Test name
Test status
Simulation time 8452911262 ps
CPU time 8.51 seconds
Started Apr 16 01:04:20 PM PDT 24
Finished Apr 16 01:04:29 PM PDT 24
Peak memory 204048 kb
Host smart-564014ad-5f00-426a-8a8d-465c07532c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38738
79896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.3873879896
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.4202176695
Short name T9
Test name
Test status
Simulation time 8389635036 ps
CPU time 8.27 seconds
Started Apr 16 01:04:24 PM PDT 24
Finished Apr 16 01:04:33 PM PDT 24
Peak memory 204048 kb
Host smart-09565beb-a0fe-482d-800f-a9b02cc63743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42021
76695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.4202176695
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.2164817356
Short name T873
Test name
Test status
Simulation time 8397206317 ps
CPU time 8.22 seconds
Started Apr 16 01:04:19 PM PDT 24
Finished Apr 16 01:04:28 PM PDT 24
Peak memory 204044 kb
Host smart-3c6523c1-5e6a-4e92-95f6-c2a352d9d6fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21648
17356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.2164817356
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.3630081150
Short name T1220
Test name
Test status
Simulation time 8489349178 ps
CPU time 8.49 seconds
Started Apr 16 01:04:26 PM PDT 24
Finished Apr 16 01:04:36 PM PDT 24
Peak memory 203924 kb
Host smart-4495afd3-7d41-4922-b03a-196675537c75
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3630081150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.3630081150
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.1216975314
Short name T671
Test name
Test status
Simulation time 8377694533 ps
CPU time 8.34 seconds
Started Apr 16 01:04:25 PM PDT 24
Finished Apr 16 01:04:35 PM PDT 24
Peak memory 203964 kb
Host smart-915d909a-e5dd-40b5-a688-852e1ceeee31
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1216975314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.1216975314
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.1915377894
Short name T364
Test name
Test status
Simulation time 8386617960 ps
CPU time 8.65 seconds
Started Apr 16 01:04:26 PM PDT 24
Finished Apr 16 01:04:36 PM PDT 24
Peak memory 204044 kb
Host smart-ee76339f-6e0c-4f05-a66b-96bd4a5f65c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19153
77894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.1915377894
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.1657269396
Short name T1218
Test name
Test status
Simulation time 8379303625 ps
CPU time 7.49 seconds
Started Apr 16 01:04:29 PM PDT 24
Finished Apr 16 01:04:37 PM PDT 24
Peak memory 203984 kb
Host smart-79dd3c4c-2041-4cf2-9312-bdbb06840707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16572
69396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1657269396
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_enable.1519446023
Short name T945
Test name
Test status
Simulation time 8398220758 ps
CPU time 9.24 seconds
Started Apr 16 01:04:22 PM PDT 24
Finished Apr 16 01:04:32 PM PDT 24
Peak memory 204048 kb
Host smart-69dbcf74-602e-4b95-9e43-95a9baee0855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15194
46023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1519446023
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.3401925723
Short name T1157
Test name
Test status
Simulation time 189520426 ps
CPU time 2.07 seconds
Started Apr 16 01:04:24 PM PDT 24
Finished Apr 16 01:04:26 PM PDT 24
Peak memory 204212 kb
Host smart-d2167d43-2daa-44c9-bc2c-fc08f7010485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34019
25723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3401925723
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.2410783139
Short name T524
Test name
Test status
Simulation time 8450650167 ps
CPU time 8.36 seconds
Started Apr 16 01:04:23 PM PDT 24
Finished Apr 16 01:04:33 PM PDT 24
Peak memory 203928 kb
Host smart-c81fc698-49e1-474b-8aa1-f8766bbd12ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24107
83139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2410783139
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2670684342
Short name T1074
Test name
Test status
Simulation time 8398640742 ps
CPU time 8.09 seconds
Started Apr 16 01:04:21 PM PDT 24
Finished Apr 16 01:04:30 PM PDT 24
Peak memory 204024 kb
Host smart-ad1a5dfb-a544-46d2-aa2f-ac3a726c2912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26706
84342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2670684342
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.1092922234
Short name T360
Test name
Test status
Simulation time 8443822748 ps
CPU time 8.34 seconds
Started Apr 16 01:04:20 PM PDT 24
Finished Apr 16 01:04:29 PM PDT 24
Peak memory 204044 kb
Host smart-b288d8ed-bdbf-4d26-8680-e83051c36054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10929
22234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.1092922234
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.568704648
Short name T1216
Test name
Test status
Simulation time 8415459578 ps
CPU time 10.76 seconds
Started Apr 16 01:04:21 PM PDT 24
Finished Apr 16 01:04:32 PM PDT 24
Peak memory 204016 kb
Host smart-50540535-e1ad-457c-baca-c0fb73b589f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56870
4648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.568704648
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.1870190354
Short name T567
Test name
Test status
Simulation time 8369517310 ps
CPU time 9 seconds
Started Apr 16 01:04:20 PM PDT 24
Finished Apr 16 01:04:30 PM PDT 24
Peak memory 204028 kb
Host smart-2a634f46-8527-4eeb-b438-4f0236f7189a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18701
90354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.1870190354
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3738917091
Short name T103
Test name
Test status
Simulation time 8393910701 ps
CPU time 7.99 seconds
Started Apr 16 01:04:21 PM PDT 24
Finished Apr 16 01:04:30 PM PDT 24
Peak memory 203992 kb
Host smart-6123d814-d278-4884-be2e-09bf469a530f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37389
17091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3738917091
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.4085738697
Short name T1299
Test name
Test status
Simulation time 8406928219 ps
CPU time 9.04 seconds
Started Apr 16 01:04:20 PM PDT 24
Finished Apr 16 01:04:30 PM PDT 24
Peak memory 204044 kb
Host smart-658957f4-a22f-418c-af4f-1940a64c5e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40857
38697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.4085738697
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.4115406011
Short name T1018
Test name
Test status
Simulation time 8429647671 ps
CPU time 8.01 seconds
Started Apr 16 01:04:21 PM PDT 24
Finished Apr 16 01:04:30 PM PDT 24
Peak memory 204032 kb
Host smart-8c5430be-14a0-4c58-91dd-6d4bece0877c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41154
06011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.4115406011
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.2343429486
Short name T160
Test name
Test status
Simulation time 8404546339 ps
CPU time 8.78 seconds
Started Apr 16 01:04:22 PM PDT 24
Finished Apr 16 01:04:31 PM PDT 24
Peak memory 204024 kb
Host smart-1fdb7a68-38d8-45df-8ae9-e0c587aa3329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23434
29486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.2343429486
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.2978843313
Short name T684
Test name
Test status
Simulation time 8415238046 ps
CPU time 8.04 seconds
Started Apr 16 01:04:24 PM PDT 24
Finished Apr 16 01:04:33 PM PDT 24
Peak memory 203900 kb
Host smart-6408b4d4-a421-4419-aeb4-e51aee44c4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29788
43313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.2978843313
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.2646964409
Short name T510
Test name
Test status
Simulation time 50238692 ps
CPU time 0.68 seconds
Started Apr 16 01:04:24 PM PDT 24
Finished Apr 16 01:04:25 PM PDT 24
Peak memory 203820 kb
Host smart-d273e1d7-307b-4f43-99e5-78f987149cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26469
64409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.2646964409
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.1447123687
Short name T236
Test name
Test status
Simulation time 29778887492 ps
CPU time 61.05 seconds
Started Apr 16 01:04:22 PM PDT 24
Finished Apr 16 01:05:24 PM PDT 24
Peak memory 204316 kb
Host smart-1b078adb-d431-4829-9057-ce944c1a604f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14471
23687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.1447123687
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.1224928906
Short name T349
Test name
Test status
Simulation time 8400754815 ps
CPU time 9.73 seconds
Started Apr 16 01:04:22 PM PDT 24
Finished Apr 16 01:04:32 PM PDT 24
Peak memory 203964 kb
Host smart-19999036-fcda-4a98-9160-d08cfa7e38ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12249
28906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.1224928906
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.3401653594
Short name T517
Test name
Test status
Simulation time 8384768153 ps
CPU time 8 seconds
Started Apr 16 01:04:24 PM PDT 24
Finished Apr 16 01:04:32 PM PDT 24
Peak memory 203956 kb
Host smart-98a305f6-0707-46d7-9d02-b326fac422ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34016
53594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3401653594
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.2137980385
Short name T1045
Test name
Test status
Simulation time 8393704255 ps
CPU time 7.82 seconds
Started Apr 16 01:04:21 PM PDT 24
Finished Apr 16 01:04:30 PM PDT 24
Peak memory 204028 kb
Host smart-5d92771d-6478-4618-a5e6-39b1f1d74234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21379
80385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.2137980385
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.683544971
Short name T534
Test name
Test status
Simulation time 8375949434 ps
CPU time 9.58 seconds
Started Apr 16 01:04:21 PM PDT 24
Finished Apr 16 01:04:31 PM PDT 24
Peak memory 204024 kb
Host smart-6757837b-d9c7-4486-8408-556f8767b194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68354
4971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.683544971
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.1189138939
Short name T1182
Test name
Test status
Simulation time 8378958493 ps
CPU time 9.72 seconds
Started Apr 16 01:04:24 PM PDT 24
Finished Apr 16 01:04:35 PM PDT 24
Peak memory 203944 kb
Host smart-ea261682-a131-4c2a-b0ce-9a18223c46f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11891
38939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.1189138939
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2366624403
Short name T460
Test name
Test status
Simulation time 8412812144 ps
CPU time 9.35 seconds
Started Apr 16 01:04:26 PM PDT 24
Finished Apr 16 01:04:36 PM PDT 24
Peak memory 203944 kb
Host smart-ccd9c08b-cd1f-4e64-b23f-74659c580abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23666
24403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2366624403
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.1927665481
Short name T387
Test name
Test status
Simulation time 8420808788 ps
CPU time 7.94 seconds
Started Apr 16 01:04:22 PM PDT 24
Finished Apr 16 01:04:30 PM PDT 24
Peak memory 204016 kb
Host smart-4e6d3d43-a6ea-4b5d-b18b-25e2c359a345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19276
65481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.1927665481
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.2222445752
Short name T326
Test name
Test status
Simulation time 8402205991 ps
CPU time 7.86 seconds
Started Apr 16 01:04:26 PM PDT 24
Finished Apr 16 01:04:35 PM PDT 24
Peak memory 204044 kb
Host smart-953955fb-eca3-4c8b-8b1c-cead3ada3197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22224
45752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.2222445752
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.789293402
Short name T903
Test name
Test status
Simulation time 8472446814 ps
CPU time 8.83 seconds
Started Apr 16 01:04:29 PM PDT 24
Finished Apr 16 01:04:39 PM PDT 24
Peak memory 203932 kb
Host smart-fbc74893-a842-4369-a98f-c2660e85a189
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=789293402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.789293402
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.2307073840
Short name T875
Test name
Test status
Simulation time 8384142282 ps
CPU time 9.02 seconds
Started Apr 16 01:04:29 PM PDT 24
Finished Apr 16 01:04:39 PM PDT 24
Peak memory 204052 kb
Host smart-06914a9c-82f8-4b0d-8148-5e90aa337a81
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2307073840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.2307073840
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.4066946417
Short name T631
Test name
Test status
Simulation time 8500309481 ps
CPU time 8.27 seconds
Started Apr 16 01:04:28 PM PDT 24
Finished Apr 16 01:04:37 PM PDT 24
Peak memory 204024 kb
Host smart-1a0a7ede-da51-4648-8cbf-02e4a2a48e70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40669
46417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.4066946417
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2602081940
Short name T936
Test name
Test status
Simulation time 8423627317 ps
CPU time 7.45 seconds
Started Apr 16 01:04:23 PM PDT 24
Finished Apr 16 01:04:31 PM PDT 24
Peak memory 203992 kb
Host smart-0130be17-5afc-4470-ac01-50e9a5a7a376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26020
81940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2602081940
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_enable.2215468356
Short name T348
Test name
Test status
Simulation time 8383998835 ps
CPU time 8.51 seconds
Started Apr 16 01:04:27 PM PDT 24
Finished Apr 16 01:04:36 PM PDT 24
Peak memory 204032 kb
Host smart-9de6b0a2-edb8-4767-866f-df13923fab14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22154
68356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.2215468356
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.100345986
Short name T560
Test name
Test status
Simulation time 138950588 ps
CPU time 1.41 seconds
Started Apr 16 01:04:26 PM PDT 24
Finished Apr 16 01:04:28 PM PDT 24
Peak memory 204328 kb
Host smart-a8977da3-0b29-44f7-b099-3be4fe66421e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10034
5986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.100345986
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.457617121
Short name T1358
Test name
Test status
Simulation time 8415713698 ps
CPU time 8.06 seconds
Started Apr 16 01:04:30 PM PDT 24
Finished Apr 16 01:04:40 PM PDT 24
Peak memory 204032 kb
Host smart-d6486d97-c425-4451-b26c-35d6450bb9d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45761
7121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.457617121
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.1121407838
Short name T1347
Test name
Test status
Simulation time 8372866038 ps
CPU time 9.77 seconds
Started Apr 16 01:04:31 PM PDT 24
Finished Apr 16 01:04:42 PM PDT 24
Peak memory 204252 kb
Host smart-e3883d75-4503-4524-a265-34d39735c38d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11214
07838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.1121407838
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.891061694
Short name T669
Test name
Test status
Simulation time 8387155991 ps
CPU time 9.88 seconds
Started Apr 16 01:04:23 PM PDT 24
Finished Apr 16 01:04:34 PM PDT 24
Peak memory 204016 kb
Host smart-b70a37fa-2989-43e2-b446-43e86b2321f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89106
1694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.891061694
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.3027885983
Short name T963
Test name
Test status
Simulation time 8416754334 ps
CPU time 8.27 seconds
Started Apr 16 01:04:33 PM PDT 24
Finished Apr 16 01:04:42 PM PDT 24
Peak memory 204024 kb
Host smart-8f9d39b6-676b-4624-b270-858857e06367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30278
85983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.3027885983
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.4257605393
Short name T948
Test name
Test status
Simulation time 8387997404 ps
CPU time 7.43 seconds
Started Apr 16 01:04:26 PM PDT 24
Finished Apr 16 01:04:34 PM PDT 24
Peak memory 204028 kb
Host smart-9774e416-0032-433e-b704-6b6f62422b02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42576
05393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.4257605393
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2115648813
Short name T703
Test name
Test status
Simulation time 8406526332 ps
CPU time 9.79 seconds
Started Apr 16 01:04:26 PM PDT 24
Finished Apr 16 01:04:37 PM PDT 24
Peak memory 204032 kb
Host smart-eb97d581-f345-46cb-a45b-f43df377054f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21156
48813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2115648813
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.2809748523
Short name T301
Test name
Test status
Simulation time 8383860004 ps
CPU time 7.75 seconds
Started Apr 16 01:04:28 PM PDT 24
Finished Apr 16 01:04:37 PM PDT 24
Peak memory 204048 kb
Host smart-add30b5e-a2c3-4503-b264-a41757678fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28097
48523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.2809748523
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.2785171193
Short name T1024
Test name
Test status
Simulation time 8400034054 ps
CPU time 7.93 seconds
Started Apr 16 01:04:31 PM PDT 24
Finished Apr 16 01:04:40 PM PDT 24
Peak memory 203988 kb
Host smart-75b0534a-4f68-4f2d-9135-43fab0ae729a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27851
71193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.2785171193
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.3580446686
Short name T733
Test name
Test status
Simulation time 8364067556 ps
CPU time 8.36 seconds
Started Apr 16 01:04:32 PM PDT 24
Finished Apr 16 01:04:41 PM PDT 24
Peak memory 203732 kb
Host smart-313232d9-b6bc-4d8d-aa4f-d153e560d3bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35804
46686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.3580446686
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.805062062
Short name T550
Test name
Test status
Simulation time 201219207 ps
CPU time 0.87 seconds
Started Apr 16 01:04:31 PM PDT 24
Finished Apr 16 01:04:33 PM PDT 24
Peak memory 203856 kb
Host smart-d5cd6b80-49f6-48df-85a7-b5a17886f2ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80506
2062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.805062062
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.3516669819
Short name T1264
Test name
Test status
Simulation time 28975728482 ps
CPU time 61.7 seconds
Started Apr 16 01:04:29 PM PDT 24
Finished Apr 16 01:05:32 PM PDT 24
Peak memory 204332 kb
Host smart-62530b4f-d30d-499a-b239-d96db7d919a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35166
69819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.3516669819
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.4068657696
Short name T1101
Test name
Test status
Simulation time 8398276254 ps
CPU time 7.91 seconds
Started Apr 16 01:04:28 PM PDT 24
Finished Apr 16 01:04:37 PM PDT 24
Peak memory 204048 kb
Host smart-0ed87ebc-acd0-4f35-a2b0-049de693e8a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40686
57696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.4068657696
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.4156600967
Short name T1254
Test name
Test status
Simulation time 8443512985 ps
CPU time 8.18 seconds
Started Apr 16 01:04:25 PM PDT 24
Finished Apr 16 01:04:34 PM PDT 24
Peak memory 203960 kb
Host smart-e3f97cf9-6154-4a01-b4cb-d2495f5b1690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41566
00967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.4156600967
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.4206560999
Short name T687
Test name
Test status
Simulation time 8410384168 ps
CPU time 8.19 seconds
Started Apr 16 01:04:28 PM PDT 24
Finished Apr 16 01:04:37 PM PDT 24
Peak memory 204048 kb
Host smart-0bf11b9b-7fab-4f63-ae10-1996832cf614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42065
60999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.4206560999
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.2285945265
Short name T157
Test name
Test status
Simulation time 8378179153 ps
CPU time 8.61 seconds
Started Apr 16 01:04:32 PM PDT 24
Finished Apr 16 01:04:41 PM PDT 24
Peak memory 204044 kb
Host smart-47e86941-3e08-47c5-bace-085ff91abd6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22859
45265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.2285945265
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.849050482
Short name T1270
Test name
Test status
Simulation time 8378721411 ps
CPU time 8.78 seconds
Started Apr 16 01:04:31 PM PDT 24
Finished Apr 16 01:04:41 PM PDT 24
Peak memory 203976 kb
Host smart-3b3c2527-a775-4399-8ea8-61b948861063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84905
0482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.849050482
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.3593037905
Short name T1166
Test name
Test status
Simulation time 8409033947 ps
CPU time 8.06 seconds
Started Apr 16 01:04:25 PM PDT 24
Finished Apr 16 01:04:34 PM PDT 24
Peak memory 204020 kb
Host smart-6148352e-0ad1-41ba-b657-4f45b10c5012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35930
37905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.3593037905
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.3899744954
Short name T1047
Test name
Test status
Simulation time 8448660981 ps
CPU time 8.72 seconds
Started Apr 16 01:04:30 PM PDT 24
Finished Apr 16 01:04:40 PM PDT 24
Peak memory 204016 kb
Host smart-020eeaa9-5f35-448f-a968-3d04e416c5e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38997
44954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.3899744954
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.1735453216
Short name T958
Test name
Test status
Simulation time 8441069750 ps
CPU time 8.14 seconds
Started Apr 16 01:04:25 PM PDT 24
Finished Apr 16 01:04:33 PM PDT 24
Peak memory 204024 kb
Host smart-d69cce49-17a9-48c0-8ec6-b0458dea2e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17354
53216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.1735453216
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.2344197470
Short name T796
Test name
Test status
Simulation time 8466233493 ps
CPU time 7.92 seconds
Started Apr 16 01:04:38 PM PDT 24
Finished Apr 16 01:04:47 PM PDT 24
Peak memory 204020 kb
Host smart-06e79f3c-f9cd-4d6e-95bd-75a9a543b1bb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2344197470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.2344197470
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.355336122
Short name T483
Test name
Test status
Simulation time 8378669465 ps
CPU time 8.16 seconds
Started Apr 16 01:04:35 PM PDT 24
Finished Apr 16 01:04:43 PM PDT 24
Peak memory 204004 kb
Host smart-907fe005-93f4-4d7e-b068-e8652e595598
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=355336122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.355336122
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.3482560812
Short name T1001
Test name
Test status
Simulation time 8413603343 ps
CPU time 8.56 seconds
Started Apr 16 01:04:41 PM PDT 24
Finished Apr 16 01:04:50 PM PDT 24
Peak memory 203988 kb
Host smart-0f6925a2-abb9-4673-822e-3fe56b7ea102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34825
60812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.3482560812
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.2181291600
Short name T572
Test name
Test status
Simulation time 8389746028 ps
CPU time 7.81 seconds
Started Apr 16 01:04:32 PM PDT 24
Finished Apr 16 01:04:41 PM PDT 24
Peak memory 204024 kb
Host smart-cb049ae9-cba1-4d87-99bf-e2696954d254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21812
91600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2181291600
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_enable.3707627123
Short name T463
Test name
Test status
Simulation time 8396861488 ps
CPU time 7.73 seconds
Started Apr 16 01:04:29 PM PDT 24
Finished Apr 16 01:04:38 PM PDT 24
Peak memory 203928 kb
Host smart-d71f4066-2817-47b7-847c-900b9241513f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37076
27123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.3707627123
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.3912757828
Short name T991
Test name
Test status
Simulation time 146882247 ps
CPU time 1.55 seconds
Started Apr 16 01:04:37 PM PDT 24
Finished Apr 16 01:04:39 PM PDT 24
Peak memory 204176 kb
Host smart-a78be4be-5e98-4f13-bbcc-d204c1e36938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39127
57828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.3912757828
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.1835913853
Short name T139
Test name
Test status
Simulation time 8439339623 ps
CPU time 8.87 seconds
Started Apr 16 01:04:35 PM PDT 24
Finished Apr 16 01:04:44 PM PDT 24
Peak memory 204028 kb
Host smart-2c0c73c5-9568-4173-83f6-c4e0860df878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18359
13853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.1835913853
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.3288814289
Short name T177
Test name
Test status
Simulation time 8370471937 ps
CPU time 9.09 seconds
Started Apr 16 01:04:34 PM PDT 24
Finished Apr 16 01:04:44 PM PDT 24
Peak memory 204016 kb
Host smart-f172adec-bb94-4708-80dc-2d906019dfef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32888
14289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.3288814289
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.3099342849
Short name T503
Test name
Test status
Simulation time 8462224001 ps
CPU time 8.47 seconds
Started Apr 16 01:04:35 PM PDT 24
Finished Apr 16 01:04:44 PM PDT 24
Peak memory 204016 kb
Host smart-6618ba6f-77fe-453d-8f19-6535f3e304df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30993
42849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.3099342849
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.2025003589
Short name T502
Test name
Test status
Simulation time 8418872881 ps
CPU time 7.97 seconds
Started Apr 16 01:04:36 PM PDT 24
Finished Apr 16 01:04:45 PM PDT 24
Peak memory 204024 kb
Host smart-519d8a55-e771-4ace-8dc0-d8e640bd7cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20250
03589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.2025003589
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2280085886
Short name T1080
Test name
Test status
Simulation time 8375784633 ps
CPU time 7.64 seconds
Started Apr 16 01:04:35 PM PDT 24
Finished Apr 16 01:04:43 PM PDT 24
Peak memory 203996 kb
Host smart-bfbf9a74-de21-4c3e-953e-cc6224b577e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22800
85886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2280085886
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2491786256
Short name T100
Test name
Test status
Simulation time 8391860641 ps
CPU time 8.02 seconds
Started Apr 16 01:04:36 PM PDT 24
Finished Apr 16 01:04:45 PM PDT 24
Peak memory 204028 kb
Host smart-d9aac86f-f81f-43b3-90ee-9f2b3a4c98a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24917
86256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2491786256
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3418777456
Short name T1204
Test name
Test status
Simulation time 8406109235 ps
CPU time 7.77 seconds
Started Apr 16 01:04:38 PM PDT 24
Finished Apr 16 01:04:47 PM PDT 24
Peak memory 203948 kb
Host smart-0f5509f9-3d82-4394-ae06-e27a01e7294c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34187
77456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3418777456
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.1017910488
Short name T1055
Test name
Test status
Simulation time 8406158549 ps
CPU time 8.28 seconds
Started Apr 16 01:04:40 PM PDT 24
Finished Apr 16 01:04:49 PM PDT 24
Peak memory 203988 kb
Host smart-67a670c8-965b-46f8-a96c-96edb559866f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10179
10488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.1017910488
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.3555221337
Short name T741
Test name
Test status
Simulation time 8383966127 ps
CPU time 8.71 seconds
Started Apr 16 01:04:36 PM PDT 24
Finished Apr 16 01:04:45 PM PDT 24
Peak memory 204032 kb
Host smart-07b52eed-a715-4765-87fb-e88c3a83af24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35552
21337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.3555221337
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.1404845089
Short name T734
Test name
Test status
Simulation time 8384466575 ps
CPU time 9.79 seconds
Started Apr 16 01:04:39 PM PDT 24
Finished Apr 16 01:04:50 PM PDT 24
Peak memory 204068 kb
Host smart-143d3cc8-6c73-4610-9c43-820cbe208c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14048
45089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.1404845089
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.1858317892
Short name T1200
Test name
Test status
Simulation time 103456261 ps
CPU time 0.74 seconds
Started Apr 16 01:04:35 PM PDT 24
Finished Apr 16 01:04:36 PM PDT 24
Peak memory 203884 kb
Host smart-52c6b614-2f1b-47e1-a2f0-a560f9696a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18583
17892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.1858317892
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.2533456121
Short name T823
Test name
Test status
Simulation time 21600331062 ps
CPU time 40.23 seconds
Started Apr 16 01:04:33 PM PDT 24
Finished Apr 16 01:05:14 PM PDT 24
Peak memory 204336 kb
Host smart-f9ffbcd2-fb84-4245-8ebd-5c3eb00e8876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25334
56121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.2533456121
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.1543973896
Short name T882
Test name
Test status
Simulation time 8383741071 ps
CPU time 8.87 seconds
Started Apr 16 01:04:34 PM PDT 24
Finished Apr 16 01:04:44 PM PDT 24
Peak memory 204040 kb
Host smart-720b0713-3fcd-41ae-b4d6-42377345c77c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15439
73896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.1543973896
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.3598761362
Short name T367
Test name
Test status
Simulation time 8433564592 ps
CPU time 7.61 seconds
Started Apr 16 01:04:36 PM PDT 24
Finished Apr 16 01:04:45 PM PDT 24
Peak memory 203956 kb
Host smart-e156caf5-54eb-4574-a0bc-41a13b3bab4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35987
61362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3598761362
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.103359304
Short name T893
Test name
Test status
Simulation time 8408608092 ps
CPU time 7.91 seconds
Started Apr 16 01:04:39 PM PDT 24
Finished Apr 16 01:04:47 PM PDT 24
Peak memory 204016 kb
Host smart-959acafc-0287-40c7-90e3-b610aec4fa07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10335
9304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.103359304
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.3825191643
Short name T759
Test name
Test status
Simulation time 8378509660 ps
CPU time 10.19 seconds
Started Apr 16 01:04:35 PM PDT 24
Finished Apr 16 01:04:46 PM PDT 24
Peak memory 204028 kb
Host smart-6c61f11d-b167-4ecc-958a-e55acb7174c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38251
91643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.3825191643
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.4082147124
Short name T29
Test name
Test status
Simulation time 8369076788 ps
CPU time 7.55 seconds
Started Apr 16 01:04:34 PM PDT 24
Finished Apr 16 01:04:42 PM PDT 24
Peak memory 203908 kb
Host smart-ebdcde29-ea92-447e-9a74-251c9250442b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40821
47124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.4082147124
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.1395040894
Short name T1162
Test name
Test status
Simulation time 8439568967 ps
CPU time 7.93 seconds
Started Apr 16 01:04:30 PM PDT 24
Finished Apr 16 01:04:39 PM PDT 24
Peak memory 204028 kb
Host smart-c0b08cb3-29bd-43dd-b187-677fb12c43d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13950
40894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.1395040894
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3166886875
Short name T1066
Test name
Test status
Simulation time 8376269355 ps
CPU time 9.84 seconds
Started Apr 16 01:04:35 PM PDT 24
Finished Apr 16 01:04:46 PM PDT 24
Peak memory 204048 kb
Host smart-f0de4f09-c372-4474-b4b5-b8278e9aa0aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31668
86875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3166886875
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.3663507793
Short name T561
Test name
Test status
Simulation time 8425617822 ps
CPU time 9.04 seconds
Started Apr 16 01:04:43 PM PDT 24
Finished Apr 16 01:04:53 PM PDT 24
Peak memory 203988 kb
Host smart-527a2441-7012-4d3a-ad94-302bb90742d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36635
07793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.3663507793
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.2966794420
Short name T389
Test name
Test status
Simulation time 8471603208 ps
CPU time 10.85 seconds
Started Apr 16 01:04:40 PM PDT 24
Finished Apr 16 01:04:52 PM PDT 24
Peak memory 204052 kb
Host smart-7d3debfc-4f71-4417-bcdc-3881d8ab5d9b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2966794420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.2966794420
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.1842772007
Short name T1244
Test name
Test status
Simulation time 8377445118 ps
CPU time 7.96 seconds
Started Apr 16 01:04:43 PM PDT 24
Finished Apr 16 01:04:51 PM PDT 24
Peak memory 203980 kb
Host smart-2634176b-695d-494b-8321-26abd3331af1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1842772007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.1842772007
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.256959458
Short name T328
Test name
Test status
Simulation time 8400089334 ps
CPU time 10.12 seconds
Started Apr 16 01:04:43 PM PDT 24
Finished Apr 16 01:04:53 PM PDT 24
Peak memory 203984 kb
Host smart-5afe52af-4463-44cc-a6fa-8f8795a6a348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25695
9458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.256959458
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.1807455094
Short name T925
Test name
Test status
Simulation time 8378744354 ps
CPU time 8.18 seconds
Started Apr 16 01:04:40 PM PDT 24
Finished Apr 16 01:04:49 PM PDT 24
Peak memory 204024 kb
Host smart-7f775c43-2495-46f6-9fac-6960a6e1e57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18074
55094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1807455094
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_enable.592058403
Short name T359
Test name
Test status
Simulation time 8375339370 ps
CPU time 7.62 seconds
Started Apr 16 01:04:41 PM PDT 24
Finished Apr 16 01:04:49 PM PDT 24
Peak memory 203944 kb
Host smart-de8dc6b8-62ec-43ae-a87c-8bfd834c20ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59205
8403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.592058403
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.856397373
Short name T1325
Test name
Test status
Simulation time 8394128076 ps
CPU time 8.66 seconds
Started Apr 16 01:04:38 PM PDT 24
Finished Apr 16 01:04:48 PM PDT 24
Peak memory 203988 kb
Host smart-c5df9466-4fdd-4afa-92d5-852c234b9ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85639
7373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.856397373
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.2976960431
Short name T1238
Test name
Test status
Simulation time 8370986924 ps
CPU time 7.5 seconds
Started Apr 16 01:04:39 PM PDT 24
Finished Apr 16 01:04:48 PM PDT 24
Peak memory 203936 kb
Host smart-cc41abba-121f-4a02-a40d-92338eb3bd7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29769
60431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.2976960431
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.4245461071
Short name T1131
Test name
Test status
Simulation time 8472015482 ps
CPU time 10.39 seconds
Started Apr 16 01:04:42 PM PDT 24
Finished Apr 16 01:04:53 PM PDT 24
Peak memory 204084 kb
Host smart-68e7c35f-4e46-4775-9462-5db88070ce96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42454
61071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.4245461071
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.4226716057
Short name T767
Test name
Test status
Simulation time 8413316049 ps
CPU time 8 seconds
Started Apr 16 01:04:38 PM PDT 24
Finished Apr 16 01:04:46 PM PDT 24
Peak memory 204040 kb
Host smart-dab6f568-c691-4036-912c-6ecf411cc31c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42267
16057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.4226716057
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.741929208
Short name T905
Test name
Test status
Simulation time 8377057874 ps
CPU time 8.92 seconds
Started Apr 16 01:04:42 PM PDT 24
Finished Apr 16 01:04:52 PM PDT 24
Peak memory 204068 kb
Host smart-eb856fda-09a8-476f-aba2-5af915952dd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74192
9208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.741929208
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.3587779809
Short name T765
Test name
Test status
Simulation time 8437575832 ps
CPU time 7.94 seconds
Started Apr 16 01:04:40 PM PDT 24
Finished Apr 16 01:04:49 PM PDT 24
Peak memory 204044 kb
Host smart-0ea62658-bd66-4be6-ab0a-12b04cf58b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35877
79809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.3587779809
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3762867864
Short name T397
Test name
Test status
Simulation time 8419522223 ps
CPU time 8.09 seconds
Started Apr 16 01:04:42 PM PDT 24
Finished Apr 16 01:04:51 PM PDT 24
Peak memory 203984 kb
Host smart-47a28b0a-afc9-491f-a740-d0ea1478735b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37628
67864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3762867864
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.2076441046
Short name T650
Test name
Test status
Simulation time 8413157089 ps
CPU time 8.27 seconds
Started Apr 16 01:04:47 PM PDT 24
Finished Apr 16 01:04:56 PM PDT 24
Peak memory 204020 kb
Host smart-ceeeb9f0-1585-40e8-8a6a-a9901ee27513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20764
41046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.2076441046
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.300444514
Short name T195
Test name
Test status
Simulation time 8385509051 ps
CPU time 7.51 seconds
Started Apr 16 01:04:40 PM PDT 24
Finished Apr 16 01:04:48 PM PDT 24
Peak memory 204032 kb
Host smart-b6e63566-7653-43ab-a7e6-29278cefce16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30044
4514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.300444514
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.2912740426
Short name T583
Test name
Test status
Simulation time 8370402153 ps
CPU time 8.19 seconds
Started Apr 16 01:04:40 PM PDT 24
Finished Apr 16 01:04:49 PM PDT 24
Peak memory 203972 kb
Host smart-bd624286-f2e7-4324-8b04-bd6252fe13e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29127
40426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.2912740426
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.2949232123
Short name T459
Test name
Test status
Simulation time 58359904 ps
CPU time 0.7 seconds
Started Apr 16 01:04:40 PM PDT 24
Finished Apr 16 01:04:42 PM PDT 24
Peak memory 203844 kb
Host smart-38099a2d-4071-4835-9640-449f77c1f1c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29492
32123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.2949232123
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.559421052
Short name T215
Test name
Test status
Simulation time 18673964238 ps
CPU time 33.35 seconds
Started Apr 16 01:04:43 PM PDT 24
Finished Apr 16 01:05:17 PM PDT 24
Peak memory 204324 kb
Host smart-d688aecb-50d0-4231-bbf2-d6519aa672c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55942
1052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.559421052
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.4197140279
Short name T847
Test name
Test status
Simulation time 8402077834 ps
CPU time 7.92 seconds
Started Apr 16 01:04:46 PM PDT 24
Finished Apr 16 01:04:55 PM PDT 24
Peak memory 203948 kb
Host smart-5044df57-8d7c-4b63-b215-4fd88a0fa877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41971
40279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.4197140279
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.1964922085
Short name T1140
Test name
Test status
Simulation time 8426245775 ps
CPU time 8 seconds
Started Apr 16 01:04:40 PM PDT 24
Finished Apr 16 01:04:49 PM PDT 24
Peak memory 204024 kb
Host smart-96a3b725-127e-491c-8757-d08047a61c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19649
22085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1964922085
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.1840965068
Short name T333
Test name
Test status
Simulation time 8411969459 ps
CPU time 8.51 seconds
Started Apr 16 01:04:42 PM PDT 24
Finished Apr 16 01:04:51 PM PDT 24
Peak memory 204040 kb
Host smart-f357c860-ca9a-4413-a0aa-4b63b5012d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18409
65068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.1840965068
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.189909236
Short name T1295
Test name
Test status
Simulation time 8368287960 ps
CPU time 8.84 seconds
Started Apr 16 01:04:40 PM PDT 24
Finished Apr 16 01:04:50 PM PDT 24
Peak memory 203988 kb
Host smart-e873a932-1a13-450c-92bb-20016305a847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18990
9236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.189909236
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.747318360
Short name T632
Test name
Test status
Simulation time 8394973569 ps
CPU time 8.08 seconds
Started Apr 16 01:04:44 PM PDT 24
Finished Apr 16 01:04:53 PM PDT 24
Peak memory 204080 kb
Host smart-c513a40b-50db-4353-8f94-c9b195155212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74731
8360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.747318360
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.1098421153
Short name T1000
Test name
Test status
Simulation time 8448512574 ps
CPU time 8.39 seconds
Started Apr 16 01:04:38 PM PDT 24
Finished Apr 16 01:04:48 PM PDT 24
Peak memory 204020 kb
Host smart-6fb07ce3-376e-48a4-b56d-4c933258db13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10984
21153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.1098421153
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.3395226372
Short name T785
Test name
Test status
Simulation time 8416196263 ps
CPU time 8.9 seconds
Started Apr 16 01:04:38 PM PDT 24
Finished Apr 16 01:04:48 PM PDT 24
Peak memory 203980 kb
Host smart-53d5b9a3-f0aa-4194-9737-80fb73cd9fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33952
26372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.3395226372
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.139902967
Short name T771
Test name
Test status
Simulation time 8377839884 ps
CPU time 8.41 seconds
Started Apr 16 01:04:40 PM PDT 24
Finished Apr 16 01:04:49 PM PDT 24
Peak memory 204032 kb
Host smart-33616121-4b52-4c58-9774-cc203024fb9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13990
2967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.139902967
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.2362590445
Short name T1261
Test name
Test status
Simulation time 8462602932 ps
CPU time 8.17 seconds
Started Apr 16 01:04:44 PM PDT 24
Finished Apr 16 01:04:54 PM PDT 24
Peak memory 203976 kb
Host smart-a1e9d16d-a1fe-400a-81b1-6c1c5c27167f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2362590445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.2362590445
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.420549072
Short name T618
Test name
Test status
Simulation time 8420768936 ps
CPU time 8.02 seconds
Started Apr 16 01:04:48 PM PDT 24
Finished Apr 16 01:04:57 PM PDT 24
Peak memory 203984 kb
Host smart-cbc4961b-674c-42e8-9992-1ff7aa9cbe96
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=420549072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.420549072
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.random_length_in_trans.3124468217
Short name T386
Test name
Test status
Simulation time 8406541711 ps
CPU time 7.7 seconds
Started Apr 16 01:04:48 PM PDT 24
Finished Apr 16 01:04:56 PM PDT 24
Peak memory 203980 kb
Host smart-c9357ff7-6e09-4958-8a96-a4528598ab93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31244
68217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.3124468217
Directory /workspace/37.random_length_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3098533330
Short name T1111
Test name
Test status
Simulation time 8407018923 ps
CPU time 8.1 seconds
Started Apr 16 01:04:44 PM PDT 24
Finished Apr 16 01:04:53 PM PDT 24
Peak memory 203980 kb
Host smart-674e8cde-b1be-4cd9-a8bc-3a75497c08c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30985
33330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3098533330
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_enable.3386783787
Short name T986
Test name
Test status
Simulation time 8380932366 ps
CPU time 7.65 seconds
Started Apr 16 01:04:47 PM PDT 24
Finished Apr 16 01:04:56 PM PDT 24
Peak memory 203988 kb
Host smart-dae27404-3d1a-4c0e-8de7-fe240dc53c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33867
83787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.3386783787
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.1400491515
Short name T363
Test name
Test status
Simulation time 126653236 ps
CPU time 1.16 seconds
Started Apr 16 01:04:44 PM PDT 24
Finished Apr 16 01:04:46 PM PDT 24
Peak memory 204212 kb
Host smart-a9269ab7-5979-4bdf-882f-a05ee5ea4d9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14004
91515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.1400491515
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.2851764095
Short name T144
Test name
Test status
Simulation time 8450060997 ps
CPU time 7.86 seconds
Started Apr 16 01:04:48 PM PDT 24
Finished Apr 16 01:04:57 PM PDT 24
Peak memory 204024 kb
Host smart-39f42fce-91d8-4d90-b3cc-e007d464005f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28517
64095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.2851764095
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.4072666857
Short name T473
Test name
Test status
Simulation time 8411555820 ps
CPU time 8.06 seconds
Started Apr 16 01:04:45 PM PDT 24
Finished Apr 16 01:04:54 PM PDT 24
Peak memory 203944 kb
Host smart-7e44b5d9-d362-4a4e-b042-87737c58d451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40726
66857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.4072666857
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.756167110
Short name T612
Test name
Test status
Simulation time 8463190463 ps
CPU time 10.34 seconds
Started Apr 16 01:04:46 PM PDT 24
Finished Apr 16 01:04:57 PM PDT 24
Peak memory 204032 kb
Host smart-fd18cdb9-c5a2-48ec-bd39-743cd0a20f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75616
7110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.756167110
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1499346733
Short name T1297
Test name
Test status
Simulation time 8413095480 ps
CPU time 7.92 seconds
Started Apr 16 01:04:46 PM PDT 24
Finished Apr 16 01:04:54 PM PDT 24
Peak memory 204016 kb
Host smart-89f24bd3-4ac2-4759-83cd-1a13e1defe02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14993
46733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1499346733
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.1977027390
Short name T506
Test name
Test status
Simulation time 8446422688 ps
CPU time 8.69 seconds
Started Apr 16 01:04:43 PM PDT 24
Finished Apr 16 01:04:52 PM PDT 24
Peak memory 204028 kb
Host smart-e6a140cb-08e9-44a4-aced-7282b4e4dd3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19770
27390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.1977027390
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.1161638487
Short name T120
Test name
Test status
Simulation time 8434969644 ps
CPU time 8.01 seconds
Started Apr 16 01:04:48 PM PDT 24
Finished Apr 16 01:04:57 PM PDT 24
Peak memory 204024 kb
Host smart-890ce529-e45c-49b9-babc-5975f9c52a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11616
38487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.1161638487
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.3455729095
Short name T1235
Test name
Test status
Simulation time 8415295125 ps
CPU time 7.97 seconds
Started Apr 16 01:04:45 PM PDT 24
Finished Apr 16 01:04:54 PM PDT 24
Peak memory 203908 kb
Host smart-69b0efbe-8d7e-4651-af34-14341532c223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34557
29095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.3455729095
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.2242989617
Short name T565
Test name
Test status
Simulation time 8393223135 ps
CPU time 7.91 seconds
Started Apr 16 01:04:45 PM PDT 24
Finished Apr 16 01:04:54 PM PDT 24
Peak memory 204012 kb
Host smart-73152037-5740-4d6f-917c-61aa3b8010d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22429
89617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2242989617
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.1561677108
Short name T187
Test name
Test status
Simulation time 8406023087 ps
CPU time 8.31 seconds
Started Apr 16 01:04:48 PM PDT 24
Finished Apr 16 01:04:58 PM PDT 24
Peak memory 203928 kb
Host smart-4931df80-082e-4f65-89cb-dae63b077999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15616
77108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.1561677108
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.4089776870
Short name T737
Test name
Test status
Simulation time 8364101083 ps
CPU time 8.51 seconds
Started Apr 16 01:04:43 PM PDT 24
Finished Apr 16 01:04:53 PM PDT 24
Peak memory 204048 kb
Host smart-6936e9ef-1455-42c3-a464-240e75594465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40897
76870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.4089776870
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.1061730384
Short name T807
Test name
Test status
Simulation time 23723788496 ps
CPU time 47.71 seconds
Started Apr 16 01:04:43 PM PDT 24
Finished Apr 16 01:05:32 PM PDT 24
Peak memory 204324 kb
Host smart-786475ff-629d-4988-bed0-d8df1853b1e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10617
30384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.1061730384
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.1174232070
Short name T516
Test name
Test status
Simulation time 8397853109 ps
CPU time 8.26 seconds
Started Apr 16 01:04:47 PM PDT 24
Finished Apr 16 01:04:56 PM PDT 24
Peak memory 204028 kb
Host smart-6e24a658-bb3e-4330-991e-0dd986f84042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11742
32070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.1174232070
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.951073260
Short name T978
Test name
Test status
Simulation time 8391517669 ps
CPU time 7.78 seconds
Started Apr 16 01:04:46 PM PDT 24
Finished Apr 16 01:04:55 PM PDT 24
Peak memory 203944 kb
Host smart-735032bc-ac47-4c7e-9e85-a8f5a1049953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95107
3260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.951073260
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.1612525442
Short name T890
Test name
Test status
Simulation time 8402336886 ps
CPU time 8.49 seconds
Started Apr 16 01:04:50 PM PDT 24
Finished Apr 16 01:04:59 PM PDT 24
Peak memory 204020 kb
Host smart-d57b8780-c03c-4dc1-aaf6-c4d91585cddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16125
25442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.1612525442
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.234775500
Short name T1278
Test name
Test status
Simulation time 8373065642 ps
CPU time 8.1 seconds
Started Apr 16 01:04:45 PM PDT 24
Finished Apr 16 01:04:55 PM PDT 24
Peak memory 204044 kb
Host smart-408b3dd3-883b-4343-bebc-7f7d75c51787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23477
5500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.234775500
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2823001382
Short name T1335
Test name
Test status
Simulation time 8374322092 ps
CPU time 8.95 seconds
Started Apr 16 01:04:45 PM PDT 24
Finished Apr 16 01:04:55 PM PDT 24
Peak memory 204044 kb
Host smart-4fce6af4-bd33-4ac1-b21e-7928da4f7782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28230
01382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2823001382
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.2587871960
Short name T1178
Test name
Test status
Simulation time 8402812143 ps
CPU time 9.69 seconds
Started Apr 16 01:04:42 PM PDT 24
Finished Apr 16 01:04:53 PM PDT 24
Peak memory 203976 kb
Host smart-e328ed91-c2e2-4a2f-aa92-0cedd79ce6f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25878
71960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.2587871960
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.3413547332
Short name T1097
Test name
Test status
Simulation time 8416828685 ps
CPU time 7.76 seconds
Started Apr 16 01:04:49 PM PDT 24
Finished Apr 16 01:04:58 PM PDT 24
Peak memory 203984 kb
Host smart-0ff1584e-0a52-4a10-930b-fb6bfeee3a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34135
47332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.3413547332
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.656627407
Short name T1354
Test name
Test status
Simulation time 8469252551 ps
CPU time 10.01 seconds
Started Apr 16 01:04:54 PM PDT 24
Finished Apr 16 01:05:05 PM PDT 24
Peak memory 204052 kb
Host smart-6d9804b1-2add-479f-b928-985a54bb3a4f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=656627407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.656627407
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.2857584818
Short name T961
Test name
Test status
Simulation time 8403671379 ps
CPU time 7.81 seconds
Started Apr 16 01:04:50 PM PDT 24
Finished Apr 16 01:04:59 PM PDT 24
Peak memory 204016 kb
Host smart-e80d166f-f698-4ba4-9168-7ac4d3d4b338
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2857584818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.2857584818
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.1364845130
Short name T853
Test name
Test status
Simulation time 8408074911 ps
CPU time 7.64 seconds
Started Apr 16 01:04:51 PM PDT 24
Finished Apr 16 01:04:59 PM PDT 24
Peak memory 204044 kb
Host smart-fd1738a4-1809-413e-b880-abf25741bf17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13648
45130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.1364845130
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.3116277980
Short name T519
Test name
Test status
Simulation time 8451517605 ps
CPU time 8.44 seconds
Started Apr 16 01:04:45 PM PDT 24
Finished Apr 16 01:04:55 PM PDT 24
Peak memory 203988 kb
Host smart-f6697e63-c422-4362-b34d-35a807a87d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31162
77980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3116277980
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_enable.2574045073
Short name T305
Test name
Test status
Simulation time 8389691750 ps
CPU time 8.59 seconds
Started Apr 16 01:04:43 PM PDT 24
Finished Apr 16 01:04:53 PM PDT 24
Peak memory 204012 kb
Host smart-1e83efa0-478c-4c58-aab8-ab8e15077404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25740
45073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.2574045073
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.871704585
Short name T1096
Test name
Test status
Simulation time 189312868 ps
CPU time 2 seconds
Started Apr 16 01:04:49 PM PDT 24
Finished Apr 16 01:04:52 PM PDT 24
Peak memory 203752 kb
Host smart-7d0cf020-9fa6-497d-a594-01e222affcf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87170
4585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.871704585
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.3301046143
Short name T129
Test name
Test status
Simulation time 8382788577 ps
CPU time 10.38 seconds
Started Apr 16 01:04:56 PM PDT 24
Finished Apr 16 01:05:08 PM PDT 24
Peak memory 203996 kb
Host smart-8a85c772-f887-4337-8225-00fb4e04d67c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33010
46143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.3301046143
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.2339998265
Short name T693
Test name
Test status
Simulation time 8372047419 ps
CPU time 8.87 seconds
Started Apr 16 01:04:51 PM PDT 24
Finished Apr 16 01:05:00 PM PDT 24
Peak memory 203968 kb
Host smart-0a845d1f-26ea-4953-ac7d-b2045287d4ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23399
98265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.2339998265
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.3348207781
Short name T1357
Test name
Test status
Simulation time 8384360000 ps
CPU time 8.82 seconds
Started Apr 16 01:04:46 PM PDT 24
Finished Apr 16 01:04:56 PM PDT 24
Peak memory 203940 kb
Host smart-04fc22ca-2f1a-4a4d-aa4c-06cb9c431343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33482
07781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.3348207781
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1256229722
Short name T613
Test name
Test status
Simulation time 8416006030 ps
CPU time 7.95 seconds
Started Apr 16 01:04:47 PM PDT 24
Finished Apr 16 01:04:56 PM PDT 24
Peak memory 204032 kb
Host smart-3762cea5-3a99-475a-85d7-8d8f4e391e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12562
29722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1256229722
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.4064426103
Short name T294
Test name
Test status
Simulation time 8381854807 ps
CPU time 10.14 seconds
Started Apr 16 01:04:49 PM PDT 24
Finished Apr 16 01:05:01 PM PDT 24
Peak memory 203656 kb
Host smart-401eba07-8e35-4301-a718-56914eb078cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40644
26103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.4064426103
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.2384230187
Short name T858
Test name
Test status
Simulation time 8398266904 ps
CPU time 8.5 seconds
Started Apr 16 01:04:45 PM PDT 24
Finished Apr 16 01:04:54 PM PDT 24
Peak memory 203948 kb
Host smart-39236af8-500c-488f-87d8-336dcdb712d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23842
30187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.2384230187
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.3867107465
Short name T445
Test name
Test status
Simulation time 8407186010 ps
CPU time 9.7 seconds
Started Apr 16 01:04:48 PM PDT 24
Finished Apr 16 01:04:58 PM PDT 24
Peak memory 204028 kb
Host smart-a0af9921-a7d9-4190-aa6d-179a54babbee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38671
07465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.3867107465
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.1762860105
Short name T521
Test name
Test status
Simulation time 8375140133 ps
CPU time 7.86 seconds
Started Apr 16 01:04:52 PM PDT 24
Finished Apr 16 01:05:01 PM PDT 24
Peak memory 203948 kb
Host smart-31209b4e-d95f-4ca9-ad06-e2f2bb28961a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17628
60105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.1762860105
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.4085852628
Short name T654
Test name
Test status
Simulation time 8375035942 ps
CPU time 8.05 seconds
Started Apr 16 01:04:48 PM PDT 24
Finished Apr 16 01:04:57 PM PDT 24
Peak memory 204032 kb
Host smart-da6e900d-53ae-494c-86c1-0272ea235c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40858
52628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.4085852628
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.636762992
Short name T1344
Test name
Test status
Simulation time 49848357 ps
CPU time 0.69 seconds
Started Apr 16 01:04:52 PM PDT 24
Finished Apr 16 01:04:53 PM PDT 24
Peak memory 203796 kb
Host smart-68501f27-c5f8-4709-be49-ce5f44e98c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63676
2992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.636762992
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.2247961901
Short name T13
Test name
Test status
Simulation time 22951420736 ps
CPU time 41.62 seconds
Started Apr 16 01:04:50 PM PDT 24
Finished Apr 16 01:05:33 PM PDT 24
Peak memory 204328 kb
Host smart-8c138e80-1263-4a9e-9a6b-a19e98a64ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22479
61901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.2247961901
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.431238960
Short name T546
Test name
Test status
Simulation time 8406780226 ps
CPU time 8.3 seconds
Started Apr 16 01:04:50 PM PDT 24
Finished Apr 16 01:04:59 PM PDT 24
Peak memory 204012 kb
Host smart-b43dba23-5fa8-4fbe-ba1d-5ee767bba552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43123
8960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.431238960
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.559027897
Short name T820
Test name
Test status
Simulation time 8421644216 ps
CPU time 8.35 seconds
Started Apr 16 01:04:50 PM PDT 24
Finished Apr 16 01:04:59 PM PDT 24
Peak memory 204012 kb
Host smart-10317ccf-8142-4765-8127-43ac2ec0e4d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55902
7897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.559027897
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.772052276
Short name T744
Test name
Test status
Simulation time 8399584099 ps
CPU time 7.63 seconds
Started Apr 16 01:04:56 PM PDT 24
Finished Apr 16 01:05:05 PM PDT 24
Peak memory 204004 kb
Host smart-27281748-d2a4-43f5-9c35-8a5ce73af5a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77205
2276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.772052276
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.1385855087
Short name T1272
Test name
Test status
Simulation time 8429345930 ps
CPU time 8.6 seconds
Started Apr 16 01:04:50 PM PDT 24
Finished Apr 16 01:05:00 PM PDT 24
Peak memory 204016 kb
Host smart-ab5f53c1-9569-43ac-9631-0f779c60ae0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13858
55087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.1385855087
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.534907060
Short name T400
Test name
Test status
Simulation time 8375705539 ps
CPU time 9.94 seconds
Started Apr 16 01:04:55 PM PDT 24
Finished Apr 16 01:05:07 PM PDT 24
Peak memory 203992 kb
Host smart-1abe0efb-5ee7-4772-b1cc-4b964264de00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53490
7060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.534907060
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.4069432626
Short name T790
Test name
Test status
Simulation time 8471702965 ps
CPU time 9.99 seconds
Started Apr 16 01:04:44 PM PDT 24
Finished Apr 16 01:04:55 PM PDT 24
Peak memory 203948 kb
Host smart-d9d03ae8-61ed-4d32-b29b-3e4348e97615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40694
32626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.4069432626
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.2214686750
Short name T313
Test name
Test status
Simulation time 8388767827 ps
CPU time 8.28 seconds
Started Apr 16 01:04:56 PM PDT 24
Finished Apr 16 01:05:06 PM PDT 24
Peak memory 203992 kb
Host smart-2b444e1a-c849-4b2a-894e-34ef97b48b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22146
86750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.2214686750
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.1625494012
Short name T375
Test name
Test status
Simulation time 8380639620 ps
CPU time 8.44 seconds
Started Apr 16 01:04:48 PM PDT 24
Finished Apr 16 01:04:58 PM PDT 24
Peak memory 204000 kb
Host smart-747ac782-40a0-427c-8f82-d2a724a378c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16254
94012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.1625494012
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.863520809
Short name T1064
Test name
Test status
Simulation time 8462738213 ps
CPU time 8.47 seconds
Started Apr 16 01:04:58 PM PDT 24
Finished Apr 16 01:05:07 PM PDT 24
Peak memory 203956 kb
Host smart-3e88b36c-36bd-4c42-b823-e73e3c4b1eff
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=863520809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.863520809
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.316333431
Short name T1151
Test name
Test status
Simulation time 8385854789 ps
CPU time 8.1 seconds
Started Apr 16 01:04:54 PM PDT 24
Finished Apr 16 01:05:03 PM PDT 24
Peak memory 204052 kb
Host smart-0778e89e-785d-4919-8f87-9d03bfe68865
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=316333431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.316333431
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.2547416454
Short name T380
Test name
Test status
Simulation time 8433361942 ps
CPU time 9.4 seconds
Started Apr 16 01:04:54 PM PDT 24
Finished Apr 16 01:05:05 PM PDT 24
Peak memory 203972 kb
Host smart-cc3b78b4-1302-44b5-8c5b-25dad3d9ea22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25474
16454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.2547416454
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.3781511678
Short name T1191
Test name
Test status
Simulation time 8380184060 ps
CPU time 8.79 seconds
Started Apr 16 01:04:51 PM PDT 24
Finished Apr 16 01:05:00 PM PDT 24
Peak memory 204024 kb
Host smart-7c14b470-cd39-4104-b2df-74c86337bc8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37815
11678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.3781511678
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_enable.960055521
Short name T1127
Test name
Test status
Simulation time 8394953460 ps
CPU time 7.46 seconds
Started Apr 16 01:04:47 PM PDT 24
Finished Apr 16 01:04:56 PM PDT 24
Peak memory 204052 kb
Host smart-b067bd21-f828-4261-9ad2-0731ed315ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96005
5521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.960055521
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.1997444611
Short name T523
Test name
Test status
Simulation time 245244700 ps
CPU time 1.85 seconds
Started Apr 16 01:04:56 PM PDT 24
Finished Apr 16 01:04:59 PM PDT 24
Peak memory 204060 kb
Host smart-00da455f-f7cc-4db1-810d-b98f7d1d3ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19974
44611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.1997444611
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.3572366719
Short name T40
Test name
Test status
Simulation time 8389182145 ps
CPU time 7.63 seconds
Started Apr 16 01:05:00 PM PDT 24
Finished Apr 16 01:05:09 PM PDT 24
Peak memory 204016 kb
Host smart-fe6578ab-3e42-4ef9-8d38-3d3b6aa14675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35723
66719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.3572366719
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.1444838458
Short name T962
Test name
Test status
Simulation time 8369179138 ps
CPU time 7.67 seconds
Started Apr 16 01:04:54 PM PDT 24
Finished Apr 16 01:05:03 PM PDT 24
Peak memory 204040 kb
Host smart-867bc07e-377f-4505-82c3-17c32a0d9378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14448
38458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1444838458
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.2529780961
Short name T1339
Test name
Test status
Simulation time 8463493272 ps
CPU time 9.57 seconds
Started Apr 16 01:04:56 PM PDT 24
Finished Apr 16 01:05:07 PM PDT 24
Peak memory 203996 kb
Host smart-99468315-c1a2-40bc-86bb-e64529900d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25297
80961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.2529780961
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.4127420194
Short name T624
Test name
Test status
Simulation time 8412746927 ps
CPU time 8.43 seconds
Started Apr 16 01:04:52 PM PDT 24
Finished Apr 16 01:05:01 PM PDT 24
Peak memory 203948 kb
Host smart-c0570e2a-461f-4417-bb06-b0116db139c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41274
20194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.4127420194
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.2858940882
Short name T1267
Test name
Test status
Simulation time 8367584209 ps
CPU time 9.87 seconds
Started Apr 16 01:04:50 PM PDT 24
Finished Apr 16 01:05:01 PM PDT 24
Peak memory 204000 kb
Host smart-fb3728f9-84b9-4137-969f-8410b24867ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28589
40882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.2858940882
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.3632343530
Short name T117
Test name
Test status
Simulation time 8470298957 ps
CPU time 10.01 seconds
Started Apr 16 01:04:56 PM PDT 24
Finished Apr 16 01:05:07 PM PDT 24
Peak memory 204004 kb
Host smart-25cb6df3-dbb3-46f6-adc0-f5f6e9b5443a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36323
43530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3632343530
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.3184021370
Short name T345
Test name
Test status
Simulation time 8410667885 ps
CPU time 9.49 seconds
Started Apr 16 01:04:49 PM PDT 24
Finished Apr 16 01:04:59 PM PDT 24
Peak memory 204036 kb
Host smart-d247bdfc-d77f-45bf-acf7-b74def1c287f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31840
21370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.3184021370
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.2083574977
Short name T780
Test name
Test status
Simulation time 8411468672 ps
CPU time 8.74 seconds
Started Apr 16 01:04:54 PM PDT 24
Finished Apr 16 01:05:04 PM PDT 24
Peak memory 204048 kb
Host smart-53de1e7e-6aa4-4239-a456-27462339827e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20835
74977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.2083574977
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1698067447
Short name T724
Test name
Test status
Simulation time 8403945268 ps
CPU time 8.84 seconds
Started Apr 16 01:04:56 PM PDT 24
Finished Apr 16 01:05:07 PM PDT 24
Peak memory 204048 kb
Host smart-589540a5-a8d6-4310-88cc-eb38c0caf644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16980
67447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1698067447
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.2886866731
Short name T317
Test name
Test status
Simulation time 8391813708 ps
CPU time 8.63 seconds
Started Apr 16 01:04:57 PM PDT 24
Finished Apr 16 01:05:07 PM PDT 24
Peak memory 204004 kb
Host smart-0a14f058-0e1f-4fc6-b50a-d7cb173ac9a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28868
66731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.2886866731
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.1989443242
Short name T777
Test name
Test status
Simulation time 41756620 ps
CPU time 0.66 seconds
Started Apr 16 01:04:53 PM PDT 24
Finished Apr 16 01:04:55 PM PDT 24
Peak memory 203864 kb
Host smart-c3a9d803-e2ef-4687-8eaa-c8410e689e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19894
43242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.1989443242
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.1178954947
Short name T1054
Test name
Test status
Simulation time 21190704543 ps
CPU time 39.68 seconds
Started Apr 16 01:04:56 PM PDT 24
Finished Apr 16 01:05:37 PM PDT 24
Peak memory 204292 kb
Host smart-a7b389f3-ae08-4ca4-aa78-17c095f255ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11789
54947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.1178954947
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.3540630541
Short name T55
Test name
Test status
Simulation time 8408662575 ps
CPU time 8.29 seconds
Started Apr 16 01:04:51 PM PDT 24
Finished Apr 16 01:05:00 PM PDT 24
Peak memory 203980 kb
Host smart-26c1d281-b0c4-4e84-b2ce-dca44778be17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35406
30541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.3540630541
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1852430451
Short name T230
Test name
Test status
Simulation time 8483611582 ps
CPU time 8.63 seconds
Started Apr 16 01:04:54 PM PDT 24
Finished Apr 16 01:05:04 PM PDT 24
Peak memory 204048 kb
Host smart-eae6f560-bd82-4431-8bd1-3fb5c1d09192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18524
30451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1852430451
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.234968473
Short name T644
Test name
Test status
Simulation time 8397180222 ps
CPU time 8.46 seconds
Started Apr 16 01:04:50 PM PDT 24
Finished Apr 16 01:04:59 PM PDT 24
Peak memory 203908 kb
Host smart-11b7b3e8-e209-41d4-8e13-ad936532fd93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23496
8473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.234968473
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.3607433658
Short name T672
Test name
Test status
Simulation time 8379560719 ps
CPU time 8.56 seconds
Started Apr 16 01:04:56 PM PDT 24
Finished Apr 16 01:05:06 PM PDT 24
Peak memory 204032 kb
Host smart-9e205192-a3b6-4f72-8011-57aa9839e1df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36074
33658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.3607433658
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.60696632
Short name T868
Test name
Test status
Simulation time 8366711237 ps
CPU time 8.27 seconds
Started Apr 16 01:05:04 PM PDT 24
Finished Apr 16 01:05:14 PM PDT 24
Peak memory 203960 kb
Host smart-eb2bafb0-97d1-407d-a288-bd32206081a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60696
632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.60696632
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.1733744173
Short name T1137
Test name
Test status
Simulation time 8442505041 ps
CPU time 7.66 seconds
Started Apr 16 01:04:46 PM PDT 24
Finished Apr 16 01:04:55 PM PDT 24
Peak memory 203968 kb
Host smart-503607f0-c04a-43c7-b1e3-6f0ac8a862e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17337
44173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1733744173
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.1195407110
Short name T476
Test name
Test status
Simulation time 8370791425 ps
CPU time 8.38 seconds
Started Apr 16 01:04:52 PM PDT 24
Finished Apr 16 01:05:01 PM PDT 24
Peak memory 204028 kb
Host smart-874cc292-fc66-49df-8a60-7405f6112f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11954
07110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.1195407110
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.3693835206
Short name T474
Test name
Test status
Simulation time 8370549362 ps
CPU time 8.24 seconds
Started Apr 16 01:04:49 PM PDT 24
Finished Apr 16 01:04:58 PM PDT 24
Peak memory 204008 kb
Host smart-940abfd4-4bf8-4c21-9943-83b8ccbe22ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36938
35206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.3693835206
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.942779440
Short name T449
Test name
Test status
Simulation time 8465770830 ps
CPU time 8.14 seconds
Started Apr 16 01:01:34 PM PDT 24
Finished Apr 16 01:01:44 PM PDT 24
Peak memory 204056 kb
Host smart-b02df1f3-3983-4c1c-8710-1d9c933399ff
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=942779440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.942779440
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.2666039617
Short name T439
Test name
Test status
Simulation time 8381397596 ps
CPU time 8.46 seconds
Started Apr 16 01:01:36 PM PDT 24
Finished Apr 16 01:01:45 PM PDT 24
Peak memory 203972 kb
Host smart-30bbfaec-aec0-4d9a-a5f5-f3169935069a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2666039617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.2666039617
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.2636954116
Short name T1215
Test name
Test status
Simulation time 8403543836 ps
CPU time 8.54 seconds
Started Apr 16 01:01:34 PM PDT 24
Finished Apr 16 01:01:44 PM PDT 24
Peak memory 203940 kb
Host smart-d28712b2-8219-456f-8901-1c633bcaa2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26369
54116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.2636954116
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.2336417923
Short name T1282
Test name
Test status
Simulation time 8387650513 ps
CPU time 8.86 seconds
Started Apr 16 01:01:32 PM PDT 24
Finished Apr 16 01:01:41 PM PDT 24
Peak memory 204008 kb
Host smart-96571c7a-7f6a-417f-b04e-05911ba305f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23364
17923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.2336417923
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_enable.1054344709
Short name T538
Test name
Test status
Simulation time 8384427133 ps
CPU time 8.13 seconds
Started Apr 16 01:01:34 PM PDT 24
Finished Apr 16 01:01:42 PM PDT 24
Peak memory 203980 kb
Host smart-1e624d21-91e1-4bca-a481-91c46e1273a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10543
44709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1054344709
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.483238029
Short name T1341
Test name
Test status
Simulation time 102384918 ps
CPU time 1.26 seconds
Started Apr 16 01:01:29 PM PDT 24
Finished Apr 16 01:01:31 PM PDT 24
Peak memory 204088 kb
Host smart-f32307f8-121f-4ffd-b8da-135e35f4b7bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48323
8029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.483238029
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.1059484188
Short name T429
Test name
Test status
Simulation time 8398231465 ps
CPU time 8.71 seconds
Started Apr 16 01:01:36 PM PDT 24
Finished Apr 16 01:01:46 PM PDT 24
Peak memory 204048 kb
Host smart-60957b55-2eb6-4e6b-aa20-66aad5341bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10594
84188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1059484188
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.531677110
Short name T4
Test name
Test status
Simulation time 8368338360 ps
CPU time 8.25 seconds
Started Apr 16 01:01:36 PM PDT 24
Finished Apr 16 01:01:45 PM PDT 24
Peak memory 203860 kb
Host smart-d411115e-29cf-43f8-bbe5-13bacce04190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53167
7110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.531677110
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.93390854
Short name T1164
Test name
Test status
Simulation time 8414193987 ps
CPU time 9.18 seconds
Started Apr 16 01:01:33 PM PDT 24
Finished Apr 16 01:01:42 PM PDT 24
Peak memory 204024 kb
Host smart-905a75f7-4ba8-4bcd-91a8-43b2fcb1d6c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93390
854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.93390854
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.1921518593
Short name T1219
Test name
Test status
Simulation time 8419621888 ps
CPU time 9.91 seconds
Started Apr 16 01:01:29 PM PDT 24
Finished Apr 16 01:01:40 PM PDT 24
Peak memory 204008 kb
Host smart-5331b229-6652-4a63-9728-540a1048975a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19215
18593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.1921518593
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1812483218
Short name T284
Test name
Test status
Simulation time 8371611692 ps
CPU time 9.98 seconds
Started Apr 16 01:01:29 PM PDT 24
Finished Apr 16 01:01:40 PM PDT 24
Peak memory 204012 kb
Host smart-04b62bc4-d547-4b08-afc7-4ff42ba7eedf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18124
83218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1812483218
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.860797013
Short name T105
Test name
Test status
Simulation time 8400827570 ps
CPU time 8.18 seconds
Started Apr 16 01:01:31 PM PDT 24
Finished Apr 16 01:01:40 PM PDT 24
Peak memory 204016 kb
Host smart-1868c161-02f3-4b66-b795-5400479c8db5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86079
7013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.860797013
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.687309087
Short name T356
Test name
Test status
Simulation time 8390356110 ps
CPU time 10.01 seconds
Started Apr 16 01:01:31 PM PDT 24
Finished Apr 16 01:01:42 PM PDT 24
Peak memory 203980 kb
Host smart-c4edd641-12c6-45d1-b7b3-f037fbeb5e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68730
9087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.687309087
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.777817862
Short name T452
Test name
Test status
Simulation time 8424562967 ps
CPU time 8.12 seconds
Started Apr 16 01:01:31 PM PDT 24
Finished Apr 16 01:01:39 PM PDT 24
Peak memory 204020 kb
Host smart-f8e194b3-4b98-4ce7-a2f2-8d5e257f29cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77781
7862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.777817862
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.1309126458
Short name T968
Test name
Test status
Simulation time 8377442383 ps
CPU time 7.47 seconds
Started Apr 16 01:01:34 PM PDT 24
Finished Apr 16 01:01:42 PM PDT 24
Peak memory 204012 kb
Host smart-ab8724b4-ce39-4f51-9894-f53336964822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13091
26458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.1309126458
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.988780218
Short name T24
Test name
Test status
Simulation time 8391470542 ps
CPU time 7.6 seconds
Started Apr 16 01:01:34 PM PDT 24
Finished Apr 16 01:01:43 PM PDT 24
Peak memory 204044 kb
Host smart-ad79527d-5a21-4e2d-b0d4-c2b467d1e476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98878
0218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.988780218
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.1405029503
Short name T1276
Test name
Test status
Simulation time 49130947 ps
CPU time 0.67 seconds
Started Apr 16 01:01:34 PM PDT 24
Finished Apr 16 01:01:35 PM PDT 24
Peak memory 203884 kb
Host smart-70392749-ce9a-4fd3-abaa-149830bf988b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14050
29503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.1405029503
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.870603384
Short name T235
Test name
Test status
Simulation time 29231684527 ps
CPU time 65.71 seconds
Started Apr 16 01:01:31 PM PDT 24
Finished Apr 16 01:02:37 PM PDT 24
Peak memory 204292 kb
Host smart-00d3be4f-d4af-4b4b-bd45-9ab4fa6f6fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87060
3384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.870603384
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.3864127758
Short name T564
Test name
Test status
Simulation time 8416420535 ps
CPU time 9.3 seconds
Started Apr 16 01:01:35 PM PDT 24
Finished Apr 16 01:01:45 PM PDT 24
Peak memory 204008 kb
Host smart-1ac764d6-09dd-408a-8b74-bd990222d081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38641
27758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3864127758
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.4086244958
Short name T1340
Test name
Test status
Simulation time 8424202281 ps
CPU time 9.71 seconds
Started Apr 16 01:01:35 PM PDT 24
Finished Apr 16 01:01:45 PM PDT 24
Peak memory 204024 kb
Host smart-72da393e-965f-48bb-9791-023b09f3a516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40862
44958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.4086244958
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.2954742184
Short name T781
Test name
Test status
Simulation time 8415145546 ps
CPU time 8.71 seconds
Started Apr 16 01:01:35 PM PDT 24
Finished Apr 16 01:01:45 PM PDT 24
Peak memory 204048 kb
Host smart-f50a5c29-b726-4e6b-8310-f4c767a48183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29547
42184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.2954742184
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.3174078130
Short name T66
Test name
Test status
Simulation time 167217856 ps
CPU time 0.97 seconds
Started Apr 16 01:01:42 PM PDT 24
Finished Apr 16 01:01:43 PM PDT 24
Peak memory 220284 kb
Host smart-1db5ccbe-cb5d-4e6d-a3f2-b888219e5e5b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3174078130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3174078130
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.4251567226
Short name T913
Test name
Test status
Simulation time 8389046698 ps
CPU time 9.8 seconds
Started Apr 16 01:01:36 PM PDT 24
Finished Apr 16 01:01:46 PM PDT 24
Peak memory 203824 kb
Host smart-363aaaec-d85c-477d-aa03-7eac137cb2ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42515
67226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.4251567226
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.3026659514
Short name T982
Test name
Test status
Simulation time 8376534025 ps
CPU time 7.75 seconds
Started Apr 16 01:01:34 PM PDT 24
Finished Apr 16 01:01:42 PM PDT 24
Peak memory 203996 kb
Host smart-2c2b9306-86be-43d9-980b-273823bee455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30266
59514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.3026659514
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.2105279686
Short name T53
Test name
Test status
Simulation time 8468099268 ps
CPU time 8.18 seconds
Started Apr 16 01:01:30 PM PDT 24
Finished Apr 16 01:01:39 PM PDT 24
Peak memory 203996 kb
Host smart-7853d0a4-ad91-4cf2-b724-2b5ccc476df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21052
79686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.2105279686
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.4234715232
Short name T604
Test name
Test status
Simulation time 8367475590 ps
CPU time 8.91 seconds
Started Apr 16 01:01:35 PM PDT 24
Finished Apr 16 01:01:45 PM PDT 24
Peak memory 203932 kb
Host smart-82d27ce4-6621-4c30-b8f0-9033cb9813d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42347
15232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.4234715232
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.2106529547
Short name T559
Test name
Test status
Simulation time 8396915235 ps
CPU time 9.46 seconds
Started Apr 16 01:01:35 PM PDT 24
Finished Apr 16 01:01:45 PM PDT 24
Peak memory 203972 kb
Host smart-dcb57aec-f566-4d50-889a-231321fb5bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21065
29547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.2106529547
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.3975339446
Short name T1269
Test name
Test status
Simulation time 8463001623 ps
CPU time 8.13 seconds
Started Apr 16 01:05:00 PM PDT 24
Finished Apr 16 01:05:09 PM PDT 24
Peak memory 204056 kb
Host smart-c83d9753-919e-474f-a8e5-d05c2784357d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3975339446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.3975339446
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.3310301503
Short name T1114
Test name
Test status
Simulation time 8376389809 ps
CPU time 8.14 seconds
Started Apr 16 01:05:04 PM PDT 24
Finished Apr 16 01:05:14 PM PDT 24
Peak memory 203968 kb
Host smart-f05ab8a9-7643-48ff-aeff-24b13644030c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3310301503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.3310301503
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.4138619654
Short name T643
Test name
Test status
Simulation time 8383914956 ps
CPU time 8.25 seconds
Started Apr 16 01:05:02 PM PDT 24
Finished Apr 16 01:05:10 PM PDT 24
Peak memory 204012 kb
Host smart-4d81b661-25af-4f0e-b549-b50712e9e200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41386
19654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.4138619654
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1903877229
Short name T973
Test name
Test status
Simulation time 8400312987 ps
CPU time 7.59 seconds
Started Apr 16 01:04:55 PM PDT 24
Finished Apr 16 01:05:04 PM PDT 24
Peak memory 203960 kb
Host smart-ef42c23a-6a0e-4c8b-a6f8-878f6f7cca6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19038
77229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1903877229
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_enable.4150347930
Short name T436
Test name
Test status
Simulation time 8378347381 ps
CPU time 8.29 seconds
Started Apr 16 01:04:53 PM PDT 24
Finished Apr 16 01:05:03 PM PDT 24
Peak memory 204032 kb
Host smart-670668ff-3394-4b22-91ef-2a11247622e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41503
47930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.4150347930
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.2886615278
Short name T216
Test name
Test status
Simulation time 170607072 ps
CPU time 1.79 seconds
Started Apr 16 01:04:55 PM PDT 24
Finished Apr 16 01:04:59 PM PDT 24
Peak memory 204108 kb
Host smart-91b39243-ec33-433d-aef1-df6f21eed8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28866
15278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2886615278
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.684995066
Short name T920
Test name
Test status
Simulation time 8429298070 ps
CPU time 9.33 seconds
Started Apr 16 01:04:58 PM PDT 24
Finished Apr 16 01:05:08 PM PDT 24
Peak memory 204032 kb
Host smart-76afaa73-ed34-4e19-af48-d2bf5c2554b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68499
5066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.684995066
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.2804839169
Short name T441
Test name
Test status
Simulation time 8362184000 ps
CPU time 9.02 seconds
Started Apr 16 01:04:57 PM PDT 24
Finished Apr 16 01:05:07 PM PDT 24
Peak memory 203936 kb
Host smart-fb54064c-ec00-46b5-b2f0-abf713e34960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28048
39169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.2804839169
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.1527315402
Short name T705
Test name
Test status
Simulation time 8448707830 ps
CPU time 8.53 seconds
Started Apr 16 01:04:54 PM PDT 24
Finished Apr 16 01:05:04 PM PDT 24
Peak memory 204032 kb
Host smart-58ba8807-068e-4e79-995a-a844a6fc52e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15273
15402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1527315402
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.1920939010
Short name T697
Test name
Test status
Simulation time 8414921688 ps
CPU time 8.31 seconds
Started Apr 16 01:04:55 PM PDT 24
Finished Apr 16 01:05:04 PM PDT 24
Peak memory 204040 kb
Host smart-5ad9c73b-8d4b-493e-9ec1-7d12e5cc335a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19209
39010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1920939010
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2088430258
Short name T926
Test name
Test status
Simulation time 8369591746 ps
CPU time 8.98 seconds
Started Apr 16 01:04:57 PM PDT 24
Finished Apr 16 01:05:08 PM PDT 24
Peak memory 203948 kb
Host smart-779c4808-5b3e-48c3-bad0-175f1a576f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20884
30258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2088430258
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.1426651304
Short name T892
Test name
Test status
Simulation time 8407768197 ps
CPU time 7.75 seconds
Started Apr 16 01:04:55 PM PDT 24
Finished Apr 16 01:05:04 PM PDT 24
Peak memory 204028 kb
Host smart-52bca3da-6065-4446-b1a2-4707697acdb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14266
51304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1426651304
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.3892951526
Short name T863
Test name
Test status
Simulation time 8387154238 ps
CPU time 7.93 seconds
Started Apr 16 01:04:54 PM PDT 24
Finished Apr 16 01:05:03 PM PDT 24
Peak memory 203976 kb
Host smart-f3b14b06-bb19-4f5a-8660-0f0628f664da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38929
51526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.3892951526
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.4266043402
Short name T505
Test name
Test status
Simulation time 8393257621 ps
CPU time 9.37 seconds
Started Apr 16 01:04:58 PM PDT 24
Finished Apr 16 01:05:08 PM PDT 24
Peak memory 203968 kb
Host smart-67d0b559-f22c-4513-8d83-49ac2da2d951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42660
43402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.4266043402
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.3726076793
Short name T1284
Test name
Test status
Simulation time 8387663434 ps
CPU time 7.74 seconds
Started Apr 16 01:04:54 PM PDT 24
Finished Apr 16 01:05:02 PM PDT 24
Peak memory 204048 kb
Host smart-89434acf-f5a9-4879-bb5d-289cbcd2a79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37260
76793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.3726076793
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.4086350140
Short name T999
Test name
Test status
Simulation time 8382027751 ps
CPU time 7.69 seconds
Started Apr 16 01:04:55 PM PDT 24
Finished Apr 16 01:05:04 PM PDT 24
Peak memory 204256 kb
Host smart-43b4e52a-82c9-4743-bf13-23807d41f17c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40863
50140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.4086350140
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.4102679293
Short name T914
Test name
Test status
Simulation time 30613544665 ps
CPU time 56.84 seconds
Started Apr 16 01:04:57 PM PDT 24
Finished Apr 16 01:05:55 PM PDT 24
Peak memory 204252 kb
Host smart-dccf13ff-11dc-42ec-833e-4d9c18d01b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41026
79293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.4102679293
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.297084611
Short name T720
Test name
Test status
Simulation time 8387813776 ps
CPU time 8.02 seconds
Started Apr 16 01:04:55 PM PDT 24
Finished Apr 16 01:05:05 PM PDT 24
Peak memory 203988 kb
Host smart-49bc877a-5543-4585-9957-c4b913712de5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29708
4611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.297084611
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.1611754907
Short name T132
Test name
Test status
Simulation time 8389664336 ps
CPU time 7.44 seconds
Started Apr 16 01:04:53 PM PDT 24
Finished Apr 16 01:05:02 PM PDT 24
Peak memory 204044 kb
Host smart-f1b7bf93-b100-4a7e-8e4f-7a5eb0ee4e6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16117
54907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.1611754907
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.1561489220
Short name T915
Test name
Test status
Simulation time 8396905494 ps
CPU time 7.89 seconds
Started Apr 16 01:04:54 PM PDT 24
Finished Apr 16 01:05:03 PM PDT 24
Peak memory 204048 kb
Host smart-34fe2bb2-7eb7-408f-96e3-824ed6b33718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15614
89220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.1561489220
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.247737276
Short name T175
Test name
Test status
Simulation time 8375204682 ps
CPU time 9.81 seconds
Started Apr 16 01:04:57 PM PDT 24
Finished Apr 16 01:05:08 PM PDT 24
Peak memory 203944 kb
Host smart-aa6defea-ec90-4c55-8437-1d7937c169e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24773
7276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.247737276
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.4280974099
Short name T1285
Test name
Test status
Simulation time 8367450470 ps
CPU time 9.02 seconds
Started Apr 16 01:04:55 PM PDT 24
Finished Apr 16 01:05:06 PM PDT 24
Peak memory 204036 kb
Host smart-9ab614e7-7915-4ab6-8e03-14404d28fe3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42809
74099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.4280974099
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1576318538
Short name T1196
Test name
Test status
Simulation time 8436296409 ps
CPU time 8.15 seconds
Started Apr 16 01:05:00 PM PDT 24
Finished Apr 16 01:05:08 PM PDT 24
Peak memory 204016 kb
Host smart-bf879922-528d-45c3-b764-15d570af2b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15763
18538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1576318538
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.2332854691
Short name T628
Test name
Test status
Simulation time 8371707568 ps
CPU time 7.95 seconds
Started Apr 16 01:04:55 PM PDT 24
Finished Apr 16 01:05:05 PM PDT 24
Peak memory 204036 kb
Host smart-2a340eb2-d1ba-40da-884e-6e702e5843ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23328
54691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.2332854691
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.1996378610
Short name T659
Test name
Test status
Simulation time 8401821914 ps
CPU time 7.8 seconds
Started Apr 16 01:04:57 PM PDT 24
Finished Apr 16 01:05:06 PM PDT 24
Peak memory 204004 kb
Host smart-222b6c1e-8d17-4531-8477-1679570613dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19963
78610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1996378610
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.3665588924
Short name T1124
Test name
Test status
Simulation time 8461549899 ps
CPU time 8.04 seconds
Started Apr 16 01:05:08 PM PDT 24
Finished Apr 16 01:05:17 PM PDT 24
Peak memory 203672 kb
Host smart-c173b929-6ad0-4957-8a0c-143d76b06557
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3665588924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.3665588924
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.3445774738
Short name T1315
Test name
Test status
Simulation time 8380444449 ps
CPU time 7.99 seconds
Started Apr 16 01:05:08 PM PDT 24
Finished Apr 16 01:05:17 PM PDT 24
Peak memory 204020 kb
Host smart-26aeef9a-50f3-4ed9-b8e5-84792c0706ea
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3445774738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.3445774738
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.7175828
Short name T1224
Test name
Test status
Simulation time 8387068595 ps
CPU time 8.19 seconds
Started Apr 16 01:04:58 PM PDT 24
Finished Apr 16 01:05:07 PM PDT 24
Peak memory 203972 kb
Host smart-6ecb8333-1759-4943-bc10-e7f12b6c1056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71758
28 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.7175828
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_enable.1516040517
Short name T891
Test name
Test status
Simulation time 8373475019 ps
CPU time 8.92 seconds
Started Apr 16 01:05:03 PM PDT 24
Finished Apr 16 01:05:12 PM PDT 24
Peak memory 204016 kb
Host smart-3b13e6ff-506a-4848-8971-d6ec42d2dfc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15160
40517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.1516040517
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3048756659
Short name T801
Test name
Test status
Simulation time 52154563 ps
CPU time 1.32 seconds
Started Apr 16 01:04:59 PM PDT 24
Finished Apr 16 01:05:01 PM PDT 24
Peak memory 204016 kb
Host smart-a6eebb96-49e6-41d1-a9a7-75db6b6ebb33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30487
56659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3048756659
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.65802383
Short name T440
Test name
Test status
Simulation time 8388749416 ps
CPU time 9.57 seconds
Started Apr 16 01:05:04 PM PDT 24
Finished Apr 16 01:05:14 PM PDT 24
Peak memory 204048 kb
Host smart-4aebeec8-2ef8-4994-bf00-282ce6ac539c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65802
383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.65802383
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2284417693
Short name T192
Test name
Test status
Simulation time 8382045853 ps
CPU time 7.86 seconds
Started Apr 16 01:05:05 PM PDT 24
Finished Apr 16 01:05:14 PM PDT 24
Peak memory 203944 kb
Host smart-d3fc61e2-182d-4f38-a321-f7dfd30a9650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22844
17693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2284417693
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3243928420
Short name T930
Test name
Test status
Simulation time 8447531680 ps
CPU time 8 seconds
Started Apr 16 01:05:00 PM PDT 24
Finished Apr 16 01:05:09 PM PDT 24
Peak memory 204044 kb
Host smart-c3d5758f-2008-4ab5-b9d2-da6d0f6c2b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32439
28420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3243928420
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.3107608806
Short name T1060
Test name
Test status
Simulation time 8418130301 ps
CPU time 10.84 seconds
Started Apr 16 01:05:03 PM PDT 24
Finished Apr 16 01:05:14 PM PDT 24
Peak memory 203980 kb
Host smart-05d71ee6-dbc1-44a0-91fa-5364f8347a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31076
08806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.3107608806
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.961233202
Short name T1217
Test name
Test status
Simulation time 8370980997 ps
CPU time 8.15 seconds
Started Apr 16 01:05:01 PM PDT 24
Finished Apr 16 01:05:10 PM PDT 24
Peak memory 204260 kb
Host smart-0ecdbd9f-06c8-47d2-8bc7-ce97be4cb6c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96123
3202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.961233202
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.4194142555
Short name T325
Test name
Test status
Simulation time 8427501792 ps
CPU time 9.99 seconds
Started Apr 16 01:05:00 PM PDT 24
Finished Apr 16 01:05:11 PM PDT 24
Peak memory 204044 kb
Host smart-0675affb-ea71-407d-af33-5203969e54e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41941
42555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.4194142555
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.1888588509
Short name T425
Test name
Test status
Simulation time 8383283709 ps
CPU time 8.81 seconds
Started Apr 16 01:05:01 PM PDT 24
Finished Apr 16 01:05:10 PM PDT 24
Peak memory 204032 kb
Host smart-3ea130dc-6a1d-4f04-8941-26080b785e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18885
88509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.1888588509
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.3188443299
Short name T164
Test name
Test status
Simulation time 8382692231 ps
CPU time 9.84 seconds
Started Apr 16 01:05:05 PM PDT 24
Finished Apr 16 01:05:16 PM PDT 24
Peak memory 204004 kb
Host smart-284d1261-df00-49a4-ac85-a3dd98ff221c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31884
43299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.3188443299
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.1000982458
Short name T622
Test name
Test status
Simulation time 8363746418 ps
CPU time 9.26 seconds
Started Apr 16 01:05:08 PM PDT 24
Finished Apr 16 01:05:19 PM PDT 24
Peak memory 203924 kb
Host smart-0da8f315-c557-4a04-9f90-529ec0264a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10009
82458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.1000982458
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3249432428
Short name T579
Test name
Test status
Simulation time 61067525 ps
CPU time 0.7 seconds
Started Apr 16 01:05:06 PM PDT 24
Finished Apr 16 01:05:08 PM PDT 24
Peak memory 203880 kb
Host smart-44c69d62-e080-488c-8cc8-484ed461233d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32494
32428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3249432428
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.3745445692
Short name T1175
Test name
Test status
Simulation time 19108335064 ps
CPU time 36.97 seconds
Started Apr 16 01:05:03 PM PDT 24
Finished Apr 16 01:05:41 PM PDT 24
Peak memory 204304 kb
Host smart-f29853d7-df12-4d98-b93f-fd587f41310f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37454
45692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3745445692
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.2897398955
Short name T935
Test name
Test status
Simulation time 8386874640 ps
CPU time 7.82 seconds
Started Apr 16 01:05:01 PM PDT 24
Finished Apr 16 01:05:10 PM PDT 24
Peak memory 203944 kb
Host smart-9973424c-7f61-4e2c-98a0-49f96111147f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28973
98955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.2897398955
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3796402983
Short name T1098
Test name
Test status
Simulation time 8401984185 ps
CPU time 7.85 seconds
Started Apr 16 01:04:59 PM PDT 24
Finished Apr 16 01:05:08 PM PDT 24
Peak memory 203940 kb
Host smart-7a537ee0-0721-49a7-8fc0-b60d4bf8f607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37964
02983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3796402983
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.1134212438
Short name T661
Test name
Test status
Simulation time 8395146955 ps
CPU time 8 seconds
Started Apr 16 01:05:03 PM PDT 24
Finished Apr 16 01:05:12 PM PDT 24
Peak memory 203976 kb
Host smart-e94cf899-9da9-4502-8c44-49111a160194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11342
12438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.1134212438
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.3030229648
Short name T675
Test name
Test status
Simulation time 8376034781 ps
CPU time 7.89 seconds
Started Apr 16 01:05:04 PM PDT 24
Finished Apr 16 01:05:13 PM PDT 24
Peak memory 204012 kb
Host smart-ad8343c9-b16c-424b-8b96-ae9f542d9440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30302
29648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.3030229648
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3810113388
Short name T1146
Test name
Test status
Simulation time 8462547339 ps
CPU time 8 seconds
Started Apr 16 01:05:09 PM PDT 24
Finished Apr 16 01:05:18 PM PDT 24
Peak memory 204008 kb
Host smart-6bee01c5-4629-4814-a849-6647c56c7bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38101
13388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3810113388
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1874636723
Short name T937
Test name
Test status
Simulation time 8436737154 ps
CPU time 8.68 seconds
Started Apr 16 01:05:00 PM PDT 24
Finished Apr 16 01:05:09 PM PDT 24
Peak memory 203992 kb
Host smart-99e90176-dc7f-4c92-9154-5674d2fbafd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18746
36723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1874636723
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.3527132193
Short name T432
Test name
Test status
Simulation time 8390079279 ps
CPU time 7.59 seconds
Started Apr 16 01:05:05 PM PDT 24
Finished Apr 16 01:05:13 PM PDT 24
Peak memory 204080 kb
Host smart-9e9a652d-a778-45d1-9256-81d8de44c874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35271
32193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.3527132193
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.2421526051
Short name T597
Test name
Test status
Simulation time 8412213277 ps
CPU time 8 seconds
Started Apr 16 01:05:03 PM PDT 24
Finished Apr 16 01:05:12 PM PDT 24
Peak memory 204256 kb
Host smart-d1cfae95-a54c-456e-84fa-5ef69aaa1c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24215
26051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.2421526051
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.3157376635
Short name T602
Test name
Test status
Simulation time 8468231353 ps
CPU time 8.81 seconds
Started Apr 16 01:05:10 PM PDT 24
Finished Apr 16 01:05:20 PM PDT 24
Peak memory 204020 kb
Host smart-0524dd7a-b025-476e-865c-06b44f7d892b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3157376635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.3157376635
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.2600602269
Short name T1082
Test name
Test status
Simulation time 8409000096 ps
CPU time 7.7 seconds
Started Apr 16 01:05:08 PM PDT 24
Finished Apr 16 01:05:17 PM PDT 24
Peak memory 204004 kb
Host smart-6d1a82ec-a95f-40df-b2ca-30e9d484fbff
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2600602269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.2600602269
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.4237369788
Short name T315
Test name
Test status
Simulation time 8475155841 ps
CPU time 7.6 seconds
Started Apr 16 01:05:10 PM PDT 24
Finished Apr 16 01:05:18 PM PDT 24
Peak memory 204028 kb
Host smart-d3a64255-7e51-4de6-9885-1b56236921be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42373
69788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.4237369788
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.4247253733
Short name T398
Test name
Test status
Simulation time 8410132357 ps
CPU time 7.72 seconds
Started Apr 16 01:05:08 PM PDT 24
Finished Apr 16 01:05:17 PM PDT 24
Peak memory 203928 kb
Host smart-f42bacd2-0a00-4180-a5a2-83e2bf4e72a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42472
53733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.4247253733
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_enable.2938015217
Short name T374
Test name
Test status
Simulation time 8373581878 ps
CPU time 7.99 seconds
Started Apr 16 01:05:04 PM PDT 24
Finished Apr 16 01:05:13 PM PDT 24
Peak memory 204016 kb
Host smart-0c4aa13c-d425-4b0e-8d99-b57411b0341a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29380
15217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.2938015217
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.1620301566
Short name T59
Test name
Test status
Simulation time 49285831 ps
CPU time 1.12 seconds
Started Apr 16 01:05:03 PM PDT 24
Finished Apr 16 01:05:05 PM PDT 24
Peak memory 204084 kb
Host smart-0f543bfc-60f5-485e-bdb5-285c4c8c0aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16203
01566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.1620301566
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.249880974
Short name T1359
Test name
Test status
Simulation time 8449410506 ps
CPU time 7.66 seconds
Started Apr 16 01:05:12 PM PDT 24
Finished Apr 16 01:05:21 PM PDT 24
Peak memory 204048 kb
Host smart-c3dd2092-eeae-410d-a5e0-a5b1dbc0a329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24988
0974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.249880974
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.3724688073
Short name T754
Test name
Test status
Simulation time 8397607802 ps
CPU time 8.13 seconds
Started Apr 16 01:05:10 PM PDT 24
Finished Apr 16 01:05:19 PM PDT 24
Peak memory 203980 kb
Host smart-6d419e3a-5ad7-49c0-b081-eeb66838d2db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37246
88073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.3724688073
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.942627544
Short name T488
Test name
Test status
Simulation time 8397235960 ps
CPU time 7.75 seconds
Started Apr 16 01:05:08 PM PDT 24
Finished Apr 16 01:05:17 PM PDT 24
Peak memory 204008 kb
Host smart-2c10d4cc-ab7c-43c0-8e05-3968ef02733e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94262
7544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.942627544
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.1650371386
Short name T713
Test name
Test status
Simulation time 8438396971 ps
CPU time 7.89 seconds
Started Apr 16 01:05:05 PM PDT 24
Finished Apr 16 01:05:14 PM PDT 24
Peak memory 203992 kb
Host smart-ac1161b8-5113-4d8d-a221-153cf14da6be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16503
71386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1650371386
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.2180548455
Short name T1087
Test name
Test status
Simulation time 8379913245 ps
CPU time 8.43 seconds
Started Apr 16 01:05:04 PM PDT 24
Finished Apr 16 01:05:13 PM PDT 24
Peak memory 203992 kb
Host smart-e3f36ba4-403c-4d50-b2af-e6dfb4b4e493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21805
48455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.2180548455
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.1724902046
Short name T430
Test name
Test status
Simulation time 8452190207 ps
CPU time 9.21 seconds
Started Apr 16 01:05:04 PM PDT 24
Finished Apr 16 01:05:14 PM PDT 24
Peak memory 204028 kb
Host smart-dcda3060-b8f4-466b-a2fc-79d86bad3e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17249
02046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.1724902046
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.2854301915
Short name T1059
Test name
Test status
Simulation time 8391353829 ps
CPU time 8.65 seconds
Started Apr 16 01:05:09 PM PDT 24
Finished Apr 16 01:05:18 PM PDT 24
Peak memory 203928 kb
Host smart-aea00036-7de5-4be9-972a-2fbe6d7b17be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28543
01915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.2854301915
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.711337988
Short name T827
Test name
Test status
Simulation time 8383636037 ps
CPU time 7.57 seconds
Started Apr 16 01:05:05 PM PDT 24
Finished Apr 16 01:05:14 PM PDT 24
Peak memory 203980 kb
Host smart-64521b91-f5a4-499c-b397-290cf8b33313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71133
7988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.711337988
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.356963890
Short name T1092
Test name
Test status
Simulation time 8433636809 ps
CPU time 8.77 seconds
Started Apr 16 01:05:08 PM PDT 24
Finished Apr 16 01:05:18 PM PDT 24
Peak memory 204028 kb
Host smart-954b9f00-4fb0-40f2-98f0-cef82a9e5b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35696
3890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.356963890
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.3089734300
Short name T486
Test name
Test status
Simulation time 8383271489 ps
CPU time 7.68 seconds
Started Apr 16 01:05:08 PM PDT 24
Finished Apr 16 01:05:16 PM PDT 24
Peak memory 204040 kb
Host smart-b4c79804-bb3f-4808-8309-22160d1ac030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30897
34300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.3089734300
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.2925104441
Short name T1158
Test name
Test status
Simulation time 43755200 ps
CPU time 0.7 seconds
Started Apr 16 01:05:10 PM PDT 24
Finished Apr 16 01:05:11 PM PDT 24
Peak memory 203832 kb
Host smart-dc97df5f-6d38-485b-8ca3-23da68864909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29251
04441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2925104441
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.2950565630
Short name T78
Test name
Test status
Simulation time 25386310304 ps
CPU time 53.62 seconds
Started Apr 16 01:05:05 PM PDT 24
Finished Apr 16 01:06:00 PM PDT 24
Peak memory 204324 kb
Host smart-51c50b49-ebcd-42a5-925d-cbe05aa318e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29505
65630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.2950565630
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.45573087
Short name T701
Test name
Test status
Simulation time 8423519014 ps
CPU time 8.98 seconds
Started Apr 16 01:05:04 PM PDT 24
Finished Apr 16 01:05:14 PM PDT 24
Peak memory 204016 kb
Host smart-786fd0ed-2da9-417a-8bdf-15330529560a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45573
087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.45573087
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.4227731948
Short name T475
Test name
Test status
Simulation time 8414038056 ps
CPU time 8.42 seconds
Started Apr 16 01:05:09 PM PDT 24
Finished Apr 16 01:05:19 PM PDT 24
Peak memory 204024 kb
Host smart-e2b00f69-2316-4b42-bc99-a6f2511a710b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42277
31948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.4227731948
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.966361117
Short name T388
Test name
Test status
Simulation time 8412494387 ps
CPU time 8.33 seconds
Started Apr 16 01:05:08 PM PDT 24
Finished Apr 16 01:05:18 PM PDT 24
Peak memory 204048 kb
Host smart-de84f7d1-e23d-4804-9d77-a066ea35ca9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96636
1117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.966361117
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.737898766
Short name T1251
Test name
Test status
Simulation time 8439022875 ps
CPU time 9.26 seconds
Started Apr 16 01:05:08 PM PDT 24
Finished Apr 16 01:05:18 PM PDT 24
Peak memory 204044 kb
Host smart-00fb0d22-d847-4761-a434-556956449e9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73789
8766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.737898766
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.3123801555
Short name T657
Test name
Test status
Simulation time 8362392761 ps
CPU time 8.17 seconds
Started Apr 16 01:05:08 PM PDT 24
Finished Apr 16 01:05:17 PM PDT 24
Peak memory 204028 kb
Host smart-e30bf40d-b8f1-4e67-9797-f58485ea0524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31238
01555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.3123801555
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.3705929562
Short name T683
Test name
Test status
Simulation time 8430749112 ps
CPU time 8.16 seconds
Started Apr 16 01:05:04 PM PDT 24
Finished Apr 16 01:05:13 PM PDT 24
Peak memory 204020 kb
Host smart-0ad09c9e-9c4c-4de7-b15b-08796e67a66e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37059
29562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.3705929562
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2723434361
Short name T736
Test name
Test status
Simulation time 8397851441 ps
CPU time 10.39 seconds
Started Apr 16 01:05:13 PM PDT 24
Finished Apr 16 01:05:24 PM PDT 24
Peak memory 203936 kb
Host smart-79ce5116-6ea0-4511-9a62-0a9350e85f5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27234
34361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2723434361
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.30369006
Short name T762
Test name
Test status
Simulation time 8399412180 ps
CPU time 8.05 seconds
Started Apr 16 01:05:09 PM PDT 24
Finished Apr 16 01:05:18 PM PDT 24
Peak memory 203992 kb
Host smart-3c096503-cafe-48fc-8b12-6df25f3d6c53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30369
006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.30369006
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.2487456440
Short name T297
Test name
Test status
Simulation time 8472155211 ps
CPU time 8.24 seconds
Started Apr 16 01:05:12 PM PDT 24
Finished Apr 16 01:05:22 PM PDT 24
Peak memory 204032 kb
Host smart-b4ee1b1d-715f-41e2-8cf9-e6541e9eb5d0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2487456440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.2487456440
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.955014067
Short name T423
Test name
Test status
Simulation time 8376746791 ps
CPU time 8.02 seconds
Started Apr 16 01:05:15 PM PDT 24
Finished Apr 16 01:05:24 PM PDT 24
Peak memory 204020 kb
Host smart-7eb43c61-0845-4309-a441-9e050b667ac7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=955014067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.955014067
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.3291500196
Short name T1027
Test name
Test status
Simulation time 8455107610 ps
CPU time 8.09 seconds
Started Apr 16 01:05:12 PM PDT 24
Finished Apr 16 01:05:21 PM PDT 24
Peak memory 204012 kb
Host smart-c1d5b9e3-2ba8-45d1-bd5c-abda0cbebed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32915
00196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.3291500196
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.1482610502
Short name T455
Test name
Test status
Simulation time 8399593006 ps
CPU time 8 seconds
Started Apr 16 01:05:09 PM PDT 24
Finished Apr 16 01:05:18 PM PDT 24
Peak memory 204028 kb
Host smart-1a69b801-46fe-44e9-97d4-95b63d784c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14826
10502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1482610502
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_enable.1478364902
Short name T1013
Test name
Test status
Simulation time 8391198632 ps
CPU time 7.7 seconds
Started Apr 16 01:05:12 PM PDT 24
Finished Apr 16 01:05:21 PM PDT 24
Peak memory 204048 kb
Host smart-abb1e821-2452-40d0-9e0b-b1df99ea3244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14783
64902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1478364902
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3958507193
Short name T1008
Test name
Test status
Simulation time 163798923 ps
CPU time 1.38 seconds
Started Apr 16 01:05:08 PM PDT 24
Finished Apr 16 01:05:10 PM PDT 24
Peak memory 204156 kb
Host smart-874a7fbf-d81b-4e40-8e69-29e06ce9d0db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39585
07193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3958507193
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.137754256
Short name T540
Test name
Test status
Simulation time 8439447839 ps
CPU time 8.54 seconds
Started Apr 16 01:05:23 PM PDT 24
Finished Apr 16 01:05:33 PM PDT 24
Peak memory 203984 kb
Host smart-ea054ef5-cc42-47c1-80dd-23844fe1863b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13775
4256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.137754256
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.3895846150
Short name T1352
Test name
Test status
Simulation time 8376480371 ps
CPU time 8.36 seconds
Started Apr 16 01:05:23 PM PDT 24
Finished Apr 16 01:05:33 PM PDT 24
Peak memory 203980 kb
Host smart-4f876841-aee9-4856-af16-ec0ade8f1cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38958
46150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.3895846150
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.3935442747
Short name T951
Test name
Test status
Simulation time 8414764484 ps
CPU time 8.59 seconds
Started Apr 16 01:05:09 PM PDT 24
Finished Apr 16 01:05:19 PM PDT 24
Peak memory 204024 kb
Host smart-dcbf7690-fca4-4670-90f8-0a348aa903f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39354
42747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3935442747
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.1442338765
Short name T340
Test name
Test status
Simulation time 8417803958 ps
CPU time 8.01 seconds
Started Apr 16 01:05:13 PM PDT 24
Finished Apr 16 01:05:22 PM PDT 24
Peak memory 204012 kb
Host smart-3fe3defb-e755-4a8e-9220-a1322165de26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14423
38765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.1442338765
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.3798574107
Short name T344
Test name
Test status
Simulation time 8366363702 ps
CPU time 7.77 seconds
Started Apr 16 01:05:06 PM PDT 24
Finished Apr 16 01:05:14 PM PDT 24
Peak memory 203984 kb
Host smart-ad5033f4-79bf-4a3c-805b-1d653dfc5c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37985
74107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.3798574107
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.1177318451
Short name T36
Test name
Test status
Simulation time 8452937459 ps
CPU time 7.7 seconds
Started Apr 16 01:05:11 PM PDT 24
Finished Apr 16 01:05:19 PM PDT 24
Peak memory 204012 kb
Host smart-282e6d5b-4e8c-49f2-a29e-c020eaf536a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11773
18451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.1177318451
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.3857442206
Short name T417
Test name
Test status
Simulation time 8399248824 ps
CPU time 8.59 seconds
Started Apr 16 01:05:09 PM PDT 24
Finished Apr 16 01:05:18 PM PDT 24
Peak memory 204044 kb
Host smart-7228c889-9a21-4ccd-b082-af7ed30d11df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38574
42206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.3857442206
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.820241783
Short name T917
Test name
Test status
Simulation time 8396846095 ps
CPU time 8.74 seconds
Started Apr 16 01:05:12 PM PDT 24
Finished Apr 16 01:05:22 PM PDT 24
Peak memory 203948 kb
Host smart-7515fe60-db82-49f0-9f1c-2953a3a4f286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82024
1783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.820241783
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.521159829
Short name T178
Test name
Test status
Simulation time 8402065141 ps
CPU time 7.87 seconds
Started Apr 16 01:05:14 PM PDT 24
Finished Apr 16 01:05:23 PM PDT 24
Peak memory 203948 kb
Host smart-13b71654-7137-4e25-bf2a-641b6eb2fd4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52115
9829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.521159829
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.1811138371
Short name T813
Test name
Test status
Simulation time 8398470066 ps
CPU time 8.04 seconds
Started Apr 16 01:05:14 PM PDT 24
Finished Apr 16 01:05:23 PM PDT 24
Peak memory 204016 kb
Host smart-c4e22a31-9c09-4763-9044-79560d5ebf6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18111
38371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.1811138371
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.4179586907
Short name T15
Test name
Test status
Simulation time 53389448 ps
CPU time 0.64 seconds
Started Apr 16 01:05:12 PM PDT 24
Finished Apr 16 01:05:13 PM PDT 24
Peak memory 203896 kb
Host smart-77602bab-f951-4fd9-b512-a70e48b7bb2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41795
86907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.4179586907
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.1567412563
Short name T237
Test name
Test status
Simulation time 24953245345 ps
CPU time 47.76 seconds
Started Apr 16 01:05:09 PM PDT 24
Finished Apr 16 01:05:58 PM PDT 24
Peak memory 204332 kb
Host smart-60184005-943d-4a84-b742-7195c16771d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15674
12563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.1567412563
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.3594869253
Short name T1017
Test name
Test status
Simulation time 8391979577 ps
CPU time 8.25 seconds
Started Apr 16 01:05:09 PM PDT 24
Finished Apr 16 01:05:18 PM PDT 24
Peak memory 203992 kb
Host smart-963b2a58-0077-497b-baad-094324447cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35948
69253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.3594869253
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2742414749
Short name T38
Test name
Test status
Simulation time 8434216931 ps
CPU time 7.81 seconds
Started Apr 16 01:05:23 PM PDT 24
Finished Apr 16 01:05:32 PM PDT 24
Peak memory 203960 kb
Host smart-cf81adf2-9bbb-4a9b-983c-b4937247bfe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27424
14749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2742414749
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.3332032838
Short name T1048
Test name
Test status
Simulation time 8384257055 ps
CPU time 8.23 seconds
Started Apr 16 01:05:12 PM PDT 24
Finished Apr 16 01:05:22 PM PDT 24
Peak memory 204028 kb
Host smart-f0b7b069-2deb-4d73-90f7-064baa2a4e9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33320
32838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.3332032838
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.4059103100
Short name T229
Test name
Test status
Simulation time 8386719024 ps
CPU time 9.19 seconds
Started Apr 16 01:05:23 PM PDT 24
Finished Apr 16 01:05:33 PM PDT 24
Peak memory 203940 kb
Host smart-3b87a18a-f605-4f39-9c1e-41104b09959d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40591
03100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.4059103100
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.20687635
Short name T929
Test name
Test status
Simulation time 8373463210 ps
CPU time 8.73 seconds
Started Apr 16 01:05:13 PM PDT 24
Finished Apr 16 01:05:23 PM PDT 24
Peak memory 203952 kb
Host smart-ee2f205f-ca91-44f0-9cae-2578e069cae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20687
635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.20687635
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.388970818
Short name T162
Test name
Test status
Simulation time 8479638087 ps
CPU time 8.66 seconds
Started Apr 16 01:05:07 PM PDT 24
Finished Apr 16 01:05:16 PM PDT 24
Peak memory 203992 kb
Host smart-5ad8a065-4c5b-4740-af58-92ea33dfacf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38897
0818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.388970818
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.2806112096
Short name T783
Test name
Test status
Simulation time 8378537798 ps
CPU time 7.42 seconds
Started Apr 16 01:05:15 PM PDT 24
Finished Apr 16 01:05:23 PM PDT 24
Peak memory 203956 kb
Host smart-247b76e3-ac1d-44cb-a7c1-1ad65cad59a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28061
12096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.2806112096
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.2626737427
Short name T844
Test name
Test status
Simulation time 8413622481 ps
CPU time 8.28 seconds
Started Apr 16 01:05:17 PM PDT 24
Finished Apr 16 01:05:26 PM PDT 24
Peak memory 204012 kb
Host smart-9b921418-6a7a-4063-938f-6aa1e1655356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26267
37427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.2626737427
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.845605312
Short name T674
Test name
Test status
Simulation time 8468225741 ps
CPU time 8.25 seconds
Started Apr 16 01:05:23 PM PDT 24
Finished Apr 16 01:05:33 PM PDT 24
Peak memory 203960 kb
Host smart-ff047ab5-0d76-497a-8f41-b8692b65d8dd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=845605312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.845605312
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.204820761
Short name T453
Test name
Test status
Simulation time 8380410391 ps
CPU time 8.38 seconds
Started Apr 16 01:05:22 PM PDT 24
Finished Apr 16 01:05:31 PM PDT 24
Peak memory 203988 kb
Host smart-26fa881b-25ec-4d2b-9733-6ebe05930eba
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=204820761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.204820761
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.1453803784
Short name T1067
Test name
Test status
Simulation time 8444311406 ps
CPU time 7.85 seconds
Started Apr 16 01:05:22 PM PDT 24
Finished Apr 16 01:05:31 PM PDT 24
Peak memory 203928 kb
Host smart-58fa4f2c-d1ca-4365-860d-7b17b233a38e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14538
03784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.1453803784
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.3112264089
Short name T1143
Test name
Test status
Simulation time 8375033693 ps
CPU time 8.93 seconds
Started Apr 16 01:05:13 PM PDT 24
Finished Apr 16 01:05:23 PM PDT 24
Peak memory 203960 kb
Host smart-ff42c533-bc30-490a-b62a-27fcfcf961f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31122
64089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.3112264089
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_enable.118146278
Short name T888
Test name
Test status
Simulation time 8378170084 ps
CPU time 8.06 seconds
Started Apr 16 01:05:16 PM PDT 24
Finished Apr 16 01:05:25 PM PDT 24
Peak memory 203948 kb
Host smart-c356d663-ea0b-42fa-a535-5f0712fb572b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11814
6278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.118146278
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.2571819056
Short name T692
Test name
Test status
Simulation time 147977811 ps
CPU time 1.44 seconds
Started Apr 16 01:05:14 PM PDT 24
Finished Apr 16 01:05:16 PM PDT 24
Peak memory 204140 kb
Host smart-c712734a-4e57-4f60-80f1-45ccfb88a63f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25718
19056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.2571819056
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.833076075
Short name T1035
Test name
Test status
Simulation time 8438173637 ps
CPU time 9.65 seconds
Started Apr 16 01:05:24 PM PDT 24
Finished Apr 16 01:05:35 PM PDT 24
Peak memory 203972 kb
Host smart-e502b1e9-a091-490d-ad5c-50c56edccea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83307
6075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.833076075
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.702780905
Short name T818
Test name
Test status
Simulation time 8368724537 ps
CPU time 7.69 seconds
Started Apr 16 01:05:22 PM PDT 24
Finished Apr 16 01:05:30 PM PDT 24
Peak memory 203992 kb
Host smart-357c4122-40bc-4870-bf27-7c869f434e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70278
0905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.702780905
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.2546411197
Short name T709
Test name
Test status
Simulation time 8396481732 ps
CPU time 8.22 seconds
Started Apr 16 01:05:14 PM PDT 24
Finished Apr 16 01:05:24 PM PDT 24
Peak memory 203992 kb
Host smart-c38639e7-f76e-4c17-96c5-3de58634e8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25464
11197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.2546411197
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1210603299
Short name T457
Test name
Test status
Simulation time 8441949314 ps
CPU time 8.92 seconds
Started Apr 16 01:05:15 PM PDT 24
Finished Apr 16 01:05:25 PM PDT 24
Peak memory 203948 kb
Host smart-dd064de5-3dc3-4736-b368-67f39daa9aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12106
03299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1210603299
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.1365657185
Short name T1222
Test name
Test status
Simulation time 8367297346 ps
CPU time 7.83 seconds
Started Apr 16 01:05:12 PM PDT 24
Finished Apr 16 01:05:21 PM PDT 24
Peak memory 203980 kb
Host smart-f1e9bbb7-e51e-469b-afad-32ed0939d541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13656
57185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.1365657185
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.2472202718
Short name T1073
Test name
Test status
Simulation time 8433601308 ps
CPU time 7.55 seconds
Started Apr 16 01:05:13 PM PDT 24
Finished Apr 16 01:05:22 PM PDT 24
Peak memory 204016 kb
Host smart-21a25b47-c831-40ea-b36c-33f1c89a37ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24722
02718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.2472202718
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.1424900787
Short name T943
Test name
Test status
Simulation time 8387090536 ps
CPU time 7.83 seconds
Started Apr 16 01:05:28 PM PDT 24
Finished Apr 16 01:05:37 PM PDT 24
Peak memory 204024 kb
Host smart-d0da63c9-a520-4cff-b2d8-04aa5c380b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14249
00787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.1424900787
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.21888971
Short name T1332
Test name
Test status
Simulation time 8389605746 ps
CPU time 8.27 seconds
Started Apr 16 01:05:21 PM PDT 24
Finished Apr 16 01:05:31 PM PDT 24
Peak memory 203948 kb
Host smart-49d547e7-1b8e-4cf1-8369-4de2a62712bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21888
971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.21888971
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.106449805
Short name T1252
Test name
Test status
Simulation time 8415226282 ps
CPU time 8.81 seconds
Started Apr 16 01:05:23 PM PDT 24
Finished Apr 16 01:05:33 PM PDT 24
Peak memory 204032 kb
Host smart-c24e6f14-d506-4d53-a4e9-49cef61b60b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10644
9805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.106449805
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.2805572458
Short name T819
Test name
Test status
Simulation time 8371027815 ps
CPU time 8.46 seconds
Started Apr 16 01:05:20 PM PDT 24
Finished Apr 16 01:05:29 PM PDT 24
Peak memory 204028 kb
Host smart-059e17ca-d62a-4f69-b983-463a9a3f6301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28055
72458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.2805572458
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.2794978718
Short name T368
Test name
Test status
Simulation time 65851377 ps
CPU time 0.75 seconds
Started Apr 16 01:05:20 PM PDT 24
Finished Apr 16 01:05:22 PM PDT 24
Peak memory 204132 kb
Host smart-6da30312-bf46-4439-be74-bdc00b117e85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27949
78718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.2794978718
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.1268305306
Short name T851
Test name
Test status
Simulation time 28571011503 ps
CPU time 53.99 seconds
Started Apr 16 01:05:28 PM PDT 24
Finished Apr 16 01:06:23 PM PDT 24
Peak memory 204316 kb
Host smart-7fc56c9d-92d7-408c-bef9-e9993f82b09d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12683
05306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.1268305306
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.585849990
Short name T407
Test name
Test status
Simulation time 8402048934 ps
CPU time 9.58 seconds
Started Apr 16 01:05:21 PM PDT 24
Finished Apr 16 01:05:31 PM PDT 24
Peak memory 203976 kb
Host smart-898e614f-e5a9-4e82-92a0-ee487c7b74e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58584
9990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.585849990
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.2294120005
Short name T127
Test name
Test status
Simulation time 8449037829 ps
CPU time 8.39 seconds
Started Apr 16 01:05:21 PM PDT 24
Finished Apr 16 01:05:31 PM PDT 24
Peak memory 204020 kb
Host smart-eb7e5449-69c0-47ae-8b58-70cf43f25966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22941
20005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2294120005
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.1655118098
Short name T286
Test name
Test status
Simulation time 8410527944 ps
CPU time 8.29 seconds
Started Apr 16 01:05:21 PM PDT 24
Finished Apr 16 01:05:31 PM PDT 24
Peak memory 204008 kb
Host smart-49b18227-96c1-4ee4-bba6-a057effa2140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16551
18098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.1655118098
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.3503549551
Short name T170
Test name
Test status
Simulation time 8376423067 ps
CPU time 7.87 seconds
Started Apr 16 01:05:22 PM PDT 24
Finished Apr 16 01:05:31 PM PDT 24
Peak memory 203944 kb
Host smart-82b6590f-1d35-4c12-8705-42c96e4bfee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35035
49551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.3503549551
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3212532732
Short name T1327
Test name
Test status
Simulation time 8374001070 ps
CPU time 7.78 seconds
Started Apr 16 01:05:21 PM PDT 24
Finished Apr 16 01:05:29 PM PDT 24
Peak memory 203904 kb
Host smart-d7f3938b-4503-42cf-960c-59aca8a4cdc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32125
32732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3212532732
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.2234963738
Short name T166
Test name
Test status
Simulation time 8442426611 ps
CPU time 8.57 seconds
Started Apr 16 01:05:13 PM PDT 24
Finished Apr 16 01:05:23 PM PDT 24
Peak memory 204000 kb
Host smart-5c8e4881-b392-40ef-803d-4dd260d0e0a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22349
63738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.2234963738
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.3075891651
Short name T1274
Test name
Test status
Simulation time 8414160237 ps
CPU time 7.97 seconds
Started Apr 16 01:05:21 PM PDT 24
Finished Apr 16 01:05:29 PM PDT 24
Peak memory 203992 kb
Host smart-35ecb8d0-d570-4e0f-ae6d-44c192110ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30758
91651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.3075891651
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.1656125337
Short name T562
Test name
Test status
Simulation time 8467040367 ps
CPU time 8.35 seconds
Started Apr 16 01:05:22 PM PDT 24
Finished Apr 16 01:05:31 PM PDT 24
Peak memory 204036 kb
Host smart-9f0da79d-1130-4568-bb58-36fa9e75b322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16561
25337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.1656125337
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.max_length_in_transaction.1565411112
Short name T747
Test name
Test status
Simulation time 8465161011 ps
CPU time 9.07 seconds
Started Apr 16 01:05:23 PM PDT 24
Finished Apr 16 01:05:33 PM PDT 24
Peak memory 204032 kb
Host smart-37c68b1e-2646-4770-a5e5-ac7b034401e2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1565411112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.1565411112
Directory /workspace/45.max_length_in_transaction/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.2001307988
Short name T507
Test name
Test status
Simulation time 8384307351 ps
CPU time 7.78 seconds
Started Apr 16 01:05:22 PM PDT 24
Finished Apr 16 01:05:31 PM PDT 24
Peak memory 204048 kb
Host smart-7d7d1a22-782c-42d8-9a4c-ebbe8a353748
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2001307988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.2001307988
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.random_length_in_trans.2673416325
Short name T37
Test name
Test status
Simulation time 8467041303 ps
CPU time 7.91 seconds
Started Apr 16 01:05:35 PM PDT 24
Finished Apr 16 01:05:44 PM PDT 24
Peak memory 203904 kb
Host smart-d5803e1b-3a0b-4f99-95a9-08caef33813f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26734
16325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.2673416325
Directory /workspace/45.random_length_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.267572288
Short name T1113
Test name
Test status
Simulation time 8376889824 ps
CPU time 7.78 seconds
Started Apr 16 01:05:23 PM PDT 24
Finished Apr 16 01:05:32 PM PDT 24
Peak memory 203960 kb
Host smart-cd49b381-1eb7-4205-8692-d2a8f535d644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26757
2288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.267572288
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_enable.2284041668
Short name T652
Test name
Test status
Simulation time 8385255700 ps
CPU time 7.43 seconds
Started Apr 16 01:05:21 PM PDT 24
Finished Apr 16 01:05:29 PM PDT 24
Peak memory 204044 kb
Host smart-6a447198-3794-4e8a-8fb6-d00ed0c912e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22840
41668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.2284041668
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.3911546502
Short name T581
Test name
Test status
Simulation time 177562049 ps
CPU time 1.98 seconds
Started Apr 16 01:05:21 PM PDT 24
Finished Apr 16 01:05:24 PM PDT 24
Peak memory 204156 kb
Host smart-bc359199-cfe0-4462-97ab-1d37c48c32ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39115
46502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.3911546502
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.768853206
Short name T535
Test name
Test status
Simulation time 8401734112 ps
CPU time 8.09 seconds
Started Apr 16 01:05:23 PM PDT 24
Finished Apr 16 01:05:33 PM PDT 24
Peak memory 203948 kb
Host smart-d414e56b-4303-4aa4-967c-6f65498ec3b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76885
3206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.768853206
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3466751005
Short name T1084
Test name
Test status
Simulation time 8370281340 ps
CPU time 8.73 seconds
Started Apr 16 01:05:36 PM PDT 24
Finished Apr 16 01:05:46 PM PDT 24
Peak memory 203896 kb
Host smart-30d70cbd-69c4-4653-8907-9198c3144c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34667
51005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3466751005
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.4023196353
Short name T405
Test name
Test status
Simulation time 8438117683 ps
CPU time 9.67 seconds
Started Apr 16 01:05:25 PM PDT 24
Finished Apr 16 01:05:36 PM PDT 24
Peak memory 203968 kb
Host smart-fcecabf6-9d60-480e-bbb4-fd81b3374927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40231
96353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.4023196353
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.4280165841
Short name T32
Test name
Test status
Simulation time 8418509666 ps
CPU time 9.49 seconds
Started Apr 16 01:05:25 PM PDT 24
Finished Apr 16 01:05:35 PM PDT 24
Peak memory 204028 kb
Host smart-ed94c1f0-a49e-4059-bb7f-8740e5c1f3c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42801
65841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.4280165841
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.3184819544
Short name T587
Test name
Test status
Simulation time 8376936554 ps
CPU time 8.07 seconds
Started Apr 16 01:05:23 PM PDT 24
Finished Apr 16 01:05:32 PM PDT 24
Peak memory 204016 kb
Host smart-2a4cb729-cc5e-4ce3-b3aa-3b17ae293455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31848
19544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.3184819544
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.3307770609
Short name T354
Test name
Test status
Simulation time 8420909637 ps
CPU time 7.74 seconds
Started Apr 16 01:05:22 PM PDT 24
Finished Apr 16 01:05:31 PM PDT 24
Peak memory 204028 kb
Host smart-9c46d742-b1cf-495e-97e8-ca015bc17d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33077
70609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3307770609
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.2759104842
Short name T424
Test name
Test status
Simulation time 8389588709 ps
CPU time 11 seconds
Started Apr 16 01:05:36 PM PDT 24
Finished Apr 16 01:05:48 PM PDT 24
Peak memory 203904 kb
Host smart-fe82d091-8261-4dda-b7bd-b0faa2285eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27591
04842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.2759104842
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.830102734
Short name T307
Test name
Test status
Simulation time 8403453713 ps
CPU time 8.68 seconds
Started Apr 16 01:05:24 PM PDT 24
Finished Apr 16 01:05:33 PM PDT 24
Peak memory 203948 kb
Host smart-5b0e6797-9de8-42e6-a5cf-5e53f1a9ebc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83010
2734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.830102734
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1024997660
Short name T784
Test name
Test status
Simulation time 8412018126 ps
CPU time 8.1 seconds
Started Apr 16 01:05:25 PM PDT 24
Finished Apr 16 01:05:34 PM PDT 24
Peak memory 204032 kb
Host smart-36968299-8dcc-43a7-9346-389ca1736018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10249
97660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1024997660
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.271339121
Short name T1149
Test name
Test status
Simulation time 8372363555 ps
CPU time 8.79 seconds
Started Apr 16 01:05:21 PM PDT 24
Finished Apr 16 01:05:31 PM PDT 24
Peak memory 203992 kb
Host smart-22948e54-7173-4c0b-99a5-4f9ce2f0077d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27133
9121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.271339121
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.722072198
Short name T1123
Test name
Test status
Simulation time 36779552 ps
CPU time 0.61 seconds
Started Apr 16 01:05:36 PM PDT 24
Finished Apr 16 01:05:38 PM PDT 24
Peak memory 203768 kb
Host smart-6d77f9e2-b315-4b31-8200-16d15684a492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72207
2198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.722072198
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.1414499611
Short name T1026
Test name
Test status
Simulation time 26689597674 ps
CPU time 59.39 seconds
Started Apr 16 01:05:24 PM PDT 24
Finished Apr 16 01:06:24 PM PDT 24
Peak memory 204268 kb
Host smart-812d8c4d-a4a1-496f-ba59-f2a1036e584b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14144
99611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.1414499611
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.311915957
Short name T815
Test name
Test status
Simulation time 8433235641 ps
CPU time 7.82 seconds
Started Apr 16 01:05:35 PM PDT 24
Finished Apr 16 01:05:44 PM PDT 24
Peak memory 203904 kb
Host smart-d65bc907-e361-49f4-b00c-e5d675279ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31191
5957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.311915957
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.3129212984
Short name T809
Test name
Test status
Simulation time 8416803643 ps
CPU time 8.91 seconds
Started Apr 16 01:05:23 PM PDT 24
Finished Apr 16 01:05:33 PM PDT 24
Peak memory 203960 kb
Host smart-76ac8161-c261-473b-a005-9ca5be22b4b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31292
12984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.3129212984
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.3594890879
Short name T593
Test name
Test status
Simulation time 8413879631 ps
CPU time 7.84 seconds
Started Apr 16 01:05:23 PM PDT 24
Finished Apr 16 01:05:32 PM PDT 24
Peak memory 204036 kb
Host smart-fed42917-0e99-4861-aa04-de8a373f9914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35948
90879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.3594890879
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.1127023459
Short name T681
Test name
Test status
Simulation time 8378522352 ps
CPU time 8.21 seconds
Started Apr 16 01:05:26 PM PDT 24
Finished Apr 16 01:05:35 PM PDT 24
Peak memory 204084 kb
Host smart-4f3d513d-45ec-45a6-afd4-c98ea27eeafb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11270
23459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.1127023459
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.16825441
Short name T494
Test name
Test status
Simulation time 8424527425 ps
CPU time 9.03 seconds
Started Apr 16 01:05:27 PM PDT 24
Finished Apr 16 01:05:37 PM PDT 24
Peak memory 204044 kb
Host smart-09a59b26-5cde-4496-bc9f-500d2bcef0cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16825
441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.16825441
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.4164063805
Short name T967
Test name
Test status
Simulation time 8489162880 ps
CPU time 7.8 seconds
Started Apr 16 01:05:20 PM PDT 24
Finished Apr 16 01:05:28 PM PDT 24
Peak memory 204040 kb
Host smart-d1ee676b-2c29-403c-b08a-f1c1f8bb7bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41640
63805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.4164063805
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.603468616
Short name T889
Test name
Test status
Simulation time 8389372779 ps
CPU time 9.58 seconds
Started Apr 16 01:05:24 PM PDT 24
Finished Apr 16 01:05:34 PM PDT 24
Peak memory 203956 kb
Host smart-a1dfc004-ad65-4d88-8c6c-4fb77953bee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60346
8616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.603468616
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.3232105040
Short name T718
Test name
Test status
Simulation time 8384869358 ps
CPU time 7.84 seconds
Started Apr 16 01:05:25 PM PDT 24
Finished Apr 16 01:05:34 PM PDT 24
Peak memory 204020 kb
Host smart-64448f72-b5e9-4c9a-93f4-1c31da362476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32321
05040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.3232105040
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.4172966006
Short name T392
Test name
Test status
Simulation time 8476556503 ps
CPU time 7.65 seconds
Started Apr 16 01:05:30 PM PDT 24
Finished Apr 16 01:05:39 PM PDT 24
Peak memory 204000 kb
Host smart-474b2514-d174-4a33-acb9-932b22c4e13b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4172966006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.4172966006
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.2598361170
Short name T529
Test name
Test status
Simulation time 8377385007 ps
CPU time 7.52 seconds
Started Apr 16 01:05:27 PM PDT 24
Finished Apr 16 01:05:35 PM PDT 24
Peak memory 203940 kb
Host smart-d441ed78-a91a-45bc-9515-124ef1fd788c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2598361170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.2598361170
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.1431665439
Short name T745
Test name
Test status
Simulation time 8489087753 ps
CPU time 9.53 seconds
Started Apr 16 01:05:27 PM PDT 24
Finished Apr 16 01:05:38 PM PDT 24
Peak memory 203988 kb
Host smart-43068343-71d2-4645-90c5-f0de2d394e35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14316
65439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.1431665439
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.2078903472
Short name T854
Test name
Test status
Simulation time 8376393620 ps
CPU time 10.18 seconds
Started Apr 16 01:05:36 PM PDT 24
Finished Apr 16 01:05:48 PM PDT 24
Peak memory 203908 kb
Host smart-d097a627-26d5-4f7f-b5b4-09ce9aacf332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20789
03472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.2078903472
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_enable.3554712217
Short name T911
Test name
Test status
Simulation time 8378716700 ps
CPU time 9.69 seconds
Started Apr 16 01:05:26 PM PDT 24
Finished Apr 16 01:05:37 PM PDT 24
Peak memory 204048 kb
Host smart-96357e53-0d0d-4cae-8b07-286258701dab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35547
12217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.3554712217
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.642367935
Short name T1256
Test name
Test status
Simulation time 91018930 ps
CPU time 1.76 seconds
Started Apr 16 01:05:27 PM PDT 24
Finished Apr 16 01:05:30 PM PDT 24
Peak memory 204160 kb
Host smart-1414239c-d6d9-4bc0-a6d3-5d5e1cf45280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64236
7935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.642367935
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.3549688723
Short name T140
Test name
Test status
Simulation time 8394312195 ps
CPU time 9.4 seconds
Started Apr 16 01:05:35 PM PDT 24
Finished Apr 16 01:05:46 PM PDT 24
Peak memory 203896 kb
Host smart-f8797e84-d028-4362-bb13-8ad1a0ffe0d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35496
88723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.3549688723
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.68373190
Short name T776
Test name
Test status
Simulation time 8380883161 ps
CPU time 7.69 seconds
Started Apr 16 01:05:29 PM PDT 24
Finished Apr 16 01:05:38 PM PDT 24
Peak memory 204080 kb
Host smart-0269a113-e2ea-4b77-aeb5-b6c9a78f37e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68373
190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.68373190
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.203146456
Short name T1169
Test name
Test status
Simulation time 8419398420 ps
CPU time 8.69 seconds
Started Apr 16 01:05:26 PM PDT 24
Finished Apr 16 01:05:35 PM PDT 24
Peak memory 204024 kb
Host smart-541f04e7-b546-418a-a03f-e00f320f188c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20314
6456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.203146456
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.1360732632
Short name T361
Test name
Test status
Simulation time 8427478514 ps
CPU time 8.54 seconds
Started Apr 16 01:05:25 PM PDT 24
Finished Apr 16 01:05:35 PM PDT 24
Peak memory 203948 kb
Host smart-60eae0c2-a105-4e41-8818-83b22ed1c4ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13607
32632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.1360732632
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.4163507934
Short name T1246
Test name
Test status
Simulation time 8369722707 ps
CPU time 9.79 seconds
Started Apr 16 01:05:29 PM PDT 24
Finished Apr 16 01:05:39 PM PDT 24
Peak memory 204012 kb
Host smart-80005f76-8bf2-4dc3-a2e8-1f34d8d52008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41635
07934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.4163507934
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.754664645
Short name T106
Test name
Test status
Simulation time 8444727529 ps
CPU time 8.79 seconds
Started Apr 16 01:05:25 PM PDT 24
Finished Apr 16 01:05:35 PM PDT 24
Peak memory 204024 kb
Host smart-0c6d8df7-e146-4d5f-9dd0-d81c9a78db3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75466
4645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.754664645
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.1630790360
Short name T857
Test name
Test status
Simulation time 8405795949 ps
CPU time 9.11 seconds
Started Apr 16 01:05:27 PM PDT 24
Finished Apr 16 01:05:37 PM PDT 24
Peak memory 204048 kb
Host smart-e83ad1d5-4053-41c0-978d-3c833c95a180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16307
90360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.1630790360
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.1381938919
Short name T778
Test name
Test status
Simulation time 8418859936 ps
CPU time 7.61 seconds
Started Apr 16 01:05:25 PM PDT 24
Finished Apr 16 01:05:33 PM PDT 24
Peak memory 203984 kb
Host smart-a90b70c9-535e-447c-87aa-8eae67cba0d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13819
38919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.1381938919
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.3689562519
Short name T155
Test name
Test status
Simulation time 8404438239 ps
CPU time 7.57 seconds
Started Apr 16 01:05:29 PM PDT 24
Finished Apr 16 01:05:37 PM PDT 24
Peak memory 204016 kb
Host smart-9e2f2976-5772-49ee-bd52-19aeaf6b8e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36895
62519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.3689562519
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.4216878703
Short name T1253
Test name
Test status
Simulation time 8376458261 ps
CPU time 7.31 seconds
Started Apr 16 01:05:26 PM PDT 24
Finished Apr 16 01:05:35 PM PDT 24
Peak memory 204028 kb
Host smart-4f754a58-21b0-4e51-8bdd-26bad8c329f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42168
78703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.4216878703
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.1156329829
Short name T1093
Test name
Test status
Simulation time 35144181 ps
CPU time 0.65 seconds
Started Apr 16 01:05:37 PM PDT 24
Finished Apr 16 01:05:39 PM PDT 24
Peak memory 203724 kb
Host smart-b371a209-acf8-42d2-96b2-40315336f681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11563
29829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.1156329829
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.2257414241
Short name T887
Test name
Test status
Simulation time 20096423498 ps
CPU time 36.44 seconds
Started Apr 16 01:05:35 PM PDT 24
Finished Apr 16 01:06:13 PM PDT 24
Peak memory 204192 kb
Host smart-e5344a44-614e-4811-b412-34155de9cc75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22574
14241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.2257414241
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.505951120
Short name T1279
Test name
Test status
Simulation time 8403934855 ps
CPU time 8.24 seconds
Started Apr 16 01:05:35 PM PDT 24
Finished Apr 16 01:05:45 PM PDT 24
Peak memory 203980 kb
Host smart-f3342fd5-95b6-42ac-8dca-9d87f2192dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50595
1120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.505951120
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.2180587638
Short name T314
Test name
Test status
Simulation time 8451155910 ps
CPU time 7.77 seconds
Started Apr 16 01:05:35 PM PDT 24
Finished Apr 16 01:05:44 PM PDT 24
Peak memory 203980 kb
Host smart-07e98c1c-6cbc-4c0e-9711-e11d047b8bc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21805
87638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.2180587638
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.4254408124
Short name T88
Test name
Test status
Simulation time 8403697591 ps
CPU time 8.94 seconds
Started Apr 16 01:05:31 PM PDT 24
Finished Apr 16 01:05:41 PM PDT 24
Peak memory 204048 kb
Host smart-a929d858-7fc2-4667-8051-c0f7572da1bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42544
08124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.4254408124
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.4107079153
Short name T172
Test name
Test status
Simulation time 8378814272 ps
CPU time 9.39 seconds
Started Apr 16 01:05:27 PM PDT 24
Finished Apr 16 01:05:38 PM PDT 24
Peak memory 204024 kb
Host smart-c999211b-9c60-4ce5-bbfb-e3ab5e0244ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41070
79153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.4107079153
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.537752683
Short name T1300
Test name
Test status
Simulation time 8372528460 ps
CPU time 7.85 seconds
Started Apr 16 01:05:31 PM PDT 24
Finished Apr 16 01:05:40 PM PDT 24
Peak memory 203940 kb
Host smart-748e8187-1e28-4cfa-9a91-2d50a097ce0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53775
2683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.537752683
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.659131746
Short name T1232
Test name
Test status
Simulation time 8463630338 ps
CPU time 7.98 seconds
Started Apr 16 01:05:35 PM PDT 24
Finished Apr 16 01:05:44 PM PDT 24
Peak memory 203904 kb
Host smart-0c8b6eea-1f2a-4478-9b06-51b65e3cd26c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65913
1746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.659131746
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.597427001
Short name T1338
Test name
Test status
Simulation time 8411496717 ps
CPU time 9.52 seconds
Started Apr 16 01:05:28 PM PDT 24
Finished Apr 16 01:05:38 PM PDT 24
Peak memory 203980 kb
Host smart-6b5c1586-174c-4c1e-8e4d-0e39b9491223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59742
7001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.597427001
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.3374993304
Short name T298
Test name
Test status
Simulation time 8394996175 ps
CPU time 8.12 seconds
Started Apr 16 01:05:29 PM PDT 24
Finished Apr 16 01:05:38 PM PDT 24
Peak memory 204028 kb
Host smart-9df2990f-abdf-426b-a7b8-56b15bb0bcad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33749
93304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.3374993304
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.3008071212
Short name T1190
Test name
Test status
Simulation time 8460338950 ps
CPU time 7.75 seconds
Started Apr 16 01:05:33 PM PDT 24
Finished Apr 16 01:05:42 PM PDT 24
Peak memory 203912 kb
Host smart-da9d85bc-6c3d-43ae-8b12-f157c94b589f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3008071212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.3008071212
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.848847157
Short name T1039
Test name
Test status
Simulation time 8388970098 ps
CPU time 8.79 seconds
Started Apr 16 01:05:32 PM PDT 24
Finished Apr 16 01:05:42 PM PDT 24
Peak memory 204052 kb
Host smart-1af27984-aabd-4dde-b20c-2d2f1aafb2e4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=848847157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.848847157
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.2165931785
Short name T1227
Test name
Test status
Simulation time 8462689768 ps
CPU time 7.98 seconds
Started Apr 16 01:05:31 PM PDT 24
Finished Apr 16 01:05:40 PM PDT 24
Peak memory 204008 kb
Host smart-a1240844-19b0-4934-91d7-bedd9e2898a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21659
31785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.2165931785
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2532534306
Short name T435
Test name
Test status
Simulation time 8385758084 ps
CPU time 8.48 seconds
Started Apr 16 01:05:28 PM PDT 24
Finished Apr 16 01:05:37 PM PDT 24
Peak memory 204028 kb
Host smart-39d268c8-379d-435a-a02f-656408fc74d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25325
34306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2532534306
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_enable.2483299543
Short name T1136
Test name
Test status
Simulation time 8384545484 ps
CPU time 9.8 seconds
Started Apr 16 01:05:28 PM PDT 24
Finished Apr 16 01:05:38 PM PDT 24
Peak memory 204044 kb
Host smart-b30e0f3b-40fb-4eaf-801a-e6f75a14afd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24832
99543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2483299543
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.374382806
Short name T1083
Test name
Test status
Simulation time 104876985 ps
CPU time 1.81 seconds
Started Apr 16 01:05:27 PM PDT 24
Finished Apr 16 01:05:30 PM PDT 24
Peak memory 204164 kb
Host smart-35470289-07ea-4439-8c7b-92062a49963a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37438
2806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.374382806
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.549099666
Short name T515
Test name
Test status
Simulation time 8424695562 ps
CPU time 8.06 seconds
Started Apr 16 01:05:32 PM PDT 24
Finished Apr 16 01:05:41 PM PDT 24
Peak memory 203980 kb
Host smart-9e6150a5-c9c3-440f-90da-3c824b1c1a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54909
9666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.549099666
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.1777039246
Short name T1177
Test name
Test status
Simulation time 8372522898 ps
CPU time 8.17 seconds
Started Apr 16 01:05:32 PM PDT 24
Finished Apr 16 01:05:41 PM PDT 24
Peak memory 204028 kb
Host smart-a415d8c5-cf04-4ca1-a7a8-eee4f094b76a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17770
39246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.1777039246
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.1132892840
Short name T1336
Test name
Test status
Simulation time 8450438982 ps
CPU time 8.58 seconds
Started Apr 16 01:05:35 PM PDT 24
Finished Apr 16 01:05:45 PM PDT 24
Peak memory 203980 kb
Host smart-ff16a555-2c75-4b81-b14f-f08df34072fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11328
92840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.1132892840
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.3815449832
Short name T971
Test name
Test status
Simulation time 8421726110 ps
CPU time 8.83 seconds
Started Apr 16 01:05:27 PM PDT 24
Finished Apr 16 01:05:37 PM PDT 24
Peak memory 204020 kb
Host smart-b370ea01-983c-48a8-89c9-2607ff92d4b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38154
49832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.3815449832
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.1907177357
Short name T689
Test name
Test status
Simulation time 8379048153 ps
CPU time 8.29 seconds
Started Apr 16 01:05:37 PM PDT 24
Finished Apr 16 01:05:47 PM PDT 24
Peak memory 204016 kb
Host smart-ecec1cbb-6d46-4d86-9bc4-364342bf966b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19071
77357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.1907177357
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.1445331617
Short name T124
Test name
Test status
Simulation time 8439909529 ps
CPU time 7.97 seconds
Started Apr 16 01:05:30 PM PDT 24
Finished Apr 16 01:05:39 PM PDT 24
Peak memory 204024 kb
Host smart-3845fd89-346f-4938-9376-144f3d34d8f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14453
31617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.1445331617
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.4189241302
Short name T514
Test name
Test status
Simulation time 8407928283 ps
CPU time 8.5 seconds
Started Apr 16 01:05:29 PM PDT 24
Finished Apr 16 01:05:38 PM PDT 24
Peak memory 203972 kb
Host smart-c2c81e4c-424d-4695-bbe2-80e707ad54a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41892
41302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.4189241302
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1570259341
Short name T403
Test name
Test status
Simulation time 8387113698 ps
CPU time 8.43 seconds
Started Apr 16 01:05:29 PM PDT 24
Finished Apr 16 01:05:38 PM PDT 24
Peak memory 204048 kb
Host smart-2786085c-91df-4bed-a6a5-388356cb1324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15702
59341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1570259341
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.2317302558
Short name T699
Test name
Test status
Simulation time 8440687215 ps
CPU time 9.13 seconds
Started Apr 16 01:05:35 PM PDT 24
Finished Apr 16 01:05:45 PM PDT 24
Peak memory 204012 kb
Host smart-651f3fe6-a445-48ec-bcb9-110a6c5f31cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23173
02558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.2317302558
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.1001986552
Short name T369
Test name
Test status
Simulation time 8376965292 ps
CPU time 7.9 seconds
Started Apr 16 01:05:37 PM PDT 24
Finished Apr 16 01:05:46 PM PDT 24
Peak memory 203888 kb
Host smart-deb18086-f2cd-4f66-913a-ad2d86a327d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10019
86552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.1001986552
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.1910705177
Short name T556
Test name
Test status
Simulation time 41473017 ps
CPU time 0.69 seconds
Started Apr 16 01:05:31 PM PDT 24
Finished Apr 16 01:05:33 PM PDT 24
Peak memory 203848 kb
Host smart-ea81b43d-3a5a-4119-804d-056ae8566c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19107
05177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.1910705177
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.3565497426
Short name T1052
Test name
Test status
Simulation time 17665840103 ps
CPU time 31.25 seconds
Started Apr 16 01:05:29 PM PDT 24
Finished Apr 16 01:06:01 PM PDT 24
Peak memory 204256 kb
Host smart-41a6edb7-c08c-4676-9572-51bb202b52ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35654
97426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.3565497426
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.1440755225
Short name T1206
Test name
Test status
Simulation time 8399445793 ps
CPU time 10.07 seconds
Started Apr 16 01:05:26 PM PDT 24
Finished Apr 16 01:05:37 PM PDT 24
Peak memory 203940 kb
Host smart-2da3d531-c428-48a6-b8b1-f47a7b09de6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14407
55225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1440755225
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.1304774405
Short name T1187
Test name
Test status
Simulation time 8390991307 ps
CPU time 7.77 seconds
Started Apr 16 01:05:37 PM PDT 24
Finished Apr 16 01:05:46 PM PDT 24
Peak memory 203908 kb
Host smart-86c661f7-ddcb-4bfc-93f1-6e65757f6e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13047
74405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.1304774405
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.1522776491
Short name T87
Test name
Test status
Simulation time 8404307467 ps
CPU time 8.8 seconds
Started Apr 16 01:05:31 PM PDT 24
Finished Apr 16 01:05:40 PM PDT 24
Peak memory 203988 kb
Host smart-22bd2de4-6f14-401b-a742-d1c426331082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15227
76491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.1522776491
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.2923069696
Short name T518
Test name
Test status
Simulation time 8407924802 ps
CPU time 8.66 seconds
Started Apr 16 01:05:31 PM PDT 24
Finished Apr 16 01:05:41 PM PDT 24
Peak memory 203992 kb
Host smart-585af085-d54a-43b4-985b-663669707249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29230
69696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.2923069696
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.246439609
Short name T1377
Test name
Test status
Simulation time 8368857008 ps
CPU time 8.52 seconds
Started Apr 16 01:05:35 PM PDT 24
Finished Apr 16 01:05:45 PM PDT 24
Peak memory 203976 kb
Host smart-8f06d074-8486-4f79-bade-98b948efa7bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24643
9609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.246439609
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.609928598
Short name T86
Test name
Test status
Simulation time 8492820711 ps
CPU time 7.62 seconds
Started Apr 16 01:05:27 PM PDT 24
Finished Apr 16 01:05:36 PM PDT 24
Peak memory 204016 kb
Host smart-8f9156c9-aca6-40d2-b828-64ec8ac8c51b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60992
8598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.609928598
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.3804452926
Short name T680
Test name
Test status
Simulation time 8399644350 ps
CPU time 8.1 seconds
Started Apr 16 01:05:26 PM PDT 24
Finished Apr 16 01:05:35 PM PDT 24
Peak memory 204000 kb
Host smart-22c3c369-d0a1-4e85-b5f0-3edd4fb21186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38044
52926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.3804452926
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.3566053738
Short name T664
Test name
Test status
Simulation time 8444889695 ps
CPU time 8.07 seconds
Started Apr 16 01:05:37 PM PDT 24
Finished Apr 16 01:05:46 PM PDT 24
Peak memory 204016 kb
Host smart-e4def001-73bf-4727-8b44-9899a54b281f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35660
53738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.3566053738
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.693122075
Short name T1081
Test name
Test status
Simulation time 8462234067 ps
CPU time 8.84 seconds
Started Apr 16 01:05:38 PM PDT 24
Finished Apr 16 01:05:48 PM PDT 24
Peak memory 203956 kb
Host smart-b7618905-2371-4f0a-8157-3ca32fa72770
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=693122075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.693122075
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.1179025802
Short name T977
Test name
Test status
Simulation time 8411911033 ps
CPU time 9.09 seconds
Started Apr 16 01:05:35 PM PDT 24
Finished Apr 16 01:05:45 PM PDT 24
Peak memory 203924 kb
Host smart-c6c26a7c-ee57-498d-b1a4-c9c81b79495e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1179025802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.1179025802
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.3134406969
Short name T980
Test name
Test status
Simulation time 8471243413 ps
CPU time 8.47 seconds
Started Apr 16 01:05:33 PM PDT 24
Finished Apr 16 01:05:42 PM PDT 24
Peak memory 203996 kb
Host smart-3444d444-0354-445f-9af1-94be8569c1f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31344
06969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.3134406969
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.2811919625
Short name T899
Test name
Test status
Simulation time 8374343996 ps
CPU time 8.08 seconds
Started Apr 16 01:05:36 PM PDT 24
Finished Apr 16 01:05:46 PM PDT 24
Peak memory 203948 kb
Host smart-d33760f4-8b2c-4fca-a867-5abe5310fbb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28119
19625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.2811919625
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_enable.3083799066
Short name T347
Test name
Test status
Simulation time 8375025418 ps
CPU time 7.96 seconds
Started Apr 16 01:05:32 PM PDT 24
Finished Apr 16 01:05:41 PM PDT 24
Peak memory 204048 kb
Host smart-2caf0393-e088-4d23-a976-8cf6133147ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30837
99066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.3083799066
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.46890399
Short name T976
Test name
Test status
Simulation time 51563569 ps
CPU time 1.15 seconds
Started Apr 16 01:05:40 PM PDT 24
Finished Apr 16 01:05:42 PM PDT 24
Peak memory 204096 kb
Host smart-b2fd27a3-116b-48bc-a9f7-5ec2a3f41d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46890
399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.46890399
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.1467925603
Short name T605
Test name
Test status
Simulation time 8385102583 ps
CPU time 9.37 seconds
Started Apr 16 01:05:30 PM PDT 24
Finished Apr 16 01:05:40 PM PDT 24
Peak memory 204044 kb
Host smart-a2a53486-d71b-425c-ae91-88805cd82755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14679
25603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.1467925603
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.191967741
Short name T194
Test name
Test status
Simulation time 8368594390 ps
CPU time 8.71 seconds
Started Apr 16 01:05:33 PM PDT 24
Finished Apr 16 01:05:43 PM PDT 24
Peak memory 203944 kb
Host smart-c6657b3d-e18b-42e7-8f59-203741ec47b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19196
7741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.191967741
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.3221063560
Short name T462
Test name
Test status
Simulation time 8423769109 ps
CPU time 9.5 seconds
Started Apr 16 01:05:36 PM PDT 24
Finished Apr 16 01:05:47 PM PDT 24
Peak memory 203980 kb
Host smart-b46c694f-bff3-46fd-9178-1b5a17926efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32210
63560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.3221063560
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3795920884
Short name T1128
Test name
Test status
Simulation time 8415048988 ps
CPU time 7.97 seconds
Started Apr 16 01:05:36 PM PDT 24
Finished Apr 16 01:05:46 PM PDT 24
Peak memory 204020 kb
Host smart-aecec3dc-83c2-4733-a3fb-b98f7d6009e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37959
20884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3795920884
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.1319196325
Short name T1226
Test name
Test status
Simulation time 8373716280 ps
CPU time 8.43 seconds
Started Apr 16 01:05:32 PM PDT 24
Finished Apr 16 01:05:42 PM PDT 24
Peak memory 204036 kb
Host smart-8c59bef1-1c93-4d03-94a0-a527ded756f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13191
96325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.1319196325
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.4288508727
Short name T1350
Test name
Test status
Simulation time 8411085942 ps
CPU time 8.97 seconds
Started Apr 16 01:05:33 PM PDT 24
Finished Apr 16 01:05:43 PM PDT 24
Peak memory 203944 kb
Host smart-822bb303-90db-42ba-aa51-2f1f4ba159ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42885
08727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.4288508727
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.2231047932
Short name T576
Test name
Test status
Simulation time 8382808737 ps
CPU time 10.3 seconds
Started Apr 16 01:05:31 PM PDT 24
Finished Apr 16 01:05:43 PM PDT 24
Peak memory 203964 kb
Host smart-4b0dd9dd-5451-4394-b1bb-8b146bf9b9e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22310
47932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.2231047932
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.58926375
Short name T508
Test name
Test status
Simulation time 8402677419 ps
CPU time 8.32 seconds
Started Apr 16 01:05:33 PM PDT 24
Finished Apr 16 01:05:43 PM PDT 24
Peak memory 203996 kb
Host smart-adc8c199-ee8b-4931-bdfc-f0af5c2f9c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58926
375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.58926375
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.2113281182
Short name T84
Test name
Test status
Simulation time 8410082874 ps
CPU time 7.48 seconds
Started Apr 16 01:05:35 PM PDT 24
Finished Apr 16 01:05:44 PM PDT 24
Peak memory 204020 kb
Host smart-42acf15c-690e-4304-ac1e-0f367f92db8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21132
81182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.2113281182
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.2075329547
Short name T421
Test name
Test status
Simulation time 8382834234 ps
CPU time 8.41 seconds
Started Apr 16 01:05:34 PM PDT 24
Finished Apr 16 01:05:44 PM PDT 24
Peak memory 203976 kb
Host smart-9a2fa936-e2ab-43dd-8490-88ac834c9d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20753
29547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.2075329547
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.3680113927
Short name T41
Test name
Test status
Simulation time 38812248 ps
CPU time 0.7 seconds
Started Apr 16 01:05:43 PM PDT 24
Finished Apr 16 01:05:45 PM PDT 24
Peak memory 203796 kb
Host smart-c62e5ef0-7685-4631-8341-c812ebc7b078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36801
13927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.3680113927
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.1259308470
Short name T1312
Test name
Test status
Simulation time 20827945248 ps
CPU time 37.17 seconds
Started Apr 16 01:05:34 PM PDT 24
Finished Apr 16 01:06:13 PM PDT 24
Peak memory 204324 kb
Host smart-7add87ae-0705-45cb-960b-111c63895fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12593
08470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.1259308470
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.3194724305
Short name T532
Test name
Test status
Simulation time 8449300662 ps
CPU time 8.7 seconds
Started Apr 16 01:05:33 PM PDT 24
Finished Apr 16 01:05:43 PM PDT 24
Peak memory 203992 kb
Host smart-c31d85ce-d805-4b6f-9789-ff566095d38c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31947
24305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.3194724305
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.1361363999
Short name T1089
Test name
Test status
Simulation time 8404753926 ps
CPU time 8.98 seconds
Started Apr 16 01:05:35 PM PDT 24
Finished Apr 16 01:05:45 PM PDT 24
Peak memory 204012 kb
Host smart-0343714a-2775-44c0-989a-8def70729427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13613
63999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.1361363999
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.875298069
Short name T500
Test name
Test status
Simulation time 8413746394 ps
CPU time 8.6 seconds
Started Apr 16 01:05:34 PM PDT 24
Finished Apr 16 01:05:43 PM PDT 24
Peak memory 203952 kb
Host smart-39aa2164-1ebe-4ed3-877c-8560d22a76c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87529
8069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.875298069
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.2686166104
Short name T158
Test name
Test status
Simulation time 8430585469 ps
CPU time 8.06 seconds
Started Apr 16 01:05:37 PM PDT 24
Finished Apr 16 01:05:46 PM PDT 24
Peak memory 204016 kb
Host smart-169c2a3a-0aed-4113-a96e-78f18d5d6e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26861
66104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.2686166104
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.3804937933
Short name T28
Test name
Test status
Simulation time 8370299518 ps
CPU time 8.42 seconds
Started Apr 16 01:05:31 PM PDT 24
Finished Apr 16 01:05:41 PM PDT 24
Peak memory 204048 kb
Host smart-54d81fd0-2a1e-41ed-ab34-2450fb9e37fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38049
37933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.3804937933
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1085907435
Short name T1320
Test name
Test status
Simulation time 8450697731 ps
CPU time 8.25 seconds
Started Apr 16 01:05:34 PM PDT 24
Finished Apr 16 01:05:44 PM PDT 24
Peak memory 204012 kb
Host smart-e45a0c9d-0c68-4f97-8fec-af13707b2361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10859
07435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1085907435
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.2326408089
Short name T323
Test name
Test status
Simulation time 8465471434 ps
CPU time 9 seconds
Started Apr 16 01:05:34 PM PDT 24
Finished Apr 16 01:05:44 PM PDT 24
Peak memory 204044 kb
Host smart-9c39ed5a-1bf5-49da-8471-d555fc83a0f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23264
08089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.2326408089
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.543051236
Short name T481
Test name
Test status
Simulation time 8399827270 ps
CPU time 8.62 seconds
Started Apr 16 01:05:32 PM PDT 24
Finished Apr 16 01:05:42 PM PDT 24
Peak memory 203980 kb
Host smart-e56c0a82-1e32-4d16-9998-5a8b07ba944a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54305
1236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.543051236
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.3783677078
Short name T979
Test name
Test status
Simulation time 8466438297 ps
CPU time 8.03 seconds
Started Apr 16 01:05:36 PM PDT 24
Finished Apr 16 01:05:46 PM PDT 24
Peak memory 204020 kb
Host smart-d01d907c-c6ed-4221-95f6-5b233a2b1605
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3783677078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.3783677078
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.3326442155
Short name T1360
Test name
Test status
Simulation time 8384593985 ps
CPU time 7.27 seconds
Started Apr 16 01:05:35 PM PDT 24
Finished Apr 16 01:05:43 PM PDT 24
Peak memory 204044 kb
Host smart-42e0d350-836d-4277-84d0-a4f01415ac30
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3326442155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.3326442155
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.368145912
Short name T308
Test name
Test status
Simulation time 8478729255 ps
CPU time 8.09 seconds
Started Apr 16 01:05:39 PM PDT 24
Finished Apr 16 01:05:48 PM PDT 24
Peak memory 204040 kb
Host smart-65e65f8e-dff2-4f8a-b388-e18615e76e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36814
5912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.368145912
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.2840170010
Short name T1015
Test name
Test status
Simulation time 8378391656 ps
CPU time 7.82 seconds
Started Apr 16 01:05:39 PM PDT 24
Finished Apr 16 01:05:48 PM PDT 24
Peak memory 203988 kb
Host smart-48a280b6-5605-446a-a260-b1808c41253d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28401
70010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.2840170010
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_enable.1500569618
Short name T319
Test name
Test status
Simulation time 8387152353 ps
CPU time 8.52 seconds
Started Apr 16 01:05:37 PM PDT 24
Finished Apr 16 01:05:47 PM PDT 24
Peak memory 204028 kb
Host smart-6cbd3d0e-c38c-4140-a873-99a34901664f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15005
69618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.1500569618
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.4288030202
Short name T1063
Test name
Test status
Simulation time 150029181 ps
CPU time 1.34 seconds
Started Apr 16 01:05:39 PM PDT 24
Finished Apr 16 01:05:41 PM PDT 24
Peak memory 204168 kb
Host smart-78b0da27-9765-4489-b6aa-7f5f6d8ddd54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42880
30202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.4288030202
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.2217111885
Short name T897
Test name
Test status
Simulation time 8435977085 ps
CPU time 9.62 seconds
Started Apr 16 01:05:39 PM PDT 24
Finished Apr 16 01:05:50 PM PDT 24
Peak memory 204084 kb
Host smart-2f1c32de-b8c0-47d1-8c4c-3c71246f4571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22171
11885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.2217111885
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.3574840912
Short name T196
Test name
Test status
Simulation time 8383232244 ps
CPU time 10.03 seconds
Started Apr 16 01:05:41 PM PDT 24
Finished Apr 16 01:05:52 PM PDT 24
Peak memory 204016 kb
Host smart-4454e657-5825-4ae4-8a54-a5781961205b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35748
40912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.3574840912
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.1675773537
Short name T142
Test name
Test status
Simulation time 8418581176 ps
CPU time 8.14 seconds
Started Apr 16 01:05:38 PM PDT 24
Finished Apr 16 01:05:47 PM PDT 24
Peak memory 204084 kb
Host smart-21612502-968a-4150-a2ad-ced2d0104b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16757
73537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.1675773537
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.1778255134
Short name T477
Test name
Test status
Simulation time 8421779544 ps
CPU time 8.04 seconds
Started Apr 16 01:05:38 PM PDT 24
Finished Apr 16 01:05:47 PM PDT 24
Peak memory 203932 kb
Host smart-634ea948-6ac0-4e07-9bc2-341846648f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17782
55134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.1778255134
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3205100887
Short name T787
Test name
Test status
Simulation time 8368064070 ps
CPU time 9.59 seconds
Started Apr 16 01:05:40 PM PDT 24
Finished Apr 16 01:05:51 PM PDT 24
Peak memory 204028 kb
Host smart-8aff10de-5cbd-4fcb-80e4-a5d9dfdf992e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32051
00887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3205100887
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.4136216835
Short name T855
Test name
Test status
Simulation time 8451734185 ps
CPU time 7.45 seconds
Started Apr 16 01:05:39 PM PDT 24
Finished Apr 16 01:05:48 PM PDT 24
Peak memory 203972 kb
Host smart-a737729a-f86c-40ec-ba0c-da8dedf701be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41362
16835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.4136216835
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.214512283
Short name T704
Test name
Test status
Simulation time 8410940771 ps
CPU time 8.55 seconds
Started Apr 16 01:05:38 PM PDT 24
Finished Apr 16 01:05:48 PM PDT 24
Peak memory 203988 kb
Host smart-3c6b5438-46b6-47b3-a393-536bda585b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21451
2283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.214512283
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.1461204206
Short name T289
Test name
Test status
Simulation time 8381141457 ps
CPU time 8.68 seconds
Started Apr 16 01:05:39 PM PDT 24
Finished Apr 16 01:05:48 PM PDT 24
Peak memory 204016 kb
Host smart-12370a9d-79fe-49a5-89e6-9290ea3eff09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14612
04206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.1461204206
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.3480259338
Short name T152
Test name
Test status
Simulation time 8400705163 ps
CPU time 8.09 seconds
Started Apr 16 01:05:35 PM PDT 24
Finished Apr 16 01:05:45 PM PDT 24
Peak memory 204024 kb
Host smart-d9bb9538-16b8-4b09-8790-b007d8644e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34802
59338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.3480259338
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3757752328
Short name T1287
Test name
Test status
Simulation time 8372183550 ps
CPU time 8.41 seconds
Started Apr 16 01:05:36 PM PDT 24
Finished Apr 16 01:05:46 PM PDT 24
Peak memory 204008 kb
Host smart-54e69a6b-752f-4ec2-bf40-290fe44fab86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37577
52328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3757752328
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.2561912840
Short name T668
Test name
Test status
Simulation time 46212541 ps
CPU time 0.68 seconds
Started Apr 16 01:05:37 PM PDT 24
Finished Apr 16 01:05:39 PM PDT 24
Peak memory 203872 kb
Host smart-254b1646-9467-4617-823f-cbc400d36bda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25619
12840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.2561912840
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.1949207941
Short name T1106
Test name
Test status
Simulation time 23707089355 ps
CPU time 45.84 seconds
Started Apr 16 01:05:36 PM PDT 24
Finished Apr 16 01:06:23 PM PDT 24
Peak memory 204316 kb
Host smart-bad169a4-5c17-4c52-8520-52300117876b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19492
07941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.1949207941
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3255338645
Short name T318
Test name
Test status
Simulation time 8385881796 ps
CPU time 7.98 seconds
Started Apr 16 01:05:40 PM PDT 24
Finished Apr 16 01:05:49 PM PDT 24
Peak memory 204028 kb
Host smart-526b987f-a160-473e-a3ef-77416836723c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32553
38645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3255338645
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.4148153355
Short name T145
Test name
Test status
Simulation time 8450411666 ps
CPU time 9.44 seconds
Started Apr 16 01:05:40 PM PDT 24
Finished Apr 16 01:05:50 PM PDT 24
Peak memory 204020 kb
Host smart-26c5d109-f177-418f-b86e-f3126699d2ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41481
53355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.4148153355
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.3566140813
Short name T336
Test name
Test status
Simulation time 8399795076 ps
CPU time 9.94 seconds
Started Apr 16 01:05:37 PM PDT 24
Finished Apr 16 01:05:49 PM PDT 24
Peak memory 204036 kb
Host smart-ca42c704-3ec3-414c-9884-43d7894b887e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35661
40813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.3566140813
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.2453396622
Short name T1205
Test name
Test status
Simulation time 8388797859 ps
CPU time 7.86 seconds
Started Apr 16 01:05:38 PM PDT 24
Finished Apr 16 01:05:47 PM PDT 24
Peak memory 204020 kb
Host smart-cca40c3f-9c6d-4b8d-ac8a-4a56a18151e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24533
96622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.2453396622
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.2557999637
Short name T1319
Test name
Test status
Simulation time 8364810566 ps
CPU time 7.86 seconds
Started Apr 16 01:05:38 PM PDT 24
Finished Apr 16 01:05:47 PM PDT 24
Peak memory 204024 kb
Host smart-838bc6e2-90a8-4a17-afdc-d35f9a2ac975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25579
99637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.2557999637
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.1612134564
Short name T955
Test name
Test status
Simulation time 8420590241 ps
CPU time 9.48 seconds
Started Apr 16 01:05:36 PM PDT 24
Finished Apr 16 01:05:47 PM PDT 24
Peak memory 203948 kb
Host smart-0e96d7b2-936d-4c1c-be45-4aa71d8a7e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16121
34564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.1612134564
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.1891989507
Short name T551
Test name
Test status
Simulation time 8388483401 ps
CPU time 7.55 seconds
Started Apr 16 01:05:43 PM PDT 24
Finished Apr 16 01:05:52 PM PDT 24
Peak memory 203924 kb
Host smart-c78843a1-2839-4839-88ca-f4bb14f1eec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18919
89507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.1891989507
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.2887688245
Short name T931
Test name
Test status
Simulation time 8377955332 ps
CPU time 9.72 seconds
Started Apr 16 01:05:37 PM PDT 24
Finished Apr 16 01:05:48 PM PDT 24
Peak memory 203904 kb
Host smart-21c68f30-6300-4432-8b69-f9e56ba2f274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28876
88245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.2887688245
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.1793108254
Short name T673
Test name
Test status
Simulation time 8494401849 ps
CPU time 7.92 seconds
Started Apr 16 01:01:46 PM PDT 24
Finished Apr 16 01:01:55 PM PDT 24
Peak memory 204004 kb
Host smart-f35defc7-8e32-4729-b6f4-c290f96c98d0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1793108254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.1793108254
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.3777324425
Short name T742
Test name
Test status
Simulation time 8382426398 ps
CPU time 8.08 seconds
Started Apr 16 01:01:45 PM PDT 24
Finished Apr 16 01:01:54 PM PDT 24
Peak memory 204040 kb
Host smart-4a60704e-6f2d-43e7-a277-ed8eadefc328
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3777324425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.3777324425
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.2271398677
Short name T766
Test name
Test status
Simulation time 8448966789 ps
CPU time 10.33 seconds
Started Apr 16 01:01:46 PM PDT 24
Finished Apr 16 01:01:57 PM PDT 24
Peak memory 204036 kb
Host smart-5fbedd67-f45c-453f-a7d8-ee4c5f8ae996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22713
98677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.2271398677
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.2627472420
Short name T802
Test name
Test status
Simulation time 8374306026 ps
CPU time 8.62 seconds
Started Apr 16 01:01:42 PM PDT 24
Finished Apr 16 01:01:51 PM PDT 24
Peak memory 204020 kb
Host smart-12c0442a-4502-41a5-8425-0b20a4aa71fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26274
72420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.2627472420
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_enable.501361062
Short name T478
Test name
Test status
Simulation time 8376234019 ps
CPU time 10.26 seconds
Started Apr 16 01:01:39 PM PDT 24
Finished Apr 16 01:01:50 PM PDT 24
Peak memory 204004 kb
Host smart-894731f4-da62-4d8e-abd3-f1e212f581a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50136
1062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.501361062
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.4005114527
Short name T1288
Test name
Test status
Simulation time 125347376 ps
CPU time 2.02 seconds
Started Apr 16 01:01:40 PM PDT 24
Finished Apr 16 01:01:43 PM PDT 24
Peak memory 204104 kb
Host smart-7a85fdb3-025f-4da8-8985-495ea580cbf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40051
14527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.4005114527
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.1885473034
Short name T667
Test name
Test status
Simulation time 8441960759 ps
CPU time 7.59 seconds
Started Apr 16 01:01:45 PM PDT 24
Finished Apr 16 01:01:53 PM PDT 24
Peak memory 204000 kb
Host smart-68f007f1-17e6-413e-b8b1-082efa9bfa91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18854
73034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.1885473034
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.2984372339
Short name T1108
Test name
Test status
Simulation time 8375887892 ps
CPU time 9.42 seconds
Started Apr 16 01:01:45 PM PDT 24
Finished Apr 16 01:01:55 PM PDT 24
Peak memory 203988 kb
Host smart-a9fec872-1e6d-4c25-8c20-9ad047476869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29843
72339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.2984372339
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.1316731297
Short name T136
Test name
Test status
Simulation time 8390635844 ps
CPU time 7.7 seconds
Started Apr 16 01:01:44 PM PDT 24
Finished Apr 16 01:01:52 PM PDT 24
Peak memory 203964 kb
Host smart-f683bcb3-8381-43af-aa87-ba0b141de1d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13167
31297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1316731297
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3897151376
Short name T283
Test name
Test status
Simulation time 8514693857 ps
CPU time 9.27 seconds
Started Apr 16 01:01:40 PM PDT 24
Finished Apr 16 01:01:50 PM PDT 24
Peak memory 204048 kb
Host smart-48da30f6-18f1-48f1-90d0-6c0b239368a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38971
51376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3897151376
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1821388927
Short name T1159
Test name
Test status
Simulation time 8376905610 ps
CPU time 8.86 seconds
Started Apr 16 01:01:40 PM PDT 24
Finished Apr 16 01:01:49 PM PDT 24
Peak memory 204048 kb
Host smart-e3fc4040-92e0-401a-bff4-e3a0c97a2f0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18213
88927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1821388927
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1271747064
Short name T1100
Test name
Test status
Simulation time 8466574821 ps
CPU time 8.62 seconds
Started Apr 16 01:01:43 PM PDT 24
Finished Apr 16 01:01:52 PM PDT 24
Peak memory 204048 kb
Host smart-9ac67452-49a0-4d21-977f-83b0e16044a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12717
47064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1271747064
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.3005975397
Short name T228
Test name
Test status
Simulation time 8376931875 ps
CPU time 9.76 seconds
Started Apr 16 01:01:43 PM PDT 24
Finished Apr 16 01:01:53 PM PDT 24
Peak memory 204020 kb
Host smart-17443d9a-e6ea-4d78-95ee-1dcd1e941781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30059
75397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.3005975397
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.2266657155
Short name T1280
Test name
Test status
Simulation time 8408771948 ps
CPU time 9.19 seconds
Started Apr 16 01:01:38 PM PDT 24
Finished Apr 16 01:01:48 PM PDT 24
Peak memory 204032 kb
Host smart-9562c2da-8e8a-4305-8dd7-4eefc1f21023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22666
57155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2266657155
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.99788391
Short name T153
Test name
Test status
Simulation time 8472440658 ps
CPU time 9.8 seconds
Started Apr 16 01:01:40 PM PDT 24
Finished Apr 16 01:01:51 PM PDT 24
Peak memory 204260 kb
Host smart-12f4f7e9-4125-421e-91b8-57675b8f40d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99788
391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.99788391
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.651519798
Short name T939
Test name
Test status
Simulation time 8363596283 ps
CPU time 8.76 seconds
Started Apr 16 01:01:44 PM PDT 24
Finished Apr 16 01:01:53 PM PDT 24
Peak memory 203964 kb
Host smart-b4c7c51c-b36e-4522-8569-9b9ebfebe948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65151
9798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.651519798
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.2049943581
Short name T43
Test name
Test status
Simulation time 34885393 ps
CPU time 0.64 seconds
Started Apr 16 01:01:45 PM PDT 24
Finished Apr 16 01:01:47 PM PDT 24
Peak memory 203920 kb
Host smart-a81dda14-b582-4f46-b800-14c29ab5b854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20499
43581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.2049943581
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.1475555350
Short name T239
Test name
Test status
Simulation time 15382660578 ps
CPU time 25.23 seconds
Started Apr 16 01:01:41 PM PDT 24
Finished Apr 16 01:02:07 PM PDT 24
Peak memory 204268 kb
Host smart-cec1ecf4-f5f2-452d-8155-b4a2b09f2d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14755
55350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.1475555350
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.3774792151
Short name T1362
Test name
Test status
Simulation time 8399184398 ps
CPU time 8.65 seconds
Started Apr 16 01:01:44 PM PDT 24
Finished Apr 16 01:01:53 PM PDT 24
Peak memory 203968 kb
Host smart-6d9e1928-a975-468d-b762-2d46437ab80f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37747
92151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.3774792151
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.3100070567
Short name T585
Test name
Test status
Simulation time 8403258126 ps
CPU time 7.83 seconds
Started Apr 16 01:01:42 PM PDT 24
Finished Apr 16 01:01:50 PM PDT 24
Peak memory 204028 kb
Host smart-bb9644a4-779a-41f9-81ac-a081fb78fe00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31000
70567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.3100070567
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.565449489
Short name T1289
Test name
Test status
Simulation time 8401534015 ps
CPU time 7.83 seconds
Started Apr 16 01:01:39 PM PDT 24
Finished Apr 16 01:01:47 PM PDT 24
Peak memory 204012 kb
Host smart-a10002fa-1130-4ee5-bd4b-f30f5a319b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56544
9489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.565449489
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.3286332502
Short name T168
Test name
Test status
Simulation time 8396264740 ps
CPU time 8.85 seconds
Started Apr 16 01:01:40 PM PDT 24
Finished Apr 16 01:01:49 PM PDT 24
Peak memory 204036 kb
Host smart-7da5e5db-8b91-4739-97c2-f421ce693f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32863
32502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.3286332502
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3132968276
Short name T798
Test name
Test status
Simulation time 8371152298 ps
CPU time 7.7 seconds
Started Apr 16 01:01:40 PM PDT 24
Finished Apr 16 01:01:48 PM PDT 24
Peak memory 203972 kb
Host smart-917efdef-8696-4765-ba71-5289246714c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31329
68276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3132968276
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1252358484
Short name T150
Test name
Test status
Simulation time 8459609901 ps
CPU time 8.12 seconds
Started Apr 16 01:01:39 PM PDT 24
Finished Apr 16 01:01:47 PM PDT 24
Peak memory 204040 kb
Host smart-d5e7f858-b03f-4b86-acfa-0c8fd753d64b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12523
58484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1252358484
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.750204103
Short name T1211
Test name
Test status
Simulation time 8376968353 ps
CPU time 8.74 seconds
Started Apr 16 01:01:43 PM PDT 24
Finished Apr 16 01:01:52 PM PDT 24
Peak memory 204044 kb
Host smart-c187bbed-1c91-4258-bc66-a9eb1ec6f858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75020
4103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.750204103
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.238472413
Short name T1266
Test name
Test status
Simulation time 8406834304 ps
CPU time 10.44 seconds
Started Apr 16 01:01:41 PM PDT 24
Finished Apr 16 01:01:51 PM PDT 24
Peak memory 204032 kb
Host smart-cf9d0149-0ca0-4aca-a05a-51d5dcaced57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23847
2413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.238472413
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.3524223612
Short name T302
Test name
Test status
Simulation time 8478810448 ps
CPU time 8.45 seconds
Started Apr 16 01:01:49 PM PDT 24
Finished Apr 16 01:01:59 PM PDT 24
Peak memory 204052 kb
Host smart-d7d315ff-2f2d-424e-bb14-81a1a21b7619
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3524223612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.3524223612
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.3523172848
Short name T410
Test name
Test status
Simulation time 8382686973 ps
CPU time 8.31 seconds
Started Apr 16 01:01:52 PM PDT 24
Finished Apr 16 01:02:01 PM PDT 24
Peak memory 203956 kb
Host smart-f818e1ec-9150-4e8d-ac7f-6ad78c5b9e71
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3523172848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.3523172848
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.243934935
Short name T1005
Test name
Test status
Simulation time 8450495732 ps
CPU time 9.99 seconds
Started Apr 16 01:01:49 PM PDT 24
Finished Apr 16 01:02:00 PM PDT 24
Peak memory 204048 kb
Host smart-e9182f52-f30f-4fb7-814b-858940a632a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24393
4935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.243934935
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.966982565
Short name T299
Test name
Test status
Simulation time 8388684460 ps
CPU time 8.02 seconds
Started Apr 16 01:01:46 PM PDT 24
Finished Apr 16 01:01:55 PM PDT 24
Peak memory 203944 kb
Host smart-f93f1e34-1855-421a-b930-a7b7de23daae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96698
2565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.966982565
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_enable.439367778
Short name T282
Test name
Test status
Simulation time 8375763051 ps
CPU time 9.83 seconds
Started Apr 16 01:01:44 PM PDT 24
Finished Apr 16 01:01:54 PM PDT 24
Peak memory 203920 kb
Host smart-f0c81556-e598-4caf-9e91-13c721d6f230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43936
7778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.439367778
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.4011896065
Short name T1233
Test name
Test status
Simulation time 126655981 ps
CPU time 1.44 seconds
Started Apr 16 01:01:44 PM PDT 24
Finished Apr 16 01:01:46 PM PDT 24
Peak memory 204088 kb
Host smart-52a81f99-d5de-4b33-8135-75bddaca05b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40118
96065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.4011896065
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.3470336477
Short name T570
Test name
Test status
Simulation time 8461550983 ps
CPU time 8.68 seconds
Started Apr 16 01:01:49 PM PDT 24
Finished Apr 16 01:01:58 PM PDT 24
Peak memory 204008 kb
Host smart-c636d0a1-0dcb-44c5-9bb4-f33fd7deadbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34703
36477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.3470336477
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.2452102186
Short name T191
Test name
Test status
Simulation time 8362954417 ps
CPU time 7.64 seconds
Started Apr 16 01:01:48 PM PDT 24
Finished Apr 16 01:01:56 PM PDT 24
Peak memory 204028 kb
Host smart-5374b9cc-7598-4478-bb07-c0a095a35115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24521
02186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.2452102186
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.960724851
Short name T547
Test name
Test status
Simulation time 8432788680 ps
CPU time 8.13 seconds
Started Apr 16 01:01:49 PM PDT 24
Finished Apr 16 01:01:58 PM PDT 24
Peak memory 204028 kb
Host smart-b8751b97-e21a-4413-b5d4-4ae5f7612983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96072
4851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.960724851
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.2387078329
Short name T1129
Test name
Test status
Simulation time 8415231760 ps
CPU time 9.21 seconds
Started Apr 16 01:01:49 PM PDT 24
Finished Apr 16 01:01:59 PM PDT 24
Peak memory 203948 kb
Host smart-40500912-08d4-45b2-bac5-02a6e0fe7327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23870
78329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.2387078329
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.3312609891
Short name T293
Test name
Test status
Simulation time 8371669344 ps
CPU time 7.83 seconds
Started Apr 16 01:01:46 PM PDT 24
Finished Apr 16 01:01:55 PM PDT 24
Peak memory 204032 kb
Host smart-24594d87-8c94-4bad-a339-60f42ba08e84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33126
09891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.3312609891
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3021529101
Short name T98
Test name
Test status
Simulation time 8490846507 ps
CPU time 8.38 seconds
Started Apr 16 01:01:45 PM PDT 24
Finished Apr 16 01:01:54 PM PDT 24
Peak memory 204040 kb
Host smart-69289dd3-6bdc-4e4e-948b-72bc21912925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30215
29101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3021529101
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.1068471228
Short name T324
Test name
Test status
Simulation time 8408043505 ps
CPU time 7.89 seconds
Started Apr 16 01:01:49 PM PDT 24
Finished Apr 16 01:01:58 PM PDT 24
Peak memory 204044 kb
Host smart-6a66011d-3520-427e-87b1-5a7d0e2a74b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10684
71228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.1068471228
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.3647072198
Short name T878
Test name
Test status
Simulation time 8421906825 ps
CPU time 7.96 seconds
Started Apr 16 01:01:51 PM PDT 24
Finished Apr 16 01:01:59 PM PDT 24
Peak memory 204048 kb
Host smart-36b09666-c345-4a9f-a5d7-0d7c872a6f74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36470
72198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.3647072198
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.2445948979
Short name T789
Test name
Test status
Simulation time 8405874218 ps
CPU time 8.09 seconds
Started Apr 16 01:01:51 PM PDT 24
Finished Apr 16 01:02:00 PM PDT 24
Peak memory 203952 kb
Host smart-de00b496-28bc-4453-b8dd-612830113728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24459
48979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.2445948979
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.2644756043
Short name T786
Test name
Test status
Simulation time 8371316215 ps
CPU time 7.67 seconds
Started Apr 16 01:01:49 PM PDT 24
Finished Apr 16 01:01:57 PM PDT 24
Peak memory 204016 kb
Host smart-b819d263-901e-4272-9341-6f6f119fa4bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26447
56043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.2644756043
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.2532923714
Short name T1138
Test name
Test status
Simulation time 62354152 ps
CPU time 0.68 seconds
Started Apr 16 01:01:51 PM PDT 24
Finished Apr 16 01:01:53 PM PDT 24
Peak memory 203860 kb
Host smart-24c9b8aa-8fc8-4328-8e92-06a2c64a2690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25329
23714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.2532923714
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.3311190522
Short name T213
Test name
Test status
Simulation time 29615352746 ps
CPU time 57.19 seconds
Started Apr 16 01:01:45 PM PDT 24
Finished Apr 16 01:02:43 PM PDT 24
Peak memory 204188 kb
Host smart-8cec93ee-e7ac-4922-b4dc-68a3a2ed951c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33111
90522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.3311190522
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.880444037
Short name T566
Test name
Test status
Simulation time 8421325968 ps
CPU time 10.6 seconds
Started Apr 16 01:01:46 PM PDT 24
Finished Apr 16 01:01:58 PM PDT 24
Peak memory 204032 kb
Host smart-ca394422-c7ae-4bcc-8f6a-f589a2b3eb1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88044
4037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.880444037
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.422817850
Short name T568
Test name
Test status
Simulation time 8398171061 ps
CPU time 8.19 seconds
Started Apr 16 01:01:42 PM PDT 24
Finished Apr 16 01:01:51 PM PDT 24
Peak memory 204036 kb
Host smart-98675015-25a9-4483-8a8a-c5e690d644a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42281
7850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.422817850
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.2159090018
Short name T748
Test name
Test status
Simulation time 8417315464 ps
CPU time 8.28 seconds
Started Apr 16 01:01:49 PM PDT 24
Finished Apr 16 01:01:58 PM PDT 24
Peak memory 203948 kb
Host smart-e6230f9b-5075-49eb-aa96-c9dd959f17bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21590
90018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.2159090018
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.252493798
Short name T981
Test name
Test status
Simulation time 8379406010 ps
CPU time 8.51 seconds
Started Apr 16 01:01:51 PM PDT 24
Finished Apr 16 01:02:01 PM PDT 24
Peak memory 203992 kb
Host smart-ba6e5f46-9148-49a1-acf2-43928d19c941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25249
3798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.252493798
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.3755564801
Short name T338
Test name
Test status
Simulation time 8399606991 ps
CPU time 8.73 seconds
Started Apr 16 01:01:51 PM PDT 24
Finished Apr 16 01:02:01 PM PDT 24
Peak memory 204028 kb
Host smart-f2edbde9-eeef-4236-8915-a04115477327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37555
64801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.3755564801
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.3009444927
Short name T1184
Test name
Test status
Simulation time 8447705610 ps
CPU time 7.96 seconds
Started Apr 16 01:01:44 PM PDT 24
Finished Apr 16 01:01:53 PM PDT 24
Peak memory 203948 kb
Host smart-7e0b89b4-1c7d-41ca-a0d0-0ee12dad1fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30094
44927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3009444927
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.968216961
Short name T320
Test name
Test status
Simulation time 8401603807 ps
CPU time 8 seconds
Started Apr 16 01:01:49 PM PDT 24
Finished Apr 16 01:01:58 PM PDT 24
Peak memory 204048 kb
Host smart-d507ec61-bcd5-46a1-8a5d-162263696a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96821
6961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.968216961
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.1506429792
Short name T17
Test name
Test status
Simulation time 8386273244 ps
CPU time 7.76 seconds
Started Apr 16 01:01:52 PM PDT 24
Finished Apr 16 01:02:01 PM PDT 24
Peak memory 203976 kb
Host smart-dc4da9b6-e430-444f-adea-83fccbc8771d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15064
29792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.1506429792
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.3831945083
Short name T1262
Test name
Test status
Simulation time 8467302198 ps
CPU time 7.82 seconds
Started Apr 16 01:01:56 PM PDT 24
Finished Apr 16 01:02:05 PM PDT 24
Peak memory 203940 kb
Host smart-b3810a5f-4659-48fc-bb14-69b9a7dc28ba
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3831945083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.3831945083
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.2537826215
Short name T1125
Test name
Test status
Simulation time 8373912319 ps
CPU time 8.24 seconds
Started Apr 16 01:01:57 PM PDT 24
Finished Apr 16 01:02:06 PM PDT 24
Peak memory 203960 kb
Host smart-c699f1c5-812b-4fd1-8652-69b2f71d4dcf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2537826215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.2537826215
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.2331497540
Short name T350
Test name
Test status
Simulation time 8380749286 ps
CPU time 10.39 seconds
Started Apr 16 01:01:56 PM PDT 24
Finished Apr 16 01:02:08 PM PDT 24
Peak memory 204024 kb
Host smart-c7f57cbc-f89b-44a8-a908-395a00ce638f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23314
97540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.2331497540
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.1717869630
Short name T310
Test name
Test status
Simulation time 8388563845 ps
CPU time 7.71 seconds
Started Apr 16 01:01:51 PM PDT 24
Finished Apr 16 01:02:00 PM PDT 24
Peak memory 204048 kb
Host smart-1918aa5d-d193-43fe-a471-c4b6b174f6e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17178
69630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.1717869630
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_enable.3326583186
Short name T826
Test name
Test status
Simulation time 8398097756 ps
CPU time 9.69 seconds
Started Apr 16 01:01:49 PM PDT 24
Finished Apr 16 01:02:00 PM PDT 24
Peak memory 204020 kb
Host smart-36e3ba80-d9cb-49fb-be6c-5a1b2096bba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33265
83186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.3326583186
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2715266056
Short name T422
Test name
Test status
Simulation time 72951451 ps
CPU time 1.71 seconds
Started Apr 16 01:01:53 PM PDT 24
Finished Apr 16 01:01:56 PM PDT 24
Peak memory 204148 kb
Host smart-42519400-8523-4a19-8c9e-cc3f3f3909e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27152
66056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2715266056
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.4085856693
Short name T639
Test name
Test status
Simulation time 8454299567 ps
CPU time 8.34 seconds
Started Apr 16 01:01:54 PM PDT 24
Finished Apr 16 01:02:04 PM PDT 24
Peak memory 203920 kb
Host smart-42aded5b-c1b5-4349-8ac0-27b1f15a7734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40858
56693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.4085856693
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3319394852
Short name T1094
Test name
Test status
Simulation time 8364908146 ps
CPU time 8.07 seconds
Started Apr 16 01:01:53 PM PDT 24
Finished Apr 16 01:02:02 PM PDT 24
Peak memory 203980 kb
Host smart-ad3c872d-5f57-4ffb-a52b-645ba07dd54a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33193
94852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3319394852
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3128042947
Short name T454
Test name
Test status
Simulation time 8411285310 ps
CPU time 9.04 seconds
Started Apr 16 01:01:53 PM PDT 24
Finished Apr 16 01:02:03 PM PDT 24
Peak memory 204084 kb
Host smart-0b48d5d9-a55b-4935-b4b5-0938db1ab963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31280
42947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3128042947
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3737073257
Short name T1367
Test name
Test status
Simulation time 8422161292 ps
CPU time 9.77 seconds
Started Apr 16 01:01:52 PM PDT 24
Finished Apr 16 01:02:02 PM PDT 24
Peak memory 204048 kb
Host smart-29f4c586-384b-41c1-94ad-4651c0df7c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37370
73257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3737073257
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.3733304202
Short name T1365
Test name
Test status
Simulation time 8373306269 ps
CPU time 8.05 seconds
Started Apr 16 01:01:53 PM PDT 24
Finished Apr 16 01:02:02 PM PDT 24
Peak memory 204016 kb
Host smart-1aee9bc6-29c2-4ca4-bcc1-8e49920c87f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37333
04202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.3733304202
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.2625696085
Short name T932
Test name
Test status
Simulation time 8436849982 ps
CPU time 10.12 seconds
Started Apr 16 01:01:55 PM PDT 24
Finished Apr 16 01:02:06 PM PDT 24
Peak memory 204020 kb
Host smart-09fcb130-8daf-49af-bb7e-722bcc3b31eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26256
96085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.2625696085
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.4185544171
Short name T795
Test name
Test status
Simulation time 8388025282 ps
CPU time 7.8 seconds
Started Apr 16 01:01:54 PM PDT 24
Finished Apr 16 01:02:02 PM PDT 24
Peak memory 204024 kb
Host smart-44a775eb-a682-470a-9972-81e966b3da93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41855
44171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.4185544171
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.2256800381
Short name T730
Test name
Test status
Simulation time 8383437187 ps
CPU time 7.68 seconds
Started Apr 16 01:01:57 PM PDT 24
Finished Apr 16 01:02:05 PM PDT 24
Peak memory 204068 kb
Host smart-d5915edc-7c65-434f-9df9-f02f0072c760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22568
00381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.2256800381
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.270723434
Short name T167
Test name
Test status
Simulation time 8401508809 ps
CPU time 7.8 seconds
Started Apr 16 01:01:53 PM PDT 24
Finished Apr 16 01:02:02 PM PDT 24
Peak memory 204040 kb
Host smart-a147d32a-d0bd-4f53-9706-8486d15c95f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27072
3434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.270723434
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.81757521
Short name T1221
Test name
Test status
Simulation time 8410183561 ps
CPU time 8.03 seconds
Started Apr 16 01:01:54 PM PDT 24
Finished Apr 16 01:02:03 PM PDT 24
Peak memory 204044 kb
Host smart-4cc34b37-39d5-40a4-ac65-71fc78798d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81757
521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.81757521
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.605156827
Short name T210
Test name
Test status
Simulation time 42582352 ps
CPU time 0.66 seconds
Started Apr 16 01:01:53 PM PDT 24
Finished Apr 16 01:01:54 PM PDT 24
Peak memory 203828 kb
Host smart-31ba4711-df65-4254-af7a-f21c8623227b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60515
6827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.605156827
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.2021744585
Short name T211
Test name
Test status
Simulation time 24982758054 ps
CPU time 54.02 seconds
Started Apr 16 01:01:53 PM PDT 24
Finished Apr 16 01:02:48 PM PDT 24
Peak memory 204300 kb
Host smart-b124e886-01f8-4feb-9c0b-2490b3e34975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20217
44585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.2021744585
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.721487188
Short name T1209
Test name
Test status
Simulation time 8378109532 ps
CPU time 9.37 seconds
Started Apr 16 01:01:55 PM PDT 24
Finished Apr 16 01:02:05 PM PDT 24
Peak memory 203304 kb
Host smart-18b8b288-0bfd-465b-813d-15d4b94854d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72148
7188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.721487188
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.625976717
Short name T773
Test name
Test status
Simulation time 8437602790 ps
CPU time 8.98 seconds
Started Apr 16 01:01:57 PM PDT 24
Finished Apr 16 01:02:06 PM PDT 24
Peak memory 204256 kb
Host smart-d9b7b6a0-3a26-419d-944e-c22e65bf8cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62597
6717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.625976717
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.1695647438
Short name T303
Test name
Test status
Simulation time 8395728065 ps
CPU time 8.63 seconds
Started Apr 16 01:01:58 PM PDT 24
Finished Apr 16 01:02:08 PM PDT 24
Peak memory 203980 kb
Host smart-515c2dd1-b21f-4022-887c-0d248a411631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16956
47438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.1695647438
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.547915293
Short name T27
Test name
Test status
Simulation time 8413372325 ps
CPU time 7.92 seconds
Started Apr 16 01:01:55 PM PDT 24
Finished Apr 16 01:02:04 PM PDT 24
Peak memory 204044 kb
Host smart-f6d54924-d8d6-452e-bf2a-831d1b27bc0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54791
5293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.547915293
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.1337792117
Short name T1203
Test name
Test status
Simulation time 8365175547 ps
CPU time 8.8 seconds
Started Apr 16 01:01:54 PM PDT 24
Finished Apr 16 01:02:04 PM PDT 24
Peak memory 203968 kb
Host smart-7381db04-d4da-410f-9f82-ef80d4d1dbbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13377
92117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.1337792117
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.1837807585
Short name T426
Test name
Test status
Simulation time 8469148348 ps
CPU time 8.86 seconds
Started Apr 16 01:01:51 PM PDT 24
Finished Apr 16 01:02:01 PM PDT 24
Peak memory 204004 kb
Host smart-2a00b28a-eee5-4310-ab92-222b6bfb3dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18378
07585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.1837807585
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.1868749721
Short name T1160
Test name
Test status
Simulation time 8416798375 ps
CPU time 8.12 seconds
Started Apr 16 01:01:56 PM PDT 24
Finished Apr 16 01:02:05 PM PDT 24
Peak memory 204020 kb
Host smart-7b05dbd4-d043-4916-80b0-9267cf3bd53d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18687
49721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.1868749721
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.2891002957
Short name T751
Test name
Test status
Simulation time 8394225855 ps
CPU time 9.05 seconds
Started Apr 16 01:01:56 PM PDT 24
Finished Apr 16 01:02:06 PM PDT 24
Peak memory 204028 kb
Host smart-fac748c7-bd10-4a05-b133-c92831cc52f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28910
02957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.2891002957
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.2072373705
Short name T48
Test name
Test status
Simulation time 8498372226 ps
CPU time 8.37 seconds
Started Apr 16 01:02:04 PM PDT 24
Finished Apr 16 01:02:13 PM PDT 24
Peak memory 204036 kb
Host smart-abc798a0-f78f-4546-b9eb-ce0946ade0d6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2072373705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.2072373705
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.324303208
Short name T1255
Test name
Test status
Simulation time 8391303919 ps
CPU time 8.02 seconds
Started Apr 16 01:01:59 PM PDT 24
Finished Apr 16 01:02:08 PM PDT 24
Peak memory 204024 kb
Host smart-288ceaf5-d508-4db9-a2b5-74ad186ce881
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=324303208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.324303208
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.4246755075
Short name T859
Test name
Test status
Simulation time 8462312701 ps
CPU time 7.8 seconds
Started Apr 16 01:02:00 PM PDT 24
Finished Apr 16 01:02:08 PM PDT 24
Peak memory 204028 kb
Host smart-0d61b26f-94b9-4bf6-98fb-98e164f9592a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42467
55075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.4246755075
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.4193824617
Short name T828
Test name
Test status
Simulation time 8375257918 ps
CPU time 7.78 seconds
Started Apr 16 01:01:55 PM PDT 24
Finished Apr 16 01:02:04 PM PDT 24
Peak memory 203988 kb
Host smart-f749d94a-d77e-4cd3-b8e6-f9a0bc93aa4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41938
24617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.4193824617
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_enable.387694018
Short name T833
Test name
Test status
Simulation time 8376606458 ps
CPU time 8.28 seconds
Started Apr 16 01:01:55 PM PDT 24
Finished Apr 16 01:02:04 PM PDT 24
Peak memory 203284 kb
Host smart-342ec004-6b55-407b-aef4-70395945a89e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38769
4018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.387694018
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.4183021842
Short name T1301
Test name
Test status
Simulation time 73381096 ps
CPU time 1.98 seconds
Started Apr 16 01:01:54 PM PDT 24
Finished Apr 16 01:01:56 PM PDT 24
Peak memory 204116 kb
Host smart-f002e54d-8aae-4d17-9790-29d5e01cbbfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41830
21842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.4183021842
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.2508176825
Short name T151
Test name
Test status
Simulation time 8434390321 ps
CPU time 8.17 seconds
Started Apr 16 01:01:59 PM PDT 24
Finished Apr 16 01:02:07 PM PDT 24
Peak memory 204052 kb
Host smart-bcb22436-4dce-4a7e-b5d7-2c423d2079b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25081
76825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.2508176825
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1270804427
Short name T1313
Test name
Test status
Simulation time 8371558118 ps
CPU time 7.86 seconds
Started Apr 16 01:02:02 PM PDT 24
Finished Apr 16 01:02:10 PM PDT 24
Peak memory 203948 kb
Host smart-ebfbae62-6e1a-43c4-a446-9f26d501b2bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12708
04427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1270804427
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3909956002
Short name T232
Test name
Test status
Simulation time 8436130284 ps
CPU time 8.6 seconds
Started Apr 16 01:02:00 PM PDT 24
Finished Apr 16 01:02:09 PM PDT 24
Peak memory 203980 kb
Host smart-9a6e725c-1795-43ee-9518-69c4bebe96a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39099
56002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3909956002
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.2965761736
Short name T834
Test name
Test status
Simulation time 8440915015 ps
CPU time 8.05 seconds
Started Apr 16 01:02:02 PM PDT 24
Finished Apr 16 01:02:11 PM PDT 24
Peak memory 204260 kb
Host smart-b550737a-1f05-42ec-a46e-88b2a05b431c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29657
61736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.2965761736
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.2755909188
Short name T448
Test name
Test status
Simulation time 8371717208 ps
CPU time 8.02 seconds
Started Apr 16 01:01:58 PM PDT 24
Finished Apr 16 01:02:07 PM PDT 24
Peak memory 204040 kb
Host smart-69cf5d63-28b8-48c9-b3bf-e13dee49458b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27559
09188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.2755909188
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.774600508
Short name T114
Test name
Test status
Simulation time 8434895997 ps
CPU time 7.66 seconds
Started Apr 16 01:02:01 PM PDT 24
Finished Apr 16 01:02:09 PM PDT 24
Peak memory 204080 kb
Host smart-5c1c7d71-4ee8-4673-97da-05244960a8d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77460
0508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.774600508
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.128956973
Short name T296
Test name
Test status
Simulation time 8403866911 ps
CPU time 9.42 seconds
Started Apr 16 01:02:00 PM PDT 24
Finished Apr 16 01:02:10 PM PDT 24
Peak memory 204016 kb
Host smart-d2366d68-893f-42c4-9df2-c84d82d478e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12895
6973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.128956973
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.964898847
Short name T492
Test name
Test status
Simulation time 8400702801 ps
CPU time 8.2 seconds
Started Apr 16 01:02:01 PM PDT 24
Finished Apr 16 01:02:10 PM PDT 24
Peak memory 203944 kb
Host smart-4824493c-b58c-4fd8-93e2-dde33d8f4ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96489
8847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.964898847
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.1399793540
Short name T1171
Test name
Test status
Simulation time 8405245499 ps
CPU time 8.57 seconds
Started Apr 16 01:02:01 PM PDT 24
Finished Apr 16 01:02:10 PM PDT 24
Peak memory 203904 kb
Host smart-0a15f2ba-2585-4d6b-8bbc-fb2176584573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13997
93540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.1399793540
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.3394464785
Short name T584
Test name
Test status
Simulation time 8364630758 ps
CPU time 8.23 seconds
Started Apr 16 01:02:00 PM PDT 24
Finished Apr 16 01:02:09 PM PDT 24
Peak memory 203996 kb
Host smart-7eedf3a5-28d9-46d5-888d-79499b22ef9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33944
64785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.3394464785
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2945309720
Short name T34
Test name
Test status
Simulation time 46297291 ps
CPU time 0.67 seconds
Started Apr 16 01:01:58 PM PDT 24
Finished Apr 16 01:01:59 PM PDT 24
Peak memory 203868 kb
Host smart-921dedd9-55f2-490d-bc85-f23cf0731277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29453
09720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2945309720
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.1905424007
Short name T1330
Test name
Test status
Simulation time 21492028056 ps
CPU time 40.05 seconds
Started Apr 16 01:01:59 PM PDT 24
Finished Apr 16 01:02:40 PM PDT 24
Peak memory 204224 kb
Host smart-5a964acc-ed63-40a2-a2e7-d992efd39b9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19054
24007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.1905424007
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.248245101
Short name T335
Test name
Test status
Simulation time 8376214185 ps
CPU time 7.55 seconds
Started Apr 16 01:02:03 PM PDT 24
Finished Apr 16 01:02:11 PM PDT 24
Peak memory 204032 kb
Host smart-026e02eb-0d86-4ec7-9b38-5444e8dc4162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24824
5101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.248245101
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.512114307
Short name T131
Test name
Test status
Simulation time 8470545027 ps
CPU time 9.99 seconds
Started Apr 16 01:02:03 PM PDT 24
Finished Apr 16 01:02:14 PM PDT 24
Peak memory 204028 kb
Host smart-5f503c60-b8da-4aee-a204-772b03419f06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51211
4307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.512114307
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.1297534529
Short name T603
Test name
Test status
Simulation time 8408954844 ps
CPU time 7.87 seconds
Started Apr 16 01:02:00 PM PDT 24
Finished Apr 16 01:02:09 PM PDT 24
Peak memory 203964 kb
Host smart-bee4ef92-7b6e-4ac3-b876-567336843f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12975
34529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.1297534529
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.2685159005
Short name T1150
Test name
Test status
Simulation time 8372288547 ps
CPU time 7.84 seconds
Started Apr 16 01:01:59 PM PDT 24
Finished Apr 16 01:02:07 PM PDT 24
Peak memory 204012 kb
Host smart-5242e732-57f1-43a1-adf5-8511a2f7e460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26851
59005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.2685159005
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.1345717816
Short name T960
Test name
Test status
Simulation time 8379656881 ps
CPU time 10.13 seconds
Started Apr 16 01:01:58 PM PDT 24
Finished Apr 16 01:02:09 PM PDT 24
Peak memory 203988 kb
Host smart-2e161374-8d98-4b5d-ad53-a08efc794e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13457
17816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.1345717816
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.1674412226
Short name T1263
Test name
Test status
Simulation time 8408013556 ps
CPU time 7.48 seconds
Started Apr 16 01:01:58 PM PDT 24
Finished Apr 16 01:02:06 PM PDT 24
Peak memory 203980 kb
Host smart-51a42345-ea8c-4a4f-ac7a-819c599c2837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16744
12226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1674412226
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.93651578
Short name T311
Test name
Test status
Simulation time 8379762454 ps
CPU time 7.74 seconds
Started Apr 16 01:02:02 PM PDT 24
Finished Apr 16 01:02:10 PM PDT 24
Peak memory 204028 kb
Host smart-3e5b83b7-11b6-4b28-a779-7493274b61a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93651
578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.93651578
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.1078756826
Short name T479
Test name
Test status
Simulation time 8421567153 ps
CPU time 8.06 seconds
Started Apr 16 01:01:59 PM PDT 24
Finished Apr 16 01:02:07 PM PDT 24
Peak memory 203980 kb
Host smart-309c01a3-e99d-4716-818f-ded3e323ae1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10787
56826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.1078756826
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.max_length_in_transaction.750833141
Short name T884
Test name
Test status
Simulation time 8482438863 ps
CPU time 7.91 seconds
Started Apr 16 01:02:10 PM PDT 24
Finished Apr 16 01:02:18 PM PDT 24
Peak memory 204024 kb
Host smart-b29d507e-aaee-4b9a-8903-177640c05327
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=750833141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.750833141
Directory /workspace/9.max_length_in_transaction/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.75096887
Short name T468
Test name
Test status
Simulation time 8400342742 ps
CPU time 8.02 seconds
Started Apr 16 01:02:08 PM PDT 24
Finished Apr 16 01:02:16 PM PDT 24
Peak memory 203980 kb
Host smart-eac31e71-aa0f-4094-b704-7f6a7c6acea3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=75096887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.75096887
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.476365888
Short name T686
Test name
Test status
Simulation time 8397290768 ps
CPU time 8.52 seconds
Started Apr 16 01:02:09 PM PDT 24
Finished Apr 16 01:02:18 PM PDT 24
Peak memory 203948 kb
Host smart-89fdf793-d1ac-4fc6-b6b6-7c5da4c2c085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47636
5888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.476365888
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.3017138696
Short name T1228
Test name
Test status
Simulation time 8460639364 ps
CPU time 7.85 seconds
Started Apr 16 01:02:05 PM PDT 24
Finished Apr 16 01:02:14 PM PDT 24
Peak memory 203992 kb
Host smart-5995dad2-2ef8-4cf5-92d0-e591d65e502f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30171
38696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.3017138696
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_enable.4126974044
Short name T469
Test name
Test status
Simulation time 8375655324 ps
CPU time 8.19 seconds
Started Apr 16 01:02:07 PM PDT 24
Finished Apr 16 01:02:16 PM PDT 24
Peak memory 203980 kb
Host smart-0be41742-513a-4409-96f1-cf3dcf69382a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41269
74044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.4126974044
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.3195732889
Short name T522
Test name
Test status
Simulation time 52294105 ps
CPU time 1.54 seconds
Started Apr 16 01:02:03 PM PDT 24
Finished Apr 16 01:02:06 PM PDT 24
Peak memory 204048 kb
Host smart-968f6969-6f51-4d09-a642-06c851befda6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31957
32889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.3195732889
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.548533563
Short name T39
Test name
Test status
Simulation time 8423581785 ps
CPU time 8.3 seconds
Started Apr 16 01:02:07 PM PDT 24
Finished Apr 16 01:02:16 PM PDT 24
Peak memory 203992 kb
Host smart-bfa601c7-968f-4fe2-bf3a-f7fe00e7bf70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54853
3563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.548533563
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.1068661034
Short name T677
Test name
Test status
Simulation time 8364615168 ps
CPU time 7.46 seconds
Started Apr 16 01:02:09 PM PDT 24
Finished Apr 16 01:02:17 PM PDT 24
Peak memory 203976 kb
Host smart-5d00952e-20c0-48ae-b43d-0d63531adad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10686
61034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.1068661034
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.3719686555
Short name T504
Test name
Test status
Simulation time 8386647240 ps
CPU time 7.99 seconds
Started Apr 16 01:02:03 PM PDT 24
Finished Apr 16 01:02:11 PM PDT 24
Peak memory 203944 kb
Host smart-85c70413-569f-4d6a-9386-2af9ff6302da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37196
86555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3719686555
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.1306594431
Short name T601
Test name
Test status
Simulation time 8430189343 ps
CPU time 7.94 seconds
Started Apr 16 01:02:04 PM PDT 24
Finished Apr 16 01:02:13 PM PDT 24
Peak memory 204028 kb
Host smart-fb98284d-fa44-4233-b2ce-c17f6c4480ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13065
94431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1306594431
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.1544784256
Short name T779
Test name
Test status
Simulation time 8368127281 ps
CPU time 7.97 seconds
Started Apr 16 01:02:05 PM PDT 24
Finished Apr 16 01:02:14 PM PDT 24
Peak memory 204024 kb
Host smart-72adf992-9dca-44d6-b2db-ced2ec78a739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15447
84256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.1544784256
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.2183797593
Short name T109
Test name
Test status
Simulation time 8445565775 ps
CPU time 9.88 seconds
Started Apr 16 01:02:03 PM PDT 24
Finished Apr 16 01:02:14 PM PDT 24
Peak memory 204016 kb
Host smart-373e8b8b-6bdd-44e5-a270-60086b594a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21837
97593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.2183797593
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.1965387183
Short name T954
Test name
Test status
Simulation time 8377677502 ps
CPU time 8.29 seconds
Started Apr 16 01:02:05 PM PDT 24
Finished Apr 16 01:02:14 PM PDT 24
Peak memory 203976 kb
Host smart-b3bc6ea5-ab24-40c2-869a-b7209a3aedad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19653
87183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.1965387183
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.2134575820
Short name T1281
Test name
Test status
Simulation time 8415316970 ps
CPU time 10.38 seconds
Started Apr 16 01:02:04 PM PDT 24
Finished Apr 16 01:02:16 PM PDT 24
Peak memory 204036 kb
Host smart-f376941e-4777-490e-b2cf-d07353408739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21345
75820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.2134575820
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.4119447459
Short name T598
Test name
Test status
Simulation time 8394542972 ps
CPU time 8.12 seconds
Started Apr 16 01:02:03 PM PDT 24
Finished Apr 16 01:02:12 PM PDT 24
Peak memory 204024 kb
Host smart-44e75069-cddd-4577-87bd-669a9ce0a78b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41194
47459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.4119447459
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.3095608583
Short name T609
Test name
Test status
Simulation time 8393258200 ps
CPU time 8.12 seconds
Started Apr 16 01:02:05 PM PDT 24
Finished Apr 16 01:02:14 PM PDT 24
Peak memory 203960 kb
Host smart-551ba275-a888-4bb3-b55e-0363e5abfc3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30956
08583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.3095608583
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.2344973046
Short name T334
Test name
Test status
Simulation time 115172136 ps
CPU time 0.73 seconds
Started Apr 16 01:02:06 PM PDT 24
Finished Apr 16 01:02:08 PM PDT 24
Peak memory 203852 kb
Host smart-91e5ece6-65d6-4401-bbe3-df9834931c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23449
73046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.2344973046
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.1118553806
Short name T950
Test name
Test status
Simulation time 18428530047 ps
CPU time 37.07 seconds
Started Apr 16 01:02:07 PM PDT 24
Finished Apr 16 01:02:45 PM PDT 24
Peak memory 204252 kb
Host smart-b9f37f1b-6419-4bd7-ac93-2c51450f854d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11185
53806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.1118553806
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.238972210
Short name T749
Test name
Test status
Simulation time 8403727096 ps
CPU time 7.82 seconds
Started Apr 16 01:02:01 PM PDT 24
Finished Apr 16 01:02:10 PM PDT 24
Peak memory 204028 kb
Host smart-34c8c139-dfce-4408-8e5c-d52e9da91cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23897
2210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.238972210
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.2815324999
Short name T512
Test name
Test status
Simulation time 8484402077 ps
CPU time 9.97 seconds
Started Apr 16 01:02:04 PM PDT 24
Finished Apr 16 01:02:15 PM PDT 24
Peak memory 204028 kb
Host smart-adfbb14a-87bb-4551-8788-f76b4c2725da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28153
24999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.2815324999
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.3351302810
Short name T635
Test name
Test status
Simulation time 8386034945 ps
CPU time 10.04 seconds
Started Apr 16 01:02:02 PM PDT 24
Finished Apr 16 01:02:13 PM PDT 24
Peak memory 204028 kb
Host smart-5490fba4-a5b8-461f-a61e-27df61391f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33513
02810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.3351302810
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.2012337412
Short name T916
Test name
Test status
Simulation time 8423422463 ps
CPU time 7.96 seconds
Started Apr 16 01:02:05 PM PDT 24
Finished Apr 16 01:02:14 PM PDT 24
Peak memory 203992 kb
Host smart-ff8b560c-7ea0-494f-8c6d-b892cf2f02cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20123
37412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.2012337412
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2375083220
Short name T209
Test name
Test status
Simulation time 8374121344 ps
CPU time 8.02 seconds
Started Apr 16 01:02:05 PM PDT 24
Finished Apr 16 01:02:14 PM PDT 24
Peak memory 204052 kb
Host smart-57f419ae-186d-499f-a230-24110070fb23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23750
83220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2375083220
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.530754985
Short name T1107
Test name
Test status
Simulation time 8417288341 ps
CPU time 8.64 seconds
Started Apr 16 01:02:05 PM PDT 24
Finished Apr 16 01:02:15 PM PDT 24
Peak memory 204016 kb
Host smart-be5e3f88-e3de-4a03-831f-16075a70f9e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53075
4985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.530754985
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.3625861553
Short name T444
Test name
Test status
Simulation time 8402666262 ps
CPU time 8.31 seconds
Started Apr 16 01:02:04 PM PDT 24
Finished Apr 16 01:02:13 PM PDT 24
Peak memory 204256 kb
Host smart-1b9d3828-150d-4d3e-b3c4-7951dfaa7967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36258
61553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.3625861553
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.3176384033
Short name T480
Test name
Test status
Simulation time 8404336585 ps
CPU time 10.41 seconds
Started Apr 16 01:02:11 PM PDT 24
Finished Apr 16 01:02:22 PM PDT 24
Peak memory 204016 kb
Host smart-11ef433f-4df4-40ee-80e2-70891c057cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31763
84033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3176384033
Directory /workspace/9.usbdev_stall_trans/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%