Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	28694	1		T1	2		T2	4		T3	4
all_values[1]	28694	1		T1	2		T2	4		T3	4
all_values[2]	28694	1		T1	2		T2	4		T3	4
all_values[3]	28694	1		T1	2		T2	4		T3	4
all_values[4]	28694	1		T1	2		T2	4		T3	4
all_values[5]	28694	1		T1	2		T2	4		T3	4
all_values[6]	28694	1		T1	2		T2	4		T3	4
all_values[7]	28694	1		T1	2		T2	4		T3	4
all_values[8]	28694	1		T1	2		T2	4		T3	4
all_values[9]	28694	1		T1	2		T2	4		T3	4
all_values[10]	28694	1		T1	2		T2	4		T3	4
all_values[11]	28694	1		T1	2		T2	4		T3	4
all_values[12]	28694	1		T1	2		T2	4		T3	4
all_values[13]	28694	1		T1	2		T2	4		T3	4
all_values[14]	28694	1		T1	2		T2	4		T3	4
all_values[15]	28694	1		T1	2		T2	4		T3	4
all_values[16]	28694	1		T1	2		T2	4		T3	4
all_values[17]	28694	1		T1	2		T2	4		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	512777	1		T1	36		T2	68		T3	72
auto[1]	3715	1		T2	4		T15	3		T17	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	511916	1		T1	36		T2	72		T3	72
auto[1]	4576	1		T64	73		T65	130		T67	67

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	27714	1		T1	2		T3	4		T8	2
all_values[0]	auto[0]	auto[1]	137	1		T64	4		T65	4		T257	4
all_values[0]	auto[1]	auto[0]	721	1		T2	4		T15	3		T20	4
all_values[0]	auto[1]	auto[1]	122	1		T65	3		T69	4		T257	4
all_values[1]	auto[0]	auto[0]	28116	1		T1	2		T2	4		T3	4
all_values[1]	auto[0]	auto[1]	116	1		T65	2		T67	5		T66	1
all_values[1]	auto[1]	auto[0]	337	1		T17	3		T39	3		T40	3
all_values[1]	auto[1]	auto[1]	125	1		T65	6		T66	4		T68	4
all_values[2]	auto[0]	auto[0]	28406	1		T1	2		T2	4		T3	4
all_values[2]	auto[0]	auto[1]	136	1		T64	4		T65	3		T68	1
all_values[2]	auto[1]	auto[0]	25	1		T67	5		T66	3		T257	2
all_values[2]	auto[1]	auto[1]	127	1		T64	1		T65	5		T68	4
all_values[3]	auto[0]	auto[0]	28398	1		T1	2		T2	4		T3	4
all_values[3]	auto[0]	auto[1]	150	1		T65	5		T66	4		T68	1
all_values[3]	auto[1]	auto[0]	21	1		T66	1		T257	1		T261	4
all_values[3]	auto[1]	auto[1]	125	1		T64	4		T65	2		T67	4
all_values[4]	auto[0]	auto[0]	28411	1		T1	2		T2	4		T3	4
all_values[4]	auto[0]	auto[1]	127	1		T64	1		T65	2		T67	3
all_values[4]	auto[1]	auto[0]	30	1		T64	1		T67	1		T66	1
all_values[4]	auto[1]	auto[1]	126	1		T64	3		T65	6		T67	1
all_values[5]	auto[0]	auto[0]	28416	1		T1	2		T2	4		T3	4
all_values[5]	auto[0]	auto[1]	144	1		T64	3		T65	1		T67	4
all_values[5]	auto[1]	auto[0]	39	1		T64	1		T65	1		T262	4
all_values[5]	auto[1]	auto[1]	95	1		T65	6		T67	1		T66	3
all_values[6]	auto[0]	auto[0]	28396	1		T1	2		T2	4		T3	4
all_values[6]	auto[0]	auto[1]	153	1		T64	4		T65	6		T67	4
all_values[6]	auto[1]	auto[0]	22	1		T68	1		T69	1		T257	1
all_values[6]	auto[1]	auto[1]	123	1		T64	1		T65	2		T67	1
all_values[7]	auto[0]	auto[0]	28411	1		T1	2		T2	4		T3	4
all_values[7]	auto[0]	auto[1]	133	1		T64	2		T67	1		T66	1
all_values[7]	auto[1]	auto[0]	19	1		T262	1		T258	1		T263	2
all_values[7]	auto[1]	auto[1]	131	1		T64	3		T65	8		T67	4
all_values[8]	auto[0]	auto[0]	28400	1		T1	2		T2	4		T3	4
all_values[8]	auto[0]	auto[1]	145	1		T65	2		T67	3		T66	5
all_values[8]	auto[1]	auto[0]	27	1		T65	1		T67	1		T257	2
all_values[8]	auto[1]	auto[1]	122	1		T64	5		T65	4		T69	5
all_values[9]	auto[0]	auto[0]	28411	1		T1	2		T2	4		T3	4
all_values[9]	auto[0]	auto[1]	135	1		T65	4		T67	1		T66	4
all_values[9]	auto[1]	auto[0]	18	1		T68	2		T257	2		T260	1
all_values[9]	auto[1]	auto[1]	130	1		T64	5		T65	4		T67	3
all_values[10]	auto[0]	auto[0]	28416	1		T1	2		T2	4		T3	4
all_values[10]	auto[0]	auto[1]	124	1		T64	4		T65	4		T67	5
all_values[10]	auto[1]	auto[0]	33	1		T65	4		T66	2		T69	1
all_values[10]	auto[1]	auto[1]	121	1		T64	1		T68	1		T69	1
all_values[11]	auto[0]	auto[0]	28405	1		T1	2		T2	4		T3	4
all_values[11]	auto[0]	auto[1]	141	1		T65	2		T67	1		T66	4
all_values[11]	auto[1]	auto[0]	41	1		T64	1		T68	2		T69	1
all_values[11]	auto[1]	auto[1]	107	1		T64	3		T65	6		T67	4
all_values[12]	auto[0]	auto[0]	28419	1		T1	2		T2	4		T3	4
all_values[12]	auto[0]	auto[1]	145	1		T65	5		T67	3		T69	3
all_values[12]	auto[1]	auto[0]	36	1		T64	1		T66	1		T68	5
all_values[12]	auto[1]	auto[1]	94	1		T64	3		T65	3		T67	2
all_values[13]	auto[0]	auto[0]	28416	1		T1	2		T2	4		T3	4
all_values[13]	auto[0]	auto[1]	125	1		T67	3		T66	4		T68	2
all_values[13]	auto[1]	auto[0]	22	1		T262	1		T258	3		T259	2
all_values[13]	auto[1]	auto[1]	131	1		T64	5		T65	7		T67	2
all_values[14]	auto[0]	auto[0]	28422	1		T1	2		T2	4		T3	4
all_values[14]	auto[0]	auto[1]	121	1		T64	3		T65	2		T67	4
all_values[14]	auto[1]	auto[0]	36	1		T65	1		T68	1		T257	1
all_values[14]	auto[1]	auto[1]	115	1		T64	1		T65	5		T66	5
all_values[15]	auto[0]	auto[0]	28426	1		T1	2		T2	4		T3	4
all_values[15]	auto[0]	auto[1]	105	1		T64	4		T65	5		T68	1
all_values[15]	auto[1]	auto[0]	43	1		T67	1		T66	1		T68	1
all_values[15]	auto[1]	auto[1]	120	1		T64	1		T65	2		T66	4
all_values[16]	auto[0]	auto[0]	28416	1		T1	2		T2	4		T3	4
all_values[16]	auto[0]	auto[1]	118	1		T64	1		T65	2		T67	3
all_values[16]	auto[1]	auto[0]	14	1		T65	1		T264	2		T263	1
all_values[16]	auto[1]	auto[1]	146	1		T64	3		T65	4		T66	3
all_values[17]	auto[0]	auto[0]	28411	1		T1	2		T2	4		T3	4
all_values[17]	auto[0]	auto[1]	112	1		T65	3		T67	2		T68	3
all_values[17]	auto[1]	auto[0]	22	1		T64	1		T68	1		T257	2
all_values[17]	auto[1]	auto[1]	149	1		T64	4		T65	5		T67	3