Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	28694	1		T1	2		T2	4		T3	4
all_pins[1]	28694	1		T1	2		T2	4		T3	4
all_pins[2]	28694	1		T1	2		T2	4		T3	4
all_pins[3]	28694	1		T1	2		T2	4		T3	4
all_pins[4]	28694	1		T1	2		T2	4		T3	4
all_pins[5]	28694	1		T1	2		T2	4		T3	4
all_pins[6]	28694	1		T1	2		T2	4		T3	4
all_pins[7]	28694	1		T1	2		T2	4		T3	4
all_pins[8]	28694	1		T1	2		T2	4		T3	4
all_pins[9]	28694	1		T1	2		T2	4		T3	4
all_pins[10]	28694	1		T1	2		T2	4		T3	4
all_pins[11]	28694	1		T1	2		T2	4		T3	4
all_pins[12]	28694	1		T1	2		T2	4		T3	4
all_pins[13]	28694	1		T1	2		T2	4		T3	4
all_pins[14]	28694	1		T1	2		T2	4		T3	4
all_pins[15]	28694	1		T1	2		T2	4		T3	4
all_pins[16]	28694	1		T1	2		T2	4		T3	4
all_pins[17]	28694	1		T1	2		T2	4		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	515270	1		T1	36		T2	71		T3	72
values[0x1]	1222	1		T2	1		T17	1		T20	1
transitions[0x0=>0x1]	979	1		T2	1		T17	1		T20	1
transitions[0x1=>0x0]	990	1		T2	1		T17	1		T20	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	28533	1		T1	2		T2	3		T3	4
all_pins[0]	values[0x1]	161	1		T2	1		T20	1		T52	1
all_pins[0]	transitions[0x0=>0x1]	151	1		T2	1		T20	1		T52	1
all_pins[0]	transitions[0x1=>0x0]	143	1		T17	1		T39	1		T40	1
all_pins[1]	values[0x0]	28541	1		T1	2		T2	4		T3	4
all_pins[1]	values[0x1]	153	1		T17	1		T39	1		T40	1
all_pins[1]	transitions[0x0=>0x1]	136	1		T17	1		T39	1		T40	1
all_pins[1]	transitions[0x1=>0x0]	49	1		T64	1		T65	1		T67	1
all_pins[2]	values[0x0]	28628	1		T1	2		T2	4		T3	4
all_pins[2]	values[0x1]	66	1		T64	1		T65	2		T67	1
all_pins[2]	transitions[0x0=>0x1]	53	1		T65	2		T67	1		T66	2
all_pins[2]	transitions[0x1=>0x0]	48	1		T64	2		T65	2		T67	1
all_pins[3]	values[0x0]	28633	1		T1	2		T2	4		T3	4
all_pins[3]	values[0x1]	61	1		T64	3		T65	2		T67	1
all_pins[3]	transitions[0x0=>0x1]	47	1		T64	1		T65	1		T68	1
all_pins[3]	transitions[0x1=>0x0]	45	1		T65	1		T66	2		T68	2
all_pins[4]	values[0x0]	28635	1		T1	2		T2	4		T3	4
all_pins[4]	values[0x1]	59	1		T64	2		T65	2		T67	1
all_pins[4]	transitions[0x0=>0x1]	45	1		T64	2		T65	1		T67	1
all_pins[4]	transitions[0x1=>0x0]	32	1		T65	3		T68	1		T257	1
all_pins[5]	values[0x0]	28648	1		T1	2		T2	4		T3	4
all_pins[5]	values[0x1]	46	1		T65	4		T66	2		T68	1
all_pins[5]	transitions[0x0=>0x1]	29	1		T65	4		T66	2		T68	1
all_pins[5]	transitions[0x1=>0x0]	54	1		T65	1		T66	1		T69	3
all_pins[6]	values[0x0]	28623	1		T1	2		T2	4		T3	4
all_pins[6]	values[0x1]	71	1		T65	1		T66	1		T69	3
all_pins[6]	transitions[0x0=>0x1]	57	1		T65	1		T69	2		T262	1
all_pins[6]	transitions[0x1=>0x0]	40	1		T65	3		T67	1		T68	1
all_pins[7]	values[0x0]	28640	1		T1	2		T2	4		T3	4
all_pins[7]	values[0x1]	54	1		T65	3		T67	1		T66	1
all_pins[7]	transitions[0x0=>0x1]	41	1		T65	3		T67	1		T66	1
all_pins[7]	transitions[0x1=>0x0]	37	1		T64	1		T69	2		T259	1
all_pins[8]	values[0x0]	28644	1		T1	2		T2	4		T3	4
all_pins[8]	values[0x1]	50	1		T64	1		T69	3		T257	1
all_pins[8]	transitions[0x0=>0x1]	39	1		T69	2		T257	1		T258	1
all_pins[8]	transitions[0x1=>0x0]	48	1		T64	1		T65	1		T67	2
all_pins[9]	values[0x0]	28635	1		T1	2		T2	4		T3	4
all_pins[9]	values[0x1]	59	1		T64	2		T65	1		T67	2
all_pins[9]	transitions[0x0=>0x1]	51	1		T64	1		T65	1		T67	2
all_pins[9]	transitions[0x1=>0x0]	37	1		T68	1		T69	1		T257	2
all_pins[10]	values[0x0]	28649	1		T1	2		T2	4		T3	4
all_pins[10]	values[0x1]	45	1		T64	1		T68	1		T69	1
all_pins[10]	transitions[0x0=>0x1]	33	1		T64	1		T68	1		T257	2
all_pins[10]	transitions[0x1=>0x0]	43	1		T64	2		T65	4		T67	2
all_pins[11]	values[0x0]	28639	1		T1	2		T2	4		T3	4
all_pins[11]	values[0x1]	55	1		T64	2		T65	4		T67	2
all_pins[11]	transitions[0x0=>0x1]	47	1		T65	2		T67	2		T66	1
all_pins[11]	transitions[0x1=>0x0]	32	1		T65	1		T257	3		T258	1
all_pins[12]	values[0x0]	28654	1		T1	2		T2	4		T3	4
all_pins[12]	values[0x1]	40	1		T64	2		T65	3		T257	3
all_pins[12]	transitions[0x0=>0x1]	24	1		T65	2		T257	2		T258	1
all_pins[12]	transitions[0x1=>0x0]	48	1		T64	1		T65	3		T66	1
all_pins[13]	values[0x0]	28630	1		T1	2		T2	4		T3	4
all_pins[13]	values[0x1]	64	1		T64	3		T65	4		T66	1
all_pins[13]	transitions[0x0=>0x1]	50	1		T64	2		T65	4		T68	2
all_pins[13]	transitions[0x1=>0x0]	40	1		T65	2		T66	3		T257	2
all_pins[14]	values[0x0]	28640	1		T1	2		T2	4		T3	4
all_pins[14]	values[0x1]	54	1		T64	1		T65	2		T66	4
all_pins[14]	transitions[0x0=>0x1]	41	1		T65	2		T66	3		T257	2
all_pins[14]	transitions[0x1=>0x0]	44	1		T65	1		T68	2		T69	4
all_pins[15]	values[0x0]	28637	1		T1	2		T2	4		T3	4
all_pins[15]	values[0x1]	57	1		T64	1		T65	1		T66	1
all_pins[15]	transitions[0x0=>0x1]	46	1		T64	1		T65	1		T66	1
all_pins[15]	transitions[0x1=>0x0]	63	1		T64	2		T65	2		T257	3
all_pins[16]	values[0x0]	28620	1		T1	2		T2	4		T3	4
all_pins[16]	values[0x1]	74	1		T64	2		T65	2		T69	2
all_pins[16]	transitions[0x0=>0x1]	62	1		T64	1		T65	2		T69	1
all_pins[16]	transitions[0x1=>0x0]	41	1		T64	1		T65	1		T67	1
all_pins[17]	values[0x0]	28641	1		T1	2		T2	4		T3	4
all_pins[17]	values[0x1]	53	1		T64	2		T65	1		T67	1
all_pins[17]	transitions[0x0=>0x1]	27	1		T64	2		T67	1		T66	1
all_pins[17]	transitions[0x1=>0x0]	146	1		T2	1		T20	1		T52	1