Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.83 96.54 89.37 97.32 50.00 94.46 97.56 96.58


Total test records in report: 1479
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T1329 /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.620196641 Apr 18 01:15:57 PM PDT 24 Apr 18 01:16:06 PM PDT 24 8369813387 ps
T1330 /workspace/coverage/default/4.usbdev_stall_priority_over_nak.684191331 Apr 18 01:14:05 PM PDT 24 Apr 18 01:14:15 PM PDT 24 8371046128 ps
T1331 /workspace/coverage/default/31.usbdev_in_trans.614574818 Apr 18 01:16:27 PM PDT 24 Apr 18 01:16:37 PM PDT 24 8438393381 ps
T1332 /workspace/coverage/default/0.random_length_in_trans.1148739571 Apr 18 01:13:26 PM PDT 24 Apr 18 01:13:34 PM PDT 24 8415204135 ps
T1333 /workspace/coverage/default/11.usbdev_pending_in_trans.923080270 Apr 18 01:14:49 PM PDT 24 Apr 18 01:14:58 PM PDT 24 8387236225 ps
T1334 /workspace/coverage/default/24.max_length_in_transaction.714190516 Apr 18 01:15:56 PM PDT 24 Apr 18 01:16:05 PM PDT 24 8462471304 ps
T1335 /workspace/coverage/default/43.usbdev_nak_trans.157641687 Apr 18 01:17:25 PM PDT 24 Apr 18 01:17:35 PM PDT 24 8408809209 ps
T1336 /workspace/coverage/default/42.usbdev_pending_in_trans.442306907 Apr 18 01:17:17 PM PDT 24 Apr 18 01:17:27 PM PDT 24 8391952628 ps
T1337 /workspace/coverage/default/9.usbdev_setup_stage.245353241 Apr 18 01:14:39 PM PDT 24 Apr 18 01:14:48 PM PDT 24 8373716831 ps
T1338 /workspace/coverage/default/6.usbdev_in_stall.3694205209 Apr 18 01:14:24 PM PDT 24 Apr 18 01:14:33 PM PDT 24 8395651135 ps
T1339 /workspace/coverage/default/39.usbdev_random_length_out_trans.529461635 Apr 18 01:17:05 PM PDT 24 Apr 18 01:17:15 PM PDT 24 8395796147 ps
T1340 /workspace/coverage/default/39.usbdev_max_length_out_transaction.3043378449 Apr 18 01:16:59 PM PDT 24 Apr 18 01:17:10 PM PDT 24 8414974554 ps
T1341 /workspace/coverage/default/13.usbdev_setup_trans_ignored.1460386448 Apr 18 01:15:03 PM PDT 24 Apr 18 01:15:12 PM PDT 24 8372813350 ps
T1342 /workspace/coverage/default/18.usbdev_setup_stage.891300008 Apr 18 01:15:47 PM PDT 24 Apr 18 01:15:55 PM PDT 24 8375355944 ps
T1343 /workspace/coverage/default/42.usbdev_setup_trans_ignored.2894211697 Apr 18 01:17:17 PM PDT 24 Apr 18 01:17:26 PM PDT 24 8365456626 ps
T1344 /workspace/coverage/default/43.usbdev_pkt_sent.958317684 Apr 18 01:17:27 PM PDT 24 Apr 18 01:17:37 PM PDT 24 8398760212 ps
T1345 /workspace/coverage/default/31.max_length_in_transaction.3059379654 Apr 18 01:16:29 PM PDT 24 Apr 18 01:16:39 PM PDT 24 8460455570 ps
T1346 /workspace/coverage/default/38.usbdev_pkt_received.1145452348 Apr 18 01:16:59 PM PDT 24 Apr 18 01:17:10 PM PDT 24 8396156745 ps
T1347 /workspace/coverage/default/11.usbdev_pkt_received.3932482271 Apr 18 01:14:50 PM PDT 24 Apr 18 01:15:00 PM PDT 24 8379172236 ps
T1348 /workspace/coverage/default/49.max_length_in_transaction.1187954832 Apr 18 01:17:48 PM PDT 24 Apr 18 01:17:58 PM PDT 24 8502785138 ps
T1349 /workspace/coverage/default/35.usbdev_out_stall.3038066735 Apr 18 01:16:50 PM PDT 24 Apr 18 01:17:00 PM PDT 24 8393951710 ps
T1350 /workspace/coverage/default/22.usbdev_pkt_received.1209169432 Apr 18 01:15:52 PM PDT 24 Apr 18 01:16:00 PM PDT 24 8418890552 ps
T1351 /workspace/coverage/default/47.usbdev_out_trans_nak.2424042086 Apr 18 01:17:43 PM PDT 24 Apr 18 01:17:53 PM PDT 24 8386821738 ps
T1352 /workspace/coverage/default/35.usbdev_pkt_received.702229935 Apr 18 01:16:47 PM PDT 24 Apr 18 01:16:55 PM PDT 24 8381150897 ps
T1353 /workspace/coverage/default/20.usbdev_stall_priority_over_nak.3617457618 Apr 18 01:15:39 PM PDT 24 Apr 18 01:15:48 PM PDT 24 8376011324 ps
T1354 /workspace/coverage/default/47.usbdev_setup_stage.3585014893 Apr 18 01:17:48 PM PDT 24 Apr 18 01:17:58 PM PDT 24 8382337209 ps
T1355 /workspace/coverage/default/30.usbdev_enable.4285577992 Apr 18 01:16:21 PM PDT 24 Apr 18 01:16:31 PM PDT 24 8379925051 ps
T1356 /workspace/coverage/default/42.usbdev_min_length_out_transaction.4117806412 Apr 18 01:17:18 PM PDT 24 Apr 18 01:17:26 PM PDT 24 8371800775 ps
T1357 /workspace/coverage/default/43.usbdev_out_trans_nak.3953132115 Apr 18 01:17:21 PM PDT 24 Apr 18 01:17:29 PM PDT 24 8415995988 ps
T1358 /workspace/coverage/default/0.usbdev_fifo_rst.1581180889 Apr 18 01:13:20 PM PDT 24 Apr 18 01:13:22 PM PDT 24 159285464 ps
T1359 /workspace/coverage/default/14.usbdev_max_length_out_transaction.1451242252 Apr 18 01:15:04 PM PDT 24 Apr 18 01:15:13 PM PDT 24 8413461811 ps
T1360 /workspace/coverage/default/25.usbdev_nak_trans.3760555926 Apr 18 01:16:00 PM PDT 24 Apr 18 01:16:13 PM PDT 24 8428421162 ps
T1361 /workspace/coverage/default/35.usbdev_stall_trans.2098352307 Apr 18 01:16:52 PM PDT 24 Apr 18 01:17:03 PM PDT 24 8415381990 ps
T1362 /workspace/coverage/default/31.usbdev_stall_trans.3108034915 Apr 18 01:16:30 PM PDT 24 Apr 18 01:16:40 PM PDT 24 8394525595 ps
T1363 /workspace/coverage/default/32.usbdev_in_trans.2651143504 Apr 18 01:16:42 PM PDT 24 Apr 18 01:16:52 PM PDT 24 8420153485 ps
T1364 /workspace/coverage/default/45.usbdev_pkt_received.2463479897 Apr 18 01:17:29 PM PDT 24 Apr 18 01:17:38 PM PDT 24 8414655829 ps
T1365 /workspace/coverage/default/34.usbdev_stall_priority_over_nak.2169033579 Apr 18 01:16:49 PM PDT 24 Apr 18 01:16:57 PM PDT 24 8411242703 ps
T1366 /workspace/coverage/default/22.usbdev_stall_trans.3501861776 Apr 18 01:15:53 PM PDT 24 Apr 18 01:16:01 PM PDT 24 8391802565 ps
T1367 /workspace/coverage/default/41.usbdev_out_stall.493636286 Apr 18 01:17:12 PM PDT 24 Apr 18 01:17:23 PM PDT 24 8403495991 ps
T1368 /workspace/coverage/default/16.usbdev_fifo_rst.3560758969 Apr 18 01:15:20 PM PDT 24 Apr 18 01:15:22 PM PDT 24 85289392 ps
T1369 /workspace/coverage/default/13.usbdev_in_trans.3215140401 Apr 18 01:14:55 PM PDT 24 Apr 18 01:15:05 PM PDT 24 8447716346 ps
T1370 /workspace/coverage/default/46.usbdev_pkt_received.771046838 Apr 18 01:17:39 PM PDT 24 Apr 18 01:17:47 PM PDT 24 8456801909 ps
T1371 /workspace/coverage/default/0.usbdev_max_length_out_transaction.1254235869 Apr 18 01:13:21 PM PDT 24 Apr 18 01:13:30 PM PDT 24 8429520128 ps
T1372 /workspace/coverage/default/19.usbdev_min_length_out_transaction.1762148601 Apr 18 01:15:32 PM PDT 24 Apr 18 01:15:40 PM PDT 24 8374090443 ps
T1373 /workspace/coverage/default/23.usbdev_fifo_rst.1015285707 Apr 18 01:15:56 PM PDT 24 Apr 18 01:16:00 PM PDT 24 140083876 ps
T1374 /workspace/coverage/default/41.max_length_in_transaction.272617907 Apr 18 01:17:17 PM PDT 24 Apr 18 01:17:28 PM PDT 24 8468176327 ps
T1375 /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1557454127 Apr 18 01:17:28 PM PDT 24 Apr 18 01:17:38 PM PDT 24 8382302555 ps
T1376 /workspace/coverage/default/10.usbdev_in_trans.3983001903 Apr 18 01:14:45 PM PDT 24 Apr 18 01:14:54 PM PDT 24 8453078133 ps
T1377 /workspace/coverage/default/37.usbdev_stall_trans.3201810215 Apr 18 01:16:54 PM PDT 24 Apr 18 01:17:05 PM PDT 24 8434148489 ps
T1378 /workspace/coverage/default/35.usbdev_min_length_out_transaction.2064869338 Apr 18 01:16:49 PM PDT 24 Apr 18 01:16:57 PM PDT 24 8373744167 ps
T1379 /workspace/coverage/default/49.usbdev_stall_trans.824319287 Apr 18 01:17:52 PM PDT 24 Apr 18 01:18:01 PM PDT 24 8431280194 ps
T1380 /workspace/coverage/default/23.usbdev_pending_in_trans.3527018167 Apr 18 01:15:57 PM PDT 24 Apr 18 01:16:06 PM PDT 24 8398157239 ps
T1381 /workspace/coverage/default/40.min_length_in_transaction.2154585765 Apr 18 01:17:12 PM PDT 24 Apr 18 01:17:23 PM PDT 24 8375929384 ps
T1382 /workspace/coverage/default/9.usbdev_fifo_rst.2646000197 Apr 18 01:14:34 PM PDT 24 Apr 18 01:14:36 PM PDT 24 41134797 ps
T231 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2294446272 Apr 18 01:38:03 PM PDT 24 Apr 18 01:38:08 PM PDT 24 156215663 ps
T55 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.61577664 Apr 18 01:37:59 PM PDT 24 Apr 18 01:38:02 PM PDT 24 220780416 ps
T56 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1802550011 Apr 18 01:38:44 PM PDT 24 Apr 18 01:38:47 PM PDT 24 186029231 ps
T4 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.4117602499 Apr 18 01:37:59 PM PDT 24 Apr 18 01:38:00 PM PDT 24 79565523 ps
T57 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.688402663 Apr 18 01:38:06 PM PDT 24 Apr 18 01:38:11 PM PDT 24 430491088 ps
T196 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1058194087 Apr 18 01:38:03 PM PDT 24 Apr 18 01:38:08 PM PDT 24 123055117 ps
T64 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1078409324 Apr 18 01:38:03 PM PDT 24 Apr 18 01:38:07 PM PDT 24 45968287 ps
T65 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2319287513 Apr 18 01:38:07 PM PDT 24 Apr 18 01:38:10 PM PDT 24 35581329 ps
T197 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.869560341 Apr 18 01:38:06 PM PDT 24 Apr 18 01:38:10 PM PDT 24 73172339 ps
T67 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2248769684 Apr 18 01:38:06 PM PDT 24 Apr 18 01:38:09 PM PDT 24 28389125 ps
T198 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.972906358 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:08 PM PDT 24 380402515 ps
T199 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3553105139 Apr 18 01:38:03 PM PDT 24 Apr 18 01:38:10 PM PDT 24 664650375 ps
T200 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1150830125 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:08 PM PDT 24 282974081 ps
T66 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3357514387 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:06 PM PDT 24 30513485 ps
T232 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3110584414 Apr 18 01:37:59 PM PDT 24 Apr 18 01:38:01 PM PDT 24 106365324 ps
T201 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.367386532 Apr 18 01:37:55 PM PDT 24 Apr 18 01:37:56 PM PDT 24 91002047 ps
T68 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3152159266 Apr 18 01:38:12 PM PDT 24 Apr 18 01:38:13 PM PDT 24 33316598 ps
T1383 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.4157892147 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:04 PM PDT 24 271601933 ps
T204 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3720758263 Apr 18 01:38:10 PM PDT 24 Apr 18 01:38:12 PM PDT 24 63411459 ps
T69 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2600430113 Apr 18 01:38:04 PM PDT 24 Apr 18 01:38:08 PM PDT 24 35776959 ps
T243 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3151857601 Apr 18 01:38:06 PM PDT 24 Apr 18 01:38:10 PM PDT 24 229002863 ps
T205 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.410531438 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:05 PM PDT 24 90049241 ps
T202 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1480606576 Apr 18 01:37:58 PM PDT 24 Apr 18 01:38:00 PM PDT 24 221260714 ps
T257 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.4259103632 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:02 PM PDT 24 41627469 ps
T206 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1638915421 Apr 18 01:38:07 PM PDT 24 Apr 18 01:38:11 PM PDT 24 230594967 ps
T1384 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3062822829 Apr 18 01:37:59 PM PDT 24 Apr 18 01:38:02 PM PDT 24 283433455 ps
T226 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3981065074 Apr 18 01:38:07 PM PDT 24 Apr 18 01:38:12 PM PDT 24 612429478 ps
T244 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3859164142 Apr 18 01:38:05 PM PDT 24 Apr 18 01:38:09 PM PDT 24 61560641 ps
T1385 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3677633861 Apr 18 01:38:05 PM PDT 24 Apr 18 01:38:12 PM PDT 24 191601368 ps
T262 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1671958473 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:04 PM PDT 24 37655584 ps
T245 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1459750263 Apr 18 01:38:03 PM PDT 24 Apr 18 01:38:07 PM PDT 24 43897711 ps
T258 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3682436714 Apr 18 01:37:58 PM PDT 24 Apr 18 01:38:00 PM PDT 24 67787710 ps
T259 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3046921543 Apr 18 01:38:05 PM PDT 24 Apr 18 01:38:09 PM PDT 24 35650256 ps
T246 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1155100883 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:02 PM PDT 24 46113172 ps
T1386 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3526550172 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:05 PM PDT 24 76803055 ps
T227 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3428897079 Apr 18 01:38:03 PM PDT 24 Apr 18 01:38:11 PM PDT 24 749939333 ps
T225 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2869766305 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:06 PM PDT 24 124298994 ps
T233 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3147090747 Apr 18 01:38:08 PM PDT 24 Apr 18 01:38:10 PM PDT 24 30952216 ps
T234 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2500039556 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:09 PM PDT 24 388420498 ps
T270 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2134078467 Apr 18 01:38:05 PM PDT 24 Apr 18 01:38:09 PM PDT 24 36938601 ps
T222 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2015445122 Apr 18 01:38:06 PM PDT 24 Apr 18 01:38:11 PM PDT 24 238227415 ps
T278 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2946218303 Apr 18 01:38:06 PM PDT 24 Apr 18 01:38:11 PM PDT 24 258602123 ps
T247 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2107375348 Apr 18 01:38:07 PM PDT 24 Apr 18 01:38:15 PM PDT 24 51691611 ps
T268 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1417481129 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:02 PM PDT 24 28387574 ps
T1387 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.267143677 Apr 18 01:38:03 PM PDT 24 Apr 18 01:38:09 PM PDT 24 518679397 ps
T223 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1436309760 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:05 PM PDT 24 258172968 ps
T269 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.650043709 Apr 18 01:37:59 PM PDT 24 Apr 18 01:38:02 PM PDT 24 32349321 ps
T260 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2925220285 Apr 18 01:37:59 PM PDT 24 Apr 18 01:38:00 PM PDT 24 41321397 ps
T235 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.388738702 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:13 PM PDT 24 1256326135 ps
T265 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.4016134738 Apr 18 01:38:03 PM PDT 24 Apr 18 01:38:07 PM PDT 24 44261479 ps
T248 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.803500208 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:05 PM PDT 24 45852213 ps
T274 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2920951986 Apr 18 01:38:08 PM PDT 24 Apr 18 01:38:12 PM PDT 24 160870786 ps
T240 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1202568111 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:06 PM PDT 24 70030787 ps
T236 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.92701903 Apr 18 01:38:07 PM PDT 24 Apr 18 01:38:11 PM PDT 24 213671613 ps
T249 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3476800387 Apr 18 01:38:07 PM PDT 24 Apr 18 01:38:10 PM PDT 24 35053729 ps
T237 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.814899696 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:05 PM PDT 24 39025223 ps
T251 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.202251956 Apr 18 01:38:05 PM PDT 24 Apr 18 01:38:09 PM PDT 24 123686167 ps
T224 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3645430709 Apr 18 01:38:04 PM PDT 24 Apr 18 01:38:10 PM PDT 24 291074424 ps
T261 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3423152067 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:06 PM PDT 24 60627443 ps
T238 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1256301947 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:06 PM PDT 24 107117168 ps
T1388 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2443133601 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:03 PM PDT 24 32177320 ps
T275 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.4204047532 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:06 PM PDT 24 503417158 ps
T252 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3268964275 Apr 18 01:38:03 PM PDT 24 Apr 18 01:38:08 PM PDT 24 155937162 ps
T1389 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1178116138 Apr 18 01:38:04 PM PDT 24 Apr 18 01:38:08 PM PDT 24 56810203 ps
T1390 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1520854240 Apr 18 01:38:03 PM PDT 24 Apr 18 01:38:06 PM PDT 24 31573532 ps
T264 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.261036561 Apr 18 01:38:03 PM PDT 24 Apr 18 01:38:07 PM PDT 24 39693127 ps
T1391 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1013172978 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:05 PM PDT 24 29784537 ps
T1392 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.553282831 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:03 PM PDT 24 55488708 ps
T253 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2832036991 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:04 PM PDT 24 279028809 ps
T1393 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1819098296 Apr 18 01:38:39 PM PDT 24 Apr 18 01:38:40 PM PDT 24 36298738 ps
T239 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3316632211 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:07 PM PDT 24 450893185 ps
T1394 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2187751537 Apr 18 01:38:06 PM PDT 24 Apr 18 01:38:11 PM PDT 24 198876352 ps
T1395 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.4093932312 Apr 18 01:38:03 PM PDT 24 Apr 18 01:38:07 PM PDT 24 30184241 ps
T1396 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.502021746 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:04 PM PDT 24 40199838 ps
T263 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1755773371 Apr 18 01:37:59 PM PDT 24 Apr 18 01:38:00 PM PDT 24 44193730 ps
T256 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.4233385112 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:02 PM PDT 24 70163986 ps
T1397 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3596278710 Apr 18 01:38:05 PM PDT 24 Apr 18 01:38:10 PM PDT 24 127861745 ps
T271 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1414144190 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:09 PM PDT 24 41936474 ps
T279 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3357438543 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:09 PM PDT 24 490417330 ps
T241 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.4070959448 Apr 18 01:38:05 PM PDT 24 Apr 18 01:38:09 PM PDT 24 30895246 ps
T254 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2662814452 Apr 18 01:38:04 PM PDT 24 Apr 18 01:38:10 PM PDT 24 431042078 ps
T255 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3557398254 Apr 18 01:37:56 PM PDT 24 Apr 18 01:38:04 PM PDT 24 1498371194 ps
T1398 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2541280424 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:07 PM PDT 24 87795615 ps
T1399 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.138969988 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:06 PM PDT 24 40077395 ps
T277 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1380848648 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:09 PM PDT 24 572723090 ps
T1400 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.998195499 Apr 18 01:38:07 PM PDT 24 Apr 18 01:38:11 PM PDT 24 156174475 ps
T1401 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.163077932 Apr 18 01:38:05 PM PDT 24 Apr 18 01:38:10 PM PDT 24 67928896 ps
T1402 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1287311115 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:04 PM PDT 24 114060061 ps
T1403 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3279054208 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:12 PM PDT 24 1753141140 ps
T1404 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2997389706 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:07 PM PDT 24 209472430 ps
T1405 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1696598803 Apr 18 01:37:59 PM PDT 24 Apr 18 01:38:05 PM PDT 24 74908152 ps
T203 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2321607775 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:03 PM PDT 24 100713930 ps
T1406 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1883348317 Apr 18 01:38:04 PM PDT 24 Apr 18 01:38:10 PM PDT 24 102408057 ps
T272 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2938850494 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:06 PM PDT 24 957287950 ps
T1407 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3837599458 Apr 18 01:37:57 PM PDT 24 Apr 18 01:37:59 PM PDT 24 97749704 ps
T266 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3708602468 Apr 18 01:38:06 PM PDT 24 Apr 18 01:38:09 PM PDT 24 35080965 ps
T242 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2672358633 Apr 18 01:37:58 PM PDT 24 Apr 18 01:38:00 PM PDT 24 84956071 ps
T1408 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.873835593 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:02 PM PDT 24 46222261 ps
T1409 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1716551270 Apr 18 01:38:05 PM PDT 24 Apr 18 01:38:09 PM PDT 24 85882994 ps
T1410 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3415203881 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:03 PM PDT 24 73183839 ps
T1411 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1600561182 Apr 18 01:38:07 PM PDT 24 Apr 18 01:38:11 PM PDT 24 173248552 ps
T1412 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.974082846 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:06 PM PDT 24 39665187 ps
T1413 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1554196120 Apr 18 01:38:04 PM PDT 24 Apr 18 01:38:09 PM PDT 24 149390104 ps
T1414 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2604117387 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:05 PM PDT 24 28142603 ps
T1415 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.4129961075 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:07 PM PDT 24 155025503 ps
T1416 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1621672709 Apr 18 01:38:04 PM PDT 24 Apr 18 01:38:08 PM PDT 24 49075466 ps
T267 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1639963788 Apr 18 01:38:04 PM PDT 24 Apr 18 01:38:08 PM PDT 24 35817359 ps
T1417 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.18996796 Apr 18 01:38:06 PM PDT 24 Apr 18 01:38:11 PM PDT 24 155968157 ps
T1418 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2818073118 Apr 18 01:38:03 PM PDT 24 Apr 18 01:38:06 PM PDT 24 37126982 ps
T1419 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2175214406 Apr 18 01:38:03 PM PDT 24 Apr 18 01:38:07 PM PDT 24 33467507 ps
T1420 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1946504668 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:03 PM PDT 24 42804744 ps
T1421 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3582304921 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:10 PM PDT 24 500332556 ps
T1422 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1698780252 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:15 PM PDT 24 40210458 ps
T1423 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.221098266 Apr 18 01:38:06 PM PDT 24 Apr 18 01:38:09 PM PDT 24 68705180 ps
T1424 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2911530738 Apr 18 01:37:58 PM PDT 24 Apr 18 01:38:00 PM PDT 24 33311817 ps
T1425 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.74152190 Apr 18 01:37:58 PM PDT 24 Apr 18 01:38:06 PM PDT 24 110599741 ps
T61 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.665018001 Apr 18 01:38:08 PM PDT 24 Apr 18 01:38:10 PM PDT 24 75519785 ps
T1426 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3831933266 Apr 18 01:38:04 PM PDT 24 Apr 18 01:38:08 PM PDT 24 30501433 ps
T1427 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.13005937 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:07 PM PDT 24 98050944 ps
T1428 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1665291286 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:07 PM PDT 24 162085920 ps
T1429 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1715789574 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:07 PM PDT 24 121232146 ps
T1430 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3506731962 Apr 18 01:38:04 PM PDT 24 Apr 18 01:38:09 PM PDT 24 61520291 ps
T1431 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.13767696 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:05 PM PDT 24 86497065 ps
T1432 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.4259585887 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:05 PM PDT 24 260128118 ps
T1433 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1394933684 Apr 18 01:38:04 PM PDT 24 Apr 18 01:38:09 PM PDT 24 72943779 ps
T1434 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.549065615 Apr 18 01:38:03 PM PDT 24 Apr 18 01:38:07 PM PDT 24 143540399 ps
T1435 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1293099971 Apr 18 01:38:21 PM PDT 24 Apr 18 01:38:22 PM PDT 24 44165204 ps
T1436 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3601031796 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:06 PM PDT 24 32997479 ps
T1437 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3531536611 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:05 PM PDT 24 109319941 ps
T1438 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3487188356 Apr 18 01:38:08 PM PDT 24 Apr 18 01:38:11 PM PDT 24 135563160 ps
T276 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3886429787 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:08 PM PDT 24 696130614 ps
T1439 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2884812704 Apr 18 01:38:10 PM PDT 24 Apr 18 01:38:11 PM PDT 24 44591505 ps
T1440 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.390795139 Apr 18 01:38:03 PM PDT 24 Apr 18 01:38:08 PM PDT 24 155080952 ps
T1441 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1114055505 Apr 18 01:37:59 PM PDT 24 Apr 18 01:38:01 PM PDT 24 95263553 ps
T1442 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.404511099 Apr 18 01:38:04 PM PDT 24 Apr 18 01:38:07 PM PDT 24 30848069 ps
T1443 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2783394840 Apr 18 01:37:59 PM PDT 24 Apr 18 01:38:01 PM PDT 24 200681053 ps
T1444 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.410742775 Apr 18 01:38:07 PM PDT 24 Apr 18 01:38:10 PM PDT 24 30655411 ps
T1445 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1281631078 Apr 18 01:38:13 PM PDT 24 Apr 18 01:38:15 PM PDT 24 27661017 ps
T1446 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3173675671 Apr 18 01:38:06 PM PDT 24 Apr 18 01:38:11 PM PDT 24 144033325 ps
T1447 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.95596352 Apr 18 01:37:58 PM PDT 24 Apr 18 01:38:00 PM PDT 24 34338300 ps
T1448 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.286296752 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:06 PM PDT 24 199728356 ps
T1449 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2969541200 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:05 PM PDT 24 143196294 ps
T1450 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.872531855 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:02 PM PDT 24 35585600 ps
T1451 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.153620757 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:03 PM PDT 24 64779819 ps
T1452 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3492260435 Apr 18 01:37:59 PM PDT 24 Apr 18 01:38:02 PM PDT 24 80930238 ps
T1453 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2927225839 Apr 18 01:37:59 PM PDT 24 Apr 18 01:38:02 PM PDT 24 58533624 ps
T1454 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1212180324 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:05 PM PDT 24 52644109 ps
T1455 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1900816701 Apr 18 01:37:58 PM PDT 24 Apr 18 01:38:00 PM PDT 24 142874525 ps
T1456 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3445128429 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:06 PM PDT 24 75968513 ps
T1457 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3174387586 Apr 18 01:37:59 PM PDT 24 Apr 18 01:38:03 PM PDT 24 238272664 ps
T1458 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2247875975 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:07 PM PDT 24 153896126 ps
T1459 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.558812776 Apr 18 01:38:03 PM PDT 24 Apr 18 01:38:07 PM PDT 24 85466081 ps
T1460 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.176527371 Apr 18 01:37:57 PM PDT 24 Apr 18 01:37:58 PM PDT 24 33009748 ps
T1461 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3847308994 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:05 PM PDT 24 134921076 ps
T1462 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1123239065 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:06 PM PDT 24 45080650 ps
T1463 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1338835208 Apr 18 01:38:04 PM PDT 24 Apr 18 01:38:08 PM PDT 24 47258441 ps
T1464 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4033369627 Apr 18 01:38:06 PM PDT 24 Apr 18 01:38:09 PM PDT 24 61172222 ps
T1465 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1480169453 Apr 18 01:38:04 PM PDT 24 Apr 18 01:38:09 PM PDT 24 258016234 ps
T1466 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.594827669 Apr 18 01:38:23 PM PDT 24 Apr 18 01:38:24 PM PDT 24 33061276 ps
T1467 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3324281079 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:07 PM PDT 24 187722423 ps
T1468 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3687873489 Apr 18 01:38:05 PM PDT 24 Apr 18 01:38:08 PM PDT 24 40853354 ps
T1469 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1336029024 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:04 PM PDT 24 127134272 ps
T1470 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3282248996 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:06 PM PDT 24 188374075 ps
T273 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3806832472 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:08 PM PDT 24 524591980 ps
T1471 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3261920872 Apr 18 01:37:59 PM PDT 24 Apr 18 01:38:03 PM PDT 24 650246629 ps
T62 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3743822284 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:05 PM PDT 24 45768577 ps
T1472 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3905982304 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:07 PM PDT 24 274577718 ps
T1473 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2386332128 Apr 18 01:38:00 PM PDT 24 Apr 18 01:38:04 PM PDT 24 88920207 ps
T1474 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2991426925 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:05 PM PDT 24 34553017 ps
T1475 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.302831529 Apr 18 01:38:01 PM PDT 24 Apr 18 01:38:06 PM PDT 24 87843412 ps
T1476 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2048593088 Apr 18 01:38:05 PM PDT 24 Apr 18 01:38:13 PM PDT 24 165868057 ps
T1477 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3228403192 Apr 18 01:38:03 PM PDT 24 Apr 18 01:38:07 PM PDT 24 67300294 ps
T63 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2577189024 Apr 18 01:37:57 PM PDT 24 Apr 18 01:37:58 PM PDT 24 123954874 ps
T1478 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1441103452 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:06 PM PDT 24 41465989 ps
T1479 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3863325227 Apr 18 01:38:02 PM PDT 24 Apr 18 01:38:08 PM PDT 24 562288202 ps

Test location /workspace/coverage/default/23.usbdev_in_trans.3474467224
Short name T17
Test name
Test status
Simulation time 8470759855 ps
CPU time 8.52 seconds
Started Apr 18 01:15:52 PM PDT 24
Finished Apr 18 01:16:02 PM PDT 24
Peak memory 203924 kb
Host smart-e4df7298-9ae3-4067-98ef-314fa76bbea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34744
67224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.3474467224
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.2586041
Short name T12
Test name
Test status
Simulation time 19880149841 ps
CPU time 35.48 seconds
Started Apr 18 01:13:36 PM PDT 24
Finished Apr 18 01:14:13 PM PDT 24
Peak memory 204328 kb
Host smart-b39867ec-08f2-4f09-b4f5-e2fc7667af8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25860
41 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.2586041
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.4259103632
Short name T257
Test name
Test status
Simulation time 41627469 ps
CPU time 0.66 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:02 PM PDT 24
Peak memory 202888 kb
Host smart-8124e9a3-9e2b-46fb-af5a-4adef4e5275f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4259103632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.4259103632
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1802550011
Short name T56
Test name
Test status
Simulation time 186029231 ps
CPU time 2.52 seconds
Started Apr 18 01:38:44 PM PDT 24
Finished Apr 18 01:38:47 PM PDT 24
Peak memory 203756 kb
Host smart-d55d2892-ac45-484c-a811-cd7ef537a8fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1802550011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1802550011
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.1052112959
Short name T32
Test name
Test status
Simulation time 8410862309 ps
CPU time 8.09 seconds
Started Apr 18 01:16:53 PM PDT 24
Finished Apr 18 01:17:03 PM PDT 24
Peak memory 204052 kb
Host smart-776534be-0aee-45c6-973d-caf4a499fc4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10521
12959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.1052112959
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_smoke.2859298502
Short name T26
Test name
Test status
Simulation time 8455609236 ps
CPU time 8.27 seconds
Started Apr 18 01:13:22 PM PDT 24
Finished Apr 18 01:13:31 PM PDT 24
Peak memory 203960 kb
Host smart-ee8eb874-ac01-43c3-b0b9-280b6fa228cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28592
98502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.2859298502
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1671958473
Short name T262
Test name
Test status
Simulation time 37655584 ps
CPU time 0.65 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:04 PM PDT 24
Peak memory 202892 kb
Host smart-5388384b-333a-4e8c-b3e1-19f6c40e7278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1671958473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.1671958473
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.2372970192
Short name T37
Test name
Test status
Simulation time 8438502161 ps
CPU time 7.89 seconds
Started Apr 18 01:13:29 PM PDT 24
Finished Apr 18 01:13:37 PM PDT 24
Peak memory 203976 kb
Host smart-c0402997-94f9-4ec4-899f-9e025c2b3501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23729
70192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2372970192
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.3007243239
Short name T16
Test name
Test status
Simulation time 63643875 ps
CPU time 0.67 seconds
Started Apr 18 01:15:34 PM PDT 24
Finished Apr 18 01:15:36 PM PDT 24
Peak memory 203860 kb
Host smart-fb309a95-e040-4656-8719-3b4563bab80a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30072
43239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.3007243239
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.3152489689
Short name T9
Test name
Test status
Simulation time 8369209167 ps
CPU time 8.78 seconds
Started Apr 18 01:15:14 PM PDT 24
Finished Apr 18 01:15:23 PM PDT 24
Peak memory 203992 kb
Host smart-77b76f9e-8caa-48c0-b43e-7b498f71f8fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31524
89689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.3152489689
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.622195941
Short name T5
Test name
Test status
Simulation time 8366475925 ps
CPU time 7.49 seconds
Started Apr 18 01:14:11 PM PDT 24
Finished Apr 18 01:14:20 PM PDT 24
Peak memory 203976 kb
Host smart-1f51efcd-f6fc-4bff-ab76-73cedda26c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62219
5941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.622195941
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.367386532
Short name T201
Test name
Test status
Simulation time 91002047 ps
CPU time 1.1 seconds
Started Apr 18 01:37:55 PM PDT 24
Finished Apr 18 01:37:56 PM PDT 24
Peak memory 211912 kb
Host smart-128db8bc-9aa8-4580-9c73-2346435a576c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367386532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev
_csr_mem_rw_with_rand_reset.367386532
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.3545820539
Short name T210
Test name
Test status
Simulation time 243670948 ps
CPU time 2.02 seconds
Started Apr 18 01:16:40 PM PDT 24
Finished Apr 18 01:16:43 PM PDT 24
Peak memory 204168 kb
Host smart-d8825113-25e1-4902-8f44-755e93ed2c3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35458
20539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.3545820539
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.4117602499
Short name T4
Test name
Test status
Simulation time 79565523 ps
CPU time 0.91 seconds
Started Apr 18 01:37:59 PM PDT 24
Finished Apr 18 01:38:00 PM PDT 24
Peak memory 203268 kb
Host smart-ab543b36-f11b-41eb-95cc-aaef21994ada
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4117602499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.4117602499
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.851590978
Short name T59
Test name
Test status
Simulation time 231605892 ps
CPU time 1.07 seconds
Started Apr 18 01:13:20 PM PDT 24
Finished Apr 18 01:13:21 PM PDT 24
Peak memory 220228 kb
Host smart-5d037063-7811-4eda-89bb-4162f3fbe686
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=851590978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.851590978
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2925220285
Short name T260
Test name
Test status
Simulation time 41321397 ps
CPU time 0.66 seconds
Started Apr 18 01:37:59 PM PDT 24
Finished Apr 18 01:38:00 PM PDT 24
Peak memory 203000 kb
Host smart-b8cc42c1-09de-4c9e-89e5-6ef2ec01dbb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2925220285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.2925220285
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.4123070974
Short name T207
Test name
Test status
Simulation time 21426775561 ps
CPU time 39.97 seconds
Started Apr 18 01:17:05 PM PDT 24
Finished Apr 18 01:17:47 PM PDT 24
Peak memory 204288 kb
Host smart-336c875a-165d-47c3-ab30-6b61a812a584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41230
70974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.4123070974
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.972906358
Short name T198
Test name
Test status
Simulation time 380402515 ps
CPU time 6.88 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:08 PM PDT 24
Peak memory 203528 kb
Host smart-2b8acd22-9cda-4c3f-9189-9a8955f6e0ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=972906358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.972906358
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1819098296
Short name T1393
Test name
Test status
Simulation time 36298738 ps
CPU time 0.76 seconds
Started Apr 18 01:38:39 PM PDT 24
Finished Apr 18 01:38:40 PM PDT 24
Peak memory 202896 kb
Host smart-31e73bc1-c577-47a1-b255-148b4e6e8ac7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1819098296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1819098296
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1436309760
Short name T223
Test name
Test status
Simulation time 258172968 ps
CPU time 2.83 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:05 PM PDT 24
Peak memory 203672 kb
Host smart-50e64106-bde4-4367-ad19-92197417a07a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1436309760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.1436309760
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.4204047532
Short name T275
Test name
Test status
Simulation time 503417158 ps
CPU time 4.11 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:06 PM PDT 24
Peak memory 203552 kb
Host smart-30b51cb9-e9c6-401a-a669-637072f84625
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4204047532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.4204047532
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1639963788
Short name T267
Test name
Test status
Simulation time 35817359 ps
CPU time 0.63 seconds
Started Apr 18 01:38:04 PM PDT 24
Finished Apr 18 01:38:08 PM PDT 24
Peak memory 202912 kb
Host smart-a9a111be-125f-4e28-941d-41d7f7c6be3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1639963788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1639963788
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/default/32.usbdev_enable.4185394392
Short name T303
Test name
Test status
Simulation time 8386582440 ps
CPU time 7.88 seconds
Started Apr 18 01:16:35 PM PDT 24
Finished Apr 18 01:16:43 PM PDT 24
Peak memory 203860 kb
Host smart-41f17ffb-1184-44c8-9c30-a424c8cc249b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41853
94392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.4185394392
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2379863542
Short name T30
Test name
Test status
Simulation time 8443927679 ps
CPU time 9 seconds
Started Apr 18 01:14:51 PM PDT 24
Finished Apr 18 01:15:01 PM PDT 24
Peak memory 204080 kb
Host smart-d8f2452a-0845-4098-a9a7-8098cd4c4811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23798
63542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2379863542
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3806832472
Short name T273
Test name
Test status
Simulation time 524591980 ps
CPU time 4.75 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:08 PM PDT 24
Peak memory 203780 kb
Host smart-113d932e-5d5e-4058-b99c-b460662c15f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3806832472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3806832472
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1078409324
Short name T64
Test name
Test status
Simulation time 45968287 ps
CPU time 0.62 seconds
Started Apr 18 01:38:03 PM PDT 24
Finished Apr 18 01:38:07 PM PDT 24
Peak memory 202920 kb
Host smart-52823864-8ec9-4f1c-bda9-7ab7f643e9dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1078409324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1078409324
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.481528469
Short name T91
Test name
Test status
Simulation time 5107189492 ps
CPU time 32.45 seconds
Started Apr 18 01:13:23 PM PDT 24
Finished Apr 18 01:13:56 PM PDT 24
Peak memory 204272 kb
Host smart-3e3bee73-7aa3-4c0d-88ca-d56613e52306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48152
8469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.481528469
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3743822284
Short name T62
Test name
Test status
Simulation time 45768577 ps
CPU time 0.85 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:05 PM PDT 24
Peak memory 203396 kb
Host smart-9e782722-d960-467e-abce-98601465d8d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3743822284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3743822284
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3553105139
Short name T199
Test name
Test status
Simulation time 664650375 ps
CPU time 4.28 seconds
Started Apr 18 01:38:03 PM PDT 24
Finished Apr 18 01:38:10 PM PDT 24
Peak memory 203716 kb
Host smart-a5a2e5bc-984b-4f0b-b7f5-48e5111ff2c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3553105139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3553105139
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1459750263
Short name T245
Test name
Test status
Simulation time 43897711 ps
CPU time 0.83 seconds
Started Apr 18 01:38:03 PM PDT 24
Finished Apr 18 01:38:07 PM PDT 24
Peak memory 203420 kb
Host smart-e69ad609-51fc-4ff0-8adf-a7e11a5565d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1459750263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1459750263
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1380848648
Short name T277
Test name
Test status
Simulation time 572723090 ps
CPU time 4.93 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:09 PM PDT 24
Peak memory 203708 kb
Host smart-1ee7404c-e5c5-4a71-8631-750ef8881020
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1380848648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1380848648
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3886429787
Short name T276
Test name
Test status
Simulation time 696130614 ps
CPU time 4.75 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:08 PM PDT 24
Peak memory 203720 kb
Host smart-5dd73062-33fd-471d-ae9f-6af90a053546
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3886429787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3886429787
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.1164011903
Short name T24
Test name
Test status
Simulation time 8376806405 ps
CPU time 8.43 seconds
Started Apr 18 01:14:25 PM PDT 24
Finished Apr 18 01:14:34 PM PDT 24
Peak memory 204260 kb
Host smart-f222072d-6f41-444c-a61e-a0140cbe0734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11640
11903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.1164011903
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3858094917
Short name T521
Test name
Test status
Simulation time 33673943 ps
CPU time 0.68 seconds
Started Apr 18 01:17:18 PM PDT 24
Finished Apr 18 01:17:19 PM PDT 24
Peak memory 203900 kb
Host smart-3e6cfe2b-5cf0-4824-9d04-3ee3ac535a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38580
94917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3858094917
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1883348317
Short name T1406
Test name
Test status
Simulation time 102408057 ps
CPU time 3.02 seconds
Started Apr 18 01:38:04 PM PDT 24
Finished Apr 18 01:38:10 PM PDT 24
Peak memory 203728 kb
Host smart-78df65b0-54c3-4387-b35a-9e27c0e33390
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1883348317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1883348317
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.821503268
Short name T47
Test name
Test status
Simulation time 8463838117 ps
CPU time 8.29 seconds
Started Apr 18 01:16:03 PM PDT 24
Finished Apr 18 01:16:13 PM PDT 24
Peak memory 203624 kb
Host smart-67c51383-46b5-4955-a9a3-572f9176130b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82150
3268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.821503268
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.1993094732
Short name T175
Test name
Test status
Simulation time 8375095282 ps
CPU time 7.52 seconds
Started Apr 18 01:13:32 PM PDT 24
Finished Apr 18 01:13:40 PM PDT 24
Peak memory 203976 kb
Host smart-978d5b5d-b0ae-4b70-ae1b-d4265c60f3cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19930
94732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.1993094732
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_smoke.17099703
Short name T524
Test name
Test status
Simulation time 8463495739 ps
CPU time 7.9 seconds
Started Apr 18 01:14:43 PM PDT 24
Finished Apr 18 01:14:52 PM PDT 24
Peak memory 203924 kb
Host smart-e652c3c6-cdbd-4ff6-a76d-f88c1df16057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17099
703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.17099703
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.923080270
Short name T1333
Test name
Test status
Simulation time 8387236225 ps
CPU time 8.57 seconds
Started Apr 18 01:14:49 PM PDT 24
Finished Apr 18 01:14:58 PM PDT 24
Peak memory 204040 kb
Host smart-84c0a2db-7d4e-435d-be32-245078b67233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92308
0270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.923080270
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.3603066678
Short name T88
Test name
Test status
Simulation time 29430811403 ps
CPU time 58.31 seconds
Started Apr 18 01:14:50 PM PDT 24
Finished Apr 18 01:15:50 PM PDT 24
Peak memory 204304 kb
Host smart-100976f2-b7b2-45eb-b0e9-03334fd1378a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36030
66678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.3603066678
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_smoke.3104829080
Short name T147
Test name
Test status
Simulation time 8457691665 ps
CPU time 8.77 seconds
Started Apr 18 01:14:57 PM PDT 24
Finished Apr 18 01:15:07 PM PDT 24
Peak memory 203948 kb
Host smart-6b8f8f14-36e6-4ebf-a0f8-5b6bf2ff8e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31048
29080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.3104829080
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.889890458
Short name T170
Test name
Test status
Simulation time 8401716621 ps
CPU time 7.82 seconds
Started Apr 18 01:15:12 PM PDT 24
Finished Apr 18 01:15:20 PM PDT 24
Peak memory 203932 kb
Host smart-3b089814-319a-4052-ad61-db40fcff0cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88989
0458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.889890458
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2462981192
Short name T622
Test name
Test status
Simulation time 8434906114 ps
CPU time 8.25 seconds
Started Apr 18 01:15:23 PM PDT 24
Finished Apr 18 01:15:31 PM PDT 24
Peak memory 203988 kb
Host smart-45937dda-bf6f-4c8e-913a-628180d2ee72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24629
81192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2462981192
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_smoke.3561343750
Short name T138
Test name
Test status
Simulation time 8432561216 ps
CPU time 8.22 seconds
Started Apr 18 01:15:25 PM PDT 24
Finished Apr 18 01:15:34 PM PDT 24
Peak memory 204008 kb
Host smart-dfbc9707-1b80-4cf3-bf0d-0ae9921f93ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35613
43750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.3561343750
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.1102823542
Short name T180
Test name
Test status
Simulation time 8389282302 ps
CPU time 9.17 seconds
Started Apr 18 01:15:41 PM PDT 24
Finished Apr 18 01:15:51 PM PDT 24
Peak memory 204044 kb
Host smart-c6420399-01e0-4660-a730-6c9d31fb2cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11028
23542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.1102823542
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.3445979956
Short name T167
Test name
Test status
Simulation time 8403136752 ps
CPU time 8.25 seconds
Started Apr 18 01:15:41 PM PDT 24
Finished Apr 18 01:15:50 PM PDT 24
Peak memory 203996 kb
Host smart-fde7b292-b695-4447-a75e-e76db59c0097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34459
79956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.3445979956
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.2072243561
Short name T1048
Test name
Test status
Simulation time 8403831630 ps
CPU time 7.92 seconds
Started Apr 18 01:16:52 PM PDT 24
Finished Apr 18 01:17:01 PM PDT 24
Peak memory 203960 kb
Host smart-338bfc73-f555-42a8-83df-640d446d8048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20722
43561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.2072243561
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.114784375
Short name T27
Test name
Test status
Simulation time 8364950761 ps
CPU time 8.26 seconds
Started Apr 18 01:16:06 PM PDT 24
Finished Apr 18 01:16:15 PM PDT 24
Peak memory 203968 kb
Host smart-1cbfcb06-f148-47b3-864b-40275b0bbd30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11478
4375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.114784375
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.61577664
Short name T55
Test name
Test status
Simulation time 220780416 ps
CPU time 2.34 seconds
Started Apr 18 01:37:59 PM PDT 24
Finished Apr 18 01:38:02 PM PDT 24
Peak memory 203768 kb
Host smart-d0d6fc12-a9c6-45aa-87d8-20ff20e5940f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=61577664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.61577664
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2741591448
Short name T537
Test name
Test status
Simulation time 8367996820 ps
CPU time 8.64 seconds
Started Apr 18 01:13:24 PM PDT 24
Finished Apr 18 01:13:33 PM PDT 24
Peak memory 204020 kb
Host smart-b83a33ca-339c-4079-a66d-50d52cf746c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27415
91448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2741591448
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.3989068908
Short name T104
Test name
Test status
Simulation time 8494773515 ps
CPU time 8.35 seconds
Started Apr 18 01:13:23 PM PDT 24
Finished Apr 18 01:13:32 PM PDT 24
Peak memory 204024 kb
Host smart-13f8f720-ac1e-4f3b-a3cb-ed8cc176f97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39890
68908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.3989068908
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.2800958840
Short name T596
Test name
Test status
Simulation time 8396754640 ps
CPU time 8.08 seconds
Started Apr 18 01:13:23 PM PDT 24
Finished Apr 18 01:13:31 PM PDT 24
Peak memory 204052 kb
Host smart-2269ddac-f2ec-4175-b370-638c562f5240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28009
58840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.2800958840
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.3485805066
Short name T146
Test name
Test status
Simulation time 8447530256 ps
CPU time 9.36 seconds
Started Apr 18 01:13:25 PM PDT 24
Finished Apr 18 01:13:35 PM PDT 24
Peak memory 204044 kb
Host smart-139ceb0a-e94c-49a3-91ab-ec09789fb4a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34858
05066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.3485805066
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1668915516
Short name T97
Test name
Test status
Simulation time 8448293038 ps
CPU time 7.79 seconds
Started Apr 18 01:13:30 PM PDT 24
Finished Apr 18 01:13:39 PM PDT 24
Peak memory 204036 kb
Host smart-5ca46784-0992-4516-9021-8b0956e7ce9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16689
15516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1668915516
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.2720361187
Short name T848
Test name
Test status
Simulation time 8382339315 ps
CPU time 9.76 seconds
Started Apr 18 01:14:45 PM PDT 24
Finished Apr 18 01:14:56 PM PDT 24
Peak memory 203996 kb
Host smart-c71fa317-68e1-4ce6-bc0d-15fa826c8741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27203
61187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.2720361187
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.2279255374
Short name T574
Test name
Test status
Simulation time 8412694675 ps
CPU time 8.24 seconds
Started Apr 18 01:14:47 PM PDT 24
Finished Apr 18 01:14:56 PM PDT 24
Peak memory 203916 kb
Host smart-b9cfaca1-4a5d-4388-8079-cc7062a1f14d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22792
55374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.2279255374
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.2516014595
Short name T106
Test name
Test status
Simulation time 8434887544 ps
CPU time 7.9 seconds
Started Apr 18 01:14:55 PM PDT 24
Finished Apr 18 01:15:04 PM PDT 24
Peak memory 203944 kb
Host smart-e9146c17-fab6-4132-a35e-f03a4796b81b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25160
14595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.2516014595
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.1934962793
Short name T1287
Test name
Test status
Simulation time 8434013087 ps
CPU time 8.43 seconds
Started Apr 18 01:15:07 PM PDT 24
Finished Apr 18 01:15:16 PM PDT 24
Peak memory 203908 kb
Host smart-88492b43-fb92-431d-bb0d-70f3950f9f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19349
62793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.1934962793
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.1960794297
Short name T787
Test name
Test status
Simulation time 8362387284 ps
CPU time 9.63 seconds
Started Apr 18 01:15:10 PM PDT 24
Finished Apr 18 01:15:20 PM PDT 24
Peak memory 204000 kb
Host smart-70edbade-a13c-49c7-952a-45b5905b5e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19607
94297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1960794297
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.1033384971
Short name T125
Test name
Test status
Simulation time 8395431690 ps
CPU time 7.68 seconds
Started Apr 18 01:15:06 PM PDT 24
Finished Apr 18 01:15:14 PM PDT 24
Peak memory 203956 kb
Host smart-3e2b1294-d311-467c-9290-8427d546d994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10333
84971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.1033384971
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.267656487
Short name T116
Test name
Test status
Simulation time 8406289245 ps
CPU time 7.82 seconds
Started Apr 18 01:15:11 PM PDT 24
Finished Apr 18 01:15:20 PM PDT 24
Peak memory 203956 kb
Host smart-d632bd15-4e2a-4991-870f-5d61c98b6988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26765
6487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.267656487
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.1921120513
Short name T94
Test name
Test status
Simulation time 8468177333 ps
CPU time 8.87 seconds
Started Apr 18 01:15:11 PM PDT 24
Finished Apr 18 01:15:20 PM PDT 24
Peak memory 204004 kb
Host smart-760da537-b78e-486d-9a02-6f1e3f4158cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19211
20513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1921120513
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.1502355153
Short name T678
Test name
Test status
Simulation time 8406325982 ps
CPU time 10.04 seconds
Started Apr 18 01:15:19 PM PDT 24
Finished Apr 18 01:15:30 PM PDT 24
Peak memory 204040 kb
Host smart-ca21e549-b115-403a-954f-a94b11335abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15023
55153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.1502355153
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.2507801301
Short name T1230
Test name
Test status
Simulation time 8388996065 ps
CPU time 10.14 seconds
Started Apr 18 01:15:20 PM PDT 24
Finished Apr 18 01:15:31 PM PDT 24
Peak memory 204012 kb
Host smart-736dc5a9-85d4-4c80-a067-1df738415f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25078
01301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.2507801301
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.3090049231
Short name T101
Test name
Test status
Simulation time 8429690341 ps
CPU time 8.11 seconds
Started Apr 18 01:15:20 PM PDT 24
Finished Apr 18 01:15:29 PM PDT 24
Peak memory 204016 kb
Host smart-1bc8b317-cad1-4afa-a041-d3e8cba70e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30900
49231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.3090049231
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.3711708003
Short name T971
Test name
Test status
Simulation time 8443359574 ps
CPU time 7.67 seconds
Started Apr 18 01:15:27 PM PDT 24
Finished Apr 18 01:15:35 PM PDT 24
Peak memory 203980 kb
Host smart-c129804e-765d-4de2-acaa-90181c62af67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37117
08003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3711708003
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.1811968218
Short name T92
Test name
Test status
Simulation time 8423130652 ps
CPU time 8.77 seconds
Started Apr 18 01:15:52 PM PDT 24
Finished Apr 18 01:16:02 PM PDT 24
Peak memory 204012 kb
Host smart-37f34468-065a-41c0-a8af-31b60a871b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18119
68218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.1811968218
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.997595567
Short name T96
Test name
Test status
Simulation time 8467250866 ps
CPU time 7.71 seconds
Started Apr 18 01:16:05 PM PDT 24
Finished Apr 18 01:16:14 PM PDT 24
Peak memory 203992 kb
Host smart-8c751dab-3950-457d-aa36-e22e17041158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99759
5567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.997595567
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3431198225
Short name T120
Test name
Test status
Simulation time 8434917811 ps
CPU time 7.68 seconds
Started Apr 18 01:13:59 PM PDT 24
Finished Apr 18 01:14:07 PM PDT 24
Peak memory 204028 kb
Host smart-9f54955e-0c16-4e4f-8b31-6d7d48c09b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34311
98225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3431198225
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3526550172
Short name T1386
Test name
Test status
Simulation time 76803055 ps
CPU time 1.92 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:05 PM PDT 24
Peak memory 203660 kb
Host smart-beb7f38f-b557-4ad2-a008-20f5f86fe55b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3526550172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.3526550172
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3279054208
Short name T1403
Test name
Test status
Simulation time 1753141140 ps
CPU time 9.15 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:12 PM PDT 24
Peak memory 203536 kb
Host smart-1c5d3e72-0860-4c60-8efb-16bbafcef38f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3279054208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.3279054208
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2969541200
Short name T1449
Test name
Test status
Simulation time 143196294 ps
CPU time 1.83 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:05 PM PDT 24
Peak memory 212000 kb
Host smart-ce8b2d27-1f49-45c5-8ba6-9f64a49ef8aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969541200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.2969541200
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3110584414
Short name T232
Test name
Test status
Simulation time 106365324 ps
CPU time 1.44 seconds
Started Apr 18 01:37:59 PM PDT 24
Finished Apr 18 01:38:01 PM PDT 24
Peak memory 211764 kb
Host smart-893afc48-f470-4eef-9494-949d7ec6aedb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3110584414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3110584414
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.4157892147
Short name T1383
Test name
Test status
Simulation time 271601933 ps
CPU time 2.32 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:04 PM PDT 24
Peak memory 203540 kb
Host smart-2509890b-e999-4f8a-bc93-2d247966ad55
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4157892147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.4157892147
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.202251956
Short name T251
Test name
Test status
Simulation time 123686167 ps
CPU time 1.22 seconds
Started Apr 18 01:38:05 PM PDT 24
Finished Apr 18 01:38:09 PM PDT 24
Peak memory 203868 kb
Host smart-b65d3b1a-3f9b-4088-ba92-5b92e32285c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=202251956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.202251956
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3174387586
Short name T1457
Test name
Test status
Simulation time 238272664 ps
CPU time 2.41 seconds
Started Apr 18 01:37:59 PM PDT 24
Finished Apr 18 01:38:03 PM PDT 24
Peak memory 203876 kb
Host smart-ca5bf47c-4cd9-46d6-93da-8b60ba901ef7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3174387586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3174387586
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.267143677
Short name T1387
Test name
Test status
Simulation time 518679397 ps
CPU time 2.42 seconds
Started Apr 18 01:38:03 PM PDT 24
Finished Apr 18 01:38:09 PM PDT 24
Peak memory 203792 kb
Host smart-8ea33ca7-2430-4d9c-81d7-913f18f6da8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=267143677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.267143677
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2247875975
Short name T1458
Test name
Test status
Simulation time 153896126 ps
CPU time 1.95 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:07 PM PDT 24
Peak memory 203612 kb
Host smart-8430df64-afbf-4cba-a580-8cddfea82d46
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2247875975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2247875975
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.665018001
Short name T61
Test name
Test status
Simulation time 75519785 ps
CPU time 0.95 seconds
Started Apr 18 01:38:08 PM PDT 24
Finished Apr 18 01:38:10 PM PDT 24
Peak memory 203492 kb
Host smart-771e4d86-b131-469b-98ab-06696e3b5654
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=665018001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.665018001
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3487188356
Short name T1438
Test name
Test status
Simulation time 135563160 ps
CPU time 1.93 seconds
Started Apr 18 01:38:08 PM PDT 24
Finished Apr 18 01:38:11 PM PDT 24
Peak memory 212132 kb
Host smart-a703fa5c-535f-4d23-b878-4ff0e89107da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487188356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.3487188356
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.814899696
Short name T237
Test name
Test status
Simulation time 39025223 ps
CPU time 0.91 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:05 PM PDT 24
Peak memory 203576 kb
Host smart-d44fbd0c-beac-4319-945a-586cdce61c68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=814899696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.814899696
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.92701903
Short name T236
Test name
Test status
Simulation time 213671613 ps
CPU time 2.37 seconds
Started Apr 18 01:38:07 PM PDT 24
Finished Apr 18 01:38:11 PM PDT 24
Peak memory 211992 kb
Host smart-fdbdb148-cd31-4812-9f3a-ec2e60f3e855
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=92701903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.92701903
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.4259585887
Short name T1432
Test name
Test status
Simulation time 260128118 ps
CPU time 2.47 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:05 PM PDT 24
Peak memory 203540 kb
Host smart-835ac919-59c8-4912-9bc8-fad66b8e6c88
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4259585887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.4259585887
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2107375348
Short name T247
Test name
Test status
Simulation time 51691611 ps
CPU time 1.04 seconds
Started Apr 18 01:38:07 PM PDT 24
Finished Apr 18 01:38:15 PM PDT 24
Peak memory 203864 kb
Host smart-72ecb37a-5cbe-4948-84ae-9382cc3f3ee5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2107375348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2107375348
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.410531438
Short name T205
Test name
Test status
Simulation time 90049241 ps
CPU time 2.58 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:05 PM PDT 24
Peak memory 203812 kb
Host smart-3e2e81a8-ee0d-4cf1-a9cc-34ab0b5d766a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=410531438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.410531438
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1554196120
Short name T1413
Test name
Test status
Simulation time 149390104 ps
CPU time 1.64 seconds
Started Apr 18 01:38:04 PM PDT 24
Finished Apr 18 01:38:09 PM PDT 24
Peak memory 214500 kb
Host smart-6b8b67fa-fbc9-423d-89a2-fdd59418240f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554196120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.1554196120
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.558812776
Short name T1459
Test name
Test status
Simulation time 85466081 ps
CPU time 1.04 seconds
Started Apr 18 01:38:03 PM PDT 24
Finished Apr 18 01:38:07 PM PDT 24
Peak memory 203716 kb
Host smart-d381370f-ef16-423a-8798-d14dd098a0e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=558812776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.558812776
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.594827669
Short name T1466
Test name
Test status
Simulation time 33061276 ps
CPU time 0.64 seconds
Started Apr 18 01:38:23 PM PDT 24
Finished Apr 18 01:38:24 PM PDT 24
Peak memory 202908 kb
Host smart-f241bb9c-7fa3-4372-ad62-ca850db0074c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=594827669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.594827669
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1480169453
Short name T1465
Test name
Test status
Simulation time 258016234 ps
CPU time 1.65 seconds
Started Apr 18 01:38:04 PM PDT 24
Finished Apr 18 01:38:09 PM PDT 24
Peak memory 203812 kb
Host smart-195b1d8a-7a2b-4757-923f-09a9362dfe34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1480169453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.1480169453
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3357438543
Short name T279
Test name
Test status
Simulation time 490417330 ps
CPU time 3.98 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:09 PM PDT 24
Peak memory 203676 kb
Host smart-de574c79-f342-481d-9e24-a6a2ce1ccc55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3357438543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.3357438543
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2541280424
Short name T1398
Test name
Test status
Simulation time 87795615 ps
CPU time 2.39 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:07 PM PDT 24
Peak memory 212052 kb
Host smart-e389fbb0-edc4-4a73-a405-7ef0d0166015
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541280424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2541280424
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3476800387
Short name T249
Test name
Test status
Simulation time 35053729 ps
CPU time 0.81 seconds
Started Apr 18 01:38:07 PM PDT 24
Finished Apr 18 01:38:10 PM PDT 24
Peak memory 203328 kb
Host smart-a2e00973-ef89-48de-a7f4-d4fc2e8b2cdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3476800387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3476800387
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2604117387
Short name T1414
Test name
Test status
Simulation time 28142603 ps
CPU time 0.64 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:05 PM PDT 24
Peak memory 202908 kb
Host smart-8f8d485b-fc64-4461-963b-aa755d4af22a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2604117387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2604117387
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3151857601
Short name T243
Test name
Test status
Simulation time 229002863 ps
CPU time 1.35 seconds
Started Apr 18 01:38:06 PM PDT 24
Finished Apr 18 01:38:10 PM PDT 24
Peak memory 203628 kb
Host smart-ea855502-86cb-4f91-b689-e0b5ddb6ad20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3151857601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3151857601
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.302831529
Short name T1475
Test name
Test status
Simulation time 87843412 ps
CPU time 2.47 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:06 PM PDT 24
Peak memory 203768 kb
Host smart-232fc8e5-6016-4432-a466-374a5235406c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=302831529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.302831529
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2783394840
Short name T1443
Test name
Test status
Simulation time 200681053 ps
CPU time 1.81 seconds
Started Apr 18 01:37:59 PM PDT 24
Finished Apr 18 01:38:01 PM PDT 24
Peak memory 212028 kb
Host smart-64b142f6-d503-4c12-b175-b37c1acc8552
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783394840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.2783394840
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.13767696
Short name T1431
Test name
Test status
Simulation time 86497065 ps
CPU time 0.95 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:05 PM PDT 24
Peak memory 203620 kb
Host smart-edcb9b04-265f-4ae7-adcd-e72bafe39733
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=13767696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.13767696
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.4093932312
Short name T1395
Test name
Test status
Simulation time 30184241 ps
CPU time 0.62 seconds
Started Apr 18 01:38:03 PM PDT 24
Finished Apr 18 01:38:07 PM PDT 24
Peak memory 202888 kb
Host smart-2e607e3d-f332-4874-be15-524b34734e9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4093932312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.4093932312
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1900816701
Short name T1455
Test name
Test status
Simulation time 142874525 ps
CPU time 1.54 seconds
Started Apr 18 01:37:58 PM PDT 24
Finished Apr 18 01:38:00 PM PDT 24
Peak memory 203716 kb
Host smart-d97f4de5-246d-4d9c-8436-e1e306cb871e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1900816701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.1900816701
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2015445122
Short name T222
Test name
Test status
Simulation time 238227415 ps
CPU time 3.01 seconds
Started Apr 18 01:38:06 PM PDT 24
Finished Apr 18 01:38:11 PM PDT 24
Peak memory 203684 kb
Host smart-ea8a34a0-ed61-443f-b51b-fd388581ab4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2015445122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2015445122
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.286296752
Short name T1448
Test name
Test status
Simulation time 199728356 ps
CPU time 2.42 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:06 PM PDT 24
Peak memory 203644 kb
Host smart-051f3494-3c5f-45d6-aceb-478a3618faed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=286296752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.286296752
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.153620757
Short name T1451
Test name
Test status
Simulation time 64779819 ps
CPU time 1.74 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:03 PM PDT 24
Peak memory 211912 kb
Host smart-f0767894-9732-4f71-bbf1-4647a887b0bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153620757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbde
v_csr_mem_rw_with_rand_reset.153620757
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.95596352
Short name T1447
Test name
Test status
Simulation time 34338300 ps
CPU time 0.82 seconds
Started Apr 18 01:37:58 PM PDT 24
Finished Apr 18 01:38:00 PM PDT 24
Peak memory 203344 kb
Host smart-bef69ce9-77f5-4ccb-b14a-2c7a115ab2b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=95596352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.95596352
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1698780252
Short name T1422
Test name
Test status
Simulation time 40210458 ps
CPU time 0.66 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:15 PM PDT 24
Peak memory 202932 kb
Host smart-b010ae0e-0349-4dd4-be97-b2d83cac2a9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1698780252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1698780252
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2832036991
Short name T253
Test name
Test status
Simulation time 279028809 ps
CPU time 1.78 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:04 PM PDT 24
Peak memory 203712 kb
Host smart-78f2357f-c143-4011-b0c9-9f650f364988
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2832036991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.2832036991
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3645430709
Short name T224
Test name
Test status
Simulation time 291074424 ps
CPU time 3.32 seconds
Started Apr 18 01:38:04 PM PDT 24
Finished Apr 18 01:38:10 PM PDT 24
Peak memory 203872 kb
Host smart-be224c5e-c134-4183-97f7-fd343a26bd13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3645430709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3645430709
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.998195499
Short name T1400
Test name
Test status
Simulation time 156174475 ps
CPU time 1.74 seconds
Started Apr 18 01:38:07 PM PDT 24
Finished Apr 18 01:38:11 PM PDT 24
Peak memory 214656 kb
Host smart-882c2d8f-23ac-4521-8d84-f7de8f0da5e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998195499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbde
v_csr_mem_rw_with_rand_reset.998195499
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1202568111
Short name T240
Test name
Test status
Simulation time 70030787 ps
CPU time 0.91 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:06 PM PDT 24
Peak memory 203652 kb
Host smart-81a91d4b-b2ca-4410-b2e3-e6190877db40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1202568111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1202568111
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1417481129
Short name T268
Test name
Test status
Simulation time 28387574 ps
CPU time 0.71 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:02 PM PDT 24
Peak memory 202784 kb
Host smart-8150bc3c-1262-42c0-9848-ff1764d56b37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1417481129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1417481129
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1665291286
Short name T1428
Test name
Test status
Simulation time 162085920 ps
CPU time 1.56 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:07 PM PDT 24
Peak memory 203740 kb
Host smart-4f3d446e-e1f5-4d71-9e3c-2b2551ac429f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1665291286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.1665291286
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2187751537
Short name T1394
Test name
Test status
Simulation time 198876352 ps
CPU time 2.56 seconds
Started Apr 18 01:38:06 PM PDT 24
Finished Apr 18 01:38:11 PM PDT 24
Peak memory 211868 kb
Host smart-54aeb196-2e0c-4a63-b72c-5c9836742446
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2187751537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2187751537
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1150830125
Short name T200
Test name
Test status
Simulation time 282974081 ps
CPU time 2.52 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:08 PM PDT 24
Peak memory 203776 kb
Host smart-92ece0bc-5235-446d-8661-359f724eb201
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1150830125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1150830125
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1480606576
Short name T202
Test name
Test status
Simulation time 221260714 ps
CPU time 1.76 seconds
Started Apr 18 01:37:58 PM PDT 24
Finished Apr 18 01:38:00 PM PDT 24
Peak memory 212076 kb
Host smart-b7f28138-7153-4140-9c4a-4ff249b20492
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480606576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.1480606576
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3147090747
Short name T233
Test name
Test status
Simulation time 30952216 ps
CPU time 0.88 seconds
Started Apr 18 01:38:08 PM PDT 24
Finished Apr 18 01:38:10 PM PDT 24
Peak memory 203656 kb
Host smart-59b9cc33-dbbd-47b0-b02f-dccfaeec4f6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3147090747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.3147090747
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3682436714
Short name T258
Test name
Test status
Simulation time 67787710 ps
CPU time 0.7 seconds
Started Apr 18 01:37:58 PM PDT 24
Finished Apr 18 01:38:00 PM PDT 24
Peak memory 202988 kb
Host smart-a2cdc952-b7e0-4170-a8ab-10f10cf30f6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3682436714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.3682436714
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1716551270
Short name T1409
Test name
Test status
Simulation time 85882994 ps
CPU time 1.07 seconds
Started Apr 18 01:38:05 PM PDT 24
Finished Apr 18 01:38:09 PM PDT 24
Peak memory 203780 kb
Host smart-1939676f-05dc-49b4-9d24-e61c146e86ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1716551270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1716551270
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3173675671
Short name T1446
Test name
Test status
Simulation time 144033325 ps
CPU time 2.2 seconds
Started Apr 18 01:38:06 PM PDT 24
Finished Apr 18 01:38:11 PM PDT 24
Peak memory 203684 kb
Host smart-98b361b8-c232-44c2-9b8b-cf05439a3f75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3173675671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3173675671
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1715789574
Short name T1429
Test name
Test status
Simulation time 121232146 ps
CPU time 1.68 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:07 PM PDT 24
Peak memory 211868 kb
Host smart-90c75e0d-a239-41a9-9093-019cdb7ef630
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715789574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.1715789574
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2927225839
Short name T1453
Test name
Test status
Simulation time 58533624 ps
CPU time 0.95 seconds
Started Apr 18 01:37:59 PM PDT 24
Finished Apr 18 01:38:02 PM PDT 24
Peak memory 203568 kb
Host smart-c26c36e9-9a4c-45fb-b296-b2bbdd147658
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2927225839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2927225839
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.974082846
Short name T1412
Test name
Test status
Simulation time 39665187 ps
CPU time 0.66 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:06 PM PDT 24
Peak memory 202840 kb
Host smart-1a4e9046-2aac-4ebc-b822-df88f50ba39e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=974082846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.974082846
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3596278710
Short name T1397
Test name
Test status
Simulation time 127861745 ps
CPU time 1.59 seconds
Started Apr 18 01:38:05 PM PDT 24
Finished Apr 18 01:38:10 PM PDT 24
Peak memory 203804 kb
Host smart-fbef8d08-0dfa-4415-99e3-544dbc4e845b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3596278710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3596278710
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.74152190
Short name T1425
Test name
Test status
Simulation time 110599741 ps
CPU time 1.47 seconds
Started Apr 18 01:37:58 PM PDT 24
Finished Apr 18 01:38:06 PM PDT 24
Peak memory 203820 kb
Host smart-b79f8fdc-b7ba-4864-a978-41959722191f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=74152190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.74152190
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2662814452
Short name T254
Test name
Test status
Simulation time 431042078 ps
CPU time 2.89 seconds
Started Apr 18 01:38:04 PM PDT 24
Finished Apr 18 01:38:10 PM PDT 24
Peak memory 203764 kb
Host smart-d992b14a-4c47-4877-b0d3-c1edc02db6b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2662814452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.2662814452
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.553282831
Short name T1392
Test name
Test status
Simulation time 55488708 ps
CPU time 1.45 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:03 PM PDT 24
Peak memory 214672 kb
Host smart-fcabf9c3-5d39-4eba-b7d9-9498ba9eee40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553282831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbde
v_csr_mem_rw_with_rand_reset.553282831
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3415203881
Short name T1410
Test name
Test status
Simulation time 73183839 ps
CPU time 1.01 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:03 PM PDT 24
Peak memory 203660 kb
Host smart-273df8bc-1c1d-46d3-b60d-046f5dacf41a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3415203881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3415203881
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1281631078
Short name T1445
Test name
Test status
Simulation time 27661017 ps
CPU time 0.64 seconds
Started Apr 18 01:38:13 PM PDT 24
Finished Apr 18 01:38:15 PM PDT 24
Peak memory 202900 kb
Host smart-b4a90667-3486-44f5-b244-25db6825ccbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1281631078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1281631078
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3859164142
Short name T244
Test name
Test status
Simulation time 61560641 ps
CPU time 1.33 seconds
Started Apr 18 01:38:05 PM PDT 24
Finished Apr 18 01:38:09 PM PDT 24
Peak memory 203804 kb
Host smart-0a6b09d9-5e82-4e07-85df-d19dbd0e4313
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3859164142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.3859164142
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1394933684
Short name T1433
Test name
Test status
Simulation time 72943779 ps
CPU time 1.3 seconds
Started Apr 18 01:38:04 PM PDT 24
Finished Apr 18 01:38:09 PM PDT 24
Peak memory 203900 kb
Host smart-dd3490eb-141c-4cc3-b8d3-b96d72158bdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1394933684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1394933684
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3863325227
Short name T1479
Test name
Test status
Simulation time 562288202 ps
CPU time 2.65 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:08 PM PDT 24
Peak memory 203660 kb
Host smart-6e5e9d45-71b3-4f55-887f-5634f4b422a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3863325227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3863325227
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3506731962
Short name T1430
Test name
Test status
Simulation time 61520291 ps
CPU time 1.58 seconds
Started Apr 18 01:38:04 PM PDT 24
Finished Apr 18 01:38:09 PM PDT 24
Peak memory 212028 kb
Host smart-6ae88983-f5cb-4652-afe0-891149f4a111
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506731962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.3506731962
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4033369627
Short name T1464
Test name
Test status
Simulation time 61172222 ps
CPU time 0.97 seconds
Started Apr 18 01:38:06 PM PDT 24
Finished Apr 18 01:38:09 PM PDT 24
Peak memory 203748 kb
Host smart-12cfaed7-9146-4449-805c-3711bbd25c97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4033369627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.4033369627
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.650043709
Short name T269
Test name
Test status
Simulation time 32349321 ps
CPU time 0.65 seconds
Started Apr 18 01:37:59 PM PDT 24
Finished Apr 18 01:38:02 PM PDT 24
Peak memory 202872 kb
Host smart-5720b993-ed02-4048-a2f5-8820da091df1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=650043709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.650043709
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3268964275
Short name T252
Test name
Test status
Simulation time 155937162 ps
CPU time 1.2 seconds
Started Apr 18 01:38:03 PM PDT 24
Finished Apr 18 01:38:08 PM PDT 24
Peak memory 203712 kb
Host smart-9fda16d5-6ad1-4a48-bc6f-22f1b03412fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3268964275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3268964275
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3228403192
Short name T1477
Test name
Test status
Simulation time 67300294 ps
CPU time 1.61 seconds
Started Apr 18 01:38:03 PM PDT 24
Finished Apr 18 01:38:07 PM PDT 24
Peak memory 203772 kb
Host smart-0b5d9f84-29a4-43e2-8d00-c0b23fb89dd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3228403192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3228403192
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.4129961075
Short name T1415
Test name
Test status
Simulation time 155025503 ps
CPU time 2.01 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:07 PM PDT 24
Peak memory 212000 kb
Host smart-246b66a0-c6f5-402a-951d-9e96e94604b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129961075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.4129961075
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.221098266
Short name T1423
Test name
Test status
Simulation time 68705180 ps
CPU time 0.98 seconds
Started Apr 18 01:38:06 PM PDT 24
Finished Apr 18 01:38:09 PM PDT 24
Peak memory 203624 kb
Host smart-7d51caba-8361-4a52-ad09-8aba4b2a37ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=221098266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.221098266
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1946504668
Short name T1420
Test name
Test status
Simulation time 42804744 ps
CPU time 0.65 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:03 PM PDT 24
Peak memory 202988 kb
Host smart-2dd5c010-12a7-4a38-ad11-f19fcd0ec2a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1946504668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.1946504668
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.390795139
Short name T1440
Test name
Test status
Simulation time 155080952 ps
CPU time 1.41 seconds
Started Apr 18 01:38:03 PM PDT 24
Finished Apr 18 01:38:08 PM PDT 24
Peak memory 203704 kb
Host smart-ec795a7d-d270-4dbc-925d-6984c3746aec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=390795139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.390795139
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1336029024
Short name T1469
Test name
Test status
Simulation time 127134272 ps
CPU time 1.43 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:04 PM PDT 24
Peak memory 203676 kb
Host smart-edb87704-fc9c-48ca-a6de-05019e6b1859
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1336029024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1336029024
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2938850494
Short name T272
Test name
Test status
Simulation time 957287950 ps
CPU time 3.01 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:06 PM PDT 24
Peak memory 203928 kb
Host smart-271d8c07-60f5-4e23-940e-4b3f0c2b4a10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2938850494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2938850494
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3324281079
Short name T1467
Test name
Test status
Simulation time 187722423 ps
CPU time 2.08 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:07 PM PDT 24
Peak memory 203600 kb
Host smart-9ddd5b37-917a-482a-b2d9-4f3a29364a17
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3324281079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3324281079
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3316632211
Short name T239
Test name
Test status
Simulation time 450893185 ps
CPU time 4.08 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:07 PM PDT 24
Peak memory 203628 kb
Host smart-3ab0bffd-5458-4621-844f-4407530d66ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3316632211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.3316632211
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1058194087
Short name T196
Test name
Test status
Simulation time 123055117 ps
CPU time 1.61 seconds
Started Apr 18 01:38:03 PM PDT 24
Finished Apr 18 01:38:08 PM PDT 24
Peak memory 220092 kb
Host smart-7679eb8d-36ba-450d-958d-62133d13cf09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058194087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.1058194087
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.4070959448
Short name T241
Test name
Test status
Simulation time 30895246 ps
CPU time 0.77 seconds
Started Apr 18 01:38:05 PM PDT 24
Finished Apr 18 01:38:09 PM PDT 24
Peak memory 203244 kb
Host smart-8958c1ab-01c6-4312-8251-4913351a4756
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4070959448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.4070959448
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3831933266
Short name T1426
Test name
Test status
Simulation time 30501433 ps
CPU time 0.63 seconds
Started Apr 18 01:38:04 PM PDT 24
Finished Apr 18 01:38:08 PM PDT 24
Peak memory 202864 kb
Host smart-8eaa256a-1542-43a0-b534-35811960f16b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3831933266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3831933266
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2294446272
Short name T231
Test name
Test status
Simulation time 156215663 ps
CPU time 2.23 seconds
Started Apr 18 01:38:03 PM PDT 24
Finished Apr 18 01:38:08 PM PDT 24
Peak memory 211804 kb
Host smart-eaf04e2f-6b47-4cee-a53e-c052b2f4887a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2294446272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2294446272
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3677633861
Short name T1385
Test name
Test status
Simulation time 191601368 ps
CPU time 4.03 seconds
Started Apr 18 01:38:05 PM PDT 24
Finished Apr 18 01:38:12 PM PDT 24
Peak memory 203768 kb
Host smart-1b78ea2e-0ed8-40a7-ae95-b78c64ae61f6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3677633861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3677633861
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.803500208
Short name T248
Test name
Test status
Simulation time 45852213 ps
CPU time 0.95 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:05 PM PDT 24
Peak memory 203672 kb
Host smart-2fc51039-6b7e-41e0-a537-a6998afddf32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=803500208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.803500208
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.163077932
Short name T1401
Test name
Test status
Simulation time 67928896 ps
CPU time 1.88 seconds
Started Apr 18 01:38:05 PM PDT 24
Finished Apr 18 01:38:10 PM PDT 24
Peak memory 203900 kb
Host smart-843ec008-6845-47c4-ac0c-32e17a6d17fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=163077932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.163077932
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2443133601
Short name T1388
Test name
Test status
Simulation time 32177320 ps
CPU time 0.63 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:03 PM PDT 24
Peak memory 202840 kb
Host smart-679e9a7d-7600-4c81-b051-e686432344ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2443133601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2443133601
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2134078467
Short name T270
Test name
Test status
Simulation time 36938601 ps
CPU time 0.63 seconds
Started Apr 18 01:38:05 PM PDT 24
Finished Apr 18 01:38:09 PM PDT 24
Peak memory 202924 kb
Host smart-5f37a663-8e00-450b-be9d-fec227ffe179
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2134078467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2134078467
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3708602468
Short name T266
Test name
Test status
Simulation time 35080965 ps
CPU time 0.68 seconds
Started Apr 18 01:38:06 PM PDT 24
Finished Apr 18 01:38:09 PM PDT 24
Peak memory 202832 kb
Host smart-3f636a7f-c25b-42a2-95e7-f235ac9cdeca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3708602468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3708602468
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.873835593
Short name T1408
Test name
Test status
Simulation time 46222261 ps
CPU time 0.69 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:02 PM PDT 24
Peak memory 202908 kb
Host smart-ce6c609e-298a-48bb-80d4-7781ed66ac9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=873835593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.873835593
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1212180324
Short name T1454
Test name
Test status
Simulation time 52644109 ps
CPU time 0.67 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:05 PM PDT 24
Peak memory 203004 kb
Host smart-bdf17d65-bfb3-48d2-8cec-97ba64e430dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1212180324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1212180324
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1013172978
Short name T1391
Test name
Test status
Simulation time 29784537 ps
CPU time 0.65 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:05 PM PDT 24
Peak memory 203092 kb
Host smart-409b90cb-3168-49cd-a572-46774e6b4ad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1013172978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.1013172978
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.404511099
Short name T1442
Test name
Test status
Simulation time 30848069 ps
CPU time 0.66 seconds
Started Apr 18 01:38:04 PM PDT 24
Finished Apr 18 01:38:07 PM PDT 24
Peak memory 202836 kb
Host smart-aedf9393-5b33-4b15-a5ce-e23110d37f7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=404511099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.404511099
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2991426925
Short name T1474
Test name
Test status
Simulation time 34553017 ps
CPU time 0.66 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:05 PM PDT 24
Peak memory 202976 kb
Host smart-eb869ab8-30e7-4a3d-bca3-91eff2247a8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2991426925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2991426925
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2048593088
Short name T1476
Test name
Test status
Simulation time 165868057 ps
CPU time 2.01 seconds
Started Apr 18 01:38:05 PM PDT 24
Finished Apr 18 01:38:13 PM PDT 24
Peak memory 203588 kb
Host smart-a3bf5584-0fdb-47e6-8718-1d6a30bde431
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2048593088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2048593088
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.388738702
Short name T235
Test name
Test status
Simulation time 1256326135 ps
CPU time 7.61 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:13 PM PDT 24
Peak memory 203576 kb
Host smart-be4b8df0-5072-4073-9766-030f8124bf5e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=388738702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.388738702
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2386332128
Short name T1473
Test name
Test status
Simulation time 88920207 ps
CPU time 0.93 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:04 PM PDT 24
Peak memory 203236 kb
Host smart-212d9209-2a1b-401a-b497-63f2871a40c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2386332128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2386332128
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1696598803
Short name T1405
Test name
Test status
Simulation time 74908152 ps
CPU time 1.85 seconds
Started Apr 18 01:37:59 PM PDT 24
Finished Apr 18 01:38:05 PM PDT 24
Peak memory 212020 kb
Host smart-6476bb19-99ac-4c4c-aacd-0a5e5f675d16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696598803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.1696598803
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.4233385112
Short name T256
Test name
Test status
Simulation time 70163986 ps
CPU time 1 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:02 PM PDT 24
Peak memory 203544 kb
Host smart-1eba96ce-c420-4d9c-8982-f1cc65598423
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4233385112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.4233385112
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.872531855
Short name T1450
Test name
Test status
Simulation time 35585600 ps
CPU time 0.7 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:02 PM PDT 24
Peak memory 202848 kb
Host smart-c65e2f93-79f9-4099-88ba-98d28246f73e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=872531855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.872531855
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1256301947
Short name T238
Test name
Test status
Simulation time 107117168 ps
CPU time 1.41 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:06 PM PDT 24
Peak memory 203608 kb
Host smart-28c93bb1-edae-48bf-916e-40f059276211
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1256301947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1256301947
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3582304921
Short name T1421
Test name
Test status
Simulation time 500332556 ps
CPU time 4.55 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:10 PM PDT 24
Peak memory 203516 kb
Host smart-481e8a3c-ac11-484d-a4ea-d3e8042399e5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3582304921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3582304921
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3492260435
Short name T1452
Test name
Test status
Simulation time 80930238 ps
CPU time 1.51 seconds
Started Apr 18 01:37:59 PM PDT 24
Finished Apr 18 01:38:02 PM PDT 24
Peak memory 203772 kb
Host smart-e13a1a84-f6d2-41a7-b7b7-9e904110f925
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3492260435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.3492260435
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.688402663
Short name T57
Test name
Test status
Simulation time 430491088 ps
CPU time 2.76 seconds
Started Apr 18 01:38:06 PM PDT 24
Finished Apr 18 01:38:11 PM PDT 24
Peak memory 203540 kb
Host smart-543522a2-c6e4-43d7-8b19-0c1326026a16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=688402663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.688402663
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2911530738
Short name T1424
Test name
Test status
Simulation time 33311817 ps
CPU time 0.71 seconds
Started Apr 18 01:37:58 PM PDT 24
Finished Apr 18 01:38:00 PM PDT 24
Peak memory 202952 kb
Host smart-186cf219-ae8e-4827-9baa-5be44fadddda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2911530738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.2911530738
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2884812704
Short name T1439
Test name
Test status
Simulation time 44591505 ps
CPU time 0.65 seconds
Started Apr 18 01:38:10 PM PDT 24
Finished Apr 18 01:38:11 PM PDT 24
Peak memory 202956 kb
Host smart-4f6f9193-3bf3-4736-bcd4-ada60dd7e729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2884812704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2884812704
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3046921543
Short name T259
Test name
Test status
Simulation time 35650256 ps
CPU time 0.63 seconds
Started Apr 18 01:38:05 PM PDT 24
Finished Apr 18 01:38:09 PM PDT 24
Peak memory 202976 kb
Host smart-3c3fb6b3-21a7-4002-9809-b5ac4a2dc224
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3046921543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3046921543
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1293099971
Short name T1435
Test name
Test status
Simulation time 44165204 ps
CPU time 0.65 seconds
Started Apr 18 01:38:21 PM PDT 24
Finished Apr 18 01:38:22 PM PDT 24
Peak memory 202908 kb
Host smart-5a6ce3ef-dedd-48f0-97e6-bbcb073d026f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1293099971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1293099971
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1520854240
Short name T1390
Test name
Test status
Simulation time 31573532 ps
CPU time 0.62 seconds
Started Apr 18 01:38:03 PM PDT 24
Finished Apr 18 01:38:06 PM PDT 24
Peak memory 202968 kb
Host smart-9d75e264-26cf-46f4-800f-0c468ad9e53f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1520854240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1520854240
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.176527371
Short name T1460
Test name
Test status
Simulation time 33009748 ps
CPU time 0.68 seconds
Started Apr 18 01:37:57 PM PDT 24
Finished Apr 18 01:37:58 PM PDT 24
Peak memory 203020 kb
Host smart-3f20ade7-0fc4-4bae-8251-ed64d88812f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=176527371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.176527371
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3357514387
Short name T66
Test name
Test status
Simulation time 30513485 ps
CPU time 0.62 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:06 PM PDT 24
Peak memory 202876 kb
Host smart-bfabdc3c-fb35-48d0-a470-27f60b1514d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3357514387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3357514387
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3423152067
Short name T261
Test name
Test status
Simulation time 60627443 ps
CPU time 0.65 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:06 PM PDT 24
Peak memory 202832 kb
Host smart-54e710cb-6747-4150-9a76-59cdfa6ee957
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3423152067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3423152067
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3601031796
Short name T1436
Test name
Test status
Simulation time 32997479 ps
CPU time 0.66 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:06 PM PDT 24
Peak memory 202936 kb
Host smart-0290a6e7-fc10-4af0-aa57-71693cf614ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3601031796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3601031796
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2500039556
Short name T234
Test name
Test status
Simulation time 388420498 ps
CPU time 3.62 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:09 PM PDT 24
Peak memory 203592 kb
Host smart-06330a24-204a-4a94-8e6b-f5faa585206a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2500039556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2500039556
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3557398254
Short name T255
Test name
Test status
Simulation time 1498371194 ps
CPU time 7.84 seconds
Started Apr 18 01:37:56 PM PDT 24
Finished Apr 18 01:38:04 PM PDT 24
Peak memory 203468 kb
Host smart-7efc40c9-f294-42e7-ad2d-7d4b24c1dfaa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3557398254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3557398254
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2577189024
Short name T63
Test name
Test status
Simulation time 123954874 ps
CPU time 0.92 seconds
Started Apr 18 01:37:57 PM PDT 24
Finished Apr 18 01:37:58 PM PDT 24
Peak memory 203460 kb
Host smart-5a493f47-cda7-4e60-8780-04ca9588166e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2577189024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2577189024
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2321607775
Short name T203
Test name
Test status
Simulation time 100713930 ps
CPU time 1.44 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:03 PM PDT 24
Peak memory 211976 kb
Host smart-15af58c9-e176-416c-8871-6daaa7904184
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321607775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.2321607775
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1178116138
Short name T1389
Test name
Test status
Simulation time 56810203 ps
CPU time 0.99 seconds
Started Apr 18 01:38:04 PM PDT 24
Finished Apr 18 01:38:08 PM PDT 24
Peak memory 203724 kb
Host smart-973fc4ba-1d2d-4d3e-9c0e-934ea0aa5ddc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1178116138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.1178116138
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1755773371
Short name T263
Test name
Test status
Simulation time 44193730 ps
CPU time 0.63 seconds
Started Apr 18 01:37:59 PM PDT 24
Finished Apr 18 01:38:00 PM PDT 24
Peak memory 202908 kb
Host smart-a710dc53-e513-4ddc-91f7-50280217167c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1755773371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1755773371
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3445128429
Short name T1456
Test name
Test status
Simulation time 75968513 ps
CPU time 2.16 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:06 PM PDT 24
Peak memory 211876 kb
Host smart-6cc57f83-e2e6-42a8-a87c-c5038b7bd12d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3445128429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3445128429
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3062822829
Short name T1384
Test name
Test status
Simulation time 283433455 ps
CPU time 2.51 seconds
Started Apr 18 01:37:59 PM PDT 24
Finished Apr 18 01:38:02 PM PDT 24
Peak memory 203548 kb
Host smart-f7e54a3e-1ddd-4daa-bc5d-6092cdb0474e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3062822829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.3062822829
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3282248996
Short name T1470
Test name
Test status
Simulation time 188374075 ps
CPU time 1.83 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:06 PM PDT 24
Peak memory 203796 kb
Host smart-6b59f841-67da-4987-97e6-259d4f02a32e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3282248996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.3282248996
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3905982304
Short name T1472
Test name
Test status
Simulation time 274577718 ps
CPU time 2.7 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:07 PM PDT 24
Peak memory 203868 kb
Host smart-13dd2da3-4eaa-4b8c-99a4-1b3e938bcdfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3905982304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3905982304
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2920951986
Short name T274
Test name
Test status
Simulation time 160870786 ps
CPU time 2.23 seconds
Started Apr 18 01:38:08 PM PDT 24
Finished Apr 18 01:38:12 PM PDT 24
Peak memory 203788 kb
Host smart-a3a8ea1a-c658-4714-92a2-3521166f751c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2920951986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2920951986
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3687873489
Short name T1468
Test name
Test status
Simulation time 40853354 ps
CPU time 0.67 seconds
Started Apr 18 01:38:05 PM PDT 24
Finished Apr 18 01:38:08 PM PDT 24
Peak memory 202892 kb
Host smart-6833d6df-e657-4adc-bc2a-e3001e169f14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3687873489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3687873489
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1414144190
Short name T271
Test name
Test status
Simulation time 41936474 ps
CPU time 0.68 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:09 PM PDT 24
Peak memory 202820 kb
Host smart-a2fa6f2e-dc81-448c-bd9c-3a9d8a6da5a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1414144190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1414144190
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2175214406
Short name T1419
Test name
Test status
Simulation time 33467507 ps
CPU time 0.64 seconds
Started Apr 18 01:38:03 PM PDT 24
Finished Apr 18 01:38:07 PM PDT 24
Peak memory 202860 kb
Host smart-41858027-e18d-452c-be8d-513ea9cf2824
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2175214406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2175214406
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1338835208
Short name T1463
Test name
Test status
Simulation time 47258441 ps
CPU time 0.63 seconds
Started Apr 18 01:38:04 PM PDT 24
Finished Apr 18 01:38:08 PM PDT 24
Peak memory 202952 kb
Host smart-fae1534f-07ad-459c-aee9-4a28cfa4957f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1338835208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.1338835208
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.4016134738
Short name T265
Test name
Test status
Simulation time 44261479 ps
CPU time 0.64 seconds
Started Apr 18 01:38:03 PM PDT 24
Finished Apr 18 01:38:07 PM PDT 24
Peak memory 202936 kb
Host smart-fd750a71-2de4-4efb-bd49-3d63459c378e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4016134738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.4016134738
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2600430113
Short name T69
Test name
Test status
Simulation time 35776959 ps
CPU time 0.62 seconds
Started Apr 18 01:38:04 PM PDT 24
Finished Apr 18 01:38:08 PM PDT 24
Peak memory 202948 kb
Host smart-891e1df3-944c-4c47-9723-11c8418a4dd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2600430113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2600430113
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2248769684
Short name T67
Test name
Test status
Simulation time 28389125 ps
CPU time 0.65 seconds
Started Apr 18 01:38:06 PM PDT 24
Finished Apr 18 01:38:09 PM PDT 24
Peak memory 202980 kb
Host smart-a85388f5-9843-4e3f-83ad-85c085b9b4bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2248769684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2248769684
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1621672709
Short name T1416
Test name
Test status
Simulation time 49075466 ps
CPU time 0.65 seconds
Started Apr 18 01:38:04 PM PDT 24
Finished Apr 18 01:38:08 PM PDT 24
Peak memory 202972 kb
Host smart-3e1714c9-6172-4c16-bd56-c389ee6a807c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1621672709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.1621672709
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3152159266
Short name T68
Test name
Test status
Simulation time 33316598 ps
CPU time 0.62 seconds
Started Apr 18 01:38:12 PM PDT 24
Finished Apr 18 01:38:13 PM PDT 24
Peak memory 202996 kb
Host smart-a2d54bda-f835-42c5-9043-643a0d364627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3152159266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3152159266
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.138969988
Short name T1399
Test name
Test status
Simulation time 40077395 ps
CPU time 0.64 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:06 PM PDT 24
Peak memory 202924 kb
Host smart-9a32dde2-3610-4fc5-8a18-91036ff2f4c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=138969988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.138969988
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2869766305
Short name T225
Test name
Test status
Simulation time 124298994 ps
CPU time 2.28 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:06 PM PDT 24
Peak memory 211944 kb
Host smart-0945edc9-56fd-4492-ad81-a2717a5fbfbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869766305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.2869766305
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1155100883
Short name T246
Test name
Test status
Simulation time 46113172 ps
CPU time 0.88 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:02 PM PDT 24
Peak memory 203696 kb
Host smart-3890bd4a-05ae-4d0b-b2ea-b49cd9ccf1ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1155100883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1155100883
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1114055505
Short name T1441
Test name
Test status
Simulation time 95263553 ps
CPU time 1.44 seconds
Started Apr 18 01:37:59 PM PDT 24
Finished Apr 18 01:38:01 PM PDT 24
Peak memory 203688 kb
Host smart-a1aba645-4bbb-402b-a5b4-2b369a037e92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1114055505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1114055505
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1638915421
Short name T206
Test name
Test status
Simulation time 230594967 ps
CPU time 2.32 seconds
Started Apr 18 01:38:07 PM PDT 24
Finished Apr 18 01:38:11 PM PDT 24
Peak memory 203672 kb
Host smart-b0cf8e66-abdb-4d72-a28d-c2955e48a7ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1638915421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1638915421
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2946218303
Short name T278
Test name
Test status
Simulation time 258602123 ps
CPU time 2.26 seconds
Started Apr 18 01:38:06 PM PDT 24
Finished Apr 18 01:38:11 PM PDT 24
Peak memory 203680 kb
Host smart-1874d1e3-34a8-43c4-a0ca-c5612b3a33d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2946218303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2946218303
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2672358633
Short name T242
Test name
Test status
Simulation time 84956071 ps
CPU time 1.03 seconds
Started Apr 18 01:37:58 PM PDT 24
Finished Apr 18 01:38:00 PM PDT 24
Peak memory 203712 kb
Host smart-6a4d948f-3a0f-4c27-9b8d-d5c3a80fabbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2672358633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2672358633
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.502021746
Short name T1396
Test name
Test status
Simulation time 40199838 ps
CPU time 0.63 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:04 PM PDT 24
Peak memory 202896 kb
Host smart-80207861-dd51-498c-833b-14456b8c5a46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=502021746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.502021746
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.549065615
Short name T1434
Test name
Test status
Simulation time 143540399 ps
CPU time 1.13 seconds
Started Apr 18 01:38:03 PM PDT 24
Finished Apr 18 01:38:07 PM PDT 24
Peak memory 203732 kb
Host smart-9c83f388-2060-4d0d-9c7f-a97616c24307
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=549065615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.549065615
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1123239065
Short name T1462
Test name
Test status
Simulation time 45080650 ps
CPU time 1.35 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:06 PM PDT 24
Peak memory 203724 kb
Host smart-dcf02b2b-ddd3-4a14-9bf2-4b265d1625be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1123239065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1123239065
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3981065074
Short name T226
Test name
Test status
Simulation time 612429478 ps
CPU time 2.95 seconds
Started Apr 18 01:38:07 PM PDT 24
Finished Apr 18 01:38:12 PM PDT 24
Peak memory 203604 kb
Host smart-24c14d3f-911b-4052-a447-b8ff984b5e4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3981065074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3981065074
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.13005937
Short name T1427
Test name
Test status
Simulation time 98050944 ps
CPU time 1.85 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:07 PM PDT 24
Peak memory 215080 kb
Host smart-d6973443-0ac6-48c0-95b6-aba46733b676
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13005937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_
csr_mem_rw_with_rand_reset.13005937
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1441103452
Short name T1478
Test name
Test status
Simulation time 41465989 ps
CPU time 0.9 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:06 PM PDT 24
Peak memory 203700 kb
Host smart-e9d6ddb6-b99c-408a-a434-33488da8de7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1441103452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1441103452
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.261036561
Short name T264
Test name
Test status
Simulation time 39693127 ps
CPU time 0.65 seconds
Started Apr 18 01:38:03 PM PDT 24
Finished Apr 18 01:38:07 PM PDT 24
Peak memory 202976 kb
Host smart-bf526499-855f-41c4-aa33-0abbd6cf7ca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=261036561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.261036561
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1600561182
Short name T1411
Test name
Test status
Simulation time 173248552 ps
CPU time 1.83 seconds
Started Apr 18 01:38:07 PM PDT 24
Finished Apr 18 01:38:11 PM PDT 24
Peak memory 203664 kb
Host smart-e2e76339-721a-4c66-a87a-ada8c08fb6b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1600561182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1600561182
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3720758263
Short name T204
Test name
Test status
Simulation time 63411459 ps
CPU time 1.57 seconds
Started Apr 18 01:38:10 PM PDT 24
Finished Apr 18 01:38:12 PM PDT 24
Peak memory 203776 kb
Host smart-e233b721-a1ec-40b1-9f11-2a5a35d19fb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3720758263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3720758263
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1287311115
Short name T1402
Test name
Test status
Simulation time 114060061 ps
CPU time 2.33 seconds
Started Apr 18 01:38:00 PM PDT 24
Finished Apr 18 01:38:04 PM PDT 24
Peak memory 212020 kb
Host smart-c248e4df-818e-4234-86c7-75dd5eb57c4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287311115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.1287311115
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.410742775
Short name T1444
Test name
Test status
Simulation time 30655411 ps
CPU time 0.73 seconds
Started Apr 18 01:38:07 PM PDT 24
Finished Apr 18 01:38:10 PM PDT 24
Peak memory 203388 kb
Host smart-004316a1-8e96-4ac5-9c0a-e0ca8a55084f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=410742775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.410742775
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2818073118
Short name T1418
Test name
Test status
Simulation time 37126982 ps
CPU time 0.64 seconds
Started Apr 18 01:38:03 PM PDT 24
Finished Apr 18 01:38:06 PM PDT 24
Peak memory 202904 kb
Host smart-7f1ad5ee-5bc8-4d96-b5fd-0a5d509320b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2818073118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2818073118
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3847308994
Short name T1461
Test name
Test status
Simulation time 134921076 ps
CPU time 1.31 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:05 PM PDT 24
Peak memory 203768 kb
Host smart-9e2526f7-2858-4abd-add5-8fcada93abc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3847308994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3847308994
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.18996796
Short name T1417
Test name
Test status
Simulation time 155968157 ps
CPU time 2.21 seconds
Started Apr 18 01:38:06 PM PDT 24
Finished Apr 18 01:38:11 PM PDT 24
Peak memory 203740 kb
Host smart-bff0db0b-2f57-42c9-ac48-c4411ee7837a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=18996796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.18996796
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3428897079
Short name T227
Test name
Test status
Simulation time 749939333 ps
CPU time 4.99 seconds
Started Apr 18 01:38:03 PM PDT 24
Finished Apr 18 01:38:11 PM PDT 24
Peak memory 203820 kb
Host smart-de292282-c267-417f-99cb-ba104faded7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3428897079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3428897079
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.869560341
Short name T197
Test name
Test status
Simulation time 73172339 ps
CPU time 1.8 seconds
Started Apr 18 01:38:06 PM PDT 24
Finished Apr 18 01:38:10 PM PDT 24
Peak memory 211852 kb
Host smart-ac0de8b6-31a9-416a-9231-e38f8db8a0cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869560341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev
_csr_mem_rw_with_rand_reset.869560341
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3531536611
Short name T1437
Test name
Test status
Simulation time 109319941 ps
CPU time 1.03 seconds
Started Apr 18 01:38:01 PM PDT 24
Finished Apr 18 01:38:05 PM PDT 24
Peak memory 203628 kb
Host smart-6b483875-ab92-417a-aa6f-4dd47d71211e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3531536611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.3531536611
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2319287513
Short name T65
Test name
Test status
Simulation time 35581329 ps
CPU time 0.66 seconds
Started Apr 18 01:38:07 PM PDT 24
Finished Apr 18 01:38:10 PM PDT 24
Peak memory 202848 kb
Host smart-5f65647e-7ade-4747-add6-a1bbd139e51f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2319287513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.2319287513
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3837599458
Short name T1407
Test name
Test status
Simulation time 97749704 ps
CPU time 1.46 seconds
Started Apr 18 01:37:57 PM PDT 24
Finished Apr 18 01:37:59 PM PDT 24
Peak memory 203756 kb
Host smart-66a28b8f-16a9-4ec2-8151-cec4bb4c3eb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3837599458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3837599458
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2997389706
Short name T1404
Test name
Test status
Simulation time 209472430 ps
CPU time 2.29 seconds
Started Apr 18 01:38:02 PM PDT 24
Finished Apr 18 01:38:07 PM PDT 24
Peak memory 203812 kb
Host smart-cd74354c-1217-423d-bf4d-ecface61849f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2997389706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2997389706
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3261920872
Short name T1471
Test name
Test status
Simulation time 650246629 ps
CPU time 2.89 seconds
Started Apr 18 01:37:59 PM PDT 24
Finished Apr 18 01:38:03 PM PDT 24
Peak memory 203800 kb
Host smart-fd6bdd01-c7d2-4491-8042-90c08111b286
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3261920872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3261920872
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.171543887
Short name T314
Test name
Test status
Simulation time 8466685973 ps
CPU time 8.46 seconds
Started Apr 18 01:13:23 PM PDT 24
Finished Apr 18 01:13:32 PM PDT 24
Peak memory 204048 kb
Host smart-3f857109-6407-4adf-89a0-6bb9ddc84523
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=171543887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.171543887
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.1820297110
Short name T355
Test name
Test status
Simulation time 8382124012 ps
CPU time 8.48 seconds
Started Apr 18 01:13:23 PM PDT 24
Finished Apr 18 01:13:32 PM PDT 24
Peak memory 204072 kb
Host smart-181a04fd-5008-4d1a-a74e-36cb1fc0c5b6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1820297110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.1820297110
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.1148739571
Short name T1332
Test name
Test status
Simulation time 8415204135 ps
CPU time 8.36 seconds
Started Apr 18 01:13:26 PM PDT 24
Finished Apr 18 01:13:34 PM PDT 24
Peak memory 204012 kb
Host smart-9c1d356c-1966-4a0f-af4c-0dd4bc9af357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11487
39571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.1148739571
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.728506927
Short name T331
Test name
Test status
Simulation time 8380336237 ps
CPU time 7.42 seconds
Started Apr 18 01:13:20 PM PDT 24
Finished Apr 18 01:13:28 PM PDT 24
Peak memory 204040 kb
Host smart-2c07c36d-4115-495c-8141-9967d6213cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72850
6927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.728506927
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_enable.2536638799
Short name T360
Test name
Test status
Simulation time 8427105480 ps
CPU time 8.82 seconds
Started Apr 18 01:13:21 PM PDT 24
Finished Apr 18 01:13:31 PM PDT 24
Peak memory 204044 kb
Host smart-24153f3b-6fd2-47a1-bdc3-780455176d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25366
38799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.2536638799
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.1581180889
Short name T1358
Test name
Test status
Simulation time 159285464 ps
CPU time 1.43 seconds
Started Apr 18 01:13:20 PM PDT 24
Finished Apr 18 01:13:22 PM PDT 24
Peak memory 204152 kb
Host smart-e26acf60-0446-4f14-b370-bb2c60608d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15811
80889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.1581180889
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.1463532649
Short name T142
Test name
Test status
Simulation time 8455614693 ps
CPU time 10.13 seconds
Started Apr 18 01:13:20 PM PDT 24
Finished Apr 18 01:13:31 PM PDT 24
Peak memory 203984 kb
Host smart-e87164e5-48ca-495d-b412-bab01ebf66c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14635
32649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.1463532649
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.1986019681
Short name T316
Test name
Test status
Simulation time 8400866567 ps
CPU time 7.71 seconds
Started Apr 18 01:13:20 PM PDT 24
Finished Apr 18 01:13:28 PM PDT 24
Peak memory 204012 kb
Host smart-aaf8d907-94ff-4efe-892b-5129edf8242a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19860
19681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.1986019681
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.1254235869
Short name T1371
Test name
Test status
Simulation time 8429520128 ps
CPU time 7.94 seconds
Started Apr 18 01:13:21 PM PDT 24
Finished Apr 18 01:13:30 PM PDT 24
Peak memory 204032 kb
Host smart-d5b99507-9ccd-4ac7-a9ad-4ee35ddffd4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12542
35869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.1254235869
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.391799032
Short name T1281
Test name
Test status
Simulation time 8380135815 ps
CPU time 8.02 seconds
Started Apr 18 01:13:20 PM PDT 24
Finished Apr 18 01:13:28 PM PDT 24
Peak memory 203960 kb
Host smart-1f2e3a6b-93b3-410a-b159-ca18adcce25e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39179
9032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.391799032
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.317641411
Short name T334
Test name
Test status
Simulation time 8373776133 ps
CPU time 8.28 seconds
Started Apr 18 01:13:22 PM PDT 24
Finished Apr 18 01:13:31 PM PDT 24
Peak memory 204020 kb
Host smart-aba93d38-a252-4de0-a04f-0401cc881faf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31764
1411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.317641411
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2283657078
Short name T283
Test name
Test status
Simulation time 8425606078 ps
CPU time 9.95 seconds
Started Apr 18 01:13:19 PM PDT 24
Finished Apr 18 01:13:30 PM PDT 24
Peak memory 204004 kb
Host smart-4064694a-16c2-4a4d-9d81-7a7868bdfc12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22836
57078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2283657078
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.3349070773
Short name T556
Test name
Test status
Simulation time 8409621661 ps
CPU time 9.04 seconds
Started Apr 18 01:13:22 PM PDT 24
Finished Apr 18 01:13:32 PM PDT 24
Peak memory 204004 kb
Host smart-ff071a17-6641-4937-af5a-db8bbdc7af6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33490
70773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.3349070773
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.283280121
Short name T44
Test name
Test status
Simulation time 72182724 ps
CPU time 0.67 seconds
Started Apr 18 01:13:19 PM PDT 24
Finished Apr 18 01:13:20 PM PDT 24
Peak memory 203868 kb
Host smart-62e6cb51-2201-4eb6-9548-c3b22ce56af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28328
0121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.283280121
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.1867164933
Short name T208
Test name
Test status
Simulation time 30987757566 ps
CPU time 58.57 seconds
Started Apr 18 01:13:23 PM PDT 24
Finished Apr 18 01:14:22 PM PDT 24
Peak memory 204364 kb
Host smart-549d7a96-8e22-4025-838a-2973edf69685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18671
64933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.1867164933
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.1410014363
Short name T1025
Test name
Test status
Simulation time 8379500810 ps
CPU time 8.29 seconds
Started Apr 18 01:13:23 PM PDT 24
Finished Apr 18 01:13:32 PM PDT 24
Peak memory 204044 kb
Host smart-ed94bc3e-0729-4844-9b37-7540e0564cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14100
14363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.1410014363
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.398851976
Short name T297
Test name
Test status
Simulation time 8416740707 ps
CPU time 7.88 seconds
Started Apr 18 01:13:25 PM PDT 24
Finished Apr 18 01:13:33 PM PDT 24
Peak memory 204016 kb
Host smart-981187d7-4dfe-4999-8e26-71112610ef0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39885
1976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.398851976
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.2476094862
Short name T153
Test name
Test status
Simulation time 8404043493 ps
CPU time 8.65 seconds
Started Apr 18 01:13:20 PM PDT 24
Finished Apr 18 01:13:29 PM PDT 24
Peak memory 203964 kb
Host smart-03411280-56f0-4571-947e-d0c4f0d1a196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24760
94862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2476094862
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.4184374440
Short name T776
Test name
Test status
Simulation time 8359093404 ps
CPU time 9.36 seconds
Started Apr 18 01:13:21 PM PDT 24
Finished Apr 18 01:13:31 PM PDT 24
Peak memory 204024 kb
Host smart-aced8bec-362e-4023-84ea-009dc0faf5bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41843
74440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.4184374440
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.993892705
Short name T413
Test name
Test status
Simulation time 8401317867 ps
CPU time 8.43 seconds
Started Apr 18 01:13:22 PM PDT 24
Finished Apr 18 01:13:31 PM PDT 24
Peak memory 204040 kb
Host smart-e9ff69fe-998d-4f13-98d9-76be4388b3ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99389
2705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.993892705
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.1356097980
Short name T1023
Test name
Test status
Simulation time 8382099820 ps
CPU time 8.23 seconds
Started Apr 18 01:13:23 PM PDT 24
Finished Apr 18 01:13:32 PM PDT 24
Peak memory 204036 kb
Host smart-ac66f0ce-e8ed-4f7e-ba5c-6751fe991e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13560
97980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.1356097980
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.3980361776
Short name T1242
Test name
Test status
Simulation time 8505557755 ps
CPU time 9.64 seconds
Started Apr 18 01:13:28 PM PDT 24
Finished Apr 18 01:13:38 PM PDT 24
Peak memory 203996 kb
Host smart-94cd53b8-2ebd-4692-b6ce-d767142b647e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3980361776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.3980361776
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.3814616616
Short name T370
Test name
Test status
Simulation time 8374381049 ps
CPU time 8.94 seconds
Started Apr 18 01:13:28 PM PDT 24
Finished Apr 18 01:13:37 PM PDT 24
Peak memory 204008 kb
Host smart-cad63524-98e1-4254-8ffb-45f793cb008d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3814616616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.3814616616
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.2977107832
Short name T389
Test name
Test status
Simulation time 8442807749 ps
CPU time 8.72 seconds
Started Apr 18 01:13:29 PM PDT 24
Finished Apr 18 01:13:38 PM PDT 24
Peak memory 204040 kb
Host smart-f8ce8f4e-e38b-4a1c-a6cb-2f73944acbe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29771
07832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.2977107832
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1583920800
Short name T662
Test name
Test status
Simulation time 8383181593 ps
CPU time 8.59 seconds
Started Apr 18 01:13:23 PM PDT 24
Finished Apr 18 01:13:32 PM PDT 24
Peak memory 204036 kb
Host smart-a9d3bb67-d2bf-4c2b-924f-1d89c3f3326c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15839
20800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1583920800
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_enable.4292393945
Short name T700
Test name
Test status
Simulation time 8392414861 ps
CPU time 7.61 seconds
Started Apr 18 01:13:22 PM PDT 24
Finished Apr 18 01:13:30 PM PDT 24
Peak memory 204032 kb
Host smart-a3f1649d-d3a0-4c9a-8833-d13a1e25d3c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42923
93945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.4292393945
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.94124695
Short name T835
Test name
Test status
Simulation time 274022363 ps
CPU time 1.95 seconds
Started Apr 18 01:13:21 PM PDT 24
Finished Apr 18 01:13:24 PM PDT 24
Peak memory 204120 kb
Host smart-979771ff-cdfd-43e0-865c-638004f718fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94124
695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.94124695
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.1842580933
Short name T184
Test name
Test status
Simulation time 8363658229 ps
CPU time 7.34 seconds
Started Apr 18 01:13:29 PM PDT 24
Finished Apr 18 01:13:36 PM PDT 24
Peak memory 203972 kb
Host smart-5344beac-eb69-49f5-96cd-862e214c03b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18425
80933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.1842580933
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.3892816984
Short name T454
Test name
Test status
Simulation time 8406935944 ps
CPU time 8.94 seconds
Started Apr 18 01:13:30 PM PDT 24
Finished Apr 18 01:13:39 PM PDT 24
Peak memory 204080 kb
Host smart-cd32b7f9-dbbe-445f-8676-9d01e0e8e717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38928
16984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.3892816984
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2491043275
Short name T741
Test name
Test status
Simulation time 8427273679 ps
CPU time 7.85 seconds
Started Apr 18 01:13:27 PM PDT 24
Finished Apr 18 01:13:36 PM PDT 24
Peak memory 203932 kb
Host smart-d3252afe-6cec-4df9-a8e2-f48d9dec4966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24910
43275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2491043275
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.4140096198
Short name T372
Test name
Test status
Simulation time 8370824899 ps
CPU time 7.55 seconds
Started Apr 18 01:13:30 PM PDT 24
Finished Apr 18 01:13:38 PM PDT 24
Peak memory 204044 kb
Host smart-605692cc-af22-42af-af52-55f3be7af7eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41400
96198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.4140096198
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.1248228815
Short name T865
Test name
Test status
Simulation time 8381675191 ps
CPU time 7.71 seconds
Started Apr 18 01:13:27 PM PDT 24
Finished Apr 18 01:13:35 PM PDT 24
Peak memory 203920 kb
Host smart-266ab2fc-ba06-41b8-b498-5548fb4427ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12482
28815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.1248228815
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.144676077
Short name T1169
Test name
Test status
Simulation time 8381466393 ps
CPU time 8.11 seconds
Started Apr 18 01:13:28 PM PDT 24
Finished Apr 18 01:13:36 PM PDT 24
Peak memory 204016 kb
Host smart-1ad313f1-5547-4a8f-b468-928c31cff602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14467
6077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.144676077
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.1382976987
Short name T636
Test name
Test status
Simulation time 8373922195 ps
CPU time 7.93 seconds
Started Apr 18 01:13:30 PM PDT 24
Finished Apr 18 01:13:38 PM PDT 24
Peak memory 204024 kb
Host smart-bf520120-4525-4815-9e97-c98e56cd8346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13829
76987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.1382976987
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.584165684
Short name T343
Test name
Test status
Simulation time 38413246 ps
CPU time 0.63 seconds
Started Apr 18 01:13:31 PM PDT 24
Finished Apr 18 01:13:32 PM PDT 24
Peak memory 203868 kb
Host smart-9691fe67-eef9-4144-be81-7284c5c72b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58416
5684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.584165684
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.3817007076
Short name T1246
Test name
Test status
Simulation time 29059003642 ps
CPU time 60.67 seconds
Started Apr 18 01:13:29 PM PDT 24
Finished Apr 18 01:14:30 PM PDT 24
Peak memory 204288 kb
Host smart-80673e9d-64e0-49a1-a35a-d37a0cddd93a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38170
07076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.3817007076
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.1072835285
Short name T514
Test name
Test status
Simulation time 8416470235 ps
CPU time 7.68 seconds
Started Apr 18 01:13:28 PM PDT 24
Finished Apr 18 01:13:36 PM PDT 24
Peak memory 204012 kb
Host smart-ba587a9a-891a-4110-8777-9fd7ceb49792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10728
35285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.1072835285
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.232828316
Short name T1189
Test name
Test status
Simulation time 8422954719 ps
CPU time 7.71 seconds
Started Apr 18 01:13:29 PM PDT 24
Finished Apr 18 01:13:37 PM PDT 24
Peak memory 204052 kb
Host smart-4ce40e6f-3e8d-4f39-839d-3754c7ca761d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23282
8316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.232828316
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.1064538018
Short name T746
Test name
Test status
Simulation time 8385616964 ps
CPU time 8 seconds
Started Apr 18 01:13:30 PM PDT 24
Finished Apr 18 01:13:38 PM PDT 24
Peak memory 204024 kb
Host smart-56df5177-f9c2-46fa-8ad5-3cbe4fbb813c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10645
38018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.1064538018
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.2797530411
Short name T70
Test name
Test status
Simulation time 635847382 ps
CPU time 1.43 seconds
Started Apr 18 01:13:37 PM PDT 24
Finished Apr 18 01:13:39 PM PDT 24
Peak memory 220140 kb
Host smart-a7b45d64-fdb3-4dd2-aa21-e294440812a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2797530411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2797530411
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.4184193810
Short name T168
Test name
Test status
Simulation time 8374983005 ps
CPU time 7.7 seconds
Started Apr 18 01:13:29 PM PDT 24
Finished Apr 18 01:13:37 PM PDT 24
Peak memory 204040 kb
Host smart-6aec853e-9bbd-42f6-9399-9b08fa023ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41841
93810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.4184193810
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.582263355
Short name T888
Test name
Test status
Simulation time 8366597021 ps
CPU time 8.7 seconds
Started Apr 18 01:13:35 PM PDT 24
Finished Apr 18 01:13:44 PM PDT 24
Peak memory 203940 kb
Host smart-66b6b156-aa86-4545-be0d-511ae1e9ec8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58226
3355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.582263355
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.779906298
Short name T1276
Test name
Test status
Simulation time 8435499003 ps
CPU time 8.65 seconds
Started Apr 18 01:13:20 PM PDT 24
Finished Apr 18 01:13:29 PM PDT 24
Peak memory 203964 kb
Host smart-0834b2cf-3eb8-4a49-a021-f07fc7622a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77990
6298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.779906298
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.2250375758
Short name T545
Test name
Test status
Simulation time 8390326385 ps
CPU time 7.99 seconds
Started Apr 18 01:13:29 PM PDT 24
Finished Apr 18 01:13:38 PM PDT 24
Peak memory 204036 kb
Host smart-46b58474-ab5a-40de-a766-75c3519f4b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22503
75758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.2250375758
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.3057243016
Short name T518
Test name
Test status
Simulation time 8393388503 ps
CPU time 7.87 seconds
Started Apr 18 01:13:27 PM PDT 24
Finished Apr 18 01:13:35 PM PDT 24
Peak memory 204032 kb
Host smart-ffd440bd-8e8e-4f94-bec0-364d5e8333cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30572
43016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.3057243016
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.3355814328
Short name T1093
Test name
Test status
Simulation time 8459290681 ps
CPU time 8.32 seconds
Started Apr 18 01:14:48 PM PDT 24
Finished Apr 18 01:14:57 PM PDT 24
Peak memory 204016 kb
Host smart-28b985fc-1e7e-43d8-9fa7-358c85c1580f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3355814328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.3355814328
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.1468586908
Short name T652
Test name
Test status
Simulation time 8379450229 ps
CPU time 8.68 seconds
Started Apr 18 01:14:42 PM PDT 24
Finished Apr 18 01:14:51 PM PDT 24
Peak memory 203900 kb
Host smart-c22abec5-5397-48bc-b2da-c1da30b26f0e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1468586908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.1468586908
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.3434178556
Short name T1179
Test name
Test status
Simulation time 8401235269 ps
CPU time 7.65 seconds
Started Apr 18 01:14:45 PM PDT 24
Finished Apr 18 01:14:53 PM PDT 24
Peak memory 204008 kb
Host smart-9e11977d-7f42-4716-a5d1-ef796364f213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34341
78556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.3434178556
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.1604353538
Short name T951
Test name
Test status
Simulation time 8374314758 ps
CPU time 8.33 seconds
Started Apr 18 01:14:43 PM PDT 24
Finished Apr 18 01:14:53 PM PDT 24
Peak memory 204084 kb
Host smart-e90e7282-4672-419f-a128-2ff6951d2311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16043
53538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.1604353538
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_enable.2659105735
Short name T527
Test name
Test status
Simulation time 8408684747 ps
CPU time 7.43 seconds
Started Apr 18 01:14:42 PM PDT 24
Finished Apr 18 01:14:50 PM PDT 24
Peak memory 204040 kb
Host smart-cb591bc7-e6b0-4bf4-bd8a-9c7171c861c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26591
05735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.2659105735
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.4188134865
Short name T760
Test name
Test status
Simulation time 140476532 ps
CPU time 1.41 seconds
Started Apr 18 01:14:43 PM PDT 24
Finished Apr 18 01:14:45 PM PDT 24
Peak memory 204148 kb
Host smart-dea5ed9e-db53-4eab-a2f7-e4ebf28205ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41881
34865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.4188134865
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.3682431916
Short name T569
Test name
Test status
Simulation time 8439133921 ps
CPU time 9.21 seconds
Started Apr 18 01:14:42 PM PDT 24
Finished Apr 18 01:14:52 PM PDT 24
Peak memory 204028 kb
Host smart-0efae510-b8f9-4e6f-9910-2e4fe25c958a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36824
31916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.3682431916
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.3169006172
Short name T1177
Test name
Test status
Simulation time 8370417463 ps
CPU time 9.24 seconds
Started Apr 18 01:14:46 PM PDT 24
Finished Apr 18 01:14:55 PM PDT 24
Peak memory 204044 kb
Host smart-60c15cf5-f130-4f2f-828a-bafbbc1935c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31690
06172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.3169006172
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.3983001903
Short name T1376
Test name
Test status
Simulation time 8453078133 ps
CPU time 8.41 seconds
Started Apr 18 01:14:45 PM PDT 24
Finished Apr 18 01:14:54 PM PDT 24
Peak memory 204024 kb
Host smart-8392ee2c-cdc4-44fc-9297-a4d5b7fb9e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39830
01903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3983001903
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.1200513092
Short name T563
Test name
Test status
Simulation time 8415326029 ps
CPU time 8.56 seconds
Started Apr 18 01:14:40 PM PDT 24
Finished Apr 18 01:14:49 PM PDT 24
Peak memory 204000 kb
Host smart-030f5855-ee14-436c-859b-745e7ef28b0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12005
13092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.1200513092
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.3620799536
Short name T1227
Test name
Test status
Simulation time 8375201783 ps
CPU time 8.04 seconds
Started Apr 18 01:14:42 PM PDT 24
Finished Apr 18 01:14:51 PM PDT 24
Peak memory 203948 kb
Host smart-05194b33-9a9d-4d09-ba21-c069b963f994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36207
99536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.3620799536
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.2233047254
Short name T977
Test name
Test status
Simulation time 8430132230 ps
CPU time 7.9 seconds
Started Apr 18 01:14:46 PM PDT 24
Finished Apr 18 01:14:54 PM PDT 24
Peak memory 204012 kb
Host smart-db0d231b-5a0c-46b5-b282-df9fe71eca3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22330
47254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2233047254
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.6472170
Short name T806
Test name
Test status
Simulation time 8429460852 ps
CPU time 8.57 seconds
Started Apr 18 01:14:40 PM PDT 24
Finished Apr 18 01:14:49 PM PDT 24
Peak memory 203944 kb
Host smart-813db6ac-dd8a-4342-8a2c-f78e76f92739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64721
70 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.6472170
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1186952265
Short name T1219
Test name
Test status
Simulation time 8417755339 ps
CPU time 9.77 seconds
Started Apr 18 01:14:43 PM PDT 24
Finished Apr 18 01:14:53 PM PDT 24
Peak memory 203996 kb
Host smart-0d6332a4-a8c2-41be-a7b8-c5fd5a8135e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11869
52265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1186952265
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.2747300989
Short name T75
Test name
Test status
Simulation time 8374307415 ps
CPU time 7.69 seconds
Started Apr 18 01:14:43 PM PDT 24
Finished Apr 18 01:14:51 PM PDT 24
Peak memory 204048 kb
Host smart-626c8d70-29dd-48f9-8ff0-3b89acf0f0f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27473
00989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.2747300989
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.3119196594
Short name T1044
Test name
Test status
Simulation time 30266985 ps
CPU time 0.63 seconds
Started Apr 18 01:14:49 PM PDT 24
Finished Apr 18 01:14:50 PM PDT 24
Peak memory 203884 kb
Host smart-c4d0a3c8-c162-4290-a7d4-b3e8490e5968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31191
96594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.3119196594
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.1284823693
Short name T1095
Test name
Test status
Simulation time 27172931638 ps
CPU time 51.87 seconds
Started Apr 18 01:14:41 PM PDT 24
Finished Apr 18 01:15:33 PM PDT 24
Peak memory 204288 kb
Host smart-7c7fd92b-b9f1-442c-8590-a5d8fdabf1bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12848
23693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.1284823693
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.2520716054
Short name T216
Test name
Test status
Simulation time 8416568392 ps
CPU time 7.85 seconds
Started Apr 18 01:14:41 PM PDT 24
Finished Apr 18 01:14:50 PM PDT 24
Peak memory 203996 kb
Host smart-d901e67c-3836-4e4c-9b62-6f46ce8f0b00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25207
16054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.2520716054
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.4177685459
Short name T144
Test name
Test status
Simulation time 8454629112 ps
CPU time 8.03 seconds
Started Apr 18 01:14:43 PM PDT 24
Finished Apr 18 01:14:51 PM PDT 24
Peak memory 204020 kb
Host smart-cb61fd1a-48e0-4075-8980-d8db38306884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41776
85459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.4177685459
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.2222650354
Short name T1275
Test name
Test status
Simulation time 8401777662 ps
CPU time 7.78 seconds
Started Apr 18 01:14:44 PM PDT 24
Finished Apr 18 01:14:52 PM PDT 24
Peak memory 203960 kb
Host smart-be1d4e54-d5d1-403b-89b0-db8b4237e1ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22226
50354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.2222650354
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.650757587
Short name T999
Test name
Test status
Simulation time 8376786871 ps
CPU time 8.29 seconds
Started Apr 18 01:14:42 PM PDT 24
Finished Apr 18 01:14:51 PM PDT 24
Peak memory 204036 kb
Host smart-2aae681f-0fb8-4afb-80db-4864d668a0b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65075
7587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.650757587
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1923518475
Short name T642
Test name
Test status
Simulation time 8370812179 ps
CPU time 7.32 seconds
Started Apr 18 01:14:43 PM PDT 24
Finished Apr 18 01:14:51 PM PDT 24
Peak memory 204000 kb
Host smart-15b0d6ae-14b4-4017-b3c8-397ca8925e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19235
18475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1923518475
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.168102889
Short name T804
Test name
Test status
Simulation time 8408972066 ps
CPU time 7.81 seconds
Started Apr 18 01:14:43 PM PDT 24
Finished Apr 18 01:14:51 PM PDT 24
Peak memory 203956 kb
Host smart-b6ca574d-f051-47a0-91c9-27305366486c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16810
2889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.168102889
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.3236915067
Short name T1228
Test name
Test status
Simulation time 8399569231 ps
CPU time 10.1 seconds
Started Apr 18 01:14:42 PM PDT 24
Finished Apr 18 01:14:53 PM PDT 24
Peak memory 203976 kb
Host smart-f6d8f926-f908-4978-b4f7-b7ed9e6a3881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32369
15067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.3236915067
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.3066998301
Short name T692
Test name
Test status
Simulation time 8470820599 ps
CPU time 8.08 seconds
Started Apr 18 01:14:48 PM PDT 24
Finished Apr 18 01:14:57 PM PDT 24
Peak memory 204032 kb
Host smart-3c00ec3e-330c-4ded-8626-4692d1ce0c02
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3066998301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.3066998301
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.1867236145
Short name T320
Test name
Test status
Simulation time 8377379546 ps
CPU time 7.74 seconds
Started Apr 18 01:14:48 PM PDT 24
Finished Apr 18 01:14:56 PM PDT 24
Peak memory 203948 kb
Host smart-f958e15f-cf12-4f06-9e45-4507ebcb7e58
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1867236145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.1867236145
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.3624256275
Short name T414
Test name
Test status
Simulation time 8466063605 ps
CPU time 10.15 seconds
Started Apr 18 01:14:50 PM PDT 24
Finished Apr 18 01:15:00 PM PDT 24
Peak memory 204040 kb
Host smart-afa30c83-0032-44a8-922b-49f288090782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36242
56275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.3624256275
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.1496997947
Short name T610
Test name
Test status
Simulation time 8380539409 ps
CPU time 8.38 seconds
Started Apr 18 01:14:48 PM PDT 24
Finished Apr 18 01:14:57 PM PDT 24
Peak memory 204252 kb
Host smart-accd416d-4a24-4c19-90b0-31e2155389bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14969
97947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.1496997947
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_enable.3964643477
Short name T495
Test name
Test status
Simulation time 8377890032 ps
CPU time 9.36 seconds
Started Apr 18 01:14:50 PM PDT 24
Finished Apr 18 01:15:00 PM PDT 24
Peak memory 203904 kb
Host smart-ab9e0bf8-b845-4d67-8781-1d6c61a5c698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39646
43477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3964643477
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.1096117156
Short name T382
Test name
Test status
Simulation time 67577706 ps
CPU time 1.58 seconds
Started Apr 18 01:14:49 PM PDT 24
Finished Apr 18 01:14:51 PM PDT 24
Peak memory 204112 kb
Host smart-3077ace0-1470-4ae1-9ec8-35164b3d4f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10961
17156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.1096117156
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.1194550504
Short name T442
Test name
Test status
Simulation time 8435192226 ps
CPU time 8.92 seconds
Started Apr 18 01:15:05 PM PDT 24
Finished Apr 18 01:15:14 PM PDT 24
Peak memory 204016 kb
Host smart-3ad4d953-2e20-41c6-9776-de9f06334b01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11945
50504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.1194550504
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.2967578647
Short name T446
Test name
Test status
Simulation time 8365671957 ps
CPU time 9.34 seconds
Started Apr 18 01:14:51 PM PDT 24
Finished Apr 18 01:15:01 PM PDT 24
Peak memory 203852 kb
Host smart-48774759-1c79-4b21-b2c3-d718c0968823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29675
78647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.2967578647
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.872616684
Short name T852
Test name
Test status
Simulation time 8417719442 ps
CPU time 8.65 seconds
Started Apr 18 01:14:50 PM PDT 24
Finished Apr 18 01:14:59 PM PDT 24
Peak memory 204004 kb
Host smart-d5f0539d-9b43-4730-8f8e-f0ef75e2e214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87261
6684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.872616684
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2317848469
Short name T433
Test name
Test status
Simulation time 8374909894 ps
CPU time 8.36 seconds
Started Apr 18 01:14:51 PM PDT 24
Finished Apr 18 01:15:00 PM PDT 24
Peak memory 204012 kb
Host smart-70ef7ce6-1384-48d5-a6fc-61442d92bce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23178
48469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2317848469
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1807579301
Short name T1024
Test name
Test status
Simulation time 8415059868 ps
CPU time 8.01 seconds
Started Apr 18 01:14:52 PM PDT 24
Finished Apr 18 01:15:01 PM PDT 24
Peak memory 203980 kb
Host smart-5d18d7eb-624e-476d-b66d-cfe213b1a423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18075
79301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1807579301
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1502043083
Short name T960
Test name
Test status
Simulation time 8383625260 ps
CPU time 7.93 seconds
Started Apr 18 01:14:51 PM PDT 24
Finished Apr 18 01:15:00 PM PDT 24
Peak memory 203984 kb
Host smart-711cc8a5-5803-4f88-b86b-1cfaed7c3eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15020
43083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1502043083
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.346374170
Short name T1245
Test name
Test status
Simulation time 8376805779 ps
CPU time 8.83 seconds
Started Apr 18 01:14:47 PM PDT 24
Finished Apr 18 01:14:57 PM PDT 24
Peak memory 204040 kb
Host smart-495bc4c4-8af7-4d6c-a713-ced5709d8e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34637
4170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.346374170
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.2164310017
Short name T1122
Test name
Test status
Simulation time 117786437 ps
CPU time 0.73 seconds
Started Apr 18 01:14:53 PM PDT 24
Finished Apr 18 01:14:55 PM PDT 24
Peak memory 203804 kb
Host smart-56024abe-884a-4fbd-bf45-4b6519d40811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21643
10017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.2164310017
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.3932482271
Short name T1347
Test name
Test status
Simulation time 8379172236 ps
CPU time 8.6 seconds
Started Apr 18 01:14:50 PM PDT 24
Finished Apr 18 01:15:00 PM PDT 24
Peak memory 204028 kb
Host smart-fa117cee-7c86-49f2-90be-2d918881af5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39324
82271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3932482271
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.1110219211
Short name T1058
Test name
Test status
Simulation time 8425732558 ps
CPU time 7.92 seconds
Started Apr 18 01:14:49 PM PDT 24
Finished Apr 18 01:14:58 PM PDT 24
Peak memory 204040 kb
Host smart-9b0d1037-3c6b-425e-822e-3f0a26d2c516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11102
19211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.1110219211
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.3799509595
Short name T19
Test name
Test status
Simulation time 8408725226 ps
CPU time 8.38 seconds
Started Apr 18 01:14:49 PM PDT 24
Finished Apr 18 01:14:58 PM PDT 24
Peak memory 204044 kb
Host smart-30100cf2-dc81-4bd9-b564-0e46f4ff7e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37995
09595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.3799509595
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1816252356
Short name T1040
Test name
Test status
Simulation time 8411776663 ps
CPU time 7.88 seconds
Started Apr 18 01:14:50 PM PDT 24
Finished Apr 18 01:14:59 PM PDT 24
Peak memory 203904 kb
Host smart-e7063c36-abd2-4145-9033-67f5f7521097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18162
52356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1816252356
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.1492559966
Short name T1252
Test name
Test status
Simulation time 8367640022 ps
CPU time 9.2 seconds
Started Apr 18 01:14:48 PM PDT 24
Finished Apr 18 01:14:58 PM PDT 24
Peak memory 203996 kb
Host smart-39ebe03d-da03-4578-8312-85b2d8ba404e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14925
59966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.1492559966
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.3792702879
Short name T407
Test name
Test status
Simulation time 8418947796 ps
CPU time 9.65 seconds
Started Apr 18 01:14:51 PM PDT 24
Finished Apr 18 01:15:01 PM PDT 24
Peak memory 204028 kb
Host smart-b5fe45ef-ed93-4889-b81d-5aeb280b44e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37927
02879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.3792702879
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.2730263589
Short name T299
Test name
Test status
Simulation time 8391327145 ps
CPU time 7.91 seconds
Started Apr 18 01:14:53 PM PDT 24
Finished Apr 18 01:15:02 PM PDT 24
Peak memory 203852 kb
Host smart-d4080149-8609-4803-ad94-7d445bfea4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27302
63589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.2730263589
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.1444875566
Short name T817
Test name
Test status
Simulation time 8373371299 ps
CPU time 7.82 seconds
Started Apr 18 01:14:46 PM PDT 24
Finished Apr 18 01:14:55 PM PDT 24
Peak memory 204036 kb
Host smart-ad7585c3-e127-4fc4-9cfd-9ce019de4053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14448
75566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.1444875566
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.1310852308
Short name T441
Test name
Test status
Simulation time 8513992013 ps
CPU time 10.54 seconds
Started Apr 18 01:14:55 PM PDT 24
Finished Apr 18 01:15:06 PM PDT 24
Peak memory 204040 kb
Host smart-456276e4-5ba9-44cb-83d7-356e606b810d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1310852308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.1310852308
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/12.min_length_in_transaction.3035748505
Short name T547
Test name
Test status
Simulation time 8377312270 ps
CPU time 8.81 seconds
Started Apr 18 01:14:55 PM PDT 24
Finished Apr 18 01:15:04 PM PDT 24
Peak memory 204052 kb
Host smart-3b7c6e5e-62d4-406f-bc09-c85217f47b59
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3035748505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.3035748505
Directory /workspace/12.min_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.3946465533
Short name T512
Test name
Test status
Simulation time 8447689683 ps
CPU time 9.85 seconds
Started Apr 18 01:14:58 PM PDT 24
Finished Apr 18 01:15:09 PM PDT 24
Peak memory 203300 kb
Host smart-056ec911-a292-40c2-aea0-58da97e2744a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39464
65533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.3946465533
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.3701806622
Short name T649
Test name
Test status
Simulation time 8394722934 ps
CPU time 7.65 seconds
Started Apr 18 01:14:58 PM PDT 24
Finished Apr 18 01:15:06 PM PDT 24
Peak memory 203764 kb
Host smart-01723d09-2c45-41c0-af64-7210842d2bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37018
06622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.3701806622
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_enable.56145440
Short name T889
Test name
Test status
Simulation time 8392421970 ps
CPU time 8.4 seconds
Started Apr 18 01:15:02 PM PDT 24
Finished Apr 18 01:15:11 PM PDT 24
Peak memory 204044 kb
Host smart-4cbc6216-e56b-420c-bb4e-2bcd5ec7b3cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56145
440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.56145440
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.3736501084
Short name T534
Test name
Test status
Simulation time 68321162 ps
CPU time 1.9 seconds
Started Apr 18 01:15:02 PM PDT 24
Finished Apr 18 01:15:04 PM PDT 24
Peak memory 204112 kb
Host smart-67b170eb-72ea-46f2-8643-666002b7a835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37365
01084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3736501084
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.822173416
Short name T785
Test name
Test status
Simulation time 8455443988 ps
CPU time 10.05 seconds
Started Apr 18 01:14:56 PM PDT 24
Finished Apr 18 01:15:08 PM PDT 24
Peak memory 203980 kb
Host smart-663b2523-e329-4552-970f-c2b248f3e8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82217
3416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.822173416
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.4163470172
Short name T189
Test name
Test status
Simulation time 8379707716 ps
CPU time 8.55 seconds
Started Apr 18 01:14:56 PM PDT 24
Finished Apr 18 01:15:06 PM PDT 24
Peak memory 203996 kb
Host smart-3db64f95-5535-4a2a-a9b1-a5dad0f3c2c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41634
70172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.4163470172
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.840928986
Short name T133
Test name
Test status
Simulation time 8389243070 ps
CPU time 10.01 seconds
Started Apr 18 01:14:56 PM PDT 24
Finished Apr 18 01:15:07 PM PDT 24
Peak memory 204028 kb
Host smart-45caf8db-7635-4d02-a9f2-29217eb02492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84092
8986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.840928986
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1376093574
Short name T671
Test name
Test status
Simulation time 8422898687 ps
CPU time 8.39 seconds
Started Apr 18 01:14:58 PM PDT 24
Finished Apr 18 01:15:07 PM PDT 24
Peak memory 203304 kb
Host smart-93c26ae3-4452-4145-83bd-b8c52ba36224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13760
93574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1376093574
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.711661471
Short name T326
Test name
Test status
Simulation time 8383767959 ps
CPU time 9 seconds
Started Apr 18 01:15:06 PM PDT 24
Finished Apr 18 01:15:15 PM PDT 24
Peak memory 203964 kb
Host smart-da746732-9c68-45b7-9775-c77eea2bb7f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71166
1471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.711661471
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.3469203649
Short name T670
Test name
Test status
Simulation time 8402127694 ps
CPU time 7.94 seconds
Started Apr 18 01:14:56 PM PDT 24
Finished Apr 18 01:15:05 PM PDT 24
Peak memory 203964 kb
Host smart-7a6a8d86-9095-439a-955f-fc76c0832a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34692
03649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.3469203649
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.1793605705
Short name T308
Test name
Test status
Simulation time 8387335230 ps
CPU time 7.8 seconds
Started Apr 18 01:14:59 PM PDT 24
Finished Apr 18 01:15:07 PM PDT 24
Peak memory 203304 kb
Host smart-99e100c7-38bc-46c9-b5e0-ed70e600e9e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17936
05705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.1793605705
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.2139887346
Short name T186
Test name
Test status
Simulation time 8375029281 ps
CPU time 9.67 seconds
Started Apr 18 01:14:56 PM PDT 24
Finished Apr 18 01:15:06 PM PDT 24
Peak memory 204036 kb
Host smart-4bf83190-6c1c-4d60-b9c7-c36dc24cfabf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21398
87346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.2139887346
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.3587176372
Short name T10
Test name
Test status
Simulation time 8373422154 ps
CPU time 7.7 seconds
Started Apr 18 01:14:57 PM PDT 24
Finished Apr 18 01:15:05 PM PDT 24
Peak memory 203300 kb
Host smart-fabbb075-1f37-4b2a-b68d-93e13adceb1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35871
76372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.3587176372
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.2302980740
Short name T1134
Test name
Test status
Simulation time 80887181 ps
CPU time 0.73 seconds
Started Apr 18 01:15:01 PM PDT 24
Finished Apr 18 01:15:02 PM PDT 24
Peak memory 203916 kb
Host smart-f321448f-885f-4d84-8106-fc8ae2efcc69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23029
80740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.2302980740
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.1791272951
Short name T753
Test name
Test status
Simulation time 22672130209 ps
CPU time 43.55 seconds
Started Apr 18 01:14:55 PM PDT 24
Finished Apr 18 01:15:40 PM PDT 24
Peak memory 204312 kb
Host smart-31c4b7fe-eb41-441b-a2c9-a3e46f822e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17912
72951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.1791272951
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.974556637
Short name T709
Test name
Test status
Simulation time 8414823256 ps
CPU time 7.54 seconds
Started Apr 18 01:15:00 PM PDT 24
Finished Apr 18 01:15:08 PM PDT 24
Peak memory 203924 kb
Host smart-aa8f4aa9-6c11-4741-ade1-84cfd9454487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97455
6637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.974556637
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.4132111013
Short name T1201
Test name
Test status
Simulation time 8409313899 ps
CPU time 10.54 seconds
Started Apr 18 01:14:57 PM PDT 24
Finished Apr 18 01:15:08 PM PDT 24
Peak memory 203904 kb
Host smart-aefc1ca9-9cd6-41e2-9a55-3bc3bdb909ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41321
11013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.4132111013
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.4187150371
Short name T358
Test name
Test status
Simulation time 8416566156 ps
CPU time 10.05 seconds
Started Apr 18 01:14:56 PM PDT 24
Finished Apr 18 01:15:07 PM PDT 24
Peak memory 203864 kb
Host smart-723a49c7-bbb1-4897-af16-20b47094dc68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41871
50371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.4187150371
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.2968803321
Short name T676
Test name
Test status
Simulation time 8384316188 ps
CPU time 8.58 seconds
Started Apr 18 01:14:59 PM PDT 24
Finished Apr 18 01:15:08 PM PDT 24
Peak memory 204012 kb
Host smart-e1ac7db4-ca3e-470b-b264-68c5a1d8183a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29688
03321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.2968803321
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3590787345
Short name T393
Test name
Test status
Simulation time 8375543730 ps
CPU time 7.39 seconds
Started Apr 18 01:14:55 PM PDT 24
Finished Apr 18 01:15:02 PM PDT 24
Peak memory 203960 kb
Host smart-b3bae450-2d1c-478b-92a1-8c43e4a75523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35907
87345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3590787345
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.2771529361
Short name T847
Test name
Test status
Simulation time 8405956103 ps
CPU time 7.93 seconds
Started Apr 18 01:14:54 PM PDT 24
Finished Apr 18 01:15:03 PM PDT 24
Peak memory 204040 kb
Host smart-5365f0a6-85cf-4d24-b1a1-a64fbd61d3d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27715
29361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.2771529361
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.2896795596
Short name T318
Test name
Test status
Simulation time 8391230076 ps
CPU time 7.79 seconds
Started Apr 18 01:14:54 PM PDT 24
Finished Apr 18 01:15:03 PM PDT 24
Peak memory 204004 kb
Host smart-4f01aae8-0f42-4525-9742-88ad79642432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28967
95596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2896795596
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.4081398505
Short name T1107
Test name
Test status
Simulation time 8479083405 ps
CPU time 8.48 seconds
Started Apr 18 01:15:08 PM PDT 24
Finished Apr 18 01:15:17 PM PDT 24
Peak memory 204016 kb
Host smart-589506e6-4d1e-4765-8994-2382a27a27a0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4081398505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.4081398505
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.3039422154
Short name T477
Test name
Test status
Simulation time 8391043056 ps
CPU time 7.47 seconds
Started Apr 18 01:15:08 PM PDT 24
Finished Apr 18 01:15:16 PM PDT 24
Peak memory 204016 kb
Host smart-2225609f-082b-46d3-a7e7-9cc14f7b82ed
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3039422154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.3039422154
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.1059887494
Short name T488
Test name
Test status
Simulation time 8467370944 ps
CPU time 10.02 seconds
Started Apr 18 01:15:08 PM PDT 24
Finished Apr 18 01:15:18 PM PDT 24
Peak memory 204020 kb
Host smart-1ef8a3ac-1288-4896-bb2c-a5013768f684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10598
87494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.1059887494
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.2911822152
Short name T988
Test name
Test status
Simulation time 8438033706 ps
CPU time 10.24 seconds
Started Apr 18 01:14:55 PM PDT 24
Finished Apr 18 01:15:06 PM PDT 24
Peak memory 204060 kb
Host smart-4a6781ee-7e22-4bcc-821c-663264d36d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29118
22152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.2911822152
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_enable.1585807164
Short name T373
Test name
Test status
Simulation time 8380587193 ps
CPU time 7.83 seconds
Started Apr 18 01:14:56 PM PDT 24
Finished Apr 18 01:15:05 PM PDT 24
Peak memory 204048 kb
Host smart-b4539b1e-1241-4bef-adf3-397ff99cb02d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15858
07164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.1585807164
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.837141146
Short name T1002
Test name
Test status
Simulation time 70474948 ps
CPU time 1.08 seconds
Started Apr 18 01:14:57 PM PDT 24
Finished Apr 18 01:14:59 PM PDT 24
Peak memory 204088 kb
Host smart-39410285-ac90-4fb3-b6a9-60abb6a61bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83714
1146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.837141146
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.1283314137
Short name T1269
Test name
Test status
Simulation time 8403651416 ps
CPU time 8.46 seconds
Started Apr 18 01:15:05 PM PDT 24
Finished Apr 18 01:15:14 PM PDT 24
Peak memory 204032 kb
Host smart-7f8127c8-325a-4f47-b014-ef35947cd77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12833
14137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.1283314137
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.2436387292
Short name T986
Test name
Test status
Simulation time 8381975549 ps
CPU time 10.52 seconds
Started Apr 18 01:15:04 PM PDT 24
Finished Apr 18 01:15:15 PM PDT 24
Peak memory 204004 kb
Host smart-2806fd75-5374-4193-ace3-e0d9e59ec23d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24363
87292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.2436387292
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.3215140401
Short name T1369
Test name
Test status
Simulation time 8447716346 ps
CPU time 8.73 seconds
Started Apr 18 01:14:55 PM PDT 24
Finished Apr 18 01:15:05 PM PDT 24
Peak memory 204004 kb
Host smart-0b7631fa-d67f-4001-9c20-6bcca9d686d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32151
40401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.3215140401
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3789911622
Short name T324
Test name
Test status
Simulation time 8415318700 ps
CPU time 8.12 seconds
Started Apr 18 01:14:57 PM PDT 24
Finished Apr 18 01:15:06 PM PDT 24
Peak memory 203980 kb
Host smart-ca7bd8c7-f839-4b2a-8c7a-bdd685f638e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37899
11622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3789911622
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.1751395169
Short name T1209
Test name
Test status
Simulation time 8377099286 ps
CPU time 8.66 seconds
Started Apr 18 01:15:08 PM PDT 24
Finished Apr 18 01:15:17 PM PDT 24
Peak memory 204028 kb
Host smart-aa2eb7ab-df68-4c87-8202-4d9fa55e8f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17513
95169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.1751395169
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.2978033805
Short name T1299
Test name
Test status
Simulation time 8399636898 ps
CPU time 9.57 seconds
Started Apr 18 01:15:04 PM PDT 24
Finished Apr 18 01:15:14 PM PDT 24
Peak memory 203928 kb
Host smart-03ccead8-a681-4438-a5fe-de564e22ebb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29780
33805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.2978033805
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.3292706730
Short name T612
Test name
Test status
Simulation time 8397453182 ps
CPU time 8.7 seconds
Started Apr 18 01:15:06 PM PDT 24
Finished Apr 18 01:15:15 PM PDT 24
Peak memory 204028 kb
Host smart-1cb06e5b-b439-447a-821c-22aa66ad199a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32927
06730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.3292706730
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.1544154188
Short name T86
Test name
Test status
Simulation time 8389835414 ps
CPU time 10.45 seconds
Started Apr 18 01:15:08 PM PDT 24
Finished Apr 18 01:15:19 PM PDT 24
Peak memory 204012 kb
Host smart-1e6f33a8-ff49-44da-86c9-fbd9ddc67351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15441
54188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.1544154188
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.2277410327
Short name T573
Test name
Test status
Simulation time 8389465081 ps
CPU time 7.63 seconds
Started Apr 18 01:15:03 PM PDT 24
Finished Apr 18 01:15:11 PM PDT 24
Peak memory 204016 kb
Host smart-26e1ce1a-f157-4e16-8f35-a7529a4c5e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22774
10327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.2277410327
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.4258017315
Short name T1103
Test name
Test status
Simulation time 104161951 ps
CPU time 0.72 seconds
Started Apr 18 01:15:07 PM PDT 24
Finished Apr 18 01:15:09 PM PDT 24
Peak memory 203852 kb
Host smart-9b2ce8f1-7a26-41ed-8305-9e41df94d5d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42580
17315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.4258017315
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.3112942072
Short name T229
Test name
Test status
Simulation time 24673583423 ps
CPU time 44.06 seconds
Started Apr 18 01:15:12 PM PDT 24
Finished Apr 18 01:15:56 PM PDT 24
Peak memory 204248 kb
Host smart-33b185e1-0551-4000-8636-732f96eccfb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31129
42072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.3112942072
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.2150968552
Short name T907
Test name
Test status
Simulation time 8377994915 ps
CPU time 9.5 seconds
Started Apr 18 01:15:05 PM PDT 24
Finished Apr 18 01:15:15 PM PDT 24
Peak memory 204084 kb
Host smart-d838b9b3-4c3a-49ff-8364-3ed7404c0c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21509
68552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2150968552
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.3318004927
Short name T1089
Test name
Test status
Simulation time 8461728657 ps
CPU time 8.14 seconds
Started Apr 18 01:15:01 PM PDT 24
Finished Apr 18 01:15:10 PM PDT 24
Peak memory 204052 kb
Host smart-1d98ac37-64e9-46c8-a560-1c0b2948547f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33180
04927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.3318004927
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.350685492
Short name T425
Test name
Test status
Simulation time 8376634922 ps
CPU time 8.93 seconds
Started Apr 18 01:15:05 PM PDT 24
Finished Apr 18 01:15:15 PM PDT 24
Peak memory 204032 kb
Host smart-40d57cb6-3b38-4bee-a372-fcf1ce0f366f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35068
5492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.350685492
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.2549015993
Short name T152
Test name
Test status
Simulation time 8387515092 ps
CPU time 8 seconds
Started Apr 18 01:15:04 PM PDT 24
Finished Apr 18 01:15:13 PM PDT 24
Peak memory 203972 kb
Host smart-88d6d88f-c6fe-4062-b560-ff0d22b6a748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25490
15993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.2549015993
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.1460386448
Short name T1341
Test name
Test status
Simulation time 8372813350 ps
CPU time 8.54 seconds
Started Apr 18 01:15:03 PM PDT 24
Finished Apr 18 01:15:12 PM PDT 24
Peak memory 204040 kb
Host smart-7fbebc2d-3da3-4fff-bdf3-2677e7e71ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14603
86448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.1460386448
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.2027315350
Short name T474
Test name
Test status
Simulation time 8421730712 ps
CPU time 8.26 seconds
Started Apr 18 01:14:56 PM PDT 24
Finished Apr 18 01:15:06 PM PDT 24
Peak memory 203976 kb
Host smart-039dec7c-f33b-4205-be19-298ff0b31a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20273
15350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.2027315350
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.279426554
Short name T793
Test name
Test status
Simulation time 8388740805 ps
CPU time 8.93 seconds
Started Apr 18 01:15:03 PM PDT 24
Finished Apr 18 01:15:12 PM PDT 24
Peak memory 203940 kb
Host smart-264daa50-01d9-4422-b6f1-0ed26161faed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27942
6554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.279426554
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.711420291
Short name T1190
Test name
Test status
Simulation time 8405787422 ps
CPU time 8.3 seconds
Started Apr 18 01:15:46 PM PDT 24
Finished Apr 18 01:15:55 PM PDT 24
Peak memory 204024 kb
Host smart-a9b9a7ce-0dd0-440c-8981-1ca45d872e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71142
0291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.711420291
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.max_length_in_transaction.4106534910
Short name T1127
Test name
Test status
Simulation time 8475680611 ps
CPU time 8.86 seconds
Started Apr 18 01:15:09 PM PDT 24
Finished Apr 18 01:15:19 PM PDT 24
Peak memory 204032 kb
Host smart-3b7fe535-9109-4c74-93cd-0fccbc4a60b8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4106534910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.4106534910
Directory /workspace/14.max_length_in_transaction/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.363109776
Short name T405
Test name
Test status
Simulation time 8391874211 ps
CPU time 8.58 seconds
Started Apr 18 01:15:10 PM PDT 24
Finished Apr 18 01:15:19 PM PDT 24
Peak memory 204248 kb
Host smart-0a718300-4186-4ef9-8fbd-c136d8ab753e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=363109776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.363109776
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.3028235253
Short name T1009
Test name
Test status
Simulation time 8445162644 ps
CPU time 8.32 seconds
Started Apr 18 01:15:11 PM PDT 24
Finished Apr 18 01:15:20 PM PDT 24
Peak memory 204028 kb
Host smart-c24980be-c34e-4a08-920c-d690efa70c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30282
35253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.3028235253
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.1478352163
Short name T913
Test name
Test status
Simulation time 8388940989 ps
CPU time 9.57 seconds
Started Apr 18 01:15:03 PM PDT 24
Finished Apr 18 01:15:13 PM PDT 24
Peak memory 203920 kb
Host smart-e830cf30-944e-4911-b06b-7eb919a8e971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14783
52163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.1478352163
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_enable.3256939393
Short name T20
Test name
Test status
Simulation time 8387462748 ps
CPU time 7.92 seconds
Started Apr 18 01:15:12 PM PDT 24
Finished Apr 18 01:15:20 PM PDT 24
Peak memory 203956 kb
Host smart-92df6a1c-9295-4938-8dd6-6e24ebeb7643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32569
39393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.3256939393
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.86916180
Short name T53
Test name
Test status
Simulation time 50843005 ps
CPU time 1.46 seconds
Started Apr 18 01:15:02 PM PDT 24
Finished Apr 18 01:15:04 PM PDT 24
Peak memory 204028 kb
Host smart-c09fa318-affa-4b03-b5c4-fcf55e0c51aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86916
180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.86916180
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.3974006949
Short name T140
Test name
Test status
Simulation time 8410821559 ps
CPU time 8.7 seconds
Started Apr 18 01:15:12 PM PDT 24
Finished Apr 18 01:15:22 PM PDT 24
Peak memory 203960 kb
Host smart-3c1fc426-503f-43ed-b5a3-db1de4dee09b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39740
06949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.3974006949
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.1451242252
Short name T1359
Test name
Test status
Simulation time 8413461811 ps
CPU time 8.31 seconds
Started Apr 18 01:15:04 PM PDT 24
Finished Apr 18 01:15:13 PM PDT 24
Peak memory 203940 kb
Host smart-c96bf0e9-b14b-480d-9a1d-dc0291fa7474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14512
42252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.1451242252
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.284882609
Short name T476
Test name
Test status
Simulation time 8387058603 ps
CPU time 9.74 seconds
Started Apr 18 01:15:09 PM PDT 24
Finished Apr 18 01:15:19 PM PDT 24
Peak memory 204024 kb
Host smart-408e2eaf-49f5-4dab-a063-6f7ee083d143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28488
2609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.284882609
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.3187137580
Short name T710
Test name
Test status
Simulation time 8405522146 ps
CPU time 8.38 seconds
Started Apr 18 01:15:11 PM PDT 24
Finished Apr 18 01:15:20 PM PDT 24
Peak memory 203960 kb
Host smart-d8713245-6e85-4e9c-8f6d-fbd02500e561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31871
37580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.3187137580
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.1233614395
Short name T467
Test name
Test status
Simulation time 8425162746 ps
CPU time 9.06 seconds
Started Apr 18 01:15:03 PM PDT 24
Finished Apr 18 01:15:13 PM PDT 24
Peak memory 204044 kb
Host smart-770b2505-3feb-44b4-9373-5280a4fdbfd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12336
14395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.1233614395
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.3803509243
Short name T422
Test name
Test status
Simulation time 8397742499 ps
CPU time 7.88 seconds
Started Apr 18 01:15:11 PM PDT 24
Finished Apr 18 01:15:19 PM PDT 24
Peak memory 203960 kb
Host smart-d0dbaeb4-9251-41e3-a877-9fb86de02724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38035
09243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.3803509243
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3389535282
Short name T1068
Test name
Test status
Simulation time 104622734 ps
CPU time 0.74 seconds
Started Apr 18 01:15:13 PM PDT 24
Finished Apr 18 01:15:14 PM PDT 24
Peak memory 203872 kb
Host smart-3d3d83d0-c405-43aa-90d8-9d4f4d67bbfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33895
35282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3389535282
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.1814077804
Short name T1000
Test name
Test status
Simulation time 30481119237 ps
CPU time 61.69 seconds
Started Apr 18 01:15:10 PM PDT 24
Finished Apr 18 01:16:13 PM PDT 24
Peak memory 204248 kb
Host smart-f7accb6a-d80d-4be6-8674-0fc6a710963a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18140
77804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.1814077804
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.653426218
Short name T603
Test name
Test status
Simulation time 8394726167 ps
CPU time 10.03 seconds
Started Apr 18 01:15:10 PM PDT 24
Finished Apr 18 01:15:21 PM PDT 24
Peak memory 204008 kb
Host smart-acb103aa-997b-4198-a548-241f529dd9e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65342
6218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.653426218
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.2321249833
Short name T598
Test name
Test status
Simulation time 8386242204 ps
CPU time 8.5 seconds
Started Apr 18 01:15:07 PM PDT 24
Finished Apr 18 01:15:16 PM PDT 24
Peak memory 203904 kb
Host smart-a37a324d-3c24-40dd-a9be-187d559763ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23212
49833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.2321249833
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.1030982195
Short name T1164
Test name
Test status
Simulation time 8436936776 ps
CPU time 8.24 seconds
Started Apr 18 01:15:04 PM PDT 24
Finished Apr 18 01:15:13 PM PDT 24
Peak memory 204040 kb
Host smart-fb779e69-7e75-4bd8-b779-0cfd4d7b023e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10309
82195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.1030982195
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.497679835
Short name T158
Test name
Test status
Simulation time 8377785667 ps
CPU time 7.23 seconds
Started Apr 18 01:15:14 PM PDT 24
Finished Apr 18 01:15:21 PM PDT 24
Peak memory 204040 kb
Host smart-45a3a4cc-1ef2-4edf-9057-15a055227682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49767
9835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.497679835
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.2614625064
Short name T1307
Test name
Test status
Simulation time 8386784058 ps
CPU time 9.81 seconds
Started Apr 18 01:15:05 PM PDT 24
Finished Apr 18 01:15:16 PM PDT 24
Peak memory 204020 kb
Host smart-8fe6bc33-3bbf-4fcc-8ce5-48d87248d335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26146
25064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.2614625064
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.1876634404
Short name T124
Test name
Test status
Simulation time 8451856476 ps
CPU time 9.41 seconds
Started Apr 18 01:15:04 PM PDT 24
Finished Apr 18 01:15:14 PM PDT 24
Peak memory 204012 kb
Host smart-869f5f3f-2613-4f2d-9912-e3e280ed5d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18766
34404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1876634404
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2038358137
Short name T466
Test name
Test status
Simulation time 8406221678 ps
CPU time 9.01 seconds
Started Apr 18 01:15:04 PM PDT 24
Finished Apr 18 01:15:14 PM PDT 24
Peak memory 203992 kb
Host smart-1c39c04e-497e-4bd1-aafa-2c86808c58d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20383
58137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2038358137
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.2635049329
Short name T644
Test name
Test status
Simulation time 8412239944 ps
CPU time 7.78 seconds
Started Apr 18 01:15:16 PM PDT 24
Finished Apr 18 01:15:24 PM PDT 24
Peak memory 204080 kb
Host smart-ecea1687-102b-4d0e-8e91-b0814c5781c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26350
49329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.2635049329
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.2909560548
Short name T11
Test name
Test status
Simulation time 8538924516 ps
CPU time 10.08 seconds
Started Apr 18 01:15:13 PM PDT 24
Finished Apr 18 01:15:24 PM PDT 24
Peak memory 204012 kb
Host smart-b56e2e84-2cba-41ee-8c76-34a635cb0cbb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2909560548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.2909560548
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.724417006
Short name T1121
Test name
Test status
Simulation time 8379378785 ps
CPU time 7.97 seconds
Started Apr 18 01:15:11 PM PDT 24
Finished Apr 18 01:15:20 PM PDT 24
Peak memory 203908 kb
Host smart-ca28806a-3b19-4e52-8732-b820cdca51f9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=724417006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.724417006
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.3698841649
Short name T690
Test name
Test status
Simulation time 8463216360 ps
CPU time 8.66 seconds
Started Apr 18 01:15:12 PM PDT 24
Finished Apr 18 01:15:22 PM PDT 24
Peak memory 203908 kb
Host smart-e0ee7176-dbb3-4c0f-8572-f6cb35825924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36988
41649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.3698841649
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.530894519
Short name T78
Test name
Test status
Simulation time 8372836669 ps
CPU time 8.65 seconds
Started Apr 18 01:15:11 PM PDT 24
Finished Apr 18 01:15:20 PM PDT 24
Peak memory 203968 kb
Host smart-5416619d-624e-4930-ba4a-af3dd7c8aedf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53089
4519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.530894519
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_enable.2880221300
Short name T810
Test name
Test status
Simulation time 8431594313 ps
CPU time 8.4 seconds
Started Apr 18 01:15:12 PM PDT 24
Finished Apr 18 01:15:21 PM PDT 24
Peak memory 204048 kb
Host smart-512d5872-0374-49b7-8007-e85b975152de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28802
21300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.2880221300
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.3522108434
Short name T469
Test name
Test status
Simulation time 67335947 ps
CPU time 1.63 seconds
Started Apr 18 01:15:10 PM PDT 24
Finished Apr 18 01:15:13 PM PDT 24
Peak memory 204008 kb
Host smart-1e34e997-cadf-43d3-83a1-a55b6e4155a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35221
08434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.3522108434
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.3247909638
Short name T802
Test name
Test status
Simulation time 8445777868 ps
CPU time 10.24 seconds
Started Apr 18 01:15:09 PM PDT 24
Finished Apr 18 01:15:20 PM PDT 24
Peak memory 204036 kb
Host smart-17a5db54-c892-4e7f-9286-b35c87ad053c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32479
09638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.3247909638
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.1501785933
Short name T323
Test name
Test status
Simulation time 8367567863 ps
CPU time 7.84 seconds
Started Apr 18 01:15:11 PM PDT 24
Finished Apr 18 01:15:19 PM PDT 24
Peak memory 203896 kb
Host smart-31c9ba6d-9425-4550-a310-4cd744d291b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15017
85933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.1501785933
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.2638988737
Short name T1011
Test name
Test status
Simulation time 8458666100 ps
CPU time 9.58 seconds
Started Apr 18 01:15:12 PM PDT 24
Finished Apr 18 01:15:22 PM PDT 24
Peak memory 203944 kb
Host smart-bc54d1c0-592a-43db-a77e-89901902ccca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26389
88737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.2638988737
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.2162129100
Short name T1191
Test name
Test status
Simulation time 8460127394 ps
CPU time 8.73 seconds
Started Apr 18 01:15:12 PM PDT 24
Finished Apr 18 01:15:21 PM PDT 24
Peak memory 204044 kb
Host smart-628edbc2-84a5-4270-9a47-e75cb0655080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21621
29100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.2162129100
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.1095627794
Short name T1214
Test name
Test status
Simulation time 8381751372 ps
CPU time 7.69 seconds
Started Apr 18 01:15:10 PM PDT 24
Finished Apr 18 01:15:18 PM PDT 24
Peak memory 203988 kb
Host smart-42139849-eee2-4685-aca6-43c968f6a24b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10956
27794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.1095627794
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.3052001080
Short name T798
Test name
Test status
Simulation time 8402209376 ps
CPU time 8.39 seconds
Started Apr 18 01:15:12 PM PDT 24
Finished Apr 18 01:15:21 PM PDT 24
Peak memory 204052 kb
Host smart-04bb2280-1930-4b9c-bb05-cafd15f6d9ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30520
01080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.3052001080
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.832105734
Short name T295
Test name
Test status
Simulation time 8411501046 ps
CPU time 7.73 seconds
Started Apr 18 01:15:09 PM PDT 24
Finished Apr 18 01:15:18 PM PDT 24
Peak memory 204080 kb
Host smart-04f0f611-ebf0-4b0c-9e2e-3addac3a8aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83210
5734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.832105734
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.707206494
Short name T549
Test name
Test status
Simulation time 8371161442 ps
CPU time 7.65 seconds
Started Apr 18 01:15:16 PM PDT 24
Finished Apr 18 01:15:24 PM PDT 24
Peak memory 204084 kb
Host smart-ade29b65-d15b-4519-a9ab-234ac38e3140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70720
6494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.707206494
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.1631582348
Short name T500
Test name
Test status
Simulation time 151335026 ps
CPU time 0.73 seconds
Started Apr 18 01:15:10 PM PDT 24
Finished Apr 18 01:15:11 PM PDT 24
Peak memory 203812 kb
Host smart-a91cec4a-69e3-49fd-b175-f5c259552fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16315
82348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.1631582348
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.2979405858
Short name T931
Test name
Test status
Simulation time 22339207874 ps
CPU time 38.8 seconds
Started Apr 18 01:15:11 PM PDT 24
Finished Apr 18 01:15:50 PM PDT 24
Peak memory 204244 kb
Host smart-4dd78e18-11b9-4f0a-a62f-7e1d248e2e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29794
05858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.2979405858
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.339402110
Short name T958
Test name
Test status
Simulation time 8409714836 ps
CPU time 7.87 seconds
Started Apr 18 01:15:09 PM PDT 24
Finished Apr 18 01:15:17 PM PDT 24
Peak memory 204040 kb
Host smart-cdb915dd-4f08-44a5-a988-e0c46184118f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33940
2110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.339402110
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.1982102739
Short name T1178
Test name
Test status
Simulation time 8434123214 ps
CPU time 7.6 seconds
Started Apr 18 01:15:13 PM PDT 24
Finished Apr 18 01:15:22 PM PDT 24
Peak memory 204044 kb
Host smart-c6b5616e-2140-44ac-ab75-f0a03d7b5491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19821
02739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.1982102739
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.2176852775
Short name T503
Test name
Test status
Simulation time 8410761638 ps
CPU time 8.19 seconds
Started Apr 18 01:15:13 PM PDT 24
Finished Apr 18 01:15:22 PM PDT 24
Peak memory 204012 kb
Host smart-1f426e3a-1988-4b84-bcd1-eceebd6bcc32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21768
52775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.2176852775
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.3257653674
Short name T592
Test name
Test status
Simulation time 8378296661 ps
CPU time 7.84 seconds
Started Apr 18 01:15:14 PM PDT 24
Finished Apr 18 01:15:22 PM PDT 24
Peak memory 204012 kb
Host smart-33eafcb8-2c93-4177-a693-2dae346627e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32576
53674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.3257653674
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.375567065
Short name T1088
Test name
Test status
Simulation time 8437108601 ps
CPU time 7.81 seconds
Started Apr 18 01:15:11 PM PDT 24
Finished Apr 18 01:15:19 PM PDT 24
Peak memory 204040 kb
Host smart-b644246d-e760-481c-9dcd-559dd688255b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37556
7065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.375567065
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3980581662
Short name T1181
Test name
Test status
Simulation time 8448484572 ps
CPU time 9.21 seconds
Started Apr 18 01:15:11 PM PDT 24
Finished Apr 18 01:15:21 PM PDT 24
Peak memory 204004 kb
Host smart-bd7d8b9f-18c4-40a9-be24-2c9bbc0604d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39805
81662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3980581662
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.3033569617
Short name T858
Test name
Test status
Simulation time 8388508137 ps
CPU time 7.96 seconds
Started Apr 18 01:15:09 PM PDT 24
Finished Apr 18 01:15:18 PM PDT 24
Peak memory 204028 kb
Host smart-2cf10992-fcfc-410a-a1d2-c497ad3b3d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30335
69617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.3033569617
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.3883853473
Short name T306
Test name
Test status
Simulation time 8395411884 ps
CPU time 7.67 seconds
Started Apr 18 01:15:13 PM PDT 24
Finished Apr 18 01:15:21 PM PDT 24
Peak memory 203964 kb
Host smart-8c92efc0-dfab-41ff-b117-b4ee790a7b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38838
53473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.3883853473
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.3493716961
Short name T1306
Test name
Test status
Simulation time 8462099247 ps
CPU time 8 seconds
Started Apr 18 01:15:22 PM PDT 24
Finished Apr 18 01:15:31 PM PDT 24
Peak memory 203980 kb
Host smart-ade7aa88-3c84-474a-9503-84159543c751
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3493716961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.3493716961
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.min_length_in_transaction.2937594634
Short name T1087
Test name
Test status
Simulation time 8420854484 ps
CPU time 8.78 seconds
Started Apr 18 01:15:19 PM PDT 24
Finished Apr 18 01:15:29 PM PDT 24
Peak memory 203944 kb
Host smart-33d31b34-8aa7-44a0-8fab-ecf9ca08f15b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2937594634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.2937594634
Directory /workspace/16.min_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.596709139
Short name T1232
Test name
Test status
Simulation time 8459301737 ps
CPU time 7.78 seconds
Started Apr 18 01:15:16 PM PDT 24
Finished Apr 18 01:15:24 PM PDT 24
Peak memory 204000 kb
Host smart-dc391719-a189-4c29-90fa-cca26d99d3e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59670
9139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.596709139
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.1189502494
Short name T995
Test name
Test status
Simulation time 8382309434 ps
CPU time 7.73 seconds
Started Apr 18 01:15:20 PM PDT 24
Finished Apr 18 01:15:28 PM PDT 24
Peak memory 204024 kb
Host smart-57fabf39-14e3-4683-b381-4666607fd525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11895
02494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.1189502494
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_enable.3229899110
Short name T493
Test name
Test status
Simulation time 8381224607 ps
CPU time 8.63 seconds
Started Apr 18 01:15:24 PM PDT 24
Finished Apr 18 01:15:33 PM PDT 24
Peak memory 203996 kb
Host smart-40cf5966-d98c-4fbd-b47d-7568390e8196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32298
99110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.3229899110
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3560758969
Short name T1368
Test name
Test status
Simulation time 85289392 ps
CPU time 1.62 seconds
Started Apr 18 01:15:20 PM PDT 24
Finished Apr 18 01:15:22 PM PDT 24
Peak memory 204108 kb
Host smart-7f6866bd-ab59-47e1-a9b1-2102c48b11a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35607
58969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3560758969
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3122239418
Short name T1148
Test name
Test status
Simulation time 8464477049 ps
CPU time 8.45 seconds
Started Apr 18 01:15:20 PM PDT 24
Finished Apr 18 01:15:29 PM PDT 24
Peak memory 204016 kb
Host smart-e9bf0cf5-5b1a-4198-9e85-2b19d23c8b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31222
39418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3122239418
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.2355638406
Short name T721
Test name
Test status
Simulation time 8366576983 ps
CPU time 7.99 seconds
Started Apr 18 01:15:19 PM PDT 24
Finished Apr 18 01:15:28 PM PDT 24
Peak memory 204024 kb
Host smart-de97bba8-9a3d-46d8-8bbb-78c1ad6b374e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23556
38406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.2355638406
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.1187900488
Short name T397
Test name
Test status
Simulation time 8417338109 ps
CPU time 7.58 seconds
Started Apr 18 01:15:19 PM PDT 24
Finished Apr 18 01:15:28 PM PDT 24
Peak memory 204032 kb
Host smart-f72c5543-768b-4365-8e96-33bf83465626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11879
00488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.1187900488
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.114929613
Short name T31
Test name
Test status
Simulation time 8411334721 ps
CPU time 8.3 seconds
Started Apr 18 01:15:19 PM PDT 24
Finished Apr 18 01:15:28 PM PDT 24
Peak memory 204064 kb
Host smart-32883d0f-73a8-49dd-984e-dc67243a256e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11492
9613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.114929613
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.2425149168
Short name T681
Test name
Test status
Simulation time 8370156107 ps
CPU time 7.49 seconds
Started Apr 18 01:15:20 PM PDT 24
Finished Apr 18 01:15:28 PM PDT 24
Peak memory 204028 kb
Host smart-cbd3415e-1a89-4173-8e4b-e4c992305746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24251
49168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.2425149168
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.570852244
Short name T1035
Test name
Test status
Simulation time 8381285615 ps
CPU time 8.21 seconds
Started Apr 18 01:15:18 PM PDT 24
Finished Apr 18 01:15:27 PM PDT 24
Peak memory 203992 kb
Host smart-e09e5c78-e8cb-4eb8-ab8d-82f1682e641d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57085
2244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.570852244
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2801466328
Short name T949
Test name
Test status
Simulation time 8374860566 ps
CPU time 9.08 seconds
Started Apr 18 01:15:17 PM PDT 24
Finished Apr 18 01:15:27 PM PDT 24
Peak memory 203968 kb
Host smart-ef466948-41e0-4da2-aae0-67057488d014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28014
66328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2801466328
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.2773504510
Short name T438
Test name
Test status
Simulation time 8369230676 ps
CPU time 8.44 seconds
Started Apr 18 01:15:20 PM PDT 24
Finished Apr 18 01:15:29 PM PDT 24
Peak memory 204012 kb
Host smart-b463f979-1da7-435f-bff0-a6dad218dfdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27735
04510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.2773504510
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.4149651985
Short name T1123
Test name
Test status
Simulation time 44418137 ps
CPU time 0.67 seconds
Started Apr 18 01:15:18 PM PDT 24
Finished Apr 18 01:15:20 PM PDT 24
Peak memory 203820 kb
Host smart-47bf521e-ea5e-41b8-9224-92b46cfb856b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41496
51985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.4149651985
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.3987621119
Short name T646
Test name
Test status
Simulation time 19031409415 ps
CPU time 34.06 seconds
Started Apr 18 01:15:19 PM PDT 24
Finished Apr 18 01:15:54 PM PDT 24
Peak memory 204312 kb
Host smart-ab64f443-d27c-41c1-821b-39ea99d65be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39876
21119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.3987621119
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.357293226
Short name T289
Test name
Test status
Simulation time 8404147061 ps
CPU time 8.03 seconds
Started Apr 18 01:15:18 PM PDT 24
Finished Apr 18 01:15:27 PM PDT 24
Peak memory 204036 kb
Host smart-d60602d1-219a-4505-ae9d-f9d10d1beff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35729
3226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.357293226
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.1568522193
Short name T846
Test name
Test status
Simulation time 8407948441 ps
CPU time 9.95 seconds
Started Apr 18 01:15:17 PM PDT 24
Finished Apr 18 01:15:28 PM PDT 24
Peak memory 204008 kb
Host smart-cf4e4fb0-86db-486e-92f6-2d2d492b2b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15685
22193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.1568522193
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.3367220052
Short name T989
Test name
Test status
Simulation time 8392271294 ps
CPU time 8.46 seconds
Started Apr 18 01:15:17 PM PDT 24
Finished Apr 18 01:15:26 PM PDT 24
Peak memory 204024 kb
Host smart-ef891460-6568-4746-a8e5-32a84e6faf1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33672
20052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.3367220052
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.2580547803
Short name T161
Test name
Test status
Simulation time 8386587703 ps
CPU time 7.74 seconds
Started Apr 18 01:15:18 PM PDT 24
Finished Apr 18 01:15:26 PM PDT 24
Peak memory 204008 kb
Host smart-53139c0b-8422-42df-9d94-88c414acb039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25805
47803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.2580547803
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.120622905
Short name T1147
Test name
Test status
Simulation time 8382616695 ps
CPU time 7.93 seconds
Started Apr 18 01:15:18 PM PDT 24
Finished Apr 18 01:15:27 PM PDT 24
Peak memory 203892 kb
Host smart-b0ecaee9-6d35-4f6e-b9f2-721d53fff97a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12062
2905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.120622905
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1089230893
Short name T607
Test name
Test status
Simulation time 8454000513 ps
CPU time 9.2 seconds
Started Apr 18 01:15:18 PM PDT 24
Finished Apr 18 01:15:28 PM PDT 24
Peak memory 204012 kb
Host smart-65ce5253-6ab5-4336-b185-47efb394e6b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10892
30893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1089230893
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.1302703016
Short name T864
Test name
Test status
Simulation time 8386296157 ps
CPU time 8.07 seconds
Started Apr 18 01:15:17 PM PDT 24
Finished Apr 18 01:15:26 PM PDT 24
Peak memory 203908 kb
Host smart-412a3a2b-9b3b-4b6f-bdfb-f471778b851f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13027
03016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.1302703016
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.678149766
Short name T811
Test name
Test status
Simulation time 8380382339 ps
CPU time 8.51 seconds
Started Apr 18 01:15:19 PM PDT 24
Finished Apr 18 01:15:29 PM PDT 24
Peak memory 204028 kb
Host smart-4624b348-1f77-4016-8e65-a8fd974807aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67814
9766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.678149766
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.max_length_in_transaction.1749708469
Short name T46
Test name
Test status
Simulation time 8464368538 ps
CPU time 7.61 seconds
Started Apr 18 01:15:25 PM PDT 24
Finished Apr 18 01:15:33 PM PDT 24
Peak memory 204040 kb
Host smart-859dacec-3d68-4cb3-8ef2-225862c4b4b2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1749708469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.1749708469
Directory /workspace/17.max_length_in_transaction/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.2903465062
Short name T752
Test name
Test status
Simulation time 8381186040 ps
CPU time 8 seconds
Started Apr 18 01:15:25 PM PDT 24
Finished Apr 18 01:15:34 PM PDT 24
Peak memory 204088 kb
Host smart-8ba5b2b4-04df-433f-8738-0e6ad84ebc33
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2903465062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.2903465062
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.1443473429
Short name T768
Test name
Test status
Simulation time 8446576708 ps
CPU time 9.32 seconds
Started Apr 18 01:15:25 PM PDT 24
Finished Apr 18 01:15:35 PM PDT 24
Peak memory 204036 kb
Host smart-7f6fc782-e941-4c0e-98c8-515c8494a38c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14434
73429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.1443473429
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.1261331764
Short name T366
Test name
Test status
Simulation time 8389802888 ps
CPU time 9.28 seconds
Started Apr 18 01:15:19 PM PDT 24
Finished Apr 18 01:15:29 PM PDT 24
Peak memory 204084 kb
Host smart-ce96fd83-7836-455b-a1a3-281400e65124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12613
31764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.1261331764
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_enable.1997588315
Short name T1216
Test name
Test status
Simulation time 8399228668 ps
CPU time 8.78 seconds
Started Apr 18 01:15:17 PM PDT 24
Finished Apr 18 01:15:26 PM PDT 24
Peak memory 204016 kb
Host smart-1f7ee8d8-e8c9-467b-aa51-7645e0528ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19975
88315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.1997588315
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.1587962404
Short name T485
Test name
Test status
Simulation time 295077367 ps
CPU time 2.3 seconds
Started Apr 18 01:15:19 PM PDT 24
Finished Apr 18 01:15:22 PM PDT 24
Peak memory 204208 kb
Host smart-da20c2ab-46d4-49f9-ae9b-3fbe4df06c25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15879
62404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.1587962404
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.4275365957
Short name T1317
Test name
Test status
Simulation time 8394709721 ps
CPU time 8.81 seconds
Started Apr 18 01:15:37 PM PDT 24
Finished Apr 18 01:15:46 PM PDT 24
Peak memory 203920 kb
Host smart-c7c0211f-57c2-46e6-92bc-b3ea2a5cb918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42753
65957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.4275365957
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.2103982336
Short name T499
Test name
Test status
Simulation time 8376566923 ps
CPU time 8.99 seconds
Started Apr 18 01:15:30 PM PDT 24
Finished Apr 18 01:15:39 PM PDT 24
Peak memory 203992 kb
Host smart-dd308f70-73a4-467b-8a89-2e87e9daad7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21039
82336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2103982336
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.894440363
Short name T145
Test name
Test status
Simulation time 8451853662 ps
CPU time 7.64 seconds
Started Apr 18 01:15:19 PM PDT 24
Finished Apr 18 01:15:28 PM PDT 24
Peak memory 203980 kb
Host smart-aa7f4e90-f472-4930-a675-4b63e848e4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89444
0363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.894440363
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.1781196951
Short name T1182
Test name
Test status
Simulation time 8425220619 ps
CPU time 10.31 seconds
Started Apr 18 01:15:19 PM PDT 24
Finished Apr 18 01:15:31 PM PDT 24
Peak memory 204028 kb
Host smart-040e9b07-f21c-4ff9-8337-ae7ebe3e6d48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17811
96951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.1781196951
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.3056361854
Short name T594
Test name
Test status
Simulation time 8367791038 ps
CPU time 7.76 seconds
Started Apr 18 01:15:19 PM PDT 24
Finished Apr 18 01:15:28 PM PDT 24
Peak memory 204044 kb
Host smart-1e3897da-3e2b-4c24-8a7f-ac97917de245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30563
61854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.3056361854
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.1638947427
Short name T1160
Test name
Test status
Simulation time 8375715566 ps
CPU time 7.53 seconds
Started Apr 18 01:15:46 PM PDT 24
Finished Apr 18 01:15:54 PM PDT 24
Peak memory 203964 kb
Host smart-d9f95528-4a7a-4b65-94fc-2b5634dc1ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16389
47427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.1638947427
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.408507811
Short name T160
Test name
Test status
Simulation time 8398996666 ps
CPU time 8.46 seconds
Started Apr 18 01:15:27 PM PDT 24
Finished Apr 18 01:15:36 PM PDT 24
Peak memory 203856 kb
Host smart-9e0e0ea4-d91b-4a51-af40-d443a4218845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40850
7811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.408507811
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.1442959290
Short name T560
Test name
Test status
Simulation time 8371161270 ps
CPU time 7.91 seconds
Started Apr 18 01:16:04 PM PDT 24
Finished Apr 18 01:16:13 PM PDT 24
Peak memory 204008 kb
Host smart-5f63425f-e6f3-41b3-841f-2cd20e4f44a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14429
59290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.1442959290
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.3568400116
Short name T1194
Test name
Test status
Simulation time 55161259 ps
CPU time 0.75 seconds
Started Apr 18 01:15:26 PM PDT 24
Finished Apr 18 01:15:27 PM PDT 24
Peak memory 203868 kb
Host smart-304cb878-030e-4f7f-9711-4b59219a9e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35684
00116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.3568400116
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.1143235368
Short name T664
Test name
Test status
Simulation time 22529147995 ps
CPU time 42.28 seconds
Started Apr 18 01:15:19 PM PDT 24
Finished Apr 18 01:16:02 PM PDT 24
Peak memory 204324 kb
Host smart-505af8c5-cc89-4545-afda-49fc96079c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11432
35368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.1143235368
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.1089824968
Short name T2
Test name
Test status
Simulation time 8382099127 ps
CPU time 7.95 seconds
Started Apr 18 01:15:18 PM PDT 24
Finished Apr 18 01:15:27 PM PDT 24
Peak memory 203984 kb
Host smart-a741c4c3-f05c-44a6-958a-821c8de49fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10898
24968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1089824968
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.1928847729
Short name T411
Test name
Test status
Simulation time 8440330305 ps
CPU time 8.17 seconds
Started Apr 18 01:15:17 PM PDT 24
Finished Apr 18 01:15:26 PM PDT 24
Peak memory 203968 kb
Host smart-1ce376f7-b5f4-47e7-92df-80c31c6e4860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19288
47729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.1928847729
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.1737896969
Short name T895
Test name
Test status
Simulation time 8391261839 ps
CPU time 8.35 seconds
Started Apr 18 01:15:26 PM PDT 24
Finished Apr 18 01:15:35 PM PDT 24
Peak memory 204012 kb
Host smart-6290eb00-e794-429d-b8aa-156ee8c110cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17378
96969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.1737896969
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.1828417680
Short name T996
Test name
Test status
Simulation time 8380593868 ps
CPU time 7.86 seconds
Started Apr 18 01:15:24 PM PDT 24
Finished Apr 18 01:15:33 PM PDT 24
Peak memory 204016 kb
Host smart-08ea0734-de18-4ec2-a21d-e9576796c433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18284
17680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.1828417680
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3562502273
Short name T522
Test name
Test status
Simulation time 8372023101 ps
CPU time 7.95 seconds
Started Apr 18 01:15:25 PM PDT 24
Finished Apr 18 01:15:34 PM PDT 24
Peak memory 204008 kb
Host smart-2f3e1497-f4c0-4f7c-ac66-b1f49f0418c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35625
02273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3562502273
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.3614940709
Short name T748
Test name
Test status
Simulation time 8402648308 ps
CPU time 9.54 seconds
Started Apr 18 01:15:25 PM PDT 24
Finished Apr 18 01:15:35 PM PDT 24
Peak memory 204044 kb
Host smart-b2415bf4-b892-42f4-aae1-49036bbeb60c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36149
40709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.3614940709
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2735179784
Short name T1017
Test name
Test status
Simulation time 8411004768 ps
CPU time 8.15 seconds
Started Apr 18 01:15:29 PM PDT 24
Finished Apr 18 01:15:38 PM PDT 24
Peak memory 203960 kb
Host smart-756201ee-9875-47fd-95b0-0d23bdd7a01a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27351
79784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2735179784
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.2262837616
Short name T597
Test name
Test status
Simulation time 8467102721 ps
CPU time 7.8 seconds
Started Apr 18 01:15:24 PM PDT 24
Finished Apr 18 01:15:32 PM PDT 24
Peak memory 204008 kb
Host smart-ea807908-d502-4c2e-b695-2edfad5681b9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2262837616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.2262837616
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.3048228130
Short name T313
Test name
Test status
Simulation time 8381620091 ps
CPU time 8.31 seconds
Started Apr 18 01:15:26 PM PDT 24
Finished Apr 18 01:15:36 PM PDT 24
Peak memory 204020 kb
Host smart-37189598-4b1c-4f63-8959-781d58c46a3f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3048228130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.3048228130
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.417265417
Short name T1143
Test name
Test status
Simulation time 8426320882 ps
CPU time 9.35 seconds
Started Apr 18 01:15:28 PM PDT 24
Finished Apr 18 01:15:38 PM PDT 24
Peak memory 203860 kb
Host smart-d7652b7b-9c43-478b-b8a9-8eb86f708d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41726
5417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.417265417
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2170549852
Short name T780
Test name
Test status
Simulation time 8388230421 ps
CPU time 8.31 seconds
Started Apr 18 01:15:27 PM PDT 24
Finished Apr 18 01:15:36 PM PDT 24
Peak memory 204044 kb
Host smart-2336481c-6d66-4932-8c0f-4f44168f4e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21705
49852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2170549852
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_enable.4020196252
Short name T1165
Test name
Test status
Simulation time 8386751819 ps
CPU time 7.81 seconds
Started Apr 18 01:15:26 PM PDT 24
Finished Apr 18 01:15:34 PM PDT 24
Peak memory 204016 kb
Host smart-5ac7dd28-ab54-42c3-87ab-f5720ae155dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40201
96252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.4020196252
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.573874144
Short name T443
Test name
Test status
Simulation time 147434808 ps
CPU time 1.71 seconds
Started Apr 18 01:15:33 PM PDT 24
Finished Apr 18 01:15:35 PM PDT 24
Peak memory 204108 kb
Host smart-7318a05b-26e2-4473-88c6-b5cafe31062a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57387
4144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.573874144
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.2184477146
Short name T557
Test name
Test status
Simulation time 8427739502 ps
CPU time 7.95 seconds
Started Apr 18 01:15:27 PM PDT 24
Finished Apr 18 01:15:36 PM PDT 24
Peak memory 204024 kb
Host smart-63807fd4-75cf-4b55-b483-18b2c7766557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21844
77146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.2184477146
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.48322064
Short name T190
Test name
Test status
Simulation time 8370057628 ps
CPU time 10.27 seconds
Started Apr 18 01:15:28 PM PDT 24
Finished Apr 18 01:15:39 PM PDT 24
Peak memory 204044 kb
Host smart-17419b03-7f90-4755-b723-8a3eea9c61d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48322
064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.48322064
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.1203559546
Short name T376
Test name
Test status
Simulation time 8440954129 ps
CPU time 8.17 seconds
Started Apr 18 01:15:26 PM PDT 24
Finished Apr 18 01:15:35 PM PDT 24
Peak memory 204028 kb
Host smart-362e59d6-a373-46c2-9b1e-d099300768f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12035
59546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1203559546
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.2405401704
Short name T494
Test name
Test status
Simulation time 8374732736 ps
CPU time 7.44 seconds
Started Apr 18 01:15:26 PM PDT 24
Finished Apr 18 01:15:35 PM PDT 24
Peak memory 204012 kb
Host smart-1d400339-279d-4893-8858-d8088b5c77b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24054
01704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.2405401704
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.1850206359
Short name T110
Test name
Test status
Simulation time 8449991227 ps
CPU time 8.01 seconds
Started Apr 18 01:15:26 PM PDT 24
Finished Apr 18 01:15:35 PM PDT 24
Peak memory 204060 kb
Host smart-98795c3c-ea86-4ab3-b1df-52bda99f6983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18502
06359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.1850206359
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.3699402427
Short name T869
Test name
Test status
Simulation time 8409151293 ps
CPU time 7.9 seconds
Started Apr 18 01:15:28 PM PDT 24
Finished Apr 18 01:15:36 PM PDT 24
Peak memory 203996 kb
Host smart-14ea3fbe-ff4c-42fb-aae4-a454750f0531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36994
02427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.3699402427
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1608926112
Short name T450
Test name
Test status
Simulation time 8431891909 ps
CPU time 7.7 seconds
Started Apr 18 01:15:28 PM PDT 24
Finished Apr 18 01:15:37 PM PDT 24
Peak memory 203964 kb
Host smart-c96ec1f5-b790-4177-acb0-9db82fb89e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16089
26112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1608926112
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.858674663
Short name T906
Test name
Test status
Simulation time 8413264158 ps
CPU time 7.86 seconds
Started Apr 18 01:15:28 PM PDT 24
Finished Apr 18 01:15:37 PM PDT 24
Peak memory 204040 kb
Host smart-3280ba99-a5d2-4ea3-a423-bb166086dca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85867
4663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.858674663
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.715863070
Short name T402
Test name
Test status
Simulation time 8373483312 ps
CPU time 8.2 seconds
Started Apr 18 01:15:24 PM PDT 24
Finished Apr 18 01:15:32 PM PDT 24
Peak memory 203908 kb
Host smart-df683449-7f16-43e8-a494-7b62eb2cfaca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71586
3070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.715863070
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3360763057
Short name T1080
Test name
Test status
Simulation time 82671004 ps
CPU time 0.69 seconds
Started Apr 18 01:15:25 PM PDT 24
Finished Apr 18 01:15:27 PM PDT 24
Peak memory 203816 kb
Host smart-05d3d5a7-7de1-455f-9e1f-379d56924b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33607
63057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3360763057
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.66527496
Short name T89
Test name
Test status
Simulation time 17004703803 ps
CPU time 30.31 seconds
Started Apr 18 01:15:25 PM PDT 24
Finished Apr 18 01:15:55 PM PDT 24
Peak memory 204360 kb
Host smart-6976f366-066b-4809-b649-de9cca5512b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66527
496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.66527496
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.2120353773
Short name T944
Test name
Test status
Simulation time 8382290558 ps
CPU time 9.98 seconds
Started Apr 18 01:15:27 PM PDT 24
Finished Apr 18 01:15:37 PM PDT 24
Peak memory 204000 kb
Host smart-0409ec88-7a43-44c9-86f3-243d1c8fc755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21203
53773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.2120353773
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.2879151468
Short name T1324
Test name
Test status
Simulation time 8433836275 ps
CPU time 7.97 seconds
Started Apr 18 01:15:26 PM PDT 24
Finished Apr 18 01:15:35 PM PDT 24
Peak memory 203960 kb
Host smart-f88da190-36ef-4445-a61f-8c1b489d029f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28791
51468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.2879151468
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.1539938244
Short name T751
Test name
Test status
Simulation time 8397529793 ps
CPU time 8.32 seconds
Started Apr 18 01:15:27 PM PDT 24
Finished Apr 18 01:15:36 PM PDT 24
Peak memory 204048 kb
Host smart-2d2f0122-4969-4a5f-aa4c-9b8648166c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15399
38244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.1539938244
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.891300008
Short name T1342
Test name
Test status
Simulation time 8375355944 ps
CPU time 8.17 seconds
Started Apr 18 01:15:47 PM PDT 24
Finished Apr 18 01:15:55 PM PDT 24
Peak memory 203996 kb
Host smart-c73fa7ce-1a59-42ca-9a97-ebc69f68bdcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89130
0008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.891300008
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.2244117065
Short name T602
Test name
Test status
Simulation time 8371249466 ps
CPU time 8.19 seconds
Started Apr 18 01:15:25 PM PDT 24
Finished Apr 18 01:15:33 PM PDT 24
Peak memory 204040 kb
Host smart-4da16610-c875-4f27-a60a-4b9ba7c5b568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22441
17065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.2244117065
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.334377709
Short name T912
Test name
Test status
Simulation time 8396056867 ps
CPU time 7.58 seconds
Started Apr 18 01:15:26 PM PDT 24
Finished Apr 18 01:15:34 PM PDT 24
Peak memory 204044 kb
Host smart-90e160f7-f8d4-4d3e-b815-3ca0ba17edb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33437
7709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.334377709
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.1382837876
Short name T1054
Test name
Test status
Simulation time 8396698459 ps
CPU time 9.99 seconds
Started Apr 18 01:15:26 PM PDT 24
Finished Apr 18 01:15:37 PM PDT 24
Peak memory 204028 kb
Host smart-7647d982-be5c-4cf4-8cd9-1d21c76c5649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13828
37876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.1382837876
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.1969938104
Short name T587
Test name
Test status
Simulation time 8463601857 ps
CPU time 7.89 seconds
Started Apr 18 01:15:36 PM PDT 24
Finished Apr 18 01:15:45 PM PDT 24
Peak memory 203980 kb
Host smart-dc2e8d74-46fd-4d40-a91b-26692c5a1514
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1969938104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.1969938104
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.1146088886
Short name T648
Test name
Test status
Simulation time 8382166587 ps
CPU time 8.2 seconds
Started Apr 18 01:15:36 PM PDT 24
Finished Apr 18 01:15:45 PM PDT 24
Peak memory 203924 kb
Host smart-21d497d1-ca46-4608-8212-5a97ca0108fe
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1146088886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.1146088886
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.2707382816
Short name T994
Test name
Test status
Simulation time 8429749645 ps
CPU time 8.09 seconds
Started Apr 18 01:15:34 PM PDT 24
Finished Apr 18 01:15:43 PM PDT 24
Peak memory 204040 kb
Host smart-ff4a3150-a646-495e-abcd-de9ce48ccd88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27073
82816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.2707382816
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.4044791108
Short name T558
Test name
Test status
Simulation time 8378520513 ps
CPU time 8.02 seconds
Started Apr 18 01:15:27 PM PDT 24
Finished Apr 18 01:15:35 PM PDT 24
Peak memory 204044 kb
Host smart-bc0ee328-2baf-4fa2-8b01-64d4387d07fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40447
91108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.4044791108
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_enable.787923771
Short name T1325
Test name
Test status
Simulation time 8418135093 ps
CPU time 8.04 seconds
Started Apr 18 01:15:28 PM PDT 24
Finished Apr 18 01:15:37 PM PDT 24
Peak memory 203964 kb
Host smart-2b400d3c-df60-46b9-a30e-9f7fa0fc2b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78792
3771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.787923771
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.1248443844
Short name T506
Test name
Test status
Simulation time 373489202 ps
CPU time 2.3 seconds
Started Apr 18 01:15:33 PM PDT 24
Finished Apr 18 01:15:36 PM PDT 24
Peak memory 204108 kb
Host smart-2950b7cb-ba80-4d53-a1e6-1bccdfcf0e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12484
43844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.1248443844
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.3335117793
Short name T141
Test name
Test status
Simulation time 8433546664 ps
CPU time 7.81 seconds
Started Apr 18 01:15:31 PM PDT 24
Finished Apr 18 01:15:40 PM PDT 24
Peak memory 204044 kb
Host smart-3cb46326-fc04-4df2-98b7-72e586b85e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33351
17793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.3335117793
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.1125374200
Short name T1050
Test name
Test status
Simulation time 8444782723 ps
CPU time 8.81 seconds
Started Apr 18 01:15:33 PM PDT 24
Finished Apr 18 01:15:43 PM PDT 24
Peak memory 203856 kb
Host smart-9a0d7b86-5f96-4f93-8263-8cfd8807d025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11253
74200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.1125374200
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.4148796724
Short name T572
Test name
Test status
Simulation time 8459299366 ps
CPU time 7.49 seconds
Started Apr 18 01:15:34 PM PDT 24
Finished Apr 18 01:15:42 PM PDT 24
Peak memory 203960 kb
Host smart-61739420-2abc-43e2-b44f-861be966792d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41487
96724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.4148796724
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.4247284294
Short name T961
Test name
Test status
Simulation time 8428239402 ps
CPU time 7.93 seconds
Started Apr 18 01:15:34 PM PDT 24
Finished Apr 18 01:15:42 PM PDT 24
Peak memory 204040 kb
Host smart-11d19da2-e137-40c2-9077-9dd2c22fd407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42472
84294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.4247284294
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.1762148601
Short name T1372
Test name
Test status
Simulation time 8374090443 ps
CPU time 7.89 seconds
Started Apr 18 01:15:32 PM PDT 24
Finished Apr 18 01:15:40 PM PDT 24
Peak memory 203948 kb
Host smart-9845d617-6588-4d24-a128-e2bcb2b8c5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17621
48601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.1762148601
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.3870727157
Short name T658
Test name
Test status
Simulation time 8445179268 ps
CPU time 7.93 seconds
Started Apr 18 01:15:34 PM PDT 24
Finished Apr 18 01:15:43 PM PDT 24
Peak memory 204040 kb
Host smart-288c0189-da15-4e49-8c78-bf193e427e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38707
27157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3870727157
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.2054511796
Short name T1266
Test name
Test status
Simulation time 8420461501 ps
CPU time 7.78 seconds
Started Apr 18 01:15:39 PM PDT 24
Finished Apr 18 01:15:47 PM PDT 24
Peak memory 204028 kb
Host smart-20e84ba7-51c5-4db3-8f85-40e87995036d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20545
11796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2054511796
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.1536467852
Short name T430
Test name
Test status
Simulation time 8386377551 ps
CPU time 8.15 seconds
Started Apr 18 01:15:38 PM PDT 24
Finished Apr 18 01:15:47 PM PDT 24
Peak memory 203868 kb
Host smart-b5791500-2f10-467f-a910-c583ebf85dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15364
67852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.1536467852
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.2320825009
Short name T902
Test name
Test status
Simulation time 8376615624 ps
CPU time 7.74 seconds
Started Apr 18 01:15:30 PM PDT 24
Finished Apr 18 01:15:39 PM PDT 24
Peak memory 204052 kb
Host smart-52754df2-c1fa-4375-a290-c1cf3bd3e1d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23208
25009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.2320825009
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.4072280476
Short name T510
Test name
Test status
Simulation time 8364659544 ps
CPU time 7.91 seconds
Started Apr 18 01:15:33 PM PDT 24
Finished Apr 18 01:15:41 PM PDT 24
Peak memory 204040 kb
Host smart-655faf59-2aed-45c1-b514-4db86fdc42d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40722
80476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.4072280476
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.601325984
Short name T972
Test name
Test status
Simulation time 30438720924 ps
CPU time 59.84 seconds
Started Apr 18 01:15:34 PM PDT 24
Finished Apr 18 01:16:35 PM PDT 24
Peak memory 204248 kb
Host smart-f5a91568-2c3e-4f23-be46-16f330e84ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60132
5984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.601325984
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.2372599482
Short name T531
Test name
Test status
Simulation time 8472446275 ps
CPU time 8.22 seconds
Started Apr 18 01:15:39 PM PDT 24
Finished Apr 18 01:15:48 PM PDT 24
Peak memory 203996 kb
Host smart-cde01b6f-80f6-4fba-98ae-88ff7aa5e8de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23725
99482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.2372599482
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1485671491
Short name T914
Test name
Test status
Simulation time 8439957773 ps
CPU time 8.99 seconds
Started Apr 18 01:15:33 PM PDT 24
Finished Apr 18 01:15:43 PM PDT 24
Peak memory 203992 kb
Host smart-96e4f45d-a38e-4ffc-ba9c-bb87bf1ad86d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14856
71491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1485671491
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.3101553401
Short name T877
Test name
Test status
Simulation time 8416962906 ps
CPU time 8.26 seconds
Started Apr 18 01:15:31 PM PDT 24
Finished Apr 18 01:15:40 PM PDT 24
Peak memory 203980 kb
Host smart-6aa0a481-5a46-43fc-92f6-dcca705168ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31015
53401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.3101553401
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.1840967052
Short name T164
Test name
Test status
Simulation time 8374465230 ps
CPU time 8.7 seconds
Started Apr 18 01:15:35 PM PDT 24
Finished Apr 18 01:15:45 PM PDT 24
Peak memory 203960 kb
Host smart-6ac2092b-6030-4bd1-a762-f7bd610307d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18409
67052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.1840967052
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.64195241
Short name T685
Test name
Test status
Simulation time 8370178805 ps
CPU time 9.1 seconds
Started Apr 18 01:15:35 PM PDT 24
Finished Apr 18 01:15:45 PM PDT 24
Peak memory 203924 kb
Host smart-de7c08e4-817a-427e-a010-45dc031227be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64195
241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.64195241
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.4255298025
Short name T1288
Test name
Test status
Simulation time 8500009028 ps
CPU time 7.81 seconds
Started Apr 18 01:15:24 PM PDT 24
Finished Apr 18 01:15:33 PM PDT 24
Peak memory 204028 kb
Host smart-4684665f-69d7-46c2-a865-6c25a7942876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42552
98025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.4255298025
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.3860553313
Short name T540
Test name
Test status
Simulation time 8406018364 ps
CPU time 8.45 seconds
Started Apr 18 01:15:35 PM PDT 24
Finished Apr 18 01:15:45 PM PDT 24
Peak memory 203896 kb
Host smart-4b5e9ca5-eb84-4e4d-a60c-f28bebe38c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38605
53313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.3860553313
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.1088468905
Short name T1132
Test name
Test status
Simulation time 8392478806 ps
CPU time 8.48 seconds
Started Apr 18 01:15:34 PM PDT 24
Finished Apr 18 01:15:44 PM PDT 24
Peak memory 203996 kb
Host smart-5958bf85-6920-4322-b698-809709406c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10884
68905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.1088468905
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.2704573340
Short name T1315
Test name
Test status
Simulation time 8457271476 ps
CPU time 8.28 seconds
Started Apr 18 01:13:41 PM PDT 24
Finished Apr 18 01:13:50 PM PDT 24
Peak memory 204012 kb
Host smart-a17cec7e-94c4-4dfb-9382-7950393f6b4f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2704573340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.2704573340
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.3209939575
Short name T1138
Test name
Test status
Simulation time 8421824669 ps
CPU time 9.2 seconds
Started Apr 18 01:13:43 PM PDT 24
Finished Apr 18 01:13:53 PM PDT 24
Peak memory 204016 kb
Host smart-f9834212-10e1-406a-a91d-cc66e903239c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3209939575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.3209939575
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.2798362816
Short name T1236
Test name
Test status
Simulation time 8390545034 ps
CPU time 8.66 seconds
Started Apr 18 01:13:44 PM PDT 24
Finished Apr 18 01:13:54 PM PDT 24
Peak memory 204024 kb
Host smart-b39eb156-fc51-449b-bbb1-73214548a111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27983
62816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.2798362816
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.1343124625
Short name T561
Test name
Test status
Simulation time 8388934745 ps
CPU time 7.5 seconds
Started Apr 18 01:13:42 PM PDT 24
Finished Apr 18 01:13:50 PM PDT 24
Peak memory 204024 kb
Host smart-09e26663-38f7-4660-bec4-951345c7aae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13431
24625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.1343124625
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_enable.4254054975
Short name T1030
Test name
Test status
Simulation time 8382990471 ps
CPU time 9.63 seconds
Started Apr 18 01:13:36 PM PDT 24
Finished Apr 18 01:13:46 PM PDT 24
Peak memory 204008 kb
Host smart-7ec6ed23-5fc5-440f-b15f-7a741aff835c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42540
54975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.4254054975
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2535247346
Short name T369
Test name
Test status
Simulation time 118109548 ps
CPU time 1.37 seconds
Started Apr 18 01:13:35 PM PDT 24
Finished Apr 18 01:13:37 PM PDT 24
Peak memory 204148 kb
Host smart-98ac72bb-c19b-4bad-bc9f-aa9c54985748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25352
47346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2535247346
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.4240447990
Short name T416
Test name
Test status
Simulation time 8443398845 ps
CPU time 8.21 seconds
Started Apr 18 01:13:42 PM PDT 24
Finished Apr 18 01:13:51 PM PDT 24
Peak memory 204048 kb
Host smart-a889c04f-fb4d-48e1-a1fe-0b0e54ed1c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42404
47990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.4240447990
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.3807167785
Short name T696
Test name
Test status
Simulation time 8370413051 ps
CPU time 8.59 seconds
Started Apr 18 01:13:35 PM PDT 24
Finished Apr 18 01:13:45 PM PDT 24
Peak memory 203972 kb
Host smart-25596d80-b579-4ddb-b26e-4c15e567f424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38071
67785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.3807167785
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.3816911537
Short name T1028
Test name
Test status
Simulation time 8413734565 ps
CPU time 8.63 seconds
Started Apr 18 01:13:36 PM PDT 24
Finished Apr 18 01:13:45 PM PDT 24
Peak memory 204044 kb
Host smart-b59459ae-2cd9-4c5f-a433-d79ecffac9e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38169
11537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.3816911537
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.2917506799
Short name T1260
Test name
Test status
Simulation time 8453218394 ps
CPU time 7.71 seconds
Started Apr 18 01:13:37 PM PDT 24
Finished Apr 18 01:13:46 PM PDT 24
Peak memory 204068 kb
Host smart-f333f0b0-9543-43f0-924d-1cfa0ab30c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29175
06799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.2917506799
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.3674990575
Short name T941
Test name
Test status
Simulation time 8373513585 ps
CPU time 10.12 seconds
Started Apr 18 01:13:37 PM PDT 24
Finished Apr 18 01:13:47 PM PDT 24
Peak memory 204024 kb
Host smart-6074e543-2db5-4004-a36a-916d8a607788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36749
90575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.3674990575
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.1940867497
Short name T955
Test name
Test status
Simulation time 8435582358 ps
CPU time 8.61 seconds
Started Apr 18 01:13:41 PM PDT 24
Finished Apr 18 01:13:50 PM PDT 24
Peak memory 204024 kb
Host smart-dddf3f38-c357-499a-bb74-4feb0415cabc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19408
67497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.1940867497
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.1692952599
Short name T1311
Test name
Test status
Simulation time 8406028755 ps
CPU time 10.01 seconds
Started Apr 18 01:13:36 PM PDT 24
Finished Apr 18 01:13:47 PM PDT 24
Peak memory 204004 kb
Host smart-8b0d068d-8edb-4ef1-bee1-ae159496ff91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16929
52599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.1692952599
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1349244614
Short name T668
Test name
Test status
Simulation time 8414658953 ps
CPU time 9.55 seconds
Started Apr 18 01:13:40 PM PDT 24
Finished Apr 18 01:13:50 PM PDT 24
Peak memory 204016 kb
Host smart-bf090452-d6bc-42db-91a9-23daab6f1c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13492
44614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1349244614
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.2196210770
Short name T954
Test name
Test status
Simulation time 8405059979 ps
CPU time 8.49 seconds
Started Apr 18 01:13:41 PM PDT 24
Finished Apr 18 01:13:51 PM PDT 24
Peak memory 204024 kb
Host smart-36946bac-b460-4b49-ba84-3cc8e211c75d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21962
10770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.2196210770
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.1602342281
Short name T535
Test name
Test status
Simulation time 8376721131 ps
CPU time 7.46 seconds
Started Apr 18 01:13:37 PM PDT 24
Finished Apr 18 01:13:45 PM PDT 24
Peak memory 204064 kb
Host smart-1ab82b1d-55d1-4a24-82ba-312ca4bb8a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16023
42281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.1602342281
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.1833291579
Short name T1187
Test name
Test status
Simulation time 65283815 ps
CPU time 0.69 seconds
Started Apr 18 01:13:45 PM PDT 24
Finished Apr 18 01:13:46 PM PDT 24
Peak memory 203868 kb
Host smart-a87f0df8-ca92-4dc3-bd8c-8b23766abc29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18332
91579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.1833291579
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.1212246448
Short name T892
Test name
Test status
Simulation time 8414463427 ps
CPU time 8.33 seconds
Started Apr 18 01:13:37 PM PDT 24
Finished Apr 18 01:13:46 PM PDT 24
Peak memory 203980 kb
Host smart-7a22d29e-6529-46e6-93db-7febdb9b86bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12122
46448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.1212246448
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3872089395
Short name T1047
Test name
Test status
Simulation time 8428176319 ps
CPU time 8.25 seconds
Started Apr 18 01:13:36 PM PDT 24
Finished Apr 18 01:13:45 PM PDT 24
Peak memory 203904 kb
Host smart-e3fb25e6-229e-40a4-a5d5-391007277c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38720
89395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3872089395
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.3368770151
Short name T942
Test name
Test status
Simulation time 8409193538 ps
CPU time 7.75 seconds
Started Apr 18 01:13:45 PM PDT 24
Finished Apr 18 01:13:53 PM PDT 24
Peak memory 203996 kb
Host smart-1b7cdd21-3844-44e6-a440-75f8e92368ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33687
70151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.3368770151
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.1836699059
Short name T71
Test name
Test status
Simulation time 239368186 ps
CPU time 1.24 seconds
Started Apr 18 01:13:47 PM PDT 24
Finished Apr 18 01:13:48 PM PDT 24
Peak memory 221188 kb
Host smart-d5d5700f-7827-461d-b2a7-4726e33d92e4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1836699059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1836699059
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.1829360516
Short name T953
Test name
Test status
Simulation time 8414569064 ps
CPU time 7.73 seconds
Started Apr 18 01:13:34 PM PDT 24
Finished Apr 18 01:13:42 PM PDT 24
Peak memory 204044 kb
Host smart-a6e04ca1-ce9e-4185-b24b-feb1cc9cb182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18293
60516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.1829360516
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3891639180
Short name T1301
Test name
Test status
Simulation time 8378287798 ps
CPU time 7.71 seconds
Started Apr 18 01:13:35 PM PDT 24
Finished Apr 18 01:13:43 PM PDT 24
Peak memory 204020 kb
Host smart-8b933543-5a8d-42c0-a57a-c2e1d2723a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38916
39180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3891639180
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.2947846708
Short name T1264
Test name
Test status
Simulation time 8496469317 ps
CPU time 7.96 seconds
Started Apr 18 01:13:36 PM PDT 24
Finished Apr 18 01:13:45 PM PDT 24
Peak memory 204008 kb
Host smart-ab6004a5-959a-4565-832c-c7999bbdeeea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29478
46708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.2947846708
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.3240227322
Short name T1004
Test name
Test status
Simulation time 8459425491 ps
CPU time 10.03 seconds
Started Apr 18 01:13:35 PM PDT 24
Finished Apr 18 01:13:46 PM PDT 24
Peak memory 203936 kb
Host smart-e8cc6c64-0b19-4de0-97ca-ac5ef47fe1b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32402
27322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.3240227322
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.389546752
Short name T1152
Test name
Test status
Simulation time 8387613021 ps
CPU time 7.84 seconds
Started Apr 18 01:13:36 PM PDT 24
Finished Apr 18 01:13:44 PM PDT 24
Peak memory 204044 kb
Host smart-7d4d86f6-b958-4244-a198-b60b0628c456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38954
6752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.389546752
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.3057890889
Short name T374
Test name
Test status
Simulation time 8465238444 ps
CPU time 7.89 seconds
Started Apr 18 01:15:43 PM PDT 24
Finished Apr 18 01:15:51 PM PDT 24
Peak memory 204048 kb
Host smart-9419ed56-1dae-42a6-b276-66e68edb6b4c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3057890889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.3057890889
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.1027270403
Short name T515
Test name
Test status
Simulation time 8380649494 ps
CPU time 10.18 seconds
Started Apr 18 01:15:42 PM PDT 24
Finished Apr 18 01:15:53 PM PDT 24
Peak memory 204004 kb
Host smart-53045d2c-7d75-48be-8993-8b2d50bfe69d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1027270403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.1027270403
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.2506121333
Short name T860
Test name
Test status
Simulation time 8426203308 ps
CPU time 7.79 seconds
Started Apr 18 01:15:42 PM PDT 24
Finished Apr 18 01:15:51 PM PDT 24
Peak memory 203956 kb
Host smart-8df4b891-0a48-4d91-8af5-c7595feac204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25061
21333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.2506121333
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.1532435523
Short name T660
Test name
Test status
Simulation time 8382099721 ps
CPU time 7.66 seconds
Started Apr 18 01:15:31 PM PDT 24
Finished Apr 18 01:15:39 PM PDT 24
Peak memory 203960 kb
Host smart-e4119d5c-fe44-459e-9d43-8c5ec5e9dcdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15324
35523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.1532435523
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_enable.1261331946
Short name T388
Test name
Test status
Simulation time 8440667154 ps
CPU time 7.92 seconds
Started Apr 18 01:15:34 PM PDT 24
Finished Apr 18 01:15:43 PM PDT 24
Peak memory 204040 kb
Host smart-3cc9788e-4c19-4e27-b45e-98552f42b47a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12613
31946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1261331946
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1120975173
Short name T1033
Test name
Test status
Simulation time 54266763 ps
CPU time 1.44 seconds
Started Apr 18 01:15:34 PM PDT 24
Finished Apr 18 01:15:36 PM PDT 24
Peak memory 204132 kb
Host smart-253df3f2-c2ab-4a9f-bb4c-a78d4ea0f3bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11209
75173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1120975173
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.3367484431
Short name T1286
Test name
Test status
Simulation time 8390155699 ps
CPU time 8.04 seconds
Started Apr 18 01:15:45 PM PDT 24
Finished Apr 18 01:15:54 PM PDT 24
Peak memory 203988 kb
Host smart-bd781331-280d-48c3-8407-b0da2d20ced0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33674
84431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.3367484431
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.2726956145
Short name T173
Test name
Test status
Simulation time 8408087627 ps
CPU time 7.47 seconds
Started Apr 18 01:15:43 PM PDT 24
Finished Apr 18 01:15:51 PM PDT 24
Peak memory 203976 kb
Host smart-2a9cfa08-b967-458a-91ea-79911013e0d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27269
56145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.2726956145
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.2755725874
Short name T1161
Test name
Test status
Simulation time 8438986984 ps
CPU time 9.38 seconds
Started Apr 18 01:16:02 PM PDT 24
Finished Apr 18 01:16:13 PM PDT 24
Peak memory 204080 kb
Host smart-29be9b2d-7864-4d0e-be9e-8ed4673d6ed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27557
25874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.2755725874
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1257354401
Short name T1249
Test name
Test status
Simulation time 8428776482 ps
CPU time 7.57 seconds
Started Apr 18 01:15:32 PM PDT 24
Finished Apr 18 01:15:40 PM PDT 24
Peak memory 203924 kb
Host smart-f2cb0327-c689-4549-90f1-6888c6e741ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12573
54401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1257354401
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.1529578485
Short name T689
Test name
Test status
Simulation time 8373525718 ps
CPU time 8.41 seconds
Started Apr 18 01:15:39 PM PDT 24
Finished Apr 18 01:15:48 PM PDT 24
Peak memory 204012 kb
Host smart-1501e8ff-062c-4392-be48-e94a8d4e5fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15295
78485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.1529578485
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.55985305
Short name T108
Test name
Test status
Simulation time 8413084516 ps
CPU time 8.62 seconds
Started Apr 18 01:15:39 PM PDT 24
Finished Apr 18 01:15:48 PM PDT 24
Peak memory 204020 kb
Host smart-9d6c7c21-7bd8-4f43-bedd-4e2aeaa9cddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55985
305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.55985305
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.3303525131
Short name T352
Test name
Test status
Simulation time 8401759994 ps
CPU time 8.08 seconds
Started Apr 18 01:16:02 PM PDT 24
Finished Apr 18 01:16:12 PM PDT 24
Peak memory 204012 kb
Host smart-6d540012-e009-461c-89bb-8ad5e012700a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33035
25131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.3303525131
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.4245745730
Short name T990
Test name
Test status
Simulation time 8418121862 ps
CPU time 8.78 seconds
Started Apr 18 01:15:34 PM PDT 24
Finished Apr 18 01:15:43 PM PDT 24
Peak memory 204084 kb
Host smart-080266c4-aad9-4369-a091-acde115d3957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42457
45730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.4245745730
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.1233141463
Short name T532
Test name
Test status
Simulation time 8372395359 ps
CPU time 9.21 seconds
Started Apr 18 01:15:39 PM PDT 24
Finished Apr 18 01:15:49 PM PDT 24
Peak memory 204008 kb
Host smart-29f92745-b284-427d-8327-aefb6f85a2d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12331
41463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.1233141463
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.799056111
Short name T1145
Test name
Test status
Simulation time 35840844 ps
CPU time 0.66 seconds
Started Apr 18 01:15:41 PM PDT 24
Finished Apr 18 01:15:43 PM PDT 24
Peak memory 203848 kb
Host smart-01f41b00-82fd-4bee-941a-86a9624bbce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79905
6111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.799056111
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3034650790
Short name T1302
Test name
Test status
Simulation time 26271662938 ps
CPU time 53.02 seconds
Started Apr 18 01:15:37 PM PDT 24
Finished Apr 18 01:16:31 PM PDT 24
Peak memory 204292 kb
Host smart-3ab087b8-5120-4504-a71e-01aa329fc477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30346
50790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3034650790
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.830652609
Short name T915
Test name
Test status
Simulation time 8408811017 ps
CPU time 8.7 seconds
Started Apr 18 01:15:34 PM PDT 24
Finished Apr 18 01:15:43 PM PDT 24
Peak memory 204004 kb
Host smart-a947838c-6242-4e9b-8541-eb7133c3fad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83065
2609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.830652609
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.1432461455
Short name T1274
Test name
Test status
Simulation time 8529119004 ps
CPU time 8.65 seconds
Started Apr 18 01:15:39 PM PDT 24
Finished Apr 18 01:15:48 PM PDT 24
Peak memory 204024 kb
Host smart-ddb0716f-d1d9-43b5-b6a3-8e09b13d484c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14324
61455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.1432461455
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.1137965405
Short name T1005
Test name
Test status
Simulation time 8374954834 ps
CPU time 7.55 seconds
Started Apr 18 01:15:36 PM PDT 24
Finished Apr 18 01:15:44 PM PDT 24
Peak memory 203984 kb
Host smart-95039eb3-759e-4166-8c52-b4ecfa4b7bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11379
65405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.1137965405
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.3800382430
Short name T925
Test name
Test status
Simulation time 8385117561 ps
CPU time 8 seconds
Started Apr 18 01:15:44 PM PDT 24
Finished Apr 18 01:15:52 PM PDT 24
Peak memory 203908 kb
Host smart-bf3a8146-4497-4d03-b112-68eac7174002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38003
82430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.3800382430
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.336643507
Short name T991
Test name
Test status
Simulation time 8372998189 ps
CPU time 7.55 seconds
Started Apr 18 01:15:37 PM PDT 24
Finished Apr 18 01:15:45 PM PDT 24
Peak memory 203976 kb
Host smart-fef42c9b-d392-4a96-9ccf-80b72b98a3d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33664
3507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.336643507
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.3212698905
Short name T492
Test name
Test status
Simulation time 8455924272 ps
CPU time 9.34 seconds
Started Apr 18 01:15:34 PM PDT 24
Finished Apr 18 01:15:44 PM PDT 24
Peak memory 203996 kb
Host smart-845049d2-9356-4f6e-8c3d-b871c537c3f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32126
98905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.3212698905
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.3617457618
Short name T1353
Test name
Test status
Simulation time 8376011324 ps
CPU time 8.23 seconds
Started Apr 18 01:15:39 PM PDT 24
Finished Apr 18 01:15:48 PM PDT 24
Peak memory 204020 kb
Host smart-95bb9459-a15b-4533-81a8-f9cfc657264a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36174
57618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.3617457618
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.754522378
Short name T408
Test name
Test status
Simulation time 8411871022 ps
CPU time 8.11 seconds
Started Apr 18 01:15:33 PM PDT 24
Finished Apr 18 01:15:42 PM PDT 24
Peak memory 204060 kb
Host smart-82e81dd5-926a-4fe3-b3f3-71795e090b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75452
2378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.754522378
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.731169098
Short name T807
Test name
Test status
Simulation time 8458856341 ps
CPU time 7.9 seconds
Started Apr 18 01:15:40 PM PDT 24
Finished Apr 18 01:15:49 PM PDT 24
Peak memory 204012 kb
Host smart-fb0e17fd-c56e-45c8-95a7-453749897e2f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=731169098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.731169098
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.2884696455
Short name T969
Test name
Test status
Simulation time 8379960090 ps
CPU time 9.94 seconds
Started Apr 18 01:16:22 PM PDT 24
Finished Apr 18 01:16:32 PM PDT 24
Peak memory 204020 kb
Host smart-3ad4863c-ccd7-4069-b6cd-ba99fc4f13a7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2884696455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.2884696455
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.1276390504
Short name T987
Test name
Test status
Simulation time 8425328945 ps
CPU time 9.04 seconds
Started Apr 18 01:15:41 PM PDT 24
Finished Apr 18 01:15:51 PM PDT 24
Peak memory 203944 kb
Host smart-92007513-18a5-4ffb-ac89-a633987f5288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12763
90504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.1276390504
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.900844319
Short name T1251
Test name
Test status
Simulation time 8471906684 ps
CPU time 9.14 seconds
Started Apr 18 01:15:57 PM PDT 24
Finished Apr 18 01:16:08 PM PDT 24
Peak memory 204044 kb
Host smart-ab23745d-20d3-42a4-b73d-f1e2c2c7944f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90084
4319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.900844319
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_enable.2692067284
Short name T1282
Test name
Test status
Simulation time 8371363142 ps
CPU time 8.44 seconds
Started Apr 18 01:15:41 PM PDT 24
Finished Apr 18 01:15:50 PM PDT 24
Peak memory 204004 kb
Host smart-a8fc0341-ebc3-48da-b36e-a614b5ba0d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26920
67284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.2692067284
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.3116509998
Short name T1293
Test name
Test status
Simulation time 259210380 ps
CPU time 2.08 seconds
Started Apr 18 01:15:45 PM PDT 24
Finished Apr 18 01:15:48 PM PDT 24
Peak memory 204116 kb
Host smart-77718a2a-299d-4ae3-b3f3-821c28bc3727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31165
09998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.3116509998
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.3724106108
Short name T1071
Test name
Test status
Simulation time 8418344633 ps
CPU time 7.8 seconds
Started Apr 18 01:15:43 PM PDT 24
Finished Apr 18 01:15:52 PM PDT 24
Peak memory 204036 kb
Host smart-d3ec1e46-464d-4c1f-908e-89578df90f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37241
06108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.3724106108
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.1624985487
Short name T966
Test name
Test status
Simulation time 8366745651 ps
CPU time 8.27 seconds
Started Apr 18 01:15:44 PM PDT 24
Finished Apr 18 01:15:53 PM PDT 24
Peak memory 204024 kb
Host smart-82a02429-aa60-4d06-b99a-2c77d263b158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16249
85487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.1624985487
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.1265411426
Short name T131
Test name
Test status
Simulation time 8491136640 ps
CPU time 7.43 seconds
Started Apr 18 01:15:41 PM PDT 24
Finished Apr 18 01:15:49 PM PDT 24
Peak memory 204248 kb
Host smart-b98373ee-740d-42ac-8cd3-ef6cf855d7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12654
11426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.1265411426
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.1911854011
Short name T790
Test name
Test status
Simulation time 8443246185 ps
CPU time 9.14 seconds
Started Apr 18 01:15:40 PM PDT 24
Finished Apr 18 01:15:49 PM PDT 24
Peak memory 204028 kb
Host smart-098b39ca-d86d-4718-8748-5cf5794aafdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19118
54011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.1911854011
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.773346742
Short name T1321
Test name
Test status
Simulation time 8369291507 ps
CPU time 7.58 seconds
Started Apr 18 01:15:43 PM PDT 24
Finished Apr 18 01:15:51 PM PDT 24
Peak memory 204016 kb
Host smart-1a16d0f0-48d3-4787-a4c2-bb98fa57ac9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77334
6742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.773346742
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3906922332
Short name T114
Test name
Test status
Simulation time 8433538424 ps
CPU time 8.63 seconds
Started Apr 18 01:15:41 PM PDT 24
Finished Apr 18 01:15:50 PM PDT 24
Peak memory 204012 kb
Host smart-5e60b500-230d-4400-b9ba-1e87e1c7a938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39069
22332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3906922332
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.1897450531
Short name T346
Test name
Test status
Simulation time 8394926693 ps
CPU time 10.15 seconds
Started Apr 18 01:15:41 PM PDT 24
Finished Apr 18 01:15:52 PM PDT 24
Peak memory 204080 kb
Host smart-fa69e2fc-6d6d-4d0f-8efe-b52ae31b9e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18974
50531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.1897450531
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3130545056
Short name T354
Test name
Test status
Simulation time 8401328246 ps
CPU time 8.17 seconds
Started Apr 18 01:15:42 PM PDT 24
Finished Apr 18 01:15:51 PM PDT 24
Peak memory 203956 kb
Host smart-a0b038da-5c6d-454a-99bf-04594ef730de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31305
45056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3130545056
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.620196641
Short name T1329
Test name
Test status
Simulation time 8369813387 ps
CPU time 7.72 seconds
Started Apr 18 01:15:57 PM PDT 24
Finished Apr 18 01:16:06 PM PDT 24
Peak memory 203992 kb
Host smart-37f8f9e6-7801-4494-b0ac-c6daa4ac7980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62019
6641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.620196641
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.1713119094
Short name T1101
Test name
Test status
Simulation time 76621924 ps
CPU time 0.7 seconds
Started Apr 18 01:15:41 PM PDT 24
Finished Apr 18 01:15:42 PM PDT 24
Peak memory 203876 kb
Host smart-845b8a21-f12c-4ebf-9511-a075e7e6977b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17131
19094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.1713119094
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.1061212634
Short name T1032
Test name
Test status
Simulation time 15491259673 ps
CPU time 31.64 seconds
Started Apr 18 01:15:41 PM PDT 24
Finished Apr 18 01:16:13 PM PDT 24
Peak memory 204328 kb
Host smart-38a8489e-b61f-408b-b443-0fa6c89d6720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10612
12634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.1061212634
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.2629818557
Short name T616
Test name
Test status
Simulation time 8384572545 ps
CPU time 8.47 seconds
Started Apr 18 01:15:41 PM PDT 24
Finished Apr 18 01:15:51 PM PDT 24
Peak memory 203960 kb
Host smart-f1e9c1b0-cec7-4f82-a263-758b9267ffc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26298
18557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.2629818557
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.729952507
Short name T1137
Test name
Test status
Simulation time 8404449711 ps
CPU time 9.05 seconds
Started Apr 18 01:15:41 PM PDT 24
Finished Apr 18 01:15:51 PM PDT 24
Peak memory 203940 kb
Host smart-bdc89230-29f8-4ebe-9987-fc3c482c2a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72995
2507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.729952507
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.2361649179
Short name T651
Test name
Test status
Simulation time 8383518000 ps
CPU time 10.07 seconds
Started Apr 18 01:15:44 PM PDT 24
Finished Apr 18 01:15:54 PM PDT 24
Peak memory 204024 kb
Host smart-9db980c1-0c6b-4230-a2c6-cb239b7a8563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23616
49179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.2361649179
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.885833028
Short name T169
Test name
Test status
Simulation time 8380287654 ps
CPU time 8.48 seconds
Started Apr 18 01:15:40 PM PDT 24
Finished Apr 18 01:15:50 PM PDT 24
Peak memory 204028 kb
Host smart-b01b8066-8698-4ba8-a36f-3a66dadc750d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88583
3028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.885833028
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1992546001
Short name T429
Test name
Test status
Simulation time 8374602774 ps
CPU time 10.21 seconds
Started Apr 18 01:15:45 PM PDT 24
Finished Apr 18 01:15:55 PM PDT 24
Peak memory 204020 kb
Host smart-b9458a79-5322-466d-9a4b-9189409cc848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19925
46001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1992546001
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1443945281
Short name T81
Test name
Test status
Simulation time 8442278697 ps
CPU time 8.37 seconds
Started Apr 18 01:15:41 PM PDT 24
Finished Apr 18 01:15:50 PM PDT 24
Peak memory 203948 kb
Host smart-edfb3456-264e-4a39-a02c-5c857d8a8007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14439
45281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1443945281
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.3373352681
Short name T300
Test name
Test status
Simulation time 8410052041 ps
CPU time 8.09 seconds
Started Apr 18 01:15:40 PM PDT 24
Finished Apr 18 01:15:48 PM PDT 24
Peak memory 204016 kb
Host smart-02a4f6ae-cec8-44fd-86a2-e689b4563369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33733
52681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.3373352681
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.4126366039
Short name T887
Test name
Test status
Simulation time 8394236614 ps
CPU time 8.3 seconds
Started Apr 18 01:15:42 PM PDT 24
Finished Apr 18 01:15:51 PM PDT 24
Peak memory 204040 kb
Host smart-146edd8a-71d4-4326-9c4f-c84e1ccea250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41263
66039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.4126366039
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.3912880347
Short name T750
Test name
Test status
Simulation time 8477589477 ps
CPU time 7.55 seconds
Started Apr 18 01:15:49 PM PDT 24
Finished Apr 18 01:15:57 PM PDT 24
Peak memory 203868 kb
Host smart-f6bdac94-a781-441b-a41f-374967b3970d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3912880347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.3912880347
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.728994163
Short name T1234
Test name
Test status
Simulation time 8376199451 ps
CPU time 8.22 seconds
Started Apr 18 01:15:52 PM PDT 24
Finished Apr 18 01:16:01 PM PDT 24
Peak memory 204032 kb
Host smart-6fd084ca-71ff-4966-99f3-e4fd7a30db68
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=728994163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.728994163
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.134748756
Short name T1052
Test name
Test status
Simulation time 8463103101 ps
CPU time 7.72 seconds
Started Apr 18 01:15:51 PM PDT 24
Finished Apr 18 01:15:59 PM PDT 24
Peak memory 204036 kb
Host smart-0d3bbd64-3465-42af-83e0-f5c3aa24c4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13474
8756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.134748756
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.757132431
Short name T862
Test name
Test status
Simulation time 8379929253 ps
CPU time 7.63 seconds
Started Apr 18 01:15:42 PM PDT 24
Finished Apr 18 01:15:51 PM PDT 24
Peak memory 203900 kb
Host smart-53bef699-cb25-444f-a7dc-c2be6aaa0db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75713
2431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.757132431
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_enable.1605114515
Short name T698
Test name
Test status
Simulation time 8376543306 ps
CPU time 7.94 seconds
Started Apr 18 01:15:49 PM PDT 24
Finished Apr 18 01:15:57 PM PDT 24
Peak memory 204004 kb
Host smart-de435e66-5926-4f0e-9a7a-897d4b695810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16051
14515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.1605114515
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.1768613660
Short name T1171
Test name
Test status
Simulation time 172734411 ps
CPU time 1.53 seconds
Started Apr 18 01:15:53 PM PDT 24
Finished Apr 18 01:15:55 PM PDT 24
Peak memory 204048 kb
Host smart-ae8a151f-4e60-44bf-9b55-9eae1e4fc14e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17686
13660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1768613660
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.873403716
Short name T1256
Test name
Test status
Simulation time 8439742959 ps
CPU time 9.39 seconds
Started Apr 18 01:15:51 PM PDT 24
Finished Apr 18 01:16:01 PM PDT 24
Peak memory 204020 kb
Host smart-957c844b-2058-4361-a4d7-76acca7e6324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87340
3716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.873403716
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2396228064
Short name T178
Test name
Test status
Simulation time 8367427019 ps
CPU time 9.13 seconds
Started Apr 18 01:15:53 PM PDT 24
Finished Apr 18 01:16:02 PM PDT 24
Peak memory 203976 kb
Host smart-3f9d67db-a226-4992-8dc2-1bc4f0fdfd50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23962
28064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2396228064
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.4286729082
Short name T1115
Test name
Test status
Simulation time 8473150371 ps
CPU time 7.71 seconds
Started Apr 18 01:15:51 PM PDT 24
Finished Apr 18 01:15:59 PM PDT 24
Peak memory 203944 kb
Host smart-1b950c6c-3b25-4f87-ac13-d4d5a51bb742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42867
29082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.4286729082
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.2186768777
Short name T375
Test name
Test status
Simulation time 8418917582 ps
CPU time 8.57 seconds
Started Apr 18 01:15:51 PM PDT 24
Finished Apr 18 01:16:00 PM PDT 24
Peak memory 204012 kb
Host smart-37ac97ca-1d0c-4d64-b855-8f4d034413c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21867
68777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.2186768777
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3990382401
Short name T738
Test name
Test status
Simulation time 8375154040 ps
CPU time 8.66 seconds
Started Apr 18 01:15:50 PM PDT 24
Finished Apr 18 01:16:00 PM PDT 24
Peak memory 203868 kb
Host smart-5159add6-8cb4-4105-88a6-f4fd2b5f92c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39903
82401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3990382401
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.1567907859
Short name T694
Test name
Test status
Simulation time 8415560001 ps
CPU time 7.57 seconds
Started Apr 18 01:15:53 PM PDT 24
Finished Apr 18 01:16:01 PM PDT 24
Peak memory 204044 kb
Host smart-a859c3b8-ecfb-4373-b62f-942f5955b97c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15679
07859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.1567907859
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.3708524183
Short name T789
Test name
Test status
Simulation time 8440999150 ps
CPU time 7.85 seconds
Started Apr 18 01:15:50 PM PDT 24
Finished Apr 18 01:15:59 PM PDT 24
Peak memory 203920 kb
Host smart-7ec90d6f-ba39-4e1c-b926-9d296e79cde0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37085
24183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.3708524183
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.3090249648
Short name T1272
Test name
Test status
Simulation time 8427256357 ps
CPU time 7.92 seconds
Started Apr 18 01:15:50 PM PDT 24
Finished Apr 18 01:15:59 PM PDT 24
Peak memory 204024 kb
Host smart-b4a55c91-e595-45a3-9fe0-09c2ecb9e6c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30902
49648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.3090249648
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.92648136
Short name T193
Test name
Test status
Simulation time 8377486187 ps
CPU time 9.94 seconds
Started Apr 18 01:15:50 PM PDT 24
Finished Apr 18 01:16:01 PM PDT 24
Peak memory 204020 kb
Host smart-819f8f19-4bd0-4e4d-a493-d356b5066a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92648
136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.92648136
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.2167009414
Short name T1312
Test name
Test status
Simulation time 8432109627 ps
CPU time 7.88 seconds
Started Apr 18 01:15:51 PM PDT 24
Finished Apr 18 01:16:00 PM PDT 24
Peak memory 204024 kb
Host smart-25802b96-4d4c-4219-b149-f291cf8f21d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21670
09414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.2167009414
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.3920406587
Short name T1320
Test name
Test status
Simulation time 65978027 ps
CPU time 0.7 seconds
Started Apr 18 01:15:51 PM PDT 24
Finished Apr 18 01:15:53 PM PDT 24
Peak memory 203872 kb
Host smart-a1214031-cc70-4ba5-abcf-1efe9f1bbd15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39204
06587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.3920406587
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.2063490628
Short name T1158
Test name
Test status
Simulation time 16297658513 ps
CPU time 28.4 seconds
Started Apr 18 01:15:53 PM PDT 24
Finished Apr 18 01:16:22 PM PDT 24
Peak memory 204264 kb
Host smart-f1ecfb74-c40f-4130-9901-19d64f12a1ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20634
90628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.2063490628
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.1209169432
Short name T1350
Test name
Test status
Simulation time 8418890552 ps
CPU time 7.76 seconds
Started Apr 18 01:15:52 PM PDT 24
Finished Apr 18 01:16:00 PM PDT 24
Peak memory 204064 kb
Host smart-0e473d02-20b0-4bae-af64-03b6be38c015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12091
69432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.1209169432
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.140058950
Short name T129
Test name
Test status
Simulation time 8384288490 ps
CPU time 8.13 seconds
Started Apr 18 01:15:56 PM PDT 24
Finished Apr 18 01:16:06 PM PDT 24
Peak memory 204012 kb
Host smart-ccc646f6-6313-4791-96a6-558df267ab7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14005
8950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.140058950
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.2487589097
Short name T978
Test name
Test status
Simulation time 8388944257 ps
CPU time 7.71 seconds
Started Apr 18 01:15:51 PM PDT 24
Finished Apr 18 01:16:00 PM PDT 24
Peak memory 203940 kb
Host smart-02077cb5-d916-42d4-8c76-c832321e150c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24875
89097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.2487589097
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.2387961697
Short name T159
Test name
Test status
Simulation time 8375688816 ps
CPU time 7.58 seconds
Started Apr 18 01:15:51 PM PDT 24
Finished Apr 18 01:15:59 PM PDT 24
Peak memory 204040 kb
Host smart-07e32ee9-dc79-4088-89ae-3d74c1edeb8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23879
61697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.2387961697
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.762610233
Short name T830
Test name
Test status
Simulation time 8374153933 ps
CPU time 9.05 seconds
Started Apr 18 01:15:52 PM PDT 24
Finished Apr 18 01:16:02 PM PDT 24
Peak memory 204012 kb
Host smart-aa295aa4-b72f-400d-a813-5f0cbcaae357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76261
0233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.762610233
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.1055875469
Short name T444
Test name
Test status
Simulation time 8457418134 ps
CPU time 10.53 seconds
Started Apr 18 01:15:44 PM PDT 24
Finished Apr 18 01:15:54 PM PDT 24
Peak memory 203984 kb
Host smart-cde64ad6-bf3d-44a6-8f53-d7c0579ea973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10558
75469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.1055875469
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.1411660595
Short name T680
Test name
Test status
Simulation time 8395719247 ps
CPU time 8 seconds
Started Apr 18 01:15:51 PM PDT 24
Finished Apr 18 01:16:00 PM PDT 24
Peak memory 203992 kb
Host smart-ae4d91a4-24d2-4916-90fa-05fabc283418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14116
60595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.1411660595
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.3501861776
Short name T1366
Test name
Test status
Simulation time 8391802565 ps
CPU time 7.98 seconds
Started Apr 18 01:15:53 PM PDT 24
Finished Apr 18 01:16:01 PM PDT 24
Peak memory 204048 kb
Host smart-ca5854f9-3a1f-420d-b27c-b8523372de37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35018
61776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.3501861776
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.1501236780
Short name T432
Test name
Test status
Simulation time 8464801082 ps
CPU time 8 seconds
Started Apr 18 01:16:05 PM PDT 24
Finished Apr 18 01:16:14 PM PDT 24
Peak memory 204036 kb
Host smart-d393c57b-f7a8-4960-90a4-721261b20dd4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1501236780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.1501236780
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.2854413398
Short name T305
Test name
Test status
Simulation time 8378605843 ps
CPU time 8.45 seconds
Started Apr 18 01:15:59 PM PDT 24
Finished Apr 18 01:16:08 PM PDT 24
Peak memory 204020 kb
Host smart-7c694c28-b44f-49e7-9d76-607aafb959e5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2854413398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.2854413398
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.4206321294
Short name T344
Test name
Test status
Simulation time 8463096098 ps
CPU time 8.33 seconds
Started Apr 18 01:15:56 PM PDT 24
Finished Apr 18 01:16:06 PM PDT 24
Peak memory 204040 kb
Host smart-4c76e586-909f-4d45-a276-8e32159e3adc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42063
21294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.4206321294
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.4146996309
Short name T83
Test name
Test status
Simulation time 8376234798 ps
CPU time 8.22 seconds
Started Apr 18 01:15:52 PM PDT 24
Finished Apr 18 01:16:01 PM PDT 24
Peak memory 203940 kb
Host smart-15d26b94-b840-4902-9540-295b1338f81a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41469
96309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.4146996309
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_enable.2193765244
Short name T1295
Test name
Test status
Simulation time 8410258851 ps
CPU time 7.56 seconds
Started Apr 18 01:15:49 PM PDT 24
Finished Apr 18 01:15:57 PM PDT 24
Peak memory 204020 kb
Host smart-00fd9ad7-5f07-4247-a2c5-9f898ea69072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21937
65244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2193765244
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.1015285707
Short name T1373
Test name
Test status
Simulation time 140083876 ps
CPU time 1.76 seconds
Started Apr 18 01:15:56 PM PDT 24
Finished Apr 18 01:16:00 PM PDT 24
Peak memory 204136 kb
Host smart-2d53111c-74b8-4edf-9d83-16787c2921b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10152
85707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.1015285707
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.1298947651
Short name T1163
Test name
Test status
Simulation time 8474246265 ps
CPU time 8.15 seconds
Started Apr 18 01:15:57 PM PDT 24
Finished Apr 18 01:16:06 PM PDT 24
Peak memory 204044 kb
Host smart-cc2617fd-8c92-4ab2-8ce6-8addb8ddbc16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12989
47651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.1298947651
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.3183107044
Short name T179
Test name
Test status
Simulation time 8374248967 ps
CPU time 9.41 seconds
Started Apr 18 01:15:57 PM PDT 24
Finished Apr 18 01:16:08 PM PDT 24
Peak memory 203972 kb
Host smart-f3c8ed22-1add-4eed-9b12-ded0232d4bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31831
07044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.3183107044
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.1202193946
Short name T606
Test name
Test status
Simulation time 8420045181 ps
CPU time 10.69 seconds
Started Apr 18 01:15:51 PM PDT 24
Finished Apr 18 01:16:03 PM PDT 24
Peak memory 203996 kb
Host smart-523a9202-943d-4167-b957-40f9e87dcd00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12021
93946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.1202193946
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3632282491
Short name T536
Test name
Test status
Simulation time 8385174601 ps
CPU time 7.97 seconds
Started Apr 18 01:15:50 PM PDT 24
Finished Apr 18 01:15:58 PM PDT 24
Peak memory 203964 kb
Host smart-2979f3f6-82b8-4c8d-9b18-f473c0de899a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36322
82491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3632282491
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.3986936664
Short name T511
Test name
Test status
Simulation time 8435454952 ps
CPU time 9.35 seconds
Started Apr 18 01:15:52 PM PDT 24
Finished Apr 18 01:16:02 PM PDT 24
Peak memory 204000 kb
Host smart-578990c2-c9a0-41fd-832d-b25594d5db61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39869
36664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.3986936664
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.1808014597
Short name T838
Test name
Test status
Simulation time 8409865125 ps
CPU time 8.14 seconds
Started Apr 18 01:15:57 PM PDT 24
Finished Apr 18 01:16:06 PM PDT 24
Peak memory 204248 kb
Host smart-41e13344-fd69-4785-bac5-ac4ca83df4ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18080
14597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.1808014597
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.3527018167
Short name T1380
Test name
Test status
Simulation time 8398157239 ps
CPU time 7.8 seconds
Started Apr 18 01:15:57 PM PDT 24
Finished Apr 18 01:16:06 PM PDT 24
Peak memory 204044 kb
Host smart-d8747b67-a94c-422e-93f1-fcb523b60508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35270
18167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.3527018167
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.1460678421
Short name T1229
Test name
Test status
Simulation time 8403495291 ps
CPU time 8.28 seconds
Started Apr 18 01:15:59 PM PDT 24
Finished Apr 18 01:16:08 PM PDT 24
Peak memory 203928 kb
Host smart-570f7976-eca5-4da0-aee2-1dd59f9075e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14606
78421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.1460678421
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.1944666116
Short name T489
Test name
Test status
Simulation time 122465264 ps
CPU time 0.71 seconds
Started Apr 18 01:15:58 PM PDT 24
Finished Apr 18 01:16:00 PM PDT 24
Peak memory 203852 kb
Host smart-af395053-77ae-4a95-814b-78986faa1210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19446
66116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.1944666116
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.726590389
Short name T87
Test name
Test status
Simulation time 27253023030 ps
CPU time 51.19 seconds
Started Apr 18 01:16:00 PM PDT 24
Finished Apr 18 01:16:54 PM PDT 24
Peak memory 204284 kb
Host smart-8164cbcc-865c-49b2-a49f-5be79d4eed11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72659
0389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.726590389
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.2565295199
Short name T940
Test name
Test status
Simulation time 8404393511 ps
CPU time 8.74 seconds
Started Apr 18 01:15:57 PM PDT 24
Finished Apr 18 01:16:07 PM PDT 24
Peak memory 204080 kb
Host smart-cf6299f6-a0d8-4be6-95d4-088373f197bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25652
95199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.2565295199
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.1240120860
Short name T571
Test name
Test status
Simulation time 8472440212 ps
CPU time 8.53 seconds
Started Apr 18 01:15:58 PM PDT 24
Finished Apr 18 01:16:08 PM PDT 24
Peak memory 204028 kb
Host smart-c23ddfe5-7f91-4037-bad0-910614b16d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12401
20860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.1240120860
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.3986208018
Short name T661
Test name
Test status
Simulation time 8425557159 ps
CPU time 8.09 seconds
Started Apr 18 01:15:58 PM PDT 24
Finished Apr 18 01:16:07 PM PDT 24
Peak memory 203944 kb
Host smart-cd02e57f-fa61-4a12-9c46-ee0a2e105a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39862
08018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.3986208018
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.2623121015
Short name T1174
Test name
Test status
Simulation time 8387159752 ps
CPU time 9.75 seconds
Started Apr 18 01:16:06 PM PDT 24
Finished Apr 18 01:16:16 PM PDT 24
Peak memory 204040 kb
Host smart-e85712d6-fbb8-49d0-a949-381b026b569c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26231
21015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.2623121015
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2762876307
Short name T462
Test name
Test status
Simulation time 8374918681 ps
CPU time 8.34 seconds
Started Apr 18 01:15:58 PM PDT 24
Finished Apr 18 01:16:07 PM PDT 24
Peak memory 204020 kb
Host smart-7bc8e7c1-edf5-4c43-9a15-cdd701a20787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27628
76307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2762876307
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3054497404
Short name T588
Test name
Test status
Simulation time 8461530721 ps
CPU time 8.19 seconds
Started Apr 18 01:16:01 PM PDT 24
Finished Apr 18 01:16:12 PM PDT 24
Peak memory 204036 kb
Host smart-71777f7a-66be-4d94-bb48-ca3531c1afc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30544
97404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3054497404
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.807599168
Short name T339
Test name
Test status
Simulation time 8381463013 ps
CPU time 7.93 seconds
Started Apr 18 01:16:00 PM PDT 24
Finished Apr 18 01:16:11 PM PDT 24
Peak memory 204004 kb
Host smart-e1170cf1-86cc-42f7-a8f3-4ac27bf36d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80759
9168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.807599168
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.624113982
Short name T650
Test name
Test status
Simulation time 8394595450 ps
CPU time 8.33 seconds
Started Apr 18 01:15:56 PM PDT 24
Finished Apr 18 01:16:06 PM PDT 24
Peak memory 203920 kb
Host smart-d959c102-aec3-4ade-bbdd-0acd93ee6e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62411
3982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.624113982
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.max_length_in_transaction.714190516
Short name T1334
Test name
Test status
Simulation time 8462471304 ps
CPU time 8.01 seconds
Started Apr 18 01:15:56 PM PDT 24
Finished Apr 18 01:16:05 PM PDT 24
Peak memory 203924 kb
Host smart-54ba68a2-7f67-4427-be02-5da0ae36e504
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=714190516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.714190516
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.2397976328
Short name T796
Test name
Test status
Simulation time 8395705875 ps
CPU time 7.78 seconds
Started Apr 18 01:15:58 PM PDT 24
Finished Apr 18 01:16:07 PM PDT 24
Peak memory 204008 kb
Host smart-b01ba16d-66b3-4c97-bd66-0ff3445066f4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2397976328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.2397976328
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.3362564257
Short name T758
Test name
Test status
Simulation time 8427566747 ps
CPU time 8.23 seconds
Started Apr 18 01:16:05 PM PDT 24
Finished Apr 18 01:16:14 PM PDT 24
Peak memory 204024 kb
Host smart-303f195b-f2eb-4abb-abda-f28ef1f26f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33625
64257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.3362564257
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.2308844375
Short name T719
Test name
Test status
Simulation time 8390100467 ps
CPU time 7.88 seconds
Started Apr 18 01:16:07 PM PDT 24
Finished Apr 18 01:16:16 PM PDT 24
Peak memory 203572 kb
Host smart-756a0d26-7662-46e7-9240-803638c4432e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23088
44375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2308844375
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_enable.2688779149
Short name T491
Test name
Test status
Simulation time 8372426834 ps
CPU time 8.72 seconds
Started Apr 18 01:15:58 PM PDT 24
Finished Apr 18 01:16:08 PM PDT 24
Peak memory 204084 kb
Host smart-2269a7d6-8ae6-4bfc-894a-28720b40065a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26887
79149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.2688779149
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.3523804315
Short name T591
Test name
Test status
Simulation time 58127109 ps
CPU time 1.37 seconds
Started Apr 18 01:16:07 PM PDT 24
Finished Apr 18 01:16:09 PM PDT 24
Peak memory 203660 kb
Host smart-479281ee-261b-4437-9fc2-82fb4fe8e632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35238
04315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.3523804315
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.1066272524
Short name T1067
Test name
Test status
Simulation time 8419717223 ps
CPU time 7.84 seconds
Started Apr 18 01:15:57 PM PDT 24
Finished Apr 18 01:16:06 PM PDT 24
Peak memory 204036 kb
Host smart-30108a86-c8f7-4468-a131-96b58341771f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10662
72524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.1066272524
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.2434450776
Short name T7
Test name
Test status
Simulation time 8365599120 ps
CPU time 8.86 seconds
Started Apr 18 01:15:56 PM PDT 24
Finished Apr 18 01:16:06 PM PDT 24
Peak memory 204060 kb
Host smart-a284e157-5240-4005-ba2a-29176fe9ef18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24344
50776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.2434450776
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.312717504
Short name T1261
Test name
Test status
Simulation time 8465375784 ps
CPU time 10.22 seconds
Started Apr 18 01:15:57 PM PDT 24
Finished Apr 18 01:16:08 PM PDT 24
Peak memory 204004 kb
Host smart-7045da7c-64eb-4833-8617-9402b8207a07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31271
7504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.312717504
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.3439312138
Short name T1313
Test name
Test status
Simulation time 8413688061 ps
CPU time 9.38 seconds
Started Apr 18 01:15:57 PM PDT 24
Finished Apr 18 01:16:08 PM PDT 24
Peak memory 204016 kb
Host smart-b0fba2ab-4544-4df8-926b-334a9e3ed13b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34393
12138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.3439312138
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.669270386
Short name T371
Test name
Test status
Simulation time 8385809874 ps
CPU time 9.85 seconds
Started Apr 18 01:16:06 PM PDT 24
Finished Apr 18 01:16:17 PM PDT 24
Peak memory 204044 kb
Host smart-dfc957f5-b27d-4968-91d2-9850b128e741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66927
0386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.669270386
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.1191610556
Short name T1133
Test name
Test status
Simulation time 8407214541 ps
CPU time 8.18 seconds
Started Apr 18 01:16:06 PM PDT 24
Finished Apr 18 01:16:15 PM PDT 24
Peak memory 203960 kb
Host smart-64d5af9e-b163-402a-a772-342a6e0ccbc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11916
10556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.1191610556
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.3261375183
Short name T335
Test name
Test status
Simulation time 8398160504 ps
CPU time 7.48 seconds
Started Apr 18 01:15:58 PM PDT 24
Finished Apr 18 01:16:07 PM PDT 24
Peak memory 204000 kb
Host smart-a9299e67-6589-45d4-8ae1-9a954c8aeff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32613
75183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.3261375183
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.1756032301
Short name T1090
Test name
Test status
Simulation time 8420366206 ps
CPU time 8.02 seconds
Started Apr 18 01:16:01 PM PDT 24
Finished Apr 18 01:16:12 PM PDT 24
Peak memory 203908 kb
Host smart-4aff745b-4544-46bd-ae1c-3df6fa30d373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17560
32301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.1756032301
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.2671731609
Short name T154
Test name
Test status
Simulation time 8456190147 ps
CPU time 10.29 seconds
Started Apr 18 01:15:56 PM PDT 24
Finished Apr 18 01:16:08 PM PDT 24
Peak memory 203980 kb
Host smart-73a57fd2-dd49-48f4-9417-b0153d2f20eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26717
31609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.2671731609
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3595228746
Short name T564
Test name
Test status
Simulation time 8372867756 ps
CPU time 7.37 seconds
Started Apr 18 01:16:03 PM PDT 24
Finished Apr 18 01:16:12 PM PDT 24
Peak memory 204032 kb
Host smart-6629d1c3-1f61-462c-a697-91f55a009427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35952
28746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3595228746
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.1544012323
Short name T667
Test name
Test status
Simulation time 169433450 ps
CPU time 0.76 seconds
Started Apr 18 01:16:07 PM PDT 24
Finished Apr 18 01:16:09 PM PDT 24
Peak memory 203912 kb
Host smart-a79824bb-7fb2-44c4-a235-8649fa99c3cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15440
12323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.1544012323
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.689710147
Short name T228
Test name
Test status
Simulation time 25110886794 ps
CPU time 46.4 seconds
Started Apr 18 01:16:00 PM PDT 24
Finished Apr 18 01:16:49 PM PDT 24
Peak memory 204316 kb
Host smart-138a04f1-ba25-433f-8386-2ace2d8e04a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68971
0147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.689710147
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1682269530
Short name T737
Test name
Test status
Simulation time 8407730923 ps
CPU time 8.4 seconds
Started Apr 18 01:16:03 PM PDT 24
Finished Apr 18 01:16:13 PM PDT 24
Peak memory 204036 kb
Host smart-37ada76c-bbb5-4bda-a0e9-56c7e6dc79c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16822
69530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1682269530
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.3941108401
Short name T901
Test name
Test status
Simulation time 8414524147 ps
CPU time 7.93 seconds
Started Apr 18 01:16:01 PM PDT 24
Finished Apr 18 01:16:12 PM PDT 24
Peak memory 203592 kb
Host smart-8464d5e2-d7e6-45de-8b8f-a28695ed8377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39411
08401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.3941108401
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.298353370
Short name T542
Test name
Test status
Simulation time 8390781655 ps
CPU time 8.41 seconds
Started Apr 18 01:16:24 PM PDT 24
Finished Apr 18 01:16:33 PM PDT 24
Peak memory 203864 kb
Host smart-2257d9c8-3fd9-4141-a484-3a0e210151c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29835
3370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.298353370
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.3542443554
Short name T21
Test name
Test status
Simulation time 8406447262 ps
CPU time 10.37 seconds
Started Apr 18 01:16:00 PM PDT 24
Finished Apr 18 01:16:14 PM PDT 24
Peak memory 203908 kb
Host smart-38f2853d-b8cc-4131-b05f-8437f046c7c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35424
43554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.3542443554
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2812510103
Short name T772
Test name
Test status
Simulation time 8404254633 ps
CPU time 7.65 seconds
Started Apr 18 01:15:55 PM PDT 24
Finished Apr 18 01:16:03 PM PDT 24
Peak memory 204040 kb
Host smart-825f8dc3-65d0-46f6-82ed-0dd3e6f5257b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28125
10103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2812510103
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.4043386377
Short name T595
Test name
Test status
Simulation time 8453029671 ps
CPU time 7.91 seconds
Started Apr 18 01:16:00 PM PDT 24
Finished Apr 18 01:16:10 PM PDT 24
Peak memory 204032 kb
Host smart-94bc3c7e-4f63-45c7-8b07-979f1691cc28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40433
86377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.4043386377
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.2100896842
Short name T682
Test name
Test status
Simulation time 8376682071 ps
CPU time 8.23 seconds
Started Apr 18 01:15:57 PM PDT 24
Finished Apr 18 01:16:06 PM PDT 24
Peak memory 203936 kb
Host smart-d1b4b739-cbf9-4401-83b2-a4df0017c65b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21008
96842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.2100896842
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.435766324
Short name T795
Test name
Test status
Simulation time 8409724353 ps
CPU time 7.6 seconds
Started Apr 18 01:16:03 PM PDT 24
Finished Apr 18 01:16:12 PM PDT 24
Peak memory 204032 kb
Host smart-8781d7b2-5025-434c-9a32-26ed9d8bdca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43576
6324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.435766324
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.max_length_in_transaction.545206003
Short name T683
Test name
Test status
Simulation time 8460425200 ps
CPU time 7.83 seconds
Started Apr 18 01:16:08 PM PDT 24
Finished Apr 18 01:16:16 PM PDT 24
Peak memory 204052 kb
Host smart-0439461c-d744-4a95-9c97-1ecaefcc0782
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=545206003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.545206003
Directory /workspace/25.max_length_in_transaction/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.1878155526
Short name T801
Test name
Test status
Simulation time 8377400013 ps
CPU time 7.62 seconds
Started Apr 18 01:15:59 PM PDT 24
Finished Apr 18 01:16:10 PM PDT 24
Peak memory 203304 kb
Host smart-7d7d2e1d-3559-4dbb-9847-6cf6fcd2c1b8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1878155526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.1878155526
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.2682513428
Short name T1185
Test name
Test status
Simulation time 8423160037 ps
CPU time 8.5 seconds
Started Apr 18 01:15:59 PM PDT 24
Finished Apr 18 01:16:08 PM PDT 24
Peak memory 203928 kb
Host smart-d337fdb0-ec95-4355-9373-a87e07d342f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26825
13428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.2682513428
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.207728711
Short name T669
Test name
Test status
Simulation time 8393726967 ps
CPU time 7.98 seconds
Started Apr 18 01:16:04 PM PDT 24
Finished Apr 18 01:16:13 PM PDT 24
Peak memory 204036 kb
Host smart-b75bf854-deec-4f30-a1fd-b4ce9efb5339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20772
8711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.207728711
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_enable.1558057368
Short name T728
Test name
Test status
Simulation time 8373510924 ps
CPU time 7.81 seconds
Started Apr 18 01:16:06 PM PDT 24
Finished Apr 18 01:16:15 PM PDT 24
Peak memory 204044 kb
Host smart-3c098171-c631-477f-8e85-fb0a908ca588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15580
57368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.1558057368
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.3006775589
Short name T54
Test name
Test status
Simulation time 298420732 ps
CPU time 2.26 seconds
Started Apr 18 01:16:03 PM PDT 24
Finished Apr 18 01:16:06 PM PDT 24
Peak memory 204104 kb
Host smart-0d351326-5de6-4cce-92ad-73d08572ec6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30067
75589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.3006775589
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.1024077919
Short name T962
Test name
Test status
Simulation time 8415449747 ps
CPU time 8.18 seconds
Started Apr 18 01:16:03 PM PDT 24
Finished Apr 18 01:16:12 PM PDT 24
Peak memory 203572 kb
Host smart-ff8bc0b3-b59e-4c6d-94f8-d49b5f077682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10240
77919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.1024077919
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.2784526298
Short name T782
Test name
Test status
Simulation time 8362789976 ps
CPU time 10.04 seconds
Started Apr 18 01:16:03 PM PDT 24
Finished Apr 18 01:16:15 PM PDT 24
Peak memory 203936 kb
Host smart-b989a886-6023-4de2-8609-6303c449a68c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27845
26298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.2784526298
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.739095860
Short name T778
Test name
Test status
Simulation time 8403426326 ps
CPU time 8.22 seconds
Started Apr 18 01:15:59 PM PDT 24
Finished Apr 18 01:16:09 PM PDT 24
Peak memory 204032 kb
Host smart-f4a2cfcd-da33-4ab0-8744-c6cfdb7de889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73909
5860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.739095860
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.769923942
Short name T1206
Test name
Test status
Simulation time 8414805960 ps
CPU time 8.06 seconds
Started Apr 18 01:16:00 PM PDT 24
Finished Apr 18 01:16:11 PM PDT 24
Peak memory 204028 kb
Host smart-76162baf-5f44-446b-96ea-bb0a73613583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76992
3942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.769923942
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.1780159051
Short name T378
Test name
Test status
Simulation time 8373323426 ps
CPU time 8.59 seconds
Started Apr 18 01:15:58 PM PDT 24
Finished Apr 18 01:16:08 PM PDT 24
Peak memory 203864 kb
Host smart-42f96e09-ea9d-4e53-b0c1-3ccad05587ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17801
59051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.1780159051
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.3760555926
Short name T1360
Test name
Test status
Simulation time 8428421162 ps
CPU time 9.94 seconds
Started Apr 18 01:16:00 PM PDT 24
Finished Apr 18 01:16:13 PM PDT 24
Peak memory 203972 kb
Host smart-648e14a2-82d8-4726-bd52-17a4cf2e4ea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37605
55926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.3760555926
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.3862279517
Short name T631
Test name
Test status
Simulation time 8395230535 ps
CPU time 8.09 seconds
Started Apr 18 01:16:01 PM PDT 24
Finished Apr 18 01:16:12 PM PDT 24
Peak memory 203568 kb
Host smart-fa1ca618-84fd-4ceb-b5dd-f5d365a7ca48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38622
79517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.3862279517
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.1882370099
Short name T329
Test name
Test status
Simulation time 8462795725 ps
CPU time 7.67 seconds
Started Apr 18 01:16:07 PM PDT 24
Finished Apr 18 01:16:15 PM PDT 24
Peak memory 204044 kb
Host smart-75ffbce1-6d3a-4c89-ad2e-50af2a8875fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18823
70099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.1882370099
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.3202385478
Short name T162
Test name
Test status
Simulation time 8414404901 ps
CPU time 8.22 seconds
Started Apr 18 01:16:05 PM PDT 24
Finished Apr 18 01:16:15 PM PDT 24
Peak memory 204028 kb
Host smart-00666837-db68-4de8-8514-4d2e59164074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32023
85478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.3202385478
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.102602520
Short name T363
Test name
Test status
Simulation time 8409220918 ps
CPU time 8.88 seconds
Started Apr 18 01:16:05 PM PDT 24
Finished Apr 18 01:16:16 PM PDT 24
Peak memory 204024 kb
Host smart-b653b2a4-0115-4b4d-8159-32b7d9d24e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10260
2520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.102602520
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.4033677386
Short name T617
Test name
Test status
Simulation time 53460910 ps
CPU time 0.67 seconds
Started Apr 18 01:16:00 PM PDT 24
Finished Apr 18 01:16:04 PM PDT 24
Peak memory 203220 kb
Host smart-3fd9ab17-c419-4eb3-b949-4a118851eed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40336
77386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.4033677386
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.4046618097
Short name T803
Test name
Test status
Simulation time 24569774377 ps
CPU time 51.93 seconds
Started Apr 18 01:16:00 PM PDT 24
Finished Apr 18 01:16:55 PM PDT 24
Peak memory 203584 kb
Host smart-c6ec3478-2fe7-4b08-8044-d8056ca2d745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40466
18097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.4046618097
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.1737649351
Short name T659
Test name
Test status
Simulation time 8423541731 ps
CPU time 7.8 seconds
Started Apr 18 01:16:00 PM PDT 24
Finished Apr 18 01:16:11 PM PDT 24
Peak memory 203976 kb
Host smart-4cbb93d7-f855-4763-be62-787899dbe88c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17376
49351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.1737649351
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.3888059413
Short name T868
Test name
Test status
Simulation time 8408036517 ps
CPU time 8.4 seconds
Started Apr 18 01:16:03 PM PDT 24
Finished Apr 18 01:16:13 PM PDT 24
Peak memory 203944 kb
Host smart-a2dbf1e6-f6e8-4dc1-b556-5a0cd72140d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38880
59413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.3888059413
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.2528886841
Short name T48
Test name
Test status
Simulation time 8406851372 ps
CPU time 7.82 seconds
Started Apr 18 01:16:05 PM PDT 24
Finished Apr 18 01:16:14 PM PDT 24
Peak memory 204024 kb
Host smart-52a8ef29-1203-4e3e-aee9-bb888d31a705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25288
86841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.2528886841
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_smoke.21660170
Short name T1075
Test name
Test status
Simulation time 8437566913 ps
CPU time 8.63 seconds
Started Apr 18 01:15:59 PM PDT 24
Finished Apr 18 01:16:08 PM PDT 24
Peak memory 203956 kb
Host smart-b59a0cc3-4830-41d5-ba83-a0e161bc8e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21660
170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.21660170
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3458339658
Short name T315
Test name
Test status
Simulation time 8377369013 ps
CPU time 8.86 seconds
Started Apr 18 01:15:59 PM PDT 24
Finished Apr 18 01:16:11 PM PDT 24
Peak memory 203968 kb
Host smart-bb5c20b9-969f-4ff1-bf11-9a6eb33dcd09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34583
39658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3458339658
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.3253419322
Short name T1259
Test name
Test status
Simulation time 8388717831 ps
CPU time 8.4 seconds
Started Apr 18 01:16:01 PM PDT 24
Finished Apr 18 01:16:12 PM PDT 24
Peak memory 203296 kb
Host smart-1137633a-d32c-42d2-8fa3-337655eebc1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32534
19322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.3253419322
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.max_length_in_transaction.1667000384
Short name T1069
Test name
Test status
Simulation time 8470401866 ps
CPU time 7.84 seconds
Started Apr 18 01:16:50 PM PDT 24
Finished Apr 18 01:16:59 PM PDT 24
Peak memory 203960 kb
Host smart-de425459-fb63-454a-a5e3-3630288b6f74
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1667000384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.1667000384
Directory /workspace/26.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.316049376
Short name T1098
Test name
Test status
Simulation time 8378923940 ps
CPU time 7.83 seconds
Started Apr 18 01:16:07 PM PDT 24
Finished Apr 18 01:16:16 PM PDT 24
Peak memory 204016 kb
Host smart-c1e16a3e-27bf-43e8-a816-850dcba60aef
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=316049376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.316049376
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.185321799
Short name T850
Test name
Test status
Simulation time 8447423961 ps
CPU time 8.53 seconds
Started Apr 18 01:16:06 PM PDT 24
Finished Apr 18 01:16:16 PM PDT 24
Peak memory 204020 kb
Host smart-86915c06-8fba-418f-9fcb-7a006fca54f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18532
1799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.185321799
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.2639649497
Short name T291
Test name
Test status
Simulation time 8376658882 ps
CPU time 8.06 seconds
Started Apr 18 01:16:04 PM PDT 24
Finished Apr 18 01:16:13 PM PDT 24
Peak memory 204008 kb
Host smart-62496aae-ac07-420c-b0ea-d715bbc35159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26396
49497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.2639649497
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_enable.2865843785
Short name T421
Test name
Test status
Simulation time 8378530795 ps
CPU time 7.41 seconds
Started Apr 18 01:16:06 PM PDT 24
Finished Apr 18 01:16:15 PM PDT 24
Peak memory 204016 kb
Host smart-0bb58cf6-1aab-416b-8657-1720251de5f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28658
43785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.2865843785
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.1541042390
Short name T1094
Test name
Test status
Simulation time 156723025 ps
CPU time 1.79 seconds
Started Apr 18 01:16:04 PM PDT 24
Finished Apr 18 01:16:07 PM PDT 24
Peak memory 204132 kb
Host smart-961de5ae-4ab9-43d2-940f-438138580d2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15410
42390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.1541042390
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.2213805292
Short name T215
Test name
Test status
Simulation time 8374299798 ps
CPU time 9.6 seconds
Started Apr 18 01:16:07 PM PDT 24
Finished Apr 18 01:16:17 PM PDT 24
Peak memory 204012 kb
Host smart-40b2a3c7-1a0a-4ced-833f-79679e1a02d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22138
05292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.2213805292
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.2880617026
Short name T195
Test name
Test status
Simulation time 8368846165 ps
CPU time 7.44 seconds
Started Apr 18 01:16:07 PM PDT 24
Finished Apr 18 01:16:15 PM PDT 24
Peak memory 204016 kb
Host smart-3d63f5cc-1aa6-453f-a238-6904110d31d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28806
17026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2880617026
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.542205312
Short name T136
Test name
Test status
Simulation time 8411156625 ps
CPU time 7.48 seconds
Started Apr 18 01:16:06 PM PDT 24
Finished Apr 18 01:16:15 PM PDT 24
Peak memory 204084 kb
Host smart-4a4c60b4-2aa1-4d44-84af-5e42372df73f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54220
5312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.542205312
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.764705428
Short name T673
Test name
Test status
Simulation time 8449180550 ps
CPU time 8.14 seconds
Started Apr 18 01:16:02 PM PDT 24
Finished Apr 18 01:16:12 PM PDT 24
Peak memory 204020 kb
Host smart-b1afa4cf-b0a5-4f60-8dc9-f34da3a6d615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76470
5428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.764705428
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.933769261
Short name T993
Test name
Test status
Simulation time 8371967115 ps
CPU time 7.71 seconds
Started Apr 18 01:16:04 PM PDT 24
Finished Apr 18 01:16:13 PM PDT 24
Peak memory 204048 kb
Host smart-2947e54f-903f-4486-b067-46a89ba512f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93376
9261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.933769261
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.975032444
Short name T294
Test name
Test status
Simulation time 8417785210 ps
CPU time 7.99 seconds
Started Apr 18 01:16:03 PM PDT 24
Finished Apr 18 01:16:12 PM PDT 24
Peak memory 203968 kb
Host smart-10e2f837-d95e-4709-ab47-571c628f430e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97503
2444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.975032444
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1242004132
Short name T945
Test name
Test status
Simulation time 8406615291 ps
CPU time 8.7 seconds
Started Apr 18 01:16:06 PM PDT 24
Finished Apr 18 01:16:16 PM PDT 24
Peak memory 203996 kb
Host smart-8e3e16f9-16fe-4ed8-8343-cdb6e96653c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12420
04132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1242004132
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.500707681
Short name T647
Test name
Test status
Simulation time 8395167218 ps
CPU time 8.4 seconds
Started Apr 18 01:16:00 PM PDT 24
Finished Apr 18 01:16:12 PM PDT 24
Peak memory 203980 kb
Host smart-1e96c1b5-a829-4836-8d49-b926c1641090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50070
7681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.500707681
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.2195039635
Short name T1215
Test name
Test status
Simulation time 30546675 ps
CPU time 0.66 seconds
Started Apr 18 01:16:02 PM PDT 24
Finished Apr 18 01:16:04 PM PDT 24
Peak memory 203776 kb
Host smart-3e813060-3843-4fd0-a3fc-bdc345bafc20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21950
39635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.2195039635
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.483527544
Short name T509
Test name
Test status
Simulation time 25515622445 ps
CPU time 48.12 seconds
Started Apr 18 01:16:08 PM PDT 24
Finished Apr 18 01:16:57 PM PDT 24
Peak memory 204248 kb
Host smart-5ef53ca5-f5ce-40f9-ad88-ae77c0f637f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48352
7544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.483527544
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.3740945676
Short name T1284
Test name
Test status
Simulation time 8398707169 ps
CPU time 8.16 seconds
Started Apr 18 01:16:05 PM PDT 24
Finished Apr 18 01:16:14 PM PDT 24
Peak memory 204004 kb
Host smart-ad8bb2e3-caf2-4b0a-80f7-ef8f9ac820b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37409
45676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.3740945676
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.186361331
Short name T579
Test name
Test status
Simulation time 8429082702 ps
CPU time 9.2 seconds
Started Apr 18 01:16:01 PM PDT 24
Finished Apr 18 01:16:13 PM PDT 24
Peak memory 204080 kb
Host smart-4b869622-2628-4009-ba8b-51f55231f829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18636
1331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.186361331
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.3605104202
Short name T968
Test name
Test status
Simulation time 8413419524 ps
CPU time 8.85 seconds
Started Apr 18 01:16:04 PM PDT 24
Finished Apr 18 01:16:14 PM PDT 24
Peak memory 203996 kb
Host smart-6cc61787-b2aa-4312-a5a3-6d9673eb84fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36051
04202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.3605104202
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.899532069
Short name T165
Test name
Test status
Simulation time 8372519766 ps
CPU time 8.31 seconds
Started Apr 18 01:16:05 PM PDT 24
Finished Apr 18 01:16:14 PM PDT 24
Peak memory 204012 kb
Host smart-ef9f8455-c56e-4b5a-8fec-5f0791645169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89953
2069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.899532069
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2026811716
Short name T553
Test name
Test status
Simulation time 8402709565 ps
CPU time 7.53 seconds
Started Apr 18 01:16:02 PM PDT 24
Finished Apr 18 01:16:11 PM PDT 24
Peak memory 204004 kb
Host smart-f81e93ea-783e-49f2-8e96-56e9486edd27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20268
11716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2026811716
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.1355130757
Short name T732
Test name
Test status
Simulation time 8455385203 ps
CPU time 9.81 seconds
Started Apr 18 01:16:02 PM PDT 24
Finished Apr 18 01:16:14 PM PDT 24
Peak memory 204036 kb
Host smart-e70a2aa6-22d4-4981-9cae-66c45f652ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13551
30757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.1355130757
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.649614642
Short name T677
Test name
Test status
Simulation time 8393172316 ps
CPU time 8.24 seconds
Started Apr 18 01:16:04 PM PDT 24
Finished Apr 18 01:16:14 PM PDT 24
Peak memory 203940 kb
Host smart-2d885116-adcc-4228-8ef0-64cc0483fbb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64961
4642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.649614642
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.2886818503
Short name T284
Test name
Test status
Simulation time 8393036592 ps
CPU time 8.56 seconds
Started Apr 18 01:16:03 PM PDT 24
Finished Apr 18 01:16:13 PM PDT 24
Peak memory 203904 kb
Host smart-bada8d28-4d9c-46cc-abb1-53fe082a9b8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28868
18503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.2886818503
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.3281133771
Short name T663
Test name
Test status
Simulation time 8492532462 ps
CPU time 8.41 seconds
Started Apr 18 01:16:09 PM PDT 24
Finished Apr 18 01:16:18 PM PDT 24
Peak memory 203964 kb
Host smart-5106aca8-272f-4e90-83f5-888b3d2a10b6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3281133771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.3281133771
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.3446462852
Short name T1144
Test name
Test status
Simulation time 8375268143 ps
CPU time 7.99 seconds
Started Apr 18 01:16:09 PM PDT 24
Finished Apr 18 01:16:17 PM PDT 24
Peak memory 204032 kb
Host smart-be863bd3-af17-438c-877a-24446a743431
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3446462852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.3446462852
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.1022093363
Short name T554
Test name
Test status
Simulation time 8449432814 ps
CPU time 9.55 seconds
Started Apr 18 01:16:11 PM PDT 24
Finished Apr 18 01:16:21 PM PDT 24
Peak memory 204040 kb
Host smart-70790836-42e0-4364-8af9-ff9acbee5475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10220
93363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.1022093363
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.138534303
Short name T679
Test name
Test status
Simulation time 8377639708 ps
CPU time 9.16 seconds
Started Apr 18 01:16:06 PM PDT 24
Finished Apr 18 01:16:16 PM PDT 24
Peak memory 204084 kb
Host smart-720459de-4774-41fb-a49d-58294de71378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13853
4303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.138534303
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_enable.720420609
Short name T445
Test name
Test status
Simulation time 8386224094 ps
CPU time 9.18 seconds
Started Apr 18 01:16:03 PM PDT 24
Finished Apr 18 01:16:14 PM PDT 24
Peak memory 203960 kb
Host smart-5498779d-9f62-45f4-83d0-4814711f0c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72042
0609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.720420609
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.669212172
Short name T910
Test name
Test status
Simulation time 173558527 ps
CPU time 1.51 seconds
Started Apr 18 01:16:05 PM PDT 24
Finished Apr 18 01:16:07 PM PDT 24
Peak memory 204144 kb
Host smart-24b61334-ee7e-44ef-ba18-13ac1bfa7a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66921
2172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.669212172
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.2757162692
Short name T1298
Test name
Test status
Simulation time 8427602170 ps
CPU time 8.2 seconds
Started Apr 18 01:16:09 PM PDT 24
Finished Apr 18 01:16:18 PM PDT 24
Peak memory 204008 kb
Host smart-46635b13-fedb-41cc-be20-aa07f0190ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27571
62692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.2757162692
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.1601712540
Short name T918
Test name
Test status
Simulation time 8377395534 ps
CPU time 8.2 seconds
Started Apr 18 01:16:10 PM PDT 24
Finished Apr 18 01:16:19 PM PDT 24
Peak memory 203952 kb
Host smart-7278a097-37ab-4f6d-b7aa-1b8b044171e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16017
12540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.1601712540
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.524796379
Short name T143
Test name
Test status
Simulation time 8417955810 ps
CPU time 7.59 seconds
Started Apr 18 01:16:08 PM PDT 24
Finished Apr 18 01:16:16 PM PDT 24
Peak memory 203960 kb
Host smart-82448fa7-22ea-4d31-9b94-882958aceabe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52479
6379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.524796379
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.3465754717
Short name T747
Test name
Test status
Simulation time 8441313447 ps
CPU time 8.66 seconds
Started Apr 18 01:16:11 PM PDT 24
Finished Apr 18 01:16:21 PM PDT 24
Peak memory 203964 kb
Host smart-c9ede0d1-4e15-4d45-8c3f-a188f18956a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34657
54717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.3465754717
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.1091493706
Short name T779
Test name
Test status
Simulation time 8381747822 ps
CPU time 7.67 seconds
Started Apr 18 01:16:07 PM PDT 24
Finished Apr 18 01:16:16 PM PDT 24
Peak memory 204004 kb
Host smart-2d0cfd2f-7f6b-4a65-9a31-2d16f42aa00a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10914
93706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.1091493706
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.2577288989
Short name T113
Test name
Test status
Simulation time 8426203106 ps
CPU time 8.23 seconds
Started Apr 18 01:16:12 PM PDT 24
Finished Apr 18 01:16:21 PM PDT 24
Peak memory 204024 kb
Host smart-2370cd7b-0442-41bd-96a7-5858ca55a1e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25772
88989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2577288989
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.427055536
Short name T1277
Test name
Test status
Simulation time 8414860368 ps
CPU time 7.7 seconds
Started Apr 18 01:16:13 PM PDT 24
Finished Apr 18 01:16:21 PM PDT 24
Peak memory 204012 kb
Host smart-a0b032c1-f3e5-401b-b1ad-9a40ec07e6f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42705
5536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.427055536
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.720851260
Short name T1248
Test name
Test status
Simulation time 8386045267 ps
CPU time 7.98 seconds
Started Apr 18 01:16:11 PM PDT 24
Finished Apr 18 01:16:19 PM PDT 24
Peak memory 203980 kb
Host smart-5d96620d-4d89-43a4-a78e-2d360a5fe18e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72085
1260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.720851260
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.541805886
Short name T879
Test name
Test status
Simulation time 8417573217 ps
CPU time 7.95 seconds
Started Apr 18 01:16:11 PM PDT 24
Finished Apr 18 01:16:20 PM PDT 24
Peak memory 204008 kb
Host smart-ab3b5772-2215-4f61-b17a-fb283b7228f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54180
5886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.541805886
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.1427076778
Short name T8
Test name
Test status
Simulation time 8375436903 ps
CPU time 8.23 seconds
Started Apr 18 01:16:09 PM PDT 24
Finished Apr 18 01:16:18 PM PDT 24
Peak memory 204036 kb
Host smart-bd89fc55-da74-4c6f-aa15-c034942d8ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14270
76778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.1427076778
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.2554946593
Short name T544
Test name
Test status
Simulation time 46196717 ps
CPU time 0.7 seconds
Started Apr 18 01:16:11 PM PDT 24
Finished Apr 18 01:16:13 PM PDT 24
Peak memory 203732 kb
Host smart-44583bcd-7550-43b1-ad2a-148488c71911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25549
46593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.2554946593
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.1027054978
Short name T1060
Test name
Test status
Simulation time 20006528670 ps
CPU time 37.15 seconds
Started Apr 18 01:16:10 PM PDT 24
Finished Apr 18 01:16:47 PM PDT 24
Peak memory 204344 kb
Host smart-00f12f86-4d45-478b-92a8-629a9fb34293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10270
54978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.1027054978
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.3280902325
Short name T349
Test name
Test status
Simulation time 8401350416 ps
CPU time 8.16 seconds
Started Apr 18 01:16:10 PM PDT 24
Finished Apr 18 01:16:19 PM PDT 24
Peak memory 204036 kb
Host smart-44c57c1b-df54-41b4-8307-70bd1378a404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32809
02325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3280902325
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.1011196479
Short name T959
Test name
Test status
Simulation time 8517487169 ps
CPU time 8.52 seconds
Started Apr 18 01:16:11 PM PDT 24
Finished Apr 18 01:16:21 PM PDT 24
Peak memory 203940 kb
Host smart-4ac9b041-e564-4670-8c8e-76eecfc3be34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10111
96479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.1011196479
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.2124423112
Short name T387
Test name
Test status
Simulation time 8405278601 ps
CPU time 9.6 seconds
Started Apr 18 01:16:10 PM PDT 24
Finished Apr 18 01:16:21 PM PDT 24
Peak memory 204044 kb
Host smart-259e8ad5-b536-4a5e-bcfa-c0f4e00b0c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21244
23112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.2124423112
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.95206735
Short name T1220
Test name
Test status
Simulation time 8377119580 ps
CPU time 8.94 seconds
Started Apr 18 01:16:11 PM PDT 24
Finished Apr 18 01:16:21 PM PDT 24
Peak memory 204008 kb
Host smart-cf7b9730-0032-4bda-a623-17ac31961d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95206
735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.95206735
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.1398249095
Short name T911
Test name
Test status
Simulation time 8375434749 ps
CPU time 7.35 seconds
Started Apr 18 01:16:11 PM PDT 24
Finished Apr 18 01:16:19 PM PDT 24
Peak memory 204040 kb
Host smart-733bf246-f10d-4a19-9996-bcf1d1716141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13982
49095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.1398249095
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2891286637
Short name T1097
Test name
Test status
Simulation time 8447828597 ps
CPU time 8.26 seconds
Started Apr 18 01:16:02 PM PDT 24
Finished Apr 18 01:16:12 PM PDT 24
Peak memory 204048 kb
Host smart-b61b18aa-d9ca-4076-88ac-504b096c07aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28912
86637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2891286637
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3586323309
Short name T577
Test name
Test status
Simulation time 8390309904 ps
CPU time 8.82 seconds
Started Apr 18 01:16:12 PM PDT 24
Finished Apr 18 01:16:22 PM PDT 24
Peak memory 204052 kb
Host smart-4cded845-39c4-4d6e-ab62-85477fd4f7c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35863
23309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3586323309
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.420802678
Short name T894
Test name
Test status
Simulation time 8375834769 ps
CPU time 9.14 seconds
Started Apr 18 01:16:08 PM PDT 24
Finished Apr 18 01:16:18 PM PDT 24
Peak memory 204036 kb
Host smart-f577c881-c28a-4269-a02c-58ce0602b9ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42080
2678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.420802678
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.1842433868
Short name T1308
Test name
Test status
Simulation time 8462007807 ps
CPU time 7.81 seconds
Started Apr 18 01:16:18 PM PDT 24
Finished Apr 18 01:16:27 PM PDT 24
Peak memory 204008 kb
Host smart-87f338f2-8fda-47d8-8e6d-1ea491dd75e8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1842433868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.1842433868
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.1487707018
Short name T775
Test name
Test status
Simulation time 8392186078 ps
CPU time 7.61 seconds
Started Apr 18 01:16:19 PM PDT 24
Finished Apr 18 01:16:28 PM PDT 24
Peak memory 203904 kb
Host smart-2b4fbc33-0077-42da-bd30-f525b58182aa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1487707018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.1487707018
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.4232064075
Short name T286
Test name
Test status
Simulation time 8439215293 ps
CPU time 9.08 seconds
Started Apr 18 01:16:21 PM PDT 24
Finished Apr 18 01:16:31 PM PDT 24
Peak memory 203860 kb
Host smart-e38365ae-03ca-41e1-946f-26a0295f275f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42320
64075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.4232064075
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3150983152
Short name T819
Test name
Test status
Simulation time 8375729426 ps
CPU time 8.3 seconds
Started Apr 18 01:16:11 PM PDT 24
Finished Apr 18 01:16:20 PM PDT 24
Peak memory 204084 kb
Host smart-4ce51d3e-cbd1-42e2-ab84-bdc40e13d0f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31509
83152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3150983152
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_enable.908783295
Short name T922
Test name
Test status
Simulation time 8379266958 ps
CPU time 8.28 seconds
Started Apr 18 01:16:09 PM PDT 24
Finished Apr 18 01:16:18 PM PDT 24
Peak memory 203960 kb
Host smart-6d6fe727-d8a0-42aa-bcef-5268aebaffe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90878
3295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.908783295
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.892961443
Short name T800
Test name
Test status
Simulation time 68584646 ps
CPU time 1.69 seconds
Started Apr 18 01:16:09 PM PDT 24
Finished Apr 18 01:16:12 PM PDT 24
Peak memory 204144 kb
Host smart-0bbc1706-49d7-4966-9fac-c0b5c921fc3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89296
1443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.892961443
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.229870757
Short name T1105
Test name
Test status
Simulation time 8400003636 ps
CPU time 8.59 seconds
Started Apr 18 01:16:15 PM PDT 24
Finished Apr 18 01:16:24 PM PDT 24
Peak memory 203964 kb
Host smart-5addd01d-6964-4c15-a05b-fbcc9bbac999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22987
0757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.229870757
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.142266901
Short name T181
Test name
Test status
Simulation time 8363249244 ps
CPU time 8.68 seconds
Started Apr 18 01:16:16 PM PDT 24
Finished Apr 18 01:16:26 PM PDT 24
Peak memory 203960 kb
Host smart-65795401-7ca6-40ce-9d6e-1fb81228fde6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14226
6901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.142266901
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.1630761532
Short name T362
Test name
Test status
Simulation time 8426435277 ps
CPU time 7.9 seconds
Started Apr 18 01:16:09 PM PDT 24
Finished Apr 18 01:16:18 PM PDT 24
Peak memory 203992 kb
Host smart-1c6d614a-62dc-4a5a-9943-1e3100a1c654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16307
61532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.1630761532
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.343507189
Short name T1021
Test name
Test status
Simulation time 8418009263 ps
CPU time 8.56 seconds
Started Apr 18 01:16:11 PM PDT 24
Finished Apr 18 01:16:21 PM PDT 24
Peak memory 204028 kb
Host smart-306c7e98-32c9-42a3-81fb-acf96b8b54bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34350
7189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.343507189
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.1536291717
Short name T340
Test name
Test status
Simulation time 8391006446 ps
CPU time 10.32 seconds
Started Apr 18 01:16:12 PM PDT 24
Finished Apr 18 01:16:23 PM PDT 24
Peak memory 204024 kb
Host smart-dc5bfa50-7b10-4a45-aab7-23e0b328f31f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15362
91717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.1536291717
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.825440646
Short name T111
Test name
Test status
Simulation time 8408756230 ps
CPU time 7.65 seconds
Started Apr 18 01:16:10 PM PDT 24
Finished Apr 18 01:16:19 PM PDT 24
Peak memory 204044 kb
Host smart-7aefdf8d-af83-4567-afcf-9f8d2b454e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82544
0646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.825440646
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.36990787
Short name T282
Test name
Test status
Simulation time 8396169829 ps
CPU time 7.62 seconds
Started Apr 18 01:16:12 PM PDT 24
Finished Apr 18 01:16:21 PM PDT 24
Peak memory 204028 kb
Host smart-6a535447-66f6-4d2c-8de1-4bff447d3df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36990
787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.36990787
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.457827631
Short name T1027
Test name
Test status
Simulation time 8408521146 ps
CPU time 7.78 seconds
Started Apr 18 01:16:10 PM PDT 24
Finished Apr 18 01:16:18 PM PDT 24
Peak memory 203988 kb
Host smart-97451fad-e25a-4fd5-9013-853c45c16757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45782
7631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.457827631
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.2666924725
Short name T177
Test name
Test status
Simulation time 8383951936 ps
CPU time 8.3 seconds
Started Apr 18 01:16:17 PM PDT 24
Finished Apr 18 01:16:27 PM PDT 24
Peak memory 204020 kb
Host smart-dcd1e94e-70bd-43d5-b854-47b8867b4bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26669
24725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.2666924725
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.2264353700
Short name T766
Test name
Test status
Simulation time 8368191994 ps
CPU time 10.09 seconds
Started Apr 18 01:16:18 PM PDT 24
Finished Apr 18 01:16:30 PM PDT 24
Peak memory 204008 kb
Host smart-8fa40a39-7bd0-4e78-b223-8957c1b603e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22643
53700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.2264353700
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.1887374682
Short name T818
Test name
Test status
Simulation time 47324996 ps
CPU time 0.67 seconds
Started Apr 18 01:16:18 PM PDT 24
Finished Apr 18 01:16:21 PM PDT 24
Peak memory 203916 kb
Host smart-47c9052a-87f2-4e12-bff6-4c4997bceec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18873
74682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.1887374682
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.1735743349
Short name T1238
Test name
Test status
Simulation time 20394422913 ps
CPU time 37.62 seconds
Started Apr 18 01:16:11 PM PDT 24
Finished Apr 18 01:16:50 PM PDT 24
Peak memory 204304 kb
Host smart-a55d5796-9ac5-4aec-b46e-d38ad6c41fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17357
43349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.1735743349
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.4167804275
Short name T1135
Test name
Test status
Simulation time 8382740628 ps
CPU time 7.32 seconds
Started Apr 18 01:16:18 PM PDT 24
Finished Apr 18 01:16:27 PM PDT 24
Peak memory 204044 kb
Host smart-f02e86c5-5e5a-4073-b638-9810e06f145e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41678
04275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.4167804275
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.3168897544
Short name T135
Test name
Test status
Simulation time 8407205436 ps
CPU time 8.13 seconds
Started Apr 18 01:16:17 PM PDT 24
Finished Apr 18 01:16:27 PM PDT 24
Peak memory 204044 kb
Host smart-fd25e4a0-0414-4724-aae1-5f36ff08620e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31688
97544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.3168897544
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.3239844956
Short name T762
Test name
Test status
Simulation time 8387902934 ps
CPU time 8 seconds
Started Apr 18 01:16:17 PM PDT 24
Finished Apr 18 01:16:27 PM PDT 24
Peak memory 204044 kb
Host smart-eb8858f3-0c0e-470b-a00a-3e64bfb845ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32398
44956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.3239844956
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.397259638
Short name T74
Test name
Test status
Simulation time 8371628106 ps
CPU time 9.12 seconds
Started Apr 18 01:16:18 PM PDT 24
Finished Apr 18 01:16:29 PM PDT 24
Peak memory 203864 kb
Host smart-9c177a7d-1c99-4e54-9830-a8daeb4cd4c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39725
9638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.397259638
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.3310318767
Short name T1262
Test name
Test status
Simulation time 8369776803 ps
CPU time 8.18 seconds
Started Apr 18 01:16:18 PM PDT 24
Finished Apr 18 01:16:28 PM PDT 24
Peak memory 204008 kb
Host smart-04e0d90d-567e-4fed-95cb-a4da02cd29cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33103
18767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.3310318767
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3414864947
Short name T584
Test name
Test status
Simulation time 8421271961 ps
CPU time 8.15 seconds
Started Apr 18 01:16:09 PM PDT 24
Finished Apr 18 01:16:18 PM PDT 24
Peak memory 203984 kb
Host smart-8d882e3a-1cbe-47d1-af0e-955d090378af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34148
64947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3414864947
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.1108903057
Short name T1207
Test name
Test status
Simulation time 8413277405 ps
CPU time 9.17 seconds
Started Apr 18 01:16:18 PM PDT 24
Finished Apr 18 01:16:29 PM PDT 24
Peak memory 203940 kb
Host smart-5e3656a2-cbf4-4264-bb81-6749dcc716b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11089
03057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.1108903057
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.2312547653
Short name T722
Test name
Test status
Simulation time 8375154394 ps
CPU time 7.62 seconds
Started Apr 18 01:16:17 PM PDT 24
Finished Apr 18 01:16:26 PM PDT 24
Peak memory 204020 kb
Host smart-495d1f60-c4d8-4935-b323-3cdeed86f9bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23125
47653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.2312547653
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.947220657
Short name T609
Test name
Test status
Simulation time 8460740596 ps
CPU time 8.08 seconds
Started Apr 18 01:16:21 PM PDT 24
Finished Apr 18 01:16:30 PM PDT 24
Peak memory 204052 kb
Host smart-d5df7b6d-928d-449f-9c66-53ed8346e407
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=947220657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.947220657
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.525037808
Short name T380
Test name
Test status
Simulation time 8378971265 ps
CPU time 9.32 seconds
Started Apr 18 01:16:20 PM PDT 24
Finished Apr 18 01:16:31 PM PDT 24
Peak memory 203916 kb
Host smart-50abb5be-388f-4027-9389-77dee4744e19
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=525037808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.525037808
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.401094835
Short name T739
Test name
Test status
Simulation time 8451046457 ps
CPU time 8.22 seconds
Started Apr 18 01:16:21 PM PDT 24
Finished Apr 18 01:16:30 PM PDT 24
Peak memory 203864 kb
Host smart-7813a1fc-e73c-482f-89f2-c6ad2af9bc2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40109
4835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.401094835
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.4066806941
Short name T455
Test name
Test status
Simulation time 8435301146 ps
CPU time 7.96 seconds
Started Apr 18 01:16:15 PM PDT 24
Finished Apr 18 01:16:24 PM PDT 24
Peak memory 204004 kb
Host smart-946d99e9-d43c-4265-a225-263fcb0c42f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40668
06941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.4066806941
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_enable.4099250736
Short name T1217
Test name
Test status
Simulation time 8400865374 ps
CPU time 10.22 seconds
Started Apr 18 01:16:17 PM PDT 24
Finished Apr 18 01:16:29 PM PDT 24
Peak memory 204040 kb
Host smart-92b9afc4-e781-45f3-a4ff-26286e350d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40992
50736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.4099250736
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.1019708295
Short name T530
Test name
Test status
Simulation time 60712156 ps
CPU time 1.3 seconds
Started Apr 18 01:16:26 PM PDT 24
Finished Apr 18 01:16:28 PM PDT 24
Peak memory 204028 kb
Host smart-6a9aaf78-f6d0-4efe-976a-155bcd42b0ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10197
08295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1019708295
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.562666987
Short name T781
Test name
Test status
Simulation time 8437807304 ps
CPU time 8.26 seconds
Started Apr 18 01:16:22 PM PDT 24
Finished Apr 18 01:16:31 PM PDT 24
Peak memory 203932 kb
Host smart-78ffe5bd-5f24-457f-ac41-5f29087f181e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56266
6987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.562666987
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.1077562521
Short name T979
Test name
Test status
Simulation time 8377676557 ps
CPU time 7.47 seconds
Started Apr 18 01:16:21 PM PDT 24
Finished Apr 18 01:16:29 PM PDT 24
Peak memory 204040 kb
Host smart-e1a134fc-2279-4e7d-8905-9c7e9fc9f0dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10775
62521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.1077562521
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.1904168783
Short name T1113
Test name
Test status
Simulation time 8415834190 ps
CPU time 8.46 seconds
Started Apr 18 01:16:17 PM PDT 24
Finished Apr 18 01:16:28 PM PDT 24
Peak memory 204052 kb
Host smart-cad53fb9-5ad8-4822-843e-8dd2c5fde24c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19041
68783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.1904168783
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.3191629000
Short name T1041
Test name
Test status
Simulation time 8424031103 ps
CPU time 8.6 seconds
Started Apr 18 01:16:16 PM PDT 24
Finished Apr 18 01:16:26 PM PDT 24
Peak memory 204024 kb
Host smart-2d6a6cc7-d833-486c-8e3f-3c19d8f59091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31916
29000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.3191629000
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.1952562198
Short name T1020
Test name
Test status
Simulation time 8398398502 ps
CPU time 9.1 seconds
Started Apr 18 01:16:17 PM PDT 24
Finished Apr 18 01:16:28 PM PDT 24
Peak memory 204028 kb
Host smart-87a1b569-47c2-4844-aeb9-367ebf76d177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19525
62198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.1952562198
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.1028336117
Short name T112
Test name
Test status
Simulation time 8445915924 ps
CPU time 7.94 seconds
Started Apr 18 01:16:18 PM PDT 24
Finished Apr 18 01:16:28 PM PDT 24
Peak memory 204040 kb
Host smart-915ad2bc-ccc4-40ef-afaf-dbb02359577a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10283
36117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.1028336117
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.281957676
Short name T1031
Test name
Test status
Simulation time 8409145806 ps
CPU time 8.39 seconds
Started Apr 18 01:16:15 PM PDT 24
Finished Apr 18 01:16:25 PM PDT 24
Peak memory 204008 kb
Host smart-5d4e3b85-fa1a-421d-8185-b6282ae8a936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28195
7676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.281957676
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.3701980929
Short name T415
Test name
Test status
Simulation time 8418262410 ps
CPU time 10.12 seconds
Started Apr 18 01:16:15 PM PDT 24
Finished Apr 18 01:16:26 PM PDT 24
Peak memory 204044 kb
Host smart-e99d3ea4-aa76-4316-be5d-564eaa551ed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37019
80929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3701980929
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.1563169073
Short name T1285
Test name
Test status
Simulation time 8416028136 ps
CPU time 8.82 seconds
Started Apr 18 01:16:23 PM PDT 24
Finished Apr 18 01:16:32 PM PDT 24
Peak memory 203924 kb
Host smart-514d66fd-76c1-4b01-a67a-d520b0135deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15631
69073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.1563169073
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.284408831
Short name T1108
Test name
Test status
Simulation time 8373464182 ps
CPU time 9.97 seconds
Started Apr 18 01:16:21 PM PDT 24
Finished Apr 18 01:16:32 PM PDT 24
Peak memory 203988 kb
Host smart-51a48957-068d-4da0-a79f-ff2ea0910baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28440
8831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.284408831
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.4184337831
Short name T45
Test name
Test status
Simulation time 47369728 ps
CPU time 0.66 seconds
Started Apr 18 01:16:23 PM PDT 24
Finished Apr 18 01:16:25 PM PDT 24
Peak memory 203836 kb
Host smart-121fd96d-9a82-4db2-8cd2-9e02110dc670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41843
37831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.4184337831
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.2858642664
Short name T784
Test name
Test status
Simulation time 19316177411 ps
CPU time 35.94 seconds
Started Apr 18 01:16:17 PM PDT 24
Finished Apr 18 01:16:55 PM PDT 24
Peak memory 204296 kb
Host smart-00f8bfa5-0a31-4ff5-8bed-b599167d7bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28586
42664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.2858642664
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.3762236676
Short name T786
Test name
Test status
Simulation time 8376265094 ps
CPU time 8.08 seconds
Started Apr 18 01:16:15 PM PDT 24
Finished Apr 18 01:16:23 PM PDT 24
Peak memory 204052 kb
Host smart-0990fd9d-ac65-4d99-9456-198884ec5def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37622
36676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.3762236676
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.4217047919
Short name T1294
Test name
Test status
Simulation time 8385080325 ps
CPU time 8.57 seconds
Started Apr 18 01:16:15 PM PDT 24
Finished Apr 18 01:16:25 PM PDT 24
Peak memory 204008 kb
Host smart-c276393d-48da-4167-81eb-3aaf2a53cbd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42170
47919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.4217047919
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.336358839
Short name T399
Test name
Test status
Simulation time 8412368230 ps
CPU time 9.54 seconds
Started Apr 18 01:16:18 PM PDT 24
Finished Apr 18 01:16:29 PM PDT 24
Peak memory 203996 kb
Host smart-12768ea2-cda5-42fc-aa1e-e2e44dbc6368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33635
8839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.336358839
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.2756842977
Short name T525
Test name
Test status
Simulation time 8393437100 ps
CPU time 8.12 seconds
Started Apr 18 01:16:18 PM PDT 24
Finished Apr 18 01:16:27 PM PDT 24
Peak memory 204008 kb
Host smart-4fde82e7-f108-4b01-92c1-1c4a9f0cd328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27568
42977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.2756842977
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.1957824675
Short name T859
Test name
Test status
Simulation time 8378312599 ps
CPU time 8.25 seconds
Started Apr 18 01:16:16 PM PDT 24
Finished Apr 18 01:16:26 PM PDT 24
Peak memory 204084 kb
Host smart-c95b595e-b0f4-4485-a34f-7a0eb2337bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19578
24675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.1957824675
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1237376721
Short name T1305
Test name
Test status
Simulation time 8424307931 ps
CPU time 8.2 seconds
Started Apr 18 01:16:16 PM PDT 24
Finished Apr 18 01:16:25 PM PDT 24
Peak memory 204004 kb
Host smart-20b43768-9ec2-4751-a1d8-9bca500556f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12373
76721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1237376721
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.2349405580
Short name T761
Test name
Test status
Simulation time 8372058469 ps
CPU time 8.01 seconds
Started Apr 18 01:16:17 PM PDT 24
Finished Apr 18 01:16:26 PM PDT 24
Peak memory 204016 kb
Host smart-3afe8530-2d16-4b3c-a58b-ab05fcb0c1c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23494
05580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.2349405580
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.4150515649
Short name T1070
Test name
Test status
Simulation time 8374567409 ps
CPU time 9.4 seconds
Started Apr 18 01:16:16 PM PDT 24
Finished Apr 18 01:16:27 PM PDT 24
Peak memory 204024 kb
Host smart-00974cfa-5318-42d7-ae8c-aa706e682a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41505
15649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.4150515649
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.1556733710
Short name T735
Test name
Test status
Simulation time 8477006729 ps
CPU time 9.76 seconds
Started Apr 18 01:13:53 PM PDT 24
Finished Apr 18 01:14:03 PM PDT 24
Peak memory 204024 kb
Host smart-7c126d38-a3bf-4033-80ad-468f09bbfc16
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1556733710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.1556733710
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.1541772178
Short name T716
Test name
Test status
Simulation time 8381493729 ps
CPU time 7.78 seconds
Started Apr 18 01:13:53 PM PDT 24
Finished Apr 18 01:14:02 PM PDT 24
Peak memory 203984 kb
Host smart-67688d19-e016-437f-b46c-fdf4a010c439
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1541772178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.1541772178
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.829943635
Short name T529
Test name
Test status
Simulation time 8462043224 ps
CPU time 7.72 seconds
Started Apr 18 01:13:48 PM PDT 24
Finished Apr 18 01:13:57 PM PDT 24
Peak memory 204000 kb
Host smart-c0f8945a-dbf7-4c22-8452-e3c950c9669d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82994
3635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.829943635
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.2304795778
Short name T1231
Test name
Test status
Simulation time 8404919706 ps
CPU time 7.69 seconds
Started Apr 18 01:13:46 PM PDT 24
Finished Apr 18 01:13:54 PM PDT 24
Peak memory 203996 kb
Host smart-8fac0f38-e450-4328-bc43-52996993e07c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23047
95778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.2304795778
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_enable.4181215146
Short name T707
Test name
Test status
Simulation time 8374847099 ps
CPU time 8.21 seconds
Started Apr 18 01:13:41 PM PDT 24
Finished Apr 18 01:13:51 PM PDT 24
Peak memory 203964 kb
Host smart-91fe7836-feb5-4007-80cb-2c54bdb765a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41812
15146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.4181215146
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.611159745
Short name T1149
Test name
Test status
Simulation time 69915748 ps
CPU time 1.73 seconds
Started Apr 18 01:13:41 PM PDT 24
Finished Apr 18 01:13:43 PM PDT 24
Peak memory 203984 kb
Host smart-8960e668-6c4c-40e3-80e4-2c09a4ef7efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61115
9745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.611159745
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.327772677
Short name T391
Test name
Test status
Simulation time 8452608147 ps
CPU time 8.72 seconds
Started Apr 18 01:13:49 PM PDT 24
Finished Apr 18 01:13:58 PM PDT 24
Peak memory 203964 kb
Host smart-ba08c96e-4f72-4318-81df-bf79443e4895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32777
2677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.327772677
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.1413858291
Short name T756
Test name
Test status
Simulation time 8386027906 ps
CPU time 8.04 seconds
Started Apr 18 01:13:47 PM PDT 24
Finished Apr 18 01:13:56 PM PDT 24
Peak memory 204032 kb
Host smart-532421d5-f67e-46f3-8938-a43e330c8fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14138
58291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.1413858291
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1342989096
Short name T640
Test name
Test status
Simulation time 8405951006 ps
CPU time 9.52 seconds
Started Apr 18 01:13:44 PM PDT 24
Finished Apr 18 01:13:55 PM PDT 24
Peak memory 204028 kb
Host smart-8e9471e6-f8bd-43cd-81c6-eae0de1b73b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13429
89096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1342989096
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.2169017943
Short name T73
Test name
Test status
Simulation time 8422656302 ps
CPU time 9.16 seconds
Started Apr 18 01:13:40 PM PDT 24
Finished Apr 18 01:13:50 PM PDT 24
Peak memory 204268 kb
Host smart-50f17941-4811-456f-8d6c-98d99b9491a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21690
17943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.2169017943
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.1781881249
Short name T1086
Test name
Test status
Simulation time 8365059366 ps
CPU time 7.92 seconds
Started Apr 18 01:13:45 PM PDT 24
Finished Apr 18 01:13:54 PM PDT 24
Peak memory 204028 kb
Host smart-8d30dc41-e574-4e6c-b897-76e22ac4d366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17818
81249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.1781881249
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.1723480884
Short name T29
Test name
Test status
Simulation time 8450233774 ps
CPU time 7.53 seconds
Started Apr 18 01:13:43 PM PDT 24
Finished Apr 18 01:13:51 PM PDT 24
Peak memory 204008 kb
Host smart-3fd50f63-c0af-422a-bd1a-a5f5de549f3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17234
80884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.1723480884
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.43788178
Short name T457
Test name
Test status
Simulation time 8400576700 ps
CPU time 8.53 seconds
Started Apr 18 01:13:43 PM PDT 24
Finished Apr 18 01:13:52 PM PDT 24
Peak memory 204028 kb
Host smart-1ce6492a-daa4-4250-8e40-42281a636dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43788
178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.43788178
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3388352324
Short name T395
Test name
Test status
Simulation time 8402787426 ps
CPU time 8.02 seconds
Started Apr 18 01:13:47 PM PDT 24
Finished Apr 18 01:13:55 PM PDT 24
Peak memory 203996 kb
Host smart-be1bd271-6c1f-42bd-8231-88f6a3f4bd27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33883
52324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3388352324
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.2318953781
Short name T637
Test name
Test status
Simulation time 8414706599 ps
CPU time 7.94 seconds
Started Apr 18 01:13:48 PM PDT 24
Finished Apr 18 01:13:57 PM PDT 24
Peak memory 203992 kb
Host smart-bbadccc2-5242-47cd-928b-59da48d45234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23189
53781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.2318953781
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2316229019
Short name T875
Test name
Test status
Simulation time 8369191899 ps
CPU time 8.65 seconds
Started Apr 18 01:13:46 PM PDT 24
Finished Apr 18 01:13:56 PM PDT 24
Peak memory 204044 kb
Host smart-171b3d03-a02e-4211-b422-4de5924752e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23162
29019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2316229019
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2844034530
Short name T468
Test name
Test status
Simulation time 52729447 ps
CPU time 0.69 seconds
Started Apr 18 01:13:47 PM PDT 24
Finished Apr 18 01:13:48 PM PDT 24
Peak memory 203896 kb
Host smart-1a43234f-fa13-4f04-b048-2c2d95f31b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28440
34530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2844034530
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.3530967947
Short name T13
Test name
Test status
Simulation time 30485934492 ps
CPU time 59.28 seconds
Started Apr 18 01:13:48 PM PDT 24
Finished Apr 18 01:14:48 PM PDT 24
Peak memory 204280 kb
Host smart-231226fe-9e23-41d3-9203-8b52b2c1a53d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35309
67947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3530967947
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.225674996
Short name T763
Test name
Test status
Simulation time 8387585670 ps
CPU time 10.14 seconds
Started Apr 18 01:13:42 PM PDT 24
Finished Apr 18 01:13:53 PM PDT 24
Peak memory 203908 kb
Host smart-0a355296-70ba-4436-8e33-e1e5d2098ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22567
4996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.225674996
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.1357143416
Short name T460
Test name
Test status
Simulation time 8444374037 ps
CPU time 10.11 seconds
Started Apr 18 01:13:42 PM PDT 24
Finished Apr 18 01:13:53 PM PDT 24
Peak memory 204012 kb
Host smart-fa592263-1373-4903-9e6e-44e8c5c9d3c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13571
43416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.1357143416
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.2849479454
Short name T486
Test name
Test status
Simulation time 8408766032 ps
CPU time 8.14 seconds
Started Apr 18 01:13:39 PM PDT 24
Finished Apr 18 01:13:48 PM PDT 24
Peak memory 203872 kb
Host smart-0d1a189c-f409-4f20-8e20-cba8ff4a8064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28494
79454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.2849479454
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.524563979
Short name T60
Test name
Test status
Simulation time 182653915 ps
CPU time 0.99 seconds
Started Apr 18 01:13:55 PM PDT 24
Finished Apr 18 01:13:57 PM PDT 24
Peak memory 220052 kb
Host smart-f978df77-6ff6-4f3a-a8eb-73a71359acc0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=524563979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.524563979
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.2547174945
Short name T497
Test name
Test status
Simulation time 8375182820 ps
CPU time 8.87 seconds
Started Apr 18 01:13:48 PM PDT 24
Finished Apr 18 01:13:57 PM PDT 24
Peak memory 204024 kb
Host smart-e7d3cffa-4de2-4f69-aec9-56979a711266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25471
74945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.2547174945
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.699897782
Short name T330
Test name
Test status
Simulation time 8376199456 ps
CPU time 8.3 seconds
Started Apr 18 01:13:46 PM PDT 24
Finished Apr 18 01:13:55 PM PDT 24
Peak memory 203992 kb
Host smart-6f3809ea-4236-47bb-8cb3-b704dc0637cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69989
7782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.699897782
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.3528280743
Short name T885
Test name
Test status
Simulation time 8431644717 ps
CPU time 7.82 seconds
Started Apr 18 01:13:41 PM PDT 24
Finished Apr 18 01:13:50 PM PDT 24
Peak memory 203964 kb
Host smart-997e7023-55b1-472b-adb1-fbf49a0b7714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35282
80743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.3528280743
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.941089499
Short name T1139
Test name
Test status
Simulation time 8374988588 ps
CPU time 7.57 seconds
Started Apr 18 01:13:45 PM PDT 24
Finished Apr 18 01:13:54 PM PDT 24
Peak memory 204028 kb
Host smart-4b4e3267-5a78-4097-9951-c5833e5d1dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94108
9499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.941089499
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.652368036
Short name T638
Test name
Test status
Simulation time 8410678054 ps
CPU time 7.64 seconds
Started Apr 18 01:13:40 PM PDT 24
Finished Apr 18 01:13:49 PM PDT 24
Peak memory 203952 kb
Host smart-4e82b233-c622-4c41-8b80-14f1c340f352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65236
8036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.652368036
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.844364823
Short name T625
Test name
Test status
Simulation time 8524298344 ps
CPU time 9.02 seconds
Started Apr 18 01:16:27 PM PDT 24
Finished Apr 18 01:16:37 PM PDT 24
Peak memory 204044 kb
Host smart-0b28bb2b-ba9e-45fe-ac72-f7b8b90f017a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=844364823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.844364823
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.3349707105
Short name T336
Test name
Test status
Simulation time 8431959944 ps
CPU time 7.89 seconds
Started Apr 18 01:16:33 PM PDT 24
Finished Apr 18 01:16:41 PM PDT 24
Peak memory 203956 kb
Host smart-6b906b06-c5c3-4d35-85d3-1611a18f06a5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3349707105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.3349707105
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.848257422
Short name T1322
Test name
Test status
Simulation time 8474951447 ps
CPU time 8 seconds
Started Apr 18 01:16:32 PM PDT 24
Finished Apr 18 01:16:40 PM PDT 24
Peak memory 204008 kb
Host smart-2f405872-5e57-4d8c-b709-2a705f3c3836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84825
7422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.848257422
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.848137498
Short name T771
Test name
Test status
Simulation time 8377062511 ps
CPU time 9.22 seconds
Started Apr 18 01:16:21 PM PDT 24
Finished Apr 18 01:16:31 PM PDT 24
Peak memory 204044 kb
Host smart-35aa7c94-757a-44a2-9046-47be5e3c026d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84813
7498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.848137498
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_enable.4285577992
Short name T1355
Test name
Test status
Simulation time 8379925051 ps
CPU time 8.45 seconds
Started Apr 18 01:16:21 PM PDT 24
Finished Apr 18 01:16:31 PM PDT 24
Peak memory 204056 kb
Host smart-b6ee6994-e589-4111-96ed-3ce74bc964ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42855
77992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.4285577992
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.3112260359
Short name T872
Test name
Test status
Simulation time 57698460 ps
CPU time 1.47 seconds
Started Apr 18 01:16:21 PM PDT 24
Finished Apr 18 01:16:23 PM PDT 24
Peak memory 204208 kb
Host smart-b47c2ec9-cec7-4e3d-8a46-bc78561bb267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31122
60359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.3112260359
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.2339640689
Short name T1064
Test name
Test status
Simulation time 8464875853 ps
CPU time 9.36 seconds
Started Apr 18 01:16:30 PM PDT 24
Finished Apr 18 01:16:40 PM PDT 24
Peak memory 203856 kb
Host smart-0e755916-8314-47a6-8188-1b7038ad7f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23396
40689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.2339640689
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.875429729
Short name T209
Test name
Test status
Simulation time 8363801275 ps
CPU time 9.03 seconds
Started Apr 18 01:16:28 PM PDT 24
Finished Apr 18 01:16:38 PM PDT 24
Peak memory 204004 kb
Host smart-3c55c1d0-2cae-4778-abdc-2ec4141e051d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87542
9729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.875429729
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.3940603791
Short name T480
Test name
Test status
Simulation time 8392076902 ps
CPU time 8.08 seconds
Started Apr 18 01:16:20 PM PDT 24
Finished Apr 18 01:16:30 PM PDT 24
Peak memory 203968 kb
Host smart-b4dd4991-f304-4e51-81c6-8a8a25938086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39406
03791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.3940603791
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.3153471444
Short name T357
Test name
Test status
Simulation time 8421677284 ps
CPU time 7.6 seconds
Started Apr 18 01:16:22 PM PDT 24
Finished Apr 18 01:16:30 PM PDT 24
Peak memory 204000 kb
Host smart-edd77c29-9b25-4d00-8fd4-d44f44246bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31534
71444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3153471444
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.163910601
Short name T353
Test name
Test status
Simulation time 8380038610 ps
CPU time 8.8 seconds
Started Apr 18 01:16:21 PM PDT 24
Finished Apr 18 01:16:31 PM PDT 24
Peak memory 204016 kb
Host smart-00d3edf6-243a-4563-8241-1e514ee2e675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16391
0601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.163910601
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.4138701145
Short name T90
Test name
Test status
Simulation time 8402585109 ps
CPU time 7.9 seconds
Started Apr 18 01:16:24 PM PDT 24
Finished Apr 18 01:16:32 PM PDT 24
Peak memory 204028 kb
Host smart-1a22b2e3-c9af-4c2b-b972-43e4ffbe3810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41387
01145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.4138701145
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.961301711
Short name T871
Test name
Test status
Simulation time 8378147912 ps
CPU time 7.84 seconds
Started Apr 18 01:16:24 PM PDT 24
Finished Apr 18 01:16:32 PM PDT 24
Peak memory 204020 kb
Host smart-5a1eaf21-7a7f-49e6-bfe8-ad5418591b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96130
1711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.961301711
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.2655870550
Short name T548
Test name
Test status
Simulation time 8417214561 ps
CPU time 7.77 seconds
Started Apr 18 01:16:19 PM PDT 24
Finished Apr 18 01:16:29 PM PDT 24
Peak memory 204008 kb
Host smart-60c76746-204a-4411-a416-a6a24c163ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26558
70550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.2655870550
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.3644264484
Short name T182
Test name
Test status
Simulation time 8382097743 ps
CPU time 9.47 seconds
Started Apr 18 01:16:28 PM PDT 24
Finished Apr 18 01:16:39 PM PDT 24
Peak memory 203940 kb
Host smart-2f5c2d3c-d51a-431e-9a73-eaa19c41e150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36442
64484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.3644264484
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.492596472
Short name T797
Test name
Test status
Simulation time 8373926918 ps
CPU time 8.29 seconds
Started Apr 18 01:16:29 PM PDT 24
Finished Apr 18 01:16:38 PM PDT 24
Peak memory 204024 kb
Host smart-7a950b6d-84db-4863-b731-2e0888059de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49259
6472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.492596472
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2289567577
Short name T41
Test name
Test status
Simulation time 40647146 ps
CPU time 0.65 seconds
Started Apr 18 01:16:30 PM PDT 24
Finished Apr 18 01:16:32 PM PDT 24
Peak memory 203900 kb
Host smart-f65014fd-7349-4b47-b74f-3fa1cebe34a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22895
67577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2289567577
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.2592901861
Short name T619
Test name
Test status
Simulation time 22441289858 ps
CPU time 43.26 seconds
Started Apr 18 01:16:23 PM PDT 24
Finished Apr 18 01:17:07 PM PDT 24
Peak memory 204324 kb
Host smart-a78135ff-abed-4cdf-975c-ff76dbac2224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25929
01861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.2592901861
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.20339033
Short name T1210
Test name
Test status
Simulation time 8381565638 ps
CPU time 8.42 seconds
Started Apr 18 01:16:24 PM PDT 24
Finished Apr 18 01:16:33 PM PDT 24
Peak memory 204024 kb
Host smart-a3d4aa94-321a-430a-9305-da5d4fc89cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20339
033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.20339033
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.328032722
Short name T983
Test name
Test status
Simulation time 8405774163 ps
CPU time 8.55 seconds
Started Apr 18 01:16:25 PM PDT 24
Finished Apr 18 01:16:34 PM PDT 24
Peak memory 203984 kb
Host smart-d8b679dc-f6ec-441a-aebf-dcac83618246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32803
2722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.328032722
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.3662884167
Short name T1328
Test name
Test status
Simulation time 8408684330 ps
CPU time 7.95 seconds
Started Apr 18 01:16:23 PM PDT 24
Finished Apr 18 01:16:32 PM PDT 24
Peak memory 204040 kb
Host smart-2871a7ca-d4a9-4880-a313-fcd1837c8af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36628
84167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.3662884167
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.1442786690
Short name T833
Test name
Test status
Simulation time 8378722270 ps
CPU time 8.56 seconds
Started Apr 18 01:16:29 PM PDT 24
Finished Apr 18 01:16:39 PM PDT 24
Peak memory 204040 kb
Host smart-c7dc60ae-3af0-4e38-bb66-c342fcad5ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14427
86690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.1442786690
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.4214149532
Short name T1085
Test name
Test status
Simulation time 8377617467 ps
CPU time 7.98 seconds
Started Apr 18 01:16:23 PM PDT 24
Finished Apr 18 01:16:32 PM PDT 24
Peak memory 204040 kb
Host smart-0f6456c0-f57d-46af-a682-598cc5b8282e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42141
49532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.4214149532
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.948316390
Short name T84
Test name
Test status
Simulation time 8429887860 ps
CPU time 9.78 seconds
Started Apr 18 01:16:26 PM PDT 24
Finished Apr 18 01:16:36 PM PDT 24
Peak memory 203960 kb
Host smart-059c0e43-ffab-4883-b6fe-48f5987623f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94831
6390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.948316390
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.147813439
Short name T1117
Test name
Test status
Simulation time 8378267835 ps
CPU time 7.51 seconds
Started Apr 18 01:16:24 PM PDT 24
Finished Apr 18 01:16:32 PM PDT 24
Peak memory 204000 kb
Host smart-824aefcb-5ea9-4ea0-8140-ae4aaafec698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14781
3439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.147813439
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.3075518208
Short name T34
Test name
Test status
Simulation time 8400066916 ps
CPU time 7.72 seconds
Started Apr 18 01:16:21 PM PDT 24
Finished Apr 18 01:16:30 PM PDT 24
Peak memory 203956 kb
Host smart-6f6a2a09-e984-4e55-a0c9-4f5a13e84666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30755
18208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.3075518208
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.3059379654
Short name T1345
Test name
Test status
Simulation time 8460455570 ps
CPU time 9.11 seconds
Started Apr 18 01:16:29 PM PDT 24
Finished Apr 18 01:16:39 PM PDT 24
Peak memory 204020 kb
Host smart-04b41a37-386b-42e3-919e-b591e50a4697
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3059379654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.3059379654
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.min_length_in_transaction.2089446646
Short name T1270
Test name
Test status
Simulation time 8412083557 ps
CPU time 8.27 seconds
Started Apr 18 01:16:30 PM PDT 24
Finished Apr 18 01:16:39 PM PDT 24
Peak memory 203944 kb
Host smart-eae56191-588d-4c9b-ba74-4f1f2dacefdd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2089446646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.2089446646
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.2648515065
Short name T1039
Test name
Test status
Simulation time 8409654369 ps
CPU time 9.96 seconds
Started Apr 18 01:16:35 PM PDT 24
Finished Apr 18 01:16:46 PM PDT 24
Peak memory 203976 kb
Host smart-acd36b05-f56f-4111-8d6a-5348f8b02e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26485
15065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.2648515065
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.744661691
Short name T1034
Test name
Test status
Simulation time 8393401140 ps
CPU time 8.25 seconds
Started Apr 18 01:16:31 PM PDT 24
Finished Apr 18 01:16:40 PM PDT 24
Peak memory 204044 kb
Host smart-878594d1-f42e-425b-833d-9d5a4524e879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74466
1691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.744661691
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_enable.2429616353
Short name T1106
Test name
Test status
Simulation time 8386637085 ps
CPU time 7.71 seconds
Started Apr 18 01:16:29 PM PDT 24
Finished Apr 18 01:16:38 PM PDT 24
Peak memory 204020 kb
Host smart-f2882d44-35a4-4e98-9302-437531a5b42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24296
16353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.2429616353
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.4238068827
Short name T1203
Test name
Test status
Simulation time 212290594 ps
CPU time 2.01 seconds
Started Apr 18 01:16:32 PM PDT 24
Finished Apr 18 01:16:34 PM PDT 24
Peak memory 204136 kb
Host smart-63da5ce3-039b-436c-bae6-1eebcc89a2f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42380
68827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.4238068827
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.1702431446
Short name T757
Test name
Test status
Simulation time 8379472476 ps
CPU time 9.03 seconds
Started Apr 18 01:16:33 PM PDT 24
Finished Apr 18 01:16:42 PM PDT 24
Peak memory 203924 kb
Host smart-f3ff428c-2296-48d1-ad86-e2d4f9cce2c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17024
31446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.1702431446
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.2559419569
Short name T1146
Test name
Test status
Simulation time 8363853316 ps
CPU time 7.6 seconds
Started Apr 18 01:16:29 PM PDT 24
Finished Apr 18 01:16:38 PM PDT 24
Peak memory 203992 kb
Host smart-516f4dd3-49d7-4ca0-aa00-d699b207746d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25594
19569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.2559419569
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.614574818
Short name T1331
Test name
Test status
Simulation time 8438393381 ps
CPU time 9.13 seconds
Started Apr 18 01:16:27 PM PDT 24
Finished Apr 18 01:16:37 PM PDT 24
Peak memory 203912 kb
Host smart-f9c98a7e-bd06-4f41-944c-cc31782a3df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61457
4818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.614574818
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.3415620010
Short name T975
Test name
Test status
Simulation time 8421902945 ps
CPU time 7.7 seconds
Started Apr 18 01:16:31 PM PDT 24
Finished Apr 18 01:16:39 PM PDT 24
Peak memory 204252 kb
Host smart-a42fd14d-1ad0-43bd-8802-c4e09922870f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34156
20010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.3415620010
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1673631288
Short name T641
Test name
Test status
Simulation time 8371609113 ps
CPU time 7.61 seconds
Started Apr 18 01:16:33 PM PDT 24
Finished Apr 18 01:16:41 PM PDT 24
Peak memory 203964 kb
Host smart-1a388d57-9d00-449f-91ff-f0ceff699320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16736
31288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1673631288
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.4203136724
Short name T99
Test name
Test status
Simulation time 8417688422 ps
CPU time 7.64 seconds
Started Apr 18 01:16:29 PM PDT 24
Finished Apr 18 01:16:37 PM PDT 24
Peak memory 204020 kb
Host smart-c8fb1949-d291-4fae-a8b9-fec292a980c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42031
36724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.4203136724
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.3215483880
Short name T302
Test name
Test status
Simulation time 8419872275 ps
CPU time 10.46 seconds
Started Apr 18 01:16:28 PM PDT 24
Finished Apr 18 01:16:39 PM PDT 24
Peak memory 203960 kb
Host smart-923cbda0-f33e-4d68-8ae0-3705391bd288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32154
83880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.3215483880
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.2244784770
Short name T404
Test name
Test status
Simulation time 8419126776 ps
CPU time 8.63 seconds
Started Apr 18 01:16:30 PM PDT 24
Finished Apr 18 01:16:39 PM PDT 24
Peak memory 203980 kb
Host smart-54ca093e-cc1a-4c50-a59b-07cae5e9a99e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22447
84770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.2244784770
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.488151870
Short name T657
Test name
Test status
Simulation time 8382365091 ps
CPU time 7.69 seconds
Started Apr 18 01:16:30 PM PDT 24
Finished Apr 18 01:16:39 PM PDT 24
Peak memory 203972 kb
Host smart-97e7923d-0d81-4197-9adc-cc2b9710d9cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48815
1870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.488151870
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.56696674
Short name T471
Test name
Test status
Simulation time 8379823033 ps
CPU time 8.74 seconds
Started Apr 18 01:16:28 PM PDT 24
Finished Apr 18 01:16:38 PM PDT 24
Peak memory 204040 kb
Host smart-00415d4c-7124-4484-bade-52bee1e0b98f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56696
674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.56696674
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.269098451
Short name T821
Test name
Test status
Simulation time 45954513 ps
CPU time 0.7 seconds
Started Apr 18 01:16:30 PM PDT 24
Finished Apr 18 01:16:31 PM PDT 24
Peak memory 203816 kb
Host smart-21084295-d1da-46a3-9a6c-f7101ee48120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26909
8451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.269098451
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.4013107073
Short name T1129
Test name
Test status
Simulation time 15685869067 ps
CPU time 26.75 seconds
Started Apr 18 01:16:26 PM PDT 24
Finished Apr 18 01:16:54 PM PDT 24
Peak memory 204204 kb
Host smart-5a27b232-d4ce-4d20-af1f-6df6af02ac53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40131
07073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.4013107073
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.2200116192
Short name T1241
Test name
Test status
Simulation time 8414603507 ps
CPU time 8.14 seconds
Started Apr 18 01:16:26 PM PDT 24
Finished Apr 18 01:16:36 PM PDT 24
Peak memory 204020 kb
Host smart-10cb3ac6-eaef-4c05-90fc-e8d7d0c89582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22001
16192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.2200116192
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.1521941647
Short name T615
Test name
Test status
Simulation time 8471200965 ps
CPU time 8.34 seconds
Started Apr 18 01:16:29 PM PDT 24
Finished Apr 18 01:16:38 PM PDT 24
Peak memory 204040 kb
Host smart-da341d43-0c6c-475a-97c5-f580e62178f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15219
41647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1521941647
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.2337942047
Short name T82
Test name
Test status
Simulation time 8419126248 ps
CPU time 10.11 seconds
Started Apr 18 01:16:30 PM PDT 24
Finished Apr 18 01:16:41 PM PDT 24
Peak memory 204048 kb
Host smart-b1aa2c05-9385-4297-a219-f7c490dcdd56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23379
42047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.2337942047
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.1681911620
Short name T1254
Test name
Test status
Simulation time 8402235880 ps
CPU time 8.02 seconds
Started Apr 18 01:16:44 PM PDT 24
Finished Apr 18 01:16:53 PM PDT 24
Peak memory 203864 kb
Host smart-14c3a0c9-e4c2-45c3-86dc-fd0df90b2969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16819
11620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.1681911620
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.4287802824
Short name T1013
Test name
Test status
Simulation time 8367103793 ps
CPU time 7.57 seconds
Started Apr 18 01:16:30 PM PDT 24
Finished Apr 18 01:16:39 PM PDT 24
Peak memory 204008 kb
Host smart-1e902fdf-d87a-46e8-89a4-f6a84e634261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42878
02824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.4287802824
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.1351254042
Short name T1100
Test name
Test status
Simulation time 8439206916 ps
CPU time 8.18 seconds
Started Apr 18 01:16:31 PM PDT 24
Finished Apr 18 01:16:40 PM PDT 24
Peak memory 204048 kb
Host smart-662fac7e-efa2-4ebe-b081-9499c327e662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13512
54042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.1351254042
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.1509690392
Short name T808
Test name
Test status
Simulation time 8404982548 ps
CPU time 8.02 seconds
Started Apr 18 01:16:27 PM PDT 24
Finished Apr 18 01:16:36 PM PDT 24
Peak memory 204028 kb
Host smart-9d3a3340-8450-4f40-9de1-435ee7f0cfe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15096
90392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.1509690392
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.3108034915
Short name T1362
Test name
Test status
Simulation time 8394525595 ps
CPU time 8.44 seconds
Started Apr 18 01:16:30 PM PDT 24
Finished Apr 18 01:16:40 PM PDT 24
Peak memory 204024 kb
Host smart-fe2efc7c-5550-4d5b-aa30-69085c81f6f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31080
34915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.3108034915
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.max_length_in_transaction.25962456
Short name T412
Test name
Test status
Simulation time 8466465201 ps
CPU time 8.1 seconds
Started Apr 18 01:16:37 PM PDT 24
Finished Apr 18 01:16:45 PM PDT 24
Peak memory 204040 kb
Host smart-9c49ea6f-fec3-4f96-b6e5-2de3c103f090
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=25962456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.25962456
Directory /workspace/32.max_length_in_transaction/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.2125307818
Short name T1111
Test name
Test status
Simulation time 8381894377 ps
CPU time 9.63 seconds
Started Apr 18 01:16:41 PM PDT 24
Finished Apr 18 01:16:52 PM PDT 24
Peak memory 204004 kb
Host smart-7ce7431c-1b80-4506-8379-f8c165012b39
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2125307818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.2125307818
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.random_length_in_trans.3328689465
Short name T1066
Test name
Test status
Simulation time 8456376534 ps
CPU time 7.93 seconds
Started Apr 18 01:16:37 PM PDT 24
Finished Apr 18 01:16:45 PM PDT 24
Peak memory 203960 kb
Host smart-1c553a20-147e-4ef3-949a-1edfeb7c96b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33286
89465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.3328689465
Directory /workspace/32.random_length_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2209853227
Short name T505
Test name
Test status
Simulation time 8382695621 ps
CPU time 8.78 seconds
Started Apr 18 01:16:36 PM PDT 24
Finished Apr 18 01:16:45 PM PDT 24
Peak memory 204044 kb
Host smart-eba52460-e6f9-4463-baa9-c74335b6ea42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22098
53227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2209853227
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3298823745
Short name T79
Test name
Test status
Simulation time 169612126 ps
CPU time 1.4 seconds
Started Apr 18 01:16:36 PM PDT 24
Finished Apr 18 01:16:38 PM PDT 24
Peak memory 204024 kb
Host smart-a1ea8866-8f7a-4d9d-9780-924bb715e8e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32988
23745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3298823745
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.4280879006
Short name T50
Test name
Test status
Simulation time 8420111274 ps
CPU time 8.93 seconds
Started Apr 18 01:16:36 PM PDT 24
Finished Apr 18 01:16:45 PM PDT 24
Peak memory 203904 kb
Host smart-9fa5c265-07d7-428e-a8fd-bec481bec47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42808
79006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.4280879006
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.217128033
Short name T188
Test name
Test status
Simulation time 8361729260 ps
CPU time 7.69 seconds
Started Apr 18 01:16:35 PM PDT 24
Finished Apr 18 01:16:44 PM PDT 24
Peak memory 203996 kb
Host smart-030eb5c5-2987-4afd-ad53-5c17752fbef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21712
8033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.217128033
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.2651143504
Short name T1363
Test name
Test status
Simulation time 8420153485 ps
CPU time 8.57 seconds
Started Apr 18 01:16:42 PM PDT 24
Finished Apr 18 01:16:52 PM PDT 24
Peak memory 204024 kb
Host smart-ac4d370f-3b65-4204-b81a-669f76a9c2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26511
43504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2651143504
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1704858133
Short name T1096
Test name
Test status
Simulation time 8412266824 ps
CPU time 7.99 seconds
Started Apr 18 01:16:35 PM PDT 24
Finished Apr 18 01:16:43 PM PDT 24
Peak memory 204064 kb
Host smart-e4d5f235-3b80-4058-ac61-e12e3b763275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17048
58133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1704858133
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.1173454688
Short name T899
Test name
Test status
Simulation time 8378033800 ps
CPU time 9.6 seconds
Started Apr 18 01:16:35 PM PDT 24
Finished Apr 18 01:16:45 PM PDT 24
Peak memory 203948 kb
Host smart-8912341c-415f-4c8b-8654-8447411e84d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11734
54688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.1173454688
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.3980949755
Short name T105
Test name
Test status
Simulation time 8464548096 ps
CPU time 8.13 seconds
Started Apr 18 01:16:36 PM PDT 24
Finished Apr 18 01:16:45 PM PDT 24
Peak memory 204028 kb
Host smart-29bccdef-b86b-49eb-b5a9-4788d47a9533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39809
49755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.3980949755
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.918081742
Short name T1059
Test name
Test status
Simulation time 8404237149 ps
CPU time 7.8 seconds
Started Apr 18 01:16:34 PM PDT 24
Finished Apr 18 01:16:42 PM PDT 24
Peak memory 203996 kb
Host smart-ea64f50c-680e-4dc4-8501-7b978b4b4a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91808
1742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.918081742
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.1121950622
Short name T285
Test name
Test status
Simulation time 8441663410 ps
CPU time 8.38 seconds
Started Apr 18 01:16:34 PM PDT 24
Finished Apr 18 01:16:43 PM PDT 24
Peak memory 203980 kb
Host smart-aa0eac9d-2620-4b40-b431-e6304ee8084a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11219
50622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.1121950622
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.4265457727
Short name T194
Test name
Test status
Simulation time 8409715429 ps
CPU time 8.73 seconds
Started Apr 18 01:16:36 PM PDT 24
Finished Apr 18 01:16:46 PM PDT 24
Peak memory 204020 kb
Host smart-c1f26706-1fc0-495b-ad83-3a86a2cc75f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42654
57727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.4265457727
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.68629182
Short name T743
Test name
Test status
Simulation time 8378919990 ps
CPU time 7.85 seconds
Started Apr 18 01:16:36 PM PDT 24
Finished Apr 18 01:16:45 PM PDT 24
Peak memory 203960 kb
Host smart-9919f8f9-7c0f-46d7-8785-39e7bcda1d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68629
182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.68629182
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.1178469051
Short name T1053
Test name
Test status
Simulation time 81743829 ps
CPU time 0.76 seconds
Started Apr 18 01:16:41 PM PDT 24
Finished Apr 18 01:16:43 PM PDT 24
Peak memory 203864 kb
Host smart-e339afab-d7b6-43a5-ba00-035826dd7f0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11784
69051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.1178469051
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.1659648112
Short name T212
Test name
Test status
Simulation time 22370145216 ps
CPU time 39.99 seconds
Started Apr 18 01:16:36 PM PDT 24
Finished Apr 18 01:17:17 PM PDT 24
Peak memory 204268 kb
Host smart-e99c2432-5463-425b-ab26-eb439bbc8dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16596
48112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1659648112
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.80641884
Short name T85
Test name
Test status
Simulation time 8378526873 ps
CPU time 7.73 seconds
Started Apr 18 01:16:33 PM PDT 24
Finished Apr 18 01:16:41 PM PDT 24
Peak memory 203872 kb
Host smart-0e589b6b-ea08-4206-9734-2f732ced8ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80641
884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.80641884
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.2633713334
Short name T964
Test name
Test status
Simulation time 8429343867 ps
CPU time 7.63 seconds
Started Apr 18 01:16:35 PM PDT 24
Finished Apr 18 01:16:43 PM PDT 24
Peak memory 203920 kb
Host smart-b6bc4e91-e761-4a0c-a471-342d1dac52f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26337
13334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.2633713334
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.195398209
Short name T72
Test name
Test status
Simulation time 8418507182 ps
CPU time 9.73 seconds
Started Apr 18 01:16:38 PM PDT 24
Finished Apr 18 01:16:49 PM PDT 24
Peak memory 203964 kb
Host smart-a47a8add-a52e-487e-b556-c0f51d59ed6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19539
8209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.195398209
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.763212245
Short name T828
Test name
Test status
Simulation time 8379310029 ps
CPU time 9.6 seconds
Started Apr 18 01:16:41 PM PDT 24
Finished Apr 18 01:16:52 PM PDT 24
Peak memory 203996 kb
Host smart-fba5e0e0-9dbb-4363-905b-b0ce92509b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76321
2245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.763212245
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.1936913244
Short name T656
Test name
Test status
Simulation time 8375304932 ps
CPU time 7.69 seconds
Started Apr 18 01:16:35 PM PDT 24
Finished Apr 18 01:16:44 PM PDT 24
Peak memory 204020 kb
Host smart-df5baf8d-5432-4b32-b83c-38e18d633289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19369
13244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1936913244
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.731897637
Short name T148
Test name
Test status
Simulation time 8418340565 ps
CPU time 7.81 seconds
Started Apr 18 01:16:35 PM PDT 24
Finished Apr 18 01:16:44 PM PDT 24
Peak memory 204004 kb
Host smart-914025fa-f8d7-4832-b044-aa1458b1bfe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73189
7637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.731897637
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.2389772906
Short name T950
Test name
Test status
Simulation time 8388761733 ps
CPU time 9.22 seconds
Started Apr 18 01:16:38 PM PDT 24
Finished Apr 18 01:16:48 PM PDT 24
Peak memory 204004 kb
Host smart-f53538f8-0266-43f1-bd1b-cccd0620326b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23897
72906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.2389772906
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.643203828
Short name T723
Test name
Test status
Simulation time 8437631819 ps
CPU time 8.37 seconds
Started Apr 18 01:16:37 PM PDT 24
Finished Apr 18 01:16:46 PM PDT 24
Peak memory 203984 kb
Host smart-373873cd-9b12-40ac-b8e2-cee10ed4a9c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64320
3828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.643203828
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.719723161
Short name T1202
Test name
Test status
Simulation time 8458810270 ps
CPU time 8.05 seconds
Started Apr 18 01:16:43 PM PDT 24
Finished Apr 18 01:16:52 PM PDT 24
Peak memory 203976 kb
Host smart-58148f68-33b2-4d99-9951-e31927bbdfc7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=719723161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.719723161
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.3658334187
Short name T361
Test name
Test status
Simulation time 8375640352 ps
CPU time 9.17 seconds
Started Apr 18 01:16:44 PM PDT 24
Finished Apr 18 01:16:53 PM PDT 24
Peak memory 204020 kb
Host smart-99f9c8b8-f711-4865-bf20-dae413595779
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3658334187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.3658334187
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.2504704204
Short name T633
Test name
Test status
Simulation time 8385579961 ps
CPU time 8.3 seconds
Started Apr 18 01:16:40 PM PDT 24
Finished Apr 18 01:16:49 PM PDT 24
Peak memory 203980 kb
Host smart-64e672fe-09ec-4f04-9d56-c929192b823f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25047
04204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.2504704204
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.1750807491
Short name T1142
Test name
Test status
Simulation time 8399274684 ps
CPU time 7.71 seconds
Started Apr 18 01:16:35 PM PDT 24
Finished Apr 18 01:16:43 PM PDT 24
Peak memory 203980 kb
Host smart-b6cd5dc8-3756-4df2-8285-f629cc4dfa33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17508
07491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1750807491
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_enable.518546267
Short name T645
Test name
Test status
Simulation time 8379423704 ps
CPU time 8.78 seconds
Started Apr 18 01:16:41 PM PDT 24
Finished Apr 18 01:16:51 PM PDT 24
Peak memory 204004 kb
Host smart-08d68118-7a4b-41fb-b3a3-e99739d39621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51854
6267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.518546267
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.2796939540
Short name T791
Test name
Test status
Simulation time 168942755 ps
CPU time 1.55 seconds
Started Apr 18 01:16:41 PM PDT 24
Finished Apr 18 01:16:44 PM PDT 24
Peak memory 204116 kb
Host smart-121cab12-89a3-4fac-9b34-34379763447e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27969
39540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2796939540
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.1320642773
Short name T896
Test name
Test status
Simulation time 8468982295 ps
CPU time 7.92 seconds
Started Apr 18 01:16:54 PM PDT 24
Finished Apr 18 01:17:04 PM PDT 24
Peak memory 204024 kb
Host smart-16cb9be2-7952-4b87-8f4f-c59b744b8823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13206
42773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.1320642773
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.3393478848
Short name T890
Test name
Test status
Simulation time 8387498609 ps
CPU time 8.78 seconds
Started Apr 18 01:16:49 PM PDT 24
Finished Apr 18 01:16:58 PM PDT 24
Peak memory 204020 kb
Host smart-bd0d6e56-99c8-40f0-94e9-e028fef1fc82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33934
78848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.3393478848
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.1862664187
Short name T400
Test name
Test status
Simulation time 8459466924 ps
CPU time 9.73 seconds
Started Apr 18 01:16:46 PM PDT 24
Finished Apr 18 01:16:56 PM PDT 24
Peak memory 204000 kb
Host smart-8957f894-831d-4fd7-b224-0a75c8745e1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18626
64187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.1862664187
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1808759011
Short name T873
Test name
Test status
Simulation time 8414561698 ps
CPU time 8.85 seconds
Started Apr 18 01:16:45 PM PDT 24
Finished Apr 18 01:16:54 PM PDT 24
Peak memory 203996 kb
Host smart-c1956495-5d03-4e82-a432-8a9bcb3c8185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18087
59011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1808759011
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.3450863083
Short name T985
Test name
Test status
Simulation time 8372837051 ps
CPU time 8.16 seconds
Started Apr 18 01:16:42 PM PDT 24
Finished Apr 18 01:16:51 PM PDT 24
Peak memory 204044 kb
Host smart-dae218c6-1978-4b2d-a1da-830e104a8527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34508
63083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.3450863083
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.49709948
Short name T93
Test name
Test status
Simulation time 8423448634 ps
CPU time 8.17 seconds
Started Apr 18 01:16:39 PM PDT 24
Finished Apr 18 01:16:48 PM PDT 24
Peak memory 204016 kb
Host smart-44d9390f-4ed0-4a4f-bbf2-62a85c90054c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49709
948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.49709948
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3875461574
Short name T745
Test name
Test status
Simulation time 8416284570 ps
CPU time 9.65 seconds
Started Apr 18 01:16:40 PM PDT 24
Finished Apr 18 01:16:50 PM PDT 24
Peak memory 204044 kb
Host smart-9056ca59-94e7-4306-b61c-8bade80d030c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38754
61574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3875461574
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2091591694
Short name T448
Test name
Test status
Simulation time 8451655093 ps
CPU time 8.34 seconds
Started Apr 18 01:16:49 PM PDT 24
Finished Apr 18 01:16:58 PM PDT 24
Peak memory 204024 kb
Host smart-44ee71f8-9cbd-486a-a5e3-57be32f3355a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20915
91694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2091591694
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.1397318404
Short name T930
Test name
Test status
Simulation time 8418375446 ps
CPU time 7.72 seconds
Started Apr 18 01:16:42 PM PDT 24
Finished Apr 18 01:16:51 PM PDT 24
Peak memory 204004 kb
Host smart-53c8f7b8-1f3e-4d34-8611-4e9727cf1c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13973
18404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.1397318404
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.1508535748
Short name T1119
Test name
Test status
Simulation time 8376529213 ps
CPU time 7.83 seconds
Started Apr 18 01:16:39 PM PDT 24
Finished Apr 18 01:16:47 PM PDT 24
Peak memory 204064 kb
Host smart-fbb2e52b-c185-4832-8652-c1307a92a44d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15085
35748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.1508535748
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.2320249868
Short name T1162
Test name
Test status
Simulation time 80596085 ps
CPU time 0.67 seconds
Started Apr 18 01:16:45 PM PDT 24
Finished Apr 18 01:16:46 PM PDT 24
Peak memory 203880 kb
Host smart-4275a5fd-f3cb-48d5-88af-85731b12fcaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23202
49868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.2320249868
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.2701992194
Short name T1279
Test name
Test status
Simulation time 15174792402 ps
CPU time 24.12 seconds
Started Apr 18 01:16:41 PM PDT 24
Finished Apr 18 01:17:06 PM PDT 24
Peak memory 204288 kb
Host smart-a801f13e-db48-4e38-842c-588a1b93709f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27019
92194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.2701992194
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.242835428
Short name T424
Test name
Test status
Simulation time 8386881778 ps
CPU time 10.66 seconds
Started Apr 18 01:16:44 PM PDT 24
Finished Apr 18 01:16:56 PM PDT 24
Peak memory 204008 kb
Host smart-dc0b2a95-e841-47c0-8c7e-a9326154f10f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24283
5428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.242835428
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.3780522948
Short name T77
Test name
Test status
Simulation time 8477407220 ps
CPU time 8.3 seconds
Started Apr 18 01:16:41 PM PDT 24
Finished Apr 18 01:16:50 PM PDT 24
Peak memory 203940 kb
Host smart-ca7fc7f9-ae20-4ec1-bbf7-6fc4e338cdc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37805
22948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3780522948
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.2177211235
Short name T921
Test name
Test status
Simulation time 8451179692 ps
CPU time 7.87 seconds
Started Apr 18 01:16:46 PM PDT 24
Finished Apr 18 01:16:54 PM PDT 24
Peak memory 204004 kb
Host smart-2e6970eb-022b-486b-afee-f34775ed2694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21772
11235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.2177211235
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.2119558811
Short name T1045
Test name
Test status
Simulation time 8385552275 ps
CPU time 8.64 seconds
Started Apr 18 01:16:42 PM PDT 24
Finished Apr 18 01:16:51 PM PDT 24
Peak memory 204024 kb
Host smart-6b6e4d34-2ca3-4b53-a778-c0a21055b778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21195
58811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.2119558811
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.3365204054
Short name T465
Test name
Test status
Simulation time 8373413664 ps
CPU time 8.37 seconds
Started Apr 18 01:16:41 PM PDT 24
Finished Apr 18 01:16:51 PM PDT 24
Peak memory 204012 kb
Host smart-58e3e1c5-bee1-4ff0-a8e9-04043a23bd7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33652
04054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3365204054
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.377821906
Short name T171
Test name
Test status
Simulation time 8440672631 ps
CPU time 9.94 seconds
Started Apr 18 01:16:37 PM PDT 24
Finished Apr 18 01:16:48 PM PDT 24
Peak memory 203960 kb
Host smart-57888a08-7ec4-4cc9-84c7-99476d19db0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37782
1906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.377821906
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.2234007617
Short name T886
Test name
Test status
Simulation time 8370917573 ps
CPU time 7.39 seconds
Started Apr 18 01:16:38 PM PDT 24
Finished Apr 18 01:16:46 PM PDT 24
Peak memory 204040 kb
Host smart-b1255536-7cd2-4e2f-88c4-618a1bb9d576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22340
07617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.2234007617
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.1832915742
Short name T507
Test name
Test status
Simulation time 8378528324 ps
CPU time 7.44 seconds
Started Apr 18 01:16:42 PM PDT 24
Finished Apr 18 01:16:50 PM PDT 24
Peak memory 203928 kb
Host smart-93e47e50-e787-4475-a079-93c6ec73cd3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18329
15742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.1832915742
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.538878057
Short name T701
Test name
Test status
Simulation time 8481202455 ps
CPU time 9.04 seconds
Started Apr 18 01:16:52 PM PDT 24
Finished Apr 18 01:17:02 PM PDT 24
Peak memory 204008 kb
Host smart-62d3f8bb-c068-4786-b06f-45024bb06391
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=538878057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.538878057
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.1793570574
Short name T815
Test name
Test status
Simulation time 8395819206 ps
CPU time 7.68 seconds
Started Apr 18 01:16:47 PM PDT 24
Finished Apr 18 01:16:55 PM PDT 24
Peak memory 204048 kb
Host smart-99adc213-09b3-4776-bfd1-13e7cfa26e8f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1793570574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.1793570574
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.807092798
Short name T1049
Test name
Test status
Simulation time 8435745361 ps
CPU time 10.16 seconds
Started Apr 18 01:16:48 PM PDT 24
Finished Apr 18 01:16:58 PM PDT 24
Peak memory 203928 kb
Host smart-b45f4cd7-3d13-440f-a4a2-e58491e0d597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80709
2798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.807092798
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.3418999588
Short name T288
Test name
Test status
Simulation time 8371797425 ps
CPU time 7.99 seconds
Started Apr 18 01:16:40 PM PDT 24
Finished Apr 18 01:16:49 PM PDT 24
Peak memory 204020 kb
Host smart-4e8006f2-92a0-4023-b441-538444813cd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34189
99588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.3418999588
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_enable.573927539
Short name T769
Test name
Test status
Simulation time 8376305798 ps
CPU time 8.05 seconds
Started Apr 18 01:16:43 PM PDT 24
Finished Apr 18 01:16:52 PM PDT 24
Peak memory 204028 kb
Host smart-2cf978f8-9915-4c67-b364-699cc8a4ae29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57392
7539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.573927539
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.635910590
Short name T876
Test name
Test status
Simulation time 8385596999 ps
CPU time 8.46 seconds
Started Apr 18 01:16:52 PM PDT 24
Finished Apr 18 01:17:02 PM PDT 24
Peak memory 204044 kb
Host smart-0a3f9c7f-14ad-4175-8059-e2e464fbc2b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63591
0590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.635910590
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.2228050258
Short name T185
Test name
Test status
Simulation time 8370120557 ps
CPU time 7.49 seconds
Started Apr 18 01:16:46 PM PDT 24
Finished Apr 18 01:16:54 PM PDT 24
Peak memory 204040 kb
Host smart-041aece0-6b44-49fa-984f-0ed4e3898729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22280
50258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2228050258
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.1751536684
Short name T472
Test name
Test status
Simulation time 8415527264 ps
CPU time 9.51 seconds
Started Apr 18 01:16:41 PM PDT 24
Finished Apr 18 01:16:52 PM PDT 24
Peak memory 203956 kb
Host smart-a9c3c229-78f5-40eb-ab6c-11d4e8d3944f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17515
36684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.1751536684
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.2837231440
Short name T409
Test name
Test status
Simulation time 8448024850 ps
CPU time 8.58 seconds
Started Apr 18 01:16:43 PM PDT 24
Finished Apr 18 01:16:52 PM PDT 24
Peak memory 203908 kb
Host smart-7c617fb3-70ea-4967-8fec-8c1b84d1f644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28372
31440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.2837231440
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.1445538441
Short name T1136
Test name
Test status
Simulation time 8403188607 ps
CPU time 8.05 seconds
Started Apr 18 01:16:40 PM PDT 24
Finished Apr 18 01:16:48 PM PDT 24
Peak memory 204052 kb
Host smart-00960927-b9c5-4d2e-9474-40e138f966a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14455
38441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.1445538441
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.303673194
Short name T1015
Test name
Test status
Simulation time 8435739668 ps
CPU time 8.69 seconds
Started Apr 18 01:16:42 PM PDT 24
Finished Apr 18 01:16:52 PM PDT 24
Peak memory 204028 kb
Host smart-1cde6a7c-54cc-449c-b184-ae5ea87f8a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30367
3194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.303673194
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2252615906
Short name T730
Test name
Test status
Simulation time 8380106884 ps
CPU time 8.92 seconds
Started Apr 18 01:16:44 PM PDT 24
Finished Apr 18 01:16:53 PM PDT 24
Peak memory 204028 kb
Host smart-37c0ebaf-d676-425b-91d8-71276e4cd8b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22526
15906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2252615906
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.2953763716
Short name T684
Test name
Test status
Simulation time 8379190268 ps
CPU time 8.51 seconds
Started Apr 18 01:16:42 PM PDT 24
Finished Apr 18 01:16:51 PM PDT 24
Peak memory 204012 kb
Host smart-710135ab-6d96-4412-8319-559f5930b2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29537
63716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.2953763716
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.2460639100
Short name T496
Test name
Test status
Simulation time 8417523261 ps
CPU time 8.58 seconds
Started Apr 18 01:16:46 PM PDT 24
Finished Apr 18 01:16:55 PM PDT 24
Peak memory 203976 kb
Host smart-8fef0e54-7c1e-4ce5-b5a5-b683788bc10e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24606
39100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.2460639100
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.4277313010
Short name T310
Test name
Test status
Simulation time 8369859715 ps
CPU time 7.87 seconds
Started Apr 18 01:16:46 PM PDT 24
Finished Apr 18 01:16:54 PM PDT 24
Peak memory 203992 kb
Host smart-32f67584-d11e-46bb-bab9-709850f48543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42773
13010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.4277313010
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.528351147
Short name T952
Test name
Test status
Simulation time 39484668 ps
CPU time 0.66 seconds
Started Apr 18 01:16:47 PM PDT 24
Finished Apr 18 01:16:49 PM PDT 24
Peak memory 203856 kb
Host smart-4fd9473e-5a4c-46ef-b0c9-0362c4ba6109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52835
1147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.528351147
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.748050526
Short name T1156
Test name
Test status
Simulation time 15963011119 ps
CPU time 26.63 seconds
Started Apr 18 01:16:40 PM PDT 24
Finished Apr 18 01:17:08 PM PDT 24
Peak memory 204324 kb
Host smart-dd989247-2cb5-4b73-9f74-47436ae614f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74805
0526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.748050526
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.4278101529
Short name T1083
Test name
Test status
Simulation time 8408096765 ps
CPU time 8.5 seconds
Started Apr 18 01:16:40 PM PDT 24
Finished Apr 18 01:16:49 PM PDT 24
Peak memory 203980 kb
Host smart-47896d8d-f67d-463b-825e-cfbed64185ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42781
01529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.4278101529
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.3703136157
Short name T134
Test name
Test status
Simulation time 8423903516 ps
CPU time 8.79 seconds
Started Apr 18 01:16:42 PM PDT 24
Finished Apr 18 01:16:51 PM PDT 24
Peak memory 203944 kb
Host smart-32e104d1-0d3d-43c9-8fae-3b6b48cedad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37031
36157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.3703136157
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.2863165940
Short name T1240
Test name
Test status
Simulation time 8426823611 ps
CPU time 8.7 seconds
Started Apr 18 01:16:42 PM PDT 24
Finished Apr 18 01:16:52 PM PDT 24
Peak memory 204028 kb
Host smart-2480085a-03bf-44a5-ad82-e34d74404453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28631
65940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.2863165940
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.4041775393
Short name T163
Test name
Test status
Simulation time 8380212480 ps
CPU time 10.12 seconds
Started Apr 18 01:16:50 PM PDT 24
Finished Apr 18 01:17:00 PM PDT 24
Peak memory 204024 kb
Host smart-54bd93a2-d14b-4391-af21-78c04cf9d184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40417
75393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.4041775393
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.4252941289
Short name T501
Test name
Test status
Simulation time 8373575699 ps
CPU time 8 seconds
Started Apr 18 01:17:06 PM PDT 24
Finished Apr 18 01:17:15 PM PDT 24
Peak memory 203996 kb
Host smart-edcda275-df94-4937-8097-f3419572c806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42529
41289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.4252941289
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.2600838870
Short name T1176
Test name
Test status
Simulation time 8477825782 ps
CPU time 10.6 seconds
Started Apr 18 01:16:41 PM PDT 24
Finished Apr 18 01:16:53 PM PDT 24
Peak memory 203940 kb
Host smart-0f988eaa-df31-43fe-b2c0-ae6951f16e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26008
38870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2600838870
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.2169033579
Short name T1365
Test name
Test status
Simulation time 8411242703 ps
CPU time 7.85 seconds
Started Apr 18 01:16:49 PM PDT 24
Finished Apr 18 01:16:57 PM PDT 24
Peak memory 204040 kb
Host smart-039bbbc8-0b8c-411e-8357-42e815853be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21690
33579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.2169033579
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.2100662850
Short name T1092
Test name
Test status
Simulation time 8389593483 ps
CPU time 8.06 seconds
Started Apr 18 01:16:54 PM PDT 24
Finished Apr 18 01:17:04 PM PDT 24
Peak memory 204036 kb
Host smart-0e682319-a8d4-418f-a648-ca4a9110b5c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21006
62850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.2100662850
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.1109419133
Short name T957
Test name
Test status
Simulation time 8466797460 ps
CPU time 8.17 seconds
Started Apr 18 01:16:48 PM PDT 24
Finished Apr 18 01:16:57 PM PDT 24
Peak memory 204028 kb
Host smart-707ba870-096b-4652-b3f3-5207689f34fc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1109419133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.1109419133
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.2014716091
Short name T301
Test name
Test status
Simulation time 8384520888 ps
CPU time 8.06 seconds
Started Apr 18 01:16:48 PM PDT 24
Finished Apr 18 01:16:57 PM PDT 24
Peak memory 203972 kb
Host smart-d03502e9-c378-4d16-8964-397a2f1bba3d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2014716091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.2014716091
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.226537011
Short name T1192
Test name
Test status
Simulation time 8399699729 ps
CPU time 8.19 seconds
Started Apr 18 01:16:46 PM PDT 24
Finished Apr 18 01:16:55 PM PDT 24
Peak memory 204064 kb
Host smart-dc81445b-ee91-48a5-bfca-a5313c3baf36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22653
7011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.226537011
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.905817610
Short name T321
Test name
Test status
Simulation time 8374324559 ps
CPU time 8.25 seconds
Started Apr 18 01:16:50 PM PDT 24
Finished Apr 18 01:16:59 PM PDT 24
Peak memory 204020 kb
Host smart-2dd7aa41-0eea-4399-9e7f-53d4e9cf5068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90581
7610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.905817610
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_enable.589820762
Short name T541
Test name
Test status
Simulation time 8381226697 ps
CPU time 8.05 seconds
Started Apr 18 01:16:48 PM PDT 24
Finished Apr 18 01:16:56 PM PDT 24
Peak memory 204004 kb
Host smart-0fcec775-4c56-4b99-b829-172b2b717e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58982
0762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.589820762
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.2605799767
Short name T1074
Test name
Test status
Simulation time 232387590 ps
CPU time 1.92 seconds
Started Apr 18 01:16:54 PM PDT 24
Finished Apr 18 01:16:58 PM PDT 24
Peak memory 204168 kb
Host smart-4018915a-baf7-42d7-a558-554c947440c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26057
99767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.2605799767
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.99109917
Short name T764
Test name
Test status
Simulation time 8406473715 ps
CPU time 9.84 seconds
Started Apr 18 01:16:50 PM PDT 24
Finished Apr 18 01:17:01 PM PDT 24
Peak memory 204000 kb
Host smart-843534b7-4609-4d5f-9335-5fc9f8da43e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99109
917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.99109917
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.131267346
Short name T884
Test name
Test status
Simulation time 8395982009 ps
CPU time 8.89 seconds
Started Apr 18 01:16:49 PM PDT 24
Finished Apr 18 01:16:59 PM PDT 24
Peak memory 204008 kb
Host smart-b26d7bbe-64e5-47cb-9fdc-b12d0d8f65aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13126
7346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.131267346
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.3560402537
Short name T813
Test name
Test status
Simulation time 8482825103 ps
CPU time 7.52 seconds
Started Apr 18 01:16:52 PM PDT 24
Finished Apr 18 01:17:01 PM PDT 24
Peak memory 204000 kb
Host smart-9faa7aac-d94a-472a-8bda-8b287eb4865c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35604
02537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.3560402537
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.3542645703
Short name T1008
Test name
Test status
Simulation time 8419836930 ps
CPU time 8.27 seconds
Started Apr 18 01:16:47 PM PDT 24
Finished Apr 18 01:16:56 PM PDT 24
Peak memory 203964 kb
Host smart-afba45cf-819d-47f7-a252-78fa8f5f0ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35426
45703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3542645703
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2064869338
Short name T1378
Test name
Test status
Simulation time 8373744167 ps
CPU time 7.58 seconds
Started Apr 18 01:16:49 PM PDT 24
Finished Apr 18 01:16:57 PM PDT 24
Peak memory 203864 kb
Host smart-859d8997-d9ac-4a88-a6eb-71a2d37aaafa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20648
69338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2064869338
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2149139682
Short name T109
Test name
Test status
Simulation time 8440135363 ps
CPU time 10.23 seconds
Started Apr 18 01:16:47 PM PDT 24
Finished Apr 18 01:16:58 PM PDT 24
Peak memory 203972 kb
Host smart-b4db4c52-7adf-47b2-834f-7e7f2b3d01b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21491
39682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2149139682
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3038066735
Short name T1349
Test name
Test status
Simulation time 8393951710 ps
CPU time 9.15 seconds
Started Apr 18 01:16:50 PM PDT 24
Finished Apr 18 01:17:00 PM PDT 24
Peak memory 204032 kb
Host smart-b221f129-a55d-40fb-874e-4e8cedd4c7fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30380
66735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3038066735
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.378148768
Short name T1046
Test name
Test status
Simulation time 8411311839 ps
CPU time 9.8 seconds
Started Apr 18 01:16:47 PM PDT 24
Finished Apr 18 01:16:58 PM PDT 24
Peak memory 203944 kb
Host smart-24098060-3a6c-4f2b-b57e-7153f306e61c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37814
8768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.378148768
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.331882181
Short name T1099
Test name
Test status
Simulation time 8372924525 ps
CPU time 7.92 seconds
Started Apr 18 01:16:47 PM PDT 24
Finished Apr 18 01:16:56 PM PDT 24
Peak memory 204044 kb
Host smart-a9a09f25-8015-4277-aebc-54afa308b498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33188
2181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.331882181
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.2670228913
Short name T916
Test name
Test status
Simulation time 8390352724 ps
CPU time 9.66 seconds
Started Apr 18 01:16:53 PM PDT 24
Finished Apr 18 01:17:04 PM PDT 24
Peak memory 204036 kb
Host smart-5e9f0633-053a-4ee3-acae-4b74e6a97d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26702
28913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.2670228913
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.1038602185
Short name T447
Test name
Test status
Simulation time 33677128 ps
CPU time 0.68 seconds
Started Apr 18 01:16:51 PM PDT 24
Finished Apr 18 01:16:52 PM PDT 24
Peak memory 203892 kb
Host smart-88b93cd3-0114-4ec8-985e-1c6bc4a6dd7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10386
02185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.1038602185
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.1285238352
Short name T992
Test name
Test status
Simulation time 16524680377 ps
CPU time 29.17 seconds
Started Apr 18 01:16:49 PM PDT 24
Finished Apr 18 01:17:19 PM PDT 24
Peak memory 204296 kb
Host smart-e7d7daff-5cec-4e57-b485-85bf475ddfce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12852
38352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1285238352
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.702229935
Short name T1352
Test name
Test status
Simulation time 8381150897 ps
CPU time 7.53 seconds
Started Apr 18 01:16:47 PM PDT 24
Finished Apr 18 01:16:55 PM PDT 24
Peak memory 204264 kb
Host smart-a1bf2e6e-8220-4bd7-b2ab-64895ba7199c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70222
9935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.702229935
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.3903076990
Short name T1239
Test name
Test status
Simulation time 8439914379 ps
CPU time 7.92 seconds
Started Apr 18 01:16:49 PM PDT 24
Finished Apr 18 01:16:58 PM PDT 24
Peak memory 204020 kb
Host smart-0e452f97-6afd-43b5-b704-6f310a51d145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39030
76990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3903076990
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.3255960666
Short name T1233
Test name
Test status
Simulation time 8399434415 ps
CPU time 7.72 seconds
Started Apr 18 01:16:52 PM PDT 24
Finished Apr 18 01:17:01 PM PDT 24
Peak memory 203944 kb
Host smart-eaf6f423-c4b4-40ec-a624-383e2546cf93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32559
60666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.3255960666
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.4106813813
Short name T843
Test name
Test status
Simulation time 8390030144 ps
CPU time 8.39 seconds
Started Apr 18 01:16:49 PM PDT 24
Finished Apr 18 01:16:58 PM PDT 24
Peak memory 204024 kb
Host smart-c6559c5e-7ebe-4047-abfb-46a8de08b402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41068
13813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.4106813813
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.2818451229
Short name T475
Test name
Test status
Simulation time 8377336402 ps
CPU time 9.47 seconds
Started Apr 18 01:16:54 PM PDT 24
Finished Apr 18 01:17:06 PM PDT 24
Peak memory 204048 kb
Host smart-aa6ee4b2-41d2-4293-800f-a539dc14740b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28184
51229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.2818451229
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.2649657103
Short name T528
Test name
Test status
Simulation time 8435328179 ps
CPU time 9.06 seconds
Started Apr 18 01:16:46 PM PDT 24
Finished Apr 18 01:16:55 PM PDT 24
Peak memory 204008 kb
Host smart-90809012-ed97-46fc-83be-a6024053e78f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26496
57103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2649657103
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3019007369
Short name T624
Test name
Test status
Simulation time 8383361337 ps
CPU time 8.78 seconds
Started Apr 18 01:16:49 PM PDT 24
Finished Apr 18 01:16:58 PM PDT 24
Peak memory 203916 kb
Host smart-3c591312-5239-4fd9-9ee2-5f6954fd724c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30190
07369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3019007369
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.2098352307
Short name T1361
Test name
Test status
Simulation time 8415381990 ps
CPU time 9.55 seconds
Started Apr 18 01:16:52 PM PDT 24
Finished Apr 18 01:17:03 PM PDT 24
Peak memory 204020 kb
Host smart-5918c33e-12dc-48b3-b1b1-17710f503eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20983
52307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.2098352307
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.3223570938
Short name T1019
Test name
Test status
Simulation time 8465542110 ps
CPU time 7.98 seconds
Started Apr 18 01:16:57 PM PDT 24
Finished Apr 18 01:17:08 PM PDT 24
Peak memory 204052 kb
Host smart-3f5c5b6a-87e4-47a0-893d-19831a8cba40
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3223570938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.3223570938
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.1416109062
Short name T1124
Test name
Test status
Simulation time 8387423547 ps
CPU time 10.03 seconds
Started Apr 18 01:16:56 PM PDT 24
Finished Apr 18 01:17:09 PM PDT 24
Peak memory 204048 kb
Host smart-3802cedb-57f8-4e45-a366-9e1f69735ae1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1416109062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.1416109062
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.796676358
Short name T1226
Test name
Test status
Simulation time 8445573971 ps
CPU time 9.02 seconds
Started Apr 18 01:16:54 PM PDT 24
Finished Apr 18 01:17:05 PM PDT 24
Peak memory 203904 kb
Host smart-e0d56968-f30a-4189-b5f6-7727b3dd0aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79667
6358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.796676358
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.3146400708
Short name T428
Test name
Test status
Simulation time 8391991728 ps
CPU time 7.85 seconds
Started Apr 18 01:16:51 PM PDT 24
Finished Apr 18 01:17:00 PM PDT 24
Peak memory 204004 kb
Host smart-6faa7f4f-2e42-48af-87ae-b7e17bad53bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31464
00708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.3146400708
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_enable.2226604441
Short name T767
Test name
Test status
Simulation time 8377059306 ps
CPU time 8.78 seconds
Started Apr 18 01:16:52 PM PDT 24
Finished Apr 18 01:17:02 PM PDT 24
Peak memory 204044 kb
Host smart-d01f3106-92f0-4065-b45b-0eebe05d00a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22266
04441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.2226604441
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.443803491
Short name T322
Test name
Test status
Simulation time 272838239 ps
CPU time 1.96 seconds
Started Apr 18 01:16:47 PM PDT 24
Finished Apr 18 01:16:49 PM PDT 24
Peak memory 203992 kb
Host smart-b4ad2153-0d05-43d3-969e-9d10a0eb417d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44380
3491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.443803491
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.2783440721
Short name T844
Test name
Test status
Simulation time 8483694059 ps
CPU time 8.34 seconds
Started Apr 18 01:16:56 PM PDT 24
Finished Apr 18 01:17:07 PM PDT 24
Peak memory 203992 kb
Host smart-2cf92d2d-cecc-4e8b-a87e-042bf38c6595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27834
40721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.2783440721
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.1726066691
Short name T191
Test name
Test status
Simulation time 8373678594 ps
CPU time 7.8 seconds
Started Apr 18 01:16:53 PM PDT 24
Finished Apr 18 01:17:03 PM PDT 24
Peak memory 203940 kb
Host smart-d7a8e1b3-152a-4f59-a040-e828eee13e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17260
66691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.1726066691
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2173114331
Short name T792
Test name
Test status
Simulation time 8385131940 ps
CPU time 9.86 seconds
Started Apr 18 01:16:48 PM PDT 24
Finished Apr 18 01:16:59 PM PDT 24
Peak memory 204080 kb
Host smart-6016352f-620a-4158-b93a-11405cce281d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21731
14331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2173114331
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.2481680508
Short name T328
Test name
Test status
Simulation time 8416898470 ps
CPU time 8.12 seconds
Started Apr 18 01:16:47 PM PDT 24
Finished Apr 18 01:16:56 PM PDT 24
Peak memory 204004 kb
Host smart-dd68f581-a76a-4561-b069-2802ee10ba9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24816
80508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2481680508
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.3133170554
Short name T341
Test name
Test status
Simulation time 8363946807 ps
CPU time 8.16 seconds
Started Apr 18 01:16:48 PM PDT 24
Finished Apr 18 01:16:57 PM PDT 24
Peak memory 203932 kb
Host smart-3ed30b01-3e81-4b8d-aed6-8e498d671789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31331
70554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.3133170554
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.3847849263
Short name T107
Test name
Test status
Simulation time 8429037861 ps
CPU time 10.51 seconds
Started Apr 18 01:16:48 PM PDT 24
Finished Apr 18 01:17:00 PM PDT 24
Peak memory 204032 kb
Host smart-dce9761b-cca3-41fe-8686-9f2727b5c4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38478
49263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.3847849263
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.4168662706
Short name T1167
Test name
Test status
Simulation time 8406043353 ps
CPU time 8.24 seconds
Started Apr 18 01:16:48 PM PDT 24
Finished Apr 18 01:16:57 PM PDT 24
Peak memory 204036 kb
Host smart-eb9e393f-7fa6-4ba1-90a4-f95324bfb42c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41686
62706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.4168662706
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1550165396
Short name T435
Test name
Test status
Simulation time 8421689656 ps
CPU time 7.42 seconds
Started Apr 18 01:16:51 PM PDT 24
Finished Apr 18 01:16:59 PM PDT 24
Peak memory 204032 kb
Host smart-29338e91-d295-4bba-9aa5-9506db9479b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15501
65396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1550165396
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.121987503
Short name T1082
Test name
Test status
Simulation time 8382041791 ps
CPU time 7.81 seconds
Started Apr 18 01:16:53 PM PDT 24
Finished Apr 18 01:17:03 PM PDT 24
Peak memory 204036 kb
Host smart-1bca25e0-1903-4f7f-9e1f-994f1770e564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12198
7503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.121987503
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.3634415743
Short name T1128
Test name
Test status
Simulation time 35935053 ps
CPU time 0.69 seconds
Started Apr 18 01:16:54 PM PDT 24
Finished Apr 18 01:16:57 PM PDT 24
Peak memory 203896 kb
Host smart-439b0406-d687-4c8d-9a1b-d46c3c0444aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36344
15743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.3634415743
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3470077592
Short name T1018
Test name
Test status
Simulation time 14966135712 ps
CPU time 24.91 seconds
Started Apr 18 01:16:51 PM PDT 24
Finished Apr 18 01:17:17 PM PDT 24
Peak memory 204320 kb
Host smart-6a10ebed-bfc8-4d91-8735-adc2a54775c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34700
77592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3470077592
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3153322616
Short name T519
Test name
Test status
Simulation time 8399476560 ps
CPU time 9.78 seconds
Started Apr 18 01:16:52 PM PDT 24
Finished Apr 18 01:17:03 PM PDT 24
Peak memory 203944 kb
Host smart-66c086a9-8f99-471e-8623-bd9a033acfc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31533
22616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3153322616
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.3505267212
Short name T600
Test name
Test status
Simulation time 8412213795 ps
CPU time 10.06 seconds
Started Apr 18 01:16:54 PM PDT 24
Finished Apr 18 01:17:06 PM PDT 24
Peak memory 204028 kb
Host smart-c8143717-53df-4917-909e-5951deff8e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35052
67212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3505267212
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.624326929
Short name T1175
Test name
Test status
Simulation time 8421198138 ps
CPU time 8.35 seconds
Started Apr 18 01:16:55 PM PDT 24
Finished Apr 18 01:17:07 PM PDT 24
Peak memory 204028 kb
Host smart-b91f1593-5584-45e0-91f3-e2b22055e8f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62432
6929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.624326929
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.247940516
Short name T628
Test name
Test status
Simulation time 8381130052 ps
CPU time 7.41 seconds
Started Apr 18 01:16:55 PM PDT 24
Finished Apr 18 01:17:05 PM PDT 24
Peak memory 203984 kb
Host smart-9d4da650-faa4-4b0b-a5a6-a3a0f3457037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24794
0516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.247940516
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.2040249612
Short name T28
Test name
Test status
Simulation time 8373434055 ps
CPU time 7.56 seconds
Started Apr 18 01:16:55 PM PDT 24
Finished Apr 18 01:17:06 PM PDT 24
Peak memory 204000 kb
Host smart-1045ffd2-b393-400a-8940-abe52dd0228d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20402
49612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.2040249612
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.3165083545
Short name T128
Test name
Test status
Simulation time 8447049852 ps
CPU time 7.78 seconds
Started Apr 18 01:16:52 PM PDT 24
Finished Apr 18 01:17:01 PM PDT 24
Peak memory 204052 kb
Host smart-ad6f737f-b072-4b43-bdfc-543a5ecf3f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31650
83545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.3165083545
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.1058788814
Short name T929
Test name
Test status
Simulation time 8432053734 ps
CPU time 8.15 seconds
Started Apr 18 01:16:56 PM PDT 24
Finished Apr 18 01:17:08 PM PDT 24
Peak memory 203996 kb
Host smart-8fced5bc-f6e2-4692-80e8-e33d353133d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10587
88814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.1058788814
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.552580395
Short name T307
Test name
Test status
Simulation time 8490447242 ps
CPU time 7.8 seconds
Started Apr 18 01:16:55 PM PDT 24
Finished Apr 18 01:17:07 PM PDT 24
Peak memory 204076 kb
Host smart-098148ec-bbde-499a-a807-0e6bff047f22
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=552580395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.552580395
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.2015007397
Short name T715
Test name
Test status
Simulation time 8381568654 ps
CPU time 8.21 seconds
Started Apr 18 01:16:54 PM PDT 24
Finished Apr 18 01:17:04 PM PDT 24
Peak memory 203896 kb
Host smart-1723569e-3bcb-4668-879e-9d1d6e482c61
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2015007397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.2015007397
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.random_length_in_trans.2961697091
Short name T714
Test name
Test status
Simulation time 8401981758 ps
CPU time 8.12 seconds
Started Apr 18 01:16:56 PM PDT 24
Finished Apr 18 01:17:08 PM PDT 24
Peak memory 204036 kb
Host smart-e422740d-07cd-4cc3-8332-11aeb8743c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29616
97091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.2961697091
Directory /workspace/37.random_length_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.2640848350
Short name T1326
Test name
Test status
Simulation time 8375634900 ps
CPU time 7.77 seconds
Started Apr 18 01:16:56 PM PDT 24
Finished Apr 18 01:17:07 PM PDT 24
Peak memory 203960 kb
Host smart-adc3722f-47c9-46c7-96ca-b50d81062429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26408
48350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2640848350
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_enable.304950469
Short name T733
Test name
Test status
Simulation time 8416000187 ps
CPU time 8.3 seconds
Started Apr 18 01:16:55 PM PDT 24
Finished Apr 18 01:17:06 PM PDT 24
Peak memory 204048 kb
Host smart-4db7bad1-48d1-487b-8cf5-c0e99c6c1322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30495
0469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.304950469
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3551451513
Short name T359
Test name
Test status
Simulation time 56898549 ps
CPU time 1.13 seconds
Started Apr 18 01:16:54 PM PDT 24
Finished Apr 18 01:16:57 PM PDT 24
Peak memory 204100 kb
Host smart-7ad564e6-4906-46e7-8d9b-03e809d7be52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35514
51513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3551451513
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.1056727814
Short name T581
Test name
Test status
Simulation time 8423122962 ps
CPU time 11.13 seconds
Started Apr 18 01:16:54 PM PDT 24
Finished Apr 18 01:17:08 PM PDT 24
Peak memory 204036 kb
Host smart-4a647cb0-1f9c-43fd-a9a0-d5054f246df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10567
27814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.1056727814
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.2017025531
Short name T836
Test name
Test status
Simulation time 8373323101 ps
CPU time 8.02 seconds
Started Apr 18 01:16:55 PM PDT 24
Finished Apr 18 01:17:06 PM PDT 24
Peak memory 204004 kb
Host smart-3413381d-c804-468d-a94e-2f0572660e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20170
25531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.2017025531
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.423234604
Short name T823
Test name
Test status
Simulation time 8389937865 ps
CPU time 7.68 seconds
Started Apr 18 01:16:55 PM PDT 24
Finished Apr 18 01:17:06 PM PDT 24
Peak memory 204004 kb
Host smart-bbe73bec-a35c-4267-9eaa-c1ab517b8f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42323
4604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.423234604
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.2013176538
Short name T351
Test name
Test status
Simulation time 8412352810 ps
CPU time 9.25 seconds
Started Apr 18 01:17:01 PM PDT 24
Finished Apr 18 01:17:12 PM PDT 24
Peak memory 204044 kb
Host smart-aacc5550-71a2-4adb-8c06-3cf0530b4d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20131
76538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.2013176538
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.1966518653
Short name T1026
Test name
Test status
Simulation time 8374227281 ps
CPU time 8.32 seconds
Started Apr 18 01:17:00 PM PDT 24
Finished Apr 18 01:17:10 PM PDT 24
Peak memory 204044 kb
Host smart-ae8ef6de-be6e-4de1-a28b-391f2a97455b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19665
18653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.1966518653
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.1883051971
Short name T98
Test name
Test status
Simulation time 8430580447 ps
CPU time 10.42 seconds
Started Apr 18 01:16:57 PM PDT 24
Finished Apr 18 01:17:10 PM PDT 24
Peak memory 204084 kb
Host smart-9803303f-8f04-4242-91a5-433d60160158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18830
51971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.1883051971
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.225336788
Short name T634
Test name
Test status
Simulation time 8424191112 ps
CPU time 8.87 seconds
Started Apr 18 01:16:55 PM PDT 24
Finished Apr 18 01:17:07 PM PDT 24
Peak memory 204076 kb
Host smart-b854902f-849b-4123-900c-8ceda11e419c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22533
6788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.225336788
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.35592768
Short name T926
Test name
Test status
Simulation time 8381912256 ps
CPU time 8.41 seconds
Started Apr 18 01:16:53 PM PDT 24
Finished Apr 18 01:17:03 PM PDT 24
Peak memory 203864 kb
Host smart-a9abd4a0-96e8-4882-bcb9-54c5c7e63cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35592
768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.35592768
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.1895099262
Short name T156
Test name
Test status
Simulation time 8392940028 ps
CPU time 8.04 seconds
Started Apr 18 01:16:54 PM PDT 24
Finished Apr 18 01:17:04 PM PDT 24
Peak memory 204012 kb
Host smart-08f4b387-e290-44ef-89b1-1f0b39c7649a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18950
99262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.1895099262
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.788002714
Short name T643
Test name
Test status
Simulation time 8388630955 ps
CPU time 8.76 seconds
Started Apr 18 01:16:53 PM PDT 24
Finished Apr 18 01:17:03 PM PDT 24
Peak memory 204016 kb
Host smart-30e9a1e7-ad38-4210-b38b-e0099d708381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78800
2714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.788002714
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.123085966
Short name T36
Test name
Test status
Simulation time 40297502 ps
CPU time 0.65 seconds
Started Apr 18 01:16:55 PM PDT 24
Finished Apr 18 01:17:00 PM PDT 24
Peak memory 203844 kb
Host smart-6b50cfa2-07d0-4264-baec-c8b32b2896b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12308
5966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.123085966
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.2633697271
Short name T687
Test name
Test status
Simulation time 27108974089 ps
CPU time 53.26 seconds
Started Apr 18 01:16:55 PM PDT 24
Finished Apr 18 01:17:52 PM PDT 24
Peak memory 204292 kb
Host smart-949c8ee2-c9a0-4dc3-a32e-7cfa20136818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26336
97271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.2633697271
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3327090894
Short name T348
Test name
Test status
Simulation time 8387735674 ps
CPU time 7.97 seconds
Started Apr 18 01:16:57 PM PDT 24
Finished Apr 18 01:17:08 PM PDT 24
Peak memory 204048 kb
Host smart-387c3997-2001-485d-bbc4-b8769c3e9e0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33270
90894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3327090894
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.3927814494
Short name T39
Test name
Test status
Simulation time 8435815724 ps
CPU time 7.92 seconds
Started Apr 18 01:16:53 PM PDT 24
Finished Apr 18 01:17:03 PM PDT 24
Peak memory 204028 kb
Host smart-72985fed-dd83-4593-b8be-0233ffa25af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39278
14494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.3927814494
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.963916920
Short name T691
Test name
Test status
Simulation time 8397609781 ps
CPU time 8.3 seconds
Started Apr 18 01:16:54 PM PDT 24
Finished Apr 18 01:17:05 PM PDT 24
Peak memory 203976 kb
Host smart-13165d05-e2ef-4e40-a9bb-f87d704e64c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96391
6920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.963916920
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.2593594725
Short name T1157
Test name
Test status
Simulation time 8399881947 ps
CPU time 8.5 seconds
Started Apr 18 01:16:56 PM PDT 24
Finished Apr 18 01:17:08 PM PDT 24
Peak memory 203976 kb
Host smart-ce215514-ca92-4dce-98c8-4629029e74b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25935
94725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.2593594725
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.388722882
Short name T900
Test name
Test status
Simulation time 8388203730 ps
CPU time 8.22 seconds
Started Apr 18 01:17:00 PM PDT 24
Finished Apr 18 01:17:10 PM PDT 24
Peak memory 204040 kb
Host smart-ea3632e0-5a8b-46c4-aa8f-f7b1303e55cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38872
2882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.388722882
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.2760903863
Short name T946
Test name
Test status
Simulation time 8535511251 ps
CPU time 8.59 seconds
Started Apr 18 01:16:56 PM PDT 24
Finished Apr 18 01:17:08 PM PDT 24
Peak memory 204032 kb
Host smart-ba319a71-c7b1-4f9e-86ea-0991a39a0f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27609
03863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.2760903863
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.508733875
Short name T1151
Test name
Test status
Simulation time 8403589285 ps
CPU time 8.42 seconds
Started Apr 18 01:16:52 PM PDT 24
Finished Apr 18 01:17:02 PM PDT 24
Peak memory 204040 kb
Host smart-e147e84a-c899-45d1-8a22-7a16dbe5eef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50873
3875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.508733875
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.3201810215
Short name T1377
Test name
Test status
Simulation time 8434148489 ps
CPU time 7.97 seconds
Started Apr 18 01:16:54 PM PDT 24
Finished Apr 18 01:17:05 PM PDT 24
Peak memory 204040 kb
Host smart-2037ebd2-e097-4bfe-9897-2ae2a940862d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32018
10215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.3201810215
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.1295222568
Short name T423
Test name
Test status
Simulation time 8466140717 ps
CPU time 8.33 seconds
Started Apr 18 01:17:00 PM PDT 24
Finished Apr 18 01:17:11 PM PDT 24
Peak memory 204004 kb
Host smart-2ee16dc7-257c-40a6-bfcc-48a96733e4ba
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1295222568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.1295222568
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.928510790
Short name T439
Test name
Test status
Simulation time 8409436220 ps
CPU time 8.44 seconds
Started Apr 18 01:17:07 PM PDT 24
Finished Apr 18 01:17:17 PM PDT 24
Peak memory 203980 kb
Host smart-67ace5c9-86e4-48bd-9e11-d85b6e589ff0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=928510790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.928510790
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.3585813102
Short name T1118
Test name
Test status
Simulation time 8397165401 ps
CPU time 7.97 seconds
Started Apr 18 01:17:01 PM PDT 24
Finished Apr 18 01:17:11 PM PDT 24
Peak memory 204012 kb
Host smart-179356e7-e287-49fe-afdc-49dedb5b81b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35858
13102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.3585813102
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.1679276300
Short name T337
Test name
Test status
Simulation time 8378899034 ps
CPU time 8.97 seconds
Started Apr 18 01:17:01 PM PDT 24
Finished Apr 18 01:17:12 PM PDT 24
Peak memory 204044 kb
Host smart-60a4ad90-f57a-4b49-90c7-495934e6b34f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16792
76300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.1679276300
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_enable.1103719862
Short name T947
Test name
Test status
Simulation time 8387116994 ps
CPU time 8.47 seconds
Started Apr 18 01:16:57 PM PDT 24
Finished Apr 18 01:17:09 PM PDT 24
Peak memory 204004 kb
Host smart-02a1bbf1-202e-49f2-b7ee-6961ae6c38be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11037
19862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.1103719862
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.23953187
Short name T861
Test name
Test status
Simulation time 106120971 ps
CPU time 1.07 seconds
Started Apr 18 01:16:53 PM PDT 24
Finished Apr 18 01:16:56 PM PDT 24
Peak memory 203976 kb
Host smart-51f6d8d8-03b6-414c-9275-0ba28ff5bdae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23953
187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.23953187
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.840306159
Short name T903
Test name
Test status
Simulation time 8431689810 ps
CPU time 7.95 seconds
Started Apr 18 01:16:59 PM PDT 24
Finished Apr 18 01:17:09 PM PDT 24
Peak memory 204000 kb
Host smart-de9d8f4d-4641-4c99-bb2c-83fc2fe8465d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84030
6159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.840306159
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.441975831
Short name T1029
Test name
Test status
Simulation time 8375650874 ps
CPU time 7.58 seconds
Started Apr 18 01:17:03 PM PDT 24
Finished Apr 18 01:17:12 PM PDT 24
Peak memory 204024 kb
Host smart-f171b896-15df-46ff-9281-9042541597cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44197
5831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.441975831
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.1863420524
Short name T516
Test name
Test status
Simulation time 8412137898 ps
CPU time 8.46 seconds
Started Apr 18 01:16:57 PM PDT 24
Finished Apr 18 01:17:09 PM PDT 24
Peak memory 203984 kb
Host smart-e73dff75-10c5-4946-a65e-453fdece3ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18634
20524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.1863420524
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.32109273
Short name T909
Test name
Test status
Simulation time 8419647096 ps
CPU time 7.57 seconds
Started Apr 18 01:16:55 PM PDT 24
Finished Apr 18 01:17:05 PM PDT 24
Peak memory 204000 kb
Host smart-89be750e-7bf1-4f2b-8079-52c49ca5d491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32109
273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.32109273
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.466009912
Short name T998
Test name
Test status
Simulation time 8370020814 ps
CPU time 7.92 seconds
Started Apr 18 01:17:00 PM PDT 24
Finished Apr 18 01:17:11 PM PDT 24
Peak memory 204044 kb
Host smart-05e55f26-8402-4302-99a9-f27cc377576d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46600
9912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.466009912
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.1119096225
Short name T1257
Test name
Test status
Simulation time 8421740467 ps
CPU time 7.61 seconds
Started Apr 18 01:16:58 PM PDT 24
Finished Apr 18 01:17:08 PM PDT 24
Peak memory 204032 kb
Host smart-df7161aa-6fbe-4b9c-ba24-bf488d95313a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11190
96225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.1119096225
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.1412707086
Short name T827
Test name
Test status
Simulation time 8404982052 ps
CPU time 8.66 seconds
Started Apr 18 01:16:57 PM PDT 24
Finished Apr 18 01:17:09 PM PDT 24
Peak memory 204004 kb
Host smart-aa824ef0-6b93-454c-b4cd-7d8e177cb8fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14127
07086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.1412707086
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.101950497
Short name T281
Test name
Test status
Simulation time 8407935336 ps
CPU time 7.86 seconds
Started Apr 18 01:17:00 PM PDT 24
Finished Apr 18 01:17:11 PM PDT 24
Peak memory 204044 kb
Host smart-7c9a7dbd-0932-4b5a-bf95-9035dce98c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10195
0497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.101950497
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.363769674
Short name T820
Test name
Test status
Simulation time 8393990895 ps
CPU time 9.42 seconds
Started Apr 18 01:17:02 PM PDT 24
Finished Apr 18 01:17:13 PM PDT 24
Peak memory 204084 kb
Host smart-2d06ea23-b007-4a5b-b702-df4952b03689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36376
9674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.363769674
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.581442516
Short name T717
Test name
Test status
Simulation time 8423833787 ps
CPU time 8.83 seconds
Started Apr 18 01:17:03 PM PDT 24
Finished Apr 18 01:17:13 PM PDT 24
Peak memory 204040 kb
Host smart-7c524d87-91dc-491d-89c5-5343f9559c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58144
2516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.581442516
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.1391198590
Short name T1289
Test name
Test status
Simulation time 39809213 ps
CPU time 0.66 seconds
Started Apr 18 01:17:05 PM PDT 24
Finished Apr 18 01:17:07 PM PDT 24
Peak memory 203916 kb
Host smart-409d7a1e-58dc-42e2-9cae-371072a3f701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13911
98590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.1391198590
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.2798553599
Short name T1303
Test name
Test status
Simulation time 18907518128 ps
CPU time 33.87 seconds
Started Apr 18 01:16:55 PM PDT 24
Finished Apr 18 01:17:33 PM PDT 24
Peak memory 204248 kb
Host smart-a61ef5dc-d1f1-4108-96c2-f2d5c8b5727b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27985
53599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.2798553599
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.1145452348
Short name T1346
Test name
Test status
Simulation time 8396156745 ps
CPU time 8.12 seconds
Started Apr 18 01:16:59 PM PDT 24
Finished Apr 18 01:17:10 PM PDT 24
Peak memory 204028 kb
Host smart-4f59df2b-79ff-491d-91c5-5226ebf84dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11454
52348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.1145452348
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.3756157554
Short name T526
Test name
Test status
Simulation time 8398643020 ps
CPU time 8.14 seconds
Started Apr 18 01:17:02 PM PDT 24
Finished Apr 18 01:17:11 PM PDT 24
Peak memory 204016 kb
Host smart-c0c37f62-c803-4c77-a18d-8ea8aab9b069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37561
57554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.3756157554
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.3168988414
Short name T1283
Test name
Test status
Simulation time 8415245292 ps
CPU time 8.8 seconds
Started Apr 18 01:16:59 PM PDT 24
Finished Apr 18 01:17:10 PM PDT 24
Peak memory 204028 kb
Host smart-f7cf1f3d-4f56-4654-865f-90368445e4fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31689
88414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.3168988414
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.2647018923
Short name T1065
Test name
Test status
Simulation time 8377774153 ps
CPU time 7.51 seconds
Started Apr 18 01:17:03 PM PDT 24
Finished Apr 18 01:17:12 PM PDT 24
Peak memory 204044 kb
Host smart-dc488cd6-a2bd-4874-8298-caf343a9d821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26470
18923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.2647018923
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.887108982
Short name T845
Test name
Test status
Simulation time 8392759659 ps
CPU time 9.13 seconds
Started Apr 18 01:17:00 PM PDT 24
Finished Apr 18 01:17:12 PM PDT 24
Peak memory 204044 kb
Host smart-b8e2efbc-39e0-4008-a65b-05671a4dbc9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88710
8982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.887108982
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3275574811
Short name T1062
Test name
Test status
Simulation time 8523372999 ps
CPU time 8 seconds
Started Apr 18 01:16:56 PM PDT 24
Finished Apr 18 01:17:08 PM PDT 24
Peak memory 203996 kb
Host smart-7f1d983f-d97d-4232-be51-af65c65b4597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32755
74811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3275574811
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.1352652612
Short name T431
Test name
Test status
Simulation time 8412530073 ps
CPU time 9.21 seconds
Started Apr 18 01:17:02 PM PDT 24
Finished Apr 18 01:17:13 PM PDT 24
Peak memory 204020 kb
Host smart-394ca128-2763-4d16-84b3-73b754157efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13526
52612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.1352652612
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.199112870
Short name T364
Test name
Test status
Simulation time 8400755019 ps
CPU time 7.82 seconds
Started Apr 18 01:16:58 PM PDT 24
Finished Apr 18 01:17:08 PM PDT 24
Peak memory 204036 kb
Host smart-db341a11-909b-4921-a9a8-045c97a9a891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19911
2870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.199112870
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.2987129817
Short name T1010
Test name
Test status
Simulation time 8460365012 ps
CPU time 7.66 seconds
Started Apr 18 01:17:08 PM PDT 24
Finished Apr 18 01:17:16 PM PDT 24
Peak memory 204024 kb
Host smart-2d354968-f537-46b6-b56a-391822f293e8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2987129817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.2987129817
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.1353806081
Short name T1184
Test name
Test status
Simulation time 8397685787 ps
CPU time 7.89 seconds
Started Apr 18 01:17:05 PM PDT 24
Finished Apr 18 01:17:14 PM PDT 24
Peak memory 204044 kb
Host smart-6847b282-4ab9-4b7d-8c4a-1bda2856168e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1353806081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.1353806081
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.2323390038
Short name T1300
Test name
Test status
Simulation time 8453030962 ps
CPU time 8.82 seconds
Started Apr 18 01:17:07 PM PDT 24
Finished Apr 18 01:17:17 PM PDT 24
Peak memory 204080 kb
Host smart-fc580b89-badc-4665-944c-fa6348a0fa5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23233
90038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.2323390038
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.1313032614
Short name T325
Test name
Test status
Simulation time 8375349271 ps
CPU time 9.65 seconds
Started Apr 18 01:16:59 PM PDT 24
Finished Apr 18 01:17:11 PM PDT 24
Peak memory 204008 kb
Host smart-474476e4-ff2f-404b-a577-c049d30c484d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13130
32614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1313032614
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_enable.1514620120
Short name T211
Test name
Test status
Simulation time 8419615504 ps
CPU time 10.02 seconds
Started Apr 18 01:16:58 PM PDT 24
Finished Apr 18 01:17:11 PM PDT 24
Peak memory 203980 kb
Host smart-505c6ddb-888a-4f65-902e-066598c2ac4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15146
20120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.1514620120
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.4144172113
Short name T1197
Test name
Test status
Simulation time 96789652 ps
CPU time 1.24 seconds
Started Apr 18 01:17:01 PM PDT 24
Finished Apr 18 01:17:04 PM PDT 24
Peak memory 204084 kb
Host smart-0b364b2c-abaf-4ee1-929c-b8c0722f8010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41441
72113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.4144172113
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2598926665
Short name T123
Test name
Test status
Simulation time 8407134121 ps
CPU time 8.83 seconds
Started Apr 18 01:17:16 PM PDT 24
Finished Apr 18 01:17:26 PM PDT 24
Peak memory 203960 kb
Host smart-f9ae7fd4-4539-4abd-a1c1-15ac2a7c906e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25989
26665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2598926665
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.2829722205
Short name T183
Test name
Test status
Simulation time 8363562896 ps
CPU time 8.52 seconds
Started Apr 18 01:17:09 PM PDT 24
Finished Apr 18 01:17:18 PM PDT 24
Peak memory 203996 kb
Host smart-4f8ec71b-cf14-484c-8835-5b41cbbb1b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28297
22205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.2829722205
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.28837782
Short name T377
Test name
Test status
Simulation time 8450699708 ps
CPU time 8.29 seconds
Started Apr 18 01:16:59 PM PDT 24
Finished Apr 18 01:17:10 PM PDT 24
Peak memory 204044 kb
Host smart-ee3b0436-e121-4bef-8e14-921ff171535d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28837
782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.28837782
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.3043378449
Short name T1340
Test name
Test status
Simulation time 8414974554 ps
CPU time 8.16 seconds
Started Apr 18 01:16:59 PM PDT 24
Finished Apr 18 01:17:10 PM PDT 24
Peak memory 204032 kb
Host smart-f66a17f7-cb76-47ff-b3a8-ec9d907355b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30433
78449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.3043378449
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.4222044596
Short name T1273
Test name
Test status
Simulation time 8369458772 ps
CPU time 7.99 seconds
Started Apr 18 01:17:00 PM PDT 24
Finished Apr 18 01:17:10 PM PDT 24
Peak memory 204004 kb
Host smart-7066a92a-4636-4259-87b4-4b063cef749b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42220
44596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.4222044596
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.835520278
Short name T1196
Test name
Test status
Simulation time 8453885053 ps
CPU time 8.78 seconds
Started Apr 18 01:16:58 PM PDT 24
Finished Apr 18 01:17:09 PM PDT 24
Peak memory 203956 kb
Host smart-505498ee-faf1-4a4e-a9f2-49f3c3e0d34b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83552
0278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.835520278
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.414422705
Short name T482
Test name
Test status
Simulation time 8398480629 ps
CPU time 8.27 seconds
Started Apr 18 01:17:00 PM PDT 24
Finished Apr 18 01:17:10 PM PDT 24
Peak memory 203980 kb
Host smart-659885de-b921-4c2d-bfb5-10eb1625e2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41442
2705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.414422705
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.3366065890
Short name T449
Test name
Test status
Simulation time 8391557188 ps
CPU time 9.55 seconds
Started Apr 18 01:16:58 PM PDT 24
Finished Apr 18 01:17:10 PM PDT 24
Peak memory 203984 kb
Host smart-3bf269fc-7787-4bf6-80d8-347c0ec40012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33660
65890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.3366065890
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.503389494
Short name T570
Test name
Test status
Simulation time 8409493489 ps
CPU time 9.05 seconds
Started Apr 18 01:17:12 PM PDT 24
Finished Apr 18 01:17:21 PM PDT 24
Peak memory 204016 kb
Host smart-c44ffdd2-ea15-48ba-a86b-c022025cb929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50338
9494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.503389494
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.3775926950
Short name T867
Test name
Test status
Simulation time 8375632518 ps
CPU time 7.4 seconds
Started Apr 18 01:17:05 PM PDT 24
Finished Apr 18 01:17:14 PM PDT 24
Peak memory 203956 kb
Host smart-9aa64cb9-c6f4-4532-b96e-f9683280d221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37759
26950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.3775926950
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.329292058
Short name T736
Test name
Test status
Simulation time 81842191 ps
CPU time 0.7 seconds
Started Apr 18 01:17:07 PM PDT 24
Finished Apr 18 01:17:09 PM PDT 24
Peak memory 203896 kb
Host smart-85e603fb-dbd4-4a14-b033-4c39807d4a52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32929
2058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.329292058
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.2320501708
Short name T583
Test name
Test status
Simulation time 8402977232 ps
CPU time 7.72 seconds
Started Apr 18 01:17:08 PM PDT 24
Finished Apr 18 01:17:17 PM PDT 24
Peak memory 204028 kb
Host smart-aebe40f3-4032-4642-9dc0-a18810c66955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23205
01708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.2320501708
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2610089367
Short name T1173
Test name
Test status
Simulation time 8477648402 ps
CPU time 9.13 seconds
Started Apr 18 01:17:06 PM PDT 24
Finished Apr 18 01:17:17 PM PDT 24
Peak memory 204052 kb
Host smart-bf1855c3-6d15-4415-bc66-bc92045199a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26100
89367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2610089367
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.529461635
Short name T1339
Test name
Test status
Simulation time 8395796147 ps
CPU time 9.29 seconds
Started Apr 18 01:17:05 PM PDT 24
Finished Apr 18 01:17:15 PM PDT 24
Peak memory 204016 kb
Host smart-362b8515-6090-4f21-9485-52cce8a37311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52946
1635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.529461635
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.968486372
Short name T653
Test name
Test status
Simulation time 8385247469 ps
CPU time 8.86 seconds
Started Apr 18 01:17:06 PM PDT 24
Finished Apr 18 01:17:16 PM PDT 24
Peak memory 204024 kb
Host smart-84a9b1c1-9250-429d-96b1-ac70b3aa1260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96848
6372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.968486372
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.2197760371
Short name T487
Test name
Test status
Simulation time 8368870874 ps
CPU time 7.42 seconds
Started Apr 18 01:17:06 PM PDT 24
Finished Apr 18 01:17:14 PM PDT 24
Peak memory 203940 kb
Host smart-22caeb0c-75bb-4812-88b6-cac929b4b016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21977
60371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.2197760371
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.2884408839
Short name T546
Test name
Test status
Simulation time 8474027236 ps
CPU time 9.27 seconds
Started Apr 18 01:17:06 PM PDT 24
Finished Apr 18 01:17:17 PM PDT 24
Peak memory 204044 kb
Host smart-c4e30d88-4d32-417f-b404-bdc7c4ebb371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28844
08839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.2884408839
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.1339137893
Short name T826
Test name
Test status
Simulation time 8391803952 ps
CPU time 7.87 seconds
Started Apr 18 01:17:07 PM PDT 24
Finished Apr 18 01:17:16 PM PDT 24
Peak memory 203956 kb
Host smart-6dc5f97e-8894-41c6-85dc-a82394aaf32b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13391
37893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.1339137893
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.2555034022
Short name T552
Test name
Test status
Simulation time 8421367083 ps
CPU time 8.46 seconds
Started Apr 18 01:17:05 PM PDT 24
Finished Apr 18 01:17:14 PM PDT 24
Peak memory 204012 kb
Host smart-5a441a64-a71f-455f-9fb5-392bdcd0a9a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25550
34022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.2555034022
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.1863579915
Short name T1221
Test name
Test status
Simulation time 8462382362 ps
CPU time 9.66 seconds
Started Apr 18 01:14:07 PM PDT 24
Finished Apr 18 01:14:17 PM PDT 24
Peak memory 203960 kb
Host smart-5b88349d-c3c4-43a5-b3a3-6c943ca4daa5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1863579915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.1863579915
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.1278983504
Short name T555
Test name
Test status
Simulation time 8376675165 ps
CPU time 8.66 seconds
Started Apr 18 01:14:04 PM PDT 24
Finished Apr 18 01:14:13 PM PDT 24
Peak memory 204012 kb
Host smart-8e7d490a-77fe-4f68-96b7-5d1ca35bd054
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1278983504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.1278983504
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.1619699514
Short name T356
Test name
Test status
Simulation time 8424097695 ps
CPU time 10.17 seconds
Started Apr 18 01:14:05 PM PDT 24
Finished Apr 18 01:14:15 PM PDT 24
Peak memory 204012 kb
Host smart-875e965d-1ef8-4974-9404-5ffbe2fe284b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16196
99514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.1619699514
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.4245265459
Short name T1043
Test name
Test status
Simulation time 8375601744 ps
CPU time 7.94 seconds
Started Apr 18 01:13:54 PM PDT 24
Finished Apr 18 01:14:03 PM PDT 24
Peak memory 203996 kb
Host smart-870fcc4d-0c00-4e0b-aff0-9d98f44fcd56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42452
65459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.4245265459
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_enable.3809224696
Short name T1186
Test name
Test status
Simulation time 8380253151 ps
CPU time 8.57 seconds
Started Apr 18 01:13:54 PM PDT 24
Finished Apr 18 01:14:03 PM PDT 24
Peak memory 203920 kb
Host smart-5ab702a9-9835-4b10-a36a-a109b8f767a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38092
24696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.3809224696
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.1021682115
Short name T213
Test name
Test status
Simulation time 81714393 ps
CPU time 2 seconds
Started Apr 18 01:13:55 PM PDT 24
Finished Apr 18 01:13:58 PM PDT 24
Peak memory 204032 kb
Host smart-53762195-1297-483b-a95e-2afeaa30eb34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10216
82115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1021682115
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.1773432547
Short name T623
Test name
Test status
Simulation time 8404422733 ps
CPU time 9.36 seconds
Started Apr 18 01:14:09 PM PDT 24
Finished Apr 18 01:14:19 PM PDT 24
Peak memory 204044 kb
Host smart-308decbf-9397-4c3e-9171-7be8ee05688e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17734
32547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1773432547
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.3663761863
Short name T655
Test name
Test status
Simulation time 8368984129 ps
CPU time 8.27 seconds
Started Apr 18 01:14:09 PM PDT 24
Finished Apr 18 01:14:18 PM PDT 24
Peak memory 203700 kb
Host smart-8df6b75e-38d4-4119-aa75-063520edce85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36637
61863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.3663761863
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1076918680
Short name T809
Test name
Test status
Simulation time 8442046492 ps
CPU time 8.56 seconds
Started Apr 18 01:13:54 PM PDT 24
Finished Apr 18 01:14:04 PM PDT 24
Peak memory 204004 kb
Host smart-f8dcaaf2-4ce6-41d5-901a-e58eec16099a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10769
18680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1076918680
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.326164382
Short name T1296
Test name
Test status
Simulation time 8433748704 ps
CPU time 8.13 seconds
Started Apr 18 01:13:53 PM PDT 24
Finished Apr 18 01:14:02 PM PDT 24
Peak memory 203908 kb
Host smart-4586905f-0267-4401-a509-338d8fd817df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32616
4382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.326164382
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.918055994
Short name T368
Test name
Test status
Simulation time 8373577866 ps
CPU time 9.49 seconds
Started Apr 18 01:13:52 PM PDT 24
Finished Apr 18 01:14:02 PM PDT 24
Peak memory 203944 kb
Host smart-25132b4d-c6d5-48ae-9d2b-635413a8db24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91805
5994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.918055994
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2523664670
Short name T538
Test name
Test status
Simulation time 8419587466 ps
CPU time 8.48 seconds
Started Apr 18 01:14:02 PM PDT 24
Finished Apr 18 01:14:11 PM PDT 24
Peak memory 203908 kb
Host smart-6f41a41e-8462-4c1d-bdab-ba01c773d45a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25236
64670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2523664670
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.2363787560
Short name T464
Test name
Test status
Simulation time 8435156030 ps
CPU time 8.11 seconds
Started Apr 18 01:14:02 PM PDT 24
Finished Apr 18 01:14:10 PM PDT 24
Peak memory 204024 kb
Host smart-d8f81f5e-a233-4c9c-80a7-a553f6367f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23637
87560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.2363787560
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.3160920310
Short name T851
Test name
Test status
Simulation time 8380729751 ps
CPU time 8.06 seconds
Started Apr 18 01:14:05 PM PDT 24
Finished Apr 18 01:14:13 PM PDT 24
Peak memory 204044 kb
Host smart-6fd8740a-3f76-46f1-8fe6-c05ea9d47338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31609
20310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.3160920310
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.2991521832
Short name T578
Test name
Test status
Simulation time 8377233157 ps
CPU time 8.05 seconds
Started Apr 18 01:14:07 PM PDT 24
Finished Apr 18 01:14:15 PM PDT 24
Peak memory 204000 kb
Host smart-47edb582-722b-4951-a1f8-375df8300dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29915
21832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.2991521832
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3016993213
Short name T461
Test name
Test status
Simulation time 34884367 ps
CPU time 0.65 seconds
Started Apr 18 01:14:05 PM PDT 24
Finished Apr 18 01:14:06 PM PDT 24
Peak memory 203828 kb
Host smart-6e6bc9e8-6b11-4c82-aa1a-34c6613ef859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30169
93213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3016993213
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3290926353
Short name T220
Test name
Test status
Simulation time 28027517267 ps
CPU time 49.22 seconds
Started Apr 18 01:13:58 PM PDT 24
Finished Apr 18 01:14:48 PM PDT 24
Peak memory 204244 kb
Host smart-39093add-a540-4db1-b20a-1eb5e8aa9d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32909
26353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3290926353
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.3700604013
Short name T498
Test name
Test status
Simulation time 8419083593 ps
CPU time 8.14 seconds
Started Apr 18 01:13:59 PM PDT 24
Finished Apr 18 01:14:08 PM PDT 24
Peak memory 203996 kb
Host smart-54142a9c-822b-4881-b60b-b2886d30610b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37006
04013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3700604013
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2116527467
Short name T1243
Test name
Test status
Simulation time 8434575405 ps
CPU time 8.81 seconds
Started Apr 18 01:14:00 PM PDT 24
Finished Apr 18 01:14:09 PM PDT 24
Peak memory 204044 kb
Host smart-4e8cc962-4e30-4bf9-9e05-551395458c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21165
27467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2116527467
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.3196868112
Short name T863
Test name
Test status
Simulation time 8384318094 ps
CPU time 7.84 seconds
Started Apr 18 01:13:58 PM PDT 24
Finished Apr 18 01:14:06 PM PDT 24
Peak memory 203980 kb
Host smart-d367ce8b-f968-4bb6-ae44-c48859a74fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31968
68112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.3196868112
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.4215379554
Short name T58
Test name
Test status
Simulation time 252216827 ps
CPU time 1.23 seconds
Started Apr 18 01:14:03 PM PDT 24
Finished Apr 18 01:14:05 PM PDT 24
Peak memory 221124 kb
Host smart-78b17fec-d133-450e-a3ab-2cef0d1ab09c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4215379554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.4215379554
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.88460800
Short name T166
Test name
Test status
Simulation time 8375600728 ps
CPU time 8.24 seconds
Started Apr 18 01:14:06 PM PDT 24
Finished Apr 18 01:14:15 PM PDT 24
Peak memory 204004 kb
Host smart-f2d93c1c-4772-4444-bac7-11774d4f2877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88460
800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.88460800
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.2066763508
Short name T928
Test name
Test status
Simulation time 8364383663 ps
CPU time 7.89 seconds
Started Apr 18 01:14:04 PM PDT 24
Finished Apr 18 01:14:12 PM PDT 24
Peak memory 204040 kb
Host smart-ac0c8fa7-e4e4-4e7c-aed4-cfbd22610cf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20667
63508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.2066763508
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.465379156
Short name T1310
Test name
Test status
Simulation time 8418257815 ps
CPU time 8.95 seconds
Started Apr 18 01:13:53 PM PDT 24
Finished Apr 18 01:14:03 PM PDT 24
Peak memory 204040 kb
Host smart-dd2713ff-dcdb-4d3d-8f17-5da2ecc4c29d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46537
9156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.465379156
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.684191331
Short name T1330
Test name
Test status
Simulation time 8371046128 ps
CPU time 9.05 seconds
Started Apr 18 01:14:05 PM PDT 24
Finished Apr 18 01:14:15 PM PDT 24
Peak memory 203980 kb
Host smart-a2f4369d-2609-4906-b6b5-3bce276e264f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68419
1331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.684191331
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.1032287870
Short name T311
Test name
Test status
Simulation time 8383538096 ps
CPU time 8.83 seconds
Started Apr 18 01:13:59 PM PDT 24
Finished Apr 18 01:14:08 PM PDT 24
Peak memory 204064 kb
Host smart-00c0bf41-c6a2-418f-bafa-58a9007d400e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10322
87870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1032287870
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.245063647
Short name T1290
Test name
Test status
Simulation time 8461486695 ps
CPU time 8.4 seconds
Started Apr 18 01:17:07 PM PDT 24
Finished Apr 18 01:17:17 PM PDT 24
Peak memory 204016 kb
Host smart-1db54a7f-2b67-4827-91cd-f095114ea175
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=245063647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.245063647
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.2154585765
Short name T1381
Test name
Test status
Simulation time 8375929384 ps
CPU time 10.14 seconds
Started Apr 18 01:17:12 PM PDT 24
Finished Apr 18 01:17:23 PM PDT 24
Peak memory 204016 kb
Host smart-856f8c2a-3fc7-4468-9682-8a01093bd86a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2154585765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.2154585765
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.3834556281
Short name T18
Test name
Test status
Simulation time 8441005699 ps
CPU time 8.36 seconds
Started Apr 18 01:17:07 PM PDT 24
Finished Apr 18 01:17:17 PM PDT 24
Peak memory 204020 kb
Host smart-e573e926-d699-4c66-b259-17d4ee178370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38345
56281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.3834556281
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.3421444535
Short name T401
Test name
Test status
Simulation time 8405254326 ps
CPU time 7.87 seconds
Started Apr 18 01:17:05 PM PDT 24
Finished Apr 18 01:17:14 PM PDT 24
Peak memory 203960 kb
Host smart-738409ce-1ede-4412-9891-84a81894567c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34214
44535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.3421444535
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_enable.4283336052
Short name T1077
Test name
Test status
Simulation time 8379400796 ps
CPU time 8.27 seconds
Started Apr 18 01:17:06 PM PDT 24
Finished Apr 18 01:17:16 PM PDT 24
Peak memory 204012 kb
Host smart-763f4f86-de38-4750-a4ae-74f0b57a5bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42833
36052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.4283336052
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.3352739207
Short name T218
Test name
Test status
Simulation time 48933238 ps
CPU time 1 seconds
Started Apr 18 01:17:07 PM PDT 24
Finished Apr 18 01:17:09 PM PDT 24
Peak memory 203972 kb
Host smart-1b3aca20-d3db-42e3-8449-b70b91112a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33527
39207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.3352739207
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.1508211638
Short name T938
Test name
Test status
Simulation time 8411080152 ps
CPU time 8.89 seconds
Started Apr 18 01:17:06 PM PDT 24
Finished Apr 18 01:17:16 PM PDT 24
Peak memory 204024 kb
Host smart-d5986a92-8aa4-4a65-af52-9471ad0c9097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15082
11638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.1508211638
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.663529915
Short name T6
Test name
Test status
Simulation time 8371318286 ps
CPU time 7.72 seconds
Started Apr 18 01:17:09 PM PDT 24
Finished Apr 18 01:17:17 PM PDT 24
Peak memory 203996 kb
Host smart-0ff45d38-0eaa-46d4-be1d-762f2932761b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66352
9915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.663529915
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.3180652633
Short name T502
Test name
Test status
Simulation time 8399127227 ps
CPU time 8.66 seconds
Started Apr 18 01:17:06 PM PDT 24
Finished Apr 18 01:17:17 PM PDT 24
Peak memory 203904 kb
Host smart-044d5c86-ea29-461a-ab95-2bb4b5a02fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31806
52633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.3180652633
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.1460170274
Short name T1055
Test name
Test status
Simulation time 8411993270 ps
CPU time 9.83 seconds
Started Apr 18 01:17:06 PM PDT 24
Finished Apr 18 01:17:18 PM PDT 24
Peak memory 204068 kb
Host smart-0c75aee1-2dc5-4cf4-87a7-85e5df274ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14601
70274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1460170274
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3492987584
Short name T1042
Test name
Test status
Simulation time 8374994318 ps
CPU time 7.68 seconds
Started Apr 18 01:17:05 PM PDT 24
Finished Apr 18 01:17:14 PM PDT 24
Peak memory 203968 kb
Host smart-da18e76c-6cdf-4b6c-a12b-c20578dc2827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34929
87584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3492987584
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.3717243629
Short name T95
Test name
Test status
Simulation time 8435085500 ps
CPU time 7.91 seconds
Started Apr 18 01:17:11 PM PDT 24
Finished Apr 18 01:17:20 PM PDT 24
Peak memory 204020 kb
Host smart-0fc9eece-bfa8-41f4-8236-edeb460c60ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37172
43629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3717243629
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.1940349048
Short name T293
Test name
Test status
Simulation time 8391847977 ps
CPU time 10.45 seconds
Started Apr 18 01:17:12 PM PDT 24
Finished Apr 18 01:17:23 PM PDT 24
Peak memory 204020 kb
Host smart-7a225995-61dd-4373-8c69-1ce8ec18869b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19403
49048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.1940349048
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.131711038
Short name T839
Test name
Test status
Simulation time 8378790408 ps
CPU time 9.81 seconds
Started Apr 18 01:17:05 PM PDT 24
Finished Apr 18 01:17:16 PM PDT 24
Peak memory 204044 kb
Host smart-69e5af4c-0187-49e9-90a5-f912fdd950ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13171
1038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.131711038
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.949728421
Short name T187
Test name
Test status
Simulation time 8407630370 ps
CPU time 8.5 seconds
Started Apr 18 01:17:05 PM PDT 24
Finished Apr 18 01:17:14 PM PDT 24
Peak memory 204044 kb
Host smart-c06eca25-b4e3-499e-9d8e-4ff3b9f49dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94972
8421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.949728421
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.2672948690
Short name T974
Test name
Test status
Simulation time 8369684495 ps
CPU time 7.59 seconds
Started Apr 18 01:17:12 PM PDT 24
Finished Apr 18 01:17:20 PM PDT 24
Peak memory 204020 kb
Host smart-7c7e1d5e-4395-459b-b126-a73154137ccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26729
48690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.2672948690
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.210772032
Short name T35
Test name
Test status
Simulation time 31869244 ps
CPU time 0.64 seconds
Started Apr 18 01:17:06 PM PDT 24
Finished Apr 18 01:17:08 PM PDT 24
Peak memory 203840 kb
Host smart-4b853acb-6652-4717-ba00-ed609f6ad484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21077
2032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.210772032
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.4031828764
Short name T14
Test name
Test status
Simulation time 28438951512 ps
CPU time 59.48 seconds
Started Apr 18 01:17:07 PM PDT 24
Finished Apr 18 01:18:08 PM PDT 24
Peak memory 204328 kb
Host smart-963ac862-024a-410f-98d6-7b15c942ab28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40318
28764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.4031828764
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.655456317
Short name T842
Test name
Test status
Simulation time 8462160570 ps
CPU time 7.91 seconds
Started Apr 18 01:17:05 PM PDT 24
Finished Apr 18 01:17:13 PM PDT 24
Peak memory 204016 kb
Host smart-e9caf0e2-1dbb-4aad-9aae-c4127841f670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65545
6317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.655456317
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.3476236403
Short name T878
Test name
Test status
Simulation time 8448050741 ps
CPU time 10.07 seconds
Started Apr 18 01:17:07 PM PDT 24
Finished Apr 18 01:17:18 PM PDT 24
Peak memory 204044 kb
Host smart-aa78d5a0-0ca1-4656-bdd7-8bd9424f7036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34762
36403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.3476236403
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.1719782122
Short name T478
Test name
Test status
Simulation time 8401348089 ps
CPU time 8.49 seconds
Started Apr 18 01:17:06 PM PDT 24
Finished Apr 18 01:17:15 PM PDT 24
Peak memory 203860 kb
Host smart-a8d2c828-9052-40cc-b139-89e9efb701b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17197
82122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.1719782122
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.2279603814
Short name T601
Test name
Test status
Simulation time 8372356589 ps
CPU time 9.71 seconds
Started Apr 18 01:17:07 PM PDT 24
Finished Apr 18 01:17:18 PM PDT 24
Peak memory 203960 kb
Host smart-67ca5ffb-87f2-4342-8fc7-0e81331be0cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22796
03814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.2279603814
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.3226873319
Short name T1319
Test name
Test status
Simulation time 8365833913 ps
CPU time 8.25 seconds
Started Apr 18 01:17:07 PM PDT 24
Finished Apr 18 01:17:17 PM PDT 24
Peak memory 203960 kb
Host smart-1c703a0d-e83e-4bcb-9908-4aa996dec088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32268
73319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.3226873319
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.4073464967
Short name T130
Test name
Test status
Simulation time 8414360571 ps
CPU time 10.15 seconds
Started Apr 18 01:17:08 PM PDT 24
Finished Apr 18 01:17:19 PM PDT 24
Peak memory 203912 kb
Host smart-54cf58a1-14b8-42ed-941f-05e7bf81c232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40734
64967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.4073464967
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.1745372285
Short name T605
Test name
Test status
Simulation time 8387212848 ps
CPU time 8.76 seconds
Started Apr 18 01:17:06 PM PDT 24
Finished Apr 18 01:17:16 PM PDT 24
Peak memory 204008 kb
Host smart-93962896-51a8-4b7d-b3a3-72da90b55403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17453
72285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.1745372285
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.4275712435
Short name T420
Test name
Test status
Simulation time 8380565709 ps
CPU time 7.82 seconds
Started Apr 18 01:17:06 PM PDT 24
Finished Apr 18 01:17:15 PM PDT 24
Peak memory 203904 kb
Host smart-b9aba49c-4c2f-4418-99f7-be2dc4d6dfea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42757
12435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.4275712435
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.272617907
Short name T1374
Test name
Test status
Simulation time 8468176327 ps
CPU time 9.66 seconds
Started Apr 18 01:17:17 PM PDT 24
Finished Apr 18 01:17:28 PM PDT 24
Peak memory 203968 kb
Host smart-796a3bc5-2361-4c35-95ea-c809b89bd067
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=272617907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.272617907
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.2442929805
Short name T675
Test name
Test status
Simulation time 8382348816 ps
CPU time 7.53 seconds
Started Apr 18 01:17:16 PM PDT 24
Finished Apr 18 01:17:24 PM PDT 24
Peak memory 204044 kb
Host smart-69032471-6161-4234-aae6-d9cd7af68d00
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2442929805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.2442929805
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.random_length_in_trans.3746042182
Short name T626
Test name
Test status
Simulation time 8428377658 ps
CPU time 9.74 seconds
Started Apr 18 01:17:17 PM PDT 24
Finished Apr 18 01:17:28 PM PDT 24
Peak memory 203928 kb
Host smart-40d88de8-96a9-4f07-90cb-645b14dfb1dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37460
42182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.3746042182
Directory /workspace/41.random_length_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2200426304
Short name T589
Test name
Test status
Simulation time 8388136504 ps
CPU time 8.25 seconds
Started Apr 18 01:17:11 PM PDT 24
Finished Apr 18 01:17:20 PM PDT 24
Peak memory 204008 kb
Host smart-fff8c0ed-5fd7-45ec-b5d3-341149d2b0b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22004
26304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2200426304
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_enable.1344627258
Short name T1079
Test name
Test status
Simulation time 8372915810 ps
CPU time 8.4 seconds
Started Apr 18 01:17:13 PM PDT 24
Finished Apr 18 01:17:22 PM PDT 24
Peak memory 204044 kb
Host smart-491c8b10-fa3a-4eec-93a0-b49f6cbc11d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13446
27258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.1344627258
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.1465296622
Short name T1038
Test name
Test status
Simulation time 158344688 ps
CPU time 1.84 seconds
Started Apr 18 01:17:11 PM PDT 24
Finished Apr 18 01:17:13 PM PDT 24
Peak memory 204112 kb
Host smart-1b5ab697-bb35-4c76-8cb9-b2f9c8a79338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14652
96622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.1465296622
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.1353184835
Short name T517
Test name
Test status
Simulation time 8481473551 ps
CPU time 8.24 seconds
Started Apr 18 01:17:27 PM PDT 24
Finished Apr 18 01:17:36 PM PDT 24
Peak memory 203868 kb
Host smart-dc9e2dce-64d1-4a07-9d05-c016b8a324e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13531
84835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.1353184835
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1269480130
Short name T1225
Test name
Test status
Simulation time 8376705728 ps
CPU time 9.3 seconds
Started Apr 18 01:17:26 PM PDT 24
Finished Apr 18 01:17:36 PM PDT 24
Peak memory 204048 kb
Host smart-fed3305c-c768-4148-a5f3-46e29f1c3f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12694
80130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1269480130
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.1808038963
Short name T704
Test name
Test status
Simulation time 8485720752 ps
CPU time 9.44 seconds
Started Apr 18 01:17:10 PM PDT 24
Finished Apr 18 01:17:21 PM PDT 24
Peak memory 203940 kb
Host smart-2df3d185-9acf-4c5b-83a3-3aad6b21db2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18080
38963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.1808038963
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.3292180300
Short name T1166
Test name
Test status
Simulation time 8429130149 ps
CPU time 8.35 seconds
Started Apr 18 01:17:10 PM PDT 24
Finished Apr 18 01:17:19 PM PDT 24
Peak memory 204016 kb
Host smart-af33efe4-cfd5-4091-8188-cfea5bd970f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32921
80300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.3292180300
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.1821982358
Short name T1193
Test name
Test status
Simulation time 8447642644 ps
CPU time 7.72 seconds
Started Apr 18 01:17:14 PM PDT 24
Finished Apr 18 01:17:22 PM PDT 24
Peak memory 204028 kb
Host smart-b255d995-b017-4067-a16d-349be113d423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18219
82358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.1821982358
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.3366825179
Short name T118
Test name
Test status
Simulation time 8481434168 ps
CPU time 8.38 seconds
Started Apr 18 01:17:23 PM PDT 24
Finished Apr 18 01:17:32 PM PDT 24
Peak memory 203964 kb
Host smart-67ed6a12-9c74-4017-8023-842939cee3d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33668
25179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3366825179
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.493636286
Short name T1367
Test name
Test status
Simulation time 8403495991 ps
CPU time 9.98 seconds
Started Apr 18 01:17:12 PM PDT 24
Finished Apr 18 01:17:23 PM PDT 24
Peak memory 203952 kb
Host smart-4a33d8d2-277f-4e17-8fca-09de4110239f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49363
6286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.493636286
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.514755830
Short name T3
Test name
Test status
Simulation time 8376288900 ps
CPU time 8.58 seconds
Started Apr 18 01:17:13 PM PDT 24
Finished Apr 18 01:17:22 PM PDT 24
Peak memory 204000 kb
Host smart-b446f41c-fe01-40b3-9adc-f616ac1cc40a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51475
5830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.514755830
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.2887242241
Short name T49
Test name
Test status
Simulation time 8376882738 ps
CPU time 9.98 seconds
Started Apr 18 01:17:11 PM PDT 24
Finished Apr 18 01:17:21 PM PDT 24
Peak memory 203968 kb
Host smart-388eb542-0e0d-4fe2-b16c-bf0dce05a07d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28872
42241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.2887242241
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.1525359764
Short name T905
Test name
Test status
Simulation time 8441260428 ps
CPU time 7.93 seconds
Started Apr 18 01:17:09 PM PDT 24
Finished Apr 18 01:17:18 PM PDT 24
Peak memory 203920 kb
Host smart-fa7e5d3a-2661-4966-a3c7-cb21c7b8f191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15253
59764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.1525359764
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.3458608817
Short name T1057
Test name
Test status
Simulation time 13949674429 ps
CPU time 23.07 seconds
Started Apr 18 01:17:09 PM PDT 24
Finished Apr 18 01:17:33 PM PDT 24
Peak memory 204288 kb
Host smart-921b3564-804a-43b0-beb6-a29a31b86736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34586
08817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3458608817
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.2733281205
Short name T410
Test name
Test status
Simulation time 8388956883 ps
CPU time 8.21 seconds
Started Apr 18 01:17:10 PM PDT 24
Finished Apr 18 01:17:19 PM PDT 24
Peak memory 204044 kb
Host smart-413775f1-8099-4d0c-a77f-e16c59ed388a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27332
81205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.2733281205
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.857887312
Short name T127
Test name
Test status
Simulation time 8405282374 ps
CPU time 8.06 seconds
Started Apr 18 01:17:13 PM PDT 24
Finished Apr 18 01:17:21 PM PDT 24
Peak memory 204016 kb
Host smart-100163a3-72f1-445e-a861-4486eb84a996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85788
7312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.857887312
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.3332570013
Short name T1110
Test name
Test status
Simulation time 8401282638 ps
CPU time 8.61 seconds
Started Apr 18 01:17:13 PM PDT 24
Finished Apr 18 01:17:22 PM PDT 24
Peak memory 204028 kb
Host smart-4d39ac07-c27f-4b3e-968d-d7f238d974f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33325
70013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.3332570013
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.2754678753
Short name T1012
Test name
Test status
Simulation time 8372448958 ps
CPU time 7.69 seconds
Started Apr 18 01:17:09 PM PDT 24
Finished Apr 18 01:17:18 PM PDT 24
Peak memory 203904 kb
Host smart-3fc78b1f-4c67-464c-ae27-63c37f12475a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27546
78753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.2754678753
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.1870722424
Short name T586
Test name
Test status
Simulation time 8449331105 ps
CPU time 7.7 seconds
Started Apr 18 01:17:12 PM PDT 24
Finished Apr 18 01:17:20 PM PDT 24
Peak memory 203980 kb
Host smart-11853bb3-027e-4965-871b-094fa0abe2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18707
22424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.1870722424
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.2807225824
Short name T1253
Test name
Test status
Simulation time 8490836999 ps
CPU time 9.16 seconds
Started Apr 18 01:17:11 PM PDT 24
Finished Apr 18 01:17:21 PM PDT 24
Peak memory 204060 kb
Host smart-1a33bdc4-69ea-4ffe-b539-0b7a6abc22b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28072
25824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.2807225824
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.1624623805
Short name T365
Test name
Test status
Simulation time 8379415460 ps
CPU time 8.2 seconds
Started Apr 18 01:17:11 PM PDT 24
Finished Apr 18 01:17:20 PM PDT 24
Peak memory 204040 kb
Host smart-22e747c2-1173-40ca-891b-cb5d66213dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16246
23805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.1624623805
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.2420214545
Short name T1130
Test name
Test status
Simulation time 8443991831 ps
CPU time 8.9 seconds
Started Apr 18 01:17:13 PM PDT 24
Finished Apr 18 01:17:22 PM PDT 24
Peak memory 203992 kb
Host smart-11df57e4-4a35-49b5-98b7-6e80d424fc29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24202
14545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.2420214545
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.1911516129
Short name T891
Test name
Test status
Simulation time 8464198465 ps
CPU time 8.07 seconds
Started Apr 18 01:17:17 PM PDT 24
Finished Apr 18 01:17:26 PM PDT 24
Peak memory 203960 kb
Host smart-61ab3ca1-ce86-4417-949a-b702bdf288f5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1911516129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.1911516129
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.3713073092
Short name T427
Test name
Test status
Simulation time 8409260534 ps
CPU time 10.41 seconds
Started Apr 18 01:17:18 PM PDT 24
Finished Apr 18 01:17:29 PM PDT 24
Peak memory 204008 kb
Host smart-2ec104ac-5062-45ac-98d7-712fea6d9956
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3713073092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.3713073092
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.3555259511
Short name T853
Test name
Test status
Simulation time 8417218632 ps
CPU time 9.51 seconds
Started Apr 18 01:17:16 PM PDT 24
Finished Apr 18 01:17:27 PM PDT 24
Peak memory 204252 kb
Host smart-1959af27-6937-4bdb-a77a-7e217edb1c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35552
59511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.3555259511
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.839816693
Short name T613
Test name
Test status
Simulation time 8382138877 ps
CPU time 8.64 seconds
Started Apr 18 01:17:18 PM PDT 24
Finished Apr 18 01:17:28 PM PDT 24
Peak memory 204020 kb
Host smart-6e57dad1-41cb-4733-9232-069795b8b7e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83981
6693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.839816693
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_enable.3662210549
Short name T1268
Test name
Test status
Simulation time 8386013258 ps
CPU time 7.63 seconds
Started Apr 18 01:17:17 PM PDT 24
Finished Apr 18 01:17:25 PM PDT 24
Peak memory 203960 kb
Host smart-e6c85135-b8e3-49ce-8090-f5b8191f15c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36622
10549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.3662210549
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.1562871339
Short name T727
Test name
Test status
Simulation time 184950026 ps
CPU time 2.03 seconds
Started Apr 18 01:17:23 PM PDT 24
Finished Apr 18 01:17:25 PM PDT 24
Peak memory 204084 kb
Host smart-a50c139d-08d7-4ad6-ad4d-92dec951791a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15628
71339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.1562871339
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.3320630875
Short name T726
Test name
Test status
Simulation time 8406791334 ps
CPU time 8.09 seconds
Started Apr 18 01:17:18 PM PDT 24
Finished Apr 18 01:17:26 PM PDT 24
Peak memory 204040 kb
Host smart-c230cab8-cdc4-484a-aa93-0a9e95124e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33206
30875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.3320630875
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.2159295427
Short name T980
Test name
Test status
Simulation time 8362921904 ps
CPU time 8.82 seconds
Started Apr 18 01:17:18 PM PDT 24
Finished Apr 18 01:17:27 PM PDT 24
Peak memory 204016 kb
Host smart-ca7e2cb9-878b-445a-8994-91a8715d8d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21592
95427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.2159295427
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.3691199753
Short name T459
Test name
Test status
Simulation time 8470749950 ps
CPU time 9.58 seconds
Started Apr 18 01:17:20 PM PDT 24
Finished Apr 18 01:17:30 PM PDT 24
Peak memory 204052 kb
Host smart-dfed3936-0205-4033-aebb-2eb653dca8b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36911
99753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.3691199753
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.3506997470
Short name T490
Test name
Test status
Simulation time 8419296315 ps
CPU time 9.54 seconds
Started Apr 18 01:17:17 PM PDT 24
Finished Apr 18 01:17:27 PM PDT 24
Peak memory 203984 kb
Host smart-18b4cd91-c184-4ef4-87d2-c78a86f45ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35069
97470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.3506997470
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.4117806412
Short name T1356
Test name
Test status
Simulation time 8371800775 ps
CPU time 7.75 seconds
Started Apr 18 01:17:18 PM PDT 24
Finished Apr 18 01:17:26 PM PDT 24
Peak memory 203980 kb
Host smart-2f909590-b4a0-4581-b6d5-b57196d876ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41178
06412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.4117806412
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.1932443885
Short name T1141
Test name
Test status
Simulation time 8389481962 ps
CPU time 7.61 seconds
Started Apr 18 01:17:17 PM PDT 24
Finished Apr 18 01:17:26 PM PDT 24
Peak memory 203964 kb
Host smart-4cb19a22-7520-4374-a31e-d69d6ec2070a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19324
43885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.1932443885
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.58540753
Short name T963
Test name
Test status
Simulation time 8414021188 ps
CPU time 7.92 seconds
Started Apr 18 01:17:23 PM PDT 24
Finished Apr 18 01:17:31 PM PDT 24
Peak memory 203956 kb
Host smart-2a702784-549b-47a8-aea1-9561a7ff3c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58540
753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.58540753
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.3647280334
Short name T1091
Test name
Test status
Simulation time 8411035849 ps
CPU time 9.62 seconds
Started Apr 18 01:17:17 PM PDT 24
Finished Apr 18 01:17:27 PM PDT 24
Peak memory 203932 kb
Host smart-8cafc08f-dc48-4157-9fbf-d5543d3e4093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36472
80334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.3647280334
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.442306907
Short name T1336
Test name
Test status
Simulation time 8391952628 ps
CPU time 9.02 seconds
Started Apr 18 01:17:17 PM PDT 24
Finished Apr 18 01:17:27 PM PDT 24
Peak memory 204040 kb
Host smart-ede6e821-93f0-4194-ab7e-43f5a96349e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44230
6907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.442306907
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.1762526322
Short name T731
Test name
Test status
Simulation time 8374005482 ps
CPU time 8.21 seconds
Started Apr 18 01:17:18 PM PDT 24
Finished Apr 18 01:17:27 PM PDT 24
Peak memory 203944 kb
Host smart-8951baff-09d7-4a8a-bdec-65b0ceedeeb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17625
26322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.1762526322
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.3248836106
Short name T614
Test name
Test status
Simulation time 47468308 ps
CPU time 0.67 seconds
Started Apr 18 01:17:18 PM PDT 24
Finished Apr 18 01:17:19 PM PDT 24
Peak memory 203860 kb
Host smart-22fd7db8-7d83-40d2-966c-b90a3c3f5d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32488
36106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.3248836106
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.1944880329
Short name T937
Test name
Test status
Simulation time 21175866229 ps
CPU time 38.86 seconds
Started Apr 18 01:17:24 PM PDT 24
Finished Apr 18 01:18:04 PM PDT 24
Peak memory 204312 kb
Host smart-db0c083c-cc9f-44e8-9bb4-53048ebd5c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19448
80329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.1944880329
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.93662331
Short name T939
Test name
Test status
Simulation time 8385363005 ps
CPU time 7.66 seconds
Started Apr 18 01:17:17 PM PDT 24
Finished Apr 18 01:17:25 PM PDT 24
Peak memory 204008 kb
Host smart-c981482e-f78a-4f6f-b3b5-b57f18b08345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93662
331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.93662331
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.3741520624
Short name T122
Test name
Test status
Simulation time 8431899114 ps
CPU time 7.84 seconds
Started Apr 18 01:17:16 PM PDT 24
Finished Apr 18 01:17:25 PM PDT 24
Peak memory 203940 kb
Host smart-38c21896-dbae-42fe-8ee5-f29b707fb703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37415
20624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.3741520624
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.2463247441
Short name T565
Test name
Test status
Simulation time 8394949495 ps
CPU time 8.21 seconds
Started Apr 18 01:17:18 PM PDT 24
Finished Apr 18 01:17:27 PM PDT 24
Peak memory 204040 kb
Host smart-7990dae8-d053-49d6-b583-0072a7bd2769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24632
47441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.2463247441
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.3847657749
Short name T151
Test name
Test status
Simulation time 8377190590 ps
CPU time 8.05 seconds
Started Apr 18 01:17:16 PM PDT 24
Finished Apr 18 01:17:24 PM PDT 24
Peak memory 204028 kb
Host smart-d9a641ef-d913-4aee-ae14-596e8d08b9d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38476
57749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.3847657749
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2894211697
Short name T1343
Test name
Test status
Simulation time 8365456626 ps
CPU time 8.43 seconds
Started Apr 18 01:17:17 PM PDT 24
Finished Apr 18 01:17:26 PM PDT 24
Peak memory 204016 kb
Host smart-29b1b779-a892-4bc1-b439-c5faba16d294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28942
11697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2894211697
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2996446578
Short name T686
Test name
Test status
Simulation time 8517068511 ps
CPU time 9.11 seconds
Started Apr 18 01:17:20 PM PDT 24
Finished Apr 18 01:17:29 PM PDT 24
Peak memory 203912 kb
Host smart-fa39951e-2809-4a69-890b-cdc363018b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29964
46578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2996446578
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.1148081075
Short name T855
Test name
Test status
Simulation time 8396567757 ps
CPU time 9.02 seconds
Started Apr 18 01:17:20 PM PDT 24
Finished Apr 18 01:17:29 PM PDT 24
Peak memory 204040 kb
Host smart-f54d1fac-610f-4212-b83c-d03c5dc0294b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11480
81075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.1148081075
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.3013194163
Short name T309
Test name
Test status
Simulation time 8402085315 ps
CPU time 8.29 seconds
Started Apr 18 01:17:18 PM PDT 24
Finished Apr 18 01:17:27 PM PDT 24
Peak memory 204016 kb
Host smart-1fc3b91f-c975-4abd-baed-37cb832f9d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30131
94163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.3013194163
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.1084086501
Short name T688
Test name
Test status
Simulation time 8470370605 ps
CPU time 9 seconds
Started Apr 18 01:17:23 PM PDT 24
Finished Apr 18 01:17:33 PM PDT 24
Peak memory 203964 kb
Host smart-da0ea7aa-7acb-48d8-a96d-2dde71425425
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1084086501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.1084086501
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.3137473302
Short name T367
Test name
Test status
Simulation time 8378643651 ps
CPU time 9.49 seconds
Started Apr 18 01:17:26 PM PDT 24
Finished Apr 18 01:17:36 PM PDT 24
Peak memory 204052 kb
Host smart-7d8a82c8-e7e1-4cb8-868f-54d1c0df4034
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3137473302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.3137473302
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.1009669989
Short name T1314
Test name
Test status
Simulation time 8458607527 ps
CPU time 8.96 seconds
Started Apr 18 01:17:25 PM PDT 24
Finished Apr 18 01:17:34 PM PDT 24
Peak memory 203816 kb
Host smart-bd58c027-6c18-48ea-b8bf-7b22d16406dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10096
69989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.1009669989
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.1223510050
Short name T562
Test name
Test status
Simulation time 8372921421 ps
CPU time 8.38 seconds
Started Apr 18 01:17:26 PM PDT 24
Finished Apr 18 01:17:34 PM PDT 24
Peak memory 203996 kb
Host smart-ad42fbb4-f3b7-473f-bafa-b7baff8520df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12235
10050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1223510050
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_enable.2230141640
Short name T392
Test name
Test status
Simulation time 8439047784 ps
CPU time 9.3 seconds
Started Apr 18 01:17:24 PM PDT 24
Finished Apr 18 01:17:34 PM PDT 24
Peak memory 204044 kb
Host smart-ba919ad8-f54b-48d3-baa2-7b4bcf17dce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22301
41640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.2230141640
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.2735741086
Short name T629
Test name
Test status
Simulation time 80244397 ps
CPU time 1.24 seconds
Started Apr 18 01:17:24 PM PDT 24
Finished Apr 18 01:17:25 PM PDT 24
Peak memory 204120 kb
Host smart-4bb5665f-fe0e-4959-a62d-40796c3c73e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27357
41086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.2735741086
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.284700375
Short name T458
Test name
Test status
Simulation time 8419574508 ps
CPU time 9.02 seconds
Started Apr 18 01:17:31 PM PDT 24
Finished Apr 18 01:17:40 PM PDT 24
Peak memory 204028 kb
Host smart-2dea85d7-27f2-4ddb-9177-adeae484f826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28470
0375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.284700375
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.472614466
Short name T1198
Test name
Test status
Simulation time 8363490333 ps
CPU time 8.01 seconds
Started Apr 18 01:17:27 PM PDT 24
Finished Apr 18 01:17:36 PM PDT 24
Peak memory 204012 kb
Host smart-a30b3834-c351-49aa-aa34-b8f60f195525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47261
4466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.472614466
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1176450670
Short name T1081
Test name
Test status
Simulation time 8427578384 ps
CPU time 8.46 seconds
Started Apr 18 01:17:24 PM PDT 24
Finished Apr 18 01:17:34 PM PDT 24
Peak memory 203856 kb
Host smart-81541f0d-53a2-4668-b3c3-4d90e596d94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11764
50670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1176450670
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.3302464746
Short name T749
Test name
Test status
Simulation time 8467724451 ps
CPU time 8.29 seconds
Started Apr 18 01:17:28 PM PDT 24
Finished Apr 18 01:17:37 PM PDT 24
Peak memory 204016 kb
Host smart-976afd6d-fd03-4926-9cef-4a20dae14848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33024
64746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.3302464746
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.1480998786
Short name T384
Test name
Test status
Simulation time 8368946716 ps
CPU time 8.76 seconds
Started Apr 18 01:17:30 PM PDT 24
Finished Apr 18 01:17:39 PM PDT 24
Peak memory 204028 kb
Host smart-efd37b70-427a-42f7-b692-dd6d1048c256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14809
98786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1480998786
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.157641687
Short name T1335
Test name
Test status
Simulation time 8408809209 ps
CPU time 9.59 seconds
Started Apr 18 01:17:25 PM PDT 24
Finished Apr 18 01:17:35 PM PDT 24
Peak memory 204052 kb
Host smart-7007d2ab-cd5f-451e-89aa-75342a468834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15764
1687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.157641687
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.2103147369
Short name T1292
Test name
Test status
Simulation time 8376400738 ps
CPU time 7.91 seconds
Started Apr 18 01:17:23 PM PDT 24
Finished Apr 18 01:17:32 PM PDT 24
Peak memory 203916 kb
Host smart-00dd30df-5e25-4722-84a3-ae4c62f1491c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21031
47369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.2103147369
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3953132115
Short name T1357
Test name
Test status
Simulation time 8415995988 ps
CPU time 7.72 seconds
Started Apr 18 01:17:21 PM PDT 24
Finished Apr 18 01:17:29 PM PDT 24
Peak memory 204044 kb
Host smart-1beba5f0-9229-4004-8c26-c1a1ddf436b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39531
32115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3953132115
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.1350811848
Short name T744
Test name
Test status
Simulation time 8399603758 ps
CPU time 8.06 seconds
Started Apr 18 01:17:23 PM PDT 24
Finished Apr 18 01:17:32 PM PDT 24
Peak memory 203992 kb
Host smart-4822af6d-9c50-4bf3-9713-df2cf0482277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13508
11848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.1350811848
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.639012134
Short name T473
Test name
Test status
Simulation time 8375741381 ps
CPU time 7.94 seconds
Started Apr 18 01:17:26 PM PDT 24
Finished Apr 18 01:17:34 PM PDT 24
Peak memory 203992 kb
Host smart-b0b259fd-1042-4c8c-828d-2514f073a875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63901
2134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.639012134
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.835644189
Short name T543
Test name
Test status
Simulation time 93273937 ps
CPU time 0.73 seconds
Started Apr 18 01:17:24 PM PDT 24
Finished Apr 18 01:17:25 PM PDT 24
Peak memory 203872 kb
Host smart-2658586a-10a2-4a43-9568-c9a84552396d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83564
4189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.835644189
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.562051636
Short name T1154
Test name
Test status
Simulation time 21048783137 ps
CPU time 43.02 seconds
Started Apr 18 01:17:23 PM PDT 24
Finished Apr 18 01:18:07 PM PDT 24
Peak memory 204272 kb
Host smart-42d0ada6-98c1-4d4f-b3eb-d9806606aece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56205
1636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.562051636
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.2040901064
Short name T1297
Test name
Test status
Simulation time 8403299695 ps
CPU time 7.78 seconds
Started Apr 18 01:17:23 PM PDT 24
Finished Apr 18 01:17:31 PM PDT 24
Peak memory 204004 kb
Host smart-35688f4e-65f9-444e-b8a8-cbce44452777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20409
01064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.2040901064
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.958317684
Short name T1344
Test name
Test status
Simulation time 8398760212 ps
CPU time 8.76 seconds
Started Apr 18 01:17:27 PM PDT 24
Finished Apr 18 01:17:37 PM PDT 24
Peak memory 204044 kb
Host smart-6b860318-e5da-464f-955a-9f268fed87d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95831
7684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.958317684
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.1934301813
Short name T403
Test name
Test status
Simulation time 8416698258 ps
CPU time 9.18 seconds
Started Apr 18 01:17:23 PM PDT 24
Finished Apr 18 01:17:33 PM PDT 24
Peak memory 203980 kb
Host smart-efaa9b5f-df94-4bfc-985e-56a7cad8eeb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19343
01813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.1934301813
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.3191696054
Short name T976
Test name
Test status
Simulation time 8375166436 ps
CPU time 7.98 seconds
Started Apr 18 01:17:34 PM PDT 24
Finished Apr 18 01:17:42 PM PDT 24
Peak memory 204024 kb
Host smart-ca5512b0-da28-43ab-82fb-2705e62fd437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31916
96054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.3191696054
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.1901701188
Short name T567
Test name
Test status
Simulation time 8431041213 ps
CPU time 8.01 seconds
Started Apr 18 01:17:22 PM PDT 24
Finished Apr 18 01:17:31 PM PDT 24
Peak memory 204076 kb
Host smart-e445d736-9579-44c4-9676-3923219b2fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19017
01188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.1901701188
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.2760400217
Short name T1153
Test name
Test status
Simulation time 8427395983 ps
CPU time 8.06 seconds
Started Apr 18 01:17:23 PM PDT 24
Finished Apr 18 01:17:32 PM PDT 24
Peak memory 203988 kb
Host smart-03f103ff-373e-49bb-85a0-77ee263c42f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27604
00217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2760400217
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.3070413620
Short name T705
Test name
Test status
Simulation time 8404233646 ps
CPU time 8.21 seconds
Started Apr 18 01:17:25 PM PDT 24
Finished Apr 18 01:17:34 PM PDT 24
Peak memory 203920 kb
Host smart-60f6b9f9-16e6-4ced-a1b0-875338eaf247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30704
13620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.3070413620
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.402669223
Short name T632
Test name
Test status
Simulation time 8390814738 ps
CPU time 7.98 seconds
Started Apr 18 01:17:22 PM PDT 24
Finished Apr 18 01:17:30 PM PDT 24
Peak memory 204012 kb
Host smart-c2034667-c8b0-4b43-ba6f-9465ebb79447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40266
9223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.402669223
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.3140512919
Short name T814
Test name
Test status
Simulation time 8491865863 ps
CPU time 7.98 seconds
Started Apr 18 01:17:28 PM PDT 24
Finished Apr 18 01:17:37 PM PDT 24
Peak memory 204088 kb
Host smart-0a02a515-c771-408c-86c1-975ea50b5692
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3140512919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.3140512919
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.927218201
Short name T924
Test name
Test status
Simulation time 8380052234 ps
CPU time 9.98 seconds
Started Apr 18 01:17:30 PM PDT 24
Finished Apr 18 01:17:40 PM PDT 24
Peak memory 203952 kb
Host smart-5d5d1172-937b-4a7d-a2d7-3f034a3b85f6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=927218201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.927218201
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.1001208827
Short name T604
Test name
Test status
Simulation time 8395758631 ps
CPU time 8.37 seconds
Started Apr 18 01:17:33 PM PDT 24
Finished Apr 18 01:17:41 PM PDT 24
Peak memory 204060 kb
Host smart-5a14a55f-d633-410c-a9ac-45723dd80161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10012
08827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.1001208827
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.416509561
Short name T1218
Test name
Test status
Simulation time 8372721855 ps
CPU time 8.28 seconds
Started Apr 18 01:17:25 PM PDT 24
Finished Apr 18 01:17:34 PM PDT 24
Peak memory 203820 kb
Host smart-3b8e6c4f-584e-4cd6-8ff7-1c92c1e82a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41650
9561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.416509561
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_enable.3712108967
Short name T812
Test name
Test status
Simulation time 8378800365 ps
CPU time 7.95 seconds
Started Apr 18 01:17:27 PM PDT 24
Finished Apr 18 01:17:36 PM PDT 24
Peak memory 204008 kb
Host smart-d85fd49d-8b5f-4b40-835d-1ca676d83d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37121
08967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.3712108967
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.4269810159
Short name T1208
Test name
Test status
Simulation time 66221381 ps
CPU time 1.69 seconds
Started Apr 18 01:17:24 PM PDT 24
Finished Apr 18 01:17:27 PM PDT 24
Peak memory 204084 kb
Host smart-80cd7729-8a24-476a-b16b-2f896947e6c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42698
10159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.4269810159
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.3900353898
Short name T970
Test name
Test status
Simulation time 8417975292 ps
CPU time 10.47 seconds
Started Apr 18 01:17:38 PM PDT 24
Finished Apr 18 01:17:50 PM PDT 24
Peak memory 203956 kb
Host smart-2911b2e6-1148-4c78-870f-fcd19f9e67c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39003
53898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.3900353898
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.508773983
Short name T1199
Test name
Test status
Simulation time 8369887601 ps
CPU time 7.81 seconds
Started Apr 18 01:17:34 PM PDT 24
Finished Apr 18 01:17:42 PM PDT 24
Peak memory 203980 kb
Host smart-e4328c06-9735-4f9e-b204-d70c0433fb04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50877
3983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.508773983
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.2499148236
Short name T639
Test name
Test status
Simulation time 8454032440 ps
CPU time 10.49 seconds
Started Apr 18 01:17:27 PM PDT 24
Finished Apr 18 01:17:38 PM PDT 24
Peak memory 203904 kb
Host smart-b9161808-f7d4-49bb-b83f-774c1f09e801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24991
48236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.2499148236
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.3810642620
Short name T566
Test name
Test status
Simulation time 8418537740 ps
CPU time 7.92 seconds
Started Apr 18 01:17:30 PM PDT 24
Finished Apr 18 01:17:38 PM PDT 24
Peak memory 204028 kb
Host smart-2ccb3c2e-2d51-4da2-bdff-313bdfeb67f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38106
42620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.3810642620
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3688493288
Short name T1183
Test name
Test status
Simulation time 8374068416 ps
CPU time 8.6 seconds
Started Apr 18 01:17:23 PM PDT 24
Finished Apr 18 01:17:33 PM PDT 24
Peak memory 204028 kb
Host smart-ce2bac17-824a-4ead-93ff-62de92f17ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36884
93288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3688493288
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.1602155801
Short name T119
Test name
Test status
Simulation time 8428313053 ps
CPU time 8.65 seconds
Started Apr 18 01:17:35 PM PDT 24
Finished Apr 18 01:17:45 PM PDT 24
Peak memory 203928 kb
Host smart-6d5ee88d-c98d-496d-9809-7fad43bcd67d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16021
55801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.1602155801
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.2071292111
Short name T1073
Test name
Test status
Simulation time 8376054004 ps
CPU time 8.04 seconds
Started Apr 18 01:17:34 PM PDT 24
Finished Apr 18 01:17:43 PM PDT 24
Peak memory 203996 kb
Host smart-067a0d11-8ab3-40a9-b173-9e936aabad3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20712
92111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.2071292111
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3348185843
Short name T1155
Test name
Test status
Simulation time 8413832410 ps
CPU time 8.26 seconds
Started Apr 18 01:17:29 PM PDT 24
Finished Apr 18 01:17:38 PM PDT 24
Peak memory 203864 kb
Host smart-e46c9b06-d429-4667-82d4-f6abf6319868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33481
85843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3348185843
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.1357727359
Short name T453
Test name
Test status
Simulation time 8385147189 ps
CPU time 7.51 seconds
Started Apr 18 01:17:29 PM PDT 24
Finished Apr 18 01:17:37 PM PDT 24
Peak memory 204024 kb
Host smart-5f5a1055-b7e5-4118-9c52-a960d09f84d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13577
27359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.1357727359
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1557454127
Short name T1375
Test name
Test status
Simulation time 8382302555 ps
CPU time 8.87 seconds
Started Apr 18 01:17:28 PM PDT 24
Finished Apr 18 01:17:38 PM PDT 24
Peak memory 204020 kb
Host smart-fbd6b1a4-e163-4376-9a0d-d714387d728d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15574
54127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1557454127
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.2906720842
Short name T981
Test name
Test status
Simulation time 196015495 ps
CPU time 0.89 seconds
Started Apr 18 01:17:28 PM PDT 24
Finished Apr 18 01:17:30 PM PDT 24
Peak memory 203888 kb
Host smart-8f45561f-ff1f-4136-b496-556a2c0bd1ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29067
20842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.2906720842
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.1708252939
Short name T250
Test name
Test status
Simulation time 26396282197 ps
CPU time 52.2 seconds
Started Apr 18 01:17:34 PM PDT 24
Finished Apr 18 01:18:26 PM PDT 24
Peak memory 204268 kb
Host smart-9fd39990-710c-40ae-8a2a-2f603bf8b9aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17082
52939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.1708252939
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.35391336
Short name T1318
Test name
Test status
Simulation time 8414010941 ps
CPU time 8.72 seconds
Started Apr 18 01:17:29 PM PDT 24
Finished Apr 18 01:17:38 PM PDT 24
Peak memory 203996 kb
Host smart-aa4617a0-6f37-4de9-bc03-d6153c6bda24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35391
336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.35391336
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.3590442036
Short name T1084
Test name
Test status
Simulation time 8433252764 ps
CPU time 9.18 seconds
Started Apr 18 01:17:33 PM PDT 24
Finished Apr 18 01:17:42 PM PDT 24
Peak memory 204060 kb
Host smart-9c320340-1176-4153-91fe-9dccddb232be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35904
42036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.3590442036
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.2215397368
Short name T1016
Test name
Test status
Simulation time 8407747777 ps
CPU time 8.41 seconds
Started Apr 18 01:17:35 PM PDT 24
Finished Apr 18 01:17:43 PM PDT 24
Peak memory 203908 kb
Host smart-1d7ccb24-b67c-44c8-97fa-3386761dc8af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22153
97368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.2215397368
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.3072487452
Short name T1014
Test name
Test status
Simulation time 8408394351 ps
CPU time 8.25 seconds
Started Apr 18 01:17:27 PM PDT 24
Finished Apr 18 01:17:36 PM PDT 24
Peak memory 204048 kb
Host smart-ef1cf623-68d4-4c1e-b065-b496f9ec7500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30724
87452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.3072487452
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3592587043
Short name T338
Test name
Test status
Simulation time 8382756437 ps
CPU time 7.94 seconds
Started Apr 18 01:17:29 PM PDT 24
Finished Apr 18 01:17:37 PM PDT 24
Peak memory 203940 kb
Host smart-d4916b36-03c5-4a25-a1f8-f2d3ac6512ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35925
87043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3592587043
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.3166725310
Short name T654
Test name
Test status
Simulation time 8460951364 ps
CPU time 8.2 seconds
Started Apr 18 01:17:23 PM PDT 24
Finished Apr 18 01:17:32 PM PDT 24
Peak memory 204000 kb
Host smart-e4ecc26c-661e-455a-94e8-3cf51eef1b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31667
25310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.3166725310
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2172004597
Short name T611
Test name
Test status
Simulation time 8402489700 ps
CPU time 7.57 seconds
Started Apr 18 01:17:35 PM PDT 24
Finished Apr 18 01:17:43 PM PDT 24
Peak memory 204028 kb
Host smart-c0d8a506-f1a7-4347-98b2-fea9122fe11d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21720
04597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.2172004597
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.770803918
Short name T965
Test name
Test status
Simulation time 8384485974 ps
CPU time 8.15 seconds
Started Apr 18 01:17:27 PM PDT 24
Finished Apr 18 01:17:36 PM PDT 24
Peak memory 203980 kb
Host smart-10da4c7a-006d-4663-85df-17b0f4d71560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77080
3918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.770803918
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.max_length_in_transaction.1629007883
Short name T1304
Test name
Test status
Simulation time 8504160193 ps
CPU time 8.14 seconds
Started Apr 18 01:17:36 PM PDT 24
Finished Apr 18 01:17:45 PM PDT 24
Peak memory 204052 kb
Host smart-b3c26aa8-09e6-46dc-b63a-d7f1a7b074b9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1629007883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.1629007883
Directory /workspace/45.max_length_in_transaction/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.2472640613
Short name T1255
Test name
Test status
Simulation time 8402394393 ps
CPU time 8.14 seconds
Started Apr 18 01:17:36 PM PDT 24
Finished Apr 18 01:17:45 PM PDT 24
Peak memory 204008 kb
Host smart-9465cccd-1157-4c35-a56c-b1943579ea1e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2472640613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.2472640613
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.random_length_in_trans.4166010777
Short name T1212
Test name
Test status
Simulation time 8427069516 ps
CPU time 8.11 seconds
Started Apr 18 01:17:41 PM PDT 24
Finished Apr 18 01:17:50 PM PDT 24
Peak memory 203964 kb
Host smart-b731eb41-1fd5-4c0a-8823-4bf107a8ebe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41660
10777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.4166010777
Directory /workspace/45.random_length_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.1528446282
Short name T1003
Test name
Test status
Simulation time 8386302667 ps
CPU time 9.29 seconds
Started Apr 18 01:17:37 PM PDT 24
Finished Apr 18 01:17:47 PM PDT 24
Peak memory 204028 kb
Host smart-07b7c90e-e91f-40f5-aaba-8b7ed3e7e87a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15284
46282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.1528446282
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_enable.3433694265
Short name T582
Test name
Test status
Simulation time 8373090625 ps
CPU time 9.13 seconds
Started Apr 18 01:17:28 PM PDT 24
Finished Apr 18 01:17:37 PM PDT 24
Peak memory 203960 kb
Host smart-05f365f9-65a3-4a92-a309-906df8d2999a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34336
94265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.3433694265
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.3211135039
Short name T927
Test name
Test status
Simulation time 167451079 ps
CPU time 1.44 seconds
Started Apr 18 01:17:36 PM PDT 24
Finished Apr 18 01:17:38 PM PDT 24
Peak memory 204136 kb
Host smart-c98b054f-15e7-42b6-8c5e-c441333d0d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32111
35039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.3211135039
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.803218187
Short name T695
Test name
Test status
Simulation time 8426784865 ps
CPU time 10.42 seconds
Started Apr 18 01:17:42 PM PDT 24
Finished Apr 18 01:17:53 PM PDT 24
Peak memory 203956 kb
Host smart-1bae9c25-1073-4451-8499-a3ceaf972910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80321
8187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.803218187
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1516733301
Short name T386
Test name
Test status
Simulation time 8369752368 ps
CPU time 8.22 seconds
Started Apr 18 01:17:36 PM PDT 24
Finished Apr 18 01:17:45 PM PDT 24
Peak memory 203964 kb
Host smart-5cab6379-563c-4908-befb-b6884ab4c9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15167
33301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1516733301
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2272883216
Short name T551
Test name
Test status
Simulation time 8430801698 ps
CPU time 8.46 seconds
Started Apr 18 01:17:38 PM PDT 24
Finished Apr 18 01:17:48 PM PDT 24
Peak memory 204028 kb
Host smart-d6f05a8a-d107-467a-9f17-435ee19badd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22728
83216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2272883216
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.726500057
Short name T520
Test name
Test status
Simulation time 8421594513 ps
CPU time 7.74 seconds
Started Apr 18 01:17:35 PM PDT 24
Finished Apr 18 01:17:43 PM PDT 24
Peak memory 204028 kb
Host smart-a55d5dcd-89bb-46f2-8762-f87d97f700c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72650
0057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.726500057
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2563256
Short name T672
Test name
Test status
Simulation time 8388001754 ps
CPU time 8.43 seconds
Started Apr 18 01:17:32 PM PDT 24
Finished Apr 18 01:17:41 PM PDT 24
Peak memory 204044 kb
Host smart-ade97a32-2c59-4a59-9a73-ce8edf4d19af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25632
56 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2563256
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.745992206
Short name T102
Test name
Test status
Simulation time 8403514281 ps
CPU time 8.4 seconds
Started Apr 18 01:17:30 PM PDT 24
Finished Apr 18 01:17:39 PM PDT 24
Peak memory 204032 kb
Host smart-84e564e1-0fe0-493a-873f-4450bec6e32a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74599
2206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.745992206
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.1656943026
Short name T290
Test name
Test status
Simulation time 8407938221 ps
CPU time 8.34 seconds
Started Apr 18 01:17:56 PM PDT 24
Finished Apr 18 01:18:05 PM PDT 24
Peak memory 204012 kb
Host smart-f42ac679-9af7-4ffb-b29d-7642770b07d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16569
43026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.1656943026
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.1872507188
Short name T1250
Test name
Test status
Simulation time 8396707101 ps
CPU time 8.11 seconds
Started Apr 18 01:17:37 PM PDT 24
Finished Apr 18 01:17:46 PM PDT 24
Peak memory 203940 kb
Host smart-06504ac2-1e99-4d2a-9f04-c3c9d38ce895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18725
07188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.1872507188
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.3899701521
Short name T1114
Test name
Test status
Simulation time 8426828139 ps
CPU time 7.53 seconds
Started Apr 18 01:17:38 PM PDT 24
Finished Apr 18 01:17:46 PM PDT 24
Peak memory 204020 kb
Host smart-ed6c5eae-3761-48ff-86f5-a1fd282f5733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38997
01521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.3899701521
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.1368340295
Short name T25
Test name
Test status
Simulation time 8378188424 ps
CPU time 8.3 seconds
Started Apr 18 01:17:38 PM PDT 24
Finished Apr 18 01:17:47 PM PDT 24
Peak memory 203960 kb
Host smart-39b1985b-7ae5-4858-ab10-c07b5c6e0720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13683
40295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.1368340295
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.284188059
Short name T42
Test name
Test status
Simulation time 41192742 ps
CPU time 0.68 seconds
Started Apr 18 01:17:37 PM PDT 24
Finished Apr 18 01:17:38 PM PDT 24
Peak memory 203916 kb
Host smart-e0c1a4da-a607-4442-a437-cd1ac3e089f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28418
8059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.284188059
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.3180984467
Short name T1235
Test name
Test status
Simulation time 14445370674 ps
CPU time 25.78 seconds
Started Apr 18 01:17:54 PM PDT 24
Finished Apr 18 01:18:21 PM PDT 24
Peak memory 204216 kb
Host smart-660e4a8f-2ce3-4503-8df1-cb18715647f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31809
84467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.3180984467
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.2463479897
Short name T1364
Test name
Test status
Simulation time 8414655829 ps
CPU time 7.91 seconds
Started Apr 18 01:17:29 PM PDT 24
Finished Apr 18 01:17:38 PM PDT 24
Peak memory 203940 kb
Host smart-543d726a-836b-4ba0-a8e7-f557ff9ee12f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24634
79897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.2463479897
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.343408659
Short name T1120
Test name
Test status
Simulation time 8390507484 ps
CPU time 8.75 seconds
Started Apr 18 01:17:33 PM PDT 24
Finished Apr 18 01:17:42 PM PDT 24
Peak memory 204024 kb
Host smart-5444a6a5-9558-4e7f-afd1-d3db100b889b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34340
8659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.343408659
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.217565607
Short name T1222
Test name
Test status
Simulation time 8455724781 ps
CPU time 7.75 seconds
Started Apr 18 01:17:33 PM PDT 24
Finished Apr 18 01:17:41 PM PDT 24
Peak memory 204268 kb
Host smart-84e8cdf2-99f6-4257-9e2c-adce5d72b897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21756
5607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.217565607
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.2887986163
Short name T149
Test name
Test status
Simulation time 8371213809 ps
CPU time 8.54 seconds
Started Apr 18 01:17:36 PM PDT 24
Finished Apr 18 01:17:45 PM PDT 24
Peak memory 203944 kb
Host smart-7a0e1e83-cac4-4d7a-9db7-e1a9427b8abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28879
86163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.2887986163
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.128497558
Short name T822
Test name
Test status
Simulation time 8382050035 ps
CPU time 9.08 seconds
Started Apr 18 01:17:29 PM PDT 24
Finished Apr 18 01:17:39 PM PDT 24
Peak memory 203896 kb
Host smart-84f61c9f-4d57-4f66-be8e-6d2c9706e444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12849
7558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.128497558
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.2438006326
Short name T126
Test name
Test status
Simulation time 8436987374 ps
CPU time 7.89 seconds
Started Apr 18 01:17:28 PM PDT 24
Finished Apr 18 01:17:41 PM PDT 24
Peak memory 204044 kb
Host smart-18597935-7688-487c-bcc4-18baee3e61b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24380
06326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.2438006326
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.2626097894
Short name T312
Test name
Test status
Simulation time 8391991562 ps
CPU time 8.46 seconds
Started Apr 18 01:17:39 PM PDT 24
Finished Apr 18 01:17:48 PM PDT 24
Peak memory 204040 kb
Host smart-496f32d4-65bb-4a87-9805-ea21fccbd8b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26260
97894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.2626097894
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.2908613795
Short name T893
Test name
Test status
Simulation time 8409938207 ps
CPU time 8.29 seconds
Started Apr 18 01:17:33 PM PDT 24
Finished Apr 18 01:17:41 PM PDT 24
Peak memory 203920 kb
Host smart-ac555dd9-7757-4a5c-88ae-198b132ab730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29086
13795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.2908613795
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.1368697462
Short name T1109
Test name
Test status
Simulation time 8473022670 ps
CPU time 8.48 seconds
Started Apr 18 01:17:39 PM PDT 24
Finished Apr 18 01:17:48 PM PDT 24
Peak memory 204048 kb
Host smart-66d1a8ae-f21d-4809-a272-6201e306c37d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1368697462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.1368697462
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.2810904074
Short name T419
Test name
Test status
Simulation time 8381176388 ps
CPU time 8.22 seconds
Started Apr 18 01:17:41 PM PDT 24
Finished Apr 18 01:17:50 PM PDT 24
Peak memory 203856 kb
Host smart-0122c658-caeb-490d-b7d2-1d465917b878
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2810904074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.2810904074
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.2777008341
Short name T783
Test name
Test status
Simulation time 8449273252 ps
CPU time 8.33 seconds
Started Apr 18 01:17:38 PM PDT 24
Finished Apr 18 01:17:47 PM PDT 24
Peak memory 204016 kb
Host smart-e3fdfe95-1954-4b4e-b8e3-d3ca3bf893ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27770
08341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.2777008341
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.2016103213
Short name T706
Test name
Test status
Simulation time 8393270067 ps
CPU time 8.44 seconds
Started Apr 18 01:17:41 PM PDT 24
Finished Apr 18 01:17:50 PM PDT 24
Peak memory 203860 kb
Host smart-e6ffa32c-1a0a-4602-a2dd-fd6032e3cd98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20161
03213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.2016103213
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_enable.2660125176
Short name T816
Test name
Test status
Simulation time 8376711111 ps
CPU time 8.24 seconds
Started Apr 18 01:17:46 PM PDT 24
Finished Apr 18 01:17:55 PM PDT 24
Peak memory 204080 kb
Host smart-65a7f28a-2885-43a8-98db-07359a7ddd25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26601
25176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2660125176
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.2589846496
Short name T1
Test name
Test status
Simulation time 124069436 ps
CPU time 1.22 seconds
Started Apr 18 01:17:41 PM PDT 24
Finished Apr 18 01:17:43 PM PDT 24
Peak memory 204152 kb
Host smart-2107bb0e-01fe-46b2-86ee-4a094e3cd4ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25898
46496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.2589846496
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.1649364120
Short name T1007
Test name
Test status
Simulation time 8393556653 ps
CPU time 8.23 seconds
Started Apr 18 01:17:36 PM PDT 24
Finished Apr 18 01:17:45 PM PDT 24
Peak memory 204036 kb
Host smart-64638bb2-cfaa-403b-8379-0c441d53ac25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16493
64120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.1649364120
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.1611418021
Short name T841
Test name
Test status
Simulation time 8366591244 ps
CPU time 8.16 seconds
Started Apr 18 01:17:40 PM PDT 24
Finished Apr 18 01:17:48 PM PDT 24
Peak memory 203992 kb
Host smart-a1e58c3f-403d-45dc-907d-073779bdd84b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16114
18021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.1611418021
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.1055591687
Short name T635
Test name
Test status
Simulation time 8401087713 ps
CPU time 7.77 seconds
Started Apr 18 01:17:43 PM PDT 24
Finished Apr 18 01:17:52 PM PDT 24
Peak memory 204004 kb
Host smart-89f34bbd-f11b-4158-a96c-11627f9d6a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10555
91687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.1055591687
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.3695888525
Short name T1223
Test name
Test status
Simulation time 8426849173 ps
CPU time 8.35 seconds
Started Apr 18 01:17:36 PM PDT 24
Finished Apr 18 01:17:45 PM PDT 24
Peak memory 204044 kb
Host smart-a063cd92-846b-4211-b220-fe5712e76a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36958
88525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.3695888525
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.2968534170
Short name T484
Test name
Test status
Simulation time 8375461476 ps
CPU time 9.87 seconds
Started Apr 18 01:17:41 PM PDT 24
Finished Apr 18 01:17:51 PM PDT 24
Peak memory 203964 kb
Host smart-802deda3-30c4-441e-b33e-574a4377f5e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29685
34170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.2968534170
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.2152430385
Short name T76
Test name
Test status
Simulation time 8414413469 ps
CPU time 7.73 seconds
Started Apr 18 01:17:34 PM PDT 24
Finished Apr 18 01:17:42 PM PDT 24
Peak memory 203984 kb
Host smart-dce6952f-d504-4f8a-a391-3cc337a6dbe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21524
30385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.2152430385
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.1125976086
Short name T580
Test name
Test status
Simulation time 8410346152 ps
CPU time 8.22 seconds
Started Apr 18 01:17:39 PM PDT 24
Finished Apr 18 01:17:48 PM PDT 24
Peak memory 204024 kb
Host smart-8b968c70-a52a-459f-9841-f4fa4ffd005d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11259
76086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.1125976086
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.4075126663
Short name T1267
Test name
Test status
Simulation time 8415542846 ps
CPU time 7.5 seconds
Started Apr 18 01:17:39 PM PDT 24
Finished Apr 18 01:17:48 PM PDT 24
Peak memory 203996 kb
Host smart-30e0bbe9-de47-4899-8149-888e18505319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40751
26663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.4075126663
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.3328954996
Short name T1036
Test name
Test status
Simulation time 8433188456 ps
CPU time 8.71 seconds
Started Apr 18 01:17:38 PM PDT 24
Finished Apr 18 01:17:47 PM PDT 24
Peak memory 204004 kb
Host smart-4567e038-c534-4388-b4b1-bec05127a56b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33289
54996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.3328954996
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.477344031
Short name T1205
Test name
Test status
Simulation time 8364887217 ps
CPU time 7.83 seconds
Started Apr 18 01:17:35 PM PDT 24
Finished Apr 18 01:17:44 PM PDT 24
Peak memory 204024 kb
Host smart-82171eef-e03a-412f-8016-8c6cf1b48dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47734
4031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.477344031
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.2798259875
Short name T943
Test name
Test status
Simulation time 45583106 ps
CPU time 0.69 seconds
Started Apr 18 01:17:38 PM PDT 24
Finished Apr 18 01:17:39 PM PDT 24
Peak memory 203884 kb
Host smart-a22e6dbc-e6f3-4517-a8f2-cab8aaaf2958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27982
59875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.2798259875
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.3789225057
Short name T997
Test name
Test status
Simulation time 27856961527 ps
CPU time 57 seconds
Started Apr 18 01:17:42 PM PDT 24
Finished Apr 18 01:18:40 PM PDT 24
Peak memory 204248 kb
Host smart-a1b5dd19-f5ce-47ba-8393-50a055023cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37892
25057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.3789225057
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.771046838
Short name T1370
Test name
Test status
Simulation time 8456801909 ps
CPU time 7.77 seconds
Started Apr 18 01:17:39 PM PDT 24
Finished Apr 18 01:17:47 PM PDT 24
Peak memory 203996 kb
Host smart-b23edcb9-3e54-4b6d-8a0f-979a47bcb7d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77104
6838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.771046838
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.2045917612
Short name T513
Test name
Test status
Simulation time 8465505898 ps
CPU time 8.96 seconds
Started Apr 18 01:17:37 PM PDT 24
Finished Apr 18 01:17:47 PM PDT 24
Peak memory 204020 kb
Host smart-6cfafdc7-6e14-488a-b19f-b303cf8032b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20459
17612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.2045917612
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.145601120
Short name T856
Test name
Test status
Simulation time 8399434729 ps
CPU time 7.75 seconds
Started Apr 18 01:17:38 PM PDT 24
Finished Apr 18 01:17:46 PM PDT 24
Peak memory 204036 kb
Host smart-ede223d5-fe17-4533-a62f-80b97dc7187b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14560
1120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.145601120
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.625698013
Short name T794
Test name
Test status
Simulation time 8373132557 ps
CPU time 7.8 seconds
Started Apr 18 01:17:39 PM PDT 24
Finished Apr 18 01:17:48 PM PDT 24
Peak memory 204004 kb
Host smart-fbda0f69-0555-4518-a1d0-b51a361f26ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62569
8013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.625698013
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.1304317948
Short name T15
Test name
Test status
Simulation time 8381502623 ps
CPU time 8.08 seconds
Started Apr 18 01:17:38 PM PDT 24
Finished Apr 18 01:17:47 PM PDT 24
Peak memory 204024 kb
Host smart-248c73b7-2ac4-4981-b57c-dcabe6168718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13043
17948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.1304317948
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.821057756
Short name T1170
Test name
Test status
Simulation time 8454538790 ps
CPU time 8.27 seconds
Started Apr 18 01:17:40 PM PDT 24
Finished Apr 18 01:17:49 PM PDT 24
Peak memory 203996 kb
Host smart-d2b267ca-e3cd-4d79-9a3c-150c5c5e7486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82105
7756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.821057756
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.3260601143
Short name T593
Test name
Test status
Simulation time 8387666328 ps
CPU time 9.19 seconds
Started Apr 18 01:17:37 PM PDT 24
Finished Apr 18 01:17:47 PM PDT 24
Peak memory 204032 kb
Host smart-6ee62839-0796-4127-87f5-b921a87f7e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32606
01143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.3260601143
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2120646369
Short name T436
Test name
Test status
Simulation time 8405474001 ps
CPU time 9.47 seconds
Started Apr 18 01:17:36 PM PDT 24
Finished Apr 18 01:17:47 PM PDT 24
Peak memory 203972 kb
Host smart-277b758f-44f2-4f2c-a267-076a848340c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21206
46369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2120646369
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.425075628
Short name T1061
Test name
Test status
Simulation time 8470135509 ps
CPU time 8.98 seconds
Started Apr 18 01:17:45 PM PDT 24
Finished Apr 18 01:17:55 PM PDT 24
Peak memory 204044 kb
Host smart-d8b775e1-3a07-41a5-ab22-97d0e3d42682
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=425075628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.425075628
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.111178990
Short name T1140
Test name
Test status
Simulation time 8414937344 ps
CPU time 8.19 seconds
Started Apr 18 01:17:42 PM PDT 24
Finished Apr 18 01:17:51 PM PDT 24
Peak memory 203940 kb
Host smart-705760c0-dfd5-410b-8a24-c064b26d6d6b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=111178990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.111178990
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.3148234429
Short name T849
Test name
Test status
Simulation time 8468072832 ps
CPU time 8.87 seconds
Started Apr 18 01:17:43 PM PDT 24
Finished Apr 18 01:17:52 PM PDT 24
Peak memory 204012 kb
Host smart-4bc2b7b1-070b-4ec0-83d6-89ba7264c5fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31482
34429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.3148234429
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1013659246
Short name T1125
Test name
Test status
Simulation time 8373724190 ps
CPU time 7.91 seconds
Started Apr 18 01:17:37 PM PDT 24
Finished Apr 18 01:17:46 PM PDT 24
Peak memory 204080 kb
Host smart-90a08def-f5ac-4a47-ad82-cc847f7ac1fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10136
59246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1013659246
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_enable.2162295838
Short name T1172
Test name
Test status
Simulation time 8386709115 ps
CPU time 8.22 seconds
Started Apr 18 01:17:37 PM PDT 24
Finished Apr 18 01:17:46 PM PDT 24
Peak memory 203920 kb
Host smart-4a2ae261-c479-4cdf-9eeb-12fc5a1c4162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21622
95838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2162295838
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.541496355
Short name T711
Test name
Test status
Simulation time 136124703 ps
CPU time 1.48 seconds
Started Apr 18 01:17:38 PM PDT 24
Finished Apr 18 01:17:40 PM PDT 24
Peak memory 204084 kb
Host smart-3ad8d7d8-a391-47e1-a1ea-d3dc68c6ade1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54149
6355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.541496355
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.3417774829
Short name T479
Test name
Test status
Simulation time 8452744139 ps
CPU time 8.56 seconds
Started Apr 18 01:17:45 PM PDT 24
Finished Apr 18 01:17:54 PM PDT 24
Peak memory 204000 kb
Host smart-a8f6d29f-009a-486e-9557-8df0355a284d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34177
74829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.3417774829
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.179136945
Short name T172
Test name
Test status
Simulation time 8371042630 ps
CPU time 8.8 seconds
Started Apr 18 01:17:51 PM PDT 24
Finished Apr 18 01:18:00 PM PDT 24
Peak memory 204024 kb
Host smart-6273cad2-983a-4528-bb6d-15e41c87ae55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17913
6945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.179136945
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.2267684445
Short name T1180
Test name
Test status
Simulation time 8514081550 ps
CPU time 8.09 seconds
Started Apr 18 01:17:36 PM PDT 24
Finished Apr 18 01:17:45 PM PDT 24
Peak memory 204036 kb
Host smart-c8d78d7d-c5e9-464d-878f-9986ebb1cc24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22676
84445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2267684445
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.967800440
Short name T440
Test name
Test status
Simulation time 8444615011 ps
CPU time 8.13 seconds
Started Apr 18 01:17:37 PM PDT 24
Finished Apr 18 01:17:46 PM PDT 24
Peak memory 203920 kb
Host smart-3d091c95-6f35-491d-bca2-674a4de85aa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96780
0440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.967800440
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.559299098
Short name T327
Test name
Test status
Simulation time 8364280823 ps
CPU time 8.37 seconds
Started Apr 18 01:17:42 PM PDT 24
Finished Apr 18 01:17:51 PM PDT 24
Peak memory 204040 kb
Host smart-ecd7a186-2c02-4582-a58a-cbea40f45e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55929
9098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.559299098
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.4187519629
Short name T898
Test name
Test status
Simulation time 8431181595 ps
CPU time 9.14 seconds
Started Apr 18 01:17:50 PM PDT 24
Finished Apr 18 01:18:00 PM PDT 24
Peak memory 204028 kb
Host smart-1bb3cb45-7192-4a08-92dc-e6d85183a3b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41875
19629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.4187519629
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.848172002
Short name T725
Test name
Test status
Simulation time 8410483593 ps
CPU time 7.77 seconds
Started Apr 18 01:17:45 PM PDT 24
Finished Apr 18 01:17:53 PM PDT 24
Peak memory 204000 kb
Host smart-f5d21f90-e6b7-4231-a7e2-ec79bf75eb7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84817
2002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.848172002
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.2424042086
Short name T1351
Test name
Test status
Simulation time 8386821738 ps
CPU time 9.29 seconds
Started Apr 18 01:17:43 PM PDT 24
Finished Apr 18 01:17:53 PM PDT 24
Peak memory 204032 kb
Host smart-63594e16-350b-47b3-b310-a2bbbf1dd721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24240
42086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.2424042086
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.3595288015
Short name T854
Test name
Test status
Simulation time 8399707516 ps
CPU time 8.37 seconds
Started Apr 18 01:17:41 PM PDT 24
Finished Apr 18 01:17:50 PM PDT 24
Peak memory 203900 kb
Host smart-122757e2-b832-4b2c-8b8b-404cab401427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35952
88015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.3595288015
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.983237658
Short name T280
Test name
Test status
Simulation time 8363112073 ps
CPU time 8.44 seconds
Started Apr 18 01:17:43 PM PDT 24
Finished Apr 18 01:17:52 PM PDT 24
Peak memory 203860 kb
Host smart-4cbac6ce-7699-4155-b5e0-9708fd3a4995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98323
7658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.983237658
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.1456521247
Short name T1078
Test name
Test status
Simulation time 36588556 ps
CPU time 0.64 seconds
Started Apr 18 01:17:44 PM PDT 24
Finished Apr 18 01:17:46 PM PDT 24
Peak memory 203888 kb
Host smart-9c1c5163-c26e-4a15-b0c3-2907328a8bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14565
21247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.1456521247
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.3649313565
Short name T1051
Test name
Test status
Simulation time 13847777175 ps
CPU time 24.95 seconds
Started Apr 18 01:17:52 PM PDT 24
Finished Apr 18 01:18:17 PM PDT 24
Peak memory 204312 kb
Host smart-c520610d-fc89-4260-a6eb-7a9ee54332ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36493
13565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.3649313565
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.1424739641
Short name T52
Test name
Test status
Simulation time 8406846808 ps
CPU time 8.74 seconds
Started Apr 18 01:17:50 PM PDT 24
Finished Apr 18 01:18:00 PM PDT 24
Peak memory 204012 kb
Host smart-ee9151ca-7a2a-42e6-9bdb-79691bb94cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14247
39641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1424739641
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.1384978466
Short name T550
Test name
Test status
Simulation time 8431796514 ps
CPU time 8.15 seconds
Started Apr 18 01:17:41 PM PDT 24
Finished Apr 18 01:17:49 PM PDT 24
Peak memory 204012 kb
Host smart-de98a561-3501-45b5-a98a-ca92aae83872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13849
78466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.1384978466
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.541501428
Short name T697
Test name
Test status
Simulation time 8421011832 ps
CPU time 7.64 seconds
Started Apr 18 01:17:50 PM PDT 24
Finished Apr 18 01:17:59 PM PDT 24
Peak memory 204024 kb
Host smart-dd9dc1a5-2a26-4ac6-a1d4-f00b31646585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54150
1428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.541501428
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.3585014893
Short name T1354
Test name
Test status
Simulation time 8382337209 ps
CPU time 8.56 seconds
Started Apr 18 01:17:48 PM PDT 24
Finished Apr 18 01:17:58 PM PDT 24
Peak memory 203904 kb
Host smart-121f93c0-4cc8-4b4a-8d2f-662785071754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35850
14893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.3585014893
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2334994251
Short name T935
Test name
Test status
Simulation time 8367559030 ps
CPU time 7.38 seconds
Started Apr 18 01:17:46 PM PDT 24
Finished Apr 18 01:17:53 PM PDT 24
Peak memory 203968 kb
Host smart-33a308f3-36aa-4e31-b7a3-5c8c006294de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23349
94251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2334994251
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.4233618063
Short name T699
Test name
Test status
Simulation time 8464783603 ps
CPU time 8.86 seconds
Started Apr 18 01:17:37 PM PDT 24
Finished Apr 18 01:17:47 PM PDT 24
Peak memory 204020 kb
Host smart-1e4668ea-227b-4799-82ed-d88637c7447a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42336
18063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.4233618063
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.4154158112
Short name T1159
Test name
Test status
Simulation time 8378115012 ps
CPU time 7.76 seconds
Started Apr 18 01:17:42 PM PDT 24
Finished Apr 18 01:17:50 PM PDT 24
Peak memory 203920 kb
Host smart-ad29e0aa-a7c3-4c8b-a5b5-5e71e0b1faa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41541
58112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.4154158112
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.1592136489
Short name T708
Test name
Test status
Simulation time 8407458904 ps
CPU time 8.79 seconds
Started Apr 18 01:17:45 PM PDT 24
Finished Apr 18 01:17:54 PM PDT 24
Peak memory 204036 kb
Host smart-ab5ff239-f60e-4c8d-a171-cb96c5ed90e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15921
36489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.1592136489
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.2765664752
Short name T883
Test name
Test status
Simulation time 8468092202 ps
CPU time 9.02 seconds
Started Apr 18 01:17:52 PM PDT 24
Finished Apr 18 01:18:02 PM PDT 24
Peak memory 204004 kb
Host smart-e132503b-7fce-44b5-bb53-cab661234546
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2765664752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.2765664752
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.3075239430
Short name T674
Test name
Test status
Simulation time 8475194157 ps
CPU time 7.59 seconds
Started Apr 18 01:17:47 PM PDT 24
Finished Apr 18 01:17:56 PM PDT 24
Peak memory 204016 kb
Host smart-d12048f7-69a7-4a6f-af04-653f2993f234
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3075239430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.3075239430
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.515038927
Short name T1213
Test name
Test status
Simulation time 8412171870 ps
CPU time 9.23 seconds
Started Apr 18 01:17:47 PM PDT 24
Finished Apr 18 01:17:57 PM PDT 24
Peak memory 203964 kb
Host smart-a3d33892-629a-4346-b75c-0aeba15b03ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51503
8927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.515038927
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1084556842
Short name T214
Test name
Test status
Simulation time 8383088228 ps
CPU time 8.05 seconds
Started Apr 18 01:17:49 PM PDT 24
Finished Apr 18 01:17:58 PM PDT 24
Peak memory 204044 kb
Host smart-af891f85-a25a-4467-9981-94b144e47d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10845
56842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1084556842
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_enable.664996205
Short name T585
Test name
Test status
Simulation time 8378992458 ps
CPU time 7.99 seconds
Started Apr 18 01:17:50 PM PDT 24
Finished Apr 18 01:17:59 PM PDT 24
Peak memory 204024 kb
Host smart-183d16e9-2f12-48bf-996e-ceaf606e4d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66499
6205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.664996205
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.832607902
Short name T451
Test name
Test status
Simulation time 54594019 ps
CPU time 1.44 seconds
Started Apr 18 01:17:44 PM PDT 24
Finished Apr 18 01:17:46 PM PDT 24
Peak memory 204136 kb
Host smart-f256c5a4-2dc6-49a9-8a80-6b74db5909b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83260
7902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.832607902
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.3793382594
Short name T51
Test name
Test status
Simulation time 8398249555 ps
CPU time 8.74 seconds
Started Apr 18 01:17:52 PM PDT 24
Finished Apr 18 01:18:01 PM PDT 24
Peak memory 204080 kb
Host smart-04d29386-32bd-4494-aaf8-b4840361e13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37933
82594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3793382594
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.4111461805
Short name T881
Test name
Test status
Simulation time 8410098367 ps
CPU time 8.34 seconds
Started Apr 18 01:17:47 PM PDT 24
Finished Apr 18 01:17:56 PM PDT 24
Peak memory 204080 kb
Host smart-a6a57063-d125-4257-a178-59d7ae90cfe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41114
61805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.4111461805
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.3770815679
Short name T137
Test name
Test status
Simulation time 8379420708 ps
CPU time 7.74 seconds
Started Apr 18 01:17:45 PM PDT 24
Finished Apr 18 01:17:54 PM PDT 24
Peak memory 204044 kb
Host smart-2df9f7b3-0c13-4130-aa8b-375db27551da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37708
15679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.3770815679
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.2421612204
Short name T840
Test name
Test status
Simulation time 8453159709 ps
CPU time 7.44 seconds
Started Apr 18 01:17:48 PM PDT 24
Finished Apr 18 01:17:56 PM PDT 24
Peak memory 204044 kb
Host smart-be4601cc-5c41-4774-a971-7d06520db9ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24216
12204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.2421612204
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.1080721689
Short name T319
Test name
Test status
Simulation time 8372991584 ps
CPU time 9.57 seconds
Started Apr 18 01:17:45 PM PDT 24
Finished Apr 18 01:17:56 PM PDT 24
Peak memory 204040 kb
Host smart-5cb45cae-b4ff-4327-a797-9d8fcac57801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10807
21689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.1080721689
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.3844272673
Short name T117
Test name
Test status
Simulation time 8420401398 ps
CPU time 7.6 seconds
Started Apr 18 01:17:49 PM PDT 24
Finished Apr 18 01:17:58 PM PDT 24
Peak memory 204012 kb
Host smart-d73f10dd-34c2-4982-ab66-2e76ecd04f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38442
72673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.3844272673
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.738765038
Short name T718
Test name
Test status
Simulation time 8399018668 ps
CPU time 7.75 seconds
Started Apr 18 01:17:43 PM PDT 24
Finished Apr 18 01:17:51 PM PDT 24
Peak memory 204060 kb
Host smart-f6571cda-9a95-4202-9a87-6b145a6514ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73876
5038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.738765038
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.1053667001
Short name T832
Test name
Test status
Simulation time 8410952357 ps
CPU time 7.91 seconds
Started Apr 18 01:17:43 PM PDT 24
Finished Apr 18 01:17:51 PM PDT 24
Peak memory 204024 kb
Host smart-3b5b0dfb-26fa-4fc3-867c-0962b3275805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10536
67001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.1053667001
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.3294122958
Short name T754
Test name
Test status
Simulation time 8406096215 ps
CPU time 7.95 seconds
Started Apr 18 01:17:49 PM PDT 24
Finished Apr 18 01:17:59 PM PDT 24
Peak memory 203940 kb
Host smart-f1efb36e-dcca-4831-b2c9-ea6338fe68ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32941
22958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.3294122958
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.4086617196
Short name T350
Test name
Test status
Simulation time 8376500721 ps
CPU time 8.04 seconds
Started Apr 18 01:17:50 PM PDT 24
Finished Apr 18 01:17:59 PM PDT 24
Peak memory 204008 kb
Host smart-790a60cd-9892-4efe-b0be-40c1b95241f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40866
17196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.4086617196
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.3923685150
Short name T575
Test name
Test status
Simulation time 37929869 ps
CPU time 0.66 seconds
Started Apr 18 01:17:42 PM PDT 24
Finished Apr 18 01:17:43 PM PDT 24
Peak memory 203892 kb
Host smart-77492bb8-eabf-412e-a53f-a88d73b15ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39236
85150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.3923685150
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.1109701972
Short name T1211
Test name
Test status
Simulation time 22736555378 ps
CPU time 41.86 seconds
Started Apr 18 01:17:42 PM PDT 24
Finished Apr 18 01:18:25 PM PDT 24
Peak memory 204192 kb
Host smart-a07c9c6e-ffb1-4d08-be51-e8467601cf21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11097
01972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.1109701972
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.3621732257
Short name T1237
Test name
Test status
Simulation time 8378167120 ps
CPU time 7.88 seconds
Started Apr 18 01:17:49 PM PDT 24
Finished Apr 18 01:17:58 PM PDT 24
Peak memory 204024 kb
Host smart-db901041-14fa-4e09-9dee-432d12c111c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36217
32257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.3621732257
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.2344410485
Short name T298
Test name
Test status
Simulation time 8499986167 ps
CPU time 7.76 seconds
Started Apr 18 01:17:42 PM PDT 24
Finished Apr 18 01:17:51 PM PDT 24
Peak memory 203944 kb
Host smart-f5367cb2-5440-493c-95a2-82c65806f8f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23444
10485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.2344410485
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.1103422085
Short name T932
Test name
Test status
Simulation time 8422417973 ps
CPU time 7.96 seconds
Started Apr 18 01:17:48 PM PDT 24
Finished Apr 18 01:17:57 PM PDT 24
Peak memory 203944 kb
Host smart-0258dcfb-fce8-4b9a-a117-6aea160fa1bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11034
22085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.1103422085
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.376454873
Short name T157
Test name
Test status
Simulation time 8382244675 ps
CPU time 8.06 seconds
Started Apr 18 01:17:50 PM PDT 24
Finished Apr 18 01:17:59 PM PDT 24
Peak memory 204040 kb
Host smart-2b542c83-b88e-41b8-ad8c-8952b77ac950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37645
4873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.376454873
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.1226172036
Short name T470
Test name
Test status
Simulation time 8361597073 ps
CPU time 7.83 seconds
Started Apr 18 01:17:41 PM PDT 24
Finished Apr 18 01:17:49 PM PDT 24
Peak memory 204016 kb
Host smart-36118ad6-d2c1-4e3d-a63f-dbf0140972e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12261
72036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.1226172036
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.3826962800
Short name T1056
Test name
Test status
Simulation time 8424256097 ps
CPU time 9.75 seconds
Started Apr 18 01:17:44 PM PDT 24
Finished Apr 18 01:17:54 PM PDT 24
Peak memory 204028 kb
Host smart-499dbf5c-7f6c-4269-bcbf-4cf5ec0aadde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38269
62800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.3826962800
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.822979199
Short name T33
Test name
Test status
Simulation time 8387489726 ps
CPU time 8.1 seconds
Started Apr 18 01:17:50 PM PDT 24
Finished Apr 18 01:17:59 PM PDT 24
Peak memory 204012 kb
Host smart-626864df-5aa2-4242-9fff-ca68187a0b8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82297
9199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.822979199
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.1223331152
Short name T345
Test name
Test status
Simulation time 8388337079 ps
CPU time 9.39 seconds
Started Apr 18 01:17:49 PM PDT 24
Finished Apr 18 01:18:00 PM PDT 24
Peak memory 204008 kb
Host smart-a70014b3-9067-468a-abd0-7f4ff2f4d449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12233
31152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.1223331152
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.1187954832
Short name T1348
Test name
Test status
Simulation time 8502785138 ps
CPU time 8.65 seconds
Started Apr 18 01:17:48 PM PDT 24
Finished Apr 18 01:17:58 PM PDT 24
Peak memory 203928 kb
Host smart-30e2f9ba-175c-422d-b34e-14fcc0560d86
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1187954832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.1187954832
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.1221779920
Short name T666
Test name
Test status
Simulation time 8406428309 ps
CPU time 9.25 seconds
Started Apr 18 01:17:48 PM PDT 24
Finished Apr 18 01:17:58 PM PDT 24
Peak memory 203984 kb
Host smart-85f83a69-5559-413b-ac54-567fa4e3bfbe
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1221779920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.1221779920
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.3898471623
Short name T463
Test name
Test status
Simulation time 8428788392 ps
CPU time 10.03 seconds
Started Apr 18 01:17:54 PM PDT 24
Finished Apr 18 01:18:05 PM PDT 24
Peak memory 204024 kb
Host smart-c3c06f90-ba60-4d16-b9ff-c57122b0f191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38984
71623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.3898471623
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.1907752544
Short name T857
Test name
Test status
Simulation time 8399002380 ps
CPU time 7.8 seconds
Started Apr 18 01:17:48 PM PDT 24
Finished Apr 18 01:17:57 PM PDT 24
Peak memory 204032 kb
Host smart-873c86fb-5957-4c8a-8eab-a11df97b0ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19077
52544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.1907752544
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_enable.244064628
Short name T866
Test name
Test status
Simulation time 8418316863 ps
CPU time 9.6 seconds
Started Apr 18 01:17:51 PM PDT 24
Finished Apr 18 01:18:01 PM PDT 24
Peak memory 204052 kb
Host smart-95a638a8-ff94-4399-a72d-847ccf78d958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24406
4628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.244064628
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.3471559683
Short name T933
Test name
Test status
Simulation time 196816896 ps
CPU time 1.57 seconds
Started Apr 18 01:17:48 PM PDT 24
Finished Apr 18 01:17:50 PM PDT 24
Peak memory 204064 kb
Host smart-acf0c773-fd4b-43cd-a10f-a1fd0a6de8bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34715
59683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.3471559683
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.1030629687
Short name T621
Test name
Test status
Simulation time 8412207034 ps
CPU time 7.85 seconds
Started Apr 18 01:17:49 PM PDT 24
Finished Apr 18 01:17:58 PM PDT 24
Peak memory 204028 kb
Host smart-dcbf8cfb-0489-47b4-a7fb-82d56041a43b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10306
29687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.1030629687
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.4130174030
Short name T1188
Test name
Test status
Simulation time 8407181788 ps
CPU time 7.79 seconds
Started Apr 18 01:17:53 PM PDT 24
Finished Apr 18 01:18:02 PM PDT 24
Peak memory 203988 kb
Host smart-541fc5c0-43b5-48d2-96f4-6fa5f8358aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41301
74030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.4130174030
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.4128580940
Short name T665
Test name
Test status
Simulation time 8409759361 ps
CPU time 7.63 seconds
Started Apr 18 01:17:51 PM PDT 24
Finished Apr 18 01:17:59 PM PDT 24
Peak memory 204004 kb
Host smart-29b7e2b9-1875-43c7-be80-4c7c7de8b1d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41285
80940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.4128580940
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.1958514582
Short name T396
Test name
Test status
Simulation time 8414259732 ps
CPU time 7.63 seconds
Started Apr 18 01:17:49 PM PDT 24
Finished Apr 18 01:17:58 PM PDT 24
Peak memory 203912 kb
Host smart-37d2efbf-4351-40d3-aa92-5a80edc47b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19585
14582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.1958514582
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.686798948
Short name T599
Test name
Test status
Simulation time 8382048247 ps
CPU time 9.14 seconds
Started Apr 18 01:17:48 PM PDT 24
Finished Apr 18 01:17:58 PM PDT 24
Peak memory 204032 kb
Host smart-3ea61c8e-9f38-4629-9238-d707e17ae6cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68679
8948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.686798948
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.830238433
Short name T1271
Test name
Test status
Simulation time 8464417554 ps
CPU time 8.67 seconds
Started Apr 18 01:17:46 PM PDT 24
Finished Apr 18 01:17:56 PM PDT 24
Peak memory 204004 kb
Host smart-56864ebd-8c08-4178-bd20-b2c320718e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83023
8433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.830238433
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.2741621788
Short name T620
Test name
Test status
Simulation time 8399987006 ps
CPU time 7.5 seconds
Started Apr 18 01:17:49 PM PDT 24
Finished Apr 18 01:17:58 PM PDT 24
Peak memory 204044 kb
Host smart-96bff629-15c1-4949-b060-f8644f0861d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27416
21788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.2741621788
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.386674091
Short name T287
Test name
Test status
Simulation time 8399196864 ps
CPU time 10.1 seconds
Started Apr 18 01:17:47 PM PDT 24
Finished Apr 18 01:17:58 PM PDT 24
Peak memory 203868 kb
Host smart-4cd9d277-4921-428a-82b3-a6154be58c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38667
4091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.386674091
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.3642314108
Short name T824
Test name
Test status
Simulation time 8379008150 ps
CPU time 7.67 seconds
Started Apr 18 01:17:51 PM PDT 24
Finished Apr 18 01:17:59 PM PDT 24
Peak memory 203992 kb
Host smart-1aad2e3a-dc6c-4686-9760-c202cc44bd04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36423
14108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.3642314108
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.2331952970
Short name T23
Test name
Test status
Simulation time 8372734828 ps
CPU time 8.65 seconds
Started Apr 18 01:17:50 PM PDT 24
Finished Apr 18 01:18:00 PM PDT 24
Peak memory 204036 kb
Host smart-b59b6cf2-a2c8-4118-af16-a389c59e8480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23319
52970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.2331952970
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.124884300
Short name T333
Test name
Test status
Simulation time 50061445 ps
CPU time 0.65 seconds
Started Apr 18 01:17:52 PM PDT 24
Finished Apr 18 01:17:53 PM PDT 24
Peak memory 203952 kb
Host smart-3ec6551e-8ccd-42d1-ad92-a580ffcf6a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12488
4300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.124884300
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.1664820214
Short name T936
Test name
Test status
Simulation time 21210339213 ps
CPU time 36.43 seconds
Started Apr 18 01:17:51 PM PDT 24
Finished Apr 18 01:18:28 PM PDT 24
Peak memory 204292 kb
Host smart-1378a9a5-e527-4d6e-bb6b-e722f7d1435e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16648
20214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.1664820214
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3393583688
Short name T80
Test name
Test status
Simulation time 8453465003 ps
CPU time 7.77 seconds
Started Apr 18 01:17:49 PM PDT 24
Finished Apr 18 01:17:58 PM PDT 24
Peak memory 204028 kb
Host smart-e305eb97-a17c-4d12-a081-9db632cf636a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33935
83688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3393583688
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.342527289
Short name T1063
Test name
Test status
Simulation time 8444080632 ps
CPU time 9.1 seconds
Started Apr 18 01:17:49 PM PDT 24
Finished Apr 18 01:17:59 PM PDT 24
Peak memory 203912 kb
Host smart-e1d1a4b9-8614-48d9-a5c2-df98c9ef5a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34252
7289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.342527289
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.1193632015
Short name T693
Test name
Test status
Simulation time 8390082361 ps
CPU time 8.03 seconds
Started Apr 18 01:17:49 PM PDT 24
Finished Apr 18 01:17:58 PM PDT 24
Peak memory 204036 kb
Host smart-7d0f2207-b842-45aa-b8ec-e3ce7b321c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11936
32015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.1193632015
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.1667754190
Short name T1247
Test name
Test status
Simulation time 8376533980 ps
CPU time 9.47 seconds
Started Apr 18 01:17:49 PM PDT 24
Finished Apr 18 01:18:00 PM PDT 24
Peak memory 204024 kb
Host smart-b78ff1e9-1c1a-4abf-829a-f38c9b53f2db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16677
54190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.1667754190
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.4015428584
Short name T1131
Test name
Test status
Simulation time 8367571770 ps
CPU time 7.94 seconds
Started Apr 18 01:17:46 PM PDT 24
Finished Apr 18 01:17:55 PM PDT 24
Peak memory 204012 kb
Host smart-df8a8e91-e26e-47a0-9591-bf8992222a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40154
28584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.4015428584
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.2129418168
Short name T1006
Test name
Test status
Simulation time 8435276362 ps
CPU time 8.34 seconds
Started Apr 18 01:17:47 PM PDT 24
Finished Apr 18 01:17:56 PM PDT 24
Peak memory 203988 kb
Host smart-0d5c46bf-c50e-43f5-8d4e-912456792100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21294
18168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.2129418168
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.2441910150
Short name T759
Test name
Test status
Simulation time 8375385314 ps
CPU time 8.43 seconds
Started Apr 18 01:17:48 PM PDT 24
Finished Apr 18 01:17:57 PM PDT 24
Peak memory 203976 kb
Host smart-aaee95d7-6b33-487c-a2cd-81dba9ae67f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24419
10150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.2441910150
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.824319287
Short name T1379
Test name
Test status
Simulation time 8431280194 ps
CPU time 8 seconds
Started Apr 18 01:17:52 PM PDT 24
Finished Apr 18 01:18:01 PM PDT 24
Peak memory 204008 kb
Host smart-40d6f68c-1d6e-4b58-a825-8bbcc8f6feb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82431
9287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.824319287
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.3291127869
Short name T1104
Test name
Test status
Simulation time 8469254215 ps
CPU time 9.81 seconds
Started Apr 18 01:14:13 PM PDT 24
Finished Apr 18 01:14:24 PM PDT 24
Peak memory 204036 kb
Host smart-d23aefca-1d58-434a-b294-ccef59516f9b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3291127869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.3291127869
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.3921535858
Short name T627
Test name
Test status
Simulation time 8384214560 ps
CPU time 8.02 seconds
Started Apr 18 01:14:11 PM PDT 24
Finished Apr 18 01:14:21 PM PDT 24
Peak memory 203992 kb
Host smart-738eec11-9713-4a62-a31f-45cc37bca9e4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3921535858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.3921535858
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.644859570
Short name T1204
Test name
Test status
Simulation time 8388878336 ps
CPU time 8.61 seconds
Started Apr 18 01:14:14 PM PDT 24
Finished Apr 18 01:14:23 PM PDT 24
Peak memory 204020 kb
Host smart-299f0e2f-4651-4ad9-a820-380f2a316c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64485
9570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.644859570
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.973754441
Short name T1112
Test name
Test status
Simulation time 8395034594 ps
CPU time 9.21 seconds
Started Apr 18 01:14:07 PM PDT 24
Finished Apr 18 01:14:17 PM PDT 24
Peak memory 203632 kb
Host smart-4ae235bd-61dc-44f1-980b-04cbf1614db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97375
4441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.973754441
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_enable.1431973720
Short name T805
Test name
Test status
Simulation time 8374680066 ps
CPU time 7.84 seconds
Started Apr 18 01:14:07 PM PDT 24
Finished Apr 18 01:14:16 PM PDT 24
Peak memory 203600 kb
Host smart-daf4f73b-17a0-47d7-83fe-cc12b6a3c26e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14319
73720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.1431973720
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.3599589402
Short name T426
Test name
Test status
Simulation time 267752430 ps
CPU time 2.07 seconds
Started Apr 18 01:14:06 PM PDT 24
Finished Apr 18 01:14:08 PM PDT 24
Peak memory 204036 kb
Host smart-91405ad3-f569-40a0-8433-1509686cddde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35995
89402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.3599589402
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.1846699377
Short name T539
Test name
Test status
Simulation time 8432451695 ps
CPU time 8.01 seconds
Started Apr 18 01:14:15 PM PDT 24
Finished Apr 18 01:14:24 PM PDT 24
Peak memory 204040 kb
Host smart-d083c854-9673-47f1-9679-3fe91607a8c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18466
99377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.1846699377
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.2326114432
Short name T724
Test name
Test status
Simulation time 8413472401 ps
CPU time 8.83 seconds
Started Apr 18 01:14:09 PM PDT 24
Finished Apr 18 01:14:19 PM PDT 24
Peak memory 204044 kb
Host smart-5b23c01e-8069-410a-84b7-4a8de3f62c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23261
14432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.2326114432
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.2905079398
Short name T398
Test name
Test status
Simulation time 8446959889 ps
CPU time 7.83 seconds
Started Apr 18 01:14:06 PM PDT 24
Finished Apr 18 01:14:14 PM PDT 24
Peak memory 204048 kb
Host smart-f0588a3c-e057-4015-b846-ec57f9f50494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29050
79398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.2905079398
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.238394274
Short name T296
Test name
Test status
Simulation time 8399874157 ps
CPU time 10.2 seconds
Started Apr 18 01:14:15 PM PDT 24
Finished Apr 18 01:14:26 PM PDT 24
Peak memory 203996 kb
Host smart-0547370b-8267-4981-9fef-aa8515108e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23839
4274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.238394274
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.3804871803
Short name T1258
Test name
Test status
Simulation time 8422429449 ps
CPU time 7.97 seconds
Started Apr 18 01:14:12 PM PDT 24
Finished Apr 18 01:14:21 PM PDT 24
Peak memory 203976 kb
Host smart-a6c2bdec-35b6-4f37-9e65-e7539ae6578a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38048
71803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.3804871803
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.917998104
Short name T956
Test name
Test status
Simulation time 8409586790 ps
CPU time 8.79 seconds
Started Apr 18 01:14:13 PM PDT 24
Finished Apr 18 01:14:22 PM PDT 24
Peak memory 204044 kb
Host smart-28206de8-589d-45b5-92e6-a09ac5fceab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91799
8104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.917998104
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.743497831
Short name T923
Test name
Test status
Simulation time 8383924015 ps
CPU time 8.16 seconds
Started Apr 18 01:14:12 PM PDT 24
Finished Apr 18 01:14:21 PM PDT 24
Peak memory 203936 kb
Host smart-081fae5b-4c59-4ba6-a5f4-141b445cac57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74349
7831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.743497831
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.3475754122
Short name T176
Test name
Test status
Simulation time 8401557480 ps
CPU time 10.52 seconds
Started Apr 18 01:14:12 PM PDT 24
Finished Apr 18 01:14:23 PM PDT 24
Peak memory 203920 kb
Host smart-9fe11632-2488-44f2-b031-5a709ea3fa23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34757
54122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.3475754122
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.2964579367
Short name T406
Test name
Test status
Simulation time 8377374455 ps
CPU time 7.91 seconds
Started Apr 18 01:14:15 PM PDT 24
Finished Apr 18 01:14:23 PM PDT 24
Peak memory 203908 kb
Host smart-24075379-0657-4a67-827e-dc5fe1041515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29645
79367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.2964579367
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.2508894182
Short name T720
Test name
Test status
Simulation time 36206476 ps
CPU time 0.64 seconds
Started Apr 18 01:14:15 PM PDT 24
Finished Apr 18 01:14:16 PM PDT 24
Peak memory 203784 kb
Host smart-0e243a8b-0c0b-4c68-8557-ecd7b6867bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25088
94182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.2508894182
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.2973519604
Short name T1126
Test name
Test status
Simulation time 24014047088 ps
CPU time 41.69 seconds
Started Apr 18 01:14:15 PM PDT 24
Finished Apr 18 01:14:57 PM PDT 24
Peak memory 204328 kb
Host smart-bde3a60b-a6ba-46ab-a15e-f59400ec1b74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29735
19604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.2973519604
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.3720647843
Short name T576
Test name
Test status
Simulation time 8387442845 ps
CPU time 7.52 seconds
Started Apr 18 01:14:12 PM PDT 24
Finished Apr 18 01:14:21 PM PDT 24
Peak memory 204040 kb
Host smart-6617c550-b329-40ed-ae60-fa2917b930cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37206
47843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.3720647843
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.2480585313
Short name T139
Test name
Test status
Simulation time 8440775701 ps
CPU time 8.53 seconds
Started Apr 18 01:14:11 PM PDT 24
Finished Apr 18 01:14:21 PM PDT 24
Peak memory 204036 kb
Host smart-d3e00b42-1301-4e9b-af0f-a537384c9c25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24805
85313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.2480585313
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.2456147222
Short name T742
Test name
Test status
Simulation time 8416155790 ps
CPU time 7.71 seconds
Started Apr 18 01:14:13 PM PDT 24
Finished Apr 18 01:14:21 PM PDT 24
Peak memory 204008 kb
Host smart-fd500f85-8c85-43f1-9acb-57a15054ae5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24561
47222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.2456147222
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.162007930
Short name T702
Test name
Test status
Simulation time 8370270265 ps
CPU time 8.38 seconds
Started Apr 18 01:14:20 PM PDT 24
Finished Apr 18 01:14:29 PM PDT 24
Peak memory 204024 kb
Host smart-a3cc9a4e-07a9-4db9-aba9-c605471b4e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16200
7930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.162007930
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3999450593
Short name T734
Test name
Test status
Simulation time 8376574126 ps
CPU time 7.99 seconds
Started Apr 18 01:14:11 PM PDT 24
Finished Apr 18 01:14:20 PM PDT 24
Peak memory 203956 kb
Host smart-0fe831fa-8aa9-4d75-b445-ef99577d10b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39994
50593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3999450593
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.2892724183
Short name T831
Test name
Test status
Simulation time 8451016488 ps
CPU time 8.18 seconds
Started Apr 18 01:14:04 PM PDT 24
Finished Apr 18 01:14:13 PM PDT 24
Peak memory 203964 kb
Host smart-c6f984b2-457c-42e0-88ad-0230492b2c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28927
24183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2892724183
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.1087429879
Short name T882
Test name
Test status
Simulation time 8418274644 ps
CPU time 8.95 seconds
Started Apr 18 01:14:12 PM PDT 24
Finished Apr 18 01:14:22 PM PDT 24
Peak memory 204008 kb
Host smart-e44b9061-1701-4175-86c4-711817284d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10874
29879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.1087429879
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.2651745573
Short name T390
Test name
Test status
Simulation time 8402455814 ps
CPU time 10.4 seconds
Started Apr 18 01:14:14 PM PDT 24
Finished Apr 18 01:14:25 PM PDT 24
Peak memory 203928 kb
Host smart-c3d81c14-1692-4197-b22f-4efb781593f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26517
45573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.2651745573
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.2818796949
Short name T568
Test name
Test status
Simulation time 8480167677 ps
CPU time 8.13 seconds
Started Apr 18 01:14:19 PM PDT 24
Finished Apr 18 01:14:28 PM PDT 24
Peak memory 204032 kb
Host smart-770bb5ab-74fa-4021-b57b-458ad0638664
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2818796949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.2818796949
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.3791234110
Short name T38
Test name
Test status
Simulation time 8373575542 ps
CPU time 8.1 seconds
Started Apr 18 01:14:19 PM PDT 24
Finished Apr 18 01:14:28 PM PDT 24
Peak memory 204004 kb
Host smart-4980cd49-ae91-4f9e-8340-d28410c453af
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3791234110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.3791234110
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.3218988906
Short name T630
Test name
Test status
Simulation time 8459155352 ps
CPU time 9.86 seconds
Started Apr 18 01:14:19 PM PDT 24
Finished Apr 18 01:14:29 PM PDT 24
Peak memory 204016 kb
Host smart-ddc56138-6ed3-4f58-be1c-9d7cb3813c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32189
88906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.3218988906
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.124353715
Short name T304
Test name
Test status
Simulation time 8383332744 ps
CPU time 7.53 seconds
Started Apr 18 01:14:13 PM PDT 24
Finished Apr 18 01:14:21 PM PDT 24
Peak memory 204036 kb
Host smart-6c28845c-c062-4b4d-a869-737eaa5bb69b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12435
3715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.124353715
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_enable.2313953855
Short name T1102
Test name
Test status
Simulation time 8397203900 ps
CPU time 7.57 seconds
Started Apr 18 01:14:15 PM PDT 24
Finished Apr 18 01:14:23 PM PDT 24
Peak memory 204028 kb
Host smart-50ae1156-1c2f-45b9-92a9-7e72f67a2e27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23139
53855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.2313953855
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.527169775
Short name T608
Test name
Test status
Simulation time 242808135 ps
CPU time 1.96 seconds
Started Apr 18 01:14:59 PM PDT 24
Finished Apr 18 01:15:01 PM PDT 24
Peak memory 204100 kb
Host smart-4e3be775-8752-46b4-91d1-0eb13c3ae568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52716
9775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.527169775
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.4178342747
Short name T1072
Test name
Test status
Simulation time 8451896190 ps
CPU time 8.63 seconds
Started Apr 18 01:14:21 PM PDT 24
Finished Apr 18 01:14:30 PM PDT 24
Peak memory 204000 kb
Host smart-cb949115-ed17-41fd-95b6-5e2f96b614f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41783
42747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.4178342747
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.3694205209
Short name T1338
Test name
Test status
Simulation time 8395651135 ps
CPU time 8.03 seconds
Started Apr 18 01:14:24 PM PDT 24
Finished Apr 18 01:14:33 PM PDT 24
Peak memory 204024 kb
Host smart-2c4373a8-1143-4f8b-9025-7197f1931959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36942
05209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.3694205209
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2296278364
Short name T618
Test name
Test status
Simulation time 8477938299 ps
CPU time 8.62 seconds
Started Apr 18 01:14:14 PM PDT 24
Finished Apr 18 01:14:23 PM PDT 24
Peak memory 204012 kb
Host smart-8c5a9207-fb12-43f5-9287-03b424f72d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22962
78364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2296278364
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.3404397863
Short name T1022
Test name
Test status
Simulation time 8422535946 ps
CPU time 9.73 seconds
Started Apr 18 01:14:13 PM PDT 24
Finished Apr 18 01:14:24 PM PDT 24
Peak memory 204040 kb
Host smart-9685f34f-7e6e-4bde-9dda-166be2f0e8cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34043
97863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.3404397863
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.2979217121
Short name T417
Test name
Test status
Simulation time 8369944442 ps
CPU time 7.77 seconds
Started Apr 18 01:14:11 PM PDT 24
Finished Apr 18 01:14:20 PM PDT 24
Peak memory 204044 kb
Host smart-9051206c-b800-4a5c-901a-81067ca13b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29792
17121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.2979217121
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3416991361
Short name T115
Test name
Test status
Simulation time 8500031209 ps
CPU time 7.85 seconds
Started Apr 18 01:14:11 PM PDT 24
Finished Apr 18 01:14:20 PM PDT 24
Peak memory 203948 kb
Host smart-68aa5e07-50bd-41cf-960d-91bdc1c3ae03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34169
91361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3416991361
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.4080084570
Short name T967
Test name
Test status
Simulation time 8386562618 ps
CPU time 7.87 seconds
Started Apr 18 01:14:12 PM PDT 24
Finished Apr 18 01:14:21 PM PDT 24
Peak memory 204040 kb
Host smart-c7aca234-b95c-4936-991a-848cbb9370f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40800
84570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.4080084570
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.3667419160
Short name T385
Test name
Test status
Simulation time 8403861167 ps
CPU time 7.96 seconds
Started Apr 18 01:14:13 PM PDT 24
Finished Apr 18 01:14:22 PM PDT 24
Peak memory 204032 kb
Host smart-b473f91e-2221-468f-9f4e-aa23b4cf85db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36674
19160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.3667419160
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.835089617
Short name T22
Test name
Test status
Simulation time 8395132819 ps
CPU time 9.63 seconds
Started Apr 18 01:14:20 PM PDT 24
Finished Apr 18 01:14:30 PM PDT 24
Peak memory 204044 kb
Host smart-67b1d02c-9928-410a-9bce-1c586ae8839e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83508
9617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.835089617
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.4065341926
Short name T1265
Test name
Test status
Simulation time 8399871578 ps
CPU time 10.15 seconds
Started Apr 18 01:14:21 PM PDT 24
Finished Apr 18 01:14:32 PM PDT 24
Peak memory 203928 kb
Host smart-bdd2e2f5-d45d-4828-9a14-b93477d9e399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40653
41926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.4065341926
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.2512930914
Short name T43
Test name
Test status
Simulation time 36509814 ps
CPU time 0.65 seconds
Started Apr 18 01:14:18 PM PDT 24
Finished Apr 18 01:14:19 PM PDT 24
Peak memory 203740 kb
Host smart-78b961b2-95e6-4a75-8cd2-07f3de8b3c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25129
30914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.2512930914
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1889853975
Short name T437
Test name
Test status
Simulation time 19193877971 ps
CPU time 37.52 seconds
Started Apr 18 01:14:11 PM PDT 24
Finished Apr 18 01:14:49 PM PDT 24
Peak memory 204360 kb
Host smart-0d05ae94-849e-455c-bbd1-41926b579f7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18898
53975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1889853975
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.3622340821
Short name T1195
Test name
Test status
Simulation time 8395407017 ps
CPU time 7.76 seconds
Started Apr 18 01:14:12 PM PDT 24
Finished Apr 18 01:14:21 PM PDT 24
Peak memory 204036 kb
Host smart-93c382ff-d0fa-4b29-abd2-97f2c38655d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36223
40821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.3622340821
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.4224760085
Short name T292
Test name
Test status
Simulation time 8438023881 ps
CPU time 8.44 seconds
Started Apr 18 01:14:15 PM PDT 24
Finished Apr 18 01:14:24 PM PDT 24
Peak memory 204028 kb
Host smart-09c5c2b3-9fdf-4ad4-ae57-4d421edb970a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42247
60085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.4224760085
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.2401344938
Short name T799
Test name
Test status
Simulation time 8375807264 ps
CPU time 7.6 seconds
Started Apr 18 01:14:12 PM PDT 24
Finished Apr 18 01:14:20 PM PDT 24
Peak memory 204016 kb
Host smart-d3de6edd-117c-4d2c-9e15-fbfc6b6b3553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24013
44938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.2401344938
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.1936379077
Short name T150
Test name
Test status
Simulation time 8404430162 ps
CPU time 9.99 seconds
Started Apr 18 01:14:20 PM PDT 24
Finished Apr 18 01:14:30 PM PDT 24
Peak memory 204000 kb
Host smart-c7bef267-e5a1-4009-afaf-dfa9b5d81cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19363
79077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.1936379077
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.2450660021
Short name T379
Test name
Test status
Simulation time 8372001585 ps
CPU time 7.95 seconds
Started Apr 18 01:14:19 PM PDT 24
Finished Apr 18 01:14:28 PM PDT 24
Peak memory 204036 kb
Host smart-3031868b-89a6-4bbb-8909-f5f32b5f5982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24506
60021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.2450660021
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.1806916652
Short name T837
Test name
Test status
Simulation time 8434230507 ps
CPU time 8.2 seconds
Started Apr 18 01:14:22 PM PDT 24
Finished Apr 18 01:14:31 PM PDT 24
Peak memory 204028 kb
Host smart-3421c5a1-95ca-425d-8e97-338aa2d9b03a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18069
16652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1806916652
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.3955692317
Short name T533
Test name
Test status
Simulation time 8443541889 ps
CPU time 8.25 seconds
Started Apr 18 01:14:20 PM PDT 24
Finished Apr 18 01:14:28 PM PDT 24
Peak memory 204044 kb
Host smart-a2f6a744-91cb-435b-910a-8f3d74cbad4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39556
92317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.3955692317
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.1616290359
Short name T1309
Test name
Test status
Simulation time 8500762763 ps
CPU time 8.12 seconds
Started Apr 18 01:14:12 PM PDT 24
Finished Apr 18 01:14:22 PM PDT 24
Peak memory 204020 kb
Host smart-f1b03a88-a07d-45a0-be5c-2bec6d75cfc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16162
90359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.1616290359
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.3803291458
Short name T1168
Test name
Test status
Simulation time 8465821842 ps
CPU time 8.13 seconds
Started Apr 18 01:14:33 PM PDT 24
Finished Apr 18 01:14:42 PM PDT 24
Peak memory 204076 kb
Host smart-6a7f4aa1-14f8-4f2b-b696-4c7b44eb9005
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3803291458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.3803291458
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.2405884228
Short name T897
Test name
Test status
Simulation time 8432262091 ps
CPU time 9.13 seconds
Started Apr 18 01:15:29 PM PDT 24
Finished Apr 18 01:15:39 PM PDT 24
Peak memory 204004 kb
Host smart-51a4411f-eb50-4610-9d56-ecf8fa9a2ddd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2405884228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.2405884228
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.702467169
Short name T1327
Test name
Test status
Simulation time 8439279085 ps
CPU time 7.65 seconds
Started Apr 18 01:14:25 PM PDT 24
Finished Apr 18 01:14:33 PM PDT 24
Peak memory 204040 kb
Host smart-40bcb713-fb3b-451c-bb89-1a96a6fb4d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70246
7169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.702467169
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.3356037248
Short name T829
Test name
Test status
Simulation time 8378138764 ps
CPU time 10.25 seconds
Started Apr 18 01:14:19 PM PDT 24
Finished Apr 18 01:14:30 PM PDT 24
Peak memory 204028 kb
Host smart-c7cb521e-1488-4b20-a120-ac2287ecfe0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33560
37248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.3356037248
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_enable.1829093306
Short name T777
Test name
Test status
Simulation time 8383531446 ps
CPU time 8.73 seconds
Started Apr 18 01:14:19 PM PDT 24
Finished Apr 18 01:14:29 PM PDT 24
Peak memory 204048 kb
Host smart-bf90582e-56e1-44e2-9414-92da220e485a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18290
93306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.1829093306
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1940591036
Short name T765
Test name
Test status
Simulation time 149672366 ps
CPU time 1.66 seconds
Started Apr 18 01:14:20 PM PDT 24
Finished Apr 18 01:14:22 PM PDT 24
Peak memory 204164 kb
Host smart-e614bdbe-e28b-4b61-aacc-57969bc843e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19405
91036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1940591036
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.2491635580
Short name T381
Test name
Test status
Simulation time 8417212672 ps
CPU time 7.56 seconds
Started Apr 18 01:14:30 PM PDT 24
Finished Apr 18 01:14:39 PM PDT 24
Peak memory 204020 kb
Host smart-f648a551-9a80-44d8-b64f-01fe16a54b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24916
35580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.2491635580
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.806837960
Short name T1278
Test name
Test status
Simulation time 8394847328 ps
CPU time 7.62 seconds
Started Apr 18 01:14:27 PM PDT 24
Finished Apr 18 01:14:36 PM PDT 24
Peak memory 203968 kb
Host smart-c99b6c9b-353c-4f72-b4d6-6bb574c0f99d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80683
7960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.806837960
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.2379179802
Short name T40
Test name
Test status
Simulation time 8410324754 ps
CPU time 7.99 seconds
Started Apr 18 01:14:19 PM PDT 24
Finished Apr 18 01:14:28 PM PDT 24
Peak memory 204044 kb
Host smart-95de6432-24cb-40eb-88a3-5f8a3618a9ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23791
79802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2379179802
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.544343172
Short name T1116
Test name
Test status
Simulation time 8433047121 ps
CPU time 7.63 seconds
Started Apr 18 01:14:20 PM PDT 24
Finished Apr 18 01:14:28 PM PDT 24
Peak memory 204028 kb
Host smart-301378d4-3e0c-490e-8c69-d94a44301c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54434
3172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.544343172
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2483526536
Short name T755
Test name
Test status
Simulation time 8382218412 ps
CPU time 9.63 seconds
Started Apr 18 01:14:17 PM PDT 24
Finished Apr 18 01:14:27 PM PDT 24
Peak memory 203940 kb
Host smart-1c7523ee-4238-438e-9248-fd105849a700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24835
26536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2483526536
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.4056622226
Short name T100
Test name
Test status
Simulation time 8418933026 ps
CPU time 7.6 seconds
Started Apr 18 01:14:20 PM PDT 24
Finished Apr 18 01:14:28 PM PDT 24
Peak memory 203976 kb
Host smart-ac34922a-96f9-4459-93f9-54ef66091469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40566
22226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.4056622226
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.3240599797
Short name T1037
Test name
Test status
Simulation time 8383782910 ps
CPU time 7.83 seconds
Started Apr 18 01:14:25 PM PDT 24
Finished Apr 18 01:14:34 PM PDT 24
Peak memory 204044 kb
Host smart-df6828b2-ac7b-4bfa-a292-b797cdfa5cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32405
99797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.3240599797
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.1078195543
Short name T418
Test name
Test status
Simulation time 8379466257 ps
CPU time 8.31 seconds
Started Apr 18 01:14:26 PM PDT 24
Finished Apr 18 01:14:35 PM PDT 24
Peak memory 203920 kb
Host smart-f20849dd-168f-4fe5-8149-fe2ecb718389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10781
95543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.1078195543
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.3034220821
Short name T174
Test name
Test status
Simulation time 8383077121 ps
CPU time 7.87 seconds
Started Apr 18 01:14:26 PM PDT 24
Finished Apr 18 01:14:35 PM PDT 24
Peak memory 204060 kb
Host smart-74f0d2a7-ef9b-464f-b81d-de3db4ee1d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30342
20821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.3034220821
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.1714213339
Short name T948
Test name
Test status
Simulation time 53851766 ps
CPU time 0.67 seconds
Started Apr 18 01:14:28 PM PDT 24
Finished Apr 18 01:14:30 PM PDT 24
Peak memory 203896 kb
Host smart-7097e8df-c5bd-4ad9-9480-0a3788bd2ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17142
13339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.1714213339
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.3339286347
Short name T230
Test name
Test status
Simulation time 19219806528 ps
CPU time 35.18 seconds
Started Apr 18 01:14:33 PM PDT 24
Finished Apr 18 01:15:08 PM PDT 24
Peak memory 204292 kb
Host smart-14541018-5ffc-42e3-9fb4-b8db4d10a197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33392
86347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.3339286347
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.564982600
Short name T342
Test name
Test status
Simulation time 8431743303 ps
CPU time 8.04 seconds
Started Apr 18 01:14:27 PM PDT 24
Finished Apr 18 01:14:37 PM PDT 24
Peak memory 204008 kb
Host smart-a075b37e-4ffe-4cac-baf7-1e4184a4624e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56498
2600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.564982600
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.48214431
Short name T982
Test name
Test status
Simulation time 8423973922 ps
CPU time 8.29 seconds
Started Apr 18 01:14:29 PM PDT 24
Finished Apr 18 01:14:38 PM PDT 24
Peak memory 204004 kb
Host smart-bcb15eb5-74d6-4b8c-b7ef-50cbd95b7aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48214
431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.48214431
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.2760725818
Short name T1200
Test name
Test status
Simulation time 8406412998 ps
CPU time 9.19 seconds
Started Apr 18 01:14:27 PM PDT 24
Finished Apr 18 01:14:38 PM PDT 24
Peak memory 204004 kb
Host smart-00b5ec5a-5252-4628-bdba-fc39e8b7279d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27607
25818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.2760725818
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.352526339
Short name T155
Test name
Test status
Simulation time 8377987618 ps
CPU time 7.75 seconds
Started Apr 18 01:14:27 PM PDT 24
Finished Apr 18 01:14:37 PM PDT 24
Peak memory 203940 kb
Host smart-2fe2925e-e019-43fc-9d0d-2212a58876c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35252
6339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.352526339
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.3293553988
Short name T713
Test name
Test status
Simulation time 8380418244 ps
CPU time 9.32 seconds
Started Apr 18 01:14:25 PM PDT 24
Finished Apr 18 01:14:35 PM PDT 24
Peak memory 203868 kb
Host smart-4eaa5053-fe00-49e0-8ffb-39135438e1d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32935
53988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3293553988
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2172301368
Short name T1263
Test name
Test status
Simulation time 8450699419 ps
CPU time 7.91 seconds
Started Apr 18 01:14:21 PM PDT 24
Finished Apr 18 01:14:29 PM PDT 24
Peak memory 203976 kb
Host smart-8cd2139d-2ace-48a2-9bff-b011fd52f41e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21723
01368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2172301368
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.2662067071
Short name T332
Test name
Test status
Simulation time 8381853204 ps
CPU time 7.48 seconds
Started Apr 18 01:14:30 PM PDT 24
Finished Apr 18 01:14:38 PM PDT 24
Peak memory 204016 kb
Host smart-a116fd97-db0b-4872-96c6-46fe1657ffa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26620
67071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.2662067071
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.765729875
Short name T508
Test name
Test status
Simulation time 8400383406 ps
CPU time 8.65 seconds
Started Apr 18 01:14:32 PM PDT 24
Finished Apr 18 01:14:41 PM PDT 24
Peak memory 203996 kb
Host smart-c3ee40cf-c9ef-46cf-9366-d1b68c50096e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76572
9875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.765729875
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.515533068
Short name T383
Test name
Test status
Simulation time 8465504566 ps
CPU time 9.49 seconds
Started Apr 18 01:14:35 PM PDT 24
Finished Apr 18 01:14:45 PM PDT 24
Peak memory 204052 kb
Host smart-f9550029-2a2e-4179-846c-7eff49d8e761
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=515533068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.515533068
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.1045160799
Short name T1150
Test name
Test status
Simulation time 8377394196 ps
CPU time 10.03 seconds
Started Apr 18 01:14:45 PM PDT 24
Finished Apr 18 01:14:55 PM PDT 24
Peak memory 204000 kb
Host smart-ca6b87d3-9e26-4b84-836a-13b4316c8bf6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1045160799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.1045160799
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.1619085971
Short name T121
Test name
Test status
Simulation time 8402981772 ps
CPU time 8.01 seconds
Started Apr 18 01:14:33 PM PDT 24
Finished Apr 18 01:14:41 PM PDT 24
Peak memory 204020 kb
Host smart-8275580d-58b8-427c-a9e2-0c1a3beb65dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16190
85971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.1619085971
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.1594701420
Short name T1280
Test name
Test status
Simulation time 8386032131 ps
CPU time 8.45 seconds
Started Apr 18 01:14:30 PM PDT 24
Finished Apr 18 01:14:40 PM PDT 24
Peak memory 204024 kb
Host smart-ea5fbc60-9d25-4253-a938-753e976cc7bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15947
01420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1594701420
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_enable.2298368886
Short name T703
Test name
Test status
Simulation time 8372773338 ps
CPU time 8.19 seconds
Started Apr 18 01:14:28 PM PDT 24
Finished Apr 18 01:14:37 PM PDT 24
Peak memory 204044 kb
Host smart-1e08c4a8-71c6-4cfe-a2b0-06440003f8f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22983
68886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.2298368886
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.36610237
Short name T788
Test name
Test status
Simulation time 104188032 ps
CPU time 1.81 seconds
Started Apr 18 01:14:26 PM PDT 24
Finished Apr 18 01:14:28 PM PDT 24
Peak memory 204028 kb
Host smart-1d07777f-c7b5-42c4-941b-5785b6e32327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36610
237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.36610237
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.1678864980
Short name T483
Test name
Test status
Simulation time 8388893079 ps
CPU time 7.92 seconds
Started Apr 18 01:14:34 PM PDT 24
Finished Apr 18 01:14:43 PM PDT 24
Peak memory 204080 kb
Host smart-0f498250-a2c2-4ecf-a37c-a2de7a305ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16788
64980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.1678864980
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.3013969183
Short name T192
Test name
Test status
Simulation time 8368793487 ps
CPU time 7.91 seconds
Started Apr 18 01:14:34 PM PDT 24
Finished Apr 18 01:14:43 PM PDT 24
Peak memory 203976 kb
Host smart-9213f958-5b8d-4149-9778-bc894b923bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30139
69183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.3013969183
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.432673112
Short name T729
Test name
Test status
Simulation time 8398814796 ps
CPU time 8.63 seconds
Started Apr 18 01:14:27 PM PDT 24
Finished Apr 18 01:14:36 PM PDT 24
Peak memory 204016 kb
Host smart-695a952b-7783-458b-b423-31d93c95c1be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43267
3112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.432673112
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.1813491949
Short name T920
Test name
Test status
Simulation time 8416734565 ps
CPU time 9.94 seconds
Started Apr 18 01:14:34 PM PDT 24
Finished Apr 18 01:14:44 PM PDT 24
Peak memory 203996 kb
Host smart-63e22216-58b7-4738-b72d-68b745b99bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18134
91949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.1813491949
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.2118025768
Short name T774
Test name
Test status
Simulation time 8380191745 ps
CPU time 8.92 seconds
Started Apr 18 01:14:28 PM PDT 24
Finished Apr 18 01:14:38 PM PDT 24
Peak memory 203980 kb
Host smart-de9832ad-ac95-4edd-acad-a4bf78223359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21180
25768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.2118025768
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.1819776676
Short name T103
Test name
Test status
Simulation time 8488877192 ps
CPU time 9.64 seconds
Started Apr 18 01:14:27 PM PDT 24
Finished Apr 18 01:14:38 PM PDT 24
Peak memory 204004 kb
Host smart-00f7ca2a-23a2-42c4-9fed-1d061dfb871c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18197
76676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.1819776676
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.3456528204
Short name T973
Test name
Test status
Simulation time 8409760989 ps
CPU time 8.03 seconds
Started Apr 18 01:14:27 PM PDT 24
Finished Apr 18 01:14:37 PM PDT 24
Peak memory 204028 kb
Host smart-15233832-7e35-473e-9286-b2ea73fa556d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34565
28204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.3456528204
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3241416284
Short name T834
Test name
Test status
Simulation time 8384544635 ps
CPU time 7.99 seconds
Started Apr 18 01:14:26 PM PDT 24
Finished Apr 18 01:14:34 PM PDT 24
Peak memory 204044 kb
Host smart-a6e6e3c1-dcba-481c-9a83-a273f2c4ffcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32414
16284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3241416284
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.3995524921
Short name T1001
Test name
Test status
Simulation time 8397152229 ps
CPU time 8.25 seconds
Started Apr 18 01:14:33 PM PDT 24
Finished Apr 18 01:14:42 PM PDT 24
Peak memory 203940 kb
Host smart-858c1833-7b18-46bd-8c5f-e0c70c4aa1d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39955
24921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.3995524921
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.2774935774
Short name T870
Test name
Test status
Simulation time 8381249401 ps
CPU time 8.43 seconds
Started Apr 18 01:14:35 PM PDT 24
Finished Apr 18 01:14:44 PM PDT 24
Peak memory 204032 kb
Host smart-43fbd936-e23c-4d60-8c41-28ce6f5498b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27749
35774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.2774935774
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2382024773
Short name T481
Test name
Test status
Simulation time 32490260 ps
CPU time 0.64 seconds
Started Apr 18 01:14:33 PM PDT 24
Finished Apr 18 01:14:34 PM PDT 24
Peak memory 203832 kb
Host smart-07e2a3aa-b5bb-4244-82e3-acdeaaf41d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23820
24773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2382024773
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.3568884659
Short name T219
Test name
Test status
Simulation time 17338911015 ps
CPU time 30.59 seconds
Started Apr 18 01:14:35 PM PDT 24
Finished Apr 18 01:15:07 PM PDT 24
Peak memory 204292 kb
Host smart-fec4b1f7-f7e2-4b0c-951f-7cac7c19e415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35688
84659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.3568884659
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.471714940
Short name T317
Test name
Test status
Simulation time 8410284547 ps
CPU time 9.41 seconds
Started Apr 18 01:14:29 PM PDT 24
Finished Apr 18 01:14:39 PM PDT 24
Peak memory 204044 kb
Host smart-fd6508e1-cb83-4f74-9102-84c01a89d296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47171
4940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.471714940
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.1248802153
Short name T1291
Test name
Test status
Simulation time 8470774498 ps
CPU time 7.83 seconds
Started Apr 18 01:14:27 PM PDT 24
Finished Apr 18 01:14:36 PM PDT 24
Peak memory 204024 kb
Host smart-f6037630-56bf-4910-b27c-c118dce6716b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12488
02153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1248802153
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.728898265
Short name T1244
Test name
Test status
Simulation time 8408269454 ps
CPU time 7.72 seconds
Started Apr 18 01:14:28 PM PDT 24
Finished Apr 18 01:14:37 PM PDT 24
Peak memory 204084 kb
Host smart-eaf3156f-71d7-4053-a649-f4ec44ec22f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72889
8265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.728898265
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.3855383099
Short name T394
Test name
Test status
Simulation time 8374310329 ps
CPU time 9.83 seconds
Started Apr 18 01:14:36 PM PDT 24
Finished Apr 18 01:14:46 PM PDT 24
Peak memory 203980 kb
Host smart-2413c411-6b7e-47cc-ac45-0daaa538e719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38553
83099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.3855383099
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.1384385210
Short name T874
Test name
Test status
Simulation time 8372756202 ps
CPU time 9.89 seconds
Started Apr 18 01:14:35 PM PDT 24
Finished Apr 18 01:14:46 PM PDT 24
Peak memory 204016 kb
Host smart-75421ca2-23e5-4bfb-aad8-5f6255a9667a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13843
85210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.1384385210
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.3392362515
Short name T825
Test name
Test status
Simulation time 8436595037 ps
CPU time 8.5 seconds
Started Apr 18 01:14:28 PM PDT 24
Finished Apr 18 01:14:38 PM PDT 24
Peak memory 204024 kb
Host smart-bae88388-6542-480e-9243-bcb94075fdc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33923
62515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.3392362515
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.2174607239
Short name T919
Test name
Test status
Simulation time 8380235200 ps
CPU time 8.31 seconds
Started Apr 18 01:14:27 PM PDT 24
Finished Apr 18 01:14:36 PM PDT 24
Peak memory 203976 kb
Host smart-825f3a96-3c38-405a-9831-4ace0e387e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21746
07239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.2174607239
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.2563206410
Short name T217
Test name
Test status
Simulation time 8419667652 ps
CPU time 7.78 seconds
Started Apr 18 01:14:28 PM PDT 24
Finished Apr 18 01:14:37 PM PDT 24
Peak memory 204084 kb
Host smart-afd67db8-ab63-4af0-ad76-ee3ed227ed94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25632
06410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2563206410
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.max_length_in_transaction.3315356602
Short name T504
Test name
Test status
Simulation time 8465327612 ps
CPU time 7.98 seconds
Started Apr 18 01:14:42 PM PDT 24
Finished Apr 18 01:14:50 PM PDT 24
Peak memory 204044 kb
Host smart-69df376e-1ff5-48af-8a4f-ab956dd037bb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3315356602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.3315356602
Directory /workspace/9.max_length_in_transaction/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.1480535591
Short name T917
Test name
Test status
Simulation time 8445048007 ps
CPU time 8.69 seconds
Started Apr 18 01:14:39 PM PDT 24
Finished Apr 18 01:14:49 PM PDT 24
Peak memory 204032 kb
Host smart-231840a1-334a-454b-8678-19f847418d1a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1480535591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.1480535591
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.3671089379
Short name T712
Test name
Test status
Simulation time 8391616911 ps
CPU time 7.88 seconds
Started Apr 18 01:14:39 PM PDT 24
Finished Apr 18 01:14:47 PM PDT 24
Peak memory 204024 kb
Host smart-f57fc38d-2393-4b70-aa24-aa8fa6782370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36710
89379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.3671089379
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.3460908808
Short name T347
Test name
Test status
Simulation time 8374760453 ps
CPU time 8.62 seconds
Started Apr 18 01:14:39 PM PDT 24
Finished Apr 18 01:14:48 PM PDT 24
Peak memory 204028 kb
Host smart-e96486e4-9892-4a14-81fe-4e4a14615a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34609
08808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.3460908808
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_enable.796693118
Short name T523
Test name
Test status
Simulation time 8374337113 ps
CPU time 8.05 seconds
Started Apr 18 01:14:37 PM PDT 24
Finished Apr 18 01:14:45 PM PDT 24
Peak memory 204012 kb
Host smart-7f7de146-930b-446e-adba-18239468f7d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79669
3118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.796693118
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.2646000197
Short name T1382
Test name
Test status
Simulation time 41134797 ps
CPU time 0.98 seconds
Started Apr 18 01:14:34 PM PDT 24
Finished Apr 18 01:14:36 PM PDT 24
Peak memory 204036 kb
Host smart-f463d233-2988-449b-9670-fb3536bbbda9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26460
00197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.2646000197
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.2373435783
Short name T934
Test name
Test status
Simulation time 8411462005 ps
CPU time 9.96 seconds
Started Apr 18 01:14:34 PM PDT 24
Finished Apr 18 01:14:44 PM PDT 24
Peak memory 204044 kb
Host smart-1157b4d4-1325-4bc8-9f7c-e6852ed21a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23734
35783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.2373435783
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.3917897045
Short name T1224
Test name
Test status
Simulation time 8369370345 ps
CPU time 7.7 seconds
Started Apr 18 01:14:35 PM PDT 24
Finished Apr 18 01:14:44 PM PDT 24
Peak memory 203992 kb
Host smart-586c7ef8-3765-4cbc-8f76-13a982c10df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39178
97045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.3917897045
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.1721145816
Short name T132
Test name
Test status
Simulation time 8376020058 ps
CPU time 8.36 seconds
Started Apr 18 01:14:36 PM PDT 24
Finished Apr 18 01:14:45 PM PDT 24
Peak memory 203860 kb
Host smart-14a4c379-2fd4-4b69-8ad5-ce8fbb713f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17211
45816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.1721145816
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.1663863148
Short name T1076
Test name
Test status
Simulation time 8411740131 ps
CPU time 8.24 seconds
Started Apr 18 01:14:35 PM PDT 24
Finished Apr 18 01:14:44 PM PDT 24
Peak memory 204000 kb
Host smart-b354fd6d-1852-4239-b70c-8d2225615962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16638
63148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1663863148
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.1987921144
Short name T456
Test name
Test status
Simulation time 8383672985 ps
CPU time 7.83 seconds
Started Apr 18 01:14:33 PM PDT 24
Finished Apr 18 01:14:42 PM PDT 24
Peak memory 204028 kb
Host smart-bc736697-0c86-464a-ac2d-8c9d520024fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19879
21144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.1987921144
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1676750262
Short name T770
Test name
Test status
Simulation time 8460932170 ps
CPU time 8.2 seconds
Started Apr 18 01:14:35 PM PDT 24
Finished Apr 18 01:14:44 PM PDT 24
Peak memory 203964 kb
Host smart-429fc1d6-8af2-4080-a6ab-5932fe64da96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16767
50262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1676750262
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.794941344
Short name T590
Test name
Test status
Simulation time 8395302155 ps
CPU time 7.71 seconds
Started Apr 18 01:14:37 PM PDT 24
Finished Apr 18 01:14:45 PM PDT 24
Peak memory 204012 kb
Host smart-4b306979-ace2-4946-b8ea-08486d8513c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79494
1344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.794941344
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.3525731551
Short name T740
Test name
Test status
Simulation time 8395770650 ps
CPU time 9.58 seconds
Started Apr 18 01:14:35 PM PDT 24
Finished Apr 18 01:14:46 PM PDT 24
Peak memory 204008 kb
Host smart-ee63f6c7-ed76-48b8-a1a0-5eb3ac4e6d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35257
31551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.3525731551
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.3830351050
Short name T984
Test name
Test status
Simulation time 8471323927 ps
CPU time 7.94 seconds
Started Apr 18 01:14:33 PM PDT 24
Finished Apr 18 01:14:42 PM PDT 24
Peak memory 204008 kb
Host smart-ed18af6f-ad1b-435b-a4fe-452f96558c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38303
51050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.3830351050
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.4123602216
Short name T908
Test name
Test status
Simulation time 8382680281 ps
CPU time 7.87 seconds
Started Apr 18 01:14:36 PM PDT 24
Finished Apr 18 01:14:44 PM PDT 24
Peak memory 203860 kb
Host smart-e97d1050-27ca-4157-9931-098bed52d9c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41236
02216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.4123602216
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.147581620
Short name T1323
Test name
Test status
Simulation time 37080419 ps
CPU time 0.65 seconds
Started Apr 18 01:14:34 PM PDT 24
Finished Apr 18 01:14:36 PM PDT 24
Peak memory 203904 kb
Host smart-edee8c8f-905b-43a6-a9fa-67c730d9faa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14758
1620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.147581620
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.4201317933
Short name T221
Test name
Test status
Simulation time 19636109801 ps
CPU time 34.04 seconds
Started Apr 18 01:14:39 PM PDT 24
Finished Apr 18 01:15:14 PM PDT 24
Peak memory 204312 kb
Host smart-9788bbf2-d79b-4be3-814f-159c8f0cae08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42013
17933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.4201317933
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.3342286002
Short name T880
Test name
Test status
Simulation time 8366452004 ps
CPU time 7.82 seconds
Started Apr 18 01:14:36 PM PDT 24
Finished Apr 18 01:14:44 PM PDT 24
Peak memory 204028 kb
Host smart-c254a1d7-8509-4932-ad15-3d63f0777d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33422
86002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.3342286002
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.2446336105
Short name T904
Test name
Test status
Simulation time 8490884752 ps
CPU time 10.52 seconds
Started Apr 18 01:14:35 PM PDT 24
Finished Apr 18 01:14:46 PM PDT 24
Peak memory 204020 kb
Host smart-edba03ff-5710-413c-9966-ef160d8f3349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24463
36105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.2446336105
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.294764361
Short name T452
Test name
Test status
Simulation time 8374015602 ps
CPU time 7.77 seconds
Started Apr 18 01:14:44 PM PDT 24
Finished Apr 18 01:14:53 PM PDT 24
Peak memory 203996 kb
Host smart-1f6cc2cb-c665-4521-b32a-9ef7701edea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29476
4361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.294764361
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.245353241
Short name T1337
Test name
Test status
Simulation time 8373716831 ps
CPU time 8.27 seconds
Started Apr 18 01:14:39 PM PDT 24
Finished Apr 18 01:14:48 PM PDT 24
Peak memory 203996 kb
Host smart-fa3ca3c4-32f5-414a-bde7-4c9f2ab88ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24535
3241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.245353241
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.4278346506
Short name T434
Test name
Test status
Simulation time 8369888425 ps
CPU time 8.05 seconds
Started Apr 18 01:14:34 PM PDT 24
Finished Apr 18 01:14:43 PM PDT 24
Peak memory 203960 kb
Host smart-7404b51f-7065-47fd-80cb-1caa485ae499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42783
46506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.4278346506
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.3130193950
Short name T1316
Test name
Test status
Simulation time 8515710449 ps
CPU time 8.87 seconds
Started Apr 18 01:14:33 PM PDT 24
Finished Apr 18 01:14:42 PM PDT 24
Peak memory 204016 kb
Host smart-c2a8b3a7-6646-483f-bd85-23a8a0bdf691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31301
93950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.3130193950
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.3888509191
Short name T559
Test name
Test status
Simulation time 8398278626 ps
CPU time 8.5 seconds
Started Apr 18 01:14:35 PM PDT 24
Finished Apr 18 01:14:45 PM PDT 24
Peak memory 203956 kb
Host smart-b20e0f3b-6cef-4247-992c-edc205f3a838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38885
09191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.3888509191
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.2712013690
Short name T773
Test name
Test status
Simulation time 8397886880 ps
CPU time 7.9 seconds
Started Apr 18 01:14:36 PM PDT 24
Finished Apr 18 01:14:44 PM PDT 24
Peak memory 204048 kb
Host smart-bad9041f-abbc-4540-a82f-dad67f7be941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27120
13690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.2712013690
Directory /workspace/9.usbdev_stall_trans/latest
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