Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}
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Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 22 0 22 100.00
Crosses 72 0 72 100.00


Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 18 0 18 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_cg_cc 72 0 72 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 18 0 18 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 115434 1 T1 3 T2 4 T3 4
all_values[1] 115434 1 T1 3 T2 4 T3 4
all_values[2] 115434 1 T1 3 T2 4 T3 4
all_values[3] 115434 1 T1 3 T2 4 T3 4
all_values[4] 115434 1 T1 3 T2 4 T3 4
all_values[5] 115434 1 T1 3 T2 4 T3 4
all_values[6] 115434 1 T1 3 T2 4 T3 4
all_values[7] 115434 1 T1 3 T2 4 T3 4
all_values[8] 115434 1 T1 3 T2 4 T3 4
all_values[9] 115434 1 T1 3 T2 4 T3 4
all_values[10] 115434 1 T1 3 T2 4 T3 4
all_values[11] 115434 1 T1 3 T2 4 T3 4
all_values[12] 115434 1 T1 3 T2 4 T3 4
all_values[13] 115434 1 T1 3 T2 4 T3 4
all_values[14] 115434 1 T1 3 T2 4 T3 4
all_values[15] 115434 1 T1 3 T2 4 T3 4
all_values[16] 115434 1 T1 3 T2 4 T3 4
all_values[17] 115434 1 T1 3 T2 4 T3 4



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2073893 1 T1 54 T2 72 T3 72
auto[1] 3919 1 T16 4 T18 3 T19 3



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2072926 1 T1 54 T2 72 T3 72
auto[1] 4886 1 T67 108 T68 122 T69 68



Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 72 0 72 100.00


Automatically Generated Cross Bins for intr_cg_cc

Bins
cp_intrcp_intr_encp_intr_stateCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] 114426 1 T1 3 T2 4 T3 4
all_values[0] auto[0] auto[1] 153 1 T67 2 T68 4 T69 4
all_values[0] auto[1] auto[0] 724 1 T16 4 T19 3 T14 3
all_values[0] auto[1] auto[1] 131 1 T67 6 T68 2 T69 1
all_values[1] auto[0] auto[0] 114837 1 T1 3 T2 4 T3 4
all_values[1] auto[0] auto[1] 142 1 T67 3 T68 4 T69 3
all_values[1] auto[1] auto[0] 320 1 T18 3 T35 3 T37 3
all_values[1] auto[1] auto[1] 135 1 T67 3 T68 4 T69 2
all_values[2] auto[0] auto[0] 115136 1 T1 3 T2 4 T3 4
all_values[2] auto[0] auto[1] 130 1 T67 3 T68 3 T69 4
all_values[2] auto[1] auto[0] 28 1 T70 1 T254 1 T255 1
all_values[2] auto[1] auto[1] 140 1 T67 4 T68 4 T69 1
all_values[3] auto[0] auto[0] 115142 1 T1 3 T2 4 T3 4
all_values[3] auto[0] auto[1] 123 1 T67 4 T68 4 T71 1
all_values[3] auto[1] auto[0] 14 1 T256 1 T257 1 T258 1
all_values[3] auto[1] auto[1] 155 1 T67 3 T68 3 T69 5
all_values[4] auto[0] auto[0] 115125 1 T1 3 T2 4 T3 4
all_values[4] auto[0] auto[1] 140 1 T67 1 T68 5 T69 3
all_values[4] auto[1] auto[0] 35 1 T68 1 T70 1 T73 1
all_values[4] auto[1] auto[1] 134 1 T67 7 T68 1 T69 2
all_values[5] auto[0] auto[0] 115148 1 T1 3 T2 4 T3 4
all_values[5] auto[0] auto[1] 117 1 T68 5 T69 1 T70 1
all_values[5] auto[1] auto[0] 16 1 T67 2 T68 1 T71 1
all_values[5] auto[1] auto[1] 153 1 T68 2 T69 3 T70 5
all_values[6] auto[0] auto[0] 115128 1 T1 3 T2 4 T3 4
all_values[6] auto[0] auto[1] 153 1 T67 4 T68 2 T69 2
all_values[6] auto[1] auto[0] 20 1 T67 1 T68 1 T252 1
all_values[6] auto[1] auto[1] 133 1 T67 2 T68 4 T69 3
all_values[7] auto[0] auto[0] 115160 1 T1 3 T2 4 T3 4
all_values[7] auto[0] auto[1] 112 1 T67 3 T68 1 T71 4
all_values[7] auto[1] auto[0] 27 1 T252 1 T256 1 T254 1
all_values[7] auto[1] auto[1] 135 1 T67 5 T68 6 T69 5
all_values[8] auto[0] auto[0] 115146 1 T1 3 T2 4 T3 4
all_values[8] auto[0] auto[1] 125 1 T67 1 T68 1 T70 3
all_values[8] auto[1] auto[0] 30 1 T67 1 T68 1 T69 1
all_values[8] auto[1] auto[1] 133 1 T67 5 T68 5 T70 5
all_values[9] auto[0] auto[0] 115134 1 T1 3 T2 4 T3 4
all_values[9] auto[0] auto[1] 161 1 T67 6 T68 5 T71 2
all_values[9] auto[1] auto[0] 18 1 T69 1 T73 1 T252 1
all_values[9] auto[1] auto[1] 121 1 T67 2 T68 3 T71 3
all_values[10] auto[0] auto[0] 115136 1 T1 3 T2 4 T3 4
all_values[10] auto[0] auto[1] 127 1 T68 3 T69 4 T73 6
all_values[10] auto[1] auto[0] 21 1 T71 1 T70 3 T73 1
all_values[10] auto[1] auto[1] 150 1 T68 5 T69 1 T71 3
all_values[11] auto[0] auto[0] 115143 1 T1 3 T2 4 T3 4
all_values[11] auto[0] auto[1] 128 1 T67 3 T68 2 T69 4
all_values[11] auto[1] auto[0] 25 1 T67 1 T69 1 T71 1
all_values[11] auto[1] auto[1] 138 1 T67 4 T68 6 T71 1
all_values[12] auto[0] auto[0] 115138 1 T1 3 T2 4 T3 4
all_values[12] auto[0] auto[1] 134 1 T67 5 T71 1 T70 6
all_values[12] auto[1] auto[0] 26 1 T68 2 T69 2 T70 1
all_values[12] auto[1] auto[1] 136 1 T67 3 T68 4 T71 4
all_values[13] auto[0] auto[0] 115130 1 T1 3 T2 4 T3 4
all_values[13] auto[0] auto[1] 141 1 T67 4 T68 4 T69 1
all_values[13] auto[1] auto[0] 26 1 T67 1 T71 1 T254 2
all_values[13] auto[1] auto[1] 137 1 T67 2 T68 4 T69 4
all_values[14] auto[0] auto[0] 115139 1 T1 3 T2 4 T3 4
all_values[14] auto[0] auto[1] 113 1 T67 3 T68 1 T69 5
all_values[14] auto[1] auto[0] 31 1 T68 2 T73 1 T252 3
all_values[14] auto[1] auto[1] 151 1 T67 5 T68 3 T70 6
all_values[15] auto[0] auto[0] 115130 1 T1 3 T2 4 T3 4
all_values[15] auto[0] auto[1] 145 1 T67 6 T68 3 T69 1
all_values[15] auto[1] auto[0] 24 1 T68 1 T70 1 T254 2
all_values[15] auto[1] auto[1] 135 1 T67 2 T68 4 T69 4
all_values[16] auto[0] auto[0] 115137 1 T1 3 T2 4 T3 4
all_values[16] auto[0] auto[1] 133 1 T67 2 T68 5 T69 3
all_values[16] auto[1] auto[0] 32 1 T68 1 T71 1 T70 1
all_values[16] auto[1] auto[1] 132 1 T67 5 T68 2 T69 2
all_values[17] auto[0] auto[0] 115145 1 T1 3 T2 4 T3 4
all_values[17] auto[0] auto[1] 136 1 T68 1 T70 3 T73 4
all_values[17] auto[1] auto[0] 29 1 T67 5 T69 2 T252 2
all_values[17] auto[1] auto[1] 124 1 T68 7 T71 5 T70 4

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