Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	115434	1		T1	3		T2	4		T3	4
all_pins[1]	115434	1		T1	3		T2	4		T3	4
all_pins[2]	115434	1		T1	3		T2	4		T3	4
all_pins[3]	115434	1		T1	3		T2	4		T3	4
all_pins[4]	115434	1		T1	3		T2	4		T3	4
all_pins[5]	115434	1		T1	3		T2	4		T3	4
all_pins[6]	115434	1		T1	3		T2	4		T3	4
all_pins[7]	115434	1		T1	3		T2	4		T3	4
all_pins[8]	115434	1		T1	3		T2	4		T3	4
all_pins[9]	115434	1		T1	3		T2	4		T3	4
all_pins[10]	115434	1		T1	3		T2	4		T3	4
all_pins[11]	115434	1		T1	3		T2	4		T3	4
all_pins[12]	115434	1		T1	3		T2	4		T3	4
all_pins[13]	115434	1		T1	3		T2	4		T3	4
all_pins[14]	115434	1		T1	3		T2	4		T3	4
all_pins[15]	115434	1		T1	3		T2	4		T3	4
all_pins[16]	115434	1		T1	3		T2	4		T3	4
all_pins[17]	115434	1		T1	3		T2	4		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2076445	1		T1	54		T2	72		T3	72
values[0x1]	1367	1		T16	1		T18	1		T35	1
transitions[0x0=>0x1]	1086	1		T16	1		T18	1		T35	1
transitions[0x1=>0x0]	1096	1		T16	1		T18	1		T35	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	115277	1		T1	3		T2	4		T3	4
all_pins[0]	values[0x1]	157	1		T16	1		T54	1		T88	1
all_pins[0]	transitions[0x0=>0x1]	148	1		T16	1		T54	1		T88	1
all_pins[0]	transitions[0x1=>0x0]	145	1		T18	1		T35	1		T37	1
all_pins[1]	values[0x0]	115280	1		T1	3		T2	4		T3	4
all_pins[1]	values[0x1]	154	1		T18	1		T35	1		T37	1
all_pins[1]	transitions[0x0=>0x1]	141	1		T18	1		T35	1		T37	1
all_pins[1]	transitions[0x1=>0x0]	75	1		T67	3		T68	1		T71	1
all_pins[2]	values[0x0]	115346	1		T1	3		T2	4		T3	4
all_pins[2]	values[0x1]	88	1		T67	3		T68	1		T69	1
all_pins[2]	transitions[0x0=>0x1]	67	1		T67	1		T68	1		T71	1
all_pins[2]	transitions[0x1=>0x0]	58	1		T68	2		T69	3		T71	2
all_pins[3]	values[0x0]	115355	1		T1	3		T2	4		T3	4
all_pins[3]	values[0x1]	79	1		T67	2		T68	2		T69	4
all_pins[3]	transitions[0x0=>0x1]	59	1		T67	2		T68	2		T69	2
all_pins[3]	transitions[0x1=>0x0]	51	1		T67	2		T68	1		T71	1
all_pins[4]	values[0x0]	115363	1		T1	3		T2	4		T3	4
all_pins[4]	values[0x1]	71	1		T67	2		T68	1		T69	2
all_pins[4]	transitions[0x0=>0x1]	49	1		T67	2		T68	1		T69	2
all_pins[4]	transitions[0x1=>0x0]	46	1		T68	2		T69	2		T252	2
all_pins[5]	values[0x0]	115366	1		T1	3		T2	4		T3	4
all_pins[5]	values[0x1]	68	1		T68	2		T69	2		T70	1
all_pins[5]	transitions[0x0=>0x1]	56	1		T68	2		T69	2		T70	1
all_pins[5]	transitions[0x1=>0x0]	49	1		T67	1		T68	1		T71	1
all_pins[6]	values[0x0]	115373	1		T1	3		T2	4		T3	4
all_pins[6]	values[0x1]	61	1		T67	1		T68	1		T71	1
all_pins[6]	transitions[0x0=>0x1]	48	1		T67	1		T68	1		T70	2
all_pins[6]	transitions[0x1=>0x0]	41	1		T67	2		T68	2		T69	3
all_pins[7]	values[0x0]	115380	1		T1	3		T2	4		T3	4
all_pins[7]	values[0x1]	54	1		T67	2		T68	2		T69	3
all_pins[7]	transitions[0x0=>0x1]	44	1		T67	1		T68	2		T69	3
all_pins[7]	transitions[0x1=>0x0]	50	1		T67	1		T68	2		T70	2
all_pins[8]	values[0x0]	115374	1		T1	3		T2	4		T3	4
all_pins[8]	values[0x1]	60	1		T67	2		T68	2		T70	2
all_pins[8]	transitions[0x0=>0x1]	46	1		T67	2		T68	1		T70	2
all_pins[8]	transitions[0x1=>0x0]	45	1		T68	2		T73	4		T254	1
all_pins[9]	values[0x0]	115375	1		T1	3		T2	4		T3	4
all_pins[9]	values[0x1]	59	1		T68	3		T73	4		T254	2
all_pins[9]	transitions[0x0=>0x1]	38	1		T68	1		T73	4		T254	1
all_pins[9]	transitions[0x1=>0x0]	55	1		T69	1		T70	1		T252	2
all_pins[10]	values[0x0]	115358	1		T1	3		T2	4		T3	4
all_pins[10]	values[0x1]	76	1		T68	2		T69	1		T70	1
all_pins[10]	transitions[0x0=>0x1]	56	1		T68	1		T69	1		T70	1
all_pins[10]	transitions[0x1=>0x0]	43	1		T67	3		T68	1		T70	1
all_pins[11]	values[0x0]	115371	1		T1	3		T2	4		T3	4
all_pins[11]	values[0x1]	63	1		T67	3		T68	2		T70	1
all_pins[11]	transitions[0x0=>0x1]	49	1		T67	3		T68	2		T70	1
all_pins[11]	transitions[0x1=>0x0]	55	1		T67	1		T68	3		T252	3
all_pins[12]	values[0x0]	115365	1		T1	3		T2	4		T3	4
all_pins[12]	values[0x1]	69	1		T67	1		T68	3		T252	3
all_pins[12]	transitions[0x0=>0x1]	48	1		T68	2		T252	3		T256	1
all_pins[12]	transitions[0x1=>0x0]	47	1		T67	1		T68	3		T69	2
all_pins[13]	values[0x0]	115366	1		T1	3		T2	4		T3	4
all_pins[13]	values[0x1]	68	1		T67	2		T68	4		T69	2
all_pins[13]	transitions[0x0=>0x1]	53	1		T67	2		T68	4		T69	2
all_pins[13]	transitions[0x1=>0x0]	64	1		T67	3		T68	2		T70	4
all_pins[14]	values[0x0]	115355	1		T1	3		T2	4		T3	4
all_pins[14]	values[0x1]	79	1		T67	3		T68	2		T70	4
all_pins[14]	transitions[0x0=>0x1]	61	1		T67	3		T68	2		T70	4
all_pins[14]	transitions[0x1=>0x0]	35	1		T68	4		T69	3		T73	1
all_pins[15]	values[0x0]	115381	1		T1	3		T2	4		T3	4
all_pins[15]	values[0x1]	53	1		T68	4		T69	3		T73	2
all_pins[15]	transitions[0x0=>0x1]	43	1		T68	3		T69	2		T73	2
all_pins[15]	transitions[0x1=>0x0]	45	1		T67	3		T69	1		T70	1
all_pins[16]	values[0x0]	115379	1		T1	3		T2	4		T3	4
all_pins[16]	values[0x1]	55	1		T67	3		T68	1		T69	2
all_pins[16]	transitions[0x0=>0x1]	46	1		T67	3		T68	1		T69	2
all_pins[16]	transitions[0x1=>0x0]	44	1		T68	2		T71	1		T70	2
all_pins[17]	values[0x0]	115381	1		T1	3		T2	4		T3	4
all_pins[17]	values[0x1]	53	1		T68	2		T71	1		T70	2
all_pins[17]	transitions[0x0=>0x1]	34	1		T68	1		T70	2		T73	1
all_pins[17]	transitions[0x1=>0x0]	148	1		T16	1		T54	1		T88	1