Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1		T67	7		T68	7		T69	4
all_values[1]	275	1		T67	7		T68	7		T69	4
all_values[2]	275	1		T67	7		T68	7		T69	4
all_values[3]	275	1		T67	7		T68	7		T69	4
all_values[4]	275	1		T67	7		T68	7		T69	4
all_values[5]	275	1		T67	7		T68	7		T69	4
all_values[6]	275	1		T67	7		T68	7		T69	4
all_values[7]	275	1		T67	7		T68	7		T69	4
all_values[8]	275	1		T67	7		T68	7		T69	4
all_values[9]	275	1		T67	7		T68	7		T69	4
all_values[10]	275	1		T67	7		T68	7		T69	4
all_values[11]	275	1		T67	7		T68	7		T69	4
all_values[12]	275	1		T67	7		T68	7		T69	4
all_values[13]	275	1		T67	7		T68	7		T69	4
all_values[14]	275	1		T67	7		T68	7		T69	4
all_values[15]	275	1		T67	7		T68	7		T69	4
all_values[16]	275	1		T67	7		T68	7		T69	4
all_values[17]	275	1		T67	7		T68	7		T69	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2755	1		T67	66		T68	71		T69	32
auto[1]	2195	1		T67	60		T68	55		T69	40

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	899	1		T67	33		T68	22		T69	18
auto[1]	4051	1		T67	93		T68	104		T69	54

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2896	1		T67	81		T68	74		T69	39
auto[1]	2054	1		T67	45		T68	52		T69	33

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	23	1		T68	1		T71	1		T252	1
all_values[0]	auto[0]	auto[0]	auto[1]	65	1		T67	2		T68	1		T69	1
all_values[0]	auto[0]	auto[1]	auto[0]	16	1		T68	1		T254	1		T255	2
all_values[0]	auto[0]	auto[1]	auto[1]	46	1		T67	2		T70	4		T73	1
all_values[0]	auto[1]	auto[0]	auto[1]	79	1		T67	1		T68	1		T69	2
all_values[0]	auto[1]	auto[1]	auto[1]	46	1		T67	2		T68	3		T69	1
all_values[1]	auto[0]	auto[0]	auto[0]	33	1		T67	1		T70	1		T252	1
all_values[1]	auto[0]	auto[0]	auto[1]	61	1		T67	1		T68	2		T69	1
all_values[1]	auto[0]	auto[1]	auto[0]	13	1		T67	1		T71	2		T257	1
all_values[1]	auto[0]	auto[1]	auto[1]	56	1		T67	1		T68	2		T69	1
all_values[1]	auto[1]	auto[0]	auto[1]	59	1		T67	1		T68	3		T70	1
all_values[1]	auto[1]	auto[1]	auto[1]	53	1		T67	2		T69	2		T71	1
all_values[2]	auto[0]	auto[0]	auto[0]	29	1		T67	1		T68	1		T71	1
all_values[2]	auto[0]	auto[0]	auto[1]	52	1		T67	1		T68	1		T69	1
all_values[2]	auto[0]	auto[1]	auto[0]	23	1		T254	1		T255	1		T259	1
all_values[2]	auto[0]	auto[1]	auto[1]	53	1		T67	3		T68	2		T71	1
all_values[2]	auto[1]	auto[0]	auto[1]	67	1		T67	1		T68	3		T69	1
all_values[2]	auto[1]	auto[1]	auto[1]	51	1		T67	1		T69	2		T70	1
all_values[3]	auto[0]	auto[0]	auto[0]	36	1		T67	1		T68	1		T71	1
all_values[3]	auto[0]	auto[0]	auto[1]	50	1		T67	2		T68	2		T71	1
all_values[3]	auto[0]	auto[1]	auto[0]	9	1		T256	1		T260	1		T261	2
all_values[3]	auto[0]	auto[1]	auto[1]	65	1		T67	2		T68	1		T69	1
all_values[3]	auto[1]	auto[0]	auto[1]	60	1		T67	2		T68	3		T71	1
all_values[3]	auto[1]	auto[1]	auto[1]	55	1		T69	3		T73	2		T252	1
all_values[4]	auto[0]	auto[0]	auto[0]	28	1		T68	1		T70	1		T262	1
all_values[4]	auto[0]	auto[0]	auto[1]	63	1		T67	2		T68	2		T69	1
all_values[4]	auto[0]	auto[1]	auto[0]	19	1		T68	1		T73	1		T263	3
all_values[4]	auto[0]	auto[1]	auto[1]	55	1		T67	2		T68	1		T70	3
all_values[4]	auto[1]	auto[0]	auto[1]	57	1		T68	2		T71	1		T70	1
all_values[4]	auto[1]	auto[1]	auto[1]	53	1		T67	3		T69	3		T71	1
all_values[5]	auto[0]	auto[0]	auto[0]	36	1		T67	4		T68	1		T69	1
all_values[5]	auto[0]	auto[0]	auto[1]	53	1		T68	1		T73	3		T252	1
all_values[5]	auto[0]	auto[1]	auto[0]	14	1		T67	3		T71	1		T254	1
all_values[5]	auto[0]	auto[1]	auto[1]	64	1		T69	1		T70	3		T73	2
all_values[5]	auto[1]	auto[0]	auto[1]	55	1		T68	3		T69	2		T70	1
all_values[5]	auto[1]	auto[1]	auto[1]	53	1		T68	2		T70	1		T73	2
all_values[6]	auto[0]	auto[0]	auto[0]	27	1		T67	1		T68	2		T252	1
all_values[6]	auto[0]	auto[0]	auto[1]	58	1		T67	1		T69	2		T71	2
all_values[6]	auto[0]	auto[1]	auto[0]	10	1		T67	1		T263	1		T264	1
all_values[6]	auto[0]	auto[1]	auto[1]	49	1		T67	1		T68	2		T69	1
all_values[6]	auto[1]	auto[0]	auto[1]	79	1		T67	1		T68	3		T69	1
all_values[6]	auto[1]	auto[1]	auto[1]	52	1		T67	2		T71	2		T70	1
all_values[7]	auto[0]	auto[0]	auto[0]	49	1		T68	1		T252	2		T254	2
all_values[7]	auto[0]	auto[0]	auto[1]	45	1		T67	1		T68	1		T71	2
all_values[7]	auto[0]	auto[1]	auto[0]	22	1		T252	1		T256	1		T262	1
all_values[7]	auto[0]	auto[1]	auto[1]	58	1		T67	2		T68	3		T69	1
all_values[7]	auto[1]	auto[0]	auto[1]	57	1		T67	2		T68	1		T70	1
all_values[7]	auto[1]	auto[1]	auto[1]	44	1		T67	2		T68	1		T69	3
all_values[8]	auto[0]	auto[0]	auto[0]	39	1		T67	1		T68	2		T69	2
all_values[8]	auto[0]	auto[0]	auto[1]	65	1		T67	2		T68	1		T70	1
all_values[8]	auto[0]	auto[1]	auto[0]	21	1		T67	1		T69	2		T71	2
all_values[8]	auto[0]	auto[1]	auto[1]	45	1		T67	1		T68	1		T70	2
all_values[8]	auto[1]	auto[0]	auto[1]	48	1		T68	1		T70	2		T73	1
all_values[8]	auto[1]	auto[1]	auto[1]	57	1		T67	2		T68	2		T70	2
all_values[9]	auto[0]	auto[0]	auto[0]	30	1		T69	2		T70	1		T252	2
all_values[9]	auto[0]	auto[0]	auto[1]	70	1		T67	3		T68	2		T71	1
all_values[9]	auto[0]	auto[1]	auto[0]	11	1		T69	2		T73	1		T256	2
all_values[9]	auto[0]	auto[1]	auto[1]	50	1		T68	1		T71	1		T73	2
all_values[9]	auto[1]	auto[0]	auto[1]	72	1		T67	3		T68	3		T71	2
all_values[9]	auto[1]	auto[1]	auto[1]	42	1		T67	1		T68	1		T73	2
all_values[10]	auto[0]	auto[0]	auto[0]	30	1		T67	7		T71	2		T70	2
all_values[10]	auto[0]	auto[0]	auto[1]	62	1		T68	2		T69	3		T73	4
all_values[10]	auto[0]	auto[1]	auto[0]	15	1		T70	2		T73	1		T255	1
all_values[10]	auto[0]	auto[1]	auto[1]	56	1		T68	2		T71	1		T70	2
all_values[10]	auto[1]	auto[0]	auto[1]	56	1		T68	3		T73	1		T252	2
all_values[10]	auto[1]	auto[1]	auto[1]	56	1		T69	1		T71	1		T70	1
all_values[11]	auto[0]	auto[0]	auto[0]	35	1		T70	1		T256	1		T257	2
all_values[11]	auto[0]	auto[0]	auto[1]	46	1		T68	2		T69	1		T71	1
all_values[11]	auto[0]	auto[1]	auto[0]	18	1		T67	1		T69	1		T71	1
all_values[11]	auto[0]	auto[1]	auto[1]	62	1		T67	3		T68	2		T73	1
all_values[11]	auto[1]	auto[0]	auto[1]	69	1		T67	2		T68	2		T69	2
all_values[11]	auto[1]	auto[1]	auto[1]	45	1		T67	1		T68	1		T71	2
all_values[12]	auto[0]	auto[0]	auto[0]	33	1		T68	2		T69	1		T70	1
all_values[12]	auto[0]	auto[0]	auto[1]	63	1		T67	2		T71	1		T70	3
all_values[12]	auto[0]	auto[1]	auto[0]	18	1		T68	2		T69	3		T263	1
all_values[12]	auto[0]	auto[1]	auto[1]	57	1		T67	1		T68	2		T71	2
all_values[12]	auto[1]	auto[0]	auto[1]	54	1		T67	2		T70	2		T73	2
all_values[12]	auto[1]	auto[1]	auto[1]	50	1		T67	2		T68	1		T71	1
all_values[13]	auto[0]	auto[0]	auto[0]	27	1		T67	1		T70	2		T73	1
all_values[13]	auto[0]	auto[0]	auto[1]	55	1		T67	2		T68	1		T71	1
all_values[13]	auto[0]	auto[1]	auto[0]	18	1		T67	1		T71	1		T254	1
all_values[13]	auto[0]	auto[1]	auto[1]	51	1		T68	3		T69	2		T71	1
all_values[13]	auto[1]	auto[0]	auto[1]	70	1		T67	2		T68	1		T69	1
all_values[13]	auto[1]	auto[1]	auto[1]	54	1		T67	1		T68	2		T69	1
all_values[14]	auto[0]	auto[0]	auto[0]	34	1		T68	2		T71	1		T73	1
all_values[14]	auto[0]	auto[0]	auto[1]	41	1		T67	2		T68	1		T69	1
all_values[14]	auto[0]	auto[1]	auto[0]	24	1		T68	2		T73	1		T252	2
all_values[14]	auto[0]	auto[1]	auto[1]	61	1		T67	3		T68	1		T70	2
all_values[14]	auto[1]	auto[0]	auto[1]	73	1		T68	1		T69	3		T71	1
all_values[14]	auto[1]	auto[1]	auto[1]	42	1		T67	2		T70	3		T73	2
all_values[15]	auto[0]	auto[0]	auto[0]	25	1		T68	1		T70	1		T256	1
all_values[15]	auto[0]	auto[0]	auto[1]	58	1		T67	2		T68	1		T71	2
all_values[15]	auto[0]	auto[1]	auto[0]	18	1		T254	2		T262	2		T255	1
all_values[15]	auto[0]	auto[1]	auto[1]	46	1		T67	1		T69	2		T73	1
all_values[15]	auto[1]	auto[0]	auto[1]	72	1		T67	2		T69	1		T71	1
all_values[15]	auto[1]	auto[1]	auto[1]	56	1		T67	2		T68	5		T69	1
all_values[16]	auto[0]	auto[0]	auto[0]	40	1		T67	1		T68	1		T71	2
all_values[16]	auto[0]	auto[0]	auto[1]	49	1		T67	2		T68	2		T69	1
all_values[16]	auto[0]	auto[1]	auto[0]	15	1		T256	2		T265	1		T266	1
all_values[16]	auto[0]	auto[1]	auto[1]	64	1		T67	1		T68	2		T70	3
all_values[16]	auto[1]	auto[0]	auto[1]	59	1		T67	1		T68	1		T73	1
all_values[16]	auto[1]	auto[1]	auto[1]	48	1		T67	2		T68	1		T69	3
all_values[17]	auto[0]	auto[0]	auto[0]	40	1		T67	3		T69	1		T70	1
all_values[17]	auto[0]	auto[0]	auto[1]	55	1		T68	1		T70	2		T73	1
all_values[17]	auto[0]	auto[1]	auto[0]	21	1		T67	4		T69	3		T252	1
all_values[17]	auto[0]	auto[1]	auto[1]	48	1		T68	4		T71	3		T70	1
all_values[17]	auto[1]	auto[0]	auto[1]	64	1		T68	1		T70	2		T73	1
all_values[17]	auto[1]	auto[1]	auto[1]	47	1		T68	1		T71	1		T70	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal