Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.40 95.60 88.89 96.47 50.00 94.10 97.36 96.40


Total test records in report: 1480
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T1329 /workspace/coverage/default/39.usbdev_enable.1347539085 Apr 21 04:03:50 PM PDT 24 Apr 21 04:03:59 PM PDT 24 8404985033 ps
T1330 /workspace/coverage/default/20.usbdev_setup_stage.2518032149 Apr 21 04:01:09 PM PDT 24 Apr 21 04:01:17 PM PDT 24 8373178537 ps
T1331 /workspace/coverage/default/25.usbdev_stall_trans.1829942597 Apr 21 04:01:52 PM PDT 24 Apr 21 04:02:01 PM PDT 24 8398932117 ps
T1332 /workspace/coverage/default/17.random_length_in_trans.2395508539 Apr 21 04:00:36 PM PDT 24 Apr 21 04:00:45 PM PDT 24 8447881859 ps
T1333 /workspace/coverage/default/15.usbdev_pkt_sent.4212154209 Apr 21 04:00:14 PM PDT 24 Apr 21 04:00:22 PM PDT 24 8407328209 ps
T1334 /workspace/coverage/default/44.usbdev_setup_stage.2976516565 Apr 21 04:04:32 PM PDT 24 Apr 21 04:04:42 PM PDT 24 8374215906 ps
T1335 /workspace/coverage/default/46.usbdev_enable.2671017467 Apr 21 04:04:52 PM PDT 24 Apr 21 04:05:00 PM PDT 24 8444159218 ps
T1336 /workspace/coverage/default/27.usbdev_enable.1669416642 Apr 21 04:02:07 PM PDT 24 Apr 21 04:02:15 PM PDT 24 8384845450 ps
T1337 /workspace/coverage/default/37.usbdev_phy_pins_sense.2316191582 Apr 21 04:03:37 PM PDT 24 Apr 21 04:03:38 PM PDT 24 42025520 ps
T1338 /workspace/coverage/default/25.usbdev_stall_priority_over_nak.526413451 Apr 21 04:01:54 PM PDT 24 Apr 21 04:02:03 PM PDT 24 8394746555 ps
T1339 /workspace/coverage/default/48.max_length_in_transaction.2314395268 Apr 21 04:05:05 PM PDT 24 Apr 21 04:05:13 PM PDT 24 8515304613 ps
T1340 /workspace/coverage/default/11.usbdev_smoke.3886979027 Apr 21 03:59:20 PM PDT 24 Apr 21 03:59:28 PM PDT 24 8404844735 ps
T1341 /workspace/coverage/default/4.usbdev_fifo_rst.511645280 Apr 21 03:57:49 PM PDT 24 Apr 21 03:57:51 PM PDT 24 90495353 ps
T1342 /workspace/coverage/default/29.usbdev_min_length_out_transaction.3647838261 Apr 21 04:02:28 PM PDT 24 Apr 21 04:02:37 PM PDT 24 8388282963 ps
T1343 /workspace/coverage/default/38.min_length_in_transaction.242665750 Apr 21 04:03:48 PM PDT 24 Apr 21 04:03:57 PM PDT 24 8377844038 ps
T1344 /workspace/coverage/default/25.usbdev_setup_stage.2240893750 Apr 21 04:01:57 PM PDT 24 Apr 21 04:02:07 PM PDT 24 8379686302 ps
T1345 /workspace/coverage/default/25.usbdev_in_trans.3664764279 Apr 21 04:01:57 PM PDT 24 Apr 21 04:02:07 PM PDT 24 8402588643 ps
T1346 /workspace/coverage/default/8.usbdev_random_length_out_trans.243483052 Apr 21 03:58:49 PM PDT 24 Apr 21 03:58:58 PM PDT 24 8397383977 ps
T1347 /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.2430309463 Apr 21 04:03:58 PM PDT 24 Apr 21 04:04:07 PM PDT 24 8361686824 ps
T1348 /workspace/coverage/default/0.usbdev_smoke.3118358804 Apr 21 03:56:18 PM PDT 24 Apr 21 03:56:28 PM PDT 24 8435286921 ps
T1349 /workspace/coverage/default/37.usbdev_av_buffer.2208725317 Apr 21 04:03:30 PM PDT 24 Apr 21 04:03:40 PM PDT 24 8375263113 ps
T1350 /workspace/coverage/default/18.usbdev_stall_trans.1018609231 Apr 21 04:00:44 PM PDT 24 Apr 21 04:00:54 PM PDT 24 8414562268 ps
T1351 /workspace/coverage/default/45.usbdev_setup_trans_ignored.2860452720 Apr 21 04:04:40 PM PDT 24 Apr 21 04:04:48 PM PDT 24 8373024717 ps
T1352 /workspace/coverage/default/46.usbdev_stall_trans.3508989632 Apr 21 04:04:46 PM PDT 24 Apr 21 04:04:53 PM PDT 24 8390484286 ps
T1353 /workspace/coverage/default/46.usbdev_stall_priority_over_nak.2925201066 Apr 21 04:04:44 PM PDT 24 Apr 21 04:04:53 PM PDT 24 8395195236 ps
T1354 /workspace/coverage/default/48.usbdev_setup_stage.3928634450 Apr 21 04:05:04 PM PDT 24 Apr 21 04:05:14 PM PDT 24 8392561796 ps
T1355 /workspace/coverage/default/27.usbdev_smoke.3747674390 Apr 21 04:02:07 PM PDT 24 Apr 21 04:02:17 PM PDT 24 8450990305 ps
T1356 /workspace/coverage/default/35.usbdev_pkt_buffer.3380738646 Apr 21 04:03:17 PM PDT 24 Apr 21 04:03:48 PM PDT 24 17279352658 ps
T1357 /workspace/coverage/default/45.usbdev_phy_pins_sense.235876430 Apr 21 04:04:40 PM PDT 24 Apr 21 04:04:41 PM PDT 24 127862024 ps
T1358 /workspace/coverage/default/2.max_length_in_transaction.4046064762 Apr 21 03:57:29 PM PDT 24 Apr 21 03:57:37 PM PDT 24 8472266747 ps
T1359 /workspace/coverage/default/33.random_length_in_trans.445702643 Apr 21 04:03:07 PM PDT 24 Apr 21 04:03:15 PM PDT 24 8433253605 ps
T1360 /workspace/coverage/default/38.usbdev_setup_trans_ignored.529793672 Apr 21 04:03:45 PM PDT 24 Apr 21 04:03:53 PM PDT 24 8368044242 ps
T1361 /workspace/coverage/default/34.usbdev_pending_in_trans.999839762 Apr 21 04:03:13 PM PDT 24 Apr 21 04:03:23 PM PDT 24 8381845993 ps
T1362 /workspace/coverage/default/18.random_length_in_trans.3342130698 Apr 21 04:00:49 PM PDT 24 Apr 21 04:00:58 PM PDT 24 8408969596 ps
T1363 /workspace/coverage/default/16.usbdev_enable.193964746 Apr 21 04:00:22 PM PDT 24 Apr 21 04:00:30 PM PDT 24 8372581410 ps
T1364 /workspace/coverage/default/0.usbdev_av_buffer.4005989091 Apr 21 03:56:20 PM PDT 24 Apr 21 03:56:27 PM PDT 24 8379162634 ps
T1365 /workspace/coverage/default/41.usbdev_random_length_out_trans.2047293711 Apr 21 04:04:08 PM PDT 24 Apr 21 04:04:17 PM PDT 24 8367248105 ps
T1366 /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.1993445523 Apr 21 04:00:27 PM PDT 24 Apr 21 04:00:34 PM PDT 24 8369454109 ps
T1367 /workspace/coverage/default/39.usbdev_pkt_buffer.2241657352 Apr 21 04:03:59 PM PDT 24 Apr 21 04:04:27 PM PDT 24 15257327452 ps
T1368 /workspace/coverage/default/14.usbdev_smoke.2253310996 Apr 21 03:59:53 PM PDT 24 Apr 21 04:00:02 PM PDT 24 8452115612 ps
T1369 /workspace/coverage/default/10.usbdev_setup_trans_ignored.759369098 Apr 21 03:59:14 PM PDT 24 Apr 21 03:59:22 PM PDT 24 8402725754 ps
T1370 /workspace/coverage/default/31.usbdev_random_length_out_trans.141110110 Apr 21 04:02:44 PM PDT 24 Apr 21 04:02:52 PM PDT 24 8424137054 ps
T1371 /workspace/coverage/default/27.usbdev_stall_priority_over_nak.2249707054 Apr 21 04:02:13 PM PDT 24 Apr 21 04:02:21 PM PDT 24 8392757076 ps
T1372 /workspace/coverage/default/29.usbdev_pkt_buffer.4089434803 Apr 21 04:02:26 PM PDT 24 Apr 21 04:03:19 PM PDT 24 27927484942 ps
T1373 /workspace/coverage/default/27.usbdev_in_trans.392837359 Apr 21 04:02:05 PM PDT 24 Apr 21 04:02:13 PM PDT 24 8494220746 ps
T1374 /workspace/coverage/default/22.usbdev_in_iso.1518898732 Apr 21 04:01:30 PM PDT 24 Apr 21 04:01:38 PM PDT 24 8410325277 ps
T1375 /workspace/coverage/default/45.usbdev_in_trans.3321361803 Apr 21 04:04:36 PM PDT 24 Apr 21 04:04:46 PM PDT 24 8463519182 ps
T1376 /workspace/coverage/default/11.usbdev_fifo_rst.274993511 Apr 21 03:59:23 PM PDT 24 Apr 21 03:59:25 PM PDT 24 103064069 ps
T1377 /workspace/coverage/default/20.max_length_in_transaction.483961602 Apr 21 04:01:14 PM PDT 24 Apr 21 04:01:24 PM PDT 24 8466967711 ps
T1378 /workspace/coverage/default/6.max_length_in_transaction.2599907360 Apr 21 03:58:29 PM PDT 24 Apr 21 03:58:37 PM PDT 24 8467939437 ps
T1379 /workspace/coverage/default/48.usbdev_stall_trans.895358234 Apr 21 04:05:02 PM PDT 24 Apr 21 04:05:10 PM PDT 24 8402288075 ps
T1380 /workspace/coverage/default/24.usbdev_av_buffer.2048222046 Apr 21 04:01:45 PM PDT 24 Apr 21 04:01:53 PM PDT 24 8433631069 ps
T1381 /workspace/coverage/default/4.usbdev_pkt_buffer.4181194834 Apr 21 03:57:50 PM PDT 24 Apr 21 03:58:22 PM PDT 24 17201516948 ps
T75 /workspace/coverage/default/1.usbdev_sec_cm.3378871982 Apr 21 03:57:10 PM PDT 24 Apr 21 03:57:11 PM PDT 24 123549243 ps
T1382 /workspace/coverage/default/32.usbdev_pkt_sent.1948338119 Apr 21 04:02:53 PM PDT 24 Apr 21 04:03:02 PM PDT 24 8460469166 ps
T58 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2293499077 Apr 21 01:03:05 PM PDT 24 Apr 21 01:03:08 PM PDT 24 200954823 ps
T64 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.62686121 Apr 21 01:03:07 PM PDT 24 Apr 21 01:03:08 PM PDT 24 63408562 ps
T59 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.21288359 Apr 21 01:03:00 PM PDT 24 Apr 21 01:03:03 PM PDT 24 296020020 ps
T67 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3211694911 Apr 21 01:02:59 PM PDT 24 Apr 21 01:03:00 PM PDT 24 56075999 ps
T66 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.605293141 Apr 21 01:03:01 PM PDT 24 Apr 21 01:03:03 PM PDT 24 180894150 ps
T60 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2916230508 Apr 21 01:03:15 PM PDT 24 Apr 21 01:03:17 PM PDT 24 166244138 ps
T203 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.258660901 Apr 21 01:02:44 PM PDT 24 Apr 21 01:02:47 PM PDT 24 100123059 ps
T204 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1827730140 Apr 21 01:03:03 PM PDT 24 Apr 21 01:03:06 PM PDT 24 60215288 ps
T72 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.635799350 Apr 21 01:02:58 PM PDT 24 Apr 21 01:02:59 PM PDT 24 76156856 ps
T97 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.49366132 Apr 21 01:03:05 PM PDT 24 Apr 21 01:03:07 PM PDT 24 69704592 ps
T98 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2539619211 Apr 21 01:02:59 PM PDT 24 Apr 21 01:03:00 PM PDT 24 49849793 ps
T211 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.4101459285 Apr 21 01:03:14 PM PDT 24 Apr 21 01:03:16 PM PDT 24 70455725 ps
T99 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2318694344 Apr 21 01:02:53 PM PDT 24 Apr 21 01:02:54 PM PDT 24 39432701 ps
T100 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1933343423 Apr 21 01:03:02 PM PDT 24 Apr 21 01:03:05 PM PDT 24 88168660 ps
T68 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1130486823 Apr 21 01:03:03 PM PDT 24 Apr 21 01:03:05 PM PDT 24 104086940 ps
T101 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1751437113 Apr 21 01:02:53 PM PDT 24 Apr 21 01:02:58 PM PDT 24 250924533 ps
T69 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.680292558 Apr 21 01:03:26 PM PDT 24 Apr 21 01:03:27 PM PDT 24 23960137 ps
T71 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3057820860 Apr 21 01:03:15 PM PDT 24 Apr 21 01:03:16 PM PDT 24 33294037 ps
T70 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.190303702 Apr 21 01:03:14 PM PDT 24 Apr 21 01:03:15 PM PDT 24 56442359 ps
T102 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2695396157 Apr 21 01:03:11 PM PDT 24 Apr 21 01:03:12 PM PDT 24 50459341 ps
T212 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2491123627 Apr 21 01:03:09 PM PDT 24 Apr 21 01:03:11 PM PDT 24 144335611 ps
T206 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3572985921 Apr 21 01:03:13 PM PDT 24 Apr 21 01:03:16 PM PDT 24 261251497 ps
T222 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.634921905 Apr 21 01:02:59 PM PDT 24 Apr 21 01:03:00 PM PDT 24 72292404 ps
T73 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.506640411 Apr 21 01:03:15 PM PDT 24 Apr 21 01:03:16 PM PDT 24 40291371 ps
T230 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.236987871 Apr 21 01:02:51 PM PDT 24 Apr 21 01:02:55 PM PDT 24 136669920 ps
T231 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.262615957 Apr 21 01:02:58 PM PDT 24 Apr 21 01:03:01 PM PDT 24 71595039 ps
T252 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1920077862 Apr 21 01:03:13 PM PDT 24 Apr 21 01:03:14 PM PDT 24 46882188 ps
T223 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.683608555 Apr 21 01:03:03 PM PDT 24 Apr 21 01:03:06 PM PDT 24 193583013 ps
T221 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1929462643 Apr 21 01:03:23 PM PDT 24 Apr 21 01:03:25 PM PDT 24 84214173 ps
T213 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1443341896 Apr 21 01:02:54 PM PDT 24 Apr 21 01:02:56 PM PDT 24 97342998 ps
T240 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.652374138 Apr 21 01:03:06 PM PDT 24 Apr 21 01:03:08 PM PDT 24 45151022 ps
T247 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1835632994 Apr 21 01:02:52 PM PDT 24 Apr 21 01:02:54 PM PDT 24 195993343 ps
T256 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.4278366510 Apr 21 01:03:06 PM PDT 24 Apr 21 01:03:07 PM PDT 24 57205125 ps
T254 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.777272426 Apr 21 01:03:03 PM PDT 24 Apr 21 01:03:04 PM PDT 24 34089785 ps
T1383 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.4096487091 Apr 21 01:02:59 PM PDT 24 Apr 21 01:03:04 PM PDT 24 538804013 ps
T262 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.376390087 Apr 21 01:03:09 PM PDT 24 Apr 21 01:03:10 PM PDT 24 55906849 ps
T232 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2252938130 Apr 21 01:03:01 PM PDT 24 Apr 21 01:03:02 PM PDT 24 47785848 ps
T241 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3959618224 Apr 21 01:02:53 PM PDT 24 Apr 21 01:02:54 PM PDT 24 90803560 ps
T242 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1002292731 Apr 21 01:02:53 PM PDT 24 Apr 21 01:02:55 PM PDT 24 113381823 ps
T257 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1734323628 Apr 21 01:03:07 PM PDT 24 Apr 21 01:03:08 PM PDT 24 36529737 ps
T248 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3988926770 Apr 21 01:03:03 PM PDT 24 Apr 21 01:03:06 PM PDT 24 328141752 ps
T1384 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3792877759 Apr 21 01:02:52 PM PDT 24 Apr 21 01:02:56 PM PDT 24 150632753 ps
T243 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3365820866 Apr 21 01:03:05 PM PDT 24 Apr 21 01:03:07 PM PDT 24 200526465 ps
T1385 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1356595499 Apr 21 01:03:04 PM PDT 24 Apr 21 01:03:06 PM PDT 24 71808745 ps
T1386 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.647162005 Apr 21 01:02:57 PM PDT 24 Apr 21 01:03:02 PM PDT 24 704977510 ps
T218 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1676172160 Apr 21 01:03:17 PM PDT 24 Apr 21 01:03:24 PM PDT 24 101479694 ps
T263 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2548578530 Apr 21 01:02:58 PM PDT 24 Apr 21 01:02:59 PM PDT 24 29519539 ps
T249 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1191511826 Apr 21 01:02:58 PM PDT 24 Apr 21 01:03:00 PM PDT 24 149874693 ps
T233 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1050708258 Apr 21 01:02:57 PM PDT 24 Apr 21 01:02:58 PM PDT 24 100594508 ps
T217 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3166868616 Apr 21 01:03:02 PM PDT 24 Apr 21 01:03:05 PM PDT 24 176624085 ps
T1387 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1900229709 Apr 21 01:03:04 PM PDT 24 Apr 21 01:03:06 PM PDT 24 65668216 ps
T234 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2766598750 Apr 21 01:02:58 PM PDT 24 Apr 21 01:03:01 PM PDT 24 187374020 ps
T1388 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3786670445 Apr 21 01:03:14 PM PDT 24 Apr 21 01:03:15 PM PDT 24 90126027 ps
T214 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.132477330 Apr 21 01:02:57 PM PDT 24 Apr 21 01:02:59 PM PDT 24 75418579 ps
T1389 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2314040412 Apr 21 01:02:56 PM PDT 24 Apr 21 01:02:58 PM PDT 24 155777634 ps
T255 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.4231035829 Apr 21 01:03:22 PM PDT 24 Apr 21 01:03:23 PM PDT 24 70032963 ps
T250 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1368191904 Apr 21 01:03:16 PM PDT 24 Apr 21 01:03:18 PM PDT 24 345304343 ps
T235 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2623355250 Apr 21 01:03:17 PM PDT 24 Apr 21 01:03:19 PM PDT 24 35265662 ps
T1390 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3933465966 Apr 21 01:03:07 PM PDT 24 Apr 21 01:03:11 PM PDT 24 241286716 ps
T216 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2563019269 Apr 21 01:03:13 PM PDT 24 Apr 21 01:03:15 PM PDT 24 85994148 ps
T267 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1339130839 Apr 21 01:03:05 PM PDT 24 Apr 21 01:03:08 PM PDT 24 405307928 ps
T205 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3340077690 Apr 21 01:03:01 PM PDT 24 Apr 21 01:03:07 PM PDT 24 1490135908 ps
T219 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2711340807 Apr 21 01:02:58 PM PDT 24 Apr 21 01:03:01 PM PDT 24 215978163 ps
T264 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2496310536 Apr 21 01:03:07 PM PDT 24 Apr 21 01:03:08 PM PDT 24 52879838 ps
T258 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2897970214 Apr 21 01:03:15 PM PDT 24 Apr 21 01:03:16 PM PDT 24 77829138 ps
T1391 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2983351690 Apr 21 01:02:56 PM PDT 24 Apr 21 01:02:57 PM PDT 24 47049960 ps
T259 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3272736870 Apr 21 01:03:10 PM PDT 24 Apr 21 01:03:11 PM PDT 24 31641415 ps
T260 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3772956415 Apr 21 01:03:23 PM PDT 24 Apr 21 01:03:24 PM PDT 24 68507879 ps
T1392 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1209988402 Apr 21 01:02:53 PM PDT 24 Apr 21 01:02:54 PM PDT 24 111991482 ps
T265 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3351644271 Apr 21 01:03:23 PM PDT 24 Apr 21 01:03:24 PM PDT 24 37251235 ps
T1393 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3801263098 Apr 21 01:02:57 PM PDT 24 Apr 21 01:03:00 PM PDT 24 122441501 ps
T266 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2652589438 Apr 21 01:03:09 PM PDT 24 Apr 21 01:03:10 PM PDT 24 26832802 ps
T1394 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2183001059 Apr 21 01:03:01 PM PDT 24 Apr 21 01:03:03 PM PDT 24 71548414 ps
T270 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1303422561 Apr 21 01:03:04 PM PDT 24 Apr 21 01:03:07 PM PDT 24 294319029 ps
T1395 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.405658943 Apr 21 01:02:59 PM PDT 24 Apr 21 01:03:01 PM PDT 24 48555510 ps
T261 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3247069553 Apr 21 01:03:02 PM PDT 24 Apr 21 01:03:04 PM PDT 24 39095581 ps
T1396 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2357676074 Apr 21 01:02:59 PM PDT 24 Apr 21 01:03:00 PM PDT 24 35320378 ps
T251 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2441882674 Apr 21 01:03:11 PM PDT 24 Apr 21 01:03:14 PM PDT 24 334949949 ps
T1397 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.4255501612 Apr 21 01:02:49 PM PDT 24 Apr 21 01:02:52 PM PDT 24 167593304 ps
T1398 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3486878267 Apr 21 01:03:05 PM PDT 24 Apr 21 01:03:09 PM PDT 24 151030597 ps
T268 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.4213430765 Apr 21 01:03:15 PM PDT 24 Apr 21 01:03:19 PM PDT 24 532116265 ps
T1399 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1876110163 Apr 21 01:02:53 PM PDT 24 Apr 21 01:02:56 PM PDT 24 109002011 ps
T1400 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1450530486 Apr 21 01:03:01 PM PDT 24 Apr 21 01:03:04 PM PDT 24 156013018 ps
T1401 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2281795913 Apr 21 01:02:57 PM PDT 24 Apr 21 01:02:59 PM PDT 24 62031071 ps
T253 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.364785895 Apr 21 01:02:52 PM PDT 24 Apr 21 01:02:55 PM PDT 24 446735259 ps
T1402 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3548403257 Apr 21 01:03:24 PM PDT 24 Apr 21 01:03:26 PM PDT 24 36432374 ps
T1403 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3014663292 Apr 21 01:02:56 PM PDT 24 Apr 21 01:02:58 PM PDT 24 144090240 ps
T1404 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2942841989 Apr 21 01:03:16 PM PDT 24 Apr 21 01:03:17 PM PDT 24 97303449 ps
T236 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1903148232 Apr 21 01:02:51 PM PDT 24 Apr 21 01:02:55 PM PDT 24 547578039 ps
T272 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3887871186 Apr 21 01:03:10 PM PDT 24 Apr 21 01:03:13 PM PDT 24 424667937 ps
T1405 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1136423112 Apr 21 01:03:02 PM PDT 24 Apr 21 01:03:03 PM PDT 24 55401349 ps
T1406 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1359659727 Apr 21 01:02:59 PM PDT 24 Apr 21 01:03:02 PM PDT 24 110676810 ps
T1407 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.416283541 Apr 21 01:03:00 PM PDT 24 Apr 21 01:03:03 PM PDT 24 387013379 ps
T1408 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2678919442 Apr 21 01:02:53 PM PDT 24 Apr 21 01:02:54 PM PDT 24 59770439 ps
T1409 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3483700797 Apr 21 01:03:01 PM PDT 24 Apr 21 01:03:04 PM PDT 24 72033486 ps
T269 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1084133738 Apr 21 01:03:01 PM PDT 24 Apr 21 01:03:04 PM PDT 24 343457063 ps
T1410 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3838765808 Apr 21 01:03:11 PM PDT 24 Apr 21 01:03:13 PM PDT 24 100120325 ps
T1411 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.266335738 Apr 21 01:03:10 PM PDT 24 Apr 21 01:03:12 PM PDT 24 165099059 ps
T1412 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.466043380 Apr 21 01:02:55 PM PDT 24 Apr 21 01:02:57 PM PDT 24 70411426 ps
T65 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1645285569 Apr 21 01:02:49 PM PDT 24 Apr 21 01:02:50 PM PDT 24 69473614 ps
T1413 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3389928195 Apr 21 01:03:04 PM PDT 24 Apr 21 01:03:05 PM PDT 24 34655007 ps
T237 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2561418822 Apr 21 01:02:53 PM PDT 24 Apr 21 01:03:02 PM PDT 24 1453311180 ps
T1414 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1086630031 Apr 21 01:03:01 PM PDT 24 Apr 21 01:03:05 PM PDT 24 691934360 ps
T1415 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.103108772 Apr 21 01:02:58 PM PDT 24 Apr 21 01:03:01 PM PDT 24 248388894 ps
T1416 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1745821613 Apr 21 01:02:56 PM PDT 24 Apr 21 01:02:58 PM PDT 24 66571638 ps
T238 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.68762630 Apr 21 01:03:00 PM PDT 24 Apr 21 01:03:02 PM PDT 24 170874985 ps
T1417 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1240070380 Apr 21 01:02:59 PM PDT 24 Apr 21 01:03:00 PM PDT 24 90007651 ps
T239 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2146088864 Apr 21 01:03:01 PM PDT 24 Apr 21 01:03:03 PM PDT 24 61574093 ps
T273 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1662671540 Apr 21 01:02:56 PM PDT 24 Apr 21 01:03:01 PM PDT 24 530074569 ps
T1418 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2131546016 Apr 21 01:02:57 PM PDT 24 Apr 21 01:02:58 PM PDT 24 86349558 ps
T1419 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.509289723 Apr 21 01:03:15 PM PDT 24 Apr 21 01:03:16 PM PDT 24 48582815 ps
T1420 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1122483060 Apr 21 01:02:58 PM PDT 24 Apr 21 01:03:01 PM PDT 24 254192575 ps
T1421 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1254326840 Apr 21 01:02:54 PM PDT 24 Apr 21 01:02:55 PM PDT 24 145909708 ps
T1422 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1307983743 Apr 21 01:03:03 PM PDT 24 Apr 21 01:03:06 PM PDT 24 179004429 ps
T1423 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2923598460 Apr 21 01:02:44 PM PDT 24 Apr 21 01:02:46 PM PDT 24 116630435 ps
T1424 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.4241369970 Apr 21 01:03:06 PM PDT 24 Apr 21 01:03:07 PM PDT 24 34177665 ps
T1425 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3958956657 Apr 21 01:02:57 PM PDT 24 Apr 21 01:03:00 PM PDT 24 70138173 ps
T1426 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3125493989 Apr 21 01:03:07 PM PDT 24 Apr 21 01:03:08 PM PDT 24 42618116 ps
T1427 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1983299560 Apr 21 01:03:06 PM PDT 24 Apr 21 01:03:10 PM PDT 24 124607135 ps
T1428 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3536077283 Apr 21 01:03:01 PM PDT 24 Apr 21 01:03:03 PM PDT 24 32792259 ps
T1429 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1499312998 Apr 21 01:03:05 PM PDT 24 Apr 21 01:03:06 PM PDT 24 36820787 ps
T1430 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1578763291 Apr 21 01:02:59 PM PDT 24 Apr 21 01:03:01 PM PDT 24 61867084 ps
T220 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3712557581 Apr 21 01:03:02 PM PDT 24 Apr 21 01:03:04 PM PDT 24 50120168 ps
T1431 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2849329389 Apr 21 01:03:14 PM PDT 24 Apr 21 01:03:15 PM PDT 24 48392702 ps
T1432 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.674638904 Apr 21 01:03:19 PM PDT 24 Apr 21 01:03:21 PM PDT 24 76037210 ps
T1433 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2261215723 Apr 21 01:02:56 PM PDT 24 Apr 21 01:02:58 PM PDT 24 154053450 ps
T1434 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2549667884 Apr 21 01:03:24 PM PDT 24 Apr 21 01:03:25 PM PDT 24 22383103 ps
T1435 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.972751214 Apr 21 01:03:05 PM PDT 24 Apr 21 01:03:06 PM PDT 24 59926527 ps
T1436 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3792328593 Apr 21 01:03:06 PM PDT 24 Apr 21 01:03:09 PM PDT 24 219158725 ps
T1437 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.932012252 Apr 21 01:03:00 PM PDT 24 Apr 21 01:03:05 PM PDT 24 471162928 ps
T1438 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2996231187 Apr 21 01:02:43 PM PDT 24 Apr 21 01:02:46 PM PDT 24 292307186 ps
T1439 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3837927386 Apr 21 01:03:04 PM PDT 24 Apr 21 01:03:05 PM PDT 24 27812159 ps
T1440 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3638582860 Apr 21 01:03:12 PM PDT 24 Apr 21 01:03:13 PM PDT 24 38046594 ps
T1441 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1141772549 Apr 21 01:02:59 PM PDT 24 Apr 21 01:03:04 PM PDT 24 84328853 ps
T1442 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2161993809 Apr 21 01:02:56 PM PDT 24 Apr 21 01:02:59 PM PDT 24 122791781 ps
T215 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.324775736 Apr 21 01:03:03 PM PDT 24 Apr 21 01:03:06 PM PDT 24 707067924 ps
T1443 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.757337235 Apr 21 01:03:02 PM PDT 24 Apr 21 01:03:05 PM PDT 24 561755408 ps
T1444 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1289330802 Apr 21 01:02:54 PM PDT 24 Apr 21 01:02:55 PM PDT 24 61441018 ps
T1445 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1164485158 Apr 21 01:03:04 PM PDT 24 Apr 21 01:03:06 PM PDT 24 52448924 ps
T1446 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3789455279 Apr 21 01:03:12 PM PDT 24 Apr 21 01:03:14 PM PDT 24 50534838 ps
T1447 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.641423966 Apr 21 01:02:55 PM PDT 24 Apr 21 01:02:56 PM PDT 24 66931106 ps
T1448 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.4027881146 Apr 21 01:03:07 PM PDT 24 Apr 21 01:03:08 PM PDT 24 22655890 ps
T1449 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3864776386 Apr 21 01:03:06 PM PDT 24 Apr 21 01:03:10 PM PDT 24 273961472 ps
T1450 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.712774564 Apr 21 01:02:51 PM PDT 24 Apr 21 01:02:53 PM PDT 24 77919840 ps
T1451 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.4037790975 Apr 21 01:03:02 PM PDT 24 Apr 21 01:03:05 PM PDT 24 88016493 ps
T1452 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.4089704722 Apr 21 01:03:24 PM PDT 24 Apr 21 01:03:25 PM PDT 24 31663729 ps
T271 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2509786349 Apr 21 01:02:52 PM PDT 24 Apr 21 01:02:55 PM PDT 24 303414904 ps
T1453 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2628063449 Apr 21 01:02:52 PM PDT 24 Apr 21 01:02:54 PM PDT 24 193717741 ps
T1454 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.207162449 Apr 21 01:02:56 PM PDT 24 Apr 21 01:02:59 PM PDT 24 355801648 ps
T1455 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.905050289 Apr 21 01:03:03 PM PDT 24 Apr 21 01:03:06 PM PDT 24 218278806 ps
T1456 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2879861582 Apr 21 01:02:53 PM PDT 24 Apr 21 01:02:54 PM PDT 24 34839229 ps
T1457 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1100117825 Apr 21 01:03:08 PM PDT 24 Apr 21 01:03:09 PM PDT 24 121133493 ps
T1458 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.4191989927 Apr 21 01:02:59 PM PDT 24 Apr 21 01:03:01 PM PDT 24 66260749 ps
T1459 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1085067191 Apr 21 01:03:11 PM PDT 24 Apr 21 01:03:14 PM PDT 24 370250915 ps
T1460 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2356989629 Apr 21 01:02:56 PM PDT 24 Apr 21 01:02:57 PM PDT 24 61647051 ps
T1461 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.714225205 Apr 21 01:03:07 PM PDT 24 Apr 21 01:03:09 PM PDT 24 83137537 ps
T1462 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1755719100 Apr 21 01:03:18 PM PDT 24 Apr 21 01:03:19 PM PDT 24 70055755 ps
T1463 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.4031305947 Apr 21 01:02:57 PM PDT 24 Apr 21 01:03:00 PM PDT 24 287734445 ps
T1464 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1682837070 Apr 21 01:02:59 PM PDT 24 Apr 21 01:03:00 PM PDT 24 36825938 ps
T1465 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3333099690 Apr 21 01:02:57 PM PDT 24 Apr 21 01:02:58 PM PDT 24 45390356 ps
T1466 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1662241538 Apr 21 01:03:53 PM PDT 24 Apr 21 01:03:54 PM PDT 24 32525186 ps
T1467 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3926946518 Apr 21 01:03:20 PM PDT 24 Apr 21 01:03:21 PM PDT 24 36773827 ps
T1468 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3926499165 Apr 21 01:03:05 PM PDT 24 Apr 21 01:03:06 PM PDT 24 35420293 ps
T1469 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.455641211 Apr 21 01:03:00 PM PDT 24 Apr 21 01:03:01 PM PDT 24 41380210 ps
T1470 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2919194955 Apr 21 01:03:27 PM PDT 24 Apr 21 01:03:28 PM PDT 24 26274028 ps
T1471 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1319014503 Apr 21 01:02:59 PM PDT 24 Apr 21 01:03:00 PM PDT 24 112941907 ps
T1472 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2838811686 Apr 21 01:02:53 PM PDT 24 Apr 21 01:02:54 PM PDT 24 37238741 ps
T1473 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1894591953 Apr 21 01:03:13 PM PDT 24 Apr 21 01:03:14 PM PDT 24 26679251 ps
T1474 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2022202787 Apr 21 01:03:01 PM PDT 24 Apr 21 01:03:03 PM PDT 24 92623855 ps
T1475 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1964789921 Apr 21 01:02:49 PM PDT 24 Apr 21 01:02:51 PM PDT 24 90212655 ps
T1476 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.756955031 Apr 21 01:03:19 PM PDT 24 Apr 21 01:03:36 PM PDT 24 40069972 ps
T1477 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3750853134 Apr 21 01:02:55 PM PDT 24 Apr 21 01:02:56 PM PDT 24 82286281 ps
T1478 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2196889898 Apr 21 01:03:06 PM PDT 24 Apr 21 01:03:09 PM PDT 24 170551363 ps
T1479 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.49595031 Apr 21 01:03:05 PM PDT 24 Apr 21 01:03:06 PM PDT 24 30476957 ps
T1480 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1229269753 Apr 21 01:03:01 PM PDT 24 Apr 21 01:03:03 PM PDT 24 82825959 ps


Test location /workspace/coverage/default/30.usbdev_pkt_buffer.3657760315
Short name T10
Test name
Test status
Simulation time 23432969114 ps
CPU time 46.35 seconds
Started Apr 21 04:02:35 PM PDT 24
Finished Apr 21 04:03:22 PM PDT 24
Peak memory 204352 kb
Host smart-e05ae403-fa3a-45b1-998d-1f3f945a6068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36577
60315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.3657760315
Directory /workspace/30.usbdev_pkt_buffer/latest


Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1130486823
Short name T68
Test name
Test status
Simulation time 104086940 ps
CPU time 0.85 seconds
Started Apr 21 01:03:03 PM PDT 24
Finished Apr 21 01:03:05 PM PDT 24
Peak memory 203040 kb
Host smart-a36e9815-2f56-4c6c-aae1-912e8ef2a239
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1130486823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.1130486823
Directory /workspace/27.usbdev_intr_test/latest


Test location /workspace/coverage/default/42.usbdev_smoke.1769798488
Short name T19
Test name
Test status
Simulation time 8427069379 ps
CPU time 8.16 seconds
Started Apr 21 04:04:12 PM PDT 24
Finished Apr 21 04:04:20 PM PDT 24
Peak memory 204056 kb
Host smart-6727ac3f-cd46-4b01-8d6e-766e9f957821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17697
98488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.1769798488
Directory /workspace/42.usbdev_smoke/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2916230508
Short name T60
Test name
Test status
Simulation time 166244138 ps
CPU time 1.74 seconds
Started Apr 21 01:03:15 PM PDT 24
Finished Apr 21 01:03:17 PM PDT 24
Peak memory 214792 kb
Host smart-53b59d68-7d68-4cf2-b033-a889af7f9ffe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916230508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.2916230508
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/default/49.usbdev_fifo_rst.10827153
Short name T55
Test name
Test status
Simulation time 75063086 ps
CPU time 2.07 seconds
Started Apr 21 04:05:04 PM PDT 24
Finished Apr 21 04:05:07 PM PDT 24
Peak memory 204372 kb
Host smart-c5859683-8b63-4649-824d-13c778fd835e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10827
153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.10827153
Directory /workspace/49.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1593559063
Short name T13
Test name
Test status
Simulation time 35503340 ps
CPU time 0.67 seconds
Started Apr 21 03:57:06 PM PDT 24
Finished Apr 21 03:57:07 PM PDT 24
Peak memory 203900 kb
Host smart-ecaaabb3-efe3-4a90-84c0-d30d6c3f5633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15935
59063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1593559063
Directory /workspace/1.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/41.usbdev_in_iso.4145441801
Short name T53
Test name
Test status
Simulation time 8485538217 ps
CPU time 8.72 seconds
Started Apr 21 04:04:09 PM PDT 24
Finished Apr 21 04:04:18 PM PDT 24
Peak memory 204020 kb
Host smart-07871429-4e27-483d-a9fc-a9284562603b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41454
41801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.4145441801
Directory /workspace/41.usbdev_in_iso/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3211694911
Short name T67
Test name
Test status
Simulation time 56075999 ps
CPU time 0.67 seconds
Started Apr 21 01:02:59 PM PDT 24
Finished Apr 21 01:03:00 PM PDT 24
Peak memory 202884 kb
Host smart-24d9041d-4d82-4006-a0ab-89b4808fdad4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3211694911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3211694911
Directory /workspace/0.usbdev_intr_test/latest


Test location /workspace/coverage/default/25.usbdev_in_stall.3942914815
Short name T4
Test name
Test status
Simulation time 8416650351 ps
CPU time 8 seconds
Started Apr 21 04:01:57 PM PDT 24
Finished Apr 21 04:02:05 PM PDT 24
Peak memory 204052 kb
Host smart-9977a6fc-feb7-4a77-ba77-359075f1901b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39429
14815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.3942914815
Directory /workspace/25.usbdev_in_stall/latest


Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.2798834568
Short name T8
Test name
Test status
Simulation time 8364148414 ps
CPU time 7.82 seconds
Started Apr 21 04:01:20 PM PDT 24
Finished Apr 21 04:01:28 PM PDT 24
Peak memory 204012 kb
Host smart-ef8b7b28-db13-4ea4-938c-83ec6b35e245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27988
34568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.2798834568
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.683608555
Short name T223
Test name
Test status
Simulation time 193583013 ps
CPU time 2.55 seconds
Started Apr 21 01:03:03 PM PDT 24
Finished Apr 21 01:03:06 PM PDT 24
Peak memory 203808 kb
Host smart-aab7ad2a-9797-4d48-90ff-a6dc6730204f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=683608555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.683608555
Directory /workspace/9.usbdev_tl_intg_err/latest


Test location /workspace/coverage/default/40.usbdev_nak_trans.3944540186
Short name T104
Test name
Test status
Simulation time 8428714752 ps
CPU time 8.21 seconds
Started Apr 21 04:03:59 PM PDT 24
Finished Apr 21 04:04:07 PM PDT 24
Peak memory 204068 kb
Host smart-9e578c11-d1c2-4857-accd-dda8bdeaa85c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39445
40186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3944540186
Directory /workspace/40.usbdev_nak_trans/latest


Test location /workspace/coverage/default/0.usbdev_sec_cm.3408777982
Short name T63
Test name
Test status
Simulation time 544791071 ps
CPU time 1.4 seconds
Started Apr 21 03:56:46 PM PDT 24
Finished Apr 21 03:56:48 PM PDT 24
Peak memory 220076 kb
Host smart-4e6bc561-86a3-46f9-b29f-02ff52164f55
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3408777982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.3408777982
Directory /workspace/0.usbdev_sec_cm/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.4278366510
Short name T256
Test name
Test status
Simulation time 57205125 ps
CPU time 0.72 seconds
Started Apr 21 01:03:06 PM PDT 24
Finished Apr 21 01:03:07 PM PDT 24
Peak memory 202960 kb
Host smart-7799b0fa-3ec4-4ed0-b488-8c22bf8645b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4278366510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.4278366510
Directory /workspace/12.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2318694344
Short name T99
Test name
Test status
Simulation time 39432701 ps
CPU time 0.98 seconds
Started Apr 21 01:02:53 PM PDT 24
Finished Apr 21 01:02:54 PM PDT 24
Peak memory 203760 kb
Host smart-f8bb6e51-feb7-4b4e-8ebf-f0b3983ee0bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2318694344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2318694344
Directory /workspace/2.usbdev_csr_rw/latest


Test location /workspace/coverage/default/1.usbdev_pkt_sent.2915300517
Short name T35
Test name
Test status
Simulation time 8433875507 ps
CPU time 10.08 seconds
Started Apr 21 03:57:02 PM PDT 24
Finished Apr 21 03:57:13 PM PDT 24
Peak memory 204052 kb
Host smart-b920529c-fdfe-426d-97ae-e58769ee6f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29153
00517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.2915300517
Directory /workspace/1.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/17.usbdev_pkt_buffer.2050840406
Short name T12
Test name
Test status
Simulation time 28405584254 ps
CPU time 55.78 seconds
Started Apr 21 04:00:34 PM PDT 24
Finished Apr 21 04:01:30 PM PDT 24
Peak memory 204328 kb
Host smart-7e009f58-6b13-4856-ac14-7f252de28d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20508
40406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.2050840406
Directory /workspace/17.usbdev_pkt_buffer/latest


Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.4231035829
Short name T255
Test name
Test status
Simulation time 70032963 ps
CPU time 0.68 seconds
Started Apr 21 01:03:22 PM PDT 24
Finished Apr 21 01:03:23 PM PDT 24
Peak memory 202892 kb
Host smart-e5703b53-1ad8-40ed-a611-6850b3ae56c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4231035829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.4231035829
Directory /workspace/49.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.258660901
Short name T203
Test name
Test status
Simulation time 100123059 ps
CPU time 2.47 seconds
Started Apr 21 01:02:44 PM PDT 24
Finished Apr 21 01:02:47 PM PDT 24
Peak memory 203772 kb
Host smart-1aeba5fb-132f-41f7-a5d0-129e923fd41b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=258660901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.258660901
Directory /workspace/0.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3340077690
Short name T205
Test name
Test status
Simulation time 1490135908 ps
CPU time 4.93 seconds
Started Apr 21 01:03:01 PM PDT 24
Finished Apr 21 01:03:07 PM PDT 24
Peak memory 203688 kb
Host smart-f920b00a-4025-4a3e-b0d6-9948e3d0f707
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3340077690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3340077690
Directory /workspace/13.usbdev_tl_intg_err/latest


Test location /workspace/coverage/default/0.usbdev_enable.3124146583
Short name T54
Test name
Test status
Simulation time 8389002423 ps
CPU time 8.33 seconds
Started Apr 21 03:56:22 PM PDT 24
Finished Apr 21 03:56:30 PM PDT 24
Peak memory 203944 kb
Host smart-7725fd01-3720-437c-8562-8d79033fff8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31241
46583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.3124146583
Directory /workspace/0.usbdev_enable/latest


Test location /workspace/coverage/default/0.usbdev_dpi_config_host.3233481491
Short name T106
Test name
Test status
Simulation time 5167308640 ps
CPU time 135.77 seconds
Started Apr 21 03:56:24 PM PDT 24
Finished Apr 21 03:58:40 PM PDT 24
Peak memory 204320 kb
Host smart-15f797e9-5b38-445d-a219-51d322e10088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32334
81491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.3233481491
Directory /workspace/0.usbdev_dpi_config_host/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1645285569
Short name T65
Test name
Test status
Simulation time 69473614 ps
CPU time 0.86 seconds
Started Apr 21 01:02:49 PM PDT 24
Finished Apr 21 01:02:50 PM PDT 24
Peak memory 203408 kb
Host smart-2d8b7a93-37ea-46cc-b5be-380aeb763cc5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1645285569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.1645285569
Directory /workspace/1.usbdev_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2441882674
Short name T251
Test name
Test status
Simulation time 334949949 ps
CPU time 2.76 seconds
Started Apr 21 01:03:11 PM PDT 24
Finished Apr 21 01:03:14 PM PDT 24
Peak memory 203780 kb
Host smart-6a5250bc-9dcf-420e-a785-85d0b5b99585
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2441882674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2441882674
Directory /workspace/0.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.364785895
Short name T253
Test name
Test status
Simulation time 446735259 ps
CPU time 2.79 seconds
Started Apr 21 01:02:52 PM PDT 24
Finished Apr 21 01:02:55 PM PDT 24
Peak memory 203772 kb
Host smart-5e4217e6-b9b9-4616-b844-b1103dcab4ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=364785895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.364785895
Directory /workspace/2.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1745821613
Short name T1416
Test name
Test status
Simulation time 66571638 ps
CPU time 1.73 seconds
Started Apr 21 01:02:56 PM PDT 24
Finished Apr 21 01:02:58 PM PDT 24
Peak memory 203704 kb
Host smart-7b33131d-b036-4a7d-a6d4-bc339cefad42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1745821613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1745821613
Directory /workspace/1.usbdev_tl_errors/latest


Test location /workspace/coverage/default/0.usbdev_pending_in_trans.292655163
Short name T577
Test name
Test status
Simulation time 8430814736 ps
CPU time 7.65 seconds
Started Apr 21 03:56:32 PM PDT 24
Finished Apr 21 03:56:40 PM PDT 24
Peak memory 204016 kb
Host smart-4be72546-14ef-47a7-b5c1-101b6f756ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29265
5163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.292655163
Directory /workspace/0.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/1.usbdev_pending_in_trans.3438948865
Short name T1314
Test name
Test status
Simulation time 8428898135 ps
CPU time 8.38 seconds
Started Apr 21 03:57:04 PM PDT 24
Finished Apr 21 03:57:13 PM PDT 24
Peak memory 204064 kb
Host smart-11ca64b8-022b-45ab-bce5-b5fa2f5e4efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34389
48865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.3438948865
Directory /workspace/1.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/1.usbdev_smoke.3849652840
Short name T737
Test name
Test status
Simulation time 8447738968 ps
CPU time 8.08 seconds
Started Apr 21 03:56:46 PM PDT 24
Finished Apr 21 03:56:55 PM PDT 24
Peak memory 204032 kb
Host smart-575de8cd-0d55-450c-bd55-cd56ee2a9942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38496
52840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3849652840
Directory /workspace/1.usbdev_smoke/latest


Test location /workspace/coverage/default/10.usbdev_smoke.2618428076
Short name T144
Test name
Test status
Simulation time 8414706294 ps
CPU time 7.73 seconds
Started Apr 21 03:59:10 PM PDT 24
Finished Apr 21 03:59:18 PM PDT 24
Peak memory 204048 kb
Host smart-27517413-0031-44cc-92a7-351776055863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26184
28076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2618428076
Directory /workspace/10.usbdev_smoke/latest


Test location /workspace/coverage/default/11.usbdev_setup_stage.2941804314
Short name T169
Test name
Test status
Simulation time 8423781482 ps
CPU time 8.23 seconds
Started Apr 21 03:59:30 PM PDT 24
Finished Apr 21 03:59:39 PM PDT 24
Peak memory 204044 kb
Host smart-c6362181-f016-4457-afbf-9ca7ed060ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29418
04314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.2941804314
Directory /workspace/11.usbdev_setup_stage/latest


Test location /workspace/coverage/default/12.usbdev_pending_in_trans.2066136204
Short name T1184
Test name
Test status
Simulation time 8378958466 ps
CPU time 7.77 seconds
Started Apr 21 03:59:43 PM PDT 24
Finished Apr 21 03:59:51 PM PDT 24
Peak memory 203988 kb
Host smart-06d5c4bd-f42f-4721-9501-922d2ee3e0ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20661
36204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.2066136204
Directory /workspace/12.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/13.max_length_in_transaction.2247905982
Short name T386
Test name
Test status
Simulation time 8465120802 ps
CPU time 9.39 seconds
Started Apr 21 03:59:52 PM PDT 24
Finished Apr 21 04:00:01 PM PDT 24
Peak memory 204036 kb
Host smart-9ef2dd50-1f29-495f-8433-8f35eb9b0218
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2247905982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.2247905982
Directory /workspace/13.max_length_in_transaction/latest


Test location /workspace/coverage/default/13.usbdev_smoke.3408792299
Short name T92
Test name
Test status
Simulation time 8407289993 ps
CPU time 8.29 seconds
Started Apr 21 03:59:48 PM PDT 24
Finished Apr 21 03:59:57 PM PDT 24
Peak memory 204048 kb
Host smart-df243015-e480-4e44-9aa6-4c809e92ce6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34087
92299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.3408792299
Directory /workspace/13.usbdev_smoke/latest


Test location /workspace/coverage/default/15.usbdev_pending_in_trans.2548176190
Short name T90
Test name
Test status
Simulation time 8400952195 ps
CPU time 10.23 seconds
Started Apr 21 04:00:17 PM PDT 24
Finished Apr 21 04:00:27 PM PDT 24
Peak memory 204064 kb
Host smart-f733bdb5-e776-46c4-ba14-c1cfccbfbdff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25481
76190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.2548176190
Directory /workspace/15.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.3963752290
Short name T42
Test name
Test status
Simulation time 34275031 ps
CPU time 0.69 seconds
Started Apr 21 04:00:28 PM PDT 24
Finished Apr 21 04:00:29 PM PDT 24
Peak memory 203936 kb
Host smart-424c2f08-911b-4494-a92c-3a702c8b8fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39637
52290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.3963752290
Directory /workspace/16.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/2.usbdev_pending_in_trans.461272363
Short name T162
Test name
Test status
Simulation time 8379322752 ps
CPU time 8.85 seconds
Started Apr 21 03:57:18 PM PDT 24
Finished Apr 21 03:57:27 PM PDT 24
Peak memory 204000 kb
Host smart-c89b2824-d863-474d-b75b-d614fe2f45b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46127
2363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.461272363
Directory /workspace/2.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/21.usbdev_smoke.3387886831
Short name T175
Test name
Test status
Simulation time 8455474676 ps
CPU time 10.3 seconds
Started Apr 21 04:01:11 PM PDT 24
Finished Apr 21 04:01:22 PM PDT 24
Peak memory 204000 kb
Host smart-c04070f2-9b11-468a-a9fe-e452c589f122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33878
86831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.3387886831
Directory /workspace/21.usbdev_smoke/latest


Test location /workspace/coverage/default/25.usbdev_pending_in_trans.1673663993
Short name T1044
Test name
Test status
Simulation time 8410842332 ps
CPU time 9.79 seconds
Started Apr 21 04:01:57 PM PDT 24
Finished Apr 21 04:02:07 PM PDT 24
Peak memory 204000 kb
Host smart-145f9aae-628e-4c5c-9091-a18ea010079f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16736
63993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.1673663993
Directory /workspace/25.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/0.usbdev_stall_trans.2922584691
Short name T299
Test name
Test status
Simulation time 8404802079 ps
CPU time 8.16 seconds
Started Apr 21 03:56:30 PM PDT 24
Finished Apr 21 03:56:38 PM PDT 24
Peak memory 204068 kb
Host smart-f4c213c3-29e9-4ffb-8450-dc2563a2b36f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29225
84691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.2922584691
Directory /workspace/0.usbdev_stall_trans/latest


Test location /workspace/coverage/default/18.usbdev_pkt_buffer.1084345194
Short name T93
Test name
Test status
Simulation time 30748928774 ps
CPU time 65.25 seconds
Started Apr 21 04:00:42 PM PDT 24
Finished Apr 21 04:01:47 PM PDT 24
Peak memory 204360 kb
Host smart-36fe9840-4851-48c0-9068-834af584e7e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10843
45194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.1084345194
Directory /workspace/18.usbdev_pkt_buffer/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.324775736
Short name T215
Test name
Test status
Simulation time 707067924 ps
CPU time 2.97 seconds
Started Apr 21 01:03:03 PM PDT 24
Finished Apr 21 01:03:06 PM PDT 24
Peak memory 203728 kb
Host smart-7339256e-b132-4109-aa32-ad6dded93fda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=324775736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.324775736
Directory /workspace/15.usbdev_tl_intg_err/latest


Test location /workspace/coverage/default/0.usbdev_nak_trans.403641633
Short name T677
Test name
Test status
Simulation time 8421156560 ps
CPU time 8.85 seconds
Started Apr 21 03:56:28 PM PDT 24
Finished Apr 21 03:56:37 PM PDT 24
Peak memory 204068 kb
Host smart-c344f925-c269-440f-b428-b7f7909d248e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40364
1633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.403641633
Directory /workspace/0.usbdev_nak_trans/latest


Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.911208755
Short name T540
Test name
Test status
Simulation time 62617737 ps
CPU time 0.73 seconds
Started Apr 21 03:56:34 PM PDT 24
Finished Apr 21 03:56:35 PM PDT 24
Peak memory 203952 kb
Host smart-dca2c79a-4444-4c90-bd4b-37d080eefc4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91120
8755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.911208755
Directory /workspace/0.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/1.usbdev_nak_trans.317815056
Short name T1154
Test name
Test status
Simulation time 8393381934 ps
CPU time 7.84 seconds
Started Apr 21 03:56:56 PM PDT 24
Finished Apr 21 03:57:04 PM PDT 24
Peak memory 204068 kb
Host smart-b63e01b3-45c3-40e3-9535-4b5e2d51191d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31781
5056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.317815056
Directory /workspace/1.usbdev_nak_trans/latest


Test location /workspace/coverage/default/10.usbdev_nak_trans.2849994834
Short name T114
Test name
Test status
Simulation time 8448181979 ps
CPU time 9.48 seconds
Started Apr 21 03:59:10 PM PDT 24
Finished Apr 21 03:59:20 PM PDT 24
Peak memory 204068 kb
Host smart-22f76c3c-2ee6-4af1-9e99-ef70321fc6b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28499
94834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2849994834
Directory /workspace/10.usbdev_nak_trans/latest


Test location /workspace/coverage/default/11.usbdev_pkt_sent.2847296278
Short name T589
Test name
Test status
Simulation time 8467221540 ps
CPU time 7.98 seconds
Started Apr 21 03:59:29 PM PDT 24
Finished Apr 21 03:59:37 PM PDT 24
Peak memory 203936 kb
Host smart-53fe8a55-11e7-48e5-bbb6-8e1f27f26b00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28472
96278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.2847296278
Directory /workspace/11.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/12.usbdev_in_iso.1189418340
Short name T381
Test name
Test status
Simulation time 8424616359 ps
CPU time 7.79 seconds
Started Apr 21 03:59:45 PM PDT 24
Finished Apr 21 03:59:53 PM PDT 24
Peak memory 204040 kb
Host smart-bec9a7e4-9f4d-4a87-8f11-0de45a3c74d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11894
18340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.1189418340
Directory /workspace/12.usbdev_in_iso/latest


Test location /workspace/coverage/default/12.usbdev_nak_trans.2455929082
Short name T109
Test name
Test status
Simulation time 8453982777 ps
CPU time 8.69 seconds
Started Apr 21 03:59:39 PM PDT 24
Finished Apr 21 03:59:48 PM PDT 24
Peak memory 204068 kb
Host smart-5d618726-0528-4bd6-ba49-cf041cf494e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24559
29082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.2455929082
Directory /workspace/12.usbdev_nak_trans/latest


Test location /workspace/coverage/default/13.usbdev_pending_in_trans.491597002
Short name T170
Test name
Test status
Simulation time 8412735489 ps
CPU time 8.13 seconds
Started Apr 21 03:59:53 PM PDT 24
Finished Apr 21 04:00:02 PM PDT 24
Peak memory 204220 kb
Host smart-2ee078bc-03cd-4f01-aac9-5f8e0369cea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49159
7002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.491597002
Directory /workspace/13.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.3986481127
Short name T286
Test name
Test status
Simulation time 8448067045 ps
CPU time 7.82 seconds
Started Apr 21 04:00:03 PM PDT 24
Finished Apr 21 04:00:11 PM PDT 24
Peak memory 204032 kb
Host smart-e6a81a73-d2f8-43c8-9626-9782ef3301b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39864
81127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.3986481127
Directory /workspace/14.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/15.usbdev_in_stall.4008937209
Short name T1100
Test name
Test status
Simulation time 8390095401 ps
CPU time 7.7 seconds
Started Apr 21 04:00:18 PM PDT 24
Finished Apr 21 04:00:26 PM PDT 24
Peak memory 204040 kb
Host smart-37a75c4a-0af9-4015-8f81-7e3010b45a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40089
37209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.4008937209
Directory /workspace/15.usbdev_in_stall/latest


Test location /workspace/coverage/default/15.usbdev_nak_trans.1319806276
Short name T107
Test name
Test status
Simulation time 8419476134 ps
CPU time 9.08 seconds
Started Apr 21 04:00:16 PM PDT 24
Finished Apr 21 04:00:26 PM PDT 24
Peak memory 204036 kb
Host smart-a0700f7a-ab60-4bad-a7f7-e7cc23d37613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13198
06276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1319806276
Directory /workspace/15.usbdev_nak_trans/latest


Test location /workspace/coverage/default/16.usbdev_nak_trans.2937906008
Short name T126
Test name
Test status
Simulation time 8425178909 ps
CPU time 7.93 seconds
Started Apr 21 04:00:24 PM PDT 24
Finished Apr 21 04:00:33 PM PDT 24
Peak memory 204068 kb
Host smart-a2b6b98d-6f0d-4ed1-923c-243aaa309c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29379
06008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.2937906008
Directory /workspace/16.usbdev_nak_trans/latest


Test location /workspace/coverage/default/16.usbdev_pending_in_trans.3605080969
Short name T200
Test name
Test status
Simulation time 8392973496 ps
CPU time 8.75 seconds
Started Apr 21 04:00:25 PM PDT 24
Finished Apr 21 04:00:34 PM PDT 24
Peak memory 204020 kb
Host smart-ea3e7bba-2737-43d7-ae9a-c7b1f329b404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36050
80969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.3605080969
Directory /workspace/16.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/16.usbdev_smoke.3486720525
Short name T177
Test name
Test status
Simulation time 8477159587 ps
CPU time 8.27 seconds
Started Apr 21 04:00:23 PM PDT 24
Finished Apr 21 04:00:31 PM PDT 24
Peak memory 204068 kb
Host smart-e0c1d8a4-9aa9-4883-acc7-5f830d897ac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34867
20525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.3486720525
Directory /workspace/16.usbdev_smoke/latest


Test location /workspace/coverage/default/17.usbdev_nak_trans.423498362
Short name T129
Test name
Test status
Simulation time 8462078238 ps
CPU time 7.88 seconds
Started Apr 21 04:00:33 PM PDT 24
Finished Apr 21 04:00:41 PM PDT 24
Peak memory 204040 kb
Host smart-b44ea64e-ab11-4e7e-85d0-ae31e4a5c83c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42349
8362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.423498362
Directory /workspace/17.usbdev_nak_trans/latest


Test location /workspace/coverage/default/17.usbdev_pkt_sent.3373574501
Short name T664
Test name
Test status
Simulation time 8425772963 ps
CPU time 7.96 seconds
Started Apr 21 04:00:33 PM PDT 24
Finished Apr 21 04:00:41 PM PDT 24
Peak memory 204076 kb
Host smart-ca113cce-d75b-44fa-a445-3ee9a15f20c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33735
74501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.3373574501
Directory /workspace/17.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/18.usbdev_pending_in_trans.4060679936
Short name T1013
Test name
Test status
Simulation time 8411740018 ps
CPU time 8.92 seconds
Started Apr 21 04:00:48 PM PDT 24
Finished Apr 21 04:00:57 PM PDT 24
Peak memory 204024 kb
Host smart-96a95f45-0633-458f-abb9-c487e3b9df09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40606
79936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.4060679936
Directory /workspace/18.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/19.usbdev_nak_trans.3176882968
Short name T119
Test name
Test status
Simulation time 8405480679 ps
CPU time 7.66 seconds
Started Apr 21 04:00:54 PM PDT 24
Finished Apr 21 04:01:02 PM PDT 24
Peak memory 204088 kb
Host smart-9c022f11-fd86-4e3f-b7bd-ede6610c92fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31768
82968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3176882968
Directory /workspace/19.usbdev_nak_trans/latest


Test location /workspace/coverage/default/2.usbdev_nak_trans.2911090541
Short name T833
Test name
Test status
Simulation time 8428139333 ps
CPU time 7.71 seconds
Started Apr 21 03:57:14 PM PDT 24
Finished Apr 21 03:57:22 PM PDT 24
Peak memory 204052 kb
Host smart-53f3cdeb-b893-47d8-ba4a-0ab0ef787551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29110
90541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.2911090541
Directory /workspace/2.usbdev_nak_trans/latest


Test location /workspace/coverage/default/21.usbdev_nak_trans.59632528
Short name T117
Test name
Test status
Simulation time 8416254647 ps
CPU time 8.47 seconds
Started Apr 21 04:01:11 PM PDT 24
Finished Apr 21 04:01:20 PM PDT 24
Peak memory 204008 kb
Host smart-bbeafa1e-1493-4b64-bf9d-e73bdadcc8e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59632
528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.59632528
Directory /workspace/21.usbdev_nak_trans/latest


Test location /workspace/coverage/default/24.usbdev_pending_in_trans.3098595852
Short name T803
Test name
Test status
Simulation time 8409766851 ps
CPU time 8.76 seconds
Started Apr 21 04:01:46 PM PDT 24
Finished Apr 21 04:01:55 PM PDT 24
Peak memory 204072 kb
Host smart-87235050-aa2a-470a-a6be-3de7263a8f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30985
95852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.3098595852
Directory /workspace/24.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/28.usbdev_nak_trans.915441839
Short name T1047
Test name
Test status
Simulation time 8423826796 ps
CPU time 9.07 seconds
Started Apr 21 04:02:17 PM PDT 24
Finished Apr 21 04:02:27 PM PDT 24
Peak memory 204024 kb
Host smart-73ac8a5c-145d-4ebb-af4a-66849aab38bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91544
1839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.915441839
Directory /workspace/28.usbdev_nak_trans/latest


Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.1634262176
Short name T22
Test name
Test status
Simulation time 8386674792 ps
CPU time 7.77 seconds
Started Apr 21 03:59:04 PM PDT 24
Finished Apr 21 03:59:12 PM PDT 24
Peak memory 203936 kb
Host smart-a39a82f2-b74c-4f5c-bd2b-25c2e86c7182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16342
62176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.1634262176
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2628063449
Short name T1453
Test name
Test status
Simulation time 193717741 ps
CPU time 2.13 seconds
Started Apr 21 01:02:52 PM PDT 24
Finished Apr 21 01:02:54 PM PDT 24
Peak memory 203656 kb
Host smart-6cab2c35-5160-4d67-bbea-1ff8d2b4c25c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2628063449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2628063449
Directory /workspace/0.usbdev_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3933465966
Short name T1390
Test name
Test status
Simulation time 241286716 ps
CPU time 3.84 seconds
Started Apr 21 01:03:07 PM PDT 24
Finished Apr 21 01:03:11 PM PDT 24
Peak memory 203648 kb
Host smart-248c61fc-2ed9-42fa-a42a-05d15217d487
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3933465966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.3933465966
Directory /workspace/0.usbdev_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.62686121
Short name T64
Test name
Test status
Simulation time 63408562 ps
CPU time 0.86 seconds
Started Apr 21 01:03:07 PM PDT 24
Finished Apr 21 01:03:08 PM PDT 24
Peak memory 203420 kb
Host smart-5b0fcfa2-d465-45b5-9c97-c2a9faa4ea00
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=62686121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.62686121
Directory /workspace/0.usbdev_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2196889898
Short name T1478
Test name
Test status
Simulation time 170551363 ps
CPU time 1.98 seconds
Started Apr 21 01:03:06 PM PDT 24
Finished Apr 21 01:03:09 PM PDT 24
Peak memory 211968 kb
Host smart-947434a8-df9b-4672-8c83-650ec9921a42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196889898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.2196889898
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2252938130
Short name T232
Test name
Test status
Simulation time 47785848 ps
CPU time 0.92 seconds
Started Apr 21 01:03:01 PM PDT 24
Finished Apr 21 01:03:02 PM PDT 24
Peak memory 203716 kb
Host smart-d038c645-5e3e-4a1e-8126-d520fcdeae1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2252938130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2252938130
Directory /workspace/0.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.262615957
Short name T231
Test name
Test status
Simulation time 71595039 ps
CPU time 2.2 seconds
Started Apr 21 01:02:58 PM PDT 24
Finished Apr 21 01:03:01 PM PDT 24
Peak memory 211880 kb
Host smart-04bff07a-e04e-494e-9815-db934dcd1969
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=262615957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.262615957
Directory /workspace/0.usbdev_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3792877759
Short name T1384
Test name
Test status
Simulation time 150632753 ps
CPU time 3.9 seconds
Started Apr 21 01:02:52 PM PDT 24
Finished Apr 21 01:02:56 PM PDT 24
Peak memory 203712 kb
Host smart-ec6b1d6f-f861-4c45-9903-aed33f9d5353
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3792877759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3792877759
Directory /workspace/0.usbdev_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.4191989927
Short name T1458
Test name
Test status
Simulation time 66260749 ps
CPU time 1.34 seconds
Started Apr 21 01:02:59 PM PDT 24
Finished Apr 21 01:03:01 PM PDT 24
Peak memory 203680 kb
Host smart-3c2710ac-684b-4b62-8e9a-036d261c9644
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4191989927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.4191989927
Directory /workspace/0.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.236987871
Short name T230
Test name
Test status
Simulation time 136669920 ps
CPU time 3.31 seconds
Started Apr 21 01:02:51 PM PDT 24
Finished Apr 21 01:02:55 PM PDT 24
Peak memory 203588 kb
Host smart-e6c419f1-3e23-4230-b77f-d48ffdfc4249
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=236987871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.236987871
Directory /workspace/1.usbdev_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2561418822
Short name T237
Test name
Test status
Simulation time 1453311180 ps
CPU time 8.65 seconds
Started Apr 21 01:02:53 PM PDT 24
Finished Apr 21 01:03:02 PM PDT 24
Peak memory 203600 kb
Host smart-7a902824-70d6-40bf-a114-276cb844207f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2561418822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.2561418822
Directory /workspace/1.usbdev_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1964789921
Short name T1475
Test name
Test status
Simulation time 90212655 ps
CPU time 1.4 seconds
Started Apr 21 01:02:49 PM PDT 24
Finished Apr 21 01:02:51 PM PDT 24
Peak memory 212028 kb
Host smart-690b63bf-7ef6-4dc0-b278-68b9ec00dca9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964789921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.1964789921
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.712774564
Short name T1450
Test name
Test status
Simulation time 77919840 ps
CPU time 0.86 seconds
Started Apr 21 01:02:51 PM PDT 24
Finished Apr 21 01:02:53 PM PDT 24
Peak memory 203464 kb
Host smart-97dd0d97-7f47-4423-a3d3-4999080a770a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=712774564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.712774564
Directory /workspace/1.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2678919442
Short name T1408
Test name
Test status
Simulation time 59770439 ps
CPU time 0.7 seconds
Started Apr 21 01:02:53 PM PDT 24
Finished Apr 21 01:02:54 PM PDT 24
Peak memory 202924 kb
Host smart-d6ac752a-1d92-4443-a836-8414c50f8e88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2678919442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2678919442
Directory /workspace/1.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2923598460
Short name T1423
Test name
Test status
Simulation time 116630435 ps
CPU time 1.55 seconds
Started Apr 21 01:02:44 PM PDT 24
Finished Apr 21 01:02:46 PM PDT 24
Peak memory 203764 kb
Host smart-6641fa14-28f1-48ca-ab95-5e4f7589f6d7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2923598460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2923598460
Directory /workspace/1.usbdev_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.932012252
Short name T1437
Test name
Test status
Simulation time 471162928 ps
CPU time 4.4 seconds
Started Apr 21 01:03:00 PM PDT 24
Finished Apr 21 01:03:05 PM PDT 24
Peak memory 203636 kb
Host smart-e268c7d0-239a-4d99-b2a1-9a33d94c2747
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=932012252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.932012252
Directory /workspace/1.usbdev_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2183001059
Short name T1394
Test name
Test status
Simulation time 71548414 ps
CPU time 1.11 seconds
Started Apr 21 01:03:01 PM PDT 24
Finished Apr 21 01:03:03 PM PDT 24
Peak memory 203700 kb
Host smart-bed1591f-5314-4061-a783-9e5f3510e135
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2183001059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2183001059
Directory /workspace/1.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.4031305947
Short name T1463
Test name
Test status
Simulation time 287734445 ps
CPU time 2.56 seconds
Started Apr 21 01:02:57 PM PDT 24
Finished Apr 21 01:03:00 PM PDT 24
Peak memory 203760 kb
Host smart-ba74d56c-fa94-4889-ae9d-92dcb3959e50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4031305947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.4031305947
Directory /workspace/1.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.634921905
Short name T222
Test name
Test status
Simulation time 72292404 ps
CPU time 1.14 seconds
Started Apr 21 01:02:59 PM PDT 24
Finished Apr 21 01:03:00 PM PDT 24
Peak memory 213256 kb
Host smart-2e88cff6-c30c-4c99-9bcb-26a6c750ea8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634921905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbde
v_csr_mem_rw_with_rand_reset.634921905
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.641423966
Short name T1447
Test name
Test status
Simulation time 66931106 ps
CPU time 1.03 seconds
Started Apr 21 01:02:55 PM PDT 24
Finished Apr 21 01:02:56 PM PDT 24
Peak memory 203676 kb
Host smart-1db95da2-756d-4b13-92d6-513056080e2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=641423966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.641423966
Directory /workspace/10.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1240070380
Short name T1417
Test name
Test status
Simulation time 90007651 ps
CPU time 0.69 seconds
Started Apr 21 01:02:59 PM PDT 24
Finished Apr 21 01:03:00 PM PDT 24
Peak memory 202924 kb
Host smart-92bed45c-a5b3-4857-97f0-ce970f4ce305
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1240070380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.1240070380
Directory /workspace/10.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2261215723
Short name T1433
Test name
Test status
Simulation time 154053450 ps
CPU time 1.46 seconds
Started Apr 21 01:02:56 PM PDT 24
Finished Apr 21 01:02:58 PM PDT 24
Peak memory 203784 kb
Host smart-c56c5862-ab51-4c51-bf5f-0ffc98f90129
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2261215723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2261215723
Directory /workspace/10.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2711340807
Short name T219
Test name
Test status
Simulation time 215978163 ps
CPU time 2.75 seconds
Started Apr 21 01:02:58 PM PDT 24
Finished Apr 21 01:03:01 PM PDT 24
Peak memory 203804 kb
Host smart-fcf4c190-99fa-499d-b4e8-a12224459f3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2711340807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2711340807
Directory /workspace/10.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3887871186
Short name T272
Test name
Test status
Simulation time 424667937 ps
CPU time 3.07 seconds
Started Apr 21 01:03:10 PM PDT 24
Finished Apr 21 01:03:13 PM PDT 24
Peak memory 203696 kb
Host smart-1ab33598-76ac-4feb-947c-973a63cad94d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3887871186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.3887871186
Directory /workspace/10.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.266335738
Short name T1411
Test name
Test status
Simulation time 165099059 ps
CPU time 2.12 seconds
Started Apr 21 01:03:10 PM PDT 24
Finished Apr 21 01:03:12 PM PDT 24
Peak memory 215620 kb
Host smart-b9bb5b1d-c945-479a-9349-22919e0c765f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266335738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbde
v_csr_mem_rw_with_rand_reset.266335738
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3837927386
Short name T1439
Test name
Test status
Simulation time 27812159 ps
CPU time 0.78 seconds
Started Apr 21 01:03:04 PM PDT 24
Finished Apr 21 01:03:05 PM PDT 24
Peak memory 203480 kb
Host smart-5282acd8-f004-4ef8-94e5-2abd738f69dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3837927386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3837927386
Directory /workspace/11.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1662241538
Short name T1466
Test name
Test status
Simulation time 32525186 ps
CPU time 0.61 seconds
Started Apr 21 01:03:53 PM PDT 24
Finished Apr 21 01:03:54 PM PDT 24
Peak memory 202892 kb
Host smart-801d1a3a-1c38-4061-94d6-2d7da4b182f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1662241538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1662241538
Directory /workspace/11.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2314040412
Short name T1389
Test name
Test status
Simulation time 155777634 ps
CPU time 1.54 seconds
Started Apr 21 01:02:56 PM PDT 24
Finished Apr 21 01:02:58 PM PDT 24
Peak memory 203808 kb
Host smart-1e23b251-c32b-4ed2-ade9-6451445b4b41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2314040412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.2314040412
Directory /workspace/11.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.4037790975
Short name T1451
Test name
Test status
Simulation time 88016493 ps
CPU time 1.94 seconds
Started Apr 21 01:03:02 PM PDT 24
Finished Apr 21 01:03:05 PM PDT 24
Peak memory 203824 kb
Host smart-4134eda4-f2cb-4c62-b805-c099144a0888
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4037790975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.4037790975
Directory /workspace/11.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1086630031
Short name T1414
Test name
Test status
Simulation time 691934360 ps
CPU time 2.7 seconds
Started Apr 21 01:03:01 PM PDT 24
Finished Apr 21 01:03:05 PM PDT 24
Peak memory 203764 kb
Host smart-d97df395-85d8-4a00-8757-22126e2c378e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1086630031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1086630031
Directory /workspace/11.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1450530486
Short name T1400
Test name
Test status
Simulation time 156013018 ps
CPU time 1.81 seconds
Started Apr 21 01:03:01 PM PDT 24
Finished Apr 21 01:03:04 PM PDT 24
Peak memory 212024 kb
Host smart-9c170315-56e5-4bad-8ddf-ced9aa4ee68d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450530486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.1450530486
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3786670445
Short name T1388
Test name
Test status
Simulation time 90126027 ps
CPU time 0.87 seconds
Started Apr 21 01:03:14 PM PDT 24
Finished Apr 21 01:03:15 PM PDT 24
Peak memory 203420 kb
Host smart-ee49e09c-af21-441b-9a84-7f4f92e59d8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3786670445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3786670445
Directory /workspace/12.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3365820866
Short name T243
Test name
Test status
Simulation time 200526465 ps
CPU time 1.78 seconds
Started Apr 21 01:03:05 PM PDT 24
Finished Apr 21 01:03:07 PM PDT 24
Peak memory 203676 kb
Host smart-7f130b8d-ea07-4425-b7ab-ccb5cd1cac9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3365820866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3365820866
Directory /workspace/12.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3792328593
Short name T1436
Test name
Test status
Simulation time 219158725 ps
CPU time 2.63 seconds
Started Apr 21 01:03:06 PM PDT 24
Finished Apr 21 01:03:09 PM PDT 24
Peak memory 203760 kb
Host smart-0e502210-41bd-4e53-bdf4-06676538764f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3792328593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.3792328593
Directory /workspace/12.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.21288359
Short name T59
Test name
Test status
Simulation time 296020020 ps
CPU time 2.55 seconds
Started Apr 21 01:03:00 PM PDT 24
Finished Apr 21 01:03:03 PM PDT 24
Peak memory 203716 kb
Host smart-e4af33f2-5910-4a27-b8b8-2ab2b0434e48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=21288359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.21288359
Directory /workspace/12.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1356595499
Short name T1385
Test name
Test status
Simulation time 71808745 ps
CPU time 1.44 seconds
Started Apr 21 01:03:04 PM PDT 24
Finished Apr 21 01:03:06 PM PDT 24
Peak memory 212004 kb
Host smart-40fc4580-5b32-4ef5-804f-f7305a55990d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356595499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1356595499
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3536077283
Short name T1428
Test name
Test status
Simulation time 32792259 ps
CPU time 0.85 seconds
Started Apr 21 01:03:01 PM PDT 24
Finished Apr 21 01:03:03 PM PDT 24
Peak memory 203472 kb
Host smart-b8e15800-3d4e-4379-b2f8-dcef49d2867c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3536077283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3536077283
Directory /workspace/13.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1209988402
Short name T1392
Test name
Test status
Simulation time 111991482 ps
CPU time 0.72 seconds
Started Apr 21 01:02:53 PM PDT 24
Finished Apr 21 01:02:54 PM PDT 24
Peak memory 202864 kb
Host smart-4bdd5778-d525-4edc-8eed-1c15fae619b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1209988402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1209988402
Directory /workspace/13.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1319014503
Short name T1471
Test name
Test status
Simulation time 112941907 ps
CPU time 1.17 seconds
Started Apr 21 01:02:59 PM PDT 24
Finished Apr 21 01:03:00 PM PDT 24
Peak memory 203812 kb
Host smart-bf16f734-4141-4ba2-a829-2dba94c4fa1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1319014503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1319014503
Directory /workspace/13.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3166868616
Short name T217
Test name
Test status
Simulation time 176624085 ps
CPU time 2.09 seconds
Started Apr 21 01:03:02 PM PDT 24
Finished Apr 21 01:03:05 PM PDT 24
Peak memory 203760 kb
Host smart-41cabae0-40b2-4274-8d9d-23a2bb69aac8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3166868616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3166868616
Directory /workspace/13.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.972751214
Short name T1435
Test name
Test status
Simulation time 59926527 ps
CPU time 1.35 seconds
Started Apr 21 01:03:05 PM PDT 24
Finished Apr 21 01:03:06 PM PDT 24
Peak memory 211916 kb
Host smart-340f2120-151b-4885-a8dc-034382bf0cff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972751214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbde
v_csr_mem_rw_with_rand_reset.972751214
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2695396157
Short name T102
Test name
Test status
Simulation time 50459341 ps
CPU time 0.81 seconds
Started Apr 21 01:03:11 PM PDT 24
Finished Apr 21 01:03:12 PM PDT 24
Peak memory 203424 kb
Host smart-11435bd7-3e74-4229-917f-a073244e460a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2695396157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.2695396157
Directory /workspace/14.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3247069553
Short name T261
Test name
Test status
Simulation time 39095581 ps
CPU time 0.75 seconds
Started Apr 21 01:03:02 PM PDT 24
Finished Apr 21 01:03:04 PM PDT 24
Peak memory 202988 kb
Host smart-785ed90b-41e1-402f-bb57-d4bac95ddda2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3247069553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3247069553
Directory /workspace/14.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.605293141
Short name T66
Test name
Test status
Simulation time 180894150 ps
CPU time 1.21 seconds
Started Apr 21 01:03:01 PM PDT 24
Finished Apr 21 01:03:03 PM PDT 24
Peak memory 203752 kb
Host smart-536b4804-126a-4c53-879e-135fe0d21f1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=605293141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.605293141
Directory /workspace/14.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1983299560
Short name T1427
Test name
Test status
Simulation time 124607135 ps
CPU time 2.9 seconds
Started Apr 21 01:03:06 PM PDT 24
Finished Apr 21 01:03:10 PM PDT 24
Peak memory 203408 kb
Host smart-cdbae058-f5a3-4db9-88fb-195b427ff942
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1983299560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.1983299560
Directory /workspace/14.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.4213430765
Short name T268
Test name
Test status
Simulation time 532116265 ps
CPU time 3.08 seconds
Started Apr 21 01:03:15 PM PDT 24
Finished Apr 21 01:03:19 PM PDT 24
Peak memory 203744 kb
Host smart-1efd6175-b34e-4596-bfdf-a33d8acde699
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4213430765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.4213430765
Directory /workspace/14.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1191511826
Short name T249
Test name
Test status
Simulation time 149874693 ps
CPU time 1.72 seconds
Started Apr 21 01:02:58 PM PDT 24
Finished Apr 21 01:03:00 PM PDT 24
Peak memory 215500 kb
Host smart-229d4264-8529-4711-87e7-43a471f5945d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191511826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.1191511826
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.674638904
Short name T1432
Test name
Test status
Simulation time 76037210 ps
CPU time 0.97 seconds
Started Apr 21 01:03:19 PM PDT 24
Finished Apr 21 01:03:21 PM PDT 24
Peak memory 203668 kb
Host smart-646b9721-18d8-4bc2-bd07-a47599661c82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=674638904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.674638904
Directory /workspace/15.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2849329389
Short name T1431
Test name
Test status
Simulation time 48392702 ps
CPU time 0.65 seconds
Started Apr 21 01:03:14 PM PDT 24
Finished Apr 21 01:03:15 PM PDT 24
Peak memory 202984 kb
Host smart-1a1c84ba-f915-4d52-948f-6a833f1db3e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2849329389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2849329389
Directory /workspace/15.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.714225205
Short name T1461
Test name
Test status
Simulation time 83137537 ps
CPU time 1.08 seconds
Started Apr 21 01:03:07 PM PDT 24
Finished Apr 21 01:03:09 PM PDT 24
Peak memory 203620 kb
Host smart-d1f8292f-2683-454e-b82e-694d1703e7b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=714225205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.714225205
Directory /workspace/15.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1085067191
Short name T1459
Test name
Test status
Simulation time 370250915 ps
CPU time 3.26 seconds
Started Apr 21 01:03:11 PM PDT 24
Finished Apr 21 01:03:14 PM PDT 24
Peak memory 203712 kb
Host smart-d50706ba-14e1-4a1f-a7ae-08364dee1cf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1085067191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1085067191
Directory /workspace/15.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1307983743
Short name T1422
Test name
Test status
Simulation time 179004429 ps
CPU time 1.54 seconds
Started Apr 21 01:03:03 PM PDT 24
Finished Apr 21 01:03:06 PM PDT 24
Peak memory 212084 kb
Host smart-a96b810e-43e6-4f73-bfc5-8435869c3098
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307983743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.1307983743
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.4241369970
Short name T1424
Test name
Test status
Simulation time 34177665 ps
CPU time 0.83 seconds
Started Apr 21 01:03:06 PM PDT 24
Finished Apr 21 01:03:07 PM PDT 24
Peak memory 203456 kb
Host smart-b5fc51d8-9a20-4ace-9ae2-04bcd88b404a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4241369970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.4241369970
Directory /workspace/16.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2652589438
Short name T266
Test name
Test status
Simulation time 26832802 ps
CPU time 0.62 seconds
Started Apr 21 01:03:09 PM PDT 24
Finished Apr 21 01:03:10 PM PDT 24
Peak memory 202892 kb
Host smart-965e04d9-2ffc-4c8b-b210-8d1dc8049b71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2652589438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.2652589438
Directory /workspace/16.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1368191904
Short name T250
Test name
Test status
Simulation time 345304343 ps
CPU time 2 seconds
Started Apr 21 01:03:16 PM PDT 24
Finished Apr 21 01:03:18 PM PDT 24
Peak memory 203736 kb
Host smart-75cb579e-b92b-458c-b065-ddc7752aec8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1368191904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.1368191904
Directory /workspace/16.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3486878267
Short name T1398
Test name
Test status
Simulation time 151030597 ps
CPU time 2.94 seconds
Started Apr 21 01:03:05 PM PDT 24
Finished Apr 21 01:03:09 PM PDT 24
Peak memory 203840 kb
Host smart-40f0c7d8-b3b3-451a-8840-7d786a2915d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3486878267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3486878267
Directory /workspace/16.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3988926770
Short name T248
Test name
Test status
Simulation time 328141752 ps
CPU time 3 seconds
Started Apr 21 01:03:03 PM PDT 24
Finished Apr 21 01:03:06 PM PDT 24
Peak memory 203796 kb
Host smart-2c079f9c-1b18-41bd-b6e2-60a6090e580e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3988926770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3988926770
Directory /workspace/16.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1929462643
Short name T221
Test name
Test status
Simulation time 84214173 ps
CPU time 1.14 seconds
Started Apr 21 01:03:23 PM PDT 24
Finished Apr 21 01:03:25 PM PDT 24
Peak memory 212024 kb
Host smart-d3625509-5798-4a8f-8236-a9ef9557a470
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929462643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1929462643
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.455641211
Short name T1469
Test name
Test status
Simulation time 41380210 ps
CPU time 0.99 seconds
Started Apr 21 01:03:00 PM PDT 24
Finished Apr 21 01:03:01 PM PDT 24
Peak memory 203740 kb
Host smart-8e5227a8-c263-44b9-a078-84182161c887
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=455641211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.455641211
Directory /workspace/17.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.190303702
Short name T70
Test name
Test status
Simulation time 56442359 ps
CPU time 0.73 seconds
Started Apr 21 01:03:14 PM PDT 24
Finished Apr 21 01:03:15 PM PDT 24
Peak memory 202920 kb
Host smart-ad15a2c3-dc51-4bdd-9a83-12e48e1a5361
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=190303702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.190303702
Directory /workspace/17.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.757337235
Short name T1443
Test name
Test status
Simulation time 561755408 ps
CPU time 1.87 seconds
Started Apr 21 01:03:02 PM PDT 24
Finished Apr 21 01:03:05 PM PDT 24
Peak memory 203696 kb
Host smart-be37414a-c33e-4cca-ace3-45a4e32338ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=757337235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.757337235
Directory /workspace/17.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2563019269
Short name T216
Test name
Test status
Simulation time 85994148 ps
CPU time 1.87 seconds
Started Apr 21 01:03:13 PM PDT 24
Finished Apr 21 01:03:15 PM PDT 24
Peak memory 203776 kb
Host smart-0429ed3a-0f7f-40bb-9ce6-a55f301864cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2563019269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2563019269
Directory /workspace/17.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.905050289
Short name T1455
Test name
Test status
Simulation time 218278806 ps
CPU time 2.42 seconds
Started Apr 21 01:03:03 PM PDT 24
Finished Apr 21 01:03:06 PM PDT 24
Peak memory 203680 kb
Host smart-b3889262-c448-42b0-8166-34de45c8a723
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=905050289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.905050289
Directory /workspace/17.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1933343423
Short name T100
Test name
Test status
Simulation time 88168660 ps
CPU time 1.27 seconds
Started Apr 21 01:03:02 PM PDT 24
Finished Apr 21 01:03:05 PM PDT 24
Peak memory 213020 kb
Host smart-b87e10b1-c064-487c-b3bd-63f26e564175
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933343423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.1933343423
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2623355250
Short name T235
Test name
Test status
Simulation time 35265662 ps
CPU time 0.96 seconds
Started Apr 21 01:03:17 PM PDT 24
Finished Apr 21 01:03:19 PM PDT 24
Peak memory 203684 kb
Host smart-b4918457-ebc9-4afa-95f5-e1eed4492fff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2623355250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2623355250
Directory /workspace/18.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.376390087
Short name T262
Test name
Test status
Simulation time 55906849 ps
CPU time 0.66 seconds
Started Apr 21 01:03:09 PM PDT 24
Finished Apr 21 01:03:10 PM PDT 24
Peak memory 202980 kb
Host smart-2d39d111-f93c-4035-b5cf-896c66392e3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=376390087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.376390087
Directory /workspace/18.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.49366132
Short name T97
Test name
Test status
Simulation time 69704592 ps
CPU time 1.08 seconds
Started Apr 21 01:03:05 PM PDT 24
Finished Apr 21 01:03:07 PM PDT 24
Peak memory 203736 kb
Host smart-952007d9-f8e1-4219-9a9a-a591c1ce6b92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=49366132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.49366132
Directory /workspace/18.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.4101459285
Short name T211
Test name
Test status
Simulation time 70455725 ps
CPU time 1.41 seconds
Started Apr 21 01:03:14 PM PDT 24
Finished Apr 21 01:03:16 PM PDT 24
Peak memory 203700 kb
Host smart-ef4aa323-d20c-48bb-8155-f60906922b13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4101459285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.4101459285
Directory /workspace/18.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2293499077
Short name T58
Test name
Test status
Simulation time 200954823 ps
CPU time 2.28 seconds
Started Apr 21 01:03:05 PM PDT 24
Finished Apr 21 01:03:08 PM PDT 24
Peak memory 203772 kb
Host smart-8c629d07-e1ba-44a8-bb10-104ee75ae367
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2293499077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2293499077
Directory /workspace/18.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.652374138
Short name T240
Test name
Test status
Simulation time 45151022 ps
CPU time 0.75 seconds
Started Apr 21 01:03:06 PM PDT 24
Finished Apr 21 01:03:08 PM PDT 24
Peak memory 203408 kb
Host smart-25af6e0a-a037-4041-8f8d-2474c3041ea8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=652374138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.652374138
Directory /workspace/19.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3548403257
Short name T1402
Test name
Test status
Simulation time 36432374 ps
CPU time 0.63 seconds
Started Apr 21 01:03:24 PM PDT 24
Finished Apr 21 01:03:26 PM PDT 24
Peak memory 202896 kb
Host smart-7c624c27-9d77-43e7-bb30-d819bf194864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3548403257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3548403257
Directory /workspace/19.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1100117825
Short name T1457
Test name
Test status
Simulation time 121133493 ps
CPU time 1.35 seconds
Started Apr 21 01:03:08 PM PDT 24
Finished Apr 21 01:03:09 PM PDT 24
Peak memory 203728 kb
Host smart-a359145e-f7c2-4b00-86af-15a25da8a6f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1100117825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.1100117825
Directory /workspace/19.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1827730140
Short name T204
Test name
Test status
Simulation time 60215288 ps
CPU time 1.9 seconds
Started Apr 21 01:03:03 PM PDT 24
Finished Apr 21 01:03:06 PM PDT 24
Peak memory 203788 kb
Host smart-1c5b3f8e-434c-4e77-ad1a-35d0b36a7d2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1827730140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1827730140
Directory /workspace/19.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3572985921
Short name T206
Test name
Test status
Simulation time 261251497 ps
CPU time 2.47 seconds
Started Apr 21 01:03:13 PM PDT 24
Finished Apr 21 01:03:16 PM PDT 24
Peak memory 203768 kb
Host smart-2d1a533c-99ed-4d8b-917c-c7c95786759d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3572985921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.3572985921
Directory /workspace/19.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.4255501612
Short name T1397
Test name
Test status
Simulation time 167593304 ps
CPU time 2.01 seconds
Started Apr 21 01:02:49 PM PDT 24
Finished Apr 21 01:02:52 PM PDT 24
Peak memory 203604 kb
Host smart-3516c826-18f7-4878-8ea3-8da506cd2e26
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4255501612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.4255501612
Directory /workspace/2.usbdev_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1903148232
Short name T236
Test name
Test status
Simulation time 547578039 ps
CPU time 4.42 seconds
Started Apr 21 01:02:51 PM PDT 24
Finished Apr 21 01:02:55 PM PDT 24
Peak memory 203700 kb
Host smart-96a9b924-ff40-44d4-84a0-761a41caa213
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1903148232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1903148232
Directory /workspace/2.usbdev_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3712557581
Short name T220
Test name
Test status
Simulation time 50120168 ps
CPU time 0.8 seconds
Started Apr 21 01:03:02 PM PDT 24
Finished Apr 21 01:03:04 PM PDT 24
Peak memory 203432 kb
Host smart-6696a976-bb37-413f-a99c-4aff1172dcc9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3712557581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3712557581
Directory /workspace/2.usbdev_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3014663292
Short name T1403
Test name
Test status
Simulation time 144090240 ps
CPU time 1.71 seconds
Started Apr 21 01:02:56 PM PDT 24
Finished Apr 21 01:02:58 PM PDT 24
Peak memory 215096 kb
Host smart-8115f57a-3a1f-494f-aa08-748dc78977f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014663292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.3014663292
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2879861582
Short name T1456
Test name
Test status
Simulation time 34839229 ps
CPU time 0.66 seconds
Started Apr 21 01:02:53 PM PDT 24
Finished Apr 21 01:02:54 PM PDT 24
Peak memory 202892 kb
Host smart-31204d8d-3765-4e98-ad0f-88ff6ff063b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2879861582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2879861582
Directory /workspace/2.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.68762630
Short name T238
Test name
Test status
Simulation time 170874985 ps
CPU time 2.31 seconds
Started Apr 21 01:03:00 PM PDT 24
Finished Apr 21 01:03:02 PM PDT 24
Peak memory 211940 kb
Host smart-9d029ffb-f625-471c-ad89-f00f983b79a3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=68762630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.68762630
Directory /workspace/2.usbdev_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2996231187
Short name T1438
Test name
Test status
Simulation time 292307186 ps
CPU time 2.55 seconds
Started Apr 21 01:02:43 PM PDT 24
Finished Apr 21 01:02:46 PM PDT 24
Peak memory 203628 kb
Host smart-f3423bc3-8076-4119-b35b-d3cc2fb210e6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2996231187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2996231187
Directory /workspace/2.usbdev_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1002292731
Short name T242
Test name
Test status
Simulation time 113381823 ps
CPU time 1.58 seconds
Started Apr 21 01:02:53 PM PDT 24
Finished Apr 21 01:02:55 PM PDT 24
Peak memory 203720 kb
Host smart-d77fcec9-6820-4a7b-94ff-4088947aae22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1002292731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.1002292731
Directory /workspace/2.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3864776386
Short name T1449
Test name
Test status
Simulation time 273961472 ps
CPU time 3.18 seconds
Started Apr 21 01:03:06 PM PDT 24
Finished Apr 21 01:03:10 PM PDT 24
Peak memory 203488 kb
Host smart-344fb26d-cef1-45c5-8860-28035c978615
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3864776386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.3864776386
Directory /workspace/2.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.49595031
Short name T1479
Test name
Test status
Simulation time 30476957 ps
CPU time 0.69 seconds
Started Apr 21 01:03:05 PM PDT 24
Finished Apr 21 01:03:06 PM PDT 24
Peak memory 202980 kb
Host smart-0989cb88-bbee-4b13-ad40-acbce4170090
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=49595031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.49595031
Directory /workspace/20.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3926499165
Short name T1468
Test name
Test status
Simulation time 35420293 ps
CPU time 0.73 seconds
Started Apr 21 01:03:05 PM PDT 24
Finished Apr 21 01:03:06 PM PDT 24
Peak memory 203220 kb
Host smart-55233f35-d4eb-41d3-b7c5-f32c12facbbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3926499165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.3926499165
Directory /workspace/21.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2496310536
Short name T264
Test name
Test status
Simulation time 52879838 ps
CPU time 0.73 seconds
Started Apr 21 01:03:07 PM PDT 24
Finished Apr 21 01:03:08 PM PDT 24
Peak memory 202900 kb
Host smart-ce92d3e6-a558-4d63-b0a1-b360db0ff394
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2496310536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2496310536
Directory /workspace/22.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3926946518
Short name T1467
Test name
Test status
Simulation time 36773827 ps
CPU time 0.63 seconds
Started Apr 21 01:03:20 PM PDT 24
Finished Apr 21 01:03:21 PM PDT 24
Peak memory 202824 kb
Host smart-1ff96610-31c6-4492-9654-e0d51e85d018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3926946518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3926946518
Directory /workspace/23.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1499312998
Short name T1429
Test name
Test status
Simulation time 36820787 ps
CPU time 0.69 seconds
Started Apr 21 01:03:05 PM PDT 24
Finished Apr 21 01:03:06 PM PDT 24
Peak memory 202984 kb
Host smart-279b9058-54c8-4c7a-a015-d39cabefd3b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1499312998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.1499312998
Directory /workspace/24.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2897970214
Short name T258
Test name
Test status
Simulation time 77829138 ps
CPU time 0.67 seconds
Started Apr 21 01:03:15 PM PDT 24
Finished Apr 21 01:03:16 PM PDT 24
Peak memory 202892 kb
Host smart-e196b19b-efb2-4c9a-ba14-e8f8ec07d614
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2897970214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2897970214
Directory /workspace/25.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1734323628
Short name T257
Test name
Test status
Simulation time 36529737 ps
CPU time 0.69 seconds
Started Apr 21 01:03:07 PM PDT 24
Finished Apr 21 01:03:08 PM PDT 24
Peak memory 202928 kb
Host smart-45a0482a-06c7-40d2-9c8f-85eacba6cd96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1734323628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1734323628
Directory /workspace/26.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2942841989
Short name T1404
Test name
Test status
Simulation time 97303449 ps
CPU time 0.71 seconds
Started Apr 21 01:03:16 PM PDT 24
Finished Apr 21 01:03:17 PM PDT 24
Peak memory 202968 kb
Host smart-c7cbeec8-532e-40dd-a06d-3a601db33790
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2942841989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2942841989
Directory /workspace/28.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1164485158
Short name T1445
Test name
Test status
Simulation time 52448924 ps
CPU time 0.65 seconds
Started Apr 21 01:03:04 PM PDT 24
Finished Apr 21 01:03:06 PM PDT 24
Peak memory 202908 kb
Host smart-79fffeeb-4cde-473f-8700-041c09fba98f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1164485158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1164485158
Directory /workspace/29.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3483700797
Short name T1409
Test name
Test status
Simulation time 72033486 ps
CPU time 1.97 seconds
Started Apr 21 01:03:01 PM PDT 24
Finished Apr 21 01:03:04 PM PDT 24
Peak memory 203720 kb
Host smart-7d85f7af-ddce-406e-b06d-214de250f8af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3483700797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3483700797
Directory /workspace/3.usbdev_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.4096487091
Short name T1383
Test name
Test status
Simulation time 538804013 ps
CPU time 4.41 seconds
Started Apr 21 01:02:59 PM PDT 24
Finished Apr 21 01:03:04 PM PDT 24
Peak memory 203644 kb
Host smart-79c0090c-7ad7-449d-b586-e040b3c3fdfb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4096487091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.4096487091
Directory /workspace/3.usbdev_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3333099690
Short name T1465
Test name
Test status
Simulation time 45390356 ps
CPU time 0.77 seconds
Started Apr 21 01:02:57 PM PDT 24
Finished Apr 21 01:02:58 PM PDT 24
Peak memory 203420 kb
Host smart-6f72712f-8a72-4e18-9447-30d0896f2cba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3333099690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3333099690
Directory /workspace/3.usbdev_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1835632994
Short name T247
Test name
Test status
Simulation time 195993343 ps
CPU time 1.28 seconds
Started Apr 21 01:02:52 PM PDT 24
Finished Apr 21 01:02:54 PM PDT 24
Peak memory 213864 kb
Host smart-1aeef994-ceac-4eb3-a6c0-649ebc56e1ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835632994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.1835632994
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2356989629
Short name T1460
Test name
Test status
Simulation time 61647051 ps
CPU time 0.91 seconds
Started Apr 21 01:02:56 PM PDT 24
Finished Apr 21 01:02:57 PM PDT 24
Peak memory 203656 kb
Host smart-33c00413-82c4-41c6-982f-dbc51e1df9ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2356989629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2356989629
Directory /workspace/3.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1682837070
Short name T1464
Test name
Test status
Simulation time 36825938 ps
CPU time 0.64 seconds
Started Apr 21 01:02:59 PM PDT 24
Finished Apr 21 01:03:00 PM PDT 24
Peak memory 202908 kb
Host smart-86d01121-efd0-4a87-8969-a9d154451344
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1682837070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1682837070
Directory /workspace/3.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1050708258
Short name T233
Test name
Test status
Simulation time 100594508 ps
CPU time 1.34 seconds
Started Apr 21 01:02:57 PM PDT 24
Finished Apr 21 01:02:58 PM PDT 24
Peak memory 203756 kb
Host smart-0ad038c7-396f-49ea-b295-9d4ffd9960ed
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1050708258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1050708258
Directory /workspace/3.usbdev_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.647162005
Short name T1386
Test name
Test status
Simulation time 704977510 ps
CPU time 4.99 seconds
Started Apr 21 01:02:57 PM PDT 24
Finished Apr 21 01:03:02 PM PDT 24
Peak memory 203624 kb
Host smart-ab5c1eb4-def4-423c-b221-cece8cac2976
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=647162005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.647162005
Directory /workspace/3.usbdev_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3959618224
Short name T241
Test name
Test status
Simulation time 90803560 ps
CPU time 1.17 seconds
Started Apr 21 01:02:53 PM PDT 24
Finished Apr 21 01:02:54 PM PDT 24
Peak memory 203724 kb
Host smart-cd0f4bcb-f8ff-43d8-9131-b27f1902f2ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3959618224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.3959618224
Directory /workspace/3.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1122483060
Short name T1420
Test name
Test status
Simulation time 254192575 ps
CPU time 3.46 seconds
Started Apr 21 01:02:58 PM PDT 24
Finished Apr 21 01:03:01 PM PDT 24
Peak memory 203808 kb
Host smart-a4c3049f-4d4d-4a51-ae51-96697b0d2af8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1122483060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.1122483060
Directory /workspace/3.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1084133738
Short name T269
Test name
Test status
Simulation time 343457063 ps
CPU time 2.78 seconds
Started Apr 21 01:03:01 PM PDT 24
Finished Apr 21 01:03:04 PM PDT 24
Peak memory 203792 kb
Host smart-ebacf57d-6d1d-4b18-887f-4310a336c749
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1084133738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1084133738
Directory /workspace/3.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2919194955
Short name T1470
Test name
Test status
Simulation time 26274028 ps
CPU time 0.62 seconds
Started Apr 21 01:03:27 PM PDT 24
Finished Apr 21 01:03:28 PM PDT 24
Peak memory 202932 kb
Host smart-14917e39-2249-4f6f-9a03-db2065019810
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2919194955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.2919194955
Directory /workspace/30.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.777272426
Short name T254
Test name
Test status
Simulation time 34089785 ps
CPU time 0.65 seconds
Started Apr 21 01:03:03 PM PDT 24
Finished Apr 21 01:03:04 PM PDT 24
Peak memory 202988 kb
Host smart-c0deb831-326d-40e9-8ccd-bd8056605e29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=777272426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.777272426
Directory /workspace/31.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3057820860
Short name T71
Test name
Test status
Simulation time 33294037 ps
CPU time 0.67 seconds
Started Apr 21 01:03:15 PM PDT 24
Finished Apr 21 01:03:16 PM PDT 24
Peak memory 202960 kb
Host smart-3c48c8b2-5d9f-4ea1-9358-becdf7ed0fd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3057820860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3057820860
Directory /workspace/32.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3389928195
Short name T1413
Test name
Test status
Simulation time 34655007 ps
CPU time 0.65 seconds
Started Apr 21 01:03:04 PM PDT 24
Finished Apr 21 01:03:05 PM PDT 24
Peak memory 202924 kb
Host smart-cb4fc203-9563-4060-9064-b6583b2a4236
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3389928195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3389928195
Directory /workspace/33.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.756955031
Short name T1476
Test name
Test status
Simulation time 40069972 ps
CPU time 0.66 seconds
Started Apr 21 01:03:19 PM PDT 24
Finished Apr 21 01:03:36 PM PDT 24
Peak memory 202972 kb
Host smart-a83cb5fa-4ff6-4504-867f-6e6f2cf9e1b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=756955031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.756955031
Directory /workspace/34.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3351644271
Short name T265
Test name
Test status
Simulation time 37251235 ps
CPU time 0.64 seconds
Started Apr 21 01:03:23 PM PDT 24
Finished Apr 21 01:03:24 PM PDT 24
Peak memory 202896 kb
Host smart-1adb7ce9-7d79-4de6-8a71-55c185ddf519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3351644271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3351644271
Directory /workspace/35.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3772956415
Short name T260
Test name
Test status
Simulation time 68507879 ps
CPU time 0.69 seconds
Started Apr 21 01:03:23 PM PDT 24
Finished Apr 21 01:03:24 PM PDT 24
Peak memory 202972 kb
Host smart-c1a1f170-eb96-4b59-aa15-063f093723f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3772956415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3772956415
Directory /workspace/36.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3789455279
Short name T1446
Test name
Test status
Simulation time 50534838 ps
CPU time 0.76 seconds
Started Apr 21 01:03:12 PM PDT 24
Finished Apr 21 01:03:14 PM PDT 24
Peak memory 202992 kb
Host smart-8e4702f7-e7b8-4263-a7ca-f680064ff96b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3789455279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3789455279
Directory /workspace/37.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.4089704722
Short name T1452
Test name
Test status
Simulation time 31663729 ps
CPU time 0.65 seconds
Started Apr 21 01:03:24 PM PDT 24
Finished Apr 21 01:03:25 PM PDT 24
Peak memory 202912 kb
Host smart-910d709c-be34-478b-9bca-fd3f8214e04a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4089704722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.4089704722
Directory /workspace/38.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2549667884
Short name T1434
Test name
Test status
Simulation time 22383103 ps
CPU time 0.63 seconds
Started Apr 21 01:03:24 PM PDT 24
Finished Apr 21 01:03:25 PM PDT 24
Peak memory 202804 kb
Host smart-4306851d-4358-4949-94e0-89af57182bcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2549667884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2549667884
Directory /workspace/39.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2161993809
Short name T1442
Test name
Test status
Simulation time 122791781 ps
CPU time 3.26 seconds
Started Apr 21 01:02:56 PM PDT 24
Finished Apr 21 01:02:59 PM PDT 24
Peak memory 203708 kb
Host smart-676593bb-591c-4bbe-9948-c0750bc80847
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2161993809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2161993809
Directory /workspace/4.usbdev_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1751437113
Short name T101
Test name
Test status
Simulation time 250924533 ps
CPU time 4.01 seconds
Started Apr 21 01:02:53 PM PDT 24
Finished Apr 21 01:02:58 PM PDT 24
Peak memory 203644 kb
Host smart-682c7764-73e7-448c-a186-1aa9a4bc835b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1751437113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1751437113
Directory /workspace/4.usbdev_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.635799350
Short name T72
Test name
Test status
Simulation time 76156856 ps
CPU time 0.78 seconds
Started Apr 21 01:02:58 PM PDT 24
Finished Apr 21 01:02:59 PM PDT 24
Peak memory 203400 kb
Host smart-61c5ee27-cf0b-4591-b922-e0070670810d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=635799350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.635799350
Directory /workspace/4.usbdev_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3801263098
Short name T1393
Test name
Test status
Simulation time 122441501 ps
CPU time 2.62 seconds
Started Apr 21 01:02:57 PM PDT 24
Finished Apr 21 01:03:00 PM PDT 24
Peak memory 211984 kb
Host smart-4279d8db-80c4-4a7e-bc9f-b7702d0c5c81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801263098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.3801263098
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.405658943
Short name T1395
Test name
Test status
Simulation time 48555510 ps
CPU time 0.96 seconds
Started Apr 21 01:02:59 PM PDT 24
Finished Apr 21 01:03:01 PM PDT 24
Peak memory 203652 kb
Host smart-2fae0ba9-2881-4fb8-86f6-1dc4af83f0f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=405658943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.405658943
Directory /workspace/4.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3125493989
Short name T1426
Test name
Test status
Simulation time 42618116 ps
CPU time 0.63 seconds
Started Apr 21 01:03:07 PM PDT 24
Finished Apr 21 01:03:08 PM PDT 24
Peak memory 202900 kb
Host smart-8d771625-7d1e-44ad-b933-f1dfd89de1ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3125493989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3125493989
Directory /workspace/4.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2766598750
Short name T234
Test name
Test status
Simulation time 187374020 ps
CPU time 2.34 seconds
Started Apr 21 01:02:58 PM PDT 24
Finished Apr 21 01:03:01 PM PDT 24
Peak memory 211976 kb
Host smart-2d81e268-5fda-4e15-b0c5-68ff5a78e2b4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2766598750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2766598750
Directory /workspace/4.usbdev_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.416283541
Short name T1407
Test name
Test status
Simulation time 387013379 ps
CPU time 2.79 seconds
Started Apr 21 01:03:00 PM PDT 24
Finished Apr 21 01:03:03 PM PDT 24
Peak memory 203640 kb
Host smart-90f1e182-643d-46f2-a6f4-95e4c879997b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=416283541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.416283541
Directory /workspace/4.usbdev_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1578763291
Short name T1430
Test name
Test status
Simulation time 61867084 ps
CPU time 1.12 seconds
Started Apr 21 01:02:59 PM PDT 24
Finished Apr 21 01:03:01 PM PDT 24
Peak memory 203736 kb
Host smart-fca567d3-d987-414d-85aa-9e022fa975bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1578763291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.1578763291
Directory /workspace/4.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1443341896
Short name T213
Test name
Test status
Simulation time 97342998 ps
CPU time 2.02 seconds
Started Apr 21 01:02:54 PM PDT 24
Finished Apr 21 01:02:56 PM PDT 24
Peak memory 203688 kb
Host smart-6d586462-c7b7-49ca-bb80-ebc9e5b6cc2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1443341896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.1443341896
Directory /workspace/4.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2509786349
Short name T271
Test name
Test status
Simulation time 303414904 ps
CPU time 2.7 seconds
Started Apr 21 01:02:52 PM PDT 24
Finished Apr 21 01:02:55 PM PDT 24
Peak memory 203776 kb
Host smart-131d83bb-b111-4717-ab4d-fac9aec20c3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2509786349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2509786349
Directory /workspace/4.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1920077862
Short name T252
Test name
Test status
Simulation time 46882188 ps
CPU time 0.72 seconds
Started Apr 21 01:03:13 PM PDT 24
Finished Apr 21 01:03:14 PM PDT 24
Peak memory 202960 kb
Host smart-a601802c-533d-492d-96b9-e040fd2ec1d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1920077862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.1920077862
Directory /workspace/40.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3638582860
Short name T1440
Test name
Test status
Simulation time 38046594 ps
CPU time 0.67 seconds
Started Apr 21 01:03:12 PM PDT 24
Finished Apr 21 01:03:13 PM PDT 24
Peak memory 202916 kb
Host smart-d0f73a1d-a33b-4b02-90c8-4315535ce2ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3638582860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.3638582860
Directory /workspace/41.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.4027881146
Short name T1448
Test name
Test status
Simulation time 22655890 ps
CPU time 0.71 seconds
Started Apr 21 01:03:07 PM PDT 24
Finished Apr 21 01:03:08 PM PDT 24
Peak memory 202928 kb
Host smart-8e996fab-6796-4398-adaa-e44ec4608d1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4027881146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.4027881146
Directory /workspace/42.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1894591953
Short name T1473
Test name
Test status
Simulation time 26679251 ps
CPU time 0.72 seconds
Started Apr 21 01:03:13 PM PDT 24
Finished Apr 21 01:03:14 PM PDT 24
Peak memory 202996 kb
Host smart-3af60c78-ac77-4ba4-a2fc-02efc3d76925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1894591953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.1894591953
Directory /workspace/43.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.506640411
Short name T73
Test name
Test status
Simulation time 40291371 ps
CPU time 0.68 seconds
Started Apr 21 01:03:15 PM PDT 24
Finished Apr 21 01:03:16 PM PDT 24
Peak memory 202964 kb
Host smart-0b4a039c-f29b-4850-ae08-e1d93734a2b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=506640411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.506640411
Directory /workspace/44.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.509289723
Short name T1419
Test name
Test status
Simulation time 48582815 ps
CPU time 0.67 seconds
Started Apr 21 01:03:15 PM PDT 24
Finished Apr 21 01:03:16 PM PDT 24
Peak memory 202940 kb
Host smart-4a41b2de-593e-4998-819b-a0c63d96a898
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=509289723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.509289723
Directory /workspace/45.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3272736870
Short name T259
Test name
Test status
Simulation time 31641415 ps
CPU time 0.64 seconds
Started Apr 21 01:03:10 PM PDT 24
Finished Apr 21 01:03:11 PM PDT 24
Peak memory 203056 kb
Host smart-c205bb8e-171d-48d9-a40c-31d361bb1abd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3272736870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.3272736870
Directory /workspace/46.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.680292558
Short name T69
Test name
Test status
Simulation time 23960137 ps
CPU time 0.63 seconds
Started Apr 21 01:03:26 PM PDT 24
Finished Apr 21 01:03:27 PM PDT 24
Peak memory 202912 kb
Host smart-eae14c79-1453-4639-9c5e-a1951a912769
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=680292558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.680292558
Directory /workspace/47.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1755719100
Short name T1462
Test name
Test status
Simulation time 70055755 ps
CPU time 0.72 seconds
Started Apr 21 01:03:18 PM PDT 24
Finished Apr 21 01:03:19 PM PDT 24
Peak memory 202988 kb
Host smart-3b30c0d4-199d-4657-b4b0-30d85fc4f210
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1755719100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.1755719100
Directory /workspace/48.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2491123627
Short name T212
Test name
Test status
Simulation time 144335611 ps
CPU time 1.83 seconds
Started Apr 21 01:03:09 PM PDT 24
Finished Apr 21 01:03:11 PM PDT 24
Peak memory 215336 kb
Host smart-845e8933-4399-4bfd-8163-03f68f159255
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491123627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.2491123627
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3750853134
Short name T1477
Test name
Test status
Simulation time 82286281 ps
CPU time 0.82 seconds
Started Apr 21 01:02:55 PM PDT 24
Finished Apr 21 01:02:56 PM PDT 24
Peak memory 203440 kb
Host smart-7b810be7-1af4-4df7-b936-9de15226940b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3750853134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3750853134
Directory /workspace/5.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2357676074
Short name T1396
Test name
Test status
Simulation time 35320378 ps
CPU time 0.63 seconds
Started Apr 21 01:02:59 PM PDT 24
Finished Apr 21 01:03:00 PM PDT 24
Peak memory 203024 kb
Host smart-4b72a772-04dd-43a9-8d74-b8a4b05ce8b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2357676074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2357676074
Directory /workspace/5.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2983351690
Short name T1391
Test name
Test status
Simulation time 47049960 ps
CPU time 1.02 seconds
Started Apr 21 01:02:56 PM PDT 24
Finished Apr 21 01:02:57 PM PDT 24
Peak memory 203748 kb
Host smart-c240abd8-dfd0-4012-a77d-74d062014517
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2983351690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.2983351690
Directory /workspace/5.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1359659727
Short name T1406
Test name
Test status
Simulation time 110676810 ps
CPU time 2.65 seconds
Started Apr 21 01:02:59 PM PDT 24
Finished Apr 21 01:03:02 PM PDT 24
Peak memory 203788 kb
Host smart-3ca436a2-6fa5-4b9e-ac16-a0f1dc68f65c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1359659727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1359659727
Directory /workspace/5.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1303422561
Short name T270
Test name
Test status
Simulation time 294319029 ps
CPU time 2.78 seconds
Started Apr 21 01:03:04 PM PDT 24
Finished Apr 21 01:03:07 PM PDT 24
Peak memory 203672 kb
Host smart-b6357c76-3e9d-4fb6-959f-119e30a8141e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1303422561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1303422561
Directory /workspace/5.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3958956657
Short name T1425
Test name
Test status
Simulation time 70138173 ps
CPU time 1.89 seconds
Started Apr 21 01:02:57 PM PDT 24
Finished Apr 21 01:03:00 PM PDT 24
Peak memory 215336 kb
Host smart-e42b1315-2b0d-4fb5-a20d-85992b5ed75c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958956657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.3958956657
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2838811686
Short name T1472
Test name
Test status
Simulation time 37238741 ps
CPU time 0.76 seconds
Started Apr 21 01:02:53 PM PDT 24
Finished Apr 21 01:02:54 PM PDT 24
Peak memory 203444 kb
Host smart-77449c3d-ffea-4802-968d-dc9433ed6202
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2838811686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2838811686
Directory /workspace/6.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2131546016
Short name T1418
Test name
Test status
Simulation time 86349558 ps
CPU time 0.78 seconds
Started Apr 21 01:02:57 PM PDT 24
Finished Apr 21 01:02:58 PM PDT 24
Peak memory 202980 kb
Host smart-e454806b-a575-4c84-8ba7-c75e389430a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2131546016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2131546016
Directory /workspace/6.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.466043380
Short name T1412
Test name
Test status
Simulation time 70411426 ps
CPU time 1.13 seconds
Started Apr 21 01:02:55 PM PDT 24
Finished Apr 21 01:02:57 PM PDT 24
Peak memory 203776 kb
Host smart-6fcae62f-580e-4b0e-9b66-f44f94986a98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=466043380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.466043380
Directory /workspace/6.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.132477330
Short name T214
Test name
Test status
Simulation time 75418579 ps
CPU time 1.17 seconds
Started Apr 21 01:02:57 PM PDT 24
Finished Apr 21 01:02:59 PM PDT 24
Peak memory 203740 kb
Host smart-5b479f1d-4ffe-4d59-9de5-437ebe72f86f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=132477330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.132477330
Directory /workspace/6.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1339130839
Short name T267
Test name
Test status
Simulation time 405307928 ps
CPU time 2.71 seconds
Started Apr 21 01:03:05 PM PDT 24
Finished Apr 21 01:03:08 PM PDT 24
Peak memory 203624 kb
Host smart-c9c29cec-0773-425e-856f-b2f00abbebbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1339130839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.1339130839
Directory /workspace/6.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2022202787
Short name T1474
Test name
Test status
Simulation time 92623855 ps
CPU time 1.36 seconds
Started Apr 21 01:03:01 PM PDT 24
Finished Apr 21 01:03:03 PM PDT 24
Peak memory 211992 kb
Host smart-131f69dd-a4c6-46ce-a4e9-62ab3b67f3b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022202787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.2022202787
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1229269753
Short name T1480
Test name
Test status
Simulation time 82825959 ps
CPU time 1.02 seconds
Started Apr 21 01:03:01 PM PDT 24
Finished Apr 21 01:03:03 PM PDT 24
Peak memory 203728 kb
Host smart-2a04f2cf-eba1-4812-bc78-fc04461b9734
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1229269753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1229269753
Directory /workspace/7.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1141772549
Short name T1441
Test name
Test status
Simulation time 84328853 ps
CPU time 0.73 seconds
Started Apr 21 01:02:59 PM PDT 24
Finished Apr 21 01:03:04 PM PDT 24
Peak memory 202976 kb
Host smart-9885d5c2-1b2a-4f2f-acbf-7100735ae06e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1141772549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1141772549
Directory /workspace/7.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1254326840
Short name T1421
Test name
Test status
Simulation time 145909708 ps
CPU time 1.38 seconds
Started Apr 21 01:02:54 PM PDT 24
Finished Apr 21 01:02:55 PM PDT 24
Peak memory 203712 kb
Host smart-48c84606-7ab6-4102-a396-2f481c1fe314
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1254326840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1254326840
Directory /workspace/7.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.103108772
Short name T1415
Test name
Test status
Simulation time 248388894 ps
CPU time 2.74 seconds
Started Apr 21 01:02:58 PM PDT 24
Finished Apr 21 01:03:01 PM PDT 24
Peak memory 203736 kb
Host smart-d055a2ce-a244-4e1b-99d6-f9bb3f53e9b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=103108772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.103108772
Directory /workspace/7.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1662671540
Short name T273
Test name
Test status
Simulation time 530074569 ps
CPU time 4.85 seconds
Started Apr 21 01:02:56 PM PDT 24
Finished Apr 21 01:03:01 PM PDT 24
Peak memory 203792 kb
Host smart-dd2ae19d-4142-4c8e-aa7f-f179ec8da529
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1662671540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1662671540
Directory /workspace/7.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2539619211
Short name T98
Test name
Test status
Simulation time 49849793 ps
CPU time 1.4 seconds
Started Apr 21 01:02:59 PM PDT 24
Finished Apr 21 01:03:00 PM PDT 24
Peak memory 212060 kb
Host smart-924d6123-d0d3-49f6-8417-f0a2407f2226
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539619211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2539619211
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1136423112
Short name T1405
Test name
Test status
Simulation time 55401349 ps
CPU time 0.94 seconds
Started Apr 21 01:03:02 PM PDT 24
Finished Apr 21 01:03:03 PM PDT 24
Peak memory 203540 kb
Host smart-ce7f0f2e-627c-45ad-a8a2-cbf65e9dbf0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1136423112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1136423112
Directory /workspace/8.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2548578530
Short name T263
Test name
Test status
Simulation time 29519539 ps
CPU time 0.62 seconds
Started Apr 21 01:02:58 PM PDT 24
Finished Apr 21 01:02:59 PM PDT 24
Peak memory 202896 kb
Host smart-54bc5e55-c3d8-448c-be9f-18b09f1fff5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2548578530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2548578530
Directory /workspace/8.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1900229709
Short name T1387
Test name
Test status
Simulation time 65668216 ps
CPU time 1.45 seconds
Started Apr 21 01:03:04 PM PDT 24
Finished Apr 21 01:03:06 PM PDT 24
Peak memory 203740 kb
Host smart-2d9c605f-6ff6-4f34-ac5a-e0025e26b5b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1900229709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.1900229709
Directory /workspace/8.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2281795913
Short name T1401
Test name
Test status
Simulation time 62031071 ps
CPU time 1.55 seconds
Started Apr 21 01:02:57 PM PDT 24
Finished Apr 21 01:02:59 PM PDT 24
Peak memory 203788 kb
Host smart-6cf6a170-465a-4114-b59f-eab9d1649d01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2281795913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2281795913
Directory /workspace/8.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.207162449
Short name T1454
Test name
Test status
Simulation time 355801648 ps
CPU time 2.81 seconds
Started Apr 21 01:02:56 PM PDT 24
Finished Apr 21 01:02:59 PM PDT 24
Peak memory 203812 kb
Host smart-ef5338e7-b684-4fa8-95bb-788358652a4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=207162449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.207162449
Directory /workspace/8.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1676172160
Short name T218
Test name
Test status
Simulation time 101479694 ps
CPU time 1.28 seconds
Started Apr 21 01:03:17 PM PDT 24
Finished Apr 21 01:03:24 PM PDT 24
Peak memory 212044 kb
Host smart-af0f2cce-3406-47e9-9df7-9041a10afe36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676172160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.1676172160
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2146088864
Short name T239
Test name
Test status
Simulation time 61574093 ps
CPU time 0.85 seconds
Started Apr 21 01:03:01 PM PDT 24
Finished Apr 21 01:03:03 PM PDT 24
Peak memory 203400 kb
Host smart-c7b73e11-7214-480f-976f-83dbec6932e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2146088864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2146088864
Directory /workspace/9.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1289330802
Short name T1444
Test name
Test status
Simulation time 61441018 ps
CPU time 0.77 seconds
Started Apr 21 01:02:54 PM PDT 24
Finished Apr 21 01:02:55 PM PDT 24
Peak memory 202984 kb
Host smart-aa641303-5f48-493e-b746-6b8ed75afb76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1289330802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1289330802
Directory /workspace/9.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3838765808
Short name T1410
Test name
Test status
Simulation time 100120325 ps
CPU time 1.55 seconds
Started Apr 21 01:03:11 PM PDT 24
Finished Apr 21 01:03:13 PM PDT 24
Peak memory 203728 kb
Host smart-bed10c58-63a3-43ff-8124-09aa4b6b51ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3838765808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3838765808
Directory /workspace/9.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1876110163
Short name T1399
Test name
Test status
Simulation time 109002011 ps
CPU time 2.83 seconds
Started Apr 21 01:02:53 PM PDT 24
Finished Apr 21 01:02:56 PM PDT 24
Peak memory 203792 kb
Host smart-6ed9d48a-7d3b-4fc3-9c86-3234ed00e107
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1876110163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.1876110163
Directory /workspace/9.usbdev_tl_errors/latest


Test location /workspace/coverage/default/0.max_length_in_transaction.1926190891
Short name T461
Test name
Test status
Simulation time 8468930476 ps
CPU time 7.92 seconds
Started Apr 21 03:56:44 PM PDT 24
Finished Apr 21 03:56:52 PM PDT 24
Peak memory 204064 kb
Host smart-09a00f77-8ab4-486f-90ec-7c41f8d5a42d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1926190891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.1926190891
Directory /workspace/0.max_length_in_transaction/latest


Test location /workspace/coverage/default/0.min_length_in_transaction.1206325385
Short name T894
Test name
Test status
Simulation time 8446545512 ps
CPU time 7.7 seconds
Started Apr 21 03:56:44 PM PDT 24
Finished Apr 21 03:56:52 PM PDT 24
Peak memory 204044 kb
Host smart-a55e66b3-2cb6-4c7d-bf8a-20c50ad375d7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1206325385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.1206325385
Directory /workspace/0.min_length_in_transaction/latest


Test location /workspace/coverage/default/0.random_length_in_trans.217450055
Short name T785
Test name
Test status
Simulation time 8471871633 ps
CPU time 8.14 seconds
Started Apr 21 03:56:43 PM PDT 24
Finished Apr 21 03:56:52 PM PDT 24
Peak memory 204040 kb
Host smart-33db3158-b033-4729-bd4f-e176b3346297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21745
0055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.217450055
Directory /workspace/0.random_length_in_trans/latest


Test location /workspace/coverage/default/0.usbdev_av_buffer.4005989091
Short name T1364
Test name
Test status
Simulation time 8379162634 ps
CPU time 7.57 seconds
Started Apr 21 03:56:20 PM PDT 24
Finished Apr 21 03:56:27 PM PDT 24
Peak memory 204068 kb
Host smart-18de4cb9-b755-4d0e-b3a7-377654395abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40059
89091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.4005989091
Directory /workspace/0.usbdev_av_buffer/latest


Test location /workspace/coverage/default/0.usbdev_fifo_rst.1604285050
Short name T1276
Test name
Test status
Simulation time 89746715 ps
CPU time 1.12 seconds
Started Apr 21 03:56:26 PM PDT 24
Finished Apr 21 03:56:27 PM PDT 24
Peak memory 204136 kb
Host smart-85a9a99c-f3d9-4a69-98f4-4d1acc82d8be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16042
85050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.1604285050
Directory /workspace/0.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/0.usbdev_in_iso.4230159790
Short name T1198
Test name
Test status
Simulation time 8392294945 ps
CPU time 7.73 seconds
Started Apr 21 03:56:36 PM PDT 24
Finished Apr 21 03:56:44 PM PDT 24
Peak memory 204064 kb
Host smart-37ae94ce-8809-4b8e-8bd5-d17e65da65bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42301
59790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.4230159790
Directory /workspace/0.usbdev_in_iso/latest


Test location /workspace/coverage/default/0.usbdev_in_stall.2429634540
Short name T194
Test name
Test status
Simulation time 8378928694 ps
CPU time 8 seconds
Started Apr 21 03:56:36 PM PDT 24
Finished Apr 21 03:56:44 PM PDT 24
Peak memory 204036 kb
Host smart-f8b57574-c231-4af5-a8e5-11bd38f5d0bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24296
34540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2429634540
Directory /workspace/0.usbdev_in_stall/latest


Test location /workspace/coverage/default/0.usbdev_in_trans.1332021224
Short name T631
Test name
Test status
Simulation time 8418034063 ps
CPU time 9.91 seconds
Started Apr 21 03:56:24 PM PDT 24
Finished Apr 21 03:56:34 PM PDT 24
Peak memory 204088 kb
Host smart-6a88364e-d8b2-441e-9565-e9a61b0cd55f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13320
21224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.1332021224
Directory /workspace/0.usbdev_in_trans/latest


Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.3076522869
Short name T28
Test name
Test status
Simulation time 8430397482 ps
CPU time 9.16 seconds
Started Apr 21 03:56:24 PM PDT 24
Finished Apr 21 03:56:34 PM PDT 24
Peak memory 204044 kb
Host smart-c21b03e7-9d5b-40cb-9831-d298a7ccc307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30765
22869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.3076522869
Directory /workspace/0.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2376423723
Short name T510
Test name
Test status
Simulation time 8434814112 ps
CPU time 8.56 seconds
Started Apr 21 03:56:24 PM PDT 24
Finished Apr 21 03:56:33 PM PDT 24
Peak memory 203948 kb
Host smart-68076b71-1acb-40b9-8d8c-5e397ba6f724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23764
23723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2376423723
Directory /workspace/0.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/0.usbdev_out_stall.859867324
Short name T1042
Test name
Test status
Simulation time 8418640241 ps
CPU time 9.4 seconds
Started Apr 21 03:56:28 PM PDT 24
Finished Apr 21 03:56:37 PM PDT 24
Peak memory 204044 kb
Host smart-e0b097bf-8119-47e3-83a9-30a75ce48ed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85986
7324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.859867324
Directory /workspace/0.usbdev_out_stall/latest


Test location /workspace/coverage/default/0.usbdev_out_trans_nak.1981760557
Short name T457
Test name
Test status
Simulation time 8397838345 ps
CPU time 8.1 seconds
Started Apr 21 03:56:28 PM PDT 24
Finished Apr 21 03:56:36 PM PDT 24
Peak memory 204060 kb
Host smart-e1f5cdef-a496-4e84-a1ab-fc30ff21d65a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19817
60557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.1981760557
Directory /workspace/0.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.592966835
Short name T715
Test name
Test status
Simulation time 8380502376 ps
CPU time 7.66 seconds
Started Apr 21 03:56:34 PM PDT 24
Finished Apr 21 03:56:42 PM PDT 24
Peak memory 203452 kb
Host smart-4d5f034a-31f8-4863-ae87-ed81866a4ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59296
6835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.592966835
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/0.usbdev_pkt_buffer.1138810268
Short name T521
Test name
Test status
Simulation time 27608309872 ps
CPU time 57.06 seconds
Started Apr 21 03:56:29 PM PDT 24
Finished Apr 21 03:57:26 PM PDT 24
Peak memory 204352 kb
Host smart-8f47eefb-c4cb-4440-ac4d-3a26f5e92b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11388
10268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.1138810268
Directory /workspace/0.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/0.usbdev_pkt_received.4018792930
Short name T1025
Test name
Test status
Simulation time 8502285331 ps
CPU time 9.83 seconds
Started Apr 21 03:56:33 PM PDT 24
Finished Apr 21 03:56:43 PM PDT 24
Peak memory 204060 kb
Host smart-274c6f3b-9f12-4b38-85af-dbb048330895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40187
92930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.4018792930
Directory /workspace/0.usbdev_pkt_received/latest


Test location /workspace/coverage/default/0.usbdev_pkt_sent.3178544170
Short name T950
Test name
Test status
Simulation time 8383161590 ps
CPU time 8.79 seconds
Started Apr 21 03:56:35 PM PDT 24
Finished Apr 21 03:56:44 PM PDT 24
Peak memory 204040 kb
Host smart-3ce0922b-6f14-4e92-9b79-49a913c6d437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31785
44170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.3178544170
Directory /workspace/0.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.2421575225
Short name T469
Test name
Test status
Simulation time 8399813046 ps
CPU time 8.52 seconds
Started Apr 21 03:56:35 PM PDT 24
Finished Apr 21 03:56:44 PM PDT 24
Peak memory 204036 kb
Host smart-176b09db-7527-4144-9cb4-8044827a52b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24215
75225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.2421575225
Directory /workspace/0.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/0.usbdev_setup_stage.2348161248
Short name T336
Test name
Test status
Simulation time 8376009629 ps
CPU time 9.37 seconds
Started Apr 21 03:56:35 PM PDT 24
Finished Apr 21 03:56:45 PM PDT 24
Peak memory 204036 kb
Host smart-613b0550-a9e0-4555-81a8-563dd1e31d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23481
61248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2348161248
Directory /workspace/0.usbdev_setup_stage/latest


Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.2166033770
Short name T1226
Test name
Test status
Simulation time 8367561881 ps
CPU time 8.52 seconds
Started Apr 21 03:56:30 PM PDT 24
Finished Apr 21 03:56:39 PM PDT 24
Peak memory 204060 kb
Host smart-af7a4f06-c0dd-467a-8d71-a190f7064d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21660
33770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.2166033770
Directory /workspace/0.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/0.usbdev_smoke.3118358804
Short name T1348
Test name
Test status
Simulation time 8435286921 ps
CPU time 9.33 seconds
Started Apr 21 03:56:18 PM PDT 24
Finished Apr 21 03:56:28 PM PDT 24
Peak memory 204064 kb
Host smart-01d20492-6725-4f92-9399-ac69638188ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31183
58804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3118358804
Directory /workspace/0.usbdev_smoke/latest


Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.2351746959
Short name T985
Test name
Test status
Simulation time 8422515117 ps
CPU time 8.1 seconds
Started Apr 21 03:56:34 PM PDT 24
Finished Apr 21 03:56:43 PM PDT 24
Peak memory 203452 kb
Host smart-4fbac8bb-2bd8-4c8a-af4d-b7cf8951b194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23517
46959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.2351746959
Directory /workspace/0.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/1.max_length_in_transaction.929551122
Short name T481
Test name
Test status
Simulation time 8469781219 ps
CPU time 7.87 seconds
Started Apr 21 03:57:09 PM PDT 24
Finished Apr 21 03:57:17 PM PDT 24
Peak memory 204064 kb
Host smart-84d2f83b-556c-478f-9f54-4cc00a090e6f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=929551122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.929551122
Directory /workspace/1.max_length_in_transaction/latest


Test location /workspace/coverage/default/1.min_length_in_transaction.771410339
Short name T995
Test name
Test status
Simulation time 8401901444 ps
CPU time 7.74 seconds
Started Apr 21 03:57:07 PM PDT 24
Finished Apr 21 03:57:15 PM PDT 24
Peak memory 203932 kb
Host smart-a116d6a7-d446-4475-a95e-cb563801b688
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=771410339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.771410339
Directory /workspace/1.min_length_in_transaction/latest


Test location /workspace/coverage/default/1.random_length_in_trans.1960775417
Short name T947
Test name
Test status
Simulation time 8434752728 ps
CPU time 8.88 seconds
Started Apr 21 03:57:11 PM PDT 24
Finished Apr 21 03:57:20 PM PDT 24
Peak memory 204028 kb
Host smart-7d46a993-216c-4f90-ae24-ee0fbb60e0df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19607
75417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.1960775417
Directory /workspace/1.random_length_in_trans/latest


Test location /workspace/coverage/default/1.usbdev_av_buffer.3818170786
Short name T728
Test name
Test status
Simulation time 8377292087 ps
CPU time 7.66 seconds
Started Apr 21 03:56:50 PM PDT 24
Finished Apr 21 03:56:57 PM PDT 24
Peak memory 204048 kb
Host smart-31951d61-e6dc-4118-8f8a-792c841fbf4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38181
70786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.3818170786
Directory /workspace/1.usbdev_av_buffer/latest


Test location /workspace/coverage/default/1.usbdev_enable.3650066102
Short name T1235
Test name
Test status
Simulation time 8403276125 ps
CPU time 8.14 seconds
Started Apr 21 03:56:49 PM PDT 24
Finished Apr 21 03:56:57 PM PDT 24
Peak memory 204036 kb
Host smart-55f9f348-1dab-4be4-9e6b-5ec6b1c56d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36500
66102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3650066102
Directory /workspace/1.usbdev_enable/latest


Test location /workspace/coverage/default/1.usbdev_fifo_rst.2356029630
Short name T56
Test name
Test status
Simulation time 170098958 ps
CPU time 1.6 seconds
Started Apr 21 03:56:56 PM PDT 24
Finished Apr 21 03:56:58 PM PDT 24
Peak memory 204136 kb
Host smart-a1d5838c-97d6-4d84-abaa-12d2c2e241af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23560
29630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.2356029630
Directory /workspace/1.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/1.usbdev_in_iso.2196198721
Short name T1267
Test name
Test status
Simulation time 8413674420 ps
CPU time 7.62 seconds
Started Apr 21 03:57:06 PM PDT 24
Finished Apr 21 03:57:14 PM PDT 24
Peak memory 204040 kb
Host smart-cde90062-5bf6-4fe9-9efb-b122c61c9f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21961
98721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2196198721
Directory /workspace/1.usbdev_in_iso/latest


Test location /workspace/coverage/default/1.usbdev_in_stall.2619459282
Short name T187
Test name
Test status
Simulation time 8370099437 ps
CPU time 7.77 seconds
Started Apr 21 03:57:05 PM PDT 24
Finished Apr 21 03:57:13 PM PDT 24
Peak memory 204052 kb
Host smart-f220ac14-7cc6-44cf-a787-4e6ecb6e7d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26194
59282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.2619459282
Directory /workspace/1.usbdev_in_stall/latest


Test location /workspace/coverage/default/1.usbdev_in_trans.1435355269
Short name T871
Test name
Test status
Simulation time 8454932008 ps
CPU time 8.97 seconds
Started Apr 21 03:56:56 PM PDT 24
Finished Apr 21 03:57:05 PM PDT 24
Peak memory 204036 kb
Host smart-d2f721de-eb4e-4f3c-9342-791f5f14aa6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14353
55269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.1435355269
Directory /workspace/1.usbdev_in_trans/latest


Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2990059299
Short name T572
Test name
Test status
Simulation time 8449571251 ps
CPU time 9.03 seconds
Started Apr 21 03:56:56 PM PDT 24
Finished Apr 21 03:57:06 PM PDT 24
Peak memory 204048 kb
Host smart-9a957c54-eaa2-4c3c-8e77-f49f651eac0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29900
59299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2990059299
Directory /workspace/1.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.2533257585
Short name T578
Test name
Test status
Simulation time 8369060851 ps
CPU time 8.35 seconds
Started Apr 21 03:56:52 PM PDT 24
Finished Apr 21 03:57:00 PM PDT 24
Peak memory 204052 kb
Host smart-cf5f53ba-6f67-40d8-bd14-9efc8962ebe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25332
57585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.2533257585
Directory /workspace/1.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/1.usbdev_out_stall.3868591431
Short name T1326
Test name
Test status
Simulation time 8420381844 ps
CPU time 9.11 seconds
Started Apr 21 03:56:57 PM PDT 24
Finished Apr 21 03:57:06 PM PDT 24
Peak memory 204076 kb
Host smart-5cb6debf-4c94-4784-ae2a-bc0f4f44e642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38685
91431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3868591431
Directory /workspace/1.usbdev_out_stall/latest


Test location /workspace/coverage/default/1.usbdev_out_trans_nak.1871848999
Short name T901
Test name
Test status
Simulation time 8457418009 ps
CPU time 9.26 seconds
Started Apr 21 03:56:58 PM PDT 24
Finished Apr 21 03:57:07 PM PDT 24
Peak memory 204024 kb
Host smart-7277f3e7-118f-4923-8f91-0dda14b5ae20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18718
48999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.1871848999
Directory /workspace/1.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.2448821595
Short name T490
Test name
Test status
Simulation time 8381506831 ps
CPU time 8.33 seconds
Started Apr 21 03:57:05 PM PDT 24
Finished Apr 21 03:57:13 PM PDT 24
Peak memory 204040 kb
Host smart-dc70e22e-61d9-454d-be6d-72c7a3308758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24488
21595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.2448821595
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/1.usbdev_pkt_buffer.1777265338
Short name T225
Test name
Test status
Simulation time 15050237079 ps
CPU time 29.86 seconds
Started Apr 21 03:56:56 PM PDT 24
Finished Apr 21 03:57:26 PM PDT 24
Peak memory 204248 kb
Host smart-857ffa2b-3b77-4368-a75f-3c977a52af0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17772
65338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.1777265338
Directory /workspace/1.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/1.usbdev_pkt_received.2025779978
Short name T1040
Test name
Test status
Simulation time 8404762773 ps
CPU time 8.3 seconds
Started Apr 21 03:56:59 PM PDT 24
Finished Apr 21 03:57:08 PM PDT 24
Peak memory 204052 kb
Host smart-e62c8f4d-9457-43ad-a26b-2dc95cdd6337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20257
79978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.2025779978
Directory /workspace/1.usbdev_pkt_received/latest


Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.2902147708
Short name T584
Test name
Test status
Simulation time 8393213824 ps
CPU time 8.14 seconds
Started Apr 21 03:57:03 PM PDT 24
Finished Apr 21 03:57:12 PM PDT 24
Peak memory 204084 kb
Host smart-d78c6270-571c-45b9-95d8-a3d7f89c2880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29021
47708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.2902147708
Directory /workspace/1.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/1.usbdev_sec_cm.3378871982
Short name T75
Test name
Test status
Simulation time 123549243 ps
CPU time 1 seconds
Started Apr 21 03:57:10 PM PDT 24
Finished Apr 21 03:57:11 PM PDT 24
Peak memory 220288 kb
Host smart-b3ee9ae0-6e4b-468c-99e9-80799677c04a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3378871982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.3378871982
Directory /workspace/1.usbdev_sec_cm/latest


Test location /workspace/coverage/default/1.usbdev_setup_stage.2743770440
Short name T896
Test name
Test status
Simulation time 8378707360 ps
CPU time 8.35 seconds
Started Apr 21 03:57:06 PM PDT 24
Finished Apr 21 03:57:14 PM PDT 24
Peak memory 204060 kb
Host smart-d19756fd-4401-4ded-811f-13593a691fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27437
70440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.2743770440
Directory /workspace/1.usbdev_setup_stage/latest


Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.1587146306
Short name T502
Test name
Test status
Simulation time 8370691117 ps
CPU time 9.61 seconds
Started Apr 21 03:57:04 PM PDT 24
Finished Apr 21 03:57:14 PM PDT 24
Peak memory 204084 kb
Host smart-43f23291-131a-43e0-a24b-3777e4f47deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15871
46306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.1587146306
Directory /workspace/1.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.391058416
Short name T797
Test name
Test status
Simulation time 8379216316 ps
CPU time 7.58 seconds
Started Apr 21 03:57:12 PM PDT 24
Finished Apr 21 03:57:20 PM PDT 24
Peak memory 204072 kb
Host smart-7493b37e-701c-4d3d-8085-eb547f573c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39105
8416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.391058416
Directory /workspace/1.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/1.usbdev_stall_trans.291031868
Short name T465
Test name
Test status
Simulation time 8414992156 ps
CPU time 9.93 seconds
Started Apr 21 03:57:01 PM PDT 24
Finished Apr 21 03:57:11 PM PDT 24
Peak memory 204064 kb
Host smart-c075d4e9-6bc3-4e15-ac3e-b1e9ac1bbb07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29103
1868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.291031868
Directory /workspace/1.usbdev_stall_trans/latest


Test location /workspace/coverage/default/10.max_length_in_transaction.3526193336
Short name T1251
Test name
Test status
Simulation time 8471582374 ps
CPU time 8.03 seconds
Started Apr 21 03:59:17 PM PDT 24
Finished Apr 21 03:59:25 PM PDT 24
Peak memory 204068 kb
Host smart-cb357d08-5a4b-4df0-b33b-028a5956506b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3526193336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.3526193336
Directory /workspace/10.max_length_in_transaction/latest


Test location /workspace/coverage/default/10.min_length_in_transaction.3246102367
Short name T1020
Test name
Test status
Simulation time 8380057423 ps
CPU time 7.77 seconds
Started Apr 21 03:59:17 PM PDT 24
Finished Apr 21 03:59:25 PM PDT 24
Peak memory 204052 kb
Host smart-09a1e534-6f8e-4a39-8eda-96522210e161
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3246102367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.3246102367
Directory /workspace/10.min_length_in_transaction/latest


Test location /workspace/coverage/default/10.random_length_in_trans.2798925344
Short name T419
Test name
Test status
Simulation time 8432928926 ps
CPU time 10.19 seconds
Started Apr 21 03:59:17 PM PDT 24
Finished Apr 21 03:59:27 PM PDT 24
Peak memory 204056 kb
Host smart-b1e95cc8-cac9-4601-b65a-bc79e8ac43e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27989
25344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.2798925344
Directory /workspace/10.random_length_in_trans/latest


Test location /workspace/coverage/default/10.usbdev_av_buffer.538035813
Short name T329
Test name
Test status
Simulation time 8439140680 ps
CPU time 8.52 seconds
Started Apr 21 03:59:12 PM PDT 24
Finished Apr 21 03:59:21 PM PDT 24
Peak memory 204036 kb
Host smart-b1c4216d-fd13-4de1-8bc5-414b7d9f89a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53803
5813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.538035813
Directory /workspace/10.usbdev_av_buffer/latest


Test location /workspace/coverage/default/10.usbdev_enable.3662244237
Short name T1084
Test name
Test status
Simulation time 8381514401 ps
CPU time 8.12 seconds
Started Apr 21 03:59:10 PM PDT 24
Finished Apr 21 03:59:18 PM PDT 24
Peak memory 204024 kb
Host smart-1c096eea-f138-4c50-a676-14a077126271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36622
44237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.3662244237
Directory /workspace/10.usbdev_enable/latest


Test location /workspace/coverage/default/10.usbdev_fifo_rst.2322730200
Short name T1285
Test name
Test status
Simulation time 119644636 ps
CPU time 1.52 seconds
Started Apr 21 03:59:09 PM PDT 24
Finished Apr 21 03:59:11 PM PDT 24
Peak memory 204196 kb
Host smart-b818454b-4a33-4cbd-ae8d-739f3e42b6f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23227
30200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.2322730200
Directory /workspace/10.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/10.usbdev_in_iso.987776690
Short name T745
Test name
Test status
Simulation time 8444380257 ps
CPU time 9.88 seconds
Started Apr 21 03:59:17 PM PDT 24
Finished Apr 21 03:59:28 PM PDT 24
Peak memory 204036 kb
Host smart-b327da63-0823-4e8a-b050-e66fd65e05e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98777
6690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.987776690
Directory /workspace/10.usbdev_in_iso/latest


Test location /workspace/coverage/default/10.usbdev_in_stall.4180159816
Short name T400
Test name
Test status
Simulation time 8368017199 ps
CPU time 8.85 seconds
Started Apr 21 03:59:21 PM PDT 24
Finished Apr 21 03:59:30 PM PDT 24
Peak memory 204060 kb
Host smart-3a476072-bc45-42b7-94d3-c68a095207ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41801
59816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.4180159816
Directory /workspace/10.usbdev_in_stall/latest


Test location /workspace/coverage/default/10.usbdev_in_trans.3302979369
Short name T1018
Test name
Test status
Simulation time 8410004794 ps
CPU time 8.01 seconds
Started Apr 21 03:59:11 PM PDT 24
Finished Apr 21 03:59:20 PM PDT 24
Peak memory 204040 kb
Host smart-14d9739f-ab97-4b21-93d4-9786972300ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33029
79369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3302979369
Directory /workspace/10.usbdev_in_trans/latest


Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.3535135603
Short name T719
Test name
Test status
Simulation time 8429355146 ps
CPU time 8.29 seconds
Started Apr 21 03:59:11 PM PDT 24
Finished Apr 21 03:59:20 PM PDT 24
Peak memory 204052 kb
Host smart-157b55a3-90fd-4198-96fe-48e25b92e856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35351
35603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.3535135603
Directory /workspace/10.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.1482795693
Short name T868
Test name
Test status
Simulation time 8370697771 ps
CPU time 7.51 seconds
Started Apr 21 03:59:09 PM PDT 24
Finished Apr 21 03:59:17 PM PDT 24
Peak memory 204084 kb
Host smart-58525607-ea94-4ed3-8a51-e7833cf0cc47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14827
95693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.1482795693
Directory /workspace/10.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/10.usbdev_out_stall.2485609920
Short name T1172
Test name
Test status
Simulation time 8407152341 ps
CPU time 8.26 seconds
Started Apr 21 03:59:12 PM PDT 24
Finished Apr 21 03:59:20 PM PDT 24
Peak memory 204040 kb
Host smart-54a2f687-8d46-4dfc-8676-e9aae6a57a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24856
09920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2485609920
Directory /workspace/10.usbdev_out_stall/latest


Test location /workspace/coverage/default/10.usbdev_out_trans_nak.3686632221
Short name T207
Test name
Test status
Simulation time 8383749695 ps
CPU time 7.65 seconds
Started Apr 21 03:59:12 PM PDT 24
Finished Apr 21 03:59:20 PM PDT 24
Peak memory 204044 kb
Host smart-406a8c59-dd9a-48ec-8c69-42347505eaf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36866
32221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.3686632221
Directory /workspace/10.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/10.usbdev_pending_in_trans.3402253807
Short name T1223
Test name
Test status
Simulation time 8403819227 ps
CPU time 9.31 seconds
Started Apr 21 03:59:18 PM PDT 24
Finished Apr 21 03:59:27 PM PDT 24
Peak memory 204040 kb
Host smart-2193fc4c-7dd8-4de3-a795-243f4746950e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34022
53807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.3402253807
Directory /workspace/10.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.1251578501
Short name T9
Test name
Test status
Simulation time 8367341794 ps
CPU time 7.88 seconds
Started Apr 21 03:59:14 PM PDT 24
Finished Apr 21 03:59:22 PM PDT 24
Peak memory 204020 kb
Host smart-22a9a782-d573-4ec8-8fbe-84d97c1dd1f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12515
78501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.1251578501
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.3163587966
Short name T1085
Test name
Test status
Simulation time 120878158 ps
CPU time 0.76 seconds
Started Apr 21 03:59:18 PM PDT 24
Finished Apr 21 03:59:19 PM PDT 24
Peak memory 203916 kb
Host smart-85bfeea8-3262-4463-bfe9-3f6752c54b9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31635
87966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.3163587966
Directory /workspace/10.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/10.usbdev_pkt_buffer.2297688937
Short name T1126
Test name
Test status
Simulation time 23509828907 ps
CPU time 55.01 seconds
Started Apr 21 03:59:13 PM PDT 24
Finished Apr 21 04:00:08 PM PDT 24
Peak memory 204296 kb
Host smart-3934ae81-6cb3-4faf-a387-e31cc1f2e144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22976
88937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.2297688937
Directory /workspace/10.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/10.usbdev_pkt_received.119263739
Short name T404
Test name
Test status
Simulation time 8401143492 ps
CPU time 7.79 seconds
Started Apr 21 03:59:11 PM PDT 24
Finished Apr 21 03:59:19 PM PDT 24
Peak memory 204024 kb
Host smart-4d9a4557-e558-482d-81cb-371c01538857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11926
3739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.119263739
Directory /workspace/10.usbdev_pkt_received/latest


Test location /workspace/coverage/default/10.usbdev_pkt_sent.891194352
Short name T512
Test name
Test status
Simulation time 8478663779 ps
CPU time 8.44 seconds
Started Apr 21 03:59:13 PM PDT 24
Finished Apr 21 03:59:22 PM PDT 24
Peak memory 204060 kb
Host smart-69502a4c-08ac-4795-a522-7400642d193d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89119
4352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.891194352
Directory /workspace/10.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.3295546242
Short name T340
Test name
Test status
Simulation time 8414760955 ps
CPU time 8.61 seconds
Started Apr 21 03:59:12 PM PDT 24
Finished Apr 21 03:59:21 PM PDT 24
Peak memory 204052 kb
Host smart-a8384289-220e-4057-83f8-9b21c0cf1281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32955
46242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.3295546242
Directory /workspace/10.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/10.usbdev_setup_stage.2469657860
Short name T733
Test name
Test status
Simulation time 8376028941 ps
CPU time 7.94 seconds
Started Apr 21 03:59:16 PM PDT 24
Finished Apr 21 03:59:24 PM PDT 24
Peak memory 204048 kb
Host smart-ec1146b5-d23c-4e1c-ac7b-b944409f9b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24696
57860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.2469657860
Directory /workspace/10.usbdev_setup_stage/latest


Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.759369098
Short name T1369
Test name
Test status
Simulation time 8402725754 ps
CPU time 8.01 seconds
Started Apr 21 03:59:14 PM PDT 24
Finished Apr 21 03:59:22 PM PDT 24
Peak memory 204060 kb
Host smart-0ff9310d-21b2-4e5f-9ba5-1a6bf6178dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75936
9098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.759369098
Directory /workspace/10.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.25707331
Short name T29
Test name
Test status
Simulation time 8414038712 ps
CPU time 7.99 seconds
Started Apr 21 03:59:15 PM PDT 24
Finished Apr 21 03:59:23 PM PDT 24
Peak memory 204056 kb
Host smart-c6765991-fabe-4305-bc69-c899b70e88d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25707
331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.25707331
Directory /workspace/10.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/10.usbdev_stall_trans.409566013
Short name T1268
Test name
Test status
Simulation time 8397349946 ps
CPU time 8.27 seconds
Started Apr 21 03:59:13 PM PDT 24
Finished Apr 21 03:59:22 PM PDT 24
Peak memory 204048 kb
Host smart-37849ff0-5d9f-4f1d-978b-189990aab7ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40956
6013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.409566013
Directory /workspace/10.usbdev_stall_trans/latest


Test location /workspace/coverage/default/11.max_length_in_transaction.3655207770
Short name T428
Test name
Test status
Simulation time 8480596211 ps
CPU time 8.03 seconds
Started Apr 21 03:59:32 PM PDT 24
Finished Apr 21 03:59:40 PM PDT 24
Peak memory 204040 kb
Host smart-3b3b8798-1b59-4fe4-a6c2-b4b8a67e32dd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3655207770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.3655207770
Directory /workspace/11.max_length_in_transaction/latest


Test location /workspace/coverage/default/11.min_length_in_transaction.3713794708
Short name T682
Test name
Test status
Simulation time 8415400478 ps
CPU time 8.64 seconds
Started Apr 21 03:59:33 PM PDT 24
Finished Apr 21 03:59:42 PM PDT 24
Peak memory 204068 kb
Host smart-a6a4b53b-2ebf-467d-bbc6-eb0ac39438ed
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3713794708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.3713794708
Directory /workspace/11.min_length_in_transaction/latest


Test location /workspace/coverage/default/11.random_length_in_trans.674413218
Short name T449
Test name
Test status
Simulation time 8433484441 ps
CPU time 8.12 seconds
Started Apr 21 03:59:31 PM PDT 24
Finished Apr 21 03:59:39 PM PDT 24
Peak memory 203964 kb
Host smart-7f000f0f-8645-4594-9a57-eb3c3515d19b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67441
3218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.674413218
Directory /workspace/11.random_length_in_trans/latest


Test location /workspace/coverage/default/11.usbdev_av_buffer.612692498
Short name T975
Test name
Test status
Simulation time 8379296748 ps
CPU time 7.9 seconds
Started Apr 21 03:59:23 PM PDT 24
Finished Apr 21 03:59:31 PM PDT 24
Peak memory 204068 kb
Host smart-25ba4a7c-48f7-4c88-9d4b-90c07cf8bdbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61269
2498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.612692498
Directory /workspace/11.usbdev_av_buffer/latest


Test location /workspace/coverage/default/11.usbdev_enable.458285859
Short name T1170
Test name
Test status
Simulation time 8376811790 ps
CPU time 7.64 seconds
Started Apr 21 03:59:24 PM PDT 24
Finished Apr 21 03:59:32 PM PDT 24
Peak memory 204068 kb
Host smart-ef187f18-e27f-4b26-b29f-a7a7abfc72bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45828
5859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.458285859
Directory /workspace/11.usbdev_enable/latest


Test location /workspace/coverage/default/11.usbdev_fifo_rst.274993511
Short name T1376
Test name
Test status
Simulation time 103064069 ps
CPU time 1.67 seconds
Started Apr 21 03:59:23 PM PDT 24
Finished Apr 21 03:59:25 PM PDT 24
Peak memory 204120 kb
Host smart-027da02d-0bb9-4009-884f-01cfe5cb8b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27499
3511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.274993511
Directory /workspace/11.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/11.usbdev_in_iso.2261997079
Short name T500
Test name
Test status
Simulation time 8469217428 ps
CPU time 7.82 seconds
Started Apr 21 03:59:31 PM PDT 24
Finished Apr 21 03:59:39 PM PDT 24
Peak memory 204064 kb
Host smart-91f4a068-80d8-4a97-9194-21da166a0258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22619
97079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.2261997079
Directory /workspace/11.usbdev_in_iso/latest


Test location /workspace/coverage/default/11.usbdev_in_stall.3988198869
Short name T195
Test name
Test status
Simulation time 8364761724 ps
CPU time 8.33 seconds
Started Apr 21 03:59:33 PM PDT 24
Finished Apr 21 03:59:42 PM PDT 24
Peak memory 204060 kb
Host smart-99435a51-8ba9-4165-b724-2f36bf227d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39881
98869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3988198869
Directory /workspace/11.usbdev_in_stall/latest


Test location /workspace/coverage/default/11.usbdev_in_trans.1154019627
Short name T385
Test name
Test status
Simulation time 8448881273 ps
CPU time 8.91 seconds
Started Apr 21 03:59:28 PM PDT 24
Finished Apr 21 03:59:37 PM PDT 24
Peak memory 204036 kb
Host smart-6ae4d6f8-2675-4c34-a3d6-45fdbdfb9074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11540
19627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.1154019627
Directory /workspace/11.usbdev_in_trans/latest


Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.813606095
Short name T280
Test name
Test status
Simulation time 8455797819 ps
CPU time 10.82 seconds
Started Apr 21 03:59:27 PM PDT 24
Finished Apr 21 03:59:38 PM PDT 24
Peak memory 204060 kb
Host smart-1cef1091-b960-43e3-8f77-4de50a7f1d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81360
6095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.813606095
Directory /workspace/11.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2665482683
Short name T410
Test name
Test status
Simulation time 8375315493 ps
CPU time 8.25 seconds
Started Apr 21 03:59:26 PM PDT 24
Finished Apr 21 03:59:35 PM PDT 24
Peak memory 204056 kb
Host smart-f4b2a827-24f2-4654-bfb9-1452072e68a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26654
82683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2665482683
Directory /workspace/11.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/11.usbdev_nak_trans.127963805
Short name T795
Test name
Test status
Simulation time 8413260278 ps
CPU time 7.66 seconds
Started Apr 21 03:59:25 PM PDT 24
Finished Apr 21 03:59:33 PM PDT 24
Peak memory 203948 kb
Host smart-22976263-59df-4d9a-acbf-c8d7313d577b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12796
3805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.127963805
Directory /workspace/11.usbdev_nak_trans/latest


Test location /workspace/coverage/default/11.usbdev_out_stall.369372623
Short name T569
Test name
Test status
Simulation time 8381697320 ps
CPU time 9.67 seconds
Started Apr 21 03:59:25 PM PDT 24
Finished Apr 21 03:59:35 PM PDT 24
Peak memory 204068 kb
Host smart-d6327073-ba79-47f8-a3fa-38e12d80149f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36937
2623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.369372623
Directory /workspace/11.usbdev_out_stall/latest


Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1425314206
Short name T874
Test name
Test status
Simulation time 8392771634 ps
CPU time 8.05 seconds
Started Apr 21 03:59:26 PM PDT 24
Finished Apr 21 03:59:35 PM PDT 24
Peak memory 204052 kb
Host smart-e6ce6dfc-f97c-4191-b5df-6389dc4dc31d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14253
14206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1425314206
Directory /workspace/11.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/11.usbdev_pending_in_trans.2799322142
Short name T1275
Test name
Test status
Simulation time 8393231888 ps
CPU time 10.34 seconds
Started Apr 21 03:59:28 PM PDT 24
Finished Apr 21 03:59:39 PM PDT 24
Peak memory 204056 kb
Host smart-cb591001-9509-4181-a893-dc7914c323bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27993
22142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.2799322142
Directory /workspace/11.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.1604487809
Short name T348
Test name
Test status
Simulation time 8362830017 ps
CPU time 8.65 seconds
Started Apr 21 03:59:29 PM PDT 24
Finished Apr 21 03:59:38 PM PDT 24
Peak memory 204080 kb
Host smart-6d51eb6f-56fb-4a3e-b20d-7864d31e0b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16044
87809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.1604487809
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.4197043458
Short name T347
Test name
Test status
Simulation time 243287189 ps
CPU time 0.87 seconds
Started Apr 21 03:59:30 PM PDT 24
Finished Apr 21 03:59:31 PM PDT 24
Peak memory 203956 kb
Host smart-8422bd27-64a2-48a9-8e42-bb3cf7b205bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41970
43458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.4197043458
Directory /workspace/11.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/11.usbdev_pkt_buffer.3711487447
Short name T246
Test name
Test status
Simulation time 22171471654 ps
CPU time 42.41 seconds
Started Apr 21 03:59:28 PM PDT 24
Finished Apr 21 04:00:11 PM PDT 24
Peak memory 204348 kb
Host smart-449da869-3432-46f6-817c-53452ee43c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37114
87447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.3711487447
Directory /workspace/11.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/11.usbdev_pkt_received.3672690637
Short name T274
Test name
Test status
Simulation time 8386662029 ps
CPU time 8.01 seconds
Started Apr 21 03:59:30 PM PDT 24
Finished Apr 21 03:59:38 PM PDT 24
Peak memory 204048 kb
Host smart-a28e4d12-8f26-43b3-a6b6-3b2d56169b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36726
90637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3672690637
Directory /workspace/11.usbdev_pkt_received/latest


Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.1780442059
Short name T333
Test name
Test status
Simulation time 8406110105 ps
CPU time 9.44 seconds
Started Apr 21 03:59:28 PM PDT 24
Finished Apr 21 03:59:37 PM PDT 24
Peak memory 204040 kb
Host smart-e2a160ed-4b28-4a67-9c7c-6a12c302e27f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17804
42059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.1780442059
Directory /workspace/11.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.4281551906
Short name T1327
Test name
Test status
Simulation time 8370708682 ps
CPU time 8.41 seconds
Started Apr 21 03:59:28 PM PDT 24
Finished Apr 21 03:59:37 PM PDT 24
Peak memory 204072 kb
Host smart-f45c27c8-2f73-433b-9ef0-19f295937966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42815
51906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.4281551906
Directory /workspace/11.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/11.usbdev_smoke.3886979027
Short name T1340
Test name
Test status
Simulation time 8404844735 ps
CPU time 7.81 seconds
Started Apr 21 03:59:20 PM PDT 24
Finished Apr 21 03:59:28 PM PDT 24
Peak memory 204068 kb
Host smart-02cc247c-58c9-4338-b017-e48ad345a15c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38869
79027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.3886979027
Directory /workspace/11.usbdev_smoke/latest


Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.3890842222
Short name T930
Test name
Test status
Simulation time 8397329602 ps
CPU time 7.75 seconds
Started Apr 21 03:59:30 PM PDT 24
Finished Apr 21 03:59:37 PM PDT 24
Peak memory 204028 kb
Host smart-d873b9fa-35a4-4ebd-9c1b-37fa326c14f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38908
42222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.3890842222
Directory /workspace/11.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/11.usbdev_stall_trans.1084129782
Short name T991
Test name
Test status
Simulation time 8414223659 ps
CPU time 8.06 seconds
Started Apr 21 03:59:30 PM PDT 24
Finished Apr 21 03:59:38 PM PDT 24
Peak memory 204032 kb
Host smart-8aa608e3-7a42-4e56-b361-85799b091134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10841
29782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.1084129782
Directory /workspace/11.usbdev_stall_trans/latest


Test location /workspace/coverage/default/12.max_length_in_transaction.1773928688
Short name T916
Test name
Test status
Simulation time 8465324194 ps
CPU time 8.29 seconds
Started Apr 21 03:59:43 PM PDT 24
Finished Apr 21 03:59:52 PM PDT 24
Peak memory 204000 kb
Host smart-1e1b4cc5-ff02-496c-bab8-218ee0cd3f4b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1773928688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.1773928688
Directory /workspace/12.max_length_in_transaction/latest


Test location /workspace/coverage/default/12.min_length_in_transaction.2623271439
Short name T402
Test name
Test status
Simulation time 8376238170 ps
CPU time 9.23 seconds
Started Apr 21 03:59:43 PM PDT 24
Finished Apr 21 03:59:52 PM PDT 24
Peak memory 204068 kb
Host smart-aed0d2f5-082f-4f12-881a-2372824c7f24
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2623271439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.2623271439
Directory /workspace/12.min_length_in_transaction/latest


Test location /workspace/coverage/default/12.random_length_in_trans.80993166
Short name T945
Test name
Test status
Simulation time 8430295458 ps
CPU time 7.78 seconds
Started Apr 21 03:59:44 PM PDT 24
Finished Apr 21 03:59:53 PM PDT 24
Peak memory 204028 kb
Host smart-0c2e67cf-35eb-45d8-9e81-fbf28c997d64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80993
166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.80993166
Directory /workspace/12.random_length_in_trans/latest


Test location /workspace/coverage/default/12.usbdev_av_buffer.2277551930
Short name T1033
Test name
Test status
Simulation time 8413002436 ps
CPU time 8.81 seconds
Started Apr 21 03:59:33 PM PDT 24
Finished Apr 21 03:59:42 PM PDT 24
Peak memory 204088 kb
Host smart-be8895db-1dbc-4354-a42b-54f6f3deec6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22775
51930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2277551930
Directory /workspace/12.usbdev_av_buffer/latest


Test location /workspace/coverage/default/12.usbdev_enable.2863215918
Short name T1308
Test name
Test status
Simulation time 8386939276 ps
CPU time 9.68 seconds
Started Apr 21 03:59:39 PM PDT 24
Finished Apr 21 03:59:49 PM PDT 24
Peak memory 204064 kb
Host smart-66c7e2a1-c1e9-423d-b947-fecb8354527f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28632
15918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.2863215918
Directory /workspace/12.usbdev_enable/latest


Test location /workspace/coverage/default/12.usbdev_fifo_rst.494415009
Short name T911
Test name
Test status
Simulation time 157403958 ps
CPU time 1.21 seconds
Started Apr 21 03:59:38 PM PDT 24
Finished Apr 21 03:59:40 PM PDT 24
Peak memory 204148 kb
Host smart-faee0e89-d9ad-489e-8882-1e01e92430d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49441
5009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.494415009
Directory /workspace/12.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/12.usbdev_in_stall.1047397350
Short name T186
Test name
Test status
Simulation time 8373242980 ps
CPU time 8.21 seconds
Started Apr 21 03:59:44 PM PDT 24
Finished Apr 21 03:59:52 PM PDT 24
Peak memory 204064 kb
Host smart-7e6346e0-e156-4eeb-895c-7bddf02a01dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10473
97350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.1047397350
Directory /workspace/12.usbdev_in_stall/latest


Test location /workspace/coverage/default/12.usbdev_in_trans.3853131860
Short name T1253
Test name
Test status
Simulation time 8421905922 ps
CPU time 8.09 seconds
Started Apr 21 03:59:36 PM PDT 24
Finished Apr 21 03:59:44 PM PDT 24
Peak memory 204040 kb
Host smart-73897aaf-e48f-479d-a286-81794f703448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38531
31860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.3853131860
Directory /workspace/12.usbdev_in_trans/latest


Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1173575195
Short name T574
Test name
Test status
Simulation time 8411185820 ps
CPU time 8.76 seconds
Started Apr 21 03:59:34 PM PDT 24
Finished Apr 21 03:59:43 PM PDT 24
Peak memory 204032 kb
Host smart-6cfc7894-caa1-4469-8f18-7483b72da2c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11735
75195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1173575195
Directory /workspace/12.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.1402251072
Short name T1219
Test name
Test status
Simulation time 8370802764 ps
CPU time 7.39 seconds
Started Apr 21 03:59:37 PM PDT 24
Finished Apr 21 03:59:45 PM PDT 24
Peak memory 203996 kb
Host smart-9f0581ef-2927-4108-8369-59dc9aa20856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14022
51072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.1402251072
Directory /workspace/12.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/12.usbdev_out_stall.4056540301
Short name T305
Test name
Test status
Simulation time 8373227780 ps
CPU time 7.58 seconds
Started Apr 21 03:59:38 PM PDT 24
Finished Apr 21 03:59:45 PM PDT 24
Peak memory 204068 kb
Host smart-d9152b50-d23d-4cf8-bdbf-b64a59fb471c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40565
40301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.4056540301
Directory /workspace/12.usbdev_out_stall/latest


Test location /workspace/coverage/default/12.usbdev_out_trans_nak.3976889390
Short name T650
Test name
Test status
Simulation time 8405371717 ps
CPU time 8.04 seconds
Started Apr 21 03:59:38 PM PDT 24
Finished Apr 21 03:59:46 PM PDT 24
Peak memory 204044 kb
Host smart-140fccc5-0165-4fc6-b7a8-ac55004bbaff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39768
89390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.3976889390
Directory /workspace/12.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.2438209587
Short name T1272
Test name
Test status
Simulation time 8371695969 ps
CPU time 8.84 seconds
Started Apr 21 03:59:44 PM PDT 24
Finished Apr 21 03:59:54 PM PDT 24
Peak memory 204036 kb
Host smart-769c2194-42e1-4667-94de-78aa16bc2441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24382
09587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.2438209587
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.641221619
Short name T1146
Test name
Test status
Simulation time 63249838 ps
CPU time 0.71 seconds
Started Apr 21 03:59:42 PM PDT 24
Finished Apr 21 03:59:43 PM PDT 24
Peak memory 203940 kb
Host smart-70ffa8e9-1ec3-429c-a08e-2342d9da0bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64122
1619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.641221619
Directory /workspace/12.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/12.usbdev_pkt_buffer.2855655126
Short name T1310
Test name
Test status
Simulation time 23039032557 ps
CPU time 45.87 seconds
Started Apr 21 03:59:37 PM PDT 24
Finished Apr 21 04:00:23 PM PDT 24
Peak memory 204332 kb
Host smart-9e1f7770-65e2-4ceb-aadf-70f12319d0aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28556
55126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.2855655126
Directory /workspace/12.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/12.usbdev_pkt_received.851445796
Short name T298
Test name
Test status
Simulation time 8406799802 ps
CPU time 8.35 seconds
Started Apr 21 03:59:41 PM PDT 24
Finished Apr 21 03:59:50 PM PDT 24
Peak memory 204044 kb
Host smart-9150aa8d-2370-4ac2-8ca3-4e7530de6a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85144
5796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.851445796
Directory /workspace/12.usbdev_pkt_received/latest


Test location /workspace/coverage/default/12.usbdev_pkt_sent.2359714852
Short name T83
Test name
Test status
Simulation time 8423146615 ps
CPU time 9.2 seconds
Started Apr 21 03:59:41 PM PDT 24
Finished Apr 21 03:59:51 PM PDT 24
Peak memory 204060 kb
Host smart-de6d37af-9f7f-46f4-a176-03fa42c3a1bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23597
14852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2359714852
Directory /workspace/12.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.2009292551
Short name T1023
Test name
Test status
Simulation time 8400834677 ps
CPU time 8.82 seconds
Started Apr 21 03:59:46 PM PDT 24
Finished Apr 21 03:59:55 PM PDT 24
Peak memory 204080 kb
Host smart-de4f0253-7418-4665-b249-6a44ab5500ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20092
92551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.2009292551
Directory /workspace/12.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/12.usbdev_setup_stage.452151591
Short name T1053
Test name
Test status
Simulation time 8378619008 ps
CPU time 7.95 seconds
Started Apr 21 03:59:42 PM PDT 24
Finished Apr 21 03:59:50 PM PDT 24
Peak memory 204016 kb
Host smart-9a173208-7728-4550-8aca-1edb2ba3358d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45215
1591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.452151591
Directory /workspace/12.usbdev_setup_stage/latest


Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.143128562
Short name T1245
Test name
Test status
Simulation time 8382618434 ps
CPU time 8.48 seconds
Started Apr 21 03:59:42 PM PDT 24
Finished Apr 21 03:59:51 PM PDT 24
Peak memory 204032 kb
Host smart-1b3604aa-c569-4151-b15a-c65ae1e42acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14312
8562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.143128562
Directory /workspace/12.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/12.usbdev_smoke.845353269
Short name T1263
Test name
Test status
Simulation time 8465552416 ps
CPU time 10.61 seconds
Started Apr 21 03:59:34 PM PDT 24
Finished Apr 21 03:59:45 PM PDT 24
Peak memory 204068 kb
Host smart-0a326243-2b69-4add-932c-dc7ef460fa02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84535
3269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.845353269
Directory /workspace/12.usbdev_smoke/latest


Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.2288341184
Short name T508
Test name
Test status
Simulation time 8407342642 ps
CPU time 9.7 seconds
Started Apr 21 03:59:41 PM PDT 24
Finished Apr 21 03:59:51 PM PDT 24
Peak memory 204052 kb
Host smart-dc3b1fd5-1870-439f-b65c-2ea56ce50cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22883
41184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.2288341184
Directory /workspace/12.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/12.usbdev_stall_trans.1374267616
Short name T925
Test name
Test status
Simulation time 8390508272 ps
CPU time 7.83 seconds
Started Apr 21 03:59:40 PM PDT 24
Finished Apr 21 03:59:48 PM PDT 24
Peak memory 203964 kb
Host smart-78a7cb8c-a42c-4a13-832b-c9e3193ef092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13742
67616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1374267616
Directory /workspace/12.usbdev_stall_trans/latest


Test location /workspace/coverage/default/13.min_length_in_transaction.3665810269
Short name T1070
Test name
Test status
Simulation time 8382060229 ps
CPU time 7.74 seconds
Started Apr 21 03:59:52 PM PDT 24
Finished Apr 21 04:00:00 PM PDT 24
Peak memory 204020 kb
Host smart-d44f7d98-b55b-472a-b2ea-eeb9a643c1bd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3665810269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.3665810269
Directory /workspace/13.min_length_in_transaction/latest


Test location /workspace/coverage/default/13.random_length_in_trans.3859552922
Short name T474
Test name
Test status
Simulation time 8470828303 ps
CPU time 7.97 seconds
Started Apr 21 03:59:54 PM PDT 24
Finished Apr 21 04:00:02 PM PDT 24
Peak memory 204220 kb
Host smart-ce4cc7c6-95e0-4057-bc6c-8ef86330ca37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38595
52922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.3859552922
Directory /workspace/13.random_length_in_trans/latest


Test location /workspace/coverage/default/13.usbdev_av_buffer.2143370198
Short name T1258
Test name
Test status
Simulation time 8412726569 ps
CPU time 7.92 seconds
Started Apr 21 03:59:45 PM PDT 24
Finished Apr 21 03:59:53 PM PDT 24
Peak memory 204008 kb
Host smart-ccb3f46c-deb3-4d73-859a-6fe259095a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21433
70198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.2143370198
Directory /workspace/13.usbdev_av_buffer/latest


Test location /workspace/coverage/default/13.usbdev_enable.1450422794
Short name T501
Test name
Test status
Simulation time 8383188053 ps
CPU time 8.48 seconds
Started Apr 21 03:59:46 PM PDT 24
Finished Apr 21 03:59:54 PM PDT 24
Peak memory 204084 kb
Host smart-8c2e5b35-17cd-47cf-a7f3-a79afe02dc7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14504
22794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.1450422794
Directory /workspace/13.usbdev_enable/latest


Test location /workspace/coverage/default/13.usbdev_fifo_rst.3840884300
Short name T697
Test name
Test status
Simulation time 211914124 ps
CPU time 1.81 seconds
Started Apr 21 03:59:49 PM PDT 24
Finished Apr 21 03:59:51 PM PDT 24
Peak memory 204088 kb
Host smart-9e813726-a25b-4b7e-b05a-b0e690842d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38408
84300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.3840884300
Directory /workspace/13.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/13.usbdev_in_iso.2548214602
Short name T450
Test name
Test status
Simulation time 8422502583 ps
CPU time 10.21 seconds
Started Apr 21 03:59:57 PM PDT 24
Finished Apr 21 04:00:07 PM PDT 24
Peak memory 204028 kb
Host smart-cca72146-3e7f-4b55-9612-ec889d1e0279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25482
14602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.2548214602
Directory /workspace/13.usbdev_in_iso/latest


Test location /workspace/coverage/default/13.usbdev_in_stall.3231619180
Short name T1197
Test name
Test status
Simulation time 8377664495 ps
CPU time 8.69 seconds
Started Apr 21 03:59:52 PM PDT 24
Finished Apr 21 04:00:01 PM PDT 24
Peak memory 204036 kb
Host smart-4f0ae9f8-bc23-4840-a5f1-2fadcbea6ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32316
19180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.3231619180
Directory /workspace/13.usbdev_in_stall/latest


Test location /workspace/coverage/default/13.usbdev_in_trans.2667534522
Short name T151
Test name
Test status
Simulation time 8449432545 ps
CPU time 7.76 seconds
Started Apr 21 03:59:49 PM PDT 24
Finished Apr 21 03:59:57 PM PDT 24
Peak memory 204040 kb
Host smart-f5b279bf-9d87-4a4b-af9a-71729b00be5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26675
34522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.2667534522
Directory /workspace/13.usbdev_in_trans/latest


Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.645080672
Short name T570
Test name
Test status
Simulation time 8420525515 ps
CPU time 8.01 seconds
Started Apr 21 03:59:48 PM PDT 24
Finished Apr 21 03:59:57 PM PDT 24
Peak memory 204072 kb
Host smart-5644e9f8-a3e3-420d-bf78-b6eb801de0df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64508
0672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.645080672
Directory /workspace/13.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.3080738789
Short name T717
Test name
Test status
Simulation time 8369135273 ps
CPU time 10.24 seconds
Started Apr 21 03:59:48 PM PDT 24
Finished Apr 21 03:59:59 PM PDT 24
Peak memory 204068 kb
Host smart-f2883996-14cb-4254-8fbb-730cbcde4424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30807
38789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.3080738789
Directory /workspace/13.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/13.usbdev_nak_trans.3804825476
Short name T134
Test name
Test status
Simulation time 8487308726 ps
CPU time 7.99 seconds
Started Apr 21 03:59:48 PM PDT 24
Finished Apr 21 03:59:57 PM PDT 24
Peak memory 204040 kb
Host smart-1a944fa3-7679-4e4f-9573-449b6f774761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38048
25476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3804825476
Directory /workspace/13.usbdev_nak_trans/latest


Test location /workspace/coverage/default/13.usbdev_out_stall.3680721365
Short name T598
Test name
Test status
Simulation time 8395578275 ps
CPU time 9.18 seconds
Started Apr 21 03:59:48 PM PDT 24
Finished Apr 21 03:59:57 PM PDT 24
Peak memory 204052 kb
Host smart-28cffdfb-14e9-4346-97b0-db395c7bd586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36807
21365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3680721365
Directory /workspace/13.usbdev_out_stall/latest


Test location /workspace/coverage/default/13.usbdev_out_trans_nak.926171646
Short name T3
Test name
Test status
Simulation time 8376665017 ps
CPU time 7.76 seconds
Started Apr 21 03:59:49 PM PDT 24
Finished Apr 21 03:59:57 PM PDT 24
Peak memory 204064 kb
Host smart-ed6bea71-de47-47ab-9402-9226f449505e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92617
1646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.926171646
Directory /workspace/13.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.534238202
Short name T659
Test name
Test status
Simulation time 8367561957 ps
CPU time 8.58 seconds
Started Apr 21 03:59:57 PM PDT 24
Finished Apr 21 04:00:06 PM PDT 24
Peak memory 204028 kb
Host smart-bef89685-166b-4425-a7aa-2d4a49d482e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53423
8202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.534238202
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.4225368536
Short name T323
Test name
Test status
Simulation time 81355378 ps
CPU time 0.69 seconds
Started Apr 21 03:59:54 PM PDT 24
Finished Apr 21 03:59:55 PM PDT 24
Peak memory 204092 kb
Host smart-e1cb4d27-48ab-458c-8f4c-649d9f3740fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42253
68536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.4225368536
Directory /workspace/13.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/13.usbdev_pkt_buffer.2857480351
Short name T209
Test name
Test status
Simulation time 25902933132 ps
CPU time 48.61 seconds
Started Apr 21 03:59:50 PM PDT 24
Finished Apr 21 04:00:39 PM PDT 24
Peak memory 204328 kb
Host smart-7a1e5cea-e560-424d-8870-ea3ee7fee82f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28574
80351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.2857480351
Directory /workspace/13.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/13.usbdev_pkt_received.3232048626
Short name T969
Test name
Test status
Simulation time 8414221020 ps
CPU time 7.98 seconds
Started Apr 21 03:59:51 PM PDT 24
Finished Apr 21 03:59:59 PM PDT 24
Peak memory 203940 kb
Host smart-8dea3062-9348-4eb3-9198-bc02acaecc91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32320
48626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.3232048626
Directory /workspace/13.usbdev_pkt_received/latest


Test location /workspace/coverage/default/13.usbdev_pkt_sent.183303593
Short name T373
Test name
Test status
Simulation time 8419852270 ps
CPU time 8.15 seconds
Started Apr 21 03:59:52 PM PDT 24
Finished Apr 21 04:00:00 PM PDT 24
Peak memory 204064 kb
Host smart-563e3711-317f-4a4d-b83c-dfa5809b4c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18330
3593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.183303593
Directory /workspace/13.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.3760505760
Short name T1088
Test name
Test status
Simulation time 8448645643 ps
CPU time 8.45 seconds
Started Apr 21 03:59:52 PM PDT 24
Finished Apr 21 04:00:01 PM PDT 24
Peak memory 204072 kb
Host smart-385bc1b7-ad23-49f8-ab38-170e49898737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37605
05760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.3760505760
Directory /workspace/13.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/13.usbdev_setup_stage.657299263
Short name T563
Test name
Test status
Simulation time 8376259026 ps
CPU time 8.99 seconds
Started Apr 21 03:59:56 PM PDT 24
Finished Apr 21 04:00:05 PM PDT 24
Peak memory 204032 kb
Host smart-722c18e6-c8c7-40e3-929a-906d6c65b62c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65729
9263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.657299263
Directory /workspace/13.usbdev_setup_stage/latest


Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.774391372
Short name T746
Test name
Test status
Simulation time 8367851684 ps
CPU time 8.08 seconds
Started Apr 21 03:59:52 PM PDT 24
Finished Apr 21 04:00:01 PM PDT 24
Peak memory 204060 kb
Host smart-fe247a09-4145-49d7-8540-9568efb739d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77439
1372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.774391372
Directory /workspace/13.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.4180633934
Short name T692
Test name
Test status
Simulation time 8394471001 ps
CPU time 7.64 seconds
Started Apr 21 03:59:51 PM PDT 24
Finished Apr 21 03:59:59 PM PDT 24
Peak memory 204036 kb
Host smart-39f9ef09-2949-45c7-8c2a-0b6b4cc2eb1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41806
33934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.4180633934
Directory /workspace/13.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/13.usbdev_stall_trans.3663873625
Short name T511
Test name
Test status
Simulation time 8381055400 ps
CPU time 8.15 seconds
Started Apr 21 03:59:57 PM PDT 24
Finished Apr 21 04:00:05 PM PDT 24
Peak memory 204028 kb
Host smart-05e71b02-8293-4cbe-a581-efade624aa7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36638
73625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.3663873625
Directory /workspace/13.usbdev_stall_trans/latest


Test location /workspace/coverage/default/14.max_length_in_transaction.3380224731
Short name T317
Test name
Test status
Simulation time 8479696215 ps
CPU time 7.89 seconds
Started Apr 21 04:00:07 PM PDT 24
Finished Apr 21 04:00:15 PM PDT 24
Peak memory 204036 kb
Host smart-d70ca6e3-d6ea-430d-934d-0d64376adcd9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3380224731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.3380224731
Directory /workspace/14.max_length_in_transaction/latest


Test location /workspace/coverage/default/14.min_length_in_transaction.1257012003
Short name T284
Test name
Test status
Simulation time 8392374955 ps
CPU time 10.23 seconds
Started Apr 21 04:00:10 PM PDT 24
Finished Apr 21 04:00:21 PM PDT 24
Peak memory 204048 kb
Host smart-0447e2d6-a091-487d-ad48-61818b797bfe
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1257012003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.1257012003
Directory /workspace/14.min_length_in_transaction/latest


Test location /workspace/coverage/default/14.random_length_in_trans.1974972170
Short name T862
Test name
Test status
Simulation time 8501030939 ps
CPU time 8.62 seconds
Started Apr 21 04:00:08 PM PDT 24
Finished Apr 21 04:00:17 PM PDT 24
Peak memory 204060 kb
Host smart-bdc63ff2-316f-4c17-85d2-3eb0c7d6ade1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19749
72170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.1974972170
Directory /workspace/14.random_length_in_trans/latest


Test location /workspace/coverage/default/14.usbdev_av_buffer.3778445576
Short name T1174
Test name
Test status
Simulation time 8375052367 ps
CPU time 7.77 seconds
Started Apr 21 03:59:53 PM PDT 24
Finished Apr 21 04:00:01 PM PDT 24
Peak memory 204028 kb
Host smart-f07f4240-876a-4d01-acec-f8bda21a78a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37784
45576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3778445576
Directory /workspace/14.usbdev_av_buffer/latest


Test location /workspace/coverage/default/14.usbdev_enable.1683835212
Short name T936
Test name
Test status
Simulation time 8377199241 ps
CPU time 8.03 seconds
Started Apr 21 03:59:56 PM PDT 24
Finished Apr 21 04:00:05 PM PDT 24
Peak memory 204028 kb
Host smart-de2f4423-32ff-4377-813c-ab76d1502eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16838
35212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1683835212
Directory /workspace/14.usbdev_enable/latest


Test location /workspace/coverage/default/14.usbdev_fifo_rst.1770375906
Short name T788
Test name
Test status
Simulation time 46927374 ps
CPU time 1.13 seconds
Started Apr 21 03:59:57 PM PDT 24
Finished Apr 21 03:59:59 PM PDT 24
Peak memory 204156 kb
Host smart-32bd7b14-d5d6-41a3-80ec-f937c0917deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17703
75906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.1770375906
Directory /workspace/14.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/14.usbdev_in_iso.1565217222
Short name T555
Test name
Test status
Simulation time 8458532630 ps
CPU time 7.7 seconds
Started Apr 21 04:00:07 PM PDT 24
Finished Apr 21 04:00:15 PM PDT 24
Peak memory 204064 kb
Host smart-7bd4fcc2-c01c-4d4b-b372-089b49ee07f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15652
17222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.1565217222
Directory /workspace/14.usbdev_in_iso/latest


Test location /workspace/coverage/default/14.usbdev_in_stall.2189413383
Short name T585
Test name
Test status
Simulation time 8370231634 ps
CPU time 7.69 seconds
Started Apr 21 04:00:08 PM PDT 24
Finished Apr 21 04:00:16 PM PDT 24
Peak memory 204052 kb
Host smart-56441403-d748-4190-b45c-85c6db512da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21894
13383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.2189413383
Directory /workspace/14.usbdev_in_stall/latest


Test location /workspace/coverage/default/14.usbdev_in_trans.2268595056
Short name T1318
Test name
Test status
Simulation time 8399970845 ps
CPU time 9.26 seconds
Started Apr 21 03:59:57 PM PDT 24
Finished Apr 21 04:00:07 PM PDT 24
Peak memory 204040 kb
Host smart-c098d2b5-9c66-4415-93c7-b7cc26c5b083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22685
95056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2268595056
Directory /workspace/14.usbdev_in_trans/latest


Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.919130062
Short name T1247
Test name
Test status
Simulation time 8424696537 ps
CPU time 8.13 seconds
Started Apr 21 03:59:57 PM PDT 24
Finished Apr 21 04:00:06 PM PDT 24
Peak memory 204064 kb
Host smart-f9a88fc7-902b-4403-b133-104d80658035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91913
0062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.919130062
Directory /workspace/14.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.512062213
Short name T1129
Test name
Test status
Simulation time 8394739237 ps
CPU time 8.9 seconds
Started Apr 21 03:59:56 PM PDT 24
Finished Apr 21 04:00:05 PM PDT 24
Peak memory 204064 kb
Host smart-7fcd3c42-119d-4882-9a18-04a3efa94159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51206
2213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.512062213
Directory /workspace/14.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/14.usbdev_nak_trans.22445652
Short name T113
Test name
Test status
Simulation time 8442818682 ps
CPU time 7.86 seconds
Started Apr 21 03:59:57 PM PDT 24
Finished Apr 21 04:00:05 PM PDT 24
Peak memory 204080 kb
Host smart-028af6eb-657d-4a3c-8983-2d69e5a66a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22445
652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.22445652
Directory /workspace/14.usbdev_nak_trans/latest


Test location /workspace/coverage/default/14.usbdev_out_stall.499922772
Short name T390
Test name
Test status
Simulation time 8419762837 ps
CPU time 7.62 seconds
Started Apr 21 03:59:57 PM PDT 24
Finished Apr 21 04:00:05 PM PDT 24
Peak memory 204084 kb
Host smart-e25db67e-b69e-49c5-97f8-c9f3ea12e921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49992
2772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.499922772
Directory /workspace/14.usbdev_out_stall/latest


Test location /workspace/coverage/default/14.usbdev_out_trans_nak.3102012221
Short name T635
Test name
Test status
Simulation time 8427458310 ps
CPU time 10.12 seconds
Started Apr 21 03:59:59 PM PDT 24
Finished Apr 21 04:00:10 PM PDT 24
Peak memory 204060 kb
Host smart-8dfb375d-e920-4581-a9cf-394d57ebe0a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31020
12221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.3102012221
Directory /workspace/14.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/14.usbdev_pending_in_trans.2815264733
Short name T611
Test name
Test status
Simulation time 8415834663 ps
CPU time 8.29 seconds
Started Apr 21 04:00:05 PM PDT 24
Finished Apr 21 04:00:14 PM PDT 24
Peak memory 204048 kb
Host smart-10c52135-a70d-4852-a5a7-327d8f75ea21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28152
64733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.2815264733
Directory /workspace/14.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.1532834827
Short name T1234
Test name
Test status
Simulation time 8371521051 ps
CPU time 7.85 seconds
Started Apr 21 04:00:07 PM PDT 24
Finished Apr 21 04:00:15 PM PDT 24
Peak memory 204048 kb
Host smart-fe6f6f70-c99c-4b4e-9f3c-a67d3a07dbf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15328
34827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.1532834827
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.1608203977
Short name T672
Test name
Test status
Simulation time 60172257 ps
CPU time 0.68 seconds
Started Apr 21 04:00:08 PM PDT 24
Finished Apr 21 04:00:09 PM PDT 24
Peak memory 203932 kb
Host smart-bcc65132-6e62-4fb6-b485-40e4faf146ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16082
03977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.1608203977
Directory /workspace/14.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/14.usbdev_pkt_buffer.1278895753
Short name T1287
Test name
Test status
Simulation time 28843649254 ps
CPU time 69.87 seconds
Started Apr 21 03:59:59 PM PDT 24
Finished Apr 21 04:01:09 PM PDT 24
Peak memory 204352 kb
Host smart-50b103d6-9cbd-4503-acd2-c4e8c243955e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12788
95753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.1278895753
Directory /workspace/14.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/14.usbdev_pkt_received.2218311775
Short name T702
Test name
Test status
Simulation time 8446350236 ps
CPU time 8.17 seconds
Started Apr 21 03:59:59 PM PDT 24
Finished Apr 21 04:00:07 PM PDT 24
Peak memory 204048 kb
Host smart-a2bdf398-734b-4f16-a6f2-c8c0101fd2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22183
11775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.2218311775
Directory /workspace/14.usbdev_pkt_received/latest


Test location /workspace/coverage/default/14.usbdev_pkt_sent.1327105007
Short name T38
Test name
Test status
Simulation time 8485609289 ps
CPU time 8.88 seconds
Started Apr 21 04:00:08 PM PDT 24
Finished Apr 21 04:00:18 PM PDT 24
Peak memory 204056 kb
Host smart-ae7e6fd3-0bd2-4c66-87a0-400257691c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13271
05007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.1327105007
Directory /workspace/14.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.28340405
Short name T938
Test name
Test status
Simulation time 8403268165 ps
CPU time 8.42 seconds
Started Apr 21 04:00:03 PM PDT 24
Finished Apr 21 04:00:12 PM PDT 24
Peak memory 204064 kb
Host smart-8738bcc3-3863-48bc-a512-27ed035d2737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28340
405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.28340405
Directory /workspace/14.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/14.usbdev_setup_stage.2906587913
Short name T770
Test name
Test status
Simulation time 8382679979 ps
CPU time 8.43 seconds
Started Apr 21 04:00:07 PM PDT 24
Finished Apr 21 04:00:16 PM PDT 24
Peak memory 204060 kb
Host smart-bfefab02-2e2d-4c3e-a306-1e6d192c34ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29065
87913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.2906587913
Directory /workspace/14.usbdev_setup_stage/latest


Test location /workspace/coverage/default/14.usbdev_smoke.2253310996
Short name T1368
Test name
Test status
Simulation time 8452115612 ps
CPU time 8.6 seconds
Started Apr 21 03:59:53 PM PDT 24
Finished Apr 21 04:00:02 PM PDT 24
Peak memory 204048 kb
Host smart-0f8dc7a8-9863-42a3-88dd-15b52d80ca28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22533
10996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.2253310996
Directory /workspace/14.usbdev_smoke/latest


Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2968895510
Short name T31
Test name
Test status
Simulation time 8379065518 ps
CPU time 9.58 seconds
Started Apr 21 04:00:05 PM PDT 24
Finished Apr 21 04:00:16 PM PDT 24
Peak memory 204056 kb
Host smart-3b070a33-fe92-4046-abf5-664ad72a8cf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29688
95510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2968895510
Directory /workspace/14.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/14.usbdev_stall_trans.642893550
Short name T843
Test name
Test status
Simulation time 8380340475 ps
CPU time 8.72 seconds
Started Apr 21 04:00:02 PM PDT 24
Finished Apr 21 04:00:11 PM PDT 24
Peak memory 204024 kb
Host smart-80830bf2-212e-4c89-84d8-c5029f58a79d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64289
3550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.642893550
Directory /workspace/14.usbdev_stall_trans/latest


Test location /workspace/coverage/default/15.max_length_in_transaction.996914829
Short name T49
Test name
Test status
Simulation time 8459418462 ps
CPU time 8.17 seconds
Started Apr 21 04:00:20 PM PDT 24
Finished Apr 21 04:00:28 PM PDT 24
Peak memory 204052 kb
Host smart-bb860ce7-ca2f-4da4-a1ce-f57174e05eeb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=996914829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.996914829
Directory /workspace/15.max_length_in_transaction/latest


Test location /workspace/coverage/default/15.min_length_in_transaction.3162773939
Short name T1115
Test name
Test status
Simulation time 8389735876 ps
CPU time 9.07 seconds
Started Apr 21 04:00:18 PM PDT 24
Finished Apr 21 04:00:27 PM PDT 24
Peak memory 203960 kb
Host smart-36c64b70-4291-4a1b-830a-f9532f908e20
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3162773939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.3162773939
Directory /workspace/15.min_length_in_transaction/latest


Test location /workspace/coverage/default/15.random_length_in_trans.2562337423
Short name T937
Test name
Test status
Simulation time 8427111889 ps
CPU time 8.62 seconds
Started Apr 21 04:00:19 PM PDT 24
Finished Apr 21 04:00:28 PM PDT 24
Peak memory 203948 kb
Host smart-9593e5b0-e4f0-45ee-b719-1e93f58ccfa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25623
37423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.2562337423
Directory /workspace/15.random_length_in_trans/latest


Test location /workspace/coverage/default/15.usbdev_av_buffer.2958287566
Short name T679
Test name
Test status
Simulation time 8381804016 ps
CPU time 8.12 seconds
Started Apr 21 04:00:08 PM PDT 24
Finished Apr 21 04:00:17 PM PDT 24
Peak memory 204088 kb
Host smart-d28578f7-ead2-494a-a358-14b087fb46b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29582
87566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2958287566
Directory /workspace/15.usbdev_av_buffer/latest


Test location /workspace/coverage/default/15.usbdev_enable.3894775195
Short name T1139
Test name
Test status
Simulation time 8403093466 ps
CPU time 8.28 seconds
Started Apr 21 04:00:17 PM PDT 24
Finished Apr 21 04:00:25 PM PDT 24
Peak memory 204036 kb
Host smart-68b19d31-4ef8-4244-8c48-cee526057352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38947
75195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.3894775195
Directory /workspace/15.usbdev_enable/latest


Test location /workspace/coverage/default/15.usbdev_fifo_rst.417278659
Short name T394
Test name
Test status
Simulation time 203609504 ps
CPU time 2.28 seconds
Started Apr 21 04:00:11 PM PDT 24
Finished Apr 21 04:00:14 PM PDT 24
Peak memory 204188 kb
Host smart-b90cf414-b4e4-42de-834b-b501624c1dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41727
8659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.417278659
Directory /workspace/15.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/15.usbdev_in_iso.1753741273
Short name T711
Test name
Test status
Simulation time 8437200434 ps
CPU time 8.55 seconds
Started Apr 21 04:00:19 PM PDT 24
Finished Apr 21 04:00:28 PM PDT 24
Peak memory 204044 kb
Host smart-4c50762b-67ff-4118-994c-2ae4576755f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17537
41273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.1753741273
Directory /workspace/15.usbdev_in_iso/latest


Test location /workspace/coverage/default/15.usbdev_in_trans.1304112543
Short name T1107
Test name
Test status
Simulation time 8409009137 ps
CPU time 7.95 seconds
Started Apr 21 04:00:17 PM PDT 24
Finished Apr 21 04:00:26 PM PDT 24
Peak memory 204036 kb
Host smart-ded0d907-5a44-449e-9aec-781d377f6742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13041
12543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.1304112543
Directory /workspace/15.usbdev_in_trans/latest


Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3223220183
Short name T881
Test name
Test status
Simulation time 8414454629 ps
CPU time 10.1 seconds
Started Apr 21 04:00:10 PM PDT 24
Finished Apr 21 04:00:20 PM PDT 24
Peak memory 204032 kb
Host smart-15ea2516-43e5-413c-9cc4-098c7cf07d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32232
20183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3223220183
Directory /workspace/15.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.1445065681
Short name T330
Test name
Test status
Simulation time 8399699057 ps
CPU time 10.09 seconds
Started Apr 21 04:00:12 PM PDT 24
Finished Apr 21 04:00:22 PM PDT 24
Peak memory 204064 kb
Host smart-4e6cdfca-8e8d-4fab-adb8-c85af66208c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14450
65681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.1445065681
Directory /workspace/15.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/15.usbdev_out_stall.1770002526
Short name T302
Test name
Test status
Simulation time 8383496197 ps
CPU time 8.36 seconds
Started Apr 21 04:00:11 PM PDT 24
Finished Apr 21 04:00:20 PM PDT 24
Peak memory 204068 kb
Host smart-d602fa45-503d-443a-90d2-89f08545493e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17700
02526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1770002526
Directory /workspace/15.usbdev_out_stall/latest


Test location /workspace/coverage/default/15.usbdev_out_trans_nak.3904634700
Short name T802
Test name
Test status
Simulation time 8416241702 ps
CPU time 8.22 seconds
Started Apr 21 04:00:17 PM PDT 24
Finished Apr 21 04:00:25 PM PDT 24
Peak memory 204032 kb
Host smart-78aee938-e709-4100-8d52-491f2d03ec76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39046
34700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.3904634700
Directory /workspace/15.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.453944134
Short name T536
Test name
Test status
Simulation time 8363895148 ps
CPU time 7.92 seconds
Started Apr 21 04:00:17 PM PDT 24
Finished Apr 21 04:00:25 PM PDT 24
Peak memory 204056 kb
Host smart-44d51635-3dff-4673-98e5-d5aaeda78c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45394
4134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.453944134
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.141654996
Short name T1294
Test name
Test status
Simulation time 107067757 ps
CPU time 0.73 seconds
Started Apr 21 04:00:16 PM PDT 24
Finished Apr 21 04:00:17 PM PDT 24
Peak memory 203952 kb
Host smart-b7fbe3af-54d9-419a-a5b7-386df84ebd46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14165
4996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.141654996
Directory /workspace/15.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/15.usbdev_pkt_buffer.107815134
Short name T1083
Test name
Test status
Simulation time 30291811817 ps
CPU time 65.25 seconds
Started Apr 21 04:00:14 PM PDT 24
Finished Apr 21 04:01:20 PM PDT 24
Peak memory 204312 kb
Host smart-3de95fee-801c-4130-8592-164bb8708d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10781
5134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.107815134
Directory /workspace/15.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/15.usbdev_pkt_received.577340348
Short name T1302
Test name
Test status
Simulation time 8414167072 ps
CPU time 7.86 seconds
Started Apr 21 04:00:14 PM PDT 24
Finished Apr 21 04:00:22 PM PDT 24
Peak memory 204064 kb
Host smart-1a6eb52c-a01a-4957-8a1b-ca9dd9d75d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57734
0348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.577340348
Directory /workspace/15.usbdev_pkt_received/latest


Test location /workspace/coverage/default/15.usbdev_pkt_sent.4212154209
Short name T1333
Test name
Test status
Simulation time 8407328209 ps
CPU time 7.78 seconds
Started Apr 21 04:00:14 PM PDT 24
Finished Apr 21 04:00:22 PM PDT 24
Peak memory 204044 kb
Host smart-54787376-865e-480c-835f-a921d0de80a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42121
54209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.4212154209
Directory /workspace/15.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.1191122028
Short name T923
Test name
Test status
Simulation time 8406260443 ps
CPU time 8.56 seconds
Started Apr 21 04:00:12 PM PDT 24
Finished Apr 21 04:00:21 PM PDT 24
Peak memory 204068 kb
Host smart-5f1732ec-82cb-442c-94cd-f6c513ae7adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11911
22028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.1191122028
Directory /workspace/15.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/15.usbdev_setup_stage.4204927724
Short name T988
Test name
Test status
Simulation time 8444628047 ps
CPU time 7.96 seconds
Started Apr 21 04:00:15 PM PDT 24
Finished Apr 21 04:00:24 PM PDT 24
Peak memory 204076 kb
Host smart-665b456e-2c8b-4197-af8c-94dfe0e89777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42049
27724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.4204927724
Directory /workspace/15.usbdev_setup_stage/latest


Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.3997583916
Short name T708
Test name
Test status
Simulation time 8379691469 ps
CPU time 9.11 seconds
Started Apr 21 04:00:15 PM PDT 24
Finished Apr 21 04:00:24 PM PDT 24
Peak memory 204048 kb
Host smart-63c491a3-574a-4d17-8ded-461fcea47154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39975
83916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.3997583916
Directory /workspace/15.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/15.usbdev_smoke.3356245921
Short name T161
Test name
Test status
Simulation time 8411345936 ps
CPU time 8.51 seconds
Started Apr 21 04:00:10 PM PDT 24
Finished Apr 21 04:00:18 PM PDT 24
Peak memory 204068 kb
Host smart-9569339b-7755-46a3-ac71-6840c6bffbf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33562
45921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3356245921
Directory /workspace/15.usbdev_smoke/latest


Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.3137840299
Short name T1150
Test name
Test status
Simulation time 8375775460 ps
CPU time 9.72 seconds
Started Apr 21 04:00:14 PM PDT 24
Finished Apr 21 04:00:24 PM PDT 24
Peak memory 204036 kb
Host smart-2514dd02-efbd-4c08-a307-0749e1083520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31378
40299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.3137840299
Directory /workspace/15.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/15.usbdev_stall_trans.2731672162
Short name T1229
Test name
Test status
Simulation time 8467931355 ps
CPU time 8.78 seconds
Started Apr 21 04:00:13 PM PDT 24
Finished Apr 21 04:00:22 PM PDT 24
Peak memory 203936 kb
Host smart-52d2bbbc-3bf1-4c99-b32d-a6c8648c60f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27316
72162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.2731672162
Directory /workspace/15.usbdev_stall_trans/latest


Test location /workspace/coverage/default/16.max_length_in_transaction.627185420
Short name T1181
Test name
Test status
Simulation time 8472714773 ps
CPU time 8 seconds
Started Apr 21 04:00:30 PM PDT 24
Finished Apr 21 04:00:38 PM PDT 24
Peak memory 204068 kb
Host smart-3ff89b0f-c92d-479d-96e4-e5a223308023
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=627185420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.627185420
Directory /workspace/16.max_length_in_transaction/latest


Test location /workspace/coverage/default/16.min_length_in_transaction.3589496097
Short name T984
Test name
Test status
Simulation time 8381131305 ps
CPU time 8.91 seconds
Started Apr 21 04:00:30 PM PDT 24
Finished Apr 21 04:00:39 PM PDT 24
Peak memory 204000 kb
Host smart-d2340210-3199-472d-ac9e-ccc3ec2b7248
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3589496097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.3589496097
Directory /workspace/16.min_length_in_transaction/latest


Test location /workspace/coverage/default/16.random_length_in_trans.136466312
Short name T208
Test name
Test status
Simulation time 8436719360 ps
CPU time 8.73 seconds
Started Apr 21 04:00:27 PM PDT 24
Finished Apr 21 04:00:36 PM PDT 24
Peak memory 204060 kb
Host smart-4736776a-1a78-4558-9646-4df7c0c74751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13646
6312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.136466312
Directory /workspace/16.random_length_in_trans/latest


Test location /workspace/coverage/default/16.usbdev_av_buffer.2456777778
Short name T281
Test name
Test status
Simulation time 8430190271 ps
CPU time 8 seconds
Started Apr 21 04:00:21 PM PDT 24
Finished Apr 21 04:00:29 PM PDT 24
Peak memory 203996 kb
Host smart-80320a17-6b8c-49f7-851b-50c159b9aed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24567
77778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2456777778
Directory /workspace/16.usbdev_av_buffer/latest


Test location /workspace/coverage/default/16.usbdev_enable.193964746
Short name T1363
Test name
Test status
Simulation time 8372581410 ps
CPU time 7.93 seconds
Started Apr 21 04:00:22 PM PDT 24
Finished Apr 21 04:00:30 PM PDT 24
Peak memory 204036 kb
Host smart-f3d1a326-4e8b-4286-b85b-cb99a9c61f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19396
4746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.193964746
Directory /workspace/16.usbdev_enable/latest


Test location /workspace/coverage/default/16.usbdev_fifo_rst.2202646084
Short name T434
Test name
Test status
Simulation time 76864363 ps
CPU time 1.84 seconds
Started Apr 21 04:00:28 PM PDT 24
Finished Apr 21 04:00:30 PM PDT 24
Peak memory 204156 kb
Host smart-ed613b56-b9a9-4206-845c-dade3354fe22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22026
46084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.2202646084
Directory /workspace/16.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/16.usbdev_in_iso.1020649026
Short name T612
Test name
Test status
Simulation time 8404237732 ps
CPU time 8.54 seconds
Started Apr 21 04:00:27 PM PDT 24
Finished Apr 21 04:00:36 PM PDT 24
Peak memory 204024 kb
Host smart-15fb7aae-1bb3-4122-9b56-7775495caf73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10206
49026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.1020649026
Directory /workspace/16.usbdev_in_iso/latest


Test location /workspace/coverage/default/16.usbdev_in_stall.3252023520
Short name T738
Test name
Test status
Simulation time 8439024553 ps
CPU time 7.47 seconds
Started Apr 21 04:00:28 PM PDT 24
Finished Apr 21 04:00:36 PM PDT 24
Peak memory 203988 kb
Host smart-e7893139-e2ca-4c75-a0e3-9529308da56c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32520
23520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.3252023520
Directory /workspace/16.usbdev_in_stall/latest


Test location /workspace/coverage/default/16.usbdev_in_trans.1044724997
Short name T1191
Test name
Test status
Simulation time 8385512971 ps
CPU time 8.98 seconds
Started Apr 21 04:00:23 PM PDT 24
Finished Apr 21 04:00:32 PM PDT 24
Peak memory 204024 kb
Host smart-88706418-72bb-4a9f-99bd-dc5aebf9ce89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10447
24997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.1044724997
Directory /workspace/16.usbdev_in_trans/latest


Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.2776558864
Short name T1208
Test name
Test status
Simulation time 8415023494 ps
CPU time 9.75 seconds
Started Apr 21 04:00:23 PM PDT 24
Finished Apr 21 04:00:33 PM PDT 24
Peak memory 204052 kb
Host smart-c19ceab7-8e03-494b-9a12-ae4f954a33c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27765
58864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.2776558864
Directory /workspace/16.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.1188800128
Short name T291
Test name
Test status
Simulation time 8367271382 ps
CPU time 8.62 seconds
Started Apr 21 04:00:23 PM PDT 24
Finished Apr 21 04:00:31 PM PDT 24
Peak memory 204044 kb
Host smart-9e3c54d8-e3c4-4072-86e2-d45529c99a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11888
00128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1188800128
Directory /workspace/16.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/16.usbdev_out_stall.4168077337
Short name T1273
Test name
Test status
Simulation time 8416801807 ps
CPU time 7.97 seconds
Started Apr 21 04:00:23 PM PDT 24
Finished Apr 21 04:00:31 PM PDT 24
Peak memory 204052 kb
Host smart-af218dfc-ece0-42f6-adde-9ebbbe360ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41680
77337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.4168077337
Directory /workspace/16.usbdev_out_stall/latest


Test location /workspace/coverage/default/16.usbdev_out_trans_nak.455332596
Short name T749
Test name
Test status
Simulation time 8378145916 ps
CPU time 8.34 seconds
Started Apr 21 04:00:24 PM PDT 24
Finished Apr 21 04:00:33 PM PDT 24
Peak memory 204064 kb
Host smart-32465b40-5cc4-4cb5-ad39-7ce8c04f6b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45533
2596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.455332596
Directory /workspace/16.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.1993445523
Short name T1366
Test name
Test status
Simulation time 8369454109 ps
CPU time 7.48 seconds
Started Apr 21 04:00:27 PM PDT 24
Finished Apr 21 04:00:34 PM PDT 24
Peak memory 204044 kb
Host smart-c544ce60-0424-4e7e-aa84-56ccec10329c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19934
45523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.1993445523
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/16.usbdev_pkt_buffer.1228084687
Short name T827
Test name
Test status
Simulation time 16199295430 ps
CPU time 28.61 seconds
Started Apr 21 04:00:24 PM PDT 24
Finished Apr 21 04:00:53 PM PDT 24
Peak memory 204372 kb
Host smart-28842c34-d126-45a2-ab8a-8e024f892d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12280
84687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.1228084687
Directory /workspace/16.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/16.usbdev_pkt_received.3095028429
Short name T1021
Test name
Test status
Simulation time 8382295994 ps
CPU time 8.5 seconds
Started Apr 21 04:00:27 PM PDT 24
Finished Apr 21 04:00:36 PM PDT 24
Peak memory 204048 kb
Host smart-fb471931-fb7c-4c60-9d11-bc40628c2913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30950
28429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3095028429
Directory /workspace/16.usbdev_pkt_received/latest


Test location /workspace/coverage/default/16.usbdev_pkt_sent.1000045425
Short name T1231
Test name
Test status
Simulation time 8455548880 ps
CPU time 7.62 seconds
Started Apr 21 04:00:26 PM PDT 24
Finished Apr 21 04:00:34 PM PDT 24
Peak memory 204060 kb
Host smart-e26c6c98-9e44-4cf8-a380-4c6fb834244b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10000
45425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.1000045425
Directory /workspace/16.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.1052360819
Short name T600
Test name
Test status
Simulation time 8382712567 ps
CPU time 8.78 seconds
Started Apr 21 04:00:24 PM PDT 24
Finished Apr 21 04:00:33 PM PDT 24
Peak memory 204064 kb
Host smart-57a6252a-8274-4de0-a791-9a98d11bf188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10523
60819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.1052360819
Directory /workspace/16.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/16.usbdev_setup_stage.3233588024
Short name T1123
Test name
Test status
Simulation time 8376299567 ps
CPU time 7.44 seconds
Started Apr 21 04:00:26 PM PDT 24
Finished Apr 21 04:00:34 PM PDT 24
Peak memory 204056 kb
Host smart-6c839003-578e-4fa5-a02b-7f433eefe624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32335
88024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3233588024
Directory /workspace/16.usbdev_setup_stage/latest


Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.431549309
Short name T301
Test name
Test status
Simulation time 8406840024 ps
CPU time 8.01 seconds
Started Apr 21 04:00:25 PM PDT 24
Finished Apr 21 04:00:33 PM PDT 24
Peak memory 203956 kb
Host smart-57ccbf01-033a-4843-bfa1-a7afe1f2f0ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43154
9309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.431549309
Directory /workspace/16.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.3833223652
Short name T395
Test name
Test status
Simulation time 8398330149 ps
CPU time 7.79 seconds
Started Apr 21 04:00:30 PM PDT 24
Finished Apr 21 04:00:38 PM PDT 24
Peak memory 203992 kb
Host smart-77f9c5b0-5bde-4e89-9e42-60eb95bf8fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38332
23652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.3833223652
Directory /workspace/16.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/16.usbdev_stall_trans.784853290
Short name T850
Test name
Test status
Simulation time 8390289575 ps
CPU time 8.82 seconds
Started Apr 21 04:00:30 PM PDT 24
Finished Apr 21 04:00:39 PM PDT 24
Peak memory 204008 kb
Host smart-5376e44a-35ac-48e8-b304-c6ae736c5ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78485
3290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.784853290
Directory /workspace/16.usbdev_stall_trans/latest


Test location /workspace/coverage/default/17.max_length_in_transaction.3976349465
Short name T838
Test name
Test status
Simulation time 8469141150 ps
CPU time 8.52 seconds
Started Apr 21 04:00:40 PM PDT 24
Finished Apr 21 04:00:49 PM PDT 24
Peak memory 204020 kb
Host smart-41a45253-f1ef-4fda-adfa-0d55b2228a91
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3976349465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.3976349465
Directory /workspace/17.max_length_in_transaction/latest


Test location /workspace/coverage/default/17.min_length_in_transaction.2715650928
Short name T889
Test name
Test status
Simulation time 8391413063 ps
CPU time 9.36 seconds
Started Apr 21 04:00:40 PM PDT 24
Finished Apr 21 04:00:50 PM PDT 24
Peak memory 203900 kb
Host smart-96715708-a6db-4d8e-8b1f-785ca92b06a7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2715650928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.2715650928
Directory /workspace/17.min_length_in_transaction/latest


Test location /workspace/coverage/default/17.random_length_in_trans.2395508539
Short name T1332
Test name
Test status
Simulation time 8447881859 ps
CPU time 8.66 seconds
Started Apr 21 04:00:36 PM PDT 24
Finished Apr 21 04:00:45 PM PDT 24
Peak memory 204040 kb
Host smart-87a36644-310c-445f-a708-146211f8836b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23955
08539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.2395508539
Directory /workspace/17.random_length_in_trans/latest


Test location /workspace/coverage/default/17.usbdev_av_buffer.1514189752
Short name T709
Test name
Test status
Simulation time 8378879346 ps
CPU time 7.87 seconds
Started Apr 21 04:00:30 PM PDT 24
Finished Apr 21 04:00:38 PM PDT 24
Peak memory 204052 kb
Host smart-9b6f5ff5-c736-4aeb-82aa-efb50cadf556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15141
89752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.1514189752
Directory /workspace/17.usbdev_av_buffer/latest


Test location /workspace/coverage/default/17.usbdev_enable.1393164951
Short name T641
Test name
Test status
Simulation time 8390582155 ps
CPU time 8.3 seconds
Started Apr 21 04:00:30 PM PDT 24
Finished Apr 21 04:00:39 PM PDT 24
Peak memory 204036 kb
Host smart-a8421856-26b3-4421-ad81-afefae498593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13931
64951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.1393164951
Directory /workspace/17.usbdev_enable/latest


Test location /workspace/coverage/default/17.usbdev_fifo_rst.2546573762
Short name T1014
Test name
Test status
Simulation time 48324992 ps
CPU time 1.07 seconds
Started Apr 21 04:00:30 PM PDT 24
Finished Apr 21 04:00:31 PM PDT 24
Peak memory 204292 kb
Host smart-048dc835-b70b-4ecf-8307-00e33d0c2536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25465
73762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.2546573762
Directory /workspace/17.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/17.usbdev_in_iso.4013245000
Short name T673
Test name
Test status
Simulation time 8435814402 ps
CPU time 8.96 seconds
Started Apr 21 04:00:36 PM PDT 24
Finished Apr 21 04:00:46 PM PDT 24
Peak memory 203936 kb
Host smart-5f0b1b64-52ed-4a6a-85fd-bccc71f5124c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40132
45000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.4013245000
Directory /workspace/17.usbdev_in_iso/latest


Test location /workspace/coverage/default/17.usbdev_in_stall.1166619291
Short name T437
Test name
Test status
Simulation time 8372332889 ps
CPU time 9.64 seconds
Started Apr 21 04:00:36 PM PDT 24
Finished Apr 21 04:00:46 PM PDT 24
Peak memory 204060 kb
Host smart-48cf77df-12c4-4656-a70d-358a3441c701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11666
19291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.1166619291
Directory /workspace/17.usbdev_in_stall/latest


Test location /workspace/coverage/default/17.usbdev_in_trans.1572838017
Short name T1292
Test name
Test status
Simulation time 8452339779 ps
CPU time 10.38 seconds
Started Apr 21 04:00:31 PM PDT 24
Finished Apr 21 04:00:42 PM PDT 24
Peak memory 204068 kb
Host smart-bd844dc6-0d35-4cdb-879e-a57ec70b933e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15728
38017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1572838017
Directory /workspace/17.usbdev_in_trans/latest


Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.1216734166
Short name T905
Test name
Test status
Simulation time 8458221918 ps
CPU time 8.67 seconds
Started Apr 21 04:00:35 PM PDT 24
Finished Apr 21 04:00:44 PM PDT 24
Peak memory 204064 kb
Host smart-d6c938f9-e381-4f17-8ad2-f92f5f719adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12167
34166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.1216734166
Directory /workspace/17.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.3665234140
Short name T1128
Test name
Test status
Simulation time 8364758786 ps
CPU time 7.85 seconds
Started Apr 21 04:00:32 PM PDT 24
Finished Apr 21 04:00:40 PM PDT 24
Peak memory 204044 kb
Host smart-6a276c16-aeaa-4cb4-9d24-80a9390381a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36652
34140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.3665234140
Directory /workspace/17.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/17.usbdev_out_stall.2608833689
Short name T705
Test name
Test status
Simulation time 8402229162 ps
CPU time 9.1 seconds
Started Apr 21 04:00:36 PM PDT 24
Finished Apr 21 04:00:46 PM PDT 24
Peak memory 203956 kb
Host smart-aad0f236-5129-48ee-82f5-c1f22a33374b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26088
33689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2608833689
Directory /workspace/17.usbdev_out_stall/latest


Test location /workspace/coverage/default/17.usbdev_out_trans_nak.3460199428
Short name T1112
Test name
Test status
Simulation time 8375848684 ps
CPU time 7.66 seconds
Started Apr 21 04:00:40 PM PDT 24
Finished Apr 21 04:00:48 PM PDT 24
Peak memory 204012 kb
Host smart-11d6e71f-b23a-403e-b299-a72de30ac7e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34601
99428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.3460199428
Directory /workspace/17.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1619350776
Short name T196
Test name
Test status
Simulation time 8462604029 ps
CPU time 8.18 seconds
Started Apr 21 04:00:38 PM PDT 24
Finished Apr 21 04:00:46 PM PDT 24
Peak memory 204064 kb
Host smart-166ece6b-d192-45cc-8c74-14feb3889c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16193
50776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1619350776
Directory /workspace/17.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.3095047567
Short name T757
Test name
Test status
Simulation time 8377151173 ps
CPU time 8.45 seconds
Started Apr 21 04:00:33 PM PDT 24
Finished Apr 21 04:00:42 PM PDT 24
Peak memory 204076 kb
Host smart-40008694-e309-45e6-9211-0af4b791bed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30950
47567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.3095047567
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.1112105364
Short name T1060
Test name
Test status
Simulation time 48794958 ps
CPU time 0.68 seconds
Started Apr 21 04:00:36 PM PDT 24
Finished Apr 21 04:00:37 PM PDT 24
Peak memory 203888 kb
Host smart-bd510c3f-4b6e-4f03-a0b6-3fb8f6611cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11121
05364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.1112105364
Directory /workspace/17.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/17.usbdev_pkt_received.1494707757
Short name T424
Test name
Test status
Simulation time 8392042891 ps
CPU time 8.64 seconds
Started Apr 21 04:00:33 PM PDT 24
Finished Apr 21 04:00:42 PM PDT 24
Peak memory 204052 kb
Host smart-c22fd72a-50ab-4bf4-8ba0-4ee66920a7e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14947
07757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1494707757
Directory /workspace/17.usbdev_pkt_received/latest


Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.676625428
Short name T456
Test name
Test status
Simulation time 8407079725 ps
CPU time 7.71 seconds
Started Apr 21 04:00:32 PM PDT 24
Finished Apr 21 04:00:40 PM PDT 24
Peak memory 204044 kb
Host smart-492ab100-3c3b-4475-892c-694e68b3e2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67662
5428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.676625428
Directory /workspace/17.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/17.usbdev_setup_stage.1712974393
Short name T483
Test name
Test status
Simulation time 8381248457 ps
CPU time 7.69 seconds
Started Apr 21 04:00:40 PM PDT 24
Finished Apr 21 04:00:48 PM PDT 24
Peak memory 203992 kb
Host smart-af9b62a1-5b79-46cd-9aba-ff1364d84ad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17129
74393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.1712974393
Directory /workspace/17.usbdev_setup_stage/latest


Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.1727399488
Short name T365
Test name
Test status
Simulation time 8375177956 ps
CPU time 7.96 seconds
Started Apr 21 04:00:40 PM PDT 24
Finished Apr 21 04:00:49 PM PDT 24
Peak memory 204040 kb
Host smart-f79258bb-d1dd-41d7-96e3-43345ebbc77b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17273
99488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.1727399488
Directory /workspace/17.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/17.usbdev_smoke.4129636036
Short name T1296
Test name
Test status
Simulation time 8423688513 ps
CPU time 8.02 seconds
Started Apr 21 04:00:29 PM PDT 24
Finished Apr 21 04:00:38 PM PDT 24
Peak memory 204020 kb
Host smart-a1d9c219-56fd-4e7a-9142-fb9a12aa7df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41296
36036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.4129636036
Directory /workspace/17.usbdev_smoke/latest


Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.3111009752
Short name T1089
Test name
Test status
Simulation time 8424635165 ps
CPU time 9.86 seconds
Started Apr 21 04:00:36 PM PDT 24
Finished Apr 21 04:00:47 PM PDT 24
Peak memory 204052 kb
Host smart-68c778ce-2449-47ee-873f-c9ff585878c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31110
09752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.3111009752
Directory /workspace/17.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/17.usbdev_stall_trans.1681247462
Short name T1206
Test name
Test status
Simulation time 8381326028 ps
CPU time 8.71 seconds
Started Apr 21 04:00:36 PM PDT 24
Finished Apr 21 04:00:45 PM PDT 24
Peak memory 203948 kb
Host smart-345e699e-079d-47b1-a700-f69d2c423a19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16812
47462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.1681247462
Directory /workspace/17.usbdev_stall_trans/latest


Test location /workspace/coverage/default/18.max_length_in_transaction.4205109283
Short name T473
Test name
Test status
Simulation time 8512261771 ps
CPU time 7.58 seconds
Started Apr 21 04:00:52 PM PDT 24
Finished Apr 21 04:01:00 PM PDT 24
Peak memory 204068 kb
Host smart-c7969f98-c90b-49e3-827e-57a53940a45f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4205109283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.4205109283
Directory /workspace/18.max_length_in_transaction/latest


Test location /workspace/coverage/default/18.min_length_in_transaction.1352081825
Short name T376
Test name
Test status
Simulation time 8384846544 ps
CPU time 8.04 seconds
Started Apr 21 04:00:49 PM PDT 24
Finished Apr 21 04:00:58 PM PDT 24
Peak memory 204064 kb
Host smart-288100c7-477d-484a-9993-34f12cda0e83
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1352081825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.1352081825
Directory /workspace/18.min_length_in_transaction/latest


Test location /workspace/coverage/default/18.random_length_in_trans.3342130698
Short name T1362
Test name
Test status
Simulation time 8408969596 ps
CPU time 8.74 seconds
Started Apr 21 04:00:49 PM PDT 24
Finished Apr 21 04:00:58 PM PDT 24
Peak memory 204036 kb
Host smart-fcc3ab38-209b-492e-b286-e200c42bd80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33421
30698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.3342130698
Directory /workspace/18.random_length_in_trans/latest


Test location /workspace/coverage/default/18.usbdev_av_buffer.3118111786
Short name T1271
Test name
Test status
Simulation time 8413920061 ps
CPU time 7.91 seconds
Started Apr 21 04:00:39 PM PDT 24
Finished Apr 21 04:00:47 PM PDT 24
Peak memory 204028 kb
Host smart-fe8c191b-0f4f-410c-bc0b-564000531f74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31181
11786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.3118111786
Directory /workspace/18.usbdev_av_buffer/latest


Test location /workspace/coverage/default/18.usbdev_enable.3344919170
Short name T514
Test name
Test status
Simulation time 8384328511 ps
CPU time 9.31 seconds
Started Apr 21 04:00:41 PM PDT 24
Finished Apr 21 04:00:51 PM PDT 24
Peak memory 204060 kb
Host smart-817feda0-d077-47a8-9b60-8de8115cd252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33449
19170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.3344919170
Directory /workspace/18.usbdev_enable/latest


Test location /workspace/coverage/default/18.usbdev_fifo_rst.2341026274
Short name T608
Test name
Test status
Simulation time 262674113 ps
CPU time 2.2 seconds
Started Apr 21 04:00:41 PM PDT 24
Finished Apr 21 04:00:43 PM PDT 24
Peak memory 204196 kb
Host smart-1b42303c-aa8a-4ebb-9d1a-281dadbea0e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23410
26274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2341026274
Directory /workspace/18.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/18.usbdev_in_iso.1729272803
Short name T477
Test name
Test status
Simulation time 8412893572 ps
CPU time 7.84 seconds
Started Apr 21 04:00:49 PM PDT 24
Finished Apr 21 04:00:57 PM PDT 24
Peak memory 204056 kb
Host smart-f3ebaa59-e021-4f63-8286-926a3affde20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17292
72803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.1729272803
Directory /workspace/18.usbdev_in_iso/latest


Test location /workspace/coverage/default/18.usbdev_in_stall.1082108433
Short name T1252
Test name
Test status
Simulation time 8378454286 ps
CPU time 8.01 seconds
Started Apr 21 04:00:52 PM PDT 24
Finished Apr 21 04:01:01 PM PDT 24
Peak memory 204024 kb
Host smart-e055a333-83c9-434f-a573-758351a68cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10821
08433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.1082108433
Directory /workspace/18.usbdev_in_stall/latest


Test location /workspace/coverage/default/18.usbdev_in_trans.1826651942
Short name T142
Test name
Test status
Simulation time 8510713298 ps
CPU time 10.37 seconds
Started Apr 21 04:00:40 PM PDT 24
Finished Apr 21 04:00:51 PM PDT 24
Peak memory 204064 kb
Host smart-16e5883f-745d-4601-a22e-31acde8a8aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18266
51942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.1826651942
Directory /workspace/18.usbdev_in_trans/latest


Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.3500335419
Short name T300
Test name
Test status
Simulation time 8458468813 ps
CPU time 8.1 seconds
Started Apr 21 04:00:41 PM PDT 24
Finished Apr 21 04:00:49 PM PDT 24
Peak memory 204044 kb
Host smart-0b07e5c2-c1e7-4913-a980-b18c153209c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35003
35419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.3500335419
Directory /workspace/18.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.1645064587
Short name T902
Test name
Test status
Simulation time 8384970587 ps
CPU time 7.98 seconds
Started Apr 21 04:00:43 PM PDT 24
Finished Apr 21 04:00:51 PM PDT 24
Peak memory 204072 kb
Host smart-b0b1ddbb-8b7a-4744-b072-a1f33d3020e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16450
64587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.1645064587
Directory /workspace/18.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/18.usbdev_nak_trans.2498918732
Short name T108
Test name
Test status
Simulation time 8428907407 ps
CPU time 8.04 seconds
Started Apr 21 04:00:43 PM PDT 24
Finished Apr 21 04:00:51 PM PDT 24
Peak memory 204084 kb
Host smart-c2bc93b5-df5d-431e-8f6e-e0b218431198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24989
18732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2498918732
Directory /workspace/18.usbdev_nak_trans/latest


Test location /workspace/coverage/default/18.usbdev_out_stall.2442861284
Short name T488
Test name
Test status
Simulation time 8402994740 ps
CPU time 8.23 seconds
Started Apr 21 04:00:41 PM PDT 24
Finished Apr 21 04:00:50 PM PDT 24
Peak memory 204024 kb
Host smart-1a6f5451-2fad-4571-889e-db5f80ebc440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24428
61284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.2442861284
Directory /workspace/18.usbdev_out_stall/latest


Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1587308269
Short name T887
Test name
Test status
Simulation time 8401807446 ps
CPU time 8.39 seconds
Started Apr 21 04:00:43 PM PDT 24
Finished Apr 21 04:00:51 PM PDT 24
Peak memory 204224 kb
Host smart-45dbb759-4465-479b-8ff4-c39fed8a249e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15873
08269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1587308269
Directory /workspace/18.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.4021957331
Short name T624
Test name
Test status
Simulation time 8367769156 ps
CPU time 8.05 seconds
Started Apr 21 04:00:50 PM PDT 24
Finished Apr 21 04:00:59 PM PDT 24
Peak memory 204060 kb
Host smart-93662738-bb52-4030-8585-9a35a3e67467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40219
57331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.4021957331
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3056600980
Short name T648
Test name
Test status
Simulation time 38492876 ps
CPU time 0.73 seconds
Started Apr 21 04:00:49 PM PDT 24
Finished Apr 21 04:00:50 PM PDT 24
Peak memory 203912 kb
Host smart-25c4311d-274d-47b3-9740-2c0ecbd75b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30566
00980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3056600980
Directory /workspace/18.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/18.usbdev_pkt_received.3992185964
Short name T321
Test name
Test status
Simulation time 8391614874 ps
CPU time 7.85 seconds
Started Apr 21 04:00:43 PM PDT 24
Finished Apr 21 04:00:51 PM PDT 24
Peak memory 204084 kb
Host smart-8a2ecc37-a88b-487e-a6ee-9c54e72924b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39921
85964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.3992185964
Directory /workspace/18.usbdev_pkt_received/latest


Test location /workspace/coverage/default/18.usbdev_pkt_sent.2215952134
Short name T138
Test name
Test status
Simulation time 8475170952 ps
CPU time 9.01 seconds
Started Apr 21 04:00:45 PM PDT 24
Finished Apr 21 04:00:55 PM PDT 24
Peak memory 204004 kb
Host smart-7d39da26-a4e8-4cb4-b173-d7c2b0b6f674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22159
52134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.2215952134
Directory /workspace/18.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.2582676365
Short name T778
Test name
Test status
Simulation time 8391390061 ps
CPU time 7.79 seconds
Started Apr 21 04:00:44 PM PDT 24
Finished Apr 21 04:00:52 PM PDT 24
Peak memory 204044 kb
Host smart-b5f57a4d-b23c-44d7-96cd-1f1c5a3fd59a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25826
76365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.2582676365
Directory /workspace/18.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/18.usbdev_setup_stage.1714561885
Short name T91
Test name
Test status
Simulation time 8425481611 ps
CPU time 8.36 seconds
Started Apr 21 04:00:47 PM PDT 24
Finished Apr 21 04:00:56 PM PDT 24
Peak memory 204040 kb
Host smart-94b577de-ee55-433b-855a-577711a93dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17145
61885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.1714561885
Directory /workspace/18.usbdev_setup_stage/latest


Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.339882978
Short name T313
Test name
Test status
Simulation time 8368164673 ps
CPU time 9.25 seconds
Started Apr 21 04:00:52 PM PDT 24
Finished Apr 21 04:01:02 PM PDT 24
Peak memory 204020 kb
Host smart-30074d0c-06eb-4c09-9139-7d650f5825d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33988
2978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.339882978
Directory /workspace/18.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/18.usbdev_smoke.3909936495
Short name T1288
Test name
Test status
Simulation time 8440371576 ps
CPU time 9.4 seconds
Started Apr 21 04:00:40 PM PDT 24
Finished Apr 21 04:00:49 PM PDT 24
Peak memory 204048 kb
Host smart-17a6a325-5c57-40b8-b41e-8b0c86831762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39099
36495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.3909936495
Directory /workspace/18.usbdev_smoke/latest


Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.2451281730
Short name T848
Test name
Test status
Simulation time 8384603951 ps
CPU time 8.48 seconds
Started Apr 21 04:00:47 PM PDT 24
Finished Apr 21 04:00:56 PM PDT 24
Peak memory 204060 kb
Host smart-57999f58-d277-4039-a245-43c1484f9712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24512
81730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.2451281730
Directory /workspace/18.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/18.usbdev_stall_trans.1018609231
Short name T1350
Test name
Test status
Simulation time 8414562268 ps
CPU time 10.03 seconds
Started Apr 21 04:00:44 PM PDT 24
Finished Apr 21 04:00:54 PM PDT 24
Peak memory 204076 kb
Host smart-0cc3cac2-7c04-4328-b8a5-13237dbf3cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10186
09231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.1018609231
Directory /workspace/18.usbdev_stall_trans/latest


Test location /workspace/coverage/default/19.max_length_in_transaction.2223404268
Short name T1016
Test name
Test status
Simulation time 8464573982 ps
CPU time 7.48 seconds
Started Apr 21 04:00:58 PM PDT 24
Finished Apr 21 04:01:06 PM PDT 24
Peak memory 204040 kb
Host smart-42b9cbee-03c0-4302-9ba8-597d4cfd13c1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2223404268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.2223404268
Directory /workspace/19.max_length_in_transaction/latest


Test location /workspace/coverage/default/19.min_length_in_transaction.2566520595
Short name T873
Test name
Test status
Simulation time 8378560068 ps
CPU time 8.13 seconds
Started Apr 21 04:00:59 PM PDT 24
Finished Apr 21 04:01:07 PM PDT 24
Peak memory 204068 kb
Host smart-8b0ceadb-7c6e-4169-a145-2962d91df3b4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2566520595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.2566520595
Directory /workspace/19.min_length_in_transaction/latest


Test location /workspace/coverage/default/19.random_length_in_trans.3502974550
Short name T1134
Test name
Test status
Simulation time 8462728458 ps
CPU time 8 seconds
Started Apr 21 04:01:00 PM PDT 24
Finished Apr 21 04:01:08 PM PDT 24
Peak memory 204060 kb
Host smart-d0d9671a-770d-4a32-a523-7a911bf7790b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35029
74550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.3502974550
Directory /workspace/19.random_length_in_trans/latest


Test location /workspace/coverage/default/19.usbdev_av_buffer.444633402
Short name T357
Test name
Test status
Simulation time 8374769577 ps
CPU time 7.98 seconds
Started Apr 21 04:00:51 PM PDT 24
Finished Apr 21 04:00:59 PM PDT 24
Peak memory 204064 kb
Host smart-741bc70a-06a2-48c9-8527-c502ba914feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44463
3402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.444633402
Directory /workspace/19.usbdev_av_buffer/latest


Test location /workspace/coverage/default/19.usbdev_enable.3736994095
Short name T458
Test name
Test status
Simulation time 8382971690 ps
CPU time 7.59 seconds
Started Apr 21 04:00:55 PM PDT 24
Finished Apr 21 04:01:02 PM PDT 24
Peak memory 204056 kb
Host smart-27da33d4-2bd7-4170-b9e2-860cdb7c5591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37369
94095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.3736994095
Directory /workspace/19.usbdev_enable/latest


Test location /workspace/coverage/default/19.usbdev_fifo_rst.2326871445
Short name T358
Test name
Test status
Simulation time 210261145 ps
CPU time 2.37 seconds
Started Apr 21 04:00:53 PM PDT 24
Finished Apr 21 04:00:56 PM PDT 24
Peak memory 204192 kb
Host smart-a7e72cd7-e22f-4b8e-976f-21f5454fe212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23268
71445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2326871445
Directory /workspace/19.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/19.usbdev_in_iso.1761907645
Short name T1034
Test name
Test status
Simulation time 8430559877 ps
CPU time 7.72 seconds
Started Apr 21 04:01:00 PM PDT 24
Finished Apr 21 04:01:08 PM PDT 24
Peak memory 204028 kb
Host smart-674b103d-d1c7-4da9-a44d-258f3fd39c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17619
07645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.1761907645
Directory /workspace/19.usbdev_in_iso/latest


Test location /workspace/coverage/default/19.usbdev_in_stall.570581616
Short name T1158
Test name
Test status
Simulation time 8371824175 ps
CPU time 7.97 seconds
Started Apr 21 04:01:00 PM PDT 24
Finished Apr 21 04:01:08 PM PDT 24
Peak memory 204068 kb
Host smart-ddc59703-b47c-482f-b251-708b1d4adbf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57058
1616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.570581616
Directory /workspace/19.usbdev_in_stall/latest


Test location /workspace/coverage/default/19.usbdev_in_trans.1218851681
Short name T1220
Test name
Test status
Simulation time 8448579251 ps
CPU time 7.65 seconds
Started Apr 21 04:00:55 PM PDT 24
Finished Apr 21 04:01:03 PM PDT 24
Peak memory 204056 kb
Host smart-604f1cb8-5fe7-4249-89ad-bd58c49948bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12188
51681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.1218851681
Directory /workspace/19.usbdev_in_trans/latest


Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.746444999
Short name T741
Test name
Test status
Simulation time 8421250354 ps
CPU time 8.02 seconds
Started Apr 21 04:00:53 PM PDT 24
Finished Apr 21 04:01:01 PM PDT 24
Peak memory 204060 kb
Host smart-d49410c6-f829-4b93-ac79-674a97a92d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74644
4999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.746444999
Directory /workspace/19.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3541704424
Short name T378
Test name
Test status
Simulation time 8368385545 ps
CPU time 8.9 seconds
Started Apr 21 04:00:54 PM PDT 24
Finished Apr 21 04:01:03 PM PDT 24
Peak memory 204084 kb
Host smart-c1eaeb29-d794-40b9-8832-3bcb7e3efca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35417
04424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3541704424
Directory /workspace/19.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/19.usbdev_out_stall.2985988891
Short name T1214
Test name
Test status
Simulation time 8391594857 ps
CPU time 9.62 seconds
Started Apr 21 04:00:54 PM PDT 24
Finished Apr 21 04:01:04 PM PDT 24
Peak memory 204064 kb
Host smart-625173e0-c1a1-4d56-a510-af64a86439c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29859
88891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2985988891
Directory /workspace/19.usbdev_out_stall/latest


Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2302629735
Short name T462
Test name
Test status
Simulation time 8383298227 ps
CPU time 7.93 seconds
Started Apr 21 04:00:56 PM PDT 24
Finished Apr 21 04:01:04 PM PDT 24
Peak memory 204064 kb
Host smart-0cbc8875-eeea-4050-96cd-7f63cfc441d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23026
29735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2302629735
Directory /workspace/19.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/19.usbdev_pending_in_trans.2955152922
Short name T538
Test name
Test status
Simulation time 8408123209 ps
CPU time 7.52 seconds
Started Apr 21 04:01:00 PM PDT 24
Finished Apr 21 04:01:08 PM PDT 24
Peak memory 204064 kb
Host smart-7f2f462b-d249-4c7c-bf9a-678394220276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29551
52922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.2955152922
Directory /workspace/19.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.50678421
Short name T311
Test name
Test status
Simulation time 8367362123 ps
CPU time 8.54 seconds
Started Apr 21 04:00:58 PM PDT 24
Finished Apr 21 04:01:07 PM PDT 24
Peak memory 204068 kb
Host smart-bcfbe094-036d-4f81-9146-9e4e0ec6a53f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50678
421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.50678421
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.543116809
Short name T1056
Test name
Test status
Simulation time 37856654 ps
CPU time 0.69 seconds
Started Apr 21 04:01:00 PM PDT 24
Finished Apr 21 04:01:01 PM PDT 24
Peak memory 203812 kb
Host smart-384c62cf-b454-4847-b373-f51eba8f3828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54311
6809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.543116809
Directory /workspace/19.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/19.usbdev_pkt_buffer.2100142519
Short name T601
Test name
Test status
Simulation time 18152704193 ps
CPU time 32.53 seconds
Started Apr 21 04:00:58 PM PDT 24
Finished Apr 21 04:01:30 PM PDT 24
Peak memory 204360 kb
Host smart-6fca7145-7d63-4b2e-92db-808240d373bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21001
42519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.2100142519
Directory /workspace/19.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/19.usbdev_pkt_received.3901188943
Short name T1239
Test name
Test status
Simulation time 8388104317 ps
CPU time 10.21 seconds
Started Apr 21 04:00:56 PM PDT 24
Finished Apr 21 04:01:06 PM PDT 24
Peak memory 204032 kb
Host smart-f3d6a72b-7bfa-423d-9d2f-fb7513406a16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39011
88943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.3901188943
Directory /workspace/19.usbdev_pkt_received/latest


Test location /workspace/coverage/default/19.usbdev_pkt_sent.3136898624
Short name T683
Test name
Test status
Simulation time 8400378589 ps
CPU time 8.19 seconds
Started Apr 21 04:01:00 PM PDT 24
Finished Apr 21 04:01:08 PM PDT 24
Peak memory 204028 kb
Host smart-86c3fdf4-b08f-4711-8a7b-167026cce5b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31368
98624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.3136898624
Directory /workspace/19.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.375509057
Short name T623
Test name
Test status
Simulation time 8421030468 ps
CPU time 9.29 seconds
Started Apr 21 04:00:58 PM PDT 24
Finished Apr 21 04:01:07 PM PDT 24
Peak memory 204056 kb
Host smart-fced4ece-10d5-467f-bcad-7ab5fb27c793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37550
9057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.375509057
Directory /workspace/19.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/19.usbdev_setup_stage.4101901895
Short name T353
Test name
Test status
Simulation time 8370692622 ps
CPU time 7.81 seconds
Started Apr 21 04:01:00 PM PDT 24
Finished Apr 21 04:01:08 PM PDT 24
Peak memory 204028 kb
Host smart-4e5967ac-1d4a-4be7-acb8-da06b651a807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41019
01895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.4101901895
Directory /workspace/19.usbdev_setup_stage/latest


Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.1705907604
Short name T1281
Test name
Test status
Simulation time 8437519068 ps
CPU time 7.7 seconds
Started Apr 21 04:00:58 PM PDT 24
Finished Apr 21 04:01:06 PM PDT 24
Peak memory 204056 kb
Host smart-00ab2741-480b-4999-83bf-48325d5d59aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17059
07604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.1705907604
Directory /workspace/19.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/19.usbdev_smoke.3646750585
Short name T137
Test name
Test status
Simulation time 8432666826 ps
CPU time 8.86 seconds
Started Apr 21 04:00:51 PM PDT 24
Finished Apr 21 04:01:00 PM PDT 24
Peak memory 204048 kb
Host smart-44b345d0-14c5-4297-b069-7184d41a5db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36467
50585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.3646750585
Directory /workspace/19.usbdev_smoke/latest


Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.2383137133
Short name T466
Test name
Test status
Simulation time 8390699405 ps
CPU time 8.6 seconds
Started Apr 21 04:00:58 PM PDT 24
Finished Apr 21 04:01:07 PM PDT 24
Peak memory 204056 kb
Host smart-c14bcd00-889b-4131-a025-fa42a292f617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23831
37133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.2383137133
Directory /workspace/19.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/19.usbdev_stall_trans.1261505120
Short name T310
Test name
Test status
Simulation time 8426436921 ps
CPU time 8 seconds
Started Apr 21 04:00:56 PM PDT 24
Finished Apr 21 04:01:05 PM PDT 24
Peak memory 204060 kb
Host smart-4e544f4f-5f12-4d65-8bb3-5db4a688e9d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12615
05120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.1261505120
Directory /workspace/19.usbdev_stall_trans/latest


Test location /workspace/coverage/default/2.max_length_in_transaction.4046064762
Short name T1358
Test name
Test status
Simulation time 8472266747 ps
CPU time 8.23 seconds
Started Apr 21 03:57:29 PM PDT 24
Finished Apr 21 03:57:37 PM PDT 24
Peak memory 204076 kb
Host smart-3e6f335a-1bd9-4716-918c-3a8d27c4cd25
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4046064762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.4046064762
Directory /workspace/2.max_length_in_transaction/latest


Test location /workspace/coverage/default/2.min_length_in_transaction.1227364083
Short name T360
Test name
Test status
Simulation time 8421066284 ps
CPU time 7.67 seconds
Started Apr 21 03:57:25 PM PDT 24
Finished Apr 21 03:57:33 PM PDT 24
Peak memory 204068 kb
Host smart-9109903a-8bb8-401a-8dd0-9632a101b0ef
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1227364083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.1227364083
Directory /workspace/2.min_length_in_transaction/latest


Test location /workspace/coverage/default/2.random_length_in_trans.3361300069
Short name T879
Test name
Test status
Simulation time 8377644169 ps
CPU time 9.76 seconds
Started Apr 21 03:57:23 PM PDT 24
Finished Apr 21 03:57:33 PM PDT 24
Peak memory 203992 kb
Host smart-ebb90a9a-037e-41df-bcf0-39f4ac4d8f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33613
00069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.3361300069
Directory /workspace/2.random_length_in_trans/latest


Test location /workspace/coverage/default/2.usbdev_av_buffer.1082985456
Short name T1290
Test name
Test status
Simulation time 8421006582 ps
CPU time 7.72 seconds
Started Apr 21 03:57:11 PM PDT 24
Finished Apr 21 03:57:19 PM PDT 24
Peak memory 204084 kb
Host smart-32cb5c8a-3701-4788-9e91-b5e6275c2a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10829
85456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.1082985456
Directory /workspace/2.usbdev_av_buffer/latest


Test location /workspace/coverage/default/2.usbdev_enable.430898561
Short name T1190
Test name
Test status
Simulation time 8387056900 ps
CPU time 8.63 seconds
Started Apr 21 03:57:09 PM PDT 24
Finished Apr 21 03:57:18 PM PDT 24
Peak memory 203956 kb
Host smart-80e43826-d027-435a-b748-7ef58058f4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43089
8561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.430898561
Directory /workspace/2.usbdev_enable/latest


Test location /workspace/coverage/default/2.usbdev_fifo_rst.125981739
Short name T856
Test name
Test status
Simulation time 63808173 ps
CPU time 1.46 seconds
Started Apr 21 03:57:11 PM PDT 24
Finished Apr 21 03:57:13 PM PDT 24
Peak memory 204172 kb
Host smart-9be2e1e4-64be-4873-bbf5-094564646d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12598
1739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.125981739
Directory /workspace/2.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/2.usbdev_in_iso.2563862368
Short name T912
Test name
Test status
Simulation time 8452062872 ps
CPU time 8.65 seconds
Started Apr 21 03:57:17 PM PDT 24
Finished Apr 21 03:57:26 PM PDT 24
Peak memory 204068 kb
Host smart-74a5203c-7e6f-4c89-8cdc-a0e345bf0cd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25638
62368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.2563862368
Directory /workspace/2.usbdev_in_iso/latest


Test location /workspace/coverage/default/2.usbdev_in_stall.2697922784
Short name T764
Test name
Test status
Simulation time 8390250912 ps
CPU time 8.22 seconds
Started Apr 21 03:57:19 PM PDT 24
Finished Apr 21 03:57:28 PM PDT 24
Peak memory 204004 kb
Host smart-be2e9271-4b9a-4a1f-a07a-b979e394fcc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26979
22784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2697922784
Directory /workspace/2.usbdev_in_stall/latest


Test location /workspace/coverage/default/2.usbdev_in_trans.1456213083
Short name T958
Test name
Test status
Simulation time 8454907112 ps
CPU time 7.72 seconds
Started Apr 21 03:57:12 PM PDT 24
Finished Apr 21 03:57:20 PM PDT 24
Peak memory 204068 kb
Host smart-3e8d9fa2-bd7a-4bd1-9f18-2b20a057cb60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14562
13083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.1456213083
Directory /workspace/2.usbdev_in_trans/latest


Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.3681972597
Short name T293
Test name
Test status
Simulation time 8422430605 ps
CPU time 8.02 seconds
Started Apr 21 03:57:13 PM PDT 24
Finished Apr 21 03:57:21 PM PDT 24
Peak memory 204084 kb
Host smart-f2752588-bd65-40f0-a7e6-78b8ba2cdecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36819
72597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.3681972597
Directory /workspace/2.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.4167085767
Short name T553
Test name
Test status
Simulation time 8369900236 ps
CPU time 8.47 seconds
Started Apr 21 03:57:13 PM PDT 24
Finished Apr 21 03:57:22 PM PDT 24
Peak memory 203996 kb
Host smart-18df15e9-ef0b-4914-9af0-4ec28335c796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41670
85767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.4167085767
Directory /workspace/2.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/2.usbdev_out_stall.234839931
Short name T713
Test name
Test status
Simulation time 8405581118 ps
CPU time 7.85 seconds
Started Apr 21 03:57:13 PM PDT 24
Finished Apr 21 03:57:21 PM PDT 24
Peak memory 204060 kb
Host smart-0164f266-b820-4221-94b1-a00f29584752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23483
9931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.234839931
Directory /workspace/2.usbdev_out_stall/latest


Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2028880597
Short name T1225
Test name
Test status
Simulation time 8399372228 ps
CPU time 7.88 seconds
Started Apr 21 03:57:13 PM PDT 24
Finished Apr 21 03:57:21 PM PDT 24
Peak memory 204064 kb
Host smart-7dda2fdc-6b86-4c76-88f8-4b95f4130eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20288
80597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2028880597
Directory /workspace/2.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.1755080655
Short name T391
Test name
Test status
Simulation time 8424459620 ps
CPU time 7.7 seconds
Started Apr 21 03:57:16 PM PDT 24
Finished Apr 21 03:57:24 PM PDT 24
Peak memory 204064 kb
Host smart-78c4efd0-f494-4d11-bb3c-e76cbe5c6c21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17550
80655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.1755080655
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.900044351
Short name T443
Test name
Test status
Simulation time 48988507 ps
CPU time 0.65 seconds
Started Apr 21 03:57:18 PM PDT 24
Finished Apr 21 03:57:19 PM PDT 24
Peak memory 203956 kb
Host smart-c694afd4-0691-4ffd-afab-5a7bbf4cb4bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90004
4351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.900044351
Directory /workspace/2.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/2.usbdev_pkt_buffer.4211609006
Short name T226
Test name
Test status
Simulation time 29626419069 ps
CPU time 58.29 seconds
Started Apr 21 03:57:14 PM PDT 24
Finished Apr 21 03:58:12 PM PDT 24
Peak memory 204324 kb
Host smart-a7a4376b-0187-41cc-b9d4-bf60c36f64bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42116
09006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.4211609006
Directory /workspace/2.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/2.usbdev_pkt_received.3072985342
Short name T786
Test name
Test status
Simulation time 8402556115 ps
CPU time 7.76 seconds
Started Apr 21 03:57:19 PM PDT 24
Finished Apr 21 03:57:27 PM PDT 24
Peak memory 204032 kb
Host smart-fda961b3-a967-40c9-9098-6841ed2879cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30729
85342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.3072985342
Directory /workspace/2.usbdev_pkt_received/latest


Test location /workspace/coverage/default/2.usbdev_pkt_sent.884134303
Short name T1213
Test name
Test status
Simulation time 8474963820 ps
CPU time 10.27 seconds
Started Apr 21 03:57:17 PM PDT 24
Finished Apr 21 03:57:27 PM PDT 24
Peak memory 203940 kb
Host smart-90c01fe5-4ce9-4603-86c0-7577b49c06dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88413
4303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.884134303
Directory /workspace/2.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.2309938796
Short name T962
Test name
Test status
Simulation time 8463534697 ps
CPU time 8.97 seconds
Started Apr 21 03:57:19 PM PDT 24
Finished Apr 21 03:57:28 PM PDT 24
Peak memory 204032 kb
Host smart-a6681452-0289-437a-a869-ba0ad8410e46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23099
38796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.2309938796
Directory /workspace/2.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/2.usbdev_sec_cm.2009286140
Short name T74
Test name
Test status
Simulation time 842602546 ps
CPU time 1.65 seconds
Started Apr 21 03:57:27 PM PDT 24
Finished Apr 21 03:57:28 PM PDT 24
Peak memory 221336 kb
Host smart-4bd8ae89-d65a-4576-974c-e10a05d6af1f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2009286140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2009286140
Directory /workspace/2.usbdev_sec_cm/latest


Test location /workspace/coverage/default/2.usbdev_setup_stage.1227948793
Short name T179
Test name
Test status
Simulation time 8372389975 ps
CPU time 10.17 seconds
Started Apr 21 03:57:18 PM PDT 24
Finished Apr 21 03:57:28 PM PDT 24
Peak memory 204008 kb
Host smart-c984a2f1-aac0-46e1-869e-e58ab847a191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12279
48793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.1227948793
Directory /workspace/2.usbdev_setup_stage/latest


Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3446954150
Short name T554
Test name
Test status
Simulation time 8378201691 ps
CPU time 8.27 seconds
Started Apr 21 03:57:16 PM PDT 24
Finished Apr 21 03:57:25 PM PDT 24
Peak memory 204080 kb
Host smart-01605bd4-a5f0-4577-b9ea-6a9a82427a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34469
54150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3446954150
Directory /workspace/2.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/2.usbdev_smoke.1007815648
Short name T147
Test name
Test status
Simulation time 8463432235 ps
CPU time 8.51 seconds
Started Apr 21 03:57:13 PM PDT 24
Finished Apr 21 03:57:22 PM PDT 24
Peak memory 204088 kb
Host smart-293dfa94-4f54-4581-8dd9-ee3e773fd6a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10078
15648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.1007815648
Directory /workspace/2.usbdev_smoke/latest


Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.28337590
Short name T525
Test name
Test status
Simulation time 8392749760 ps
CPU time 8.55 seconds
Started Apr 21 03:57:17 PM PDT 24
Finished Apr 21 03:57:26 PM PDT 24
Peak memory 204012 kb
Host smart-86d62c8a-f55a-493c-bd4a-59eb6eef17f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28337
590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.28337590
Directory /workspace/2.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/2.usbdev_stall_trans.337927499
Short name T1168
Test name
Test status
Simulation time 8400329059 ps
CPU time 8.18 seconds
Started Apr 21 03:57:17 PM PDT 24
Finished Apr 21 03:57:25 PM PDT 24
Peak memory 204072 kb
Host smart-b293c62d-d3ff-4208-b577-6c74d8b263dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33792
7499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.337927499
Directory /workspace/2.usbdev_stall_trans/latest


Test location /workspace/coverage/default/20.max_length_in_transaction.483961602
Short name T1377
Test name
Test status
Simulation time 8466967711 ps
CPU time 9.78 seconds
Started Apr 21 04:01:14 PM PDT 24
Finished Apr 21 04:01:24 PM PDT 24
Peak memory 204044 kb
Host smart-5b777cc5-4871-41b6-b0a7-b6b258dfc11e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=483961602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.483961602
Directory /workspace/20.max_length_in_transaction/latest


Test location /workspace/coverage/default/20.min_length_in_transaction.3737243002
Short name T1185
Test name
Test status
Simulation time 8372869941 ps
CPU time 7.41 seconds
Started Apr 21 04:01:12 PM PDT 24
Finished Apr 21 04:01:20 PM PDT 24
Peak memory 204044 kb
Host smart-9e92ae00-c95c-4a8f-ab16-f87297f6150b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3737243002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.3737243002
Directory /workspace/20.min_length_in_transaction/latest


Test location /workspace/coverage/default/20.random_length_in_trans.2311271973
Short name T1240
Test name
Test status
Simulation time 8381960286 ps
CPU time 7.85 seconds
Started Apr 21 04:01:12 PM PDT 24
Finished Apr 21 04:01:20 PM PDT 24
Peak memory 204036 kb
Host smart-0646c219-7c48-4280-9c81-bf8ec8abbf5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23112
71973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.2311271973
Directory /workspace/20.random_length_in_trans/latest


Test location /workspace/coverage/default/20.usbdev_av_buffer.3072617547
Short name T1165
Test name
Test status
Simulation time 8381274903 ps
CPU time 9.28 seconds
Started Apr 21 04:01:03 PM PDT 24
Finished Apr 21 04:01:13 PM PDT 24
Peak memory 204068 kb
Host smart-0ab9e5ee-3326-4bea-8856-62c4922c1ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30726
17547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3072617547
Directory /workspace/20.usbdev_av_buffer/latest


Test location /workspace/coverage/default/20.usbdev_enable.3692836026
Short name T484
Test name
Test status
Simulation time 8376212046 ps
CPU time 7.5 seconds
Started Apr 21 04:01:02 PM PDT 24
Finished Apr 21 04:01:10 PM PDT 24
Peak memory 203964 kb
Host smart-cd36f8fc-1d3b-4c48-ab02-1c6c3dc7f745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36928
36026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.3692836026
Directory /workspace/20.usbdev_enable/latest


Test location /workspace/coverage/default/20.usbdev_fifo_rst.67645636
Short name T582
Test name
Test status
Simulation time 200998349 ps
CPU time 2.29 seconds
Started Apr 21 04:01:03 PM PDT 24
Finished Apr 21 04:01:06 PM PDT 24
Peak memory 204120 kb
Host smart-2651ea6d-1ca3-482a-925f-e117f8a9a60e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67645
636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.67645636
Directory /workspace/20.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/20.usbdev_in_iso.4154287872
Short name T51
Test name
Test status
Simulation time 8505808781 ps
CPU time 8.22 seconds
Started Apr 21 04:01:10 PM PDT 24
Finished Apr 21 04:01:18 PM PDT 24
Peak memory 204240 kb
Host smart-c7d63711-93ab-4ec0-b299-8378848ba9b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41542
87872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.4154287872
Directory /workspace/20.usbdev_in_iso/latest


Test location /workspace/coverage/default/20.usbdev_in_stall.478332193
Short name T1106
Test name
Test status
Simulation time 8367836224 ps
CPU time 7.78 seconds
Started Apr 21 04:01:10 PM PDT 24
Finished Apr 21 04:01:18 PM PDT 24
Peak memory 204064 kb
Host smart-b53ae76e-bd69-482e-8fec-9292bdb047c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47833
2193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.478332193
Directory /workspace/20.usbdev_in_stall/latest


Test location /workspace/coverage/default/20.usbdev_in_trans.4222769344
Short name T1099
Test name
Test status
Simulation time 8417549939 ps
CPU time 7.54 seconds
Started Apr 21 04:01:00 PM PDT 24
Finished Apr 21 04:01:08 PM PDT 24
Peak memory 204076 kb
Host smart-fd154be7-b004-4971-8467-e3d4e9834cef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42227
69344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.4222769344
Directory /workspace/20.usbdev_in_trans/latest


Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1527490026
Short name T996
Test name
Test status
Simulation time 8417792546 ps
CPU time 10.61 seconds
Started Apr 21 04:01:06 PM PDT 24
Finished Apr 21 04:01:17 PM PDT 24
Peak memory 204044 kb
Host smart-38f10095-d8da-4d7d-bff1-f7f91e326954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15274
90026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1527490026
Directory /workspace/20.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.911446272
Short name T405
Test name
Test status
Simulation time 8372889676 ps
CPU time 7.93 seconds
Started Apr 21 04:01:06 PM PDT 24
Finished Apr 21 04:01:14 PM PDT 24
Peak memory 204032 kb
Host smart-09a5a3a5-1c0f-46f4-8ee0-bda236177ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91144
6272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.911446272
Directory /workspace/20.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/20.usbdev_nak_trans.411458832
Short name T763
Test name
Test status
Simulation time 8432567799 ps
CPU time 7.82 seconds
Started Apr 21 04:01:07 PM PDT 24
Finished Apr 21 04:01:15 PM PDT 24
Peak memory 204060 kb
Host smart-38935126-d5ef-46f7-a35a-0968f948ad77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41145
8832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.411458832
Directory /workspace/20.usbdev_nak_trans/latest


Test location /workspace/coverage/default/20.usbdev_out_stall.1923233104
Short name T875
Test name
Test status
Simulation time 8417344489 ps
CPU time 7.74 seconds
Started Apr 21 04:01:07 PM PDT 24
Finished Apr 21 04:01:15 PM PDT 24
Peak memory 204088 kb
Host smart-73e67487-f90c-41d0-b68d-8be3d6ed002b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19232
33104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.1923233104
Directory /workspace/20.usbdev_out_stall/latest


Test location /workspace/coverage/default/20.usbdev_out_trans_nak.3145376144
Short name T684
Test name
Test status
Simulation time 8417601063 ps
CPU time 8.48 seconds
Started Apr 21 04:01:07 PM PDT 24
Finished Apr 21 04:01:16 PM PDT 24
Peak memory 204044 kb
Host smart-573ee820-e3fc-4790-a2dc-ebe8230287a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31453
76144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3145376144
Directory /workspace/20.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/20.usbdev_pending_in_trans.4049140817
Short name T1119
Test name
Test status
Simulation time 8381790918 ps
CPU time 7.65 seconds
Started Apr 21 04:01:09 PM PDT 24
Finished Apr 21 04:01:17 PM PDT 24
Peak memory 204024 kb
Host smart-64bd19cc-0d95-42bc-991d-dfc07224ce70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40491
40817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.4049140817
Directory /workspace/20.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.2954207512
Short name T643
Test name
Test status
Simulation time 8368280847 ps
CPU time 8.41 seconds
Started Apr 21 04:01:08 PM PDT 24
Finished Apr 21 04:01:17 PM PDT 24
Peak memory 204060 kb
Host smart-dda2bef3-96bd-4d34-86ca-d0d90c7a67a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29542
07512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.2954207512
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.3116770798
Short name T799
Test name
Test status
Simulation time 51149802 ps
CPU time 0.71 seconds
Started Apr 21 04:01:10 PM PDT 24
Finished Apr 21 04:01:11 PM PDT 24
Peak memory 203912 kb
Host smart-39c38ecf-528f-405b-be7a-07f879e44469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31167
70798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.3116770798
Directory /workspace/20.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3113080145
Short name T528
Test name
Test status
Simulation time 14483240182 ps
CPU time 29.15 seconds
Started Apr 21 04:01:05 PM PDT 24
Finished Apr 21 04:01:34 PM PDT 24
Peak memory 204284 kb
Host smart-bdb4f250-9dba-4344-8f8c-0ff9a0e6381a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31130
80145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3113080145
Directory /workspace/20.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/20.usbdev_pkt_received.4101350435
Short name T1125
Test name
Test status
Simulation time 8412451790 ps
CPU time 10.4 seconds
Started Apr 21 04:01:11 PM PDT 24
Finished Apr 21 04:01:22 PM PDT 24
Peak memory 204040 kb
Host smart-155aaf9e-2ce7-4d12-87e5-8535f76f2af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41013
50435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.4101350435
Directory /workspace/20.usbdev_pkt_received/latest


Test location /workspace/coverage/default/20.usbdev_pkt_sent.2187878675
Short name T859
Test name
Test status
Simulation time 8473980395 ps
CPU time 8.98 seconds
Started Apr 21 04:01:07 PM PDT 24
Finished Apr 21 04:01:16 PM PDT 24
Peak memory 204088 kb
Host smart-3f843599-e0f7-435d-8592-d72af9a103a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21878
78675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.2187878675
Directory /workspace/20.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.3830319807
Short name T542
Test name
Test status
Simulation time 8408908054 ps
CPU time 7.69 seconds
Started Apr 21 04:01:11 PM PDT 24
Finished Apr 21 04:01:19 PM PDT 24
Peak memory 204040 kb
Host smart-d9251158-93d5-402c-b970-9828057ff603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38303
19807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.3830319807
Directory /workspace/20.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/20.usbdev_setup_stage.2518032149
Short name T1330
Test name
Test status
Simulation time 8373178537 ps
CPU time 8.1 seconds
Started Apr 21 04:01:09 PM PDT 24
Finished Apr 21 04:01:17 PM PDT 24
Peak memory 204024 kb
Host smart-68f1eefc-c20a-43dd-bf04-4efeef9f78c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25180
32149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2518032149
Directory /workspace/20.usbdev_setup_stage/latest


Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1910277198
Short name T743
Test name
Test status
Simulation time 8429157869 ps
CPU time 9 seconds
Started Apr 21 04:01:05 PM PDT 24
Finished Apr 21 04:01:14 PM PDT 24
Peak memory 203944 kb
Host smart-42a0065c-7e18-4b26-b61e-d1c428cbf7a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19102
77198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1910277198
Directory /workspace/20.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/20.usbdev_smoke.1777578153
Short name T416
Test name
Test status
Simulation time 8432888875 ps
CPU time 7.88 seconds
Started Apr 21 04:01:06 PM PDT 24
Finished Apr 21 04:01:14 PM PDT 24
Peak memory 204088 kb
Host smart-fafb6d0d-1f30-43ac-ad02-e3902f67ba93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17775
78153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1777578153
Directory /workspace/20.usbdev_smoke/latest


Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.4206456697
Short name T136
Test name
Test status
Simulation time 8377395197 ps
CPU time 8 seconds
Started Apr 21 04:01:09 PM PDT 24
Finished Apr 21 04:01:17 PM PDT 24
Peak memory 204060 kb
Host smart-999ead5d-bae3-4227-a2aa-9046b4d2ea67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42064
56697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.4206456697
Directory /workspace/20.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/20.usbdev_stall_trans.998804571
Short name T798
Test name
Test status
Simulation time 8403793356 ps
CPU time 7.93 seconds
Started Apr 21 04:01:06 PM PDT 24
Finished Apr 21 04:01:14 PM PDT 24
Peak memory 204068 kb
Host smart-11b26dac-5860-4537-9b7b-3e9e11df627c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99880
4571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.998804571
Directory /workspace/20.usbdev_stall_trans/latest


Test location /workspace/coverage/default/21.max_length_in_transaction.3043124631
Short name T1187
Test name
Test status
Simulation time 8474330034 ps
CPU time 8.73 seconds
Started Apr 21 04:01:22 PM PDT 24
Finished Apr 21 04:01:31 PM PDT 24
Peak memory 204056 kb
Host smart-fb1d0d1e-5dbb-4129-9bd2-e06503517b34
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3043124631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.3043124631
Directory /workspace/21.max_length_in_transaction/latest


Test location /workspace/coverage/default/21.min_length_in_transaction.3751902848
Short name T1004
Test name
Test status
Simulation time 8392415480 ps
CPU time 7.5 seconds
Started Apr 21 04:01:21 PM PDT 24
Finished Apr 21 04:01:29 PM PDT 24
Peak memory 204044 kb
Host smart-3f0f4b65-c332-4104-8fb8-2a673e08a5dc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3751902848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.3751902848
Directory /workspace/21.min_length_in_transaction/latest


Test location /workspace/coverage/default/21.random_length_in_trans.1434873923
Short name T499
Test name
Test status
Simulation time 8386644188 ps
CPU time 7.89 seconds
Started Apr 21 04:01:21 PM PDT 24
Finished Apr 21 04:01:29 PM PDT 24
Peak memory 204060 kb
Host smart-f5929771-a894-4052-a456-4924f75c3f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14348
73923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.1434873923
Directory /workspace/21.random_length_in_trans/latest


Test location /workspace/coverage/default/21.usbdev_av_buffer.2794254148
Short name T954
Test name
Test status
Simulation time 8379417654 ps
CPU time 10.05 seconds
Started Apr 21 04:01:14 PM PDT 24
Finished Apr 21 04:01:25 PM PDT 24
Peak memory 204068 kb
Host smart-693a5949-bc1c-4229-81e3-0648111c4cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27942
54148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2794254148
Directory /workspace/21.usbdev_av_buffer/latest


Test location /workspace/coverage/default/21.usbdev_enable.3423048734
Short name T999
Test name
Test status
Simulation time 8394081392 ps
CPU time 10.33 seconds
Started Apr 21 04:01:14 PM PDT 24
Finished Apr 21 04:01:25 PM PDT 24
Peak memory 204044 kb
Host smart-8d2c6893-14c3-49ab-946c-cc0cb93834c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34230
48734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.3423048734
Directory /workspace/21.usbdev_enable/latest


Test location /workspace/coverage/default/21.usbdev_fifo_rst.3211702265
Short name T1132
Test name
Test status
Simulation time 86259669 ps
CPU time 1.84 seconds
Started Apr 21 04:01:14 PM PDT 24
Finished Apr 21 04:01:16 PM PDT 24
Peak memory 204100 kb
Host smart-452f0187-fec5-4479-8724-d8496d19b68e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32117
02265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.3211702265
Directory /workspace/21.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/21.usbdev_in_iso.3766887806
Short name T149
Test name
Test status
Simulation time 8422418531 ps
CPU time 7.91 seconds
Started Apr 21 04:01:21 PM PDT 24
Finished Apr 21 04:01:30 PM PDT 24
Peak memory 204240 kb
Host smart-86f7a894-dfa9-49bb-af0f-0bec11450d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37668
87806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.3766887806
Directory /workspace/21.usbdev_in_iso/latest


Test location /workspace/coverage/default/21.usbdev_in_stall.2791555795
Short name T184
Test name
Test status
Simulation time 8370748024 ps
CPU time 7.75 seconds
Started Apr 21 04:01:18 PM PDT 24
Finished Apr 21 04:01:26 PM PDT 24
Peak memory 204032 kb
Host smart-331f77c7-3d80-4bc9-b7a5-6f621a1f5282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27915
55795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.2791555795
Directory /workspace/21.usbdev_in_stall/latest


Test location /workspace/coverage/default/21.usbdev_in_trans.891257062
Short name T359
Test name
Test status
Simulation time 8464079664 ps
CPU time 8.37 seconds
Started Apr 21 04:01:16 PM PDT 24
Finished Apr 21 04:01:25 PM PDT 24
Peak memory 204040 kb
Host smart-ebf3bc72-8701-445c-9d8a-ad84890fe950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89125
7062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.891257062
Directory /workspace/21.usbdev_in_trans/latest


Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.3341564762
Short name T816
Test name
Test status
Simulation time 8414974354 ps
CPU time 9.63 seconds
Started Apr 21 04:01:11 PM PDT 24
Finished Apr 21 04:01:21 PM PDT 24
Peak memory 203968 kb
Host smart-6a1598a3-2698-44be-8ac8-5baa4f210dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33415
64762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.3341564762
Directory /workspace/21.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.1491612362
Short name T430
Test name
Test status
Simulation time 8371396781 ps
CPU time 7.55 seconds
Started Apr 21 04:01:12 PM PDT 24
Finished Apr 21 04:01:20 PM PDT 24
Peak memory 204064 kb
Host smart-4ff55b53-7f59-4cb7-bd27-53f4fe34601e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14916
12362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.1491612362
Directory /workspace/21.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/21.usbdev_out_stall.2840467654
Short name T545
Test name
Test status
Simulation time 8413768127 ps
CPU time 8.79 seconds
Started Apr 21 04:01:15 PM PDT 24
Finished Apr 21 04:01:24 PM PDT 24
Peak memory 204040 kb
Host smart-a64df2d1-e380-4008-8d34-f1e47aed01f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28404
67654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2840467654
Directory /workspace/21.usbdev_out_stall/latest


Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3299908541
Short name T479
Test name
Test status
Simulation time 8390952516 ps
CPU time 7.84 seconds
Started Apr 21 04:01:12 PM PDT 24
Finished Apr 21 04:01:20 PM PDT 24
Peak memory 204060 kb
Host smart-77e82c8c-b648-45b7-8d52-dfdfe503f972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32999
08541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3299908541
Directory /workspace/21.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/21.usbdev_pending_in_trans.3106237723
Short name T171
Test name
Test status
Simulation time 8432209512 ps
CPU time 7.82 seconds
Started Apr 21 04:01:17 PM PDT 24
Finished Apr 21 04:01:25 PM PDT 24
Peak memory 204032 kb
Host smart-6adcb15d-d8b5-4625-976f-b8865375350c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31062
37723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.3106237723
Directory /workspace/21.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.3571970377
Short name T1026
Test name
Test status
Simulation time 33945878 ps
CPU time 0.72 seconds
Started Apr 21 04:01:18 PM PDT 24
Finished Apr 21 04:01:19 PM PDT 24
Peak memory 203940 kb
Host smart-3b4cad71-5ed9-499b-84b5-d3be3a54d862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35719
70377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.3571970377
Directory /workspace/21.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/21.usbdev_pkt_buffer.1179532230
Short name T1005
Test name
Test status
Simulation time 27434819938 ps
CPU time 51.66 seconds
Started Apr 21 04:01:15 PM PDT 24
Finished Apr 21 04:02:07 PM PDT 24
Peak memory 204324 kb
Host smart-28b25cb7-2711-4323-b221-771fd4847884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11795
32230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.1179532230
Directory /workspace/21.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/21.usbdev_pkt_received.2920241165
Short name T367
Test name
Test status
Simulation time 8433367434 ps
CPU time 8.4 seconds
Started Apr 21 04:01:16 PM PDT 24
Finished Apr 21 04:01:24 PM PDT 24
Peak memory 204064 kb
Host smart-8cce6969-e23b-4e9a-86f1-1f0a75575f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29202
41165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.2920241165
Directory /workspace/21.usbdev_pkt_received/latest


Test location /workspace/coverage/default/21.usbdev_pkt_sent.1031483678
Short name T891
Test name
Test status
Simulation time 8396256932 ps
CPU time 7.99 seconds
Started Apr 21 04:01:18 PM PDT 24
Finished Apr 21 04:01:26 PM PDT 24
Peak memory 204040 kb
Host smart-0b4a7ff0-d3da-46fc-bca0-8c48430bf343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10314
83678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1031483678
Directory /workspace/21.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.2145709979
Short name T2
Test name
Test status
Simulation time 8386117169 ps
CPU time 8.47 seconds
Started Apr 21 04:01:19 PM PDT 24
Finished Apr 21 04:01:28 PM PDT 24
Peak memory 204064 kb
Host smart-507e0af3-b9c2-4675-b670-24a16074bc20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21457
09979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.2145709979
Directory /workspace/21.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/21.usbdev_setup_stage.992167563
Short name T543
Test name
Test status
Simulation time 8375214849 ps
CPU time 7.81 seconds
Started Apr 21 04:01:19 PM PDT 24
Finished Apr 21 04:01:28 PM PDT 24
Peak memory 204008 kb
Host smart-1d6a585f-bb7c-425d-b463-f7ea769f20b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99216
7563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.992167563
Directory /workspace/21.usbdev_setup_stage/latest


Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1750909963
Short name T678
Test name
Test status
Simulation time 8370120133 ps
CPU time 8.16 seconds
Started Apr 21 04:01:20 PM PDT 24
Finished Apr 21 04:01:28 PM PDT 24
Peak memory 204060 kb
Host smart-cc6e2f8b-bace-438e-9773-ca477e9e9a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17509
09963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1750909963
Directory /workspace/21.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.1889336157
Short name T667
Test name
Test status
Simulation time 8441291431 ps
CPU time 9.59 seconds
Started Apr 21 04:01:18 PM PDT 24
Finished Apr 21 04:01:28 PM PDT 24
Peak memory 204032 kb
Host smart-bd6fd5de-4492-4da5-bb58-33b1d74dd39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18893
36157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.1889336157
Directory /workspace/21.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/21.usbdev_stall_trans.1062591792
Short name T800
Test name
Test status
Simulation time 8401522193 ps
CPU time 8.34 seconds
Started Apr 21 04:01:18 PM PDT 24
Finished Apr 21 04:01:27 PM PDT 24
Peak memory 204076 kb
Host smart-25a8c9f7-7cf9-447e-96bf-137fca08d2cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10625
91792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.1062591792
Directory /workspace/21.usbdev_stall_trans/latest


Test location /workspace/coverage/default/22.max_length_in_transaction.1951636486
Short name T368
Test name
Test status
Simulation time 8466118897 ps
CPU time 9.81 seconds
Started Apr 21 04:01:33 PM PDT 24
Finished Apr 21 04:01:43 PM PDT 24
Peak memory 204220 kb
Host smart-4f06695b-4266-4df8-8600-2103d805f58f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1951636486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.1951636486
Directory /workspace/22.max_length_in_transaction/latest


Test location /workspace/coverage/default/22.min_length_in_transaction.1560353752
Short name T518
Test name
Test status
Simulation time 8372109551 ps
CPU time 7.93 seconds
Started Apr 21 04:01:31 PM PDT 24
Finished Apr 21 04:01:39 PM PDT 24
Peak memory 204036 kb
Host smart-62eb845b-be84-4c98-9b2a-f83afd6efee4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1560353752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.1560353752
Directory /workspace/22.min_length_in_transaction/latest


Test location /workspace/coverage/default/22.random_length_in_trans.237280670
Short name T1024
Test name
Test status
Simulation time 8447664299 ps
CPU time 7.55 seconds
Started Apr 21 04:01:30 PM PDT 24
Finished Apr 21 04:01:38 PM PDT 24
Peak memory 204056 kb
Host smart-c46ae312-3771-4eca-b28e-a1501e9cb35e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23728
0670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.237280670
Directory /workspace/22.random_length_in_trans/latest


Test location /workspace/coverage/default/22.usbdev_av_buffer.4037831636
Short name T442
Test name
Test status
Simulation time 8384962143 ps
CPU time 8.36 seconds
Started Apr 21 04:01:21 PM PDT 24
Finished Apr 21 04:01:29 PM PDT 24
Peak memory 203460 kb
Host smart-18f5345a-25b3-485e-a411-cf629387d9c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40378
31636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.4037831636
Directory /workspace/22.usbdev_av_buffer/latest


Test location /workspace/coverage/default/22.usbdev_enable.2502769721
Short name T805
Test name
Test status
Simulation time 8381412000 ps
CPU time 8.27 seconds
Started Apr 21 04:01:29 PM PDT 24
Finished Apr 21 04:01:37 PM PDT 24
Peak memory 204036 kb
Host smart-6a2d209c-7c9c-4231-8ce6-49464c6d6684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25027
69721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.2502769721
Directory /workspace/22.usbdev_enable/latest


Test location /workspace/coverage/default/22.usbdev_fifo_rst.3357348176
Short name T379
Test name
Test status
Simulation time 163385144 ps
CPU time 1.47 seconds
Started Apr 21 04:01:29 PM PDT 24
Finished Apr 21 04:01:30 PM PDT 24
Peak memory 204104 kb
Host smart-6c6c3659-42b9-41ae-b14d-ae7874286697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33573
48176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.3357348176
Directory /workspace/22.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/22.usbdev_in_iso.1518898732
Short name T1374
Test name
Test status
Simulation time 8410325277 ps
CPU time 7.98 seconds
Started Apr 21 04:01:30 PM PDT 24
Finished Apr 21 04:01:38 PM PDT 24
Peak memory 204088 kb
Host smart-f9a9bc4e-0074-460b-bbf7-29a2bf4afbc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15188
98732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1518898732
Directory /workspace/22.usbdev_in_iso/latest


Test location /workspace/coverage/default/22.usbdev_in_stall.1437866579
Short name T191
Test name
Test status
Simulation time 8397502100 ps
CPU time 9.19 seconds
Started Apr 21 04:01:29 PM PDT 24
Finished Apr 21 04:01:39 PM PDT 24
Peak memory 204080 kb
Host smart-46796b16-697e-40f6-a6c2-1919dabac29e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14378
66579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.1437866579
Directory /workspace/22.usbdev_in_stall/latest


Test location /workspace/coverage/default/22.usbdev_in_trans.1262508091
Short name T1041
Test name
Test status
Simulation time 8436039161 ps
CPU time 7.83 seconds
Started Apr 21 04:01:23 PM PDT 24
Finished Apr 21 04:01:31 PM PDT 24
Peak memory 204024 kb
Host smart-470f00e1-244b-4907-b285-e6642ba6c969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12625
08091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.1262508091
Directory /workspace/22.usbdev_in_trans/latest


Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.2745296525
Short name T467
Test name
Test status
Simulation time 8422174706 ps
CPU time 9.51 seconds
Started Apr 21 04:01:25 PM PDT 24
Finished Apr 21 04:01:35 PM PDT 24
Peak memory 204064 kb
Host smart-0231b9ba-8f69-4839-878a-f2b604f24338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27452
96525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.2745296525
Directory /workspace/22.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.4006114866
Short name T831
Test name
Test status
Simulation time 8391088014 ps
CPU time 9.42 seconds
Started Apr 21 04:01:28 PM PDT 24
Finished Apr 21 04:01:38 PM PDT 24
Peak memory 204032 kb
Host smart-1cb7c1c1-2445-47e6-a139-87d5439ade76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40061
14866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.4006114866
Directory /workspace/22.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/22.usbdev_nak_trans.64483305
Short name T103
Test name
Test status
Simulation time 8401734562 ps
CPU time 7.74 seconds
Started Apr 21 04:01:29 PM PDT 24
Finished Apr 21 04:01:37 PM PDT 24
Peak memory 204036 kb
Host smart-9202a1f6-1d7b-4eec-8fc8-88fd303e1999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64483
305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.64483305
Directory /workspace/22.usbdev_nak_trans/latest


Test location /workspace/coverage/default/22.usbdev_out_stall.3888019055
Short name T1065
Test name
Test status
Simulation time 8431307706 ps
CPU time 7.85 seconds
Started Apr 21 04:01:28 PM PDT 24
Finished Apr 21 04:01:36 PM PDT 24
Peak memory 204036 kb
Host smart-07dc5644-37f0-49a2-9a55-3d95b37f8567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38880
19055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.3888019055
Directory /workspace/22.usbdev_out_stall/latest


Test location /workspace/coverage/default/22.usbdev_out_trans_nak.272761792
Short name T1124
Test name
Test status
Simulation time 8420361238 ps
CPU time 7.55 seconds
Started Apr 21 04:01:24 PM PDT 24
Finished Apr 21 04:01:32 PM PDT 24
Peak memory 203940 kb
Host smart-06be43e6-7402-4987-abb5-1f4c2b39a883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27276
1792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.272761792
Directory /workspace/22.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/22.usbdev_pending_in_trans.549857934
Short name T79
Test name
Test status
Simulation time 8385634402 ps
CPU time 8.07 seconds
Started Apr 21 04:01:30 PM PDT 24
Finished Apr 21 04:01:39 PM PDT 24
Peak memory 204060 kb
Host smart-c594cd21-4340-415d-aefd-bf88c82ab7d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54985
7934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.549857934
Directory /workspace/22.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.3021043282
Short name T852
Test name
Test status
Simulation time 8375757125 ps
CPU time 7.87 seconds
Started Apr 21 04:01:27 PM PDT 24
Finished Apr 21 04:01:35 PM PDT 24
Peak memory 204068 kb
Host smart-e7157838-13cd-431e-ba8a-e6fa32ad32a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30210
43282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.3021043282
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.1048766360
Short name T970
Test name
Test status
Simulation time 66705908 ps
CPU time 0.69 seconds
Started Apr 21 04:01:31 PM PDT 24
Finished Apr 21 04:01:32 PM PDT 24
Peak memory 203928 kb
Host smart-24490edf-a364-4591-9ce3-15d55b5491b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10487
66360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.1048766360
Directory /workspace/22.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/22.usbdev_pkt_buffer.2550336774
Short name T1161
Test name
Test status
Simulation time 29360504535 ps
CPU time 63.98 seconds
Started Apr 21 04:01:26 PM PDT 24
Finished Apr 21 04:02:30 PM PDT 24
Peak memory 204352 kb
Host smart-701693f3-f2c1-452d-a4e4-e521bd4d92c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25503
36774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.2550336774
Directory /workspace/22.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/22.usbdev_pkt_received.1357575072
Short name T77
Test name
Test status
Simulation time 8414959838 ps
CPU time 7.9 seconds
Started Apr 21 04:01:30 PM PDT 24
Finished Apr 21 04:01:38 PM PDT 24
Peak memory 204032 kb
Host smart-0488efb3-67a5-4ad7-885b-1d31c1af6fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13575
75072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.1357575072
Directory /workspace/22.usbdev_pkt_received/latest


Test location /workspace/coverage/default/22.usbdev_pkt_sent.3682793101
Short name T523
Test name
Test status
Simulation time 8450996490 ps
CPU time 8.12 seconds
Started Apr 21 04:01:25 PM PDT 24
Finished Apr 21 04:01:34 PM PDT 24
Peak memory 204048 kb
Host smart-e8f5de21-6f61-47e3-95b4-52dfc41d443b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36827
93101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.3682793101
Directory /workspace/22.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.3521749894
Short name T842
Test name
Test status
Simulation time 8429410761 ps
CPU time 8.98 seconds
Started Apr 21 04:01:27 PM PDT 24
Finished Apr 21 04:01:37 PM PDT 24
Peak memory 204040 kb
Host smart-9626fed9-c7f7-48f7-8bdb-c72f1f500fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35217
49894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.3521749894
Directory /workspace/22.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/22.usbdev_setup_stage.3268831752
Short name T989
Test name
Test status
Simulation time 8379382282 ps
CPU time 7.79 seconds
Started Apr 21 04:01:26 PM PDT 24
Finished Apr 21 04:01:34 PM PDT 24
Peak memory 204016 kb
Host smart-dcba8cba-95a3-4827-865f-69cc4baf4f17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32688
31752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.3268831752
Directory /workspace/22.usbdev_setup_stage/latest


Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1217096742
Short name T275
Test name
Test status
Simulation time 8373066110 ps
CPU time 8.13 seconds
Started Apr 21 04:01:28 PM PDT 24
Finished Apr 21 04:01:36 PM PDT 24
Peak memory 204076 kb
Host smart-cad3193c-995f-4cfb-be83-297a2c7983a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12170
96742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1217096742
Directory /workspace/22.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/22.usbdev_smoke.1772937375
Short name T660
Test name
Test status
Simulation time 8449586468 ps
CPU time 8.24 seconds
Started Apr 21 04:01:23 PM PDT 24
Finished Apr 21 04:01:31 PM PDT 24
Peak memory 204036 kb
Host smart-73e0c0f2-16ea-4233-8533-2d1941efc730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17729
37375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.1772937375
Directory /workspace/22.usbdev_smoke/latest


Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.1230089241
Short name T1183
Test name
Test status
Simulation time 8383297910 ps
CPU time 9.62 seconds
Started Apr 21 04:01:27 PM PDT 24
Finished Apr 21 04:01:37 PM PDT 24
Peak memory 204040 kb
Host smart-991d0950-5a31-469b-b215-e97b5d6b5596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12300
89241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.1230089241
Directory /workspace/22.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/22.usbdev_stall_trans.1134200418
Short name T1249
Test name
Test status
Simulation time 8410144719 ps
CPU time 7.77 seconds
Started Apr 21 04:01:27 PM PDT 24
Finished Apr 21 04:01:35 PM PDT 24
Peak memory 204064 kb
Host smart-35529d9a-adf8-4bcd-8dfd-1ba8fcee8683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11342
00418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.1134200418
Directory /workspace/22.usbdev_stall_trans/latest


Test location /workspace/coverage/default/23.max_length_in_transaction.2693548769
Short name T556
Test name
Test status
Simulation time 8460411665 ps
CPU time 9.55 seconds
Started Apr 21 04:01:40 PM PDT 24
Finished Apr 21 04:01:50 PM PDT 24
Peak memory 204056 kb
Host smart-cf071ba7-428b-48fc-93cd-a0efd0e54753
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2693548769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.2693548769
Directory /workspace/23.max_length_in_transaction/latest


Test location /workspace/coverage/default/23.min_length_in_transaction.1844286095
Short name T629
Test name
Test status
Simulation time 8379837635 ps
CPU time 9.28 seconds
Started Apr 21 04:01:43 PM PDT 24
Finished Apr 21 04:01:53 PM PDT 24
Peak memory 204024 kb
Host smart-d006713b-2f63-4443-8886-76f83b916464
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1844286095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.1844286095
Directory /workspace/23.min_length_in_transaction/latest


Test location /workspace/coverage/default/23.random_length_in_trans.4133044379
Short name T653
Test name
Test status
Simulation time 8456889965 ps
CPU time 8.21 seconds
Started Apr 21 04:01:40 PM PDT 24
Finished Apr 21 04:01:48 PM PDT 24
Peak memory 204048 kb
Host smart-9bde2146-1c6b-4c00-84e3-2690e5b7eadc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41330
44379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.4133044379
Directory /workspace/23.random_length_in_trans/latest


Test location /workspace/coverage/default/23.usbdev_av_buffer.459723964
Short name T1111
Test name
Test status
Simulation time 8374394000 ps
CPU time 7.91 seconds
Started Apr 21 04:01:32 PM PDT 24
Finished Apr 21 04:01:40 PM PDT 24
Peak memory 204024 kb
Host smart-818f28cd-6b79-493f-aa1f-b413748c46f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45972
3964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.459723964
Directory /workspace/23.usbdev_av_buffer/latest


Test location /workspace/coverage/default/23.usbdev_enable.3851800274
Short name T1028
Test name
Test status
Simulation time 8398006904 ps
CPU time 8.52 seconds
Started Apr 21 04:01:33 PM PDT 24
Finished Apr 21 04:01:42 PM PDT 24
Peak memory 204064 kb
Host smart-b069cda1-50bd-43b4-9707-c4583a11b9e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38518
00274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.3851800274
Directory /workspace/23.usbdev_enable/latest


Test location /workspace/coverage/default/23.usbdev_fifo_rst.3355297143
Short name T1050
Test name
Test status
Simulation time 217621633 ps
CPU time 2.42 seconds
Started Apr 21 04:01:39 PM PDT 24
Finished Apr 21 04:01:41 PM PDT 24
Peak memory 204172 kb
Host smart-7ad32f92-0d60-4c0c-a969-06857f68ee25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33552
97143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3355297143
Directory /workspace/23.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/23.usbdev_in_iso.3609671078
Short name T1001
Test name
Test status
Simulation time 8402581039 ps
CPU time 7.88 seconds
Started Apr 21 04:01:43 PM PDT 24
Finished Apr 21 04:01:51 PM PDT 24
Peak memory 204028 kb
Host smart-eb56a238-cd72-4e31-a92c-5c4044bb491f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36096
71078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.3609671078
Directory /workspace/23.usbdev_in_iso/latest


Test location /workspace/coverage/default/23.usbdev_in_stall.3553961757
Short name T1075
Test name
Test status
Simulation time 8364735082 ps
CPU time 8.96 seconds
Started Apr 21 04:01:38 PM PDT 24
Finished Apr 21 04:01:47 PM PDT 24
Peak memory 204036 kb
Host smart-14cdf9db-63ff-4ad4-b05a-95cc7cf0221e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35539
61757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.3553961757
Directory /workspace/23.usbdev_in_stall/latest


Test location /workspace/coverage/default/23.usbdev_in_trans.2079846007
Short name T917
Test name
Test status
Simulation time 8388824529 ps
CPU time 8.16 seconds
Started Apr 21 04:01:31 PM PDT 24
Finished Apr 21 04:01:39 PM PDT 24
Peak memory 204088 kb
Host smart-826a495a-09e4-4471-aa0f-2d8232e950ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20798
46007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.2079846007
Directory /workspace/23.usbdev_in_trans/latest


Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.2535170406
Short name T351
Test name
Test status
Simulation time 8449706846 ps
CPU time 9.01 seconds
Started Apr 21 04:01:35 PM PDT 24
Finished Apr 21 04:01:44 PM PDT 24
Peak memory 204032 kb
Host smart-b69f0525-c0fd-4a4e-b2a2-0a52f37da6c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25351
70406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.2535170406
Directory /workspace/23.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.17531748
Short name T812
Test name
Test status
Simulation time 8369150407 ps
CPU time 8.72 seconds
Started Apr 21 04:01:37 PM PDT 24
Finished Apr 21 04:01:46 PM PDT 24
Peak memory 204032 kb
Host smart-9f2e0ed9-f113-4b09-a099-93a6a2883e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17531
748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.17531748
Directory /workspace/23.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/23.usbdev_nak_trans.1353458356
Short name T1256
Test name
Test status
Simulation time 8413909726 ps
CPU time 8.16 seconds
Started Apr 21 04:01:37 PM PDT 24
Finished Apr 21 04:01:45 PM PDT 24
Peak memory 204064 kb
Host smart-8e15eee0-9a2b-4c44-8da3-f57dc2d4e8b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13534
58356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.1353458356
Directory /workspace/23.usbdev_nak_trans/latest


Test location /workspace/coverage/default/23.usbdev_out_stall.3470822156
Short name T546
Test name
Test status
Simulation time 8395357900 ps
CPU time 7.42 seconds
Started Apr 21 04:01:34 PM PDT 24
Finished Apr 21 04:01:42 PM PDT 24
Peak memory 204064 kb
Host smart-d9b33223-1172-440d-9d7b-87f67c8ee22e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34708
22156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.3470822156
Directory /workspace/23.usbdev_out_stall/latest


Test location /workspace/coverage/default/23.usbdev_out_trans_nak.1775823503
Short name T383
Test name
Test status
Simulation time 8388980910 ps
CPU time 9.14 seconds
Started Apr 21 04:01:36 PM PDT 24
Finished Apr 21 04:01:45 PM PDT 24
Peak memory 204008 kb
Host smart-072bbbfe-39de-49c5-83b4-d7c18178f382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17758
23503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.1775823503
Directory /workspace/23.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/23.usbdev_pending_in_trans.633715705
Short name T163
Test name
Test status
Simulation time 8407618271 ps
CPU time 7.59 seconds
Started Apr 21 04:01:38 PM PDT 24
Finished Apr 21 04:01:46 PM PDT 24
Peak memory 204052 kb
Host smart-a5fc34cd-a9f4-4e8e-9a6a-50af9435a25b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63371
5705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.633715705
Directory /workspace/23.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.1044557606
Short name T20
Test name
Test status
Simulation time 8368296587 ps
CPU time 7.81 seconds
Started Apr 21 04:01:40 PM PDT 24
Finished Apr 21 04:01:49 PM PDT 24
Peak memory 202720 kb
Host smart-2a17d4a8-2da4-46de-a84e-5caed85538aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10445
57606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.1044557606
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2455047627
Short name T686
Test name
Test status
Simulation time 73755130 ps
CPU time 0.71 seconds
Started Apr 21 04:01:41 PM PDT 24
Finished Apr 21 04:01:42 PM PDT 24
Peak memory 203932 kb
Host smart-ef715825-ce79-49e1-ab4a-17019a53c64c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24550
47627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2455047627
Directory /workspace/23.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/23.usbdev_pkt_buffer.2311877261
Short name T951
Test name
Test status
Simulation time 30964785115 ps
CPU time 64.31 seconds
Started Apr 21 04:01:35 PM PDT 24
Finished Apr 21 04:02:40 PM PDT 24
Peak memory 204312 kb
Host smart-127bf4e0-e2b2-4ac3-ab60-05838dc07d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23118
77261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.2311877261
Directory /workspace/23.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/23.usbdev_pkt_received.83375842
Short name T277
Test name
Test status
Simulation time 8381456719 ps
CPU time 8.34 seconds
Started Apr 21 04:01:39 PM PDT 24
Finished Apr 21 04:01:47 PM PDT 24
Peak memory 204032 kb
Host smart-cf1553dc-af20-4483-a46c-b5129bee494a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83375
842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.83375842
Directory /workspace/23.usbdev_pkt_received/latest


Test location /workspace/coverage/default/23.usbdev_pkt_sent.353944277
Short name T548
Test name
Test status
Simulation time 8397598655 ps
CPU time 8.46 seconds
Started Apr 21 04:01:39 PM PDT 24
Finished Apr 21 04:01:47 PM PDT 24
Peak memory 204056 kb
Host smart-3fdaf363-eccf-4d1d-ad1a-3f5783939a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35394
4277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.353944277
Directory /workspace/23.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.3718823942
Short name T592
Test name
Test status
Simulation time 8429845877 ps
CPU time 8.12 seconds
Started Apr 21 04:01:43 PM PDT 24
Finished Apr 21 04:01:52 PM PDT 24
Peak memory 204040 kb
Host smart-a85c75f8-dac9-4139-a3c0-f2cb2a091952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37188
23942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.3718823942
Directory /workspace/23.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/23.usbdev_setup_stage.1187862315
Short name T1260
Test name
Test status
Simulation time 8406111310 ps
CPU time 8.79 seconds
Started Apr 21 04:01:43 PM PDT 24
Finished Apr 21 04:01:52 PM PDT 24
Peak memory 204060 kb
Host smart-24e714b4-c63a-4507-9b93-b8147f3e5fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11878
62315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.1187862315
Directory /workspace/23.usbdev_setup_stage/latest


Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2230056761
Short name T513
Test name
Test status
Simulation time 8372035672 ps
CPU time 9.17 seconds
Started Apr 21 04:01:40 PM PDT 24
Finished Apr 21 04:01:50 PM PDT 24
Peak memory 204080 kb
Host smart-73434274-b197-40cc-a265-3e556ce7c5ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22300
56761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2230056761
Directory /workspace/23.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/23.usbdev_smoke.3765551924
Short name T1311
Test name
Test status
Simulation time 8450450760 ps
CPU time 8.15 seconds
Started Apr 21 04:01:32 PM PDT 24
Finished Apr 21 04:01:41 PM PDT 24
Peak memory 204048 kb
Host smart-3ee6041b-d0f9-48ec-87e0-e72453202ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37655
51924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3765551924
Directory /workspace/23.usbdev_smoke/latest


Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.3876182025
Short name T401
Test name
Test status
Simulation time 8391702709 ps
CPU time 8.22 seconds
Started Apr 21 04:01:40 PM PDT 24
Finished Apr 21 04:01:49 PM PDT 24
Peak memory 203928 kb
Host smart-60328956-4404-452b-a309-5f2842ee5928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38761
82025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.3876182025
Directory /workspace/23.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/23.usbdev_stall_trans.3216176499
Short name T1058
Test name
Test status
Simulation time 8384863832 ps
CPU time 8.01 seconds
Started Apr 21 04:01:40 PM PDT 24
Finished Apr 21 04:01:48 PM PDT 24
Peak memory 204060 kb
Host smart-f2ddaf64-eab0-4ac6-95f5-81b2762f8976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32161
76499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.3216176499
Directory /workspace/23.usbdev_stall_trans/latest


Test location /workspace/coverage/default/24.max_length_in_transaction.627848454
Short name T362
Test name
Test status
Simulation time 8467973443 ps
CPU time 8 seconds
Started Apr 21 04:01:49 PM PDT 24
Finished Apr 21 04:01:58 PM PDT 24
Peak memory 204068 kb
Host smart-a48a003c-0abe-4501-b145-57308287cc6b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=627848454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.627848454
Directory /workspace/24.max_length_in_transaction/latest


Test location /workspace/coverage/default/24.min_length_in_transaction.4144552482
Short name T1264
Test name
Test status
Simulation time 8379968958 ps
CPU time 8.82 seconds
Started Apr 21 04:01:53 PM PDT 24
Finished Apr 21 04:02:02 PM PDT 24
Peak memory 204088 kb
Host smart-94958a66-b4f7-4066-b4b6-e146d07c89ad
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4144552482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.4144552482
Directory /workspace/24.min_length_in_transaction/latest


Test location /workspace/coverage/default/24.random_length_in_trans.3973426589
Short name T326
Test name
Test status
Simulation time 8431109240 ps
CPU time 9.87 seconds
Started Apr 21 04:01:51 PM PDT 24
Finished Apr 21 04:02:01 PM PDT 24
Peak memory 204080 kb
Host smart-e1630de1-1290-4277-a9ac-582329fa61ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39734
26589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.3973426589
Directory /workspace/24.random_length_in_trans/latest


Test location /workspace/coverage/default/24.usbdev_av_buffer.2048222046
Short name T1380
Test name
Test status
Simulation time 8433631069 ps
CPU time 7.7 seconds
Started Apr 21 04:01:45 PM PDT 24
Finished Apr 21 04:01:53 PM PDT 24
Peak memory 204068 kb
Host smart-79e41c63-7c66-48f9-853e-6510a25cd3ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20482
22046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2048222046
Directory /workspace/24.usbdev_av_buffer/latest


Test location /workspace/coverage/default/24.usbdev_enable.1439900552
Short name T559
Test name
Test status
Simulation time 8385418671 ps
CPU time 9.24 seconds
Started Apr 21 04:01:43 PM PDT 24
Finished Apr 21 04:01:53 PM PDT 24
Peak memory 204048 kb
Host smart-08aca88d-bafc-412e-8601-b9649c935ac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14399
00552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.1439900552
Directory /workspace/24.usbdev_enable/latest


Test location /workspace/coverage/default/24.usbdev_fifo_rst.2289762101
Short name T1177
Test name
Test status
Simulation time 87205546 ps
CPU time 1.2 seconds
Started Apr 21 04:01:46 PM PDT 24
Finished Apr 21 04:01:48 PM PDT 24
Peak memory 204168 kb
Host smart-59b090ce-9c74-4dbe-9e11-75ba3ef49f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22897
62101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2289762101
Directory /workspace/24.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/24.usbdev_in_iso.3902281545
Short name T1061
Test name
Test status
Simulation time 8445043731 ps
CPU time 7.96 seconds
Started Apr 21 04:01:49 PM PDT 24
Finished Apr 21 04:01:57 PM PDT 24
Peak memory 204020 kb
Host smart-3b3d4513-830f-4803-84b9-7f05dedcf60b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39022
81545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.3902281545
Directory /workspace/24.usbdev_in_iso/latest


Test location /workspace/coverage/default/24.usbdev_in_stall.462927346
Short name T1152
Test name
Test status
Simulation time 8372434104 ps
CPU time 7.79 seconds
Started Apr 21 04:01:52 PM PDT 24
Finished Apr 21 04:02:00 PM PDT 24
Peak memory 204068 kb
Host smart-e98c57bb-6673-4639-a41b-55d72a6f8d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46292
7346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.462927346
Directory /workspace/24.usbdev_in_stall/latest


Test location /workspace/coverage/default/24.usbdev_in_trans.3755855303
Short name T1301
Test name
Test status
Simulation time 8433603876 ps
CPU time 8.18 seconds
Started Apr 21 04:01:41 PM PDT 24
Finished Apr 21 04:01:50 PM PDT 24
Peak memory 204044 kb
Host smart-7d867ccc-1dde-4def-b5e1-5c64ab8600d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37558
55303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3755855303
Directory /workspace/24.usbdev_in_trans/latest


Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2243411161
Short name T663
Test name
Test status
Simulation time 8420206714 ps
CPU time 8.16 seconds
Started Apr 21 04:01:42 PM PDT 24
Finished Apr 21 04:01:50 PM PDT 24
Peak memory 204064 kb
Host smart-145c1478-5139-40b5-998d-a055db5c63eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22434
11161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2243411161
Directory /workspace/24.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.2573230065
Short name T1319
Test name
Test status
Simulation time 8374339330 ps
CPU time 10.53 seconds
Started Apr 21 04:01:45 PM PDT 24
Finished Apr 21 04:01:56 PM PDT 24
Peak memory 204040 kb
Host smart-1ae0124b-a005-45ed-8864-01790d527187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25732
30065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2573230065
Directory /workspace/24.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/24.usbdev_nak_trans.128524970
Short name T1079
Test name
Test status
Simulation time 8433095495 ps
CPU time 8.79 seconds
Started Apr 21 04:01:43 PM PDT 24
Finished Apr 21 04:01:52 PM PDT 24
Peak memory 204048 kb
Host smart-46592b35-7a1c-447a-a555-72ca57257fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12852
4970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.128524970
Directory /workspace/24.usbdev_nak_trans/latest


Test location /workspace/coverage/default/24.usbdev_out_stall.2080884529
Short name T509
Test name
Test status
Simulation time 8416099845 ps
CPU time 7.62 seconds
Started Apr 21 04:01:42 PM PDT 24
Finished Apr 21 04:01:50 PM PDT 24
Peak memory 204064 kb
Host smart-4a3435c0-011c-4904-ba30-de27ad362052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20808
84529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.2080884529
Directory /workspace/24.usbdev_out_stall/latest


Test location /workspace/coverage/default/24.usbdev_out_trans_nak.4119615278
Short name T496
Test name
Test status
Simulation time 8393412449 ps
CPU time 7.86 seconds
Started Apr 21 04:01:43 PM PDT 24
Finished Apr 21 04:01:51 PM PDT 24
Peak memory 204072 kb
Host smart-d15da3ec-20dd-42d4-b49c-5e1ffee922eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41196
15278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.4119615278
Directory /workspace/24.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3022869994
Short name T1121
Test name
Test status
Simulation time 8380185176 ps
CPU time 7.56 seconds
Started Apr 21 04:01:47 PM PDT 24
Finished Apr 21 04:01:55 PM PDT 24
Peak memory 204040 kb
Host smart-65887976-42a3-4de0-a3ef-d49e89d5fa93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30228
69994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3022869994
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.1566337611
Short name T581
Test name
Test status
Simulation time 107346848 ps
CPU time 0.78 seconds
Started Apr 21 04:01:46 PM PDT 24
Finished Apr 21 04:01:47 PM PDT 24
Peak memory 203920 kb
Host smart-b1efef56-ffd7-4864-9ddd-b1dd1796f518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15663
37611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.1566337611
Directory /workspace/24.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/24.usbdev_pkt_buffer.1632107284
Short name T94
Test name
Test status
Simulation time 22120433728 ps
CPU time 45.1 seconds
Started Apr 21 04:01:43 PM PDT 24
Finished Apr 21 04:02:29 PM PDT 24
Peak memory 204340 kb
Host smart-ba25d0b2-b130-4c39-9864-be3e193ba5b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16321
07284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.1632107284
Directory /workspace/24.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/24.usbdev_pkt_received.3670372883
Short name T88
Test name
Test status
Simulation time 8377794051 ps
CPU time 8.07 seconds
Started Apr 21 04:01:43 PM PDT 24
Finished Apr 21 04:01:51 PM PDT 24
Peak memory 204064 kb
Host smart-32be6500-dc2b-4bb6-8414-5a29a93b31c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36703
72883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.3670372883
Directory /workspace/24.usbdev_pkt_received/latest


Test location /workspace/coverage/default/24.usbdev_pkt_sent.2528949955
Short name T605
Test name
Test status
Simulation time 8419734177 ps
CPU time 9.01 seconds
Started Apr 21 04:01:47 PM PDT 24
Finished Apr 21 04:01:56 PM PDT 24
Peak memory 204040 kb
Host smart-dbc6cec7-89bc-491c-af42-ecf6ffecb65e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25289
49955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.2528949955
Directory /workspace/24.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.2156120944
Short name T815
Test name
Test status
Simulation time 8399884052 ps
CPU time 7.98 seconds
Started Apr 21 04:01:47 PM PDT 24
Finished Apr 21 04:01:55 PM PDT 24
Peak memory 204052 kb
Host smart-ecc8dda2-d32d-46ee-961b-4db07cdf7079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21561
20944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.2156120944
Directory /workspace/24.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/24.usbdev_setup_stage.1758693922
Short name T655
Test name
Test status
Simulation time 8378017747 ps
CPU time 9.91 seconds
Started Apr 21 04:01:46 PM PDT 24
Finished Apr 21 04:01:57 PM PDT 24
Peak memory 203964 kb
Host smart-9d106f2b-03be-40b7-9401-43e81eea510d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17586
93922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1758693922
Directory /workspace/24.usbdev_setup_stage/latest


Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2215318453
Short name T354
Test name
Test status
Simulation time 8437261584 ps
CPU time 7.8 seconds
Started Apr 21 04:01:47 PM PDT 24
Finished Apr 21 04:01:55 PM PDT 24
Peak memory 204060 kb
Host smart-ede5f194-2826-4070-b098-f66f93d63571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22153
18453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2215318453
Directory /workspace/24.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/24.usbdev_smoke.678165156
Short name T688
Test name
Test status
Simulation time 8435380166 ps
CPU time 7.56 seconds
Started Apr 21 04:01:40 PM PDT 24
Finished Apr 21 04:01:48 PM PDT 24
Peak memory 204084 kb
Host smart-004cba53-ee28-44c5-a585-6c3d8f1f280a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67816
5156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.678165156
Directory /workspace/24.usbdev_smoke/latest


Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.3691143910
Short name T1008
Test name
Test status
Simulation time 8400467158 ps
CPU time 8.38 seconds
Started Apr 21 04:01:46 PM PDT 24
Finished Apr 21 04:01:55 PM PDT 24
Peak memory 204016 kb
Host smart-92380fcf-4e8a-4b1a-9808-c4a7f30c8fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36911
43910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.3691143910
Directory /workspace/24.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/24.usbdev_stall_trans.753110492
Short name T1095
Test name
Test status
Simulation time 8379282249 ps
CPU time 8.57 seconds
Started Apr 21 04:01:47 PM PDT 24
Finished Apr 21 04:01:56 PM PDT 24
Peak memory 204068 kb
Host smart-9ea04bb9-cbfd-4dc6-9bbc-3995383fe662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75311
0492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.753110492
Directory /workspace/24.usbdev_stall_trans/latest


Test location /workspace/coverage/default/25.max_length_in_transaction.3530940592
Short name T644
Test name
Test status
Simulation time 8467756045 ps
CPU time 7.83 seconds
Started Apr 21 04:01:58 PM PDT 24
Finished Apr 21 04:02:06 PM PDT 24
Peak memory 203960 kb
Host smart-8b60775b-4609-4117-8cea-4244a907f9c7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3530940592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.3530940592
Directory /workspace/25.max_length_in_transaction/latest


Test location /workspace/coverage/default/25.min_length_in_transaction.163563526
Short name T1207
Test name
Test status
Simulation time 8378257661 ps
CPU time 9.39 seconds
Started Apr 21 04:01:57 PM PDT 24
Finished Apr 21 04:02:07 PM PDT 24
Peak memory 204220 kb
Host smart-01003742-6e01-4155-8dcd-63084fb00381
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=163563526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.163563526
Directory /workspace/25.min_length_in_transaction/latest


Test location /workspace/coverage/default/25.random_length_in_trans.3219721688
Short name T878
Test name
Test status
Simulation time 8429878962 ps
CPU time 8.67 seconds
Started Apr 21 04:01:56 PM PDT 24
Finished Apr 21 04:02:05 PM PDT 24
Peak memory 204024 kb
Host smart-19e207cc-dc8d-4c1a-955c-feb731128456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32197
21688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.3219721688
Directory /workspace/25.random_length_in_trans/latest


Test location /workspace/coverage/default/25.usbdev_av_buffer.1027134385
Short name T820
Test name
Test status
Simulation time 8378984954 ps
CPU time 7.78 seconds
Started Apr 21 04:01:51 PM PDT 24
Finished Apr 21 04:01:59 PM PDT 24
Peak memory 204048 kb
Host smart-bcbf66f5-e447-488b-bbb1-4bb01c8274bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10271
34385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.1027134385
Directory /workspace/25.usbdev_av_buffer/latest


Test location /workspace/coverage/default/25.usbdev_enable.3622732121
Short name T594
Test name
Test status
Simulation time 8403352480 ps
CPU time 9.91 seconds
Started Apr 21 04:01:51 PM PDT 24
Finished Apr 21 04:02:02 PM PDT 24
Peak memory 204028 kb
Host smart-f656647d-2426-43ed-b64c-1918fe9f056f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36227
32121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3622732121
Directory /workspace/25.usbdev_enable/latest


Test location /workspace/coverage/default/25.usbdev_fifo_rst.1603339362
Short name T830
Test name
Test status
Simulation time 58161233 ps
CPU time 1.44 seconds
Started Apr 21 04:01:54 PM PDT 24
Finished Apr 21 04:01:56 PM PDT 24
Peak memory 204092 kb
Host smart-64b5d65a-a879-4065-a06f-41215d408a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16033
39362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1603339362
Directory /workspace/25.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/25.usbdev_in_iso.1484042831
Short name T1144
Test name
Test status
Simulation time 8437115502 ps
CPU time 7.61 seconds
Started Apr 21 04:01:58 PM PDT 24
Finished Apr 21 04:02:05 PM PDT 24
Peak memory 204076 kb
Host smart-0e835f4c-c70d-4731-a8ce-0c0f79c723ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14840
42831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.1484042831
Directory /workspace/25.usbdev_in_iso/latest


Test location /workspace/coverage/default/25.usbdev_in_trans.3664764279
Short name T1345
Test name
Test status
Simulation time 8402588643 ps
CPU time 9.34 seconds
Started Apr 21 04:01:57 PM PDT 24
Finished Apr 21 04:02:07 PM PDT 24
Peak memory 204028 kb
Host smart-3acc6553-8adc-4797-a905-ee5832a9feb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36647
64279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3664764279
Directory /workspace/25.usbdev_in_trans/latest


Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.3505690113
Short name T522
Test name
Test status
Simulation time 8469980041 ps
CPU time 8.94 seconds
Started Apr 21 04:01:52 PM PDT 24
Finished Apr 21 04:02:01 PM PDT 24
Peak memory 204044 kb
Host smart-7beb68ae-1b72-48ae-ba08-d886360e9dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35056
90113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.3505690113
Directory /workspace/25.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.2706983693
Short name T480
Test name
Test status
Simulation time 8380818922 ps
CPU time 8.55 seconds
Started Apr 21 04:01:54 PM PDT 24
Finished Apr 21 04:02:03 PM PDT 24
Peak memory 204040 kb
Host smart-5bee8130-859e-4240-affc-88e2c2d255ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27069
83693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.2706983693
Directory /workspace/25.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/25.usbdev_nak_trans.4113433993
Short name T125
Test name
Test status
Simulation time 8434370718 ps
CPU time 9.86 seconds
Started Apr 21 04:01:52 PM PDT 24
Finished Apr 21 04:02:02 PM PDT 24
Peak memory 204044 kb
Host smart-6a002b4b-b8a1-4388-98ca-465a2d146e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41134
33993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.4113433993
Directory /workspace/25.usbdev_nak_trans/latest


Test location /workspace/coverage/default/25.usbdev_out_stall.1736469463
Short name T355
Test name
Test status
Simulation time 8408325535 ps
CPU time 9.11 seconds
Started Apr 21 04:01:55 PM PDT 24
Finished Apr 21 04:02:04 PM PDT 24
Peak memory 204036 kb
Host smart-bc12b462-9549-43da-879b-55a52bfbacf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17364
69463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.1736469463
Directory /workspace/25.usbdev_out_stall/latest


Test location /workspace/coverage/default/25.usbdev_out_trans_nak.512343808
Short name T350
Test name
Test status
Simulation time 8405728171 ps
CPU time 7.94 seconds
Started Apr 21 04:01:55 PM PDT 24
Finished Apr 21 04:02:03 PM PDT 24
Peak memory 204084 kb
Host smart-0c743294-705c-49a1-bcb4-1e6045262b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51234
3808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.512343808
Directory /workspace/25.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.3418439508
Short name T436
Test name
Test status
Simulation time 8376396202 ps
CPU time 8.13 seconds
Started Apr 21 04:01:55 PM PDT 24
Finished Apr 21 04:02:04 PM PDT 24
Peak memory 204044 kb
Host smart-95e9432e-e190-4d5f-9aad-2654d79b3a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34184
39508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.3418439508
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.1449235636
Short name T714
Test name
Test status
Simulation time 66790746 ps
CPU time 0.71 seconds
Started Apr 21 04:01:57 PM PDT 24
Finished Apr 21 04:01:58 PM PDT 24
Peak memory 203884 kb
Host smart-9969e0d6-35ac-4670-9457-d4cb1e9b7105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14492
35636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.1449235636
Directory /workspace/25.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/25.usbdev_pkt_buffer.3953239088
Short name T229
Test name
Test status
Simulation time 30277157805 ps
CPU time 61.85 seconds
Started Apr 21 04:01:55 PM PDT 24
Finished Apr 21 04:02:58 PM PDT 24
Peak memory 204372 kb
Host smart-ba5f65d8-9e15-49fc-84b3-02f2a59494b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39532
39088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.3953239088
Directory /workspace/25.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/25.usbdev_pkt_received.1267096492
Short name T1230
Test name
Test status
Simulation time 8399657764 ps
CPU time 10.08 seconds
Started Apr 21 04:01:54 PM PDT 24
Finished Apr 21 04:02:05 PM PDT 24
Peak memory 204040 kb
Host smart-ff4afab5-148d-4d1c-883f-74c0d6036b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12670
96492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.1267096492
Directory /workspace/25.usbdev_pkt_received/latest


Test location /workspace/coverage/default/25.usbdev_pkt_sent.2597625460
Short name T439
Test name
Test status
Simulation time 8446452760 ps
CPU time 8.51 seconds
Started Apr 21 04:01:52 PM PDT 24
Finished Apr 21 04:02:01 PM PDT 24
Peak memory 203948 kb
Host smart-8fbaf2ce-9bcf-4ffa-a7f9-884b1801acdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25976
25460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.2597625460
Directory /workspace/25.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.4202494065
Short name T768
Test name
Test status
Simulation time 8375403474 ps
CPU time 10.22 seconds
Started Apr 21 04:01:54 PM PDT 24
Finished Apr 21 04:02:05 PM PDT 24
Peak memory 204064 kb
Host smart-98cfbbdb-c3b9-4b96-ae8e-174093946d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42024
94065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.4202494065
Directory /workspace/25.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/25.usbdev_setup_stage.2240893750
Short name T1344
Test name
Test status
Simulation time 8379686302 ps
CPU time 9.25 seconds
Started Apr 21 04:01:57 PM PDT 24
Finished Apr 21 04:02:07 PM PDT 24
Peak memory 204020 kb
Host smart-bfff546e-89a7-44ac-bd33-0d9898df9940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22408
93750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.2240893750
Directory /workspace/25.usbdev_setup_stage/latest


Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.1012445369
Short name T782
Test name
Test status
Simulation time 8372237552 ps
CPU time 7.87 seconds
Started Apr 21 04:01:54 PM PDT 24
Finished Apr 21 04:02:02 PM PDT 24
Peak memory 204040 kb
Host smart-efed8b52-dfe4-4355-bff1-64e40b1b0af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10124
45369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.1012445369
Directory /workspace/25.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/25.usbdev_smoke.1292891656
Short name T166
Test name
Test status
Simulation time 8520596757 ps
CPU time 10.05 seconds
Started Apr 21 04:01:49 PM PDT 24
Finished Apr 21 04:02:00 PM PDT 24
Peak memory 204068 kb
Host smart-80668b9f-4fc9-4f52-9261-b3f76928d4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12928
91656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1292891656
Directory /workspace/25.usbdev_smoke/latest


Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.526413451
Short name T1338
Test name
Test status
Simulation time 8394746555 ps
CPU time 8.29 seconds
Started Apr 21 04:01:54 PM PDT 24
Finished Apr 21 04:02:03 PM PDT 24
Peak memory 204060 kb
Host smart-a067ba5f-fc8c-4e56-b4d4-1255ed9b6fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52641
3451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.526413451
Directory /workspace/25.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/25.usbdev_stall_trans.1829942597
Short name T1331
Test name
Test status
Simulation time 8398932117 ps
CPU time 8.53 seconds
Started Apr 21 04:01:52 PM PDT 24
Finished Apr 21 04:02:01 PM PDT 24
Peak memory 204060 kb
Host smart-38ce7242-6fcb-48f1-8fd2-ac7220c08418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18299
42597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.1829942597
Directory /workspace/25.usbdev_stall_trans/latest


Test location /workspace/coverage/default/26.max_length_in_transaction.2540873143
Short name T1166
Test name
Test status
Simulation time 8461308022 ps
CPU time 8.6 seconds
Started Apr 21 04:02:08 PM PDT 24
Finished Apr 21 04:02:17 PM PDT 24
Peak memory 204032 kb
Host smart-39c5c218-be74-42c4-bcc5-903ac11b0539
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2540873143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.2540873143
Directory /workspace/26.max_length_in_transaction/latest


Test location /workspace/coverage/default/26.min_length_in_transaction.1206079319
Short name T1148
Test name
Test status
Simulation time 8377666132 ps
CPU time 7.62 seconds
Started Apr 21 04:02:08 PM PDT 24
Finished Apr 21 04:02:16 PM PDT 24
Peak memory 204044 kb
Host smart-e9c66029-116b-43e1-9ef5-6b957b6928fb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1206079319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.1206079319
Directory /workspace/26.min_length_in_transaction/latest


Test location /workspace/coverage/default/26.random_length_in_trans.2646507065
Short name T761
Test name
Test status
Simulation time 8404663029 ps
CPU time 8.11 seconds
Started Apr 21 04:02:07 PM PDT 24
Finished Apr 21 04:02:16 PM PDT 24
Peak memory 204068 kb
Host smart-a87b11a2-d95b-4119-a752-af9dda276fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26465
07065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.2646507065
Directory /workspace/26.random_length_in_trans/latest


Test location /workspace/coverage/default/26.usbdev_av_buffer.4248571921
Short name T666
Test name
Test status
Simulation time 8394554360 ps
CPU time 9.52 seconds
Started Apr 21 04:02:01 PM PDT 24
Finished Apr 21 04:02:11 PM PDT 24
Peak memory 204044 kb
Host smart-80f271f4-71f8-4fe7-9a7b-9294d4fb4669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42485
71921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.4248571921
Directory /workspace/26.usbdev_av_buffer/latest


Test location /workspace/coverage/default/26.usbdev_enable.1834735948
Short name T1205
Test name
Test status
Simulation time 8406930506 ps
CPU time 10.28 seconds
Started Apr 21 04:02:01 PM PDT 24
Finished Apr 21 04:02:12 PM PDT 24
Peak memory 204044 kb
Host smart-542ce12f-70bf-4714-bd77-7c413d764da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18347
35948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.1834735948
Directory /workspace/26.usbdev_enable/latest


Test location /workspace/coverage/default/26.usbdev_fifo_rst.2978478951
Short name T625
Test name
Test status
Simulation time 86191145 ps
CPU time 1.97 seconds
Started Apr 21 04:02:01 PM PDT 24
Finished Apr 21 04:02:03 PM PDT 24
Peak memory 204156 kb
Host smart-5ed04a17-d90e-4f88-9d34-af3e71e5fa30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29784
78951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.2978478951
Directory /workspace/26.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/26.usbdev_in_iso.2618603051
Short name T148
Test name
Test status
Simulation time 8400954347 ps
CPU time 7.54 seconds
Started Apr 21 04:02:07 PM PDT 24
Finished Apr 21 04:02:15 PM PDT 24
Peak memory 204056 kb
Host smart-bb3ae672-b087-4ac9-8a9e-773ab011491a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26186
03051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.2618603051
Directory /workspace/26.usbdev_in_iso/latest


Test location /workspace/coverage/default/26.usbdev_in_stall.2740809878
Short name T972
Test name
Test status
Simulation time 8368139075 ps
CPU time 7.87 seconds
Started Apr 21 04:02:05 PM PDT 24
Finished Apr 21 04:02:14 PM PDT 24
Peak memory 204040 kb
Host smart-958627fc-be47-4f5b-ac67-25e2d1a09894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27408
09878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2740809878
Directory /workspace/26.usbdev_in_stall/latest


Test location /workspace/coverage/default/26.usbdev_in_trans.246601174
Short name T1114
Test name
Test status
Simulation time 8470052328 ps
CPU time 9.7 seconds
Started Apr 21 04:02:01 PM PDT 24
Finished Apr 21 04:02:11 PM PDT 24
Peak memory 204036 kb
Host smart-8407d9eb-4d1d-47e9-8571-c8f1af79e4b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24660
1174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.246601174
Directory /workspace/26.usbdev_in_trans/latest


Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.2194641560
Short name T884
Test name
Test status
Simulation time 8423909320 ps
CPU time 8.18 seconds
Started Apr 21 04:02:26 PM PDT 24
Finished Apr 21 04:02:34 PM PDT 24
Peak memory 204040 kb
Host smart-adf351da-afda-4be5-8ddd-907dfb19bf53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21946
41560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.2194641560
Directory /workspace/26.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2409637503
Short name T1057
Test name
Test status
Simulation time 8374721875 ps
CPU time 10.43 seconds
Started Apr 21 04:02:00 PM PDT 24
Finished Apr 21 04:02:11 PM PDT 24
Peak memory 204064 kb
Host smart-4df9c533-e1ca-4268-8166-b56cc6af7d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24096
37503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2409637503
Directory /workspace/26.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/26.usbdev_nak_trans.510948299
Short name T885
Test name
Test status
Simulation time 8461772676 ps
CPU time 7.93 seconds
Started Apr 21 04:01:59 PM PDT 24
Finished Apr 21 04:02:07 PM PDT 24
Peak memory 204064 kb
Host smart-c2cf9d33-a240-44db-b68e-c828358c8fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51094
8299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.510948299
Directory /workspace/26.usbdev_nak_trans/latest


Test location /workspace/coverage/default/26.usbdev_out_stall.3289160837
Short name T811
Test name
Test status
Simulation time 8411173674 ps
CPU time 8.19 seconds
Started Apr 21 04:01:59 PM PDT 24
Finished Apr 21 04:02:07 PM PDT 24
Peak memory 204044 kb
Host smart-86370677-fac7-45b3-8940-7586b25fee34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32891
60837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.3289160837
Directory /workspace/26.usbdev_out_stall/latest


Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1219763489
Short name T634
Test name
Test status
Simulation time 8428242546 ps
CPU time 7.77 seconds
Started Apr 21 04:02:01 PM PDT 24
Finished Apr 21 04:02:09 PM PDT 24
Peak memory 204064 kb
Host smart-34f11a55-fa68-4054-8a11-b41f2ad36e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12197
63489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1219763489
Directory /workspace/26.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/26.usbdev_pending_in_trans.1040752180
Short name T754
Test name
Test status
Simulation time 8385471781 ps
CPU time 7.93 seconds
Started Apr 21 04:02:04 PM PDT 24
Finished Apr 21 04:02:12 PM PDT 24
Peak memory 204080 kb
Host smart-ca081daa-a38b-4ea7-8c6e-811f1a6e9b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10407
52180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.1040752180
Directory /workspace/26.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.1214851957
Short name T573
Test name
Test status
Simulation time 8379517086 ps
CPU time 7.42 seconds
Started Apr 21 04:02:05 PM PDT 24
Finished Apr 21 04:02:12 PM PDT 24
Peak memory 204000 kb
Host smart-95772486-165d-44d2-985c-54bdfe877733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12148
51957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.1214851957
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3277114384
Short name T470
Test name
Test status
Simulation time 43624394 ps
CPU time 0.66 seconds
Started Apr 21 04:02:05 PM PDT 24
Finished Apr 21 04:02:06 PM PDT 24
Peak memory 203932 kb
Host smart-f0573b65-6a8a-417c-8b63-bf9957fcb495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32771
14384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3277114384
Directory /workspace/26.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/26.usbdev_pkt_buffer.2041919892
Short name T11
Test name
Test status
Simulation time 21820527333 ps
CPU time 41.96 seconds
Started Apr 21 04:02:04 PM PDT 24
Finished Apr 21 04:02:46 PM PDT 24
Peak memory 204352 kb
Host smart-9991558c-f6fa-42b6-8845-4132eaf17680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20419
19892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.2041919892
Directory /workspace/26.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/26.usbdev_pkt_received.3674540515
Short name T980
Test name
Test status
Simulation time 8398247137 ps
CPU time 7.91 seconds
Started Apr 21 04:02:02 PM PDT 24
Finished Apr 21 04:02:11 PM PDT 24
Peak memory 204068 kb
Host smart-1e3d2980-9c8a-4ca8-bb52-2c5a0a73bfbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36745
40515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.3674540515
Directory /workspace/26.usbdev_pkt_received/latest


Test location /workspace/coverage/default/26.usbdev_pkt_sent.1553513674
Short name T931
Test name
Test status
Simulation time 8459823666 ps
CPU time 8.03 seconds
Started Apr 21 04:02:02 PM PDT 24
Finished Apr 21 04:02:10 PM PDT 24
Peak memory 204036 kb
Host smart-54826211-972d-48c2-a192-0b00c0de4725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15535
13674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1553513674
Directory /workspace/26.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.4241438007
Short name T983
Test name
Test status
Simulation time 8397655261 ps
CPU time 7.91 seconds
Started Apr 21 04:02:01 PM PDT 24
Finished Apr 21 04:02:10 PM PDT 24
Peak memory 204052 kb
Host smart-06184257-5014-4f9a-b605-9c1c0323eba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42414
38007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.4241438007
Directory /workspace/26.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/26.usbdev_setup_stage.1592964769
Short name T890
Test name
Test status
Simulation time 8389810469 ps
CPU time 9.84 seconds
Started Apr 21 04:02:04 PM PDT 24
Finished Apr 21 04:02:15 PM PDT 24
Peak memory 204036 kb
Host smart-aac89701-8ff8-44ef-8ba0-504feadcada1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15929
64769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.1592964769
Directory /workspace/26.usbdev_setup_stage/latest


Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2204088041
Short name T14
Test name
Test status
Simulation time 8374414098 ps
CPU time 8.19 seconds
Started Apr 21 04:02:02 PM PDT 24
Finished Apr 21 04:02:11 PM PDT 24
Peak memory 204040 kb
Host smart-47319a72-62ca-455a-bb21-d339dd894017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22040
88041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2204088041
Directory /workspace/26.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/26.usbdev_smoke.2844092851
Short name T924
Test name
Test status
Simulation time 8471661351 ps
CPU time 8.41 seconds
Started Apr 21 04:01:58 PM PDT 24
Finished Apr 21 04:02:07 PM PDT 24
Peak memory 204000 kb
Host smart-9b43e6c6-f22f-4510-832f-618985849ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28440
92851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.2844092851
Directory /workspace/26.usbdev_smoke/latest


Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1528822488
Short name T429
Test name
Test status
Simulation time 8403464613 ps
CPU time 8.06 seconds
Started Apr 21 04:02:04 PM PDT 24
Finished Apr 21 04:02:12 PM PDT 24
Peak memory 204060 kb
Host smart-59a6bc7d-fe57-4400-9105-48d00365e03a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15288
22488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.1528822488
Directory /workspace/26.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/26.usbdev_stall_trans.2110454788
Short name T478
Test name
Test status
Simulation time 8380904425 ps
CPU time 9.13 seconds
Started Apr 21 04:02:02 PM PDT 24
Finished Apr 21 04:02:12 PM PDT 24
Peak memory 204036 kb
Host smart-019dd252-3cd0-4697-99c5-545065bbd8c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21104
54788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.2110454788
Directory /workspace/26.usbdev_stall_trans/latest


Test location /workspace/coverage/default/27.max_length_in_transaction.1487081710
Short name T1071
Test name
Test status
Simulation time 8464473425 ps
CPU time 8.62 seconds
Started Apr 21 04:02:17 PM PDT 24
Finished Apr 21 04:02:26 PM PDT 24
Peak memory 204036 kb
Host smart-4b74bacf-22ea-4966-9d48-e9280d168ddb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1487081710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.1487081710
Directory /workspace/27.max_length_in_transaction/latest


Test location /workspace/coverage/default/27.min_length_in_transaction.3271815889
Short name T1069
Test name
Test status
Simulation time 8395229129 ps
CPU time 7.92 seconds
Started Apr 21 04:02:17 PM PDT 24
Finished Apr 21 04:02:26 PM PDT 24
Peak memory 204040 kb
Host smart-e2ea1058-01e6-4962-894c-9f7837db8fed
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3271815889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.3271815889
Directory /workspace/27.min_length_in_transaction/latest


Test location /workspace/coverage/default/27.random_length_in_trans.2496192223
Short name T1304
Test name
Test status
Simulation time 8462774462 ps
CPU time 9.2 seconds
Started Apr 21 04:02:16 PM PDT 24
Finished Apr 21 04:02:25 PM PDT 24
Peak memory 204040 kb
Host smart-63498a67-5440-462b-be2e-ba3d5fde0b0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24961
92223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.2496192223
Directory /workspace/27.random_length_in_trans/latest


Test location /workspace/coverage/default/27.usbdev_av_buffer.1828900664
Short name T361
Test name
Test status
Simulation time 8381828421 ps
CPU time 8.41 seconds
Started Apr 21 04:02:07 PM PDT 24
Finished Apr 21 04:02:15 PM PDT 24
Peak memory 204032 kb
Host smart-e5001b04-4731-46cc-8976-c4d7a059622d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18289
00664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.1828900664
Directory /workspace/27.usbdev_av_buffer/latest


Test location /workspace/coverage/default/27.usbdev_enable.1669416642
Short name T1336
Test name
Test status
Simulation time 8384845450 ps
CPU time 7.61 seconds
Started Apr 21 04:02:07 PM PDT 24
Finished Apr 21 04:02:15 PM PDT 24
Peak memory 204044 kb
Host smart-f9a85009-9e46-4bc9-a148-5b05e53d68c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16694
16642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.1669416642
Directory /workspace/27.usbdev_enable/latest


Test location /workspace/coverage/default/27.usbdev_fifo_rst.3792555947
Short name T701
Test name
Test status
Simulation time 300829938 ps
CPU time 1.98 seconds
Started Apr 21 04:02:09 PM PDT 24
Finished Apr 21 04:02:11 PM PDT 24
Peak memory 204196 kb
Host smart-15642ca2-d131-4bc0-b58d-80f90dc0f39a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37925
55947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.3792555947
Directory /workspace/27.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/27.usbdev_in_iso.3969776759
Short name T1295
Test name
Test status
Simulation time 8387780850 ps
CPU time 8.15 seconds
Started Apr 21 04:02:15 PM PDT 24
Finished Apr 21 04:02:23 PM PDT 24
Peak memory 204080 kb
Host smart-968f7e1c-3f63-4de4-9486-6f18b1570b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39697
76759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.3969776759
Directory /workspace/27.usbdev_in_iso/latest


Test location /workspace/coverage/default/27.usbdev_in_stall.2788623228
Short name T199
Test name
Test status
Simulation time 8369216280 ps
CPU time 8.18 seconds
Started Apr 21 04:02:15 PM PDT 24
Finished Apr 21 04:02:23 PM PDT 24
Peak memory 204060 kb
Host smart-b4df28c0-c58d-4979-85d3-a016d1ba7723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27886
23228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2788623228
Directory /workspace/27.usbdev_in_stall/latest


Test location /workspace/coverage/default/27.usbdev_in_trans.392837359
Short name T1373
Test name
Test status
Simulation time 8494220746 ps
CPU time 8.13 seconds
Started Apr 21 04:02:05 PM PDT 24
Finished Apr 21 04:02:13 PM PDT 24
Peak memory 204036 kb
Host smart-c02d615c-575f-4c03-8602-abd75c15c2b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39283
7359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.392837359
Directory /workspace/27.usbdev_in_trans/latest


Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2165776944
Short name T1138
Test name
Test status
Simulation time 8414770898 ps
CPU time 8.28 seconds
Started Apr 21 04:02:10 PM PDT 24
Finished Apr 21 04:02:18 PM PDT 24
Peak memory 204056 kb
Host smart-5b6a9de3-14df-4508-9138-bc6c0a3b624f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21657
76944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2165776944
Directory /workspace/27.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.1419159876
Short name T392
Test name
Test status
Simulation time 8392853152 ps
CPU time 7.54 seconds
Started Apr 21 04:02:10 PM PDT 24
Finished Apr 21 04:02:18 PM PDT 24
Peak memory 204044 kb
Host smart-786d6c8c-da9c-4f2c-8eb2-75526ff00e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14191
59876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.1419159876
Directory /workspace/27.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/27.usbdev_nak_trans.4232807105
Short name T110
Test name
Test status
Simulation time 8460229797 ps
CPU time 7.66 seconds
Started Apr 21 04:02:09 PM PDT 24
Finished Apr 21 04:02:17 PM PDT 24
Peak memory 203940 kb
Host smart-da6a06d4-5632-4351-92cd-95e884394a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42328
07105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.4232807105
Directory /workspace/27.usbdev_nak_trans/latest


Test location /workspace/coverage/default/27.usbdev_out_stall.3904214370
Short name T621
Test name
Test status
Simulation time 8377110120 ps
CPU time 8.02 seconds
Started Apr 21 04:02:10 PM PDT 24
Finished Apr 21 04:02:18 PM PDT 24
Peak memory 204064 kb
Host smart-2b41e665-f000-4e02-962e-0596443e70bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39042
14370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.3904214370
Directory /workspace/27.usbdev_out_stall/latest


Test location /workspace/coverage/default/27.usbdev_out_trans_nak.4061389856
Short name T26
Test name
Test status
Simulation time 8396244276 ps
CPU time 8.72 seconds
Started Apr 21 04:02:10 PM PDT 24
Finished Apr 21 04:02:19 PM PDT 24
Peak memory 204032 kb
Host smart-597bd2e0-a5aa-4f17-9d44-134d8dad049b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40613
89856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.4061389856
Directory /workspace/27.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/27.usbdev_pending_in_trans.3188919741
Short name T202
Test name
Test status
Simulation time 8407231162 ps
CPU time 9.3 seconds
Started Apr 21 04:02:12 PM PDT 24
Finished Apr 21 04:02:22 PM PDT 24
Peak memory 204036 kb
Host smart-b561e083-33ed-44b9-9584-f3fdbc2b4c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31889
19741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.3188919741
Directory /workspace/27.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.573126360
Short name T665
Test name
Test status
Simulation time 8371308890 ps
CPU time 8.05 seconds
Started Apr 21 04:02:13 PM PDT 24
Finished Apr 21 04:02:22 PM PDT 24
Peak memory 204060 kb
Host smart-d1649472-ee4e-48e6-a578-c488611aadea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57312
6360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.573126360
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3601962285
Short name T784
Test name
Test status
Simulation time 58622940 ps
CPU time 0.68 seconds
Started Apr 21 04:02:18 PM PDT 24
Finished Apr 21 04:02:19 PM PDT 24
Peak memory 203916 kb
Host smart-fafbad51-6010-4a6d-a0b3-f7131fbdf3f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36019
62285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3601962285
Directory /workspace/27.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/27.usbdev_pkt_buffer.2379607680
Short name T245
Test name
Test status
Simulation time 27228407736 ps
CPU time 53.74 seconds
Started Apr 21 04:02:11 PM PDT 24
Finished Apr 21 04:03:05 PM PDT 24
Peak memory 204304 kb
Host smart-af6d663d-1cd6-46cd-9c9e-0e88b4245612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23796
07680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.2379607680
Directory /workspace/27.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/27.usbdev_pkt_received.383067528
Short name T1066
Test name
Test status
Simulation time 8378570481 ps
CPU time 7.71 seconds
Started Apr 21 04:02:10 PM PDT 24
Finished Apr 21 04:02:18 PM PDT 24
Peak memory 204064 kb
Host smart-e3689a0f-c375-4a23-b7ea-b5dae6675a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38306
7528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.383067528
Directory /workspace/27.usbdev_pkt_received/latest


Test location /workspace/coverage/default/27.usbdev_pkt_sent.330366904
Short name T558
Test name
Test status
Simulation time 8430299033 ps
CPU time 8.3 seconds
Started Apr 21 04:02:10 PM PDT 24
Finished Apr 21 04:02:19 PM PDT 24
Peak memory 204000 kb
Host smart-40a95675-1c95-4f36-8ccc-0093ca00efdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33036
6904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.330366904
Directory /workspace/27.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.1626140584
Short name T276
Test name
Test status
Simulation time 8365670277 ps
CPU time 7.71 seconds
Started Apr 21 04:02:14 PM PDT 24
Finished Apr 21 04:02:22 PM PDT 24
Peak memory 204080 kb
Host smart-cd97fca4-889a-44e8-9763-bc4c0303e7b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16261
40584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.1626140584
Directory /workspace/27.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/27.usbdev_setup_stage.3560144354
Short name T167
Test name
Test status
Simulation time 8393833059 ps
CPU time 8.24 seconds
Started Apr 21 04:02:14 PM PDT 24
Finished Apr 21 04:02:22 PM PDT 24
Peak memory 204064 kb
Host smart-da1450e6-c1de-4df2-81f1-563d4a999625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35601
44354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.3560144354
Directory /workspace/27.usbdev_setup_stage/latest


Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.3792979680
Short name T904
Test name
Test status
Simulation time 8368675242 ps
CPU time 8.76 seconds
Started Apr 21 04:02:18 PM PDT 24
Finished Apr 21 04:02:27 PM PDT 24
Peak memory 204040 kb
Host smart-f3498417-e9f3-4694-a5ab-1b443e0dd539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37929
79680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.3792979680
Directory /workspace/27.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/27.usbdev_smoke.3747674390
Short name T1355
Test name
Test status
Simulation time 8450990305 ps
CPU time 9.56 seconds
Started Apr 21 04:02:07 PM PDT 24
Finished Apr 21 04:02:17 PM PDT 24
Peak memory 204068 kb
Host smart-9650ad78-6d4b-4da6-8b58-74de0263f048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37476
74390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.3747674390
Directory /workspace/27.usbdev_smoke/latest


Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.2249707054
Short name T1371
Test name
Test status
Simulation time 8392757076 ps
CPU time 8.06 seconds
Started Apr 21 04:02:13 PM PDT 24
Finished Apr 21 04:02:21 PM PDT 24
Peak memory 204068 kb
Host smart-8ceb257d-1351-4070-9cfd-4e2572633512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22497
07054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.2249707054
Directory /workspace/27.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/27.usbdev_stall_trans.1911465984
Short name T366
Test name
Test status
Simulation time 8399393537 ps
CPU time 7.73 seconds
Started Apr 21 04:02:12 PM PDT 24
Finished Apr 21 04:02:20 PM PDT 24
Peak memory 204028 kb
Host smart-71bf02cb-d34c-4222-b9cb-3354cd595e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19114
65984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.1911465984
Directory /workspace/27.usbdev_stall_trans/latest


Test location /workspace/coverage/default/28.max_length_in_transaction.1312315334
Short name T308
Test name
Test status
Simulation time 8500025843 ps
CPU time 8.38 seconds
Started Apr 21 04:02:26 PM PDT 24
Finished Apr 21 04:02:35 PM PDT 24
Peak memory 204040 kb
Host smart-7a72371a-9b96-4bdc-a0e1-ac0de30e3613
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1312315334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.1312315334
Directory /workspace/28.max_length_in_transaction/latest


Test location /workspace/coverage/default/28.min_length_in_transaction.1601574268
Short name T384
Test name
Test status
Simulation time 8389507346 ps
CPU time 8.05 seconds
Started Apr 21 04:02:26 PM PDT 24
Finished Apr 21 04:02:34 PM PDT 24
Peak memory 204040 kb
Host smart-0c2739f8-aee4-43d6-8a1c-3537dd86716b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1601574268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.1601574268
Directory /workspace/28.min_length_in_transaction/latest


Test location /workspace/coverage/default/28.random_length_in_trans.217573738
Short name T1291
Test name
Test status
Simulation time 8440087218 ps
CPU time 8.09 seconds
Started Apr 21 04:02:24 PM PDT 24
Finished Apr 21 04:02:32 PM PDT 24
Peak memory 204016 kb
Host smart-dbb1a2f7-1c29-4377-b24e-e0154fea2343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21757
3738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.217573738
Directory /workspace/28.random_length_in_trans/latest


Test location /workspace/coverage/default/28.usbdev_av_buffer.4022981214
Short name T15
Test name
Test status
Simulation time 8388170404 ps
CPU time 9.08 seconds
Started Apr 21 04:02:23 PM PDT 24
Finished Apr 21 04:02:33 PM PDT 24
Peak memory 204064 kb
Host smart-a45f73dd-943d-4d79-8783-9f51206d4a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40229
81214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.4022981214
Directory /workspace/28.usbdev_av_buffer/latest


Test location /workspace/coverage/default/28.usbdev_enable.989708424
Short name T349
Test name
Test status
Simulation time 8373664600 ps
CPU time 8.77 seconds
Started Apr 21 04:02:17 PM PDT 24
Finished Apr 21 04:02:27 PM PDT 24
Peak memory 204028 kb
Host smart-e1d50ed9-2e6d-4a91-8428-8f563b749b02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98970
8424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.989708424
Directory /workspace/28.usbdev_enable/latest


Test location /workspace/coverage/default/28.usbdev_fifo_rst.2571159965
Short name T562
Test name
Test status
Simulation time 44804807 ps
CPU time 1.3 seconds
Started Apr 21 04:02:17 PM PDT 24
Finished Apr 21 04:02:19 PM PDT 24
Peak memory 204116 kb
Host smart-6f97ed85-d468-49c8-8a15-810c97e89757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25711
59965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2571159965
Directory /workspace/28.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/28.usbdev_in_iso.2504042622
Short name T441
Test name
Test status
Simulation time 8423872526 ps
CPU time 8.69 seconds
Started Apr 21 04:02:24 PM PDT 24
Finished Apr 21 04:02:33 PM PDT 24
Peak memory 204024 kb
Host smart-7749a872-e9f9-41c7-96c3-d0ca130d64f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25040
42622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.2504042622
Directory /workspace/28.usbdev_in_iso/latest


Test location /workspace/coverage/default/28.usbdev_in_stall.2862371930
Short name T966
Test name
Test status
Simulation time 8398974984 ps
CPU time 7.94 seconds
Started Apr 21 04:02:23 PM PDT 24
Finished Apr 21 04:02:32 PM PDT 24
Peak memory 204084 kb
Host smart-d1476110-7348-4575-aba9-0b2f1356d180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28623
71930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.2862371930
Directory /workspace/28.usbdev_in_stall/latest


Test location /workspace/coverage/default/28.usbdev_in_trans.3801950382
Short name T941
Test name
Test status
Simulation time 8524739258 ps
CPU time 8.94 seconds
Started Apr 21 04:02:17 PM PDT 24
Finished Apr 21 04:02:27 PM PDT 24
Peak memory 204084 kb
Host smart-e204a491-e83f-439f-88e5-3829a0486a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38019
50382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3801950382
Directory /workspace/28.usbdev_in_trans/latest


Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.806237708
Short name T567
Test name
Test status
Simulation time 8416234395 ps
CPU time 8.02 seconds
Started Apr 21 04:02:17 PM PDT 24
Finished Apr 21 04:02:26 PM PDT 24
Peak memory 204064 kb
Host smart-39beba0a-2f95-40f9-aedf-7a3dc5e1c8f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80623
7708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.806237708
Directory /workspace/28.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.4216764834
Short name T1076
Test name
Test status
Simulation time 8371138234 ps
CPU time 8.29 seconds
Started Apr 21 04:02:18 PM PDT 24
Finished Apr 21 04:02:27 PM PDT 24
Peak memory 204084 kb
Host smart-e63ecf26-e44d-4ced-9294-543c56198681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42167
64834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.4216764834
Directory /workspace/28.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/28.usbdev_out_stall.2559274779
Short name T433
Test name
Test status
Simulation time 8377274847 ps
CPU time 7.88 seconds
Started Apr 21 04:02:23 PM PDT 24
Finished Apr 21 04:02:31 PM PDT 24
Peak memory 204064 kb
Host smart-56a599d7-203e-419f-af51-b2f84488e37a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25592
74779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.2559274779
Directory /workspace/28.usbdev_out_stall/latest


Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2175542686
Short name T1157
Test name
Test status
Simulation time 8413048166 ps
CPU time 9.51 seconds
Started Apr 21 04:02:21 PM PDT 24
Finished Apr 21 04:02:31 PM PDT 24
Peak memory 204224 kb
Host smart-fa72cd33-9420-4443-9907-98ddd1b895f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21755
42686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2175542686
Directory /workspace/28.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1839662644
Short name T185
Test name
Test status
Simulation time 8389606369 ps
CPU time 8.4 seconds
Started Apr 21 04:02:23 PM PDT 24
Finished Apr 21 04:02:32 PM PDT 24
Peak memory 204064 kb
Host smart-cad4c041-db52-47f3-a0ad-506e4f68a5a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18396
62644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1839662644
Directory /workspace/28.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.2919209401
Short name T370
Test name
Test status
Simulation time 8367770073 ps
CPU time 8.03 seconds
Started Apr 21 04:02:22 PM PDT 24
Finished Apr 21 04:02:30 PM PDT 24
Peak memory 204060 kb
Host smart-9c216e30-383e-4107-8634-d53d2b366566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29192
09401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.2919209401
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.1220255306
Short name T1149
Test name
Test status
Simulation time 151820254 ps
CPU time 0.75 seconds
Started Apr 21 04:02:27 PM PDT 24
Finished Apr 21 04:02:28 PM PDT 24
Peak memory 203920 kb
Host smart-010346fe-eb4a-441c-a202-75639c483141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12202
55306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.1220255306
Directory /workspace/28.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/28.usbdev_pkt_buffer.500557528
Short name T1130
Test name
Test status
Simulation time 15409483612 ps
CPU time 28.19 seconds
Started Apr 21 04:02:19 PM PDT 24
Finished Apr 21 04:02:47 PM PDT 24
Peak memory 204296 kb
Host smart-344ebca9-be00-4ee3-99c2-328e465853bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50055
7528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.500557528
Directory /workspace/28.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/28.usbdev_pkt_received.2096819515
Short name T322
Test name
Test status
Simulation time 8397270573 ps
CPU time 8.97 seconds
Started Apr 21 04:02:23 PM PDT 24
Finished Apr 21 04:02:32 PM PDT 24
Peak memory 204060 kb
Host smart-e0bb44a3-6192-4a8b-8a7d-165fb219efba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20968
19515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2096819515
Directory /workspace/28.usbdev_pkt_received/latest


Test location /workspace/coverage/default/28.usbdev_pkt_sent.4269745282
Short name T1284
Test name
Test status
Simulation time 8465608437 ps
CPU time 8.15 seconds
Started Apr 21 04:02:22 PM PDT 24
Finished Apr 21 04:02:30 PM PDT 24
Peak memory 204068 kb
Host smart-9298aef2-aee2-4dbc-9480-67bba2d5173c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42697
45282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.4269745282
Directory /workspace/28.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.3423940186
Short name T475
Test name
Test status
Simulation time 8408828800 ps
CPU time 8.16 seconds
Started Apr 21 04:02:23 PM PDT 24
Finished Apr 21 04:02:32 PM PDT 24
Peak memory 204060 kb
Host smart-3510eb7e-5c13-4e8c-aae7-089a04a000bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34239
40186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.3423940186
Directory /workspace/28.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/28.usbdev_setup_stage.1521214877
Short name T716
Test name
Test status
Simulation time 8380442778 ps
CPU time 8.79 seconds
Started Apr 21 04:02:26 PM PDT 24
Finished Apr 21 04:02:35 PM PDT 24
Peak memory 204032 kb
Host smart-20511cba-00da-42a1-8698-c39742fbc4d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15212
14877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.1521214877
Directory /workspace/28.usbdev_setup_stage/latest


Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.268323147
Short name T1298
Test name
Test status
Simulation time 8368321017 ps
CPU time 8.97 seconds
Started Apr 21 04:02:23 PM PDT 24
Finished Apr 21 04:02:33 PM PDT 24
Peak memory 204052 kb
Host smart-96b7a19e-5f4f-4a9e-a4bc-c2a0eadb5574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26832
3147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.268323147
Directory /workspace/28.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/28.usbdev_smoke.3933994400
Short name T876
Test name
Test status
Simulation time 8437631506 ps
CPU time 8.15 seconds
Started Apr 21 04:02:24 PM PDT 24
Finished Apr 21 04:02:32 PM PDT 24
Peak memory 204068 kb
Host smart-32e512b0-c37c-4b67-a0d1-bf6244b28a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39339
94400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3933994400
Directory /workspace/28.usbdev_smoke/latest


Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.2184015392
Short name T396
Test name
Test status
Simulation time 8404591751 ps
CPU time 9.67 seconds
Started Apr 21 04:02:21 PM PDT 24
Finished Apr 21 04:02:31 PM PDT 24
Peak memory 204020 kb
Host smart-9f087e70-01b6-4fe0-a4d2-9967e6c7ecba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21840
15392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.2184015392
Directory /workspace/28.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/28.usbdev_stall_trans.1014602664
Short name T1038
Test name
Test status
Simulation time 8459970243 ps
CPU time 9.15 seconds
Started Apr 21 04:02:23 PM PDT 24
Finished Apr 21 04:02:33 PM PDT 24
Peak memory 204060 kb
Host smart-b0e4e292-c5bf-40b7-b862-94f5cbadc55a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10146
02664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.1014602664
Directory /workspace/28.usbdev_stall_trans/latest


Test location /workspace/coverage/default/29.max_length_in_transaction.1671902592
Short name T606
Test name
Test status
Simulation time 8461650086 ps
CPU time 8.18 seconds
Started Apr 21 04:02:34 PM PDT 24
Finished Apr 21 04:02:43 PM PDT 24
Peak memory 204044 kb
Host smart-fd538a9e-1b93-468a-9ddd-4cd4c3990044
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1671902592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.1671902592
Directory /workspace/29.max_length_in_transaction/latest


Test location /workspace/coverage/default/29.min_length_in_transaction.708808746
Short name T690
Test name
Test status
Simulation time 8391443938 ps
CPU time 8.04 seconds
Started Apr 21 04:02:33 PM PDT 24
Finished Apr 21 04:02:41 PM PDT 24
Peak memory 204048 kb
Host smart-18553556-4628-4210-bdea-714382461ef8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=708808746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.708808746
Directory /workspace/29.min_length_in_transaction/latest


Test location /workspace/coverage/default/29.random_length_in_trans.1239376700
Short name T824
Test name
Test status
Simulation time 8395058584 ps
CPU time 9.69 seconds
Started Apr 21 04:02:35 PM PDT 24
Finished Apr 21 04:02:45 PM PDT 24
Peak memory 204048 kb
Host smart-92e9fb80-c2ee-4742-92df-ccf6fee97313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12393
76700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.1239376700
Directory /workspace/29.random_length_in_trans/latest


Test location /workspace/coverage/default/29.usbdev_av_buffer.2763613604
Short name T869
Test name
Test status
Simulation time 8426351171 ps
CPU time 7.69 seconds
Started Apr 21 04:02:26 PM PDT 24
Finished Apr 21 04:02:34 PM PDT 24
Peak memory 204068 kb
Host smart-b7561844-69b4-4ba8-8145-ba56f2b8ee1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27636
13604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.2763613604
Directory /workspace/29.usbdev_av_buffer/latest


Test location /workspace/coverage/default/29.usbdev_enable.3887614854
Short name T374
Test name
Test status
Simulation time 8376831645 ps
CPU time 8.71 seconds
Started Apr 21 04:02:26 PM PDT 24
Finished Apr 21 04:02:35 PM PDT 24
Peak memory 204076 kb
Host smart-e7a55ed9-5e14-4d3e-acb3-0ac7178b24b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38876
14854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3887614854
Directory /workspace/29.usbdev_enable/latest


Test location /workspace/coverage/default/29.usbdev_fifo_rst.705738514
Short name T1280
Test name
Test status
Simulation time 258810960 ps
CPU time 2.21 seconds
Started Apr 21 04:02:26 PM PDT 24
Finished Apr 21 04:02:29 PM PDT 24
Peak memory 204132 kb
Host smart-47b51d7d-d482-48a8-8216-74882de2e5f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70573
8514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.705738514
Directory /workspace/29.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/29.usbdev_in_iso.1494428459
Short name T516
Test name
Test status
Simulation time 8427137411 ps
CPU time 8.17 seconds
Started Apr 21 04:02:32 PM PDT 24
Finished Apr 21 04:02:41 PM PDT 24
Peak memory 203964 kb
Host smart-7239c19c-0a6d-464e-bc7a-cff122f9e786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14944
28459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.1494428459
Directory /workspace/29.usbdev_in_iso/latest


Test location /workspace/coverage/default/29.usbdev_in_stall.3611404103
Short name T201
Test name
Test status
Simulation time 8370514695 ps
CPU time 8.14 seconds
Started Apr 21 04:02:33 PM PDT 24
Finished Apr 21 04:02:41 PM PDT 24
Peak memory 204036 kb
Host smart-881289bd-2d02-41cc-ba31-7d9de7c6d488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36114
04103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.3611404103
Directory /workspace/29.usbdev_in_stall/latest


Test location /workspace/coverage/default/29.usbdev_in_trans.4180695596
Short name T145
Test name
Test status
Simulation time 8412467677 ps
CPU time 7.94 seconds
Started Apr 21 04:02:25 PM PDT 24
Finished Apr 21 04:02:34 PM PDT 24
Peak memory 204084 kb
Host smart-8918104c-da28-4ea4-b78e-4269e2ce5e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41806
95596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.4180695596
Directory /workspace/29.usbdev_in_trans/latest


Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.1891540491
Short name T829
Test name
Test status
Simulation time 8415983508 ps
CPU time 9.97 seconds
Started Apr 21 04:02:25 PM PDT 24
Finished Apr 21 04:02:36 PM PDT 24
Peak memory 203940 kb
Host smart-236e0c83-7085-4bb9-a5b2-8f1102e0724e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18915
40491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.1891540491
Directory /workspace/29.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.3647838261
Short name T1342
Test name
Test status
Simulation time 8388282963 ps
CPU time 8.69 seconds
Started Apr 21 04:02:28 PM PDT 24
Finished Apr 21 04:02:37 PM PDT 24
Peak memory 204064 kb
Host smart-bc82ee77-7ce4-4750-8506-6a3eebc82161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36478
38261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3647838261
Directory /workspace/29.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/29.usbdev_nak_trans.1311130727
Short name T130
Test name
Test status
Simulation time 8423952227 ps
CPU time 7.57 seconds
Started Apr 21 04:02:27 PM PDT 24
Finished Apr 21 04:02:35 PM PDT 24
Peak memory 204044 kb
Host smart-c125c3c4-4ab6-4d4b-8aca-f9ce6f153c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13111
30727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.1311130727
Directory /workspace/29.usbdev_nak_trans/latest


Test location /workspace/coverage/default/29.usbdev_out_stall.1461652662
Short name T654
Test name
Test status
Simulation time 8378456424 ps
CPU time 8.82 seconds
Started Apr 21 04:02:29 PM PDT 24
Finished Apr 21 04:02:38 PM PDT 24
Peak memory 204088 kb
Host smart-463d0610-ab38-4314-b912-6fbcda9c5eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14616
52662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.1461652662
Directory /workspace/29.usbdev_out_stall/latest


Test location /workspace/coverage/default/29.usbdev_out_trans_nak.3585697131
Short name T468
Test name
Test status
Simulation time 8396617842 ps
CPU time 7.71 seconds
Started Apr 21 04:02:28 PM PDT 24
Finished Apr 21 04:02:36 PM PDT 24
Peak memory 204048 kb
Host smart-0fc3603f-d610-4823-8bd5-2061f5d15b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35856
97131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3585697131
Directory /workspace/29.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/29.usbdev_pending_in_trans.3569828430
Short name T597
Test name
Test status
Simulation time 8390712510 ps
CPU time 8.78 seconds
Started Apr 21 04:02:34 PM PDT 24
Finished Apr 21 04:02:43 PM PDT 24
Peak memory 204040 kb
Host smart-177ba8f9-20c2-4c10-9e4a-5860a938be1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35698
28430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.3569828430
Directory /workspace/29.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.2390995309
Short name T1082
Test name
Test status
Simulation time 8368816501 ps
CPU time 8.7 seconds
Started Apr 21 04:02:32 PM PDT 24
Finished Apr 21 04:02:41 PM PDT 24
Peak memory 204060 kb
Host smart-fcad6d44-d2dd-45eb-a3ba-5d4bcb8a4cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23909
95309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.2390995309
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.1843139254
Short name T986
Test name
Test status
Simulation time 46013629 ps
CPU time 0.68 seconds
Started Apr 21 04:02:33 PM PDT 24
Finished Apr 21 04:02:33 PM PDT 24
Peak memory 203936 kb
Host smart-661a9522-5f34-4b9a-9352-0f2e79a7347d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18431
39254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.1843139254
Directory /workspace/29.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/29.usbdev_pkt_buffer.4089434803
Short name T1372
Test name
Test status
Simulation time 27927484942 ps
CPU time 53.09 seconds
Started Apr 21 04:02:26 PM PDT 24
Finished Apr 21 04:03:19 PM PDT 24
Peak memory 204352 kb
Host smart-94e7877e-c157-45c3-8a14-9fca01aff1ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40894
34803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.4089434803
Directory /workspace/29.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/29.usbdev_pkt_received.3418112224
Short name T1169
Test name
Test status
Simulation time 8382918665 ps
CPU time 7.78 seconds
Started Apr 21 04:02:27 PM PDT 24
Finished Apr 21 04:02:35 PM PDT 24
Peak memory 204072 kb
Host smart-2c21ffc3-9ba8-4ba7-94a9-bfa892f04ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34181
12224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.3418112224
Directory /workspace/29.usbdev_pkt_received/latest


Test location /workspace/coverage/default/29.usbdev_pkt_sent.3301965612
Short name T1203
Test name
Test status
Simulation time 8384615980 ps
CPU time 10.44 seconds
Started Apr 21 04:02:29 PM PDT 24
Finished Apr 21 04:02:40 PM PDT 24
Peak memory 204068 kb
Host smart-bd5a1656-9bc3-4bc9-baf0-016699167d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33019
65612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.3301965612
Directory /workspace/29.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.1967129123
Short name T420
Test name
Test status
Simulation time 8412020946 ps
CPU time 9.34 seconds
Started Apr 21 04:02:31 PM PDT 24
Finished Apr 21 04:02:41 PM PDT 24
Peak memory 204064 kb
Host smart-3f26fb7a-0522-4512-93c2-63d4a26c4a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19671
29123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.1967129123
Directory /workspace/29.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/29.usbdev_setup_stage.1231969612
Short name T440
Test name
Test status
Simulation time 8384784350 ps
CPU time 9.89 seconds
Started Apr 21 04:02:31 PM PDT 24
Finished Apr 21 04:02:41 PM PDT 24
Peak memory 204076 kb
Host smart-cf498cd2-9e38-43a7-a838-5a92b4b8c47c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12319
69612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.1231969612
Directory /workspace/29.usbdev_setup_stage/latest


Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.3697389458
Short name T1043
Test name
Test status
Simulation time 8372514921 ps
CPU time 8.28 seconds
Started Apr 21 04:02:31 PM PDT 24
Finished Apr 21 04:02:40 PM PDT 24
Peak memory 204040 kb
Host smart-e75e40f2-4e1e-4a9e-b972-9419df0d3282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36973
89458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3697389458
Directory /workspace/29.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/29.usbdev_smoke.1740836021
Short name T157
Test name
Test status
Simulation time 8425082873 ps
CPU time 9.5 seconds
Started Apr 21 04:02:26 PM PDT 24
Finished Apr 21 04:02:36 PM PDT 24
Peak memory 204068 kb
Host smart-0c82835c-a9a4-48ea-a3e3-a53ee880ace0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17408
36021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1740836021
Directory /workspace/29.usbdev_smoke/latest


Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.3431088261
Short name T1221
Test name
Test status
Simulation time 8371912536 ps
CPU time 8.49 seconds
Started Apr 21 04:02:31 PM PDT 24
Finished Apr 21 04:02:39 PM PDT 24
Peak memory 204060 kb
Host smart-5e13e06d-d4ee-463a-acaf-6d88649c4c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34310
88261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.3431088261
Directory /workspace/29.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/29.usbdev_stall_trans.1899816422
Short name T352
Test name
Test status
Simulation time 8407024879 ps
CPU time 7.98 seconds
Started Apr 21 04:02:31 PM PDT 24
Finished Apr 21 04:02:40 PM PDT 24
Peak memory 204064 kb
Host smart-7791e67e-db47-4bdb-9d48-a8e5475cd122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18998
16422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.1899816422
Directory /workspace/29.usbdev_stall_trans/latest


Test location /workspace/coverage/default/3.max_length_in_transaction.3766317261
Short name T431
Test name
Test status
Simulation time 8461004506 ps
CPU time 7.73 seconds
Started Apr 21 03:57:43 PM PDT 24
Finished Apr 21 03:57:51 PM PDT 24
Peak memory 204036 kb
Host smart-d4a51ee9-72ce-4251-a2c1-5761fd5f52fe
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3766317261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.3766317261
Directory /workspace/3.max_length_in_transaction/latest


Test location /workspace/coverage/default/3.min_length_in_transaction.648112006
Short name T1266
Test name
Test status
Simulation time 8383152003 ps
CPU time 9.21 seconds
Started Apr 21 03:57:43 PM PDT 24
Finished Apr 21 03:57:53 PM PDT 24
Peak memory 204024 kb
Host smart-dde0a7fa-e8c9-47e8-91fa-a4db83176874
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=648112006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.648112006
Directory /workspace/3.min_length_in_transaction/latest


Test location /workspace/coverage/default/3.random_length_in_trans.121643189
Short name T36
Test name
Test status
Simulation time 8421045832 ps
CPU time 10.71 seconds
Started Apr 21 03:57:44 PM PDT 24
Finished Apr 21 03:57:55 PM PDT 24
Peak memory 204020 kb
Host smart-de6ea28d-7504-4154-accc-992e0f0a1802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12164
3189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.121643189
Directory /workspace/3.random_length_in_trans/latest


Test location /workspace/coverage/default/3.usbdev_av_buffer.758602143
Short name T661
Test name
Test status
Simulation time 8377988225 ps
CPU time 8.03 seconds
Started Apr 21 03:57:25 PM PDT 24
Finished Apr 21 03:57:34 PM PDT 24
Peak memory 204028 kb
Host smart-72f21b01-7ef5-4b05-84b6-19cb42d7f2fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75860
2143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.758602143
Directory /workspace/3.usbdev_av_buffer/latest


Test location /workspace/coverage/default/3.usbdev_enable.3793661725
Short name T1180
Test name
Test status
Simulation time 8374413299 ps
CPU time 7.78 seconds
Started Apr 21 03:57:29 PM PDT 24
Finished Apr 21 03:57:37 PM PDT 24
Peak memory 204044 kb
Host smart-2c712554-d906-478e-894f-b955f9e56013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37936
61725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.3793661725
Directory /workspace/3.usbdev_enable/latest


Test location /workspace/coverage/default/3.usbdev_fifo_rst.1414770524
Short name T557
Test name
Test status
Simulation time 105076015 ps
CPU time 1.35 seconds
Started Apr 21 03:57:29 PM PDT 24
Finished Apr 21 03:57:30 PM PDT 24
Peak memory 204140 kb
Host smart-c354ef5d-0644-4072-99f7-a379a512762e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14147
70524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.1414770524
Directory /workspace/3.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/3.usbdev_in_iso.3031142850
Short name T971
Test name
Test status
Simulation time 8486968564 ps
CPU time 8.05 seconds
Started Apr 21 03:57:43 PM PDT 24
Finished Apr 21 03:57:52 PM PDT 24
Peak memory 204052 kb
Host smart-35db4c5e-3ae2-4258-9ce6-ab5262454d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30311
42850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.3031142850
Directory /workspace/3.usbdev_in_iso/latest


Test location /workspace/coverage/default/3.usbdev_in_stall.4271094018
Short name T1261
Test name
Test status
Simulation time 8368968618 ps
CPU time 8.28 seconds
Started Apr 21 03:57:43 PM PDT 24
Finished Apr 21 03:57:52 PM PDT 24
Peak memory 204064 kb
Host smart-9f9fa8e5-d4c1-4412-8f04-b274cefb3384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42710
94018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.4271094018
Directory /workspace/3.usbdev_in_stall/latest


Test location /workspace/coverage/default/3.usbdev_in_trans.3276038508
Short name T753
Test name
Test status
Simulation time 8457463346 ps
CPU time 8.08 seconds
Started Apr 21 03:57:29 PM PDT 24
Finished Apr 21 03:57:37 PM PDT 24
Peak memory 203968 kb
Host smart-21772870-6ab8-4daf-9cc6-8d6bc8d6777a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32760
38508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.3276038508
Directory /workspace/3.usbdev_in_trans/latest


Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.765895092
Short name T893
Test name
Test status
Simulation time 8502801401 ps
CPU time 10.35 seconds
Started Apr 21 03:57:33 PM PDT 24
Finished Apr 21 03:57:43 PM PDT 24
Peak memory 204016 kb
Host smart-ba6a7a71-5098-49c5-811c-e5c233ca7ad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76589
5092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.765895092
Directory /workspace/3.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.3011851052
Short name T418
Test name
Test status
Simulation time 8381040033 ps
CPU time 9.7 seconds
Started Apr 21 03:57:35 PM PDT 24
Finished Apr 21 03:57:46 PM PDT 24
Peak memory 204036 kb
Host smart-e555449c-9d6a-4387-927b-a0cd8e1d0aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30118
51052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.3011851052
Directory /workspace/3.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/3.usbdev_nak_trans.428419567
Short name T132
Test name
Test status
Simulation time 8416690293 ps
CPU time 8.22 seconds
Started Apr 21 03:57:35 PM PDT 24
Finished Apr 21 03:57:43 PM PDT 24
Peak memory 204028 kb
Host smart-21308ef4-23ff-41d2-b4ad-0be52187996a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42841
9567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.428419567
Directory /workspace/3.usbdev_nak_trans/latest


Test location /workspace/coverage/default/3.usbdev_out_stall.2140543294
Short name T898
Test name
Test status
Simulation time 8455012221 ps
CPU time 8.12 seconds
Started Apr 21 03:57:35 PM PDT 24
Finished Apr 21 03:57:43 PM PDT 24
Peak memory 204044 kb
Host smart-15de499b-6ed2-4c12-8277-79d79c66691b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21405
43294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.2140543294
Directory /workspace/3.usbdev_out_stall/latest


Test location /workspace/coverage/default/3.usbdev_out_trans_nak.2979012372
Short name T1320
Test name
Test status
Simulation time 8397063972 ps
CPU time 9.2 seconds
Started Apr 21 03:57:35 PM PDT 24
Finished Apr 21 03:57:45 PM PDT 24
Peak memory 204080 kb
Host smart-4de42c19-b97c-4d81-9069-f341d7dcd79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29790
12372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.2979012372
Directory /workspace/3.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/3.usbdev_pending_in_trans.3416684413
Short name T935
Test name
Test status
Simulation time 8394925241 ps
CPU time 7.79 seconds
Started Apr 21 03:57:44 PM PDT 24
Finished Apr 21 03:57:52 PM PDT 24
Peak memory 204052 kb
Host smart-64a15298-96ec-48db-9cff-db5495b10543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34166
84413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.3416684413
Directory /workspace/3.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.3075371437
Short name T520
Test name
Test status
Simulation time 8370723118 ps
CPU time 7.75 seconds
Started Apr 21 03:57:46 PM PDT 24
Finished Apr 21 03:57:54 PM PDT 24
Peak memory 204060 kb
Host smart-ba7d83d5-8045-489a-90fd-ca3b98b3420d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30753
71437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.3075371437
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2948373576
Short name T1145
Test name
Test status
Simulation time 33118312 ps
CPU time 0.67 seconds
Started Apr 21 03:57:45 PM PDT 24
Finished Apr 21 03:57:46 PM PDT 24
Peak memory 203944 kb
Host smart-53ab5870-2209-447c-91a5-f3e271b704f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29483
73576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2948373576
Directory /workspace/3.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/3.usbdev_pkt_buffer.3244574413
Short name T531
Test name
Test status
Simulation time 28671364950 ps
CPU time 56.82 seconds
Started Apr 21 03:57:38 PM PDT 24
Finished Apr 21 03:58:35 PM PDT 24
Peak memory 204308 kb
Host smart-c0c62841-c6e7-42a4-839b-e7df90c7e447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32445
74413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3244574413
Directory /workspace/3.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/3.usbdev_pkt_received.2221671925
Short name T1117
Test name
Test status
Simulation time 8407683993 ps
CPU time 10.21 seconds
Started Apr 21 03:57:39 PM PDT 24
Finished Apr 21 03:57:49 PM PDT 24
Peak memory 204052 kb
Host smart-f88316ae-f8f2-447b-9908-1e396fed5aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22216
71925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.2221671925
Directory /workspace/3.usbdev_pkt_received/latest


Test location /workspace/coverage/default/3.usbdev_pkt_sent.26256491
Short name T1030
Test name
Test status
Simulation time 8437643913 ps
CPU time 10.38 seconds
Started Apr 21 03:57:38 PM PDT 24
Finished Apr 21 03:57:49 PM PDT 24
Peak memory 204060 kb
Host smart-90eed42c-a244-4888-888f-be35f4ff88ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26256
491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.26256491
Directory /workspace/3.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.4165467100
Short name T622
Test name
Test status
Simulation time 8413101397 ps
CPU time 8.16 seconds
Started Apr 21 03:57:39 PM PDT 24
Finished Apr 21 03:57:47 PM PDT 24
Peak memory 204220 kb
Host smart-ee7127ee-7eaf-4db4-8362-402718a3d944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41654
67100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.4165467100
Directory /workspace/3.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/3.usbdev_sec_cm.3509512990
Short name T62
Test name
Test status
Simulation time 385526023 ps
CPU time 1.23 seconds
Started Apr 21 03:57:48 PM PDT 24
Finished Apr 21 03:57:49 PM PDT 24
Peak memory 221256 kb
Host smart-d3b49236-c9a1-4bcf-8765-606e9376f689
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3509512990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3509512990
Directory /workspace/3.usbdev_sec_cm/latest


Test location /workspace/coverage/default/3.usbdev_setup_stage.1518748895
Short name T907
Test name
Test status
Simulation time 8392583043 ps
CPU time 8.06 seconds
Started Apr 21 03:57:48 PM PDT 24
Finished Apr 21 03:57:56 PM PDT 24
Peak memory 204032 kb
Host smart-08deeda9-66dd-44dd-8b3b-252d6ef84eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15187
48895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.1518748895
Directory /workspace/3.usbdev_setup_stage/latest


Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.1172670103
Short name T1151
Test name
Test status
Simulation time 8446768335 ps
CPU time 8.18 seconds
Started Apr 21 03:57:45 PM PDT 24
Finished Apr 21 03:57:53 PM PDT 24
Peak memory 204064 kb
Host smart-714c3131-f29a-4253-9afc-04b0a51d7b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11726
70103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.1172670103
Directory /workspace/3.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/3.usbdev_smoke.3810390129
Short name T1283
Test name
Test status
Simulation time 8432354646 ps
CPU time 8.85 seconds
Started Apr 21 03:57:30 PM PDT 24
Finished Apr 21 03:57:39 PM PDT 24
Peak memory 204036 kb
Host smart-50ce1125-ea27-4b20-acee-b6e562c435f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38103
90129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.3810390129
Directory /workspace/3.usbdev_smoke/latest


Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.2924116794
Short name T447
Test name
Test status
Simulation time 8407320594 ps
CPU time 7.98 seconds
Started Apr 21 03:57:37 PM PDT 24
Finished Apr 21 03:57:46 PM PDT 24
Peak memory 204032 kb
Host smart-b2ea86b6-9702-48e6-943c-0d762ed90bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29241
16794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.2924116794
Directory /workspace/3.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/3.usbdev_stall_trans.1634417419
Short name T282
Test name
Test status
Simulation time 8394747320 ps
CPU time 7.64 seconds
Started Apr 21 03:57:39 PM PDT 24
Finished Apr 21 03:57:47 PM PDT 24
Peak memory 204224 kb
Host smart-b6edd427-83e9-408e-bbf3-731691467630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16344
17419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.1634417419
Directory /workspace/3.usbdev_stall_trans/latest


Test location /workspace/coverage/default/30.max_length_in_transaction.2197507058
Short name T772
Test name
Test status
Simulation time 8512013246 ps
CPU time 8.05 seconds
Started Apr 21 04:02:40 PM PDT 24
Finished Apr 21 04:02:48 PM PDT 24
Peak memory 204020 kb
Host smart-a3f02407-c16d-4fd9-b180-b69de2c2b410
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2197507058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.2197507058
Directory /workspace/30.max_length_in_transaction/latest


Test location /workspace/coverage/default/30.min_length_in_transaction.2651574934
Short name T517
Test name
Test status
Simulation time 8375519793 ps
CPU time 8.66 seconds
Started Apr 21 04:02:42 PM PDT 24
Finished Apr 21 04:02:51 PM PDT 24
Peak memory 204220 kb
Host smart-9ab7c836-d802-4461-b3fb-7e20fdf01f33
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2651574934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.2651574934
Directory /workspace/30.min_length_in_transaction/latest


Test location /workspace/coverage/default/30.random_length_in_trans.1404614685
Short name T493
Test name
Test status
Simulation time 8428320832 ps
CPU time 8.63 seconds
Started Apr 21 04:02:39 PM PDT 24
Finished Apr 21 04:02:48 PM PDT 24
Peak memory 204060 kb
Host smart-c29242e7-7ae4-40e3-958d-998bd08ff5a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14046
14685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.1404614685
Directory /workspace/30.random_length_in_trans/latest


Test location /workspace/coverage/default/30.usbdev_av_buffer.1136979313
Short name T781
Test name
Test status
Simulation time 8380920292 ps
CPU time 7.78 seconds
Started Apr 21 04:02:35 PM PDT 24
Finished Apr 21 04:02:43 PM PDT 24
Peak memory 204040 kb
Host smart-258b88b6-9fa1-45b0-be1b-3beb78f54829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11369
79313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.1136979313
Directory /workspace/30.usbdev_av_buffer/latest


Test location /workspace/coverage/default/30.usbdev_enable.2043639653
Short name T948
Test name
Test status
Simulation time 8386627028 ps
CPU time 8.5 seconds
Started Apr 21 04:02:34 PM PDT 24
Finished Apr 21 04:02:43 PM PDT 24
Peak memory 204060 kb
Host smart-bbabb207-8889-464e-a0f6-50f20fbac142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20436
39653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2043639653
Directory /workspace/30.usbdev_enable/latest


Test location /workspace/coverage/default/30.usbdev_fifo_rst.392877230
Short name T920
Test name
Test status
Simulation time 112262990 ps
CPU time 1.23 seconds
Started Apr 21 04:02:33 PM PDT 24
Finished Apr 21 04:02:35 PM PDT 24
Peak memory 204136 kb
Host smart-a8921a23-3eff-4b3b-8b07-216146547b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39287
7230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.392877230
Directory /workspace/30.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/30.usbdev_in_iso.2188481458
Short name T787
Test name
Test status
Simulation time 8398141971 ps
CPU time 9.2 seconds
Started Apr 21 04:02:39 PM PDT 24
Finished Apr 21 04:02:49 PM PDT 24
Peak memory 204060 kb
Host smart-1a8b3cac-5ccb-4919-84e0-e0f12953ef11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21884
81458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.2188481458
Directory /workspace/30.usbdev_in_iso/latest


Test location /workspace/coverage/default/30.usbdev_in_stall.2668346914
Short name T182
Test name
Test status
Simulation time 8363550296 ps
CPU time 8.72 seconds
Started Apr 21 04:02:39 PM PDT 24
Finished Apr 21 04:02:48 PM PDT 24
Peak memory 204064 kb
Host smart-7df82330-e5cb-4a04-be2f-c616b8b710ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26683
46914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.2668346914
Directory /workspace/30.usbdev_in_stall/latest


Test location /workspace/coverage/default/30.usbdev_in_trans.741609623
Short name T953
Test name
Test status
Simulation time 8397473942 ps
CPU time 7.33 seconds
Started Apr 21 04:02:35 PM PDT 24
Finished Apr 21 04:02:43 PM PDT 24
Peak memory 204044 kb
Host smart-37eef338-50e3-44e1-9279-783cd47238d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74160
9623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.741609623
Directory /workspace/30.usbdev_in_trans/latest


Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.1567066192
Short name T961
Test name
Test status
Simulation time 8418018887 ps
CPU time 8.77 seconds
Started Apr 21 04:02:37 PM PDT 24
Finished Apr 21 04:02:46 PM PDT 24
Peak memory 204080 kb
Host smart-3fd82ae6-7481-47e2-8c7e-9520e4c603ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15670
66192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1567066192
Directory /workspace/30.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1875842637
Short name T922
Test name
Test status
Simulation time 8372658176 ps
CPU time 7.36 seconds
Started Apr 21 04:02:37 PM PDT 24
Finished Apr 21 04:02:45 PM PDT 24
Peak memory 203324 kb
Host smart-93ae0757-3f20-44e5-a842-ee13a0940e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18758
42637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1875842637
Directory /workspace/30.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/30.usbdev_nak_trans.3952744395
Short name T80
Test name
Test status
Simulation time 8454890847 ps
CPU time 10.3 seconds
Started Apr 21 04:02:38 PM PDT 24
Finished Apr 21 04:02:49 PM PDT 24
Peak memory 204036 kb
Host smart-614231ad-e127-4451-9c90-b2551c0fd086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39527
44395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3952744395
Directory /workspace/30.usbdev_nak_trans/latest


Test location /workspace/coverage/default/30.usbdev_out_stall.2511319191
Short name T977
Test name
Test status
Simulation time 8413944979 ps
CPU time 7.93 seconds
Started Apr 21 04:02:36 PM PDT 24
Finished Apr 21 04:02:44 PM PDT 24
Peak memory 204056 kb
Host smart-399a44f4-d6b7-468a-ac9f-9eb0ff23862e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25113
19191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2511319191
Directory /workspace/30.usbdev_out_stall/latest


Test location /workspace/coverage/default/30.usbdev_out_trans_nak.3712165840
Short name T740
Test name
Test status
Simulation time 8375033950 ps
CPU time 8.06 seconds
Started Apr 21 04:02:38 PM PDT 24
Finished Apr 21 04:02:46 PM PDT 24
Peak memory 204032 kb
Host smart-aa01b581-8f1c-408a-b018-4ad511bb1d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37121
65840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.3712165840
Directory /workspace/30.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/30.usbdev_pending_in_trans.469663792
Short name T1238
Test name
Test status
Simulation time 8370889625 ps
CPU time 8.04 seconds
Started Apr 21 04:02:40 PM PDT 24
Finished Apr 21 04:02:48 PM PDT 24
Peak memory 204044 kb
Host smart-f1b915ae-e34b-45a5-b906-e95855a286b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46966
3792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.469663792
Directory /workspace/30.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.2812525543
Short name T7
Test name
Test status
Simulation time 8369883520 ps
CPU time 8.65 seconds
Started Apr 21 04:02:39 PM PDT 24
Finished Apr 21 04:02:48 PM PDT 24
Peak memory 204044 kb
Host smart-6cf19885-4716-44fd-97eb-096a2b9e4d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28125
25543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.2812525543
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1794995824
Short name T721
Test name
Test status
Simulation time 82863157 ps
CPU time 0.69 seconds
Started Apr 21 04:02:40 PM PDT 24
Finished Apr 21 04:02:41 PM PDT 24
Peak memory 203928 kb
Host smart-c063190c-31c9-498d-bbe3-a3daac168afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17949
95824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1794995824
Directory /workspace/30.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/30.usbdev_pkt_received.1708279947
Short name T16
Test name
Test status
Simulation time 8381871254 ps
CPU time 8.37 seconds
Started Apr 21 04:02:35 PM PDT 24
Finished Apr 21 04:02:44 PM PDT 24
Peak memory 203952 kb
Host smart-59bcfa43-f601-4e87-bad1-5d087ce94135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17082
79947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1708279947
Directory /workspace/30.usbdev_pkt_received/latest


Test location /workspace/coverage/default/30.usbdev_pkt_sent.1003770553
Short name T1074
Test name
Test status
Simulation time 8419512114 ps
CPU time 9.67 seconds
Started Apr 21 04:02:37 PM PDT 24
Finished Apr 21 04:02:47 PM PDT 24
Peak memory 203420 kb
Host smart-745bd9f3-d216-4850-af9a-05ba71875715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10037
70553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.1003770553
Directory /workspace/30.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.2369202770
Short name T676
Test name
Test status
Simulation time 8400186566 ps
CPU time 10.02 seconds
Started Apr 21 04:02:36 PM PDT 24
Finished Apr 21 04:02:46 PM PDT 24
Peak memory 204016 kb
Host smart-bca31ad8-bf97-41b4-ab7e-88fedbad6404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23692
02770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.2369202770
Directory /workspace/30.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/30.usbdev_setup_stage.1329769511
Short name T897
Test name
Test status
Simulation time 8385918824 ps
CPU time 7.83 seconds
Started Apr 21 04:02:41 PM PDT 24
Finished Apr 21 04:02:49 PM PDT 24
Peak memory 204036 kb
Host smart-2d6dd6a8-b5c3-48cf-b50b-f38373412302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13297
69511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.1329769511
Directory /workspace/30.usbdev_setup_stage/latest


Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.2018001328
Short name T576
Test name
Test status
Simulation time 8378499653 ps
CPU time 7.92 seconds
Started Apr 21 04:02:38 PM PDT 24
Finished Apr 21 04:02:46 PM PDT 24
Peak memory 204056 kb
Host smart-f7d08490-0ad2-442f-a755-03a9b0c95127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20180
01328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.2018001328
Directory /workspace/30.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/30.usbdev_smoke.2959918321
Short name T978
Test name
Test status
Simulation time 8473689587 ps
CPU time 8.22 seconds
Started Apr 21 04:02:34 PM PDT 24
Finished Apr 21 04:02:42 PM PDT 24
Peak memory 204060 kb
Host smart-b2350896-16bb-4674-9d1c-e3c144b7aab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29599
18321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2959918321
Directory /workspace/30.usbdev_smoke/latest


Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.4023331158
Short name T839
Test name
Test status
Simulation time 8385263282 ps
CPU time 8.13 seconds
Started Apr 21 04:02:37 PM PDT 24
Finished Apr 21 04:02:46 PM PDT 24
Peak memory 204076 kb
Host smart-e629c51b-3195-4b0f-9c9d-f00368cc8961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40233
31158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.4023331158
Directory /workspace/30.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/30.usbdev_stall_trans.2962187428
Short name T771
Test name
Test status
Simulation time 8409784190 ps
CPU time 7.81 seconds
Started Apr 21 04:02:39 PM PDT 24
Finished Apr 21 04:02:47 PM PDT 24
Peak memory 204064 kb
Host smart-9b6d716b-7099-46fb-a51a-3c4156985fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29621
87428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.2962187428
Directory /workspace/30.usbdev_stall_trans/latest


Test location /workspace/coverage/default/31.max_length_in_transaction.2442992574
Short name T527
Test name
Test status
Simulation time 8464651143 ps
CPU time 9.21 seconds
Started Apr 21 04:02:51 PM PDT 24
Finished Apr 21 04:03:00 PM PDT 24
Peak memory 204084 kb
Host smart-34fef3a9-d3b5-453b-9c3d-8637e17ba4fc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2442992574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.2442992574
Directory /workspace/31.max_length_in_transaction/latest


Test location /workspace/coverage/default/31.min_length_in_transaction.2240320185
Short name T39
Test name
Test status
Simulation time 8379873251 ps
CPU time 7.74 seconds
Started Apr 21 04:02:49 PM PDT 24
Finished Apr 21 04:02:57 PM PDT 24
Peak memory 204060 kb
Host smart-a4c3d7cc-8446-4406-af40-722d95f0ff8a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2240320185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.2240320185
Directory /workspace/31.min_length_in_transaction/latest


Test location /workspace/coverage/default/31.random_length_in_trans.4222308517
Short name T415
Test name
Test status
Simulation time 8395055980 ps
CPU time 7.4 seconds
Started Apr 21 04:02:47 PM PDT 24
Finished Apr 21 04:02:55 PM PDT 24
Peak memory 204052 kb
Host smart-5d848741-4032-4e5e-9536-02885ab69679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42223
08517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.4222308517
Directory /workspace/31.random_length_in_trans/latest


Test location /workspace/coverage/default/31.usbdev_av_buffer.3464713338
Short name T309
Test name
Test status
Simulation time 8440888840 ps
CPU time 10.62 seconds
Started Apr 21 04:02:43 PM PDT 24
Finished Apr 21 04:02:54 PM PDT 24
Peak memory 204048 kb
Host smart-efef5dac-c6ff-4b12-a5c3-ed9547b4376c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34647
13338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.3464713338
Directory /workspace/31.usbdev_av_buffer/latest


Test location /workspace/coverage/default/31.usbdev_enable.3854421061
Short name T283
Test name
Test status
Simulation time 8378354261 ps
CPU time 9.11 seconds
Started Apr 21 04:02:42 PM PDT 24
Finished Apr 21 04:02:51 PM PDT 24
Peak memory 204036 kb
Host smart-c3925bf0-e709-46ce-a1b5-3c860cba3acd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38544
21061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.3854421061
Directory /workspace/31.usbdev_enable/latest


Test location /workspace/coverage/default/31.usbdev_fifo_rst.1673438570
Short name T331
Test name
Test status
Simulation time 96469883 ps
CPU time 1.24 seconds
Started Apr 21 04:02:43 PM PDT 24
Finished Apr 21 04:02:44 PM PDT 24
Peak memory 204204 kb
Host smart-17cfec1d-e845-40c9-9141-6dcb5f82e58c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16734
38570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.1673438570
Directory /workspace/31.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/31.usbdev_in_iso.897378125
Short name T550
Test name
Test status
Simulation time 8436415107 ps
CPU time 8.81 seconds
Started Apr 21 04:02:48 PM PDT 24
Finished Apr 21 04:02:57 PM PDT 24
Peak memory 204064 kb
Host smart-b4699da0-21d7-49ea-9a14-ef0ad86de837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89737
8125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.897378125
Directory /workspace/31.usbdev_in_iso/latest


Test location /workspace/coverage/default/31.usbdev_in_stall.2141952379
Short name T1072
Test name
Test status
Simulation time 8393116344 ps
CPU time 8.89 seconds
Started Apr 21 04:02:54 PM PDT 24
Finished Apr 21 04:03:03 PM PDT 24
Peak memory 204220 kb
Host smart-955042da-b70e-4e6c-bae0-62d92ed3351d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21419
52379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.2141952379
Directory /workspace/31.usbdev_in_stall/latest


Test location /workspace/coverage/default/31.usbdev_in_trans.1417626109
Short name T1254
Test name
Test status
Simulation time 8434165378 ps
CPU time 8.27 seconds
Started Apr 21 04:02:39 PM PDT 24
Finished Apr 21 04:02:48 PM PDT 24
Peak memory 203964 kb
Host smart-5dc306f9-3a3c-4621-8aec-125022345d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14176
26109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.1417626109
Directory /workspace/31.usbdev_in_trans/latest


Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.816171558
Short name T388
Test name
Test status
Simulation time 8415953872 ps
CPU time 8.06 seconds
Started Apr 21 04:02:42 PM PDT 24
Finished Apr 21 04:02:50 PM PDT 24
Peak memory 204060 kb
Host smart-d6fa72c2-705f-4a4f-840e-c37e51623a18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81617
1558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.816171558
Directory /workspace/31.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1093812529
Short name T356
Test name
Test status
Simulation time 8373768819 ps
CPU time 8.18 seconds
Started Apr 21 04:02:43 PM PDT 24
Finished Apr 21 04:02:52 PM PDT 24
Peak memory 204032 kb
Host smart-89a7b93b-4830-4025-91d5-215056281a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10938
12529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1093812529
Directory /workspace/31.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/31.usbdev_nak_trans.1077671113
Short name T124
Test name
Test status
Simulation time 8429505224 ps
CPU time 7.85 seconds
Started Apr 21 04:02:45 PM PDT 24
Finished Apr 21 04:02:53 PM PDT 24
Peak memory 204064 kb
Host smart-67e018c6-1f13-4a0e-a83a-0398140f672a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10776
71113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.1077671113
Directory /workspace/31.usbdev_nak_trans/latest


Test location /workspace/coverage/default/31.usbdev_out_stall.600074771
Short name T334
Test name
Test status
Simulation time 8415321783 ps
CPU time 8.84 seconds
Started Apr 21 04:02:45 PM PDT 24
Finished Apr 21 04:02:54 PM PDT 24
Peak memory 204048 kb
Host smart-baa01f4e-6192-41d3-8e44-004ad94a87fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60007
4771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.600074771
Directory /workspace/31.usbdev_out_stall/latest


Test location /workspace/coverage/default/31.usbdev_out_trans_nak.1141548319
Short name T568
Test name
Test status
Simulation time 8387333025 ps
CPU time 7.81 seconds
Started Apr 21 04:02:44 PM PDT 24
Finished Apr 21 04:02:52 PM PDT 24
Peak memory 204032 kb
Host smart-777aae6b-417f-40d4-bde4-8d953456c01f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11415
48319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1141548319
Directory /workspace/31.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/31.usbdev_pending_in_trans.1004815560
Short name T818
Test name
Test status
Simulation time 8391988785 ps
CPU time 7.86 seconds
Started Apr 21 04:02:49 PM PDT 24
Finished Apr 21 04:02:57 PM PDT 24
Peak memory 204064 kb
Host smart-900639ff-aac8-4223-ac72-d4939371e979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10048
15560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.1004815560
Directory /workspace/31.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.1303330056
Short name T444
Test name
Test status
Simulation time 8423552268 ps
CPU time 8.04 seconds
Started Apr 21 04:02:50 PM PDT 24
Finished Apr 21 04:02:59 PM PDT 24
Peak memory 204036 kb
Host smart-4980fb64-d826-49c3-b1c6-85a29abe3aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13033
30056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.1303330056
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.757060506
Short name T45
Test name
Test status
Simulation time 173546740 ps
CPU time 0.78 seconds
Started Apr 21 04:02:48 PM PDT 24
Finished Apr 21 04:02:49 PM PDT 24
Peak memory 203900 kb
Host smart-fc30e19c-4ff2-461d-9a1b-c5ef2bf52d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75706
0506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.757060506
Directory /workspace/31.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/31.usbdev_pkt_buffer.110013597
Short name T210
Test name
Test status
Simulation time 19346958263 ps
CPU time 40.29 seconds
Started Apr 21 04:02:43 PM PDT 24
Finished Apr 21 04:03:23 PM PDT 24
Peak memory 204296 kb
Host smart-0e99d86f-3ebc-4571-9bf1-6701a2412ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11001
3597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.110013597
Directory /workspace/31.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/31.usbdev_pkt_received.4146762267
Short name T417
Test name
Test status
Simulation time 8422719559 ps
CPU time 10.06 seconds
Started Apr 21 04:02:46 PM PDT 24
Finished Apr 21 04:02:56 PM PDT 24
Peak memory 204032 kb
Host smart-50576dba-9496-46da-8ffe-c47430706a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41467
62267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.4146762267
Directory /workspace/31.usbdev_pkt_received/latest


Test location /workspace/coverage/default/31.usbdev_pkt_sent.367081875
Short name T603
Test name
Test status
Simulation time 8444175528 ps
CPU time 8.59 seconds
Started Apr 21 04:02:43 PM PDT 24
Finished Apr 21 04:02:52 PM PDT 24
Peak memory 204068 kb
Host smart-52174856-f4a0-4063-8dea-5d26ea8e8d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36708
1875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.367081875
Directory /workspace/31.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.141110110
Short name T1370
Test name
Test status
Simulation time 8424137054 ps
CPU time 7.72 seconds
Started Apr 21 04:02:44 PM PDT 24
Finished Apr 21 04:02:52 PM PDT 24
Peak memory 203996 kb
Host smart-6277677e-3522-4f15-b247-a1d29691a360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14111
0110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.141110110
Directory /workspace/31.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/31.usbdev_setup_stage.770447967
Short name T1306
Test name
Test status
Simulation time 8401298565 ps
CPU time 8.35 seconds
Started Apr 21 04:02:48 PM PDT 24
Finished Apr 21 04:02:57 PM PDT 24
Peak memory 204040 kb
Host smart-0bc7b54f-cc5f-4687-8ec1-35e1bf56b56e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77044
7967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.770447967
Directory /workspace/31.usbdev_setup_stage/latest


Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.4127511148
Short name T529
Test name
Test status
Simulation time 8367145040 ps
CPU time 10.11 seconds
Started Apr 21 04:02:47 PM PDT 24
Finished Apr 21 04:02:58 PM PDT 24
Peak memory 204040 kb
Host smart-bf66f82b-e9ff-4fd2-a49d-df224a3ccbab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41275
11148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.4127511148
Directory /workspace/31.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/31.usbdev_smoke.2058809274
Short name T1315
Test name
Test status
Simulation time 8463352099 ps
CPU time 9.12 seconds
Started Apr 21 04:02:43 PM PDT 24
Finished Apr 21 04:02:53 PM PDT 24
Peak memory 204068 kb
Host smart-1189a3ee-f593-4702-be28-d040e25b13f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20588
09274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2058809274
Directory /workspace/31.usbdev_smoke/latest


Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.3845497228
Short name T566
Test name
Test status
Simulation time 8380119673 ps
CPU time 9.31 seconds
Started Apr 21 04:02:48 PM PDT 24
Finished Apr 21 04:02:58 PM PDT 24
Peak memory 204016 kb
Host smart-0eb04233-39b2-412b-bb21-e5ff0e2071c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38454
97228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.3845497228
Directory /workspace/31.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/31.usbdev_stall_trans.1640557098
Short name T775
Test name
Test status
Simulation time 8420620573 ps
CPU time 8.2 seconds
Started Apr 21 04:02:48 PM PDT 24
Finished Apr 21 04:02:56 PM PDT 24
Peak memory 204032 kb
Host smart-8cda0272-c012-4491-bee7-12a1679ae19e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16405
57098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1640557098
Directory /workspace/31.usbdev_stall_trans/latest


Test location /workspace/coverage/default/32.max_length_in_transaction.1334910137
Short name T48
Test name
Test status
Simulation time 8465509754 ps
CPU time 7.83 seconds
Started Apr 21 04:02:59 PM PDT 24
Finished Apr 21 04:03:07 PM PDT 24
Peak memory 203932 kb
Host smart-3e715b47-18ca-45f6-bb95-b817060b1f0a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1334910137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.1334910137
Directory /workspace/32.max_length_in_transaction/latest


Test location /workspace/coverage/default/32.min_length_in_transaction.794994451
Short name T693
Test name
Test status
Simulation time 8397984352 ps
CPU time 8.15 seconds
Started Apr 21 04:02:58 PM PDT 24
Finished Apr 21 04:03:07 PM PDT 24
Peak memory 204036 kb
Host smart-33db1444-2c84-4ba4-8b95-472f41ff928a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=794994451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.794994451
Directory /workspace/32.min_length_in_transaction/latest


Test location /workspace/coverage/default/32.random_length_in_trans.2818267320
Short name T463
Test name
Test status
Simulation time 8446427425 ps
CPU time 8.5 seconds
Started Apr 21 04:02:59 PM PDT 24
Finished Apr 21 04:03:08 PM PDT 24
Peak memory 204068 kb
Host smart-5ead1fea-0383-4324-90b0-96dbfea5bdab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28182
67320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.2818267320
Directory /workspace/32.random_length_in_trans/latest


Test location /workspace/coverage/default/32.usbdev_av_buffer.1094357695
Short name T448
Test name
Test status
Simulation time 8393732406 ps
CPU time 8.56 seconds
Started Apr 21 04:02:51 PM PDT 24
Finished Apr 21 04:03:00 PM PDT 24
Peak memory 204072 kb
Host smart-3a8e56a1-75bb-47c8-8179-894b1683375a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10943
57695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.1094357695
Directory /workspace/32.usbdev_av_buffer/latest


Test location /workspace/coverage/default/32.usbdev_enable.359305590
Short name T1217
Test name
Test status
Simulation time 8388149852 ps
CPU time 7.63 seconds
Started Apr 21 04:02:50 PM PDT 24
Finished Apr 21 04:02:58 PM PDT 24
Peak memory 204028 kb
Host smart-bce1f8bb-3d92-46ab-b3d6-f7a65d058b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35930
5590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.359305590
Directory /workspace/32.usbdev_enable/latest


Test location /workspace/coverage/default/32.usbdev_fifo_rst.3181503257
Short name T596
Test name
Test status
Simulation time 246236174 ps
CPU time 2.06 seconds
Started Apr 21 04:02:54 PM PDT 24
Finished Apr 21 04:02:56 PM PDT 24
Peak memory 204172 kb
Host smart-4736aee6-3fdc-42b2-9190-de9f422a4aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31815
03257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3181503257
Directory /workspace/32.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/32.usbdev_in_iso.825745579
Short name T1323
Test name
Test status
Simulation time 8489214133 ps
CPU time 8.24 seconds
Started Apr 21 04:02:59 PM PDT 24
Finished Apr 21 04:03:08 PM PDT 24
Peak memory 204072 kb
Host smart-c46b50fc-c121-49e4-bfaf-69e3db3b3efc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82574
5579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.825745579
Directory /workspace/32.usbdev_in_iso/latest


Test location /workspace/coverage/default/32.usbdev_in_stall.2988202224
Short name T192
Test name
Test status
Simulation time 8365131496 ps
CPU time 8.21 seconds
Started Apr 21 04:03:00 PM PDT 24
Finished Apr 21 04:03:09 PM PDT 24
Peak memory 204080 kb
Host smart-728bcd19-35c1-470d-af10-9deff3afa605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29882
02224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.2988202224
Directory /workspace/32.usbdev_in_stall/latest


Test location /workspace/coverage/default/32.usbdev_in_trans.2862161011
Short name T886
Test name
Test status
Simulation time 8463741741 ps
CPU time 8.86 seconds
Started Apr 21 04:02:51 PM PDT 24
Finished Apr 21 04:03:00 PM PDT 24
Peak memory 204060 kb
Host smart-0160b3f9-b543-4c27-b40e-728f363ab580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28621
61011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2862161011
Directory /workspace/32.usbdev_in_trans/latest


Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.295132800
Short name T1224
Test name
Test status
Simulation time 8421909380 ps
CPU time 8.45 seconds
Started Apr 21 04:02:55 PM PDT 24
Finished Apr 21 04:03:03 PM PDT 24
Peak memory 204048 kb
Host smart-a763585d-f29c-43ca-ba29-6dfaa45348ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29513
2800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.295132800
Directory /workspace/32.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.1989938428
Short name T973
Test name
Test status
Simulation time 8370126463 ps
CPU time 9.71 seconds
Started Apr 21 04:02:51 PM PDT 24
Finished Apr 21 04:03:01 PM PDT 24
Peak memory 204008 kb
Host smart-b93a47de-962c-4b9b-9a7b-4ac79bc4a85b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19899
38428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.1989938428
Directory /workspace/32.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/32.usbdev_nak_trans.3085445988
Short name T121
Test name
Test status
Simulation time 8421730322 ps
CPU time 7.9 seconds
Started Apr 21 04:02:53 PM PDT 24
Finished Apr 21 04:03:01 PM PDT 24
Peak memory 204064 kb
Host smart-c9a27bca-7403-4d96-83c0-6191fbfeb3dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30854
45988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.3085445988
Directory /workspace/32.usbdev_nak_trans/latest


Test location /workspace/coverage/default/32.usbdev_out_stall.1315231457
Short name T324
Test name
Test status
Simulation time 8382647653 ps
CPU time 7.71 seconds
Started Apr 21 04:02:52 PM PDT 24
Finished Apr 21 04:03:00 PM PDT 24
Peak memory 204072 kb
Host smart-18fd77d4-2647-4fef-a85f-5640284ae5cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13152
31457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1315231457
Directory /workspace/32.usbdev_out_stall/latest


Test location /workspace/coverage/default/32.usbdev_out_trans_nak.709789740
Short name T544
Test name
Test status
Simulation time 8414535048 ps
CPU time 8.49 seconds
Started Apr 21 04:02:53 PM PDT 24
Finished Apr 21 04:03:01 PM PDT 24
Peak memory 204028 kb
Host smart-02473b2d-9eb6-406f-a62b-9c024a4192ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70978
9740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.709789740
Directory /workspace/32.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/32.usbdev_pending_in_trans.650065474
Short name T173
Test name
Test status
Simulation time 8402670059 ps
CPU time 8.01 seconds
Started Apr 21 04:02:59 PM PDT 24
Finished Apr 21 04:03:07 PM PDT 24
Peak memory 204064 kb
Host smart-bdb29031-c4b9-4be5-82f9-de2ded1a6e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65006
5474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.650065474
Directory /workspace/32.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.3293583707
Short name T325
Test name
Test status
Simulation time 8375024560 ps
CPU time 7.71 seconds
Started Apr 21 04:02:55 PM PDT 24
Finished Apr 21 04:03:03 PM PDT 24
Peak memory 204044 kb
Host smart-bcb91b8f-932e-4e5d-a81c-50194c36f019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32935
83707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.3293583707
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.3044567725
Short name T1309
Test name
Test status
Simulation time 70145065 ps
CPU time 0.7 seconds
Started Apr 21 04:03:03 PM PDT 24
Finished Apr 21 04:03:04 PM PDT 24
Peak memory 203808 kb
Host smart-c4b4400b-e576-46fa-a811-0cfded46c80b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30445
67725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.3044567725
Directory /workspace/32.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/32.usbdev_pkt_buffer.1302514249
Short name T96
Test name
Test status
Simulation time 21484248358 ps
CPU time 43.83 seconds
Started Apr 21 04:02:53 PM PDT 24
Finished Apr 21 04:03:37 PM PDT 24
Peak memory 204340 kb
Host smart-9b01ba0b-3dfb-4bdc-8727-f243055badb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13025
14249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1302514249
Directory /workspace/32.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/32.usbdev_pkt_received.3418981418
Short name T87
Test name
Test status
Simulation time 8411494106 ps
CPU time 7.56 seconds
Started Apr 21 04:02:53 PM PDT 24
Finished Apr 21 04:03:01 PM PDT 24
Peak memory 204064 kb
Host smart-c883c7e3-3c4e-4b52-855b-e251c1d173b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34189
81418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3418981418
Directory /workspace/32.usbdev_pkt_received/latest


Test location /workspace/coverage/default/32.usbdev_pkt_sent.1948338119
Short name T1382
Test name
Test status
Simulation time 8460469166 ps
CPU time 9.11 seconds
Started Apr 21 04:02:53 PM PDT 24
Finished Apr 21 04:03:02 PM PDT 24
Peak memory 204036 kb
Host smart-fb8531af-67bf-4638-8e6f-704eb56409fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19483
38119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.1948338119
Directory /workspace/32.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.1378419673
Short name T1269
Test name
Test status
Simulation time 8436133721 ps
CPU time 7.78 seconds
Started Apr 21 04:02:56 PM PDT 24
Finished Apr 21 04:03:04 PM PDT 24
Peak memory 204052 kb
Host smart-f78982c2-a294-4816-8ef2-09eaf76ede2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13784
19673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.1378419673
Directory /workspace/32.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/32.usbdev_setup_stage.614268883
Short name T725
Test name
Test status
Simulation time 8383841196 ps
CPU time 9.33 seconds
Started Apr 21 04:02:59 PM PDT 24
Finished Apr 21 04:03:09 PM PDT 24
Peak memory 204044 kb
Host smart-84aecaa9-1d60-42c3-89b8-b6b7f64e690f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61426
8883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.614268883
Directory /workspace/32.usbdev_setup_stage/latest


Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.1558311956
Short name T979
Test name
Test status
Simulation time 8368602245 ps
CPU time 9.42 seconds
Started Apr 21 04:02:54 PM PDT 24
Finished Apr 21 04:03:04 PM PDT 24
Peak memory 203988 kb
Host smart-c85a9f0b-58f4-43f7-8427-58e232bdf0c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15583
11956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1558311956
Directory /workspace/32.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/32.usbdev_smoke.770118811
Short name T1032
Test name
Test status
Simulation time 8430711350 ps
CPU time 8.35 seconds
Started Apr 21 04:02:50 PM PDT 24
Finished Apr 21 04:02:59 PM PDT 24
Peak memory 204068 kb
Host smart-ad9b6601-4a33-4bfd-a259-25e0cb08ea57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77011
8811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.770118811
Directory /workspace/32.usbdev_smoke/latest


Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.3553512932
Short name T959
Test name
Test status
Simulation time 8468473403 ps
CPU time 7.89 seconds
Started Apr 21 04:02:55 PM PDT 24
Finished Apr 21 04:03:03 PM PDT 24
Peak memory 204056 kb
Host smart-abe12803-2308-4f1e-9645-d0b254965327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35535
12932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.3553512932
Directory /workspace/32.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/32.usbdev_stall_trans.997462995
Short name T932
Test name
Test status
Simulation time 8393412173 ps
CPU time 8.49 seconds
Started Apr 21 04:02:57 PM PDT 24
Finished Apr 21 04:03:06 PM PDT 24
Peak memory 204044 kb
Host smart-ea77ffc0-34dd-49ba-a927-105c70c69175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99746
2995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.997462995
Directory /workspace/32.usbdev_stall_trans/latest


Test location /workspace/coverage/default/33.max_length_in_transaction.1748502808
Short name T393
Test name
Test status
Simulation time 8467149166 ps
CPU time 9.08 seconds
Started Apr 21 04:03:10 PM PDT 24
Finished Apr 21 04:03:19 PM PDT 24
Peak memory 204044 kb
Host smart-58c3582c-e396-4e12-b5df-6c1494e5ae69
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1748502808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.1748502808
Directory /workspace/33.max_length_in_transaction/latest


Test location /workspace/coverage/default/33.min_length_in_transaction.789149112
Short name T723
Test name
Test status
Simulation time 8389196064 ps
CPU time 8.01 seconds
Started Apr 21 04:03:07 PM PDT 24
Finished Apr 21 04:03:16 PM PDT 24
Peak memory 204068 kb
Host smart-0f579854-3d00-4411-934a-ebf8fa6c960c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=789149112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.789149112
Directory /workspace/33.min_length_in_transaction/latest


Test location /workspace/coverage/default/33.random_length_in_trans.445702643
Short name T1359
Test name
Test status
Simulation time 8433253605 ps
CPU time 8.07 seconds
Started Apr 21 04:03:07 PM PDT 24
Finished Apr 21 04:03:15 PM PDT 24
Peak memory 204024 kb
Host smart-18e96528-1664-490a-96f8-9f34f8ded60b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44570
2643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.445702643
Directory /workspace/33.random_length_in_trans/latest


Test location /workspace/coverage/default/33.usbdev_av_buffer.1858089155
Short name T1116
Test name
Test status
Simulation time 8377847707 ps
CPU time 7.77 seconds
Started Apr 21 04:03:01 PM PDT 24
Finished Apr 21 04:03:09 PM PDT 24
Peak memory 204088 kb
Host smart-f4c99037-b99b-4967-bdde-60b37fc46f27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18580
89155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1858089155
Directory /workspace/33.usbdev_av_buffer/latest


Test location /workspace/coverage/default/33.usbdev_enable.349957620
Short name T724
Test name
Test status
Simulation time 8380505671 ps
CPU time 9.68 seconds
Started Apr 21 04:03:02 PM PDT 24
Finished Apr 21 04:03:12 PM PDT 24
Peak memory 204068 kb
Host smart-1c39da2b-d588-44ac-8634-f98918290122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34995
7620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.349957620
Directory /workspace/33.usbdev_enable/latest


Test location /workspace/coverage/default/33.usbdev_fifo_rst.3487012164
Short name T1127
Test name
Test status
Simulation time 259912337 ps
CPU time 2.28 seconds
Started Apr 21 04:03:02 PM PDT 24
Finished Apr 21 04:03:05 PM PDT 24
Peak memory 204136 kb
Host smart-880887cc-167e-4dab-8f5b-35bdae26658d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34870
12164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3487012164
Directory /workspace/33.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/33.usbdev_in_iso.1454070274
Short name T413
Test name
Test status
Simulation time 8391340533 ps
CPU time 7.88 seconds
Started Apr 21 04:03:07 PM PDT 24
Finished Apr 21 04:03:15 PM PDT 24
Peak memory 204064 kb
Host smart-6bfe3326-3867-407f-a2f8-d9b570f88e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14540
70274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.1454070274
Directory /workspace/33.usbdev_in_iso/latest


Test location /workspace/coverage/default/33.usbdev_in_stall.649220924
Short name T6
Test name
Test status
Simulation time 8364688643 ps
CPU time 8.77 seconds
Started Apr 21 04:03:08 PM PDT 24
Finished Apr 21 04:03:17 PM PDT 24
Peak memory 204060 kb
Host smart-3ec50f8a-ba3f-4ed0-bccb-ccc804af7e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64922
0924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.649220924
Directory /workspace/33.usbdev_in_stall/latest


Test location /workspace/coverage/default/33.usbdev_in_trans.4243643333
Short name T519
Test name
Test status
Simulation time 8435915872 ps
CPU time 7.68 seconds
Started Apr 21 04:03:03 PM PDT 24
Finished Apr 21 04:03:11 PM PDT 24
Peak memory 204064 kb
Host smart-155949fc-f7bd-4c77-8930-6eee69b9e420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42436
43333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.4243643333
Directory /workspace/33.usbdev_in_trans/latest


Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1929580925
Short name T1051
Test name
Test status
Simulation time 8412240833 ps
CPU time 8.08 seconds
Started Apr 21 04:03:09 PM PDT 24
Finished Apr 21 04:03:17 PM PDT 24
Peak memory 204048 kb
Host smart-98f60859-b4d5-437c-8af2-d645f993343b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19295
80925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1929580925
Directory /workspace/33.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.2705642061
Short name T279
Test name
Test status
Simulation time 8392361280 ps
CPU time 8.75 seconds
Started Apr 21 04:03:04 PM PDT 24
Finished Apr 21 04:03:13 PM PDT 24
Peak memory 204024 kb
Host smart-be52f441-1b36-4f5c-85b0-03ff9ea496f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27056
42061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.2705642061
Directory /workspace/33.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/33.usbdev_nak_trans.2256761765
Short name T1118
Test name
Test status
Simulation time 8445385127 ps
CPU time 8.88 seconds
Started Apr 21 04:03:12 PM PDT 24
Finished Apr 21 04:03:22 PM PDT 24
Peak memory 204032 kb
Host smart-469ea013-263b-4656-8a8c-5b7213c3bb68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22567
61765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.2256761765
Directory /workspace/33.usbdev_nak_trans/latest


Test location /workspace/coverage/default/33.usbdev_out_stall.3377720547
Short name T552
Test name
Test status
Simulation time 8387028830 ps
CPU time 9.01 seconds
Started Apr 21 04:03:12 PM PDT 24
Finished Apr 21 04:03:21 PM PDT 24
Peak memory 204028 kb
Host smart-38d2baca-7ff2-4fd8-a1b9-6a1437bccc5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33777
20547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3377720547
Directory /workspace/33.usbdev_out_stall/latest


Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2426931588
Short name T727
Test name
Test status
Simulation time 8416555357 ps
CPU time 7.9 seconds
Started Apr 21 04:03:03 PM PDT 24
Finished Apr 21 04:03:12 PM PDT 24
Peak memory 204084 kb
Host smart-089de263-541e-4df5-884a-882d9a9e110e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24269
31588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2426931588
Directory /workspace/33.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/33.usbdev_pending_in_trans.1878639265
Short name T198
Test name
Test status
Simulation time 8385821614 ps
CPU time 8.71 seconds
Started Apr 21 04:03:09 PM PDT 24
Finished Apr 21 04:03:18 PM PDT 24
Peak memory 204064 kb
Host smart-08dc1add-ff48-48d7-8b4a-96c8a2d675aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18786
39265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.1878639265
Directory /workspace/33.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.3982465644
Short name T432
Test name
Test status
Simulation time 8391086077 ps
CPU time 8.12 seconds
Started Apr 21 04:03:03 PM PDT 24
Finished Apr 21 04:03:11 PM PDT 24
Peak memory 204016 kb
Host smart-8eb41dd1-a3ae-42e0-9bb5-10a3c6d95045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39824
65644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.3982465644
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.2865282048
Short name T1153
Test name
Test status
Simulation time 230525122 ps
CPU time 0.84 seconds
Started Apr 21 04:03:07 PM PDT 24
Finished Apr 21 04:03:08 PM PDT 24
Peak memory 203920 kb
Host smart-c286a805-cbc6-4063-94fc-c8927fa5b4cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28652
82048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.2865282048
Directory /workspace/33.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/33.usbdev_pkt_buffer.2811668516
Short name T1176
Test name
Test status
Simulation time 14490086559 ps
CPU time 25.8 seconds
Started Apr 21 04:03:05 PM PDT 24
Finished Apr 21 04:03:31 PM PDT 24
Peak memory 204332 kb
Host smart-ad193900-3a6b-4e8b-a423-34286bb2f44a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28116
68516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.2811668516
Directory /workspace/33.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/33.usbdev_pkt_received.564825632
Short name T406
Test name
Test status
Simulation time 8376645209 ps
CPU time 9.13 seconds
Started Apr 21 04:03:09 PM PDT 24
Finished Apr 21 04:03:18 PM PDT 24
Peak memory 204048 kb
Host smart-1ef92cfd-1af1-4e3d-88cb-c171ad05fd33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56482
5632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.564825632
Directory /workspace/33.usbdev_pkt_received/latest


Test location /workspace/coverage/default/33.usbdev_pkt_sent.326110861
Short name T823
Test name
Test status
Simulation time 8488056271 ps
CPU time 8.03 seconds
Started Apr 21 04:03:12 PM PDT 24
Finished Apr 21 04:03:21 PM PDT 24
Peak memory 204032 kb
Host smart-b226e709-3376-43b2-a358-7a84b3101c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32611
0861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.326110861
Directory /workspace/33.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.32637813
Short name T472
Test name
Test status
Simulation time 8389608820 ps
CPU time 8.07 seconds
Started Apr 21 04:03:12 PM PDT 24
Finished Apr 21 04:03:20 PM PDT 24
Peak memory 204032 kb
Host smart-48c55b17-5e04-4e02-9b72-3b39b0b970c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32637
813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.32637813
Directory /workspace/33.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/33.usbdev_setup_stage.865702282
Short name T835
Test name
Test status
Simulation time 8377186861 ps
CPU time 8.17 seconds
Started Apr 21 04:03:04 PM PDT 24
Finished Apr 21 04:03:13 PM PDT 24
Peak memory 204068 kb
Host smart-85fe694a-07db-4aa9-ba49-dd024f21042d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86570
2282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.865702282
Directory /workspace/33.usbdev_setup_stage/latest


Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.1577005016
Short name T341
Test name
Test status
Simulation time 8373324833 ps
CPU time 8.95 seconds
Started Apr 21 04:03:09 PM PDT 24
Finished Apr 21 04:03:18 PM PDT 24
Peak memory 204040 kb
Host smart-8c8a9f67-281a-4794-bd4b-1abe625251ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15770
05016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.1577005016
Directory /workspace/33.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/33.usbdev_smoke.1679330097
Short name T1297
Test name
Test status
Simulation time 8491711339 ps
CPU time 10.51 seconds
Started Apr 21 04:03:01 PM PDT 24
Finished Apr 21 04:03:12 PM PDT 24
Peak memory 204064 kb
Host smart-17bc5a35-4980-4d51-b34d-fea138d87901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16793
30097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1679330097
Directory /workspace/33.usbdev_smoke/latest


Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.2311831565
Short name T289
Test name
Test status
Simulation time 8364802280 ps
CPU time 8.12 seconds
Started Apr 21 04:03:09 PM PDT 24
Finished Apr 21 04:03:18 PM PDT 24
Peak memory 204036 kb
Host smart-35a97ea8-e334-4db0-ac98-cdddcaed6561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23118
31565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.2311831565
Directory /workspace/33.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/33.usbdev_stall_trans.581389580
Short name T304
Test name
Test status
Simulation time 8418121235 ps
CPU time 8.24 seconds
Started Apr 21 04:03:12 PM PDT 24
Finished Apr 21 04:03:21 PM PDT 24
Peak memory 204032 kb
Host smart-d2e09a79-577f-4a33-983f-30d5b61c6cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58138
9580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.581389580
Directory /workspace/33.usbdev_stall_trans/latest


Test location /workspace/coverage/default/34.max_length_in_transaction.1121063681
Short name T1274
Test name
Test status
Simulation time 8508084296 ps
CPU time 7.84 seconds
Started Apr 21 04:03:17 PM PDT 24
Finished Apr 21 04:03:26 PM PDT 24
Peak memory 204056 kb
Host smart-93fdef2e-9fc2-47db-b4e4-43aad4609d94
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1121063681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.1121063681
Directory /workspace/34.max_length_in_transaction/latest


Test location /workspace/coverage/default/34.min_length_in_transaction.2859842730
Short name T397
Test name
Test status
Simulation time 8374197238 ps
CPU time 9.39 seconds
Started Apr 21 04:03:17 PM PDT 24
Finished Apr 21 04:03:27 PM PDT 24
Peak memory 204044 kb
Host smart-ce89964f-06a2-4dba-99c8-5cbf425e18c2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2859842730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.2859842730
Directory /workspace/34.min_length_in_transaction/latest


Test location /workspace/coverage/default/34.random_length_in_trans.965105684
Short name T306
Test name
Test status
Simulation time 8390272525 ps
CPU time 7.56 seconds
Started Apr 21 04:03:17 PM PDT 24
Finished Apr 21 04:03:25 PM PDT 24
Peak memory 204040 kb
Host smart-7a2c3a57-29bf-4877-b7f1-894b10f8ebb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96510
5684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.965105684
Directory /workspace/34.random_length_in_trans/latest


Test location /workspace/coverage/default/34.usbdev_av_buffer.2699976999
Short name T1015
Test name
Test status
Simulation time 8375805208 ps
CPU time 9.83 seconds
Started Apr 21 04:03:13 PM PDT 24
Finished Apr 21 04:03:23 PM PDT 24
Peak memory 204032 kb
Host smart-5095900d-0904-4218-a1cd-c8376149acab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26999
76999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2699976999
Directory /workspace/34.usbdev_av_buffer/latest


Test location /workspace/coverage/default/34.usbdev_enable.2225360730
Short name T921
Test name
Test status
Simulation time 8406458095 ps
CPU time 8.42 seconds
Started Apr 21 04:03:08 PM PDT 24
Finished Apr 21 04:03:16 PM PDT 24
Peak memory 204024 kb
Host smart-84d33435-e2d4-476c-9745-dfcab8401b10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22253
60730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.2225360730
Directory /workspace/34.usbdev_enable/latest


Test location /workspace/coverage/default/34.usbdev_fifo_rst.1235173663
Short name T588
Test name
Test status
Simulation time 55205211 ps
CPU time 1.39 seconds
Started Apr 21 04:03:11 PM PDT 24
Finished Apr 21 04:03:13 PM PDT 24
Peak memory 204156 kb
Host smart-245e8055-160d-4b0d-a64f-56f9a920aaa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12351
73663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.1235173663
Directory /workspace/34.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/34.usbdev_in_iso.3707845791
Short name T575
Test name
Test status
Simulation time 8477243202 ps
CPU time 8.44 seconds
Started Apr 21 04:03:18 PM PDT 24
Finished Apr 21 04:03:27 PM PDT 24
Peak memory 204056 kb
Host smart-0ffda2c7-85aa-46da-af70-41c64253c393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37078
45791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.3707845791
Directory /workspace/34.usbdev_in_iso/latest


Test location /workspace/coverage/default/34.usbdev_in_stall.3317877917
Short name T1317
Test name
Test status
Simulation time 8365341476 ps
CPU time 7.88 seconds
Started Apr 21 04:03:15 PM PDT 24
Finished Apr 21 04:03:23 PM PDT 24
Peak memory 204056 kb
Host smart-e9ea6074-b92f-4cce-97af-6f8ee464cdf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33178
77917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3317877917
Directory /workspace/34.usbdev_in_stall/latest


Test location /workspace/coverage/default/34.usbdev_in_trans.3341166238
Short name T855
Test name
Test status
Simulation time 8388417577 ps
CPU time 7.98 seconds
Started Apr 21 04:03:10 PM PDT 24
Finished Apr 21 04:03:18 PM PDT 24
Peak memory 204044 kb
Host smart-1167717b-587e-482e-8e65-390587617760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33411
66238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.3341166238
Directory /workspace/34.usbdev_in_trans/latest


Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.1980614737
Short name T409
Test name
Test status
Simulation time 8422601947 ps
CPU time 7.81 seconds
Started Apr 21 04:03:09 PM PDT 24
Finished Apr 21 04:03:17 PM PDT 24
Peak memory 204056 kb
Host smart-e1d9e481-7bab-4929-a7f4-0c5204faf8e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19806
14737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.1980614737
Directory /workspace/34.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.3528073677
Short name T620
Test name
Test status
Simulation time 8371694760 ps
CPU time 8.12 seconds
Started Apr 21 04:03:10 PM PDT 24
Finished Apr 21 04:03:18 PM PDT 24
Peak memory 204224 kb
Host smart-63d47c14-ba7d-4a00-8e0b-6fdbce4c7a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35280
73677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3528073677
Directory /workspace/34.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/34.usbdev_nak_trans.566816177
Short name T1162
Test name
Test status
Simulation time 8428671370 ps
CPU time 8.53 seconds
Started Apr 21 04:03:13 PM PDT 24
Finished Apr 21 04:03:22 PM PDT 24
Peak memory 204060 kb
Host smart-d384a281-0192-4eb5-8254-3848f460d719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56681
6177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.566816177
Directory /workspace/34.usbdev_nak_trans/latest


Test location /workspace/coverage/default/34.usbdev_out_stall.2043195822
Short name T919
Test name
Test status
Simulation time 8386078413 ps
CPU time 7.51 seconds
Started Apr 21 04:03:12 PM PDT 24
Finished Apr 21 04:03:19 PM PDT 24
Peak memory 204072 kb
Host smart-1cbc7b1f-ff01-4e4b-a754-79c557634ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20431
95822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2043195822
Directory /workspace/34.usbdev_out_stall/latest


Test location /workspace/coverage/default/34.usbdev_out_trans_nak.2265551663
Short name T426
Test name
Test status
Simulation time 8421691448 ps
CPU time 8.51 seconds
Started Apr 21 04:03:14 PM PDT 24
Finished Apr 21 04:03:23 PM PDT 24
Peak memory 204064 kb
Host smart-98843e0c-7383-49d5-ae85-0983c3e470ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22655
51663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.2265551663
Directory /workspace/34.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/34.usbdev_pending_in_trans.999839762
Short name T1361
Test name
Test status
Simulation time 8381845993 ps
CPU time 9.04 seconds
Started Apr 21 04:03:13 PM PDT 24
Finished Apr 21 04:03:23 PM PDT 24
Peak memory 204080 kb
Host smart-16b15fe8-f10c-4dbf-b231-c94dd409966e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99983
9762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.999839762
Directory /workspace/34.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.2831735082
Short name T712
Test name
Test status
Simulation time 8437566306 ps
CPU time 7.6 seconds
Started Apr 21 04:03:13 PM PDT 24
Finished Apr 21 04:03:21 PM PDT 24
Peak memory 204080 kb
Host smart-5e29077c-c495-4930-b09e-d0c5882e1eb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28317
35082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.2831735082
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.2121571229
Short name T319
Test name
Test status
Simulation time 38079976 ps
CPU time 0.67 seconds
Started Apr 21 04:03:13 PM PDT 24
Finished Apr 21 04:03:14 PM PDT 24
Peak memory 203932 kb
Host smart-f03df907-5579-4b30-97db-c6d19114d245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21215
71229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.2121571229
Directory /workspace/34.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/34.usbdev_pkt_buffer.1193210887
Short name T860
Test name
Test status
Simulation time 27270664422 ps
CPU time 57.32 seconds
Started Apr 21 04:03:13 PM PDT 24
Finished Apr 21 04:04:10 PM PDT 24
Peak memory 204368 kb
Host smart-5e258c67-dd31-4b88-9c68-43d69553d55c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11932
10887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.1193210887
Directory /workspace/34.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/34.usbdev_pkt_received.1440865531
Short name T425
Test name
Test status
Simulation time 8387608358 ps
CPU time 9.82 seconds
Started Apr 21 04:03:14 PM PDT 24
Finished Apr 21 04:03:24 PM PDT 24
Peak memory 203940 kb
Host smart-34a62461-11e9-4964-bf5f-98f47346ca18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14408
65531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.1440865531
Directory /workspace/34.usbdev_pkt_received/latest


Test location /workspace/coverage/default/34.usbdev_pkt_sent.2420416511
Short name T143
Test name
Test status
Simulation time 8391898215 ps
CPU time 7.89 seconds
Started Apr 21 04:03:13 PM PDT 24
Finished Apr 21 04:03:21 PM PDT 24
Peak memory 204028 kb
Host smart-2061d92c-d189-456f-bee1-ba8c02e5fea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24204
16511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2420416511
Directory /workspace/34.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.2785978337
Short name T455
Test name
Test status
Simulation time 8400632213 ps
CPU time 10.11 seconds
Started Apr 21 04:03:12 PM PDT 24
Finished Apr 21 04:03:22 PM PDT 24
Peak memory 204064 kb
Host smart-d3382465-6555-4ea2-9349-8f4bedbf8f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27859
78337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.2785978337
Directory /workspace/34.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/34.usbdev_setup_stage.4238711855
Short name T17
Test name
Test status
Simulation time 8376161297 ps
CPU time 7.64 seconds
Started Apr 21 04:03:12 PM PDT 24
Finished Apr 21 04:03:20 PM PDT 24
Peak memory 204068 kb
Host smart-5cfdbca4-bae2-48d7-9d4d-99f4fedc06ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42387
11855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.4238711855
Directory /workspace/34.usbdev_setup_stage/latest


Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.3840214396
Short name T710
Test name
Test status
Simulation time 8380942058 ps
CPU time 8.28 seconds
Started Apr 21 04:03:11 PM PDT 24
Finished Apr 21 04:03:20 PM PDT 24
Peak memory 204016 kb
Host smart-67c0174a-aa71-4c37-9363-bc5c10aa070b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38402
14396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.3840214396
Directory /workspace/34.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/34.usbdev_smoke.1381678496
Short name T759
Test name
Test status
Simulation time 8465501845 ps
CPU time 8.82 seconds
Started Apr 21 04:03:08 PM PDT 24
Finished Apr 21 04:03:17 PM PDT 24
Peak memory 204032 kb
Host smart-e34f079d-e08f-485f-9967-0cdbfa6ac495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13816
78496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1381678496
Directory /workspace/34.usbdev_smoke/latest


Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.2137493903
Short name T964
Test name
Test status
Simulation time 8372155626 ps
CPU time 7.81 seconds
Started Apr 21 04:03:14 PM PDT 24
Finished Apr 21 04:03:22 PM PDT 24
Peak memory 204056 kb
Host smart-4ecd14db-a73f-436b-8e11-afe44bb096fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21374
93903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.2137493903
Directory /workspace/34.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/34.usbdev_stall_trans.334197662
Short name T636
Test name
Test status
Simulation time 8398766438 ps
CPU time 8.95 seconds
Started Apr 21 04:03:18 PM PDT 24
Finished Apr 21 04:03:27 PM PDT 24
Peak memory 204032 kb
Host smart-ce6d0b73-a12d-4de4-a59b-ba9ea3ec4542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33419
7662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.334197662
Directory /workspace/34.usbdev_stall_trans/latest


Test location /workspace/coverage/default/35.max_length_in_transaction.4176334706
Short name T618
Test name
Test status
Simulation time 8464782632 ps
CPU time 8.75 seconds
Started Apr 21 04:03:24 PM PDT 24
Finished Apr 21 04:03:33 PM PDT 24
Peak memory 204068 kb
Host smart-b134a0f5-cee0-4daa-b5fb-e00a33ecce6d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4176334706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.4176334706
Directory /workspace/35.max_length_in_transaction/latest


Test location /workspace/coverage/default/35.min_length_in_transaction.3219287698
Short name T81
Test name
Test status
Simulation time 8382035411 ps
CPU time 7.78 seconds
Started Apr 21 04:03:21 PM PDT 24
Finished Apr 21 04:03:29 PM PDT 24
Peak memory 204024 kb
Host smart-11d53558-330d-43d1-a480-dcd177009255
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3219287698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.3219287698
Directory /workspace/35.min_length_in_transaction/latest


Test location /workspace/coverage/default/35.random_length_in_trans.1102890198
Short name T40
Test name
Test status
Simulation time 8397839478 ps
CPU time 8.17 seconds
Started Apr 21 04:03:20 PM PDT 24
Finished Apr 21 04:03:29 PM PDT 24
Peak memory 204036 kb
Host smart-3568f687-dd6d-447c-b999-da9c9c786dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11028
90198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.1102890198
Directory /workspace/35.random_length_in_trans/latest


Test location /workspace/coverage/default/35.usbdev_av_buffer.2225945040
Short name T602
Test name
Test status
Simulation time 8386124018 ps
CPU time 8.13 seconds
Started Apr 21 04:03:15 PM PDT 24
Finished Apr 21 04:03:24 PM PDT 24
Peak memory 204088 kb
Host smart-edb16006-4423-42a1-af61-76d42f7eff9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22259
45040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2225945040
Directory /workspace/35.usbdev_av_buffer/latest


Test location /workspace/coverage/default/35.usbdev_enable.2521633309
Short name T685
Test name
Test status
Simulation time 8385715740 ps
CPU time 8.25 seconds
Started Apr 21 04:03:15 PM PDT 24
Finished Apr 21 04:03:24 PM PDT 24
Peak memory 204088 kb
Host smart-dc7a45af-090f-44b1-bbeb-f7af8e203e02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25216
33309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.2521633309
Directory /workspace/35.usbdev_enable/latest


Test location /workspace/coverage/default/35.usbdev_fifo_rst.2217176668
Short name T438
Test name
Test status
Simulation time 77483159 ps
CPU time 2.13 seconds
Started Apr 21 04:03:15 PM PDT 24
Finished Apr 21 04:03:17 PM PDT 24
Peak memory 204092 kb
Host smart-0bf5be10-1a4b-43ac-8f23-b62f79d3d881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22171
76668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.2217176668
Directory /workspace/35.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/35.usbdev_in_iso.176481199
Short name T808
Test name
Test status
Simulation time 8428233148 ps
CPU time 9.93 seconds
Started Apr 21 04:03:20 PM PDT 24
Finished Apr 21 04:03:30 PM PDT 24
Peak memory 204048 kb
Host smart-4b1845f9-dc83-46cb-9843-dd8a5c7d484c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17648
1199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.176481199
Directory /workspace/35.usbdev_in_iso/latest


Test location /workspace/coverage/default/35.usbdev_in_stall.3286313468
Short name T668
Test name
Test status
Simulation time 8404813867 ps
CPU time 8.35 seconds
Started Apr 21 04:03:21 PM PDT 24
Finished Apr 21 04:03:29 PM PDT 24
Peak memory 204020 kb
Host smart-c7f4bd73-395f-4268-8ca7-dad699c10a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32863
13468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.3286313468
Directory /workspace/35.usbdev_in_stall/latest


Test location /workspace/coverage/default/35.usbdev_in_trans.822972940
Short name T152
Test name
Test status
Simulation time 8422177950 ps
CPU time 7.73 seconds
Started Apr 21 04:03:17 PM PDT 24
Finished Apr 21 04:03:25 PM PDT 24
Peak memory 204084 kb
Host smart-d308df60-ce38-4c23-8eb1-838a8fa5f5ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82297
2940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.822972940
Directory /workspace/35.usbdev_in_trans/latest


Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.583428429
Short name T819
Test name
Test status
Simulation time 8412410517 ps
CPU time 8.93 seconds
Started Apr 21 04:03:19 PM PDT 24
Finished Apr 21 04:03:28 PM PDT 24
Peak memory 204064 kb
Host smart-354e80cc-2edf-468f-9385-0a4c5995d34e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58342
8429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.583428429
Directory /workspace/35.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2256460422
Short name T1182
Test name
Test status
Simulation time 8370283788 ps
CPU time 7.92 seconds
Started Apr 21 04:03:17 PM PDT 24
Finished Apr 21 04:03:25 PM PDT 24
Peak memory 204064 kb
Host smart-d0ca4e21-d801-4aae-a661-199ff2006582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22564
60422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2256460422
Directory /workspace/35.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/35.usbdev_nak_trans.2211690017
Short name T1307
Test name
Test status
Simulation time 8406472149 ps
CPU time 8.98 seconds
Started Apr 21 04:03:19 PM PDT 24
Finished Apr 21 04:03:28 PM PDT 24
Peak memory 204064 kb
Host smart-42452654-aa46-4634-b1d3-916d0d485d2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22116
90017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2211690017
Directory /workspace/35.usbdev_nak_trans/latest


Test location /workspace/coverage/default/35.usbdev_out_stall.1782456997
Short name T790
Test name
Test status
Simulation time 8432411209 ps
CPU time 10.2 seconds
Started Apr 21 04:03:17 PM PDT 24
Finished Apr 21 04:03:28 PM PDT 24
Peak memory 204048 kb
Host smart-047e4d0c-a912-449d-8be1-5b8bcad3b7d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17824
56997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.1782456997
Directory /workspace/35.usbdev_out_stall/latest


Test location /workspace/coverage/default/35.usbdev_out_trans_nak.4071665601
Short name T826
Test name
Test status
Simulation time 8417946410 ps
CPU time 8.47 seconds
Started Apr 21 04:03:16 PM PDT 24
Finished Apr 21 04:03:25 PM PDT 24
Peak memory 204084 kb
Host smart-d8d18a06-b946-4677-93cd-4d1fb417c360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40716
65601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.4071665601
Directory /workspace/35.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/35.usbdev_pending_in_trans.2407727522
Short name T174
Test name
Test status
Simulation time 8391878840 ps
CPU time 8.66 seconds
Started Apr 21 04:03:21 PM PDT 24
Finished Apr 21 04:03:30 PM PDT 24
Peak memory 204032 kb
Host smart-2ad5b818-2a95-447e-ab8f-d1ec7d6b5026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24077
27522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.2407727522
Directory /workspace/35.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.192166373
Short name T571
Test name
Test status
Simulation time 8369900138 ps
CPU time 7.75 seconds
Started Apr 21 04:03:21 PM PDT 24
Finished Apr 21 04:03:29 PM PDT 24
Peak memory 204040 kb
Host smart-a55ab89a-ac66-4839-a044-d7473e862c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19216
6373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.192166373
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.927851965
Short name T628
Test name
Test status
Simulation time 41241604 ps
CPU time 0.69 seconds
Started Apr 21 04:03:19 PM PDT 24
Finished Apr 21 04:03:20 PM PDT 24
Peak memory 203908 kb
Host smart-a53f9ce9-07d2-4272-8ceb-6054e6fbaeed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92785
1965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.927851965
Directory /workspace/35.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/35.usbdev_pkt_buffer.3380738646
Short name T1356
Test name
Test status
Simulation time 17279352658 ps
CPU time 29.55 seconds
Started Apr 21 04:03:17 PM PDT 24
Finished Apr 21 04:03:48 PM PDT 24
Peak memory 204348 kb
Host smart-5d6d8d91-860d-4513-9920-ce707532c121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33807
38646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.3380738646
Directory /workspace/35.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/35.usbdev_pkt_received.19415732
Short name T1067
Test name
Test status
Simulation time 8395557150 ps
CPU time 8.09 seconds
Started Apr 21 04:03:18 PM PDT 24
Finished Apr 21 04:03:27 PM PDT 24
Peak memory 204068 kb
Host smart-916709c7-98f3-4ef3-9404-016ce15b5a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19415
732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.19415732
Directory /workspace/35.usbdev_pkt_received/latest


Test location /workspace/coverage/default/35.usbdev_pkt_sent.3848080767
Short name T445
Test name
Test status
Simulation time 8441586849 ps
CPU time 8.08 seconds
Started Apr 21 04:03:18 PM PDT 24
Finished Apr 21 04:03:26 PM PDT 24
Peak memory 204044 kb
Host smart-1e407068-8c91-4069-ade4-84be2e0b53d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38480
80767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3848080767
Directory /workspace/35.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.4284127130
Short name T371
Test name
Test status
Simulation time 8406744228 ps
CPU time 8.57 seconds
Started Apr 21 04:03:17 PM PDT 24
Finished Apr 21 04:03:26 PM PDT 24
Peak memory 204064 kb
Host smart-97e3ac46-1a25-4901-92c4-ebb3ab7ded4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42841
27130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.4284127130
Directory /workspace/35.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/35.usbdev_setup_stage.1843443893
Short name T1131
Test name
Test status
Simulation time 8372283640 ps
CPU time 8.2 seconds
Started Apr 21 04:03:20 PM PDT 24
Finished Apr 21 04:03:28 PM PDT 24
Peak memory 204060 kb
Host smart-5ea02129-a663-4369-9a95-8121734bbd65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18434
43893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.1843443893
Directory /workspace/35.usbdev_setup_stage/latest


Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.3890189053
Short name T534
Test name
Test status
Simulation time 8377592013 ps
CPU time 9.23 seconds
Started Apr 21 04:03:20 PM PDT 24
Finished Apr 21 04:03:29 PM PDT 24
Peak memory 204036 kb
Host smart-34fb8809-3f05-487a-a576-6cb80d52f59a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38901
89053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3890189053
Directory /workspace/35.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/35.usbdev_smoke.75069837
Short name T976
Test name
Test status
Simulation time 8454339051 ps
CPU time 9.02 seconds
Started Apr 21 04:03:18 PM PDT 24
Finished Apr 21 04:03:27 PM PDT 24
Peak memory 204048 kb
Host smart-9849898b-f9f1-4341-8308-36232b160004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75069
837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.75069837
Directory /workspace/35.usbdev_smoke/latest


Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.2484050883
Short name T1094
Test name
Test status
Simulation time 8393860590 ps
CPU time 7.64 seconds
Started Apr 21 04:03:21 PM PDT 24
Finished Apr 21 04:03:29 PM PDT 24
Peak memory 204020 kb
Host smart-ce2849b5-54a6-4116-b89e-b0eb094abf03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24840
50883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.2484050883
Directory /workspace/35.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/35.usbdev_stall_trans.2160031690
Short name T411
Test name
Test status
Simulation time 8398092554 ps
CPU time 8.39 seconds
Started Apr 21 04:03:20 PM PDT 24
Finished Apr 21 04:03:29 PM PDT 24
Peak memory 204040 kb
Host smart-37286886-a2ee-4edc-8cd1-e4cbe0f71b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21600
31690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.2160031690
Directory /workspace/35.usbdev_stall_trans/latest


Test location /workspace/coverage/default/36.max_length_in_transaction.560406059
Short name T694
Test name
Test status
Simulation time 8456679652 ps
CPU time 7.85 seconds
Started Apr 21 04:03:30 PM PDT 24
Finished Apr 21 04:03:38 PM PDT 24
Peak memory 204068 kb
Host smart-258fd262-f375-4d19-b5f2-c9ba378bd0c8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=560406059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.560406059
Directory /workspace/36.max_length_in_transaction/latest


Test location /workspace/coverage/default/36.min_length_in_transaction.2243109900
Short name T1
Test name
Test status
Simulation time 8391877281 ps
CPU time 7.89 seconds
Started Apr 21 04:03:31 PM PDT 24
Finished Apr 21 04:03:39 PM PDT 24
Peak memory 204040 kb
Host smart-ff4edf45-36d5-4da7-8116-ef117935dee3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2243109900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.2243109900
Directory /workspace/36.min_length_in_transaction/latest


Test location /workspace/coverage/default/36.random_length_in_trans.1184774430
Short name T346
Test name
Test status
Simulation time 8408139224 ps
CPU time 10.19 seconds
Started Apr 21 04:03:29 PM PDT 24
Finished Apr 21 04:03:40 PM PDT 24
Peak memory 204004 kb
Host smart-3dfb595a-ecf5-4463-ad68-e6083106f775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11847
74430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.1184774430
Directory /workspace/36.random_length_in_trans/latest


Test location /workspace/coverage/default/36.usbdev_av_buffer.790935143
Short name T1289
Test name
Test status
Simulation time 8376878487 ps
CPU time 9.18 seconds
Started Apr 21 04:03:23 PM PDT 24
Finished Apr 21 04:03:32 PM PDT 24
Peak memory 203948 kb
Host smart-d3c90c1b-836d-4320-8711-a46e65a159b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79093
5143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.790935143
Directory /workspace/36.usbdev_av_buffer/latest


Test location /workspace/coverage/default/36.usbdev_enable.262300955
Short name T776
Test name
Test status
Simulation time 8379447742 ps
CPU time 8.22 seconds
Started Apr 21 04:03:22 PM PDT 24
Finished Apr 21 04:03:30 PM PDT 24
Peak memory 204020 kb
Host smart-753c6c59-6275-4f2b-8b3f-86070944cc68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26230
0955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.262300955
Directory /workspace/36.usbdev_enable/latest


Test location /workspace/coverage/default/36.usbdev_fifo_rst.1376480219
Short name T609
Test name
Test status
Simulation time 113931455 ps
CPU time 1.41 seconds
Started Apr 21 04:03:22 PM PDT 24
Finished Apr 21 04:03:24 PM PDT 24
Peak memory 204144 kb
Host smart-a07af518-a91b-4dee-83ff-d8a265f2b34e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13764
80219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1376480219
Directory /workspace/36.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/36.usbdev_in_iso.703191372
Short name T454
Test name
Test status
Simulation time 8451368681 ps
CPU time 9.82 seconds
Started Apr 21 04:03:32 PM PDT 24
Finished Apr 21 04:03:42 PM PDT 24
Peak memory 204220 kb
Host smart-05790207-3f2f-4be0-92bd-81b74fde1696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70319
1372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.703191372
Directory /workspace/36.usbdev_in_iso/latest


Test location /workspace/coverage/default/36.usbdev_in_stall.3544755951
Short name T190
Test name
Test status
Simulation time 8371504588 ps
CPU time 8.59 seconds
Started Apr 21 04:03:33 PM PDT 24
Finished Apr 21 04:03:42 PM PDT 24
Peak memory 204024 kb
Host smart-7d2544b1-51f2-4e95-af69-62aa8af2ed58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35447
55951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.3544755951
Directory /workspace/36.usbdev_in_stall/latest


Test location /workspace/coverage/default/36.usbdev_in_trans.233568980
Short name T153
Test name
Test status
Simulation time 8471518558 ps
CPU time 8.32 seconds
Started Apr 21 04:03:23 PM PDT 24
Finished Apr 21 04:03:32 PM PDT 24
Peak memory 204056 kb
Host smart-b2a872ce-b8f4-4876-94d9-a5d224702534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23356
8980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.233568980
Directory /workspace/36.usbdev_in_trans/latest


Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1572849733
Short name T1000
Test name
Test status
Simulation time 8419643087 ps
CPU time 9.07 seconds
Started Apr 21 04:03:23 PM PDT 24
Finished Apr 21 04:03:33 PM PDT 24
Peak memory 204052 kb
Host smart-808c6a73-b3b3-4023-ba31-802d3335cbdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15728
49733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1572849733
Directory /workspace/36.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.442656240
Short name T1248
Test name
Test status
Simulation time 8416213856 ps
CPU time 7.8 seconds
Started Apr 21 04:03:25 PM PDT 24
Finished Apr 21 04:03:33 PM PDT 24
Peak memory 204028 kb
Host smart-5eccbb02-c88b-41f4-a7c4-0f9f4092b2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44265
6240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.442656240
Directory /workspace/36.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/36.usbdev_nak_trans.599941260
Short name T112
Test name
Test status
Simulation time 8407806389 ps
CPU time 8.96 seconds
Started Apr 21 04:03:27 PM PDT 24
Finished Apr 21 04:03:36 PM PDT 24
Peak memory 204048 kb
Host smart-b9e94117-cf8e-4be4-99dd-c82fe959ae77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59994
1260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.599941260
Directory /workspace/36.usbdev_nak_trans/latest


Test location /workspace/coverage/default/36.usbdev_out_stall.501690465
Short name T638
Test name
Test status
Simulation time 8412165948 ps
CPU time 8.7 seconds
Started Apr 21 04:03:26 PM PDT 24
Finished Apr 21 04:03:35 PM PDT 24
Peak memory 204068 kb
Host smart-ba598435-efd0-494c-ad94-84bf79bf4462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50169
0465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.501690465
Directory /workspace/36.usbdev_out_stall/latest


Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1248314908
Short name T287
Test name
Test status
Simulation time 8497664565 ps
CPU time 8.08 seconds
Started Apr 21 04:03:26 PM PDT 24
Finished Apr 21 04:03:34 PM PDT 24
Peak memory 204064 kb
Host smart-5a8e8274-c09f-4961-bb9a-ff9840c147c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12483
14908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1248314908
Directory /workspace/36.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/36.usbdev_pending_in_trans.253257451
Short name T492
Test name
Test status
Simulation time 8392322260 ps
CPU time 8.55 seconds
Started Apr 21 04:03:28 PM PDT 24
Finished Apr 21 04:03:36 PM PDT 24
Peak memory 203960 kb
Host smart-a6af5a87-82b0-4c27-ac3b-3a9c4ac3d780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25325
7451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.253257451
Directory /workspace/36.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.1768364061
Short name T1049
Test name
Test status
Simulation time 8402612332 ps
CPU time 8.75 seconds
Started Apr 21 04:03:36 PM PDT 24
Finished Apr 21 04:03:45 PM PDT 24
Peak memory 204032 kb
Host smart-8961d41f-9fbb-4008-af5d-55de2666bf4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17683
64061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.1768364061
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.1612420792
Short name T46
Test name
Test status
Simulation time 38012812 ps
CPU time 0.71 seconds
Started Apr 21 04:03:35 PM PDT 24
Finished Apr 21 04:03:36 PM PDT 24
Peak memory 203904 kb
Host smart-abfaab0e-d248-4f94-b71c-f4e7ab0695e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16124
20792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.1612420792
Directory /workspace/36.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/36.usbdev_pkt_buffer.620010518
Short name T471
Test name
Test status
Simulation time 24644398449 ps
CPU time 46.85 seconds
Started Apr 21 04:03:25 PM PDT 24
Finished Apr 21 04:04:12 PM PDT 24
Peak memory 204320 kb
Host smart-7fc35edb-620a-4150-a6cd-13b9c07e1ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62001
0518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.620010518
Directory /workspace/36.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/36.usbdev_pkt_received.892676492
Short name T657
Test name
Test status
Simulation time 8406682051 ps
CPU time 7.47 seconds
Started Apr 21 04:03:28 PM PDT 24
Finished Apr 21 04:03:36 PM PDT 24
Peak memory 204064 kb
Host smart-6f325a0c-6d7d-4896-8de7-6afe3358cb64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89267
6492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.892676492
Directory /workspace/36.usbdev_pkt_received/latest


Test location /workspace/coverage/default/36.usbdev_pkt_sent.3662237298
Short name T37
Test name
Test status
Simulation time 8481115767 ps
CPU time 8.64 seconds
Started Apr 21 04:03:35 PM PDT 24
Finished Apr 21 04:03:45 PM PDT 24
Peak memory 204040 kb
Host smart-4f973c9c-3f21-4dbc-87cd-484ebe91e351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36622
37298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3662237298
Directory /workspace/36.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.462091446
Short name T1097
Test name
Test status
Simulation time 8370064148 ps
CPU time 7.71 seconds
Started Apr 21 04:03:27 PM PDT 24
Finished Apr 21 04:03:35 PM PDT 24
Peak memory 204060 kb
Host smart-4729b34f-0ff2-46af-a86f-696678c3c0da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46209
1446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.462091446
Directory /workspace/36.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/36.usbdev_setup_stage.1067591904
Short name T1241
Test name
Test status
Simulation time 8377481964 ps
CPU time 7.62 seconds
Started Apr 21 04:03:36 PM PDT 24
Finished Apr 21 04:03:44 PM PDT 24
Peak memory 204032 kb
Host smart-3b1d9e57-41cd-4893-a6ad-65e5dc641f0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10675
91904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.1067591904
Directory /workspace/36.usbdev_setup_stage/latest


Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1237177867
Short name T928
Test name
Test status
Simulation time 8379095862 ps
CPU time 7.88 seconds
Started Apr 21 04:03:29 PM PDT 24
Finished Apr 21 04:03:37 PM PDT 24
Peak memory 203448 kb
Host smart-a0e0a6c7-8fd7-47ae-9a8e-c39929246eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12371
77867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1237177867
Directory /workspace/36.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/36.usbdev_smoke.3096389651
Short name T139
Test name
Test status
Simulation time 8467409925 ps
CPU time 8.31 seconds
Started Apr 21 04:03:23 PM PDT 24
Finished Apr 21 04:03:31 PM PDT 24
Peak memory 204052 kb
Host smart-f403cdfb-2f82-4aad-a22c-684f20a19695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30963
89651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.3096389651
Directory /workspace/36.usbdev_smoke/latest


Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.3195523996
Short name T1228
Test name
Test status
Simulation time 8383977419 ps
CPU time 8.12 seconds
Started Apr 21 04:03:35 PM PDT 24
Finished Apr 21 04:03:44 PM PDT 24
Peak memory 204032 kb
Host smart-0704429c-3e6c-4608-bf99-a95023faec48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31955
23996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.3195523996
Directory /workspace/36.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/36.usbdev_stall_trans.619681444
Short name T318
Test name
Test status
Simulation time 8370846252 ps
CPU time 10.08 seconds
Started Apr 21 04:03:30 PM PDT 24
Finished Apr 21 04:03:40 PM PDT 24
Peak memory 204048 kb
Host smart-431faa75-e4ec-47d7-b129-cd722becf316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61968
1444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.619681444
Directory /workspace/36.usbdev_stall_trans/latest


Test location /workspace/coverage/default/37.max_length_in_transaction.335009318
Short name T399
Test name
Test status
Simulation time 8477202615 ps
CPU time 8.45 seconds
Started Apr 21 04:03:40 PM PDT 24
Finished Apr 21 04:03:48 PM PDT 24
Peak memory 204052 kb
Host smart-a7403561-88f2-452d-95f1-d2bcef9519eb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=335009318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.335009318
Directory /workspace/37.max_length_in_transaction/latest


Test location /workspace/coverage/default/37.min_length_in_transaction.1889976850
Short name T338
Test name
Test status
Simulation time 8393325743 ps
CPU time 10.33 seconds
Started Apr 21 04:03:37 PM PDT 24
Finished Apr 21 04:03:48 PM PDT 24
Peak memory 204036 kb
Host smart-ae4ea563-97f7-4005-a04d-6828e6e0c6ac
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1889976850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.1889976850
Directory /workspace/37.min_length_in_transaction/latest


Test location /workspace/coverage/default/37.random_length_in_trans.1705062288
Short name T846
Test name
Test status
Simulation time 8417245919 ps
CPU time 7.93 seconds
Started Apr 21 04:03:37 PM PDT 24
Finished Apr 21 04:03:45 PM PDT 24
Peak memory 204004 kb
Host smart-5fda9456-2f9f-4ef8-881c-b037476c5d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17050
62288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.1705062288
Directory /workspace/37.random_length_in_trans/latest


Test location /workspace/coverage/default/37.usbdev_av_buffer.2208725317
Short name T1349
Test name
Test status
Simulation time 8375263113 ps
CPU time 9.55 seconds
Started Apr 21 04:03:30 PM PDT 24
Finished Apr 21 04:03:40 PM PDT 24
Peak memory 204044 kb
Host smart-6f3c8e26-ad41-43a8-bbf0-830a3f382107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22087
25317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2208725317
Directory /workspace/37.usbdev_av_buffer/latest


Test location /workspace/coverage/default/37.usbdev_enable.1725791479
Short name T1282
Test name
Test status
Simulation time 8405206001 ps
CPU time 7.41 seconds
Started Apr 21 04:03:34 PM PDT 24
Finished Apr 21 04:03:42 PM PDT 24
Peak memory 204048 kb
Host smart-babf390e-543f-4a55-8bf9-3b94aa81226a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17257
91479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.1725791479
Directory /workspace/37.usbdev_enable/latest


Test location /workspace/coverage/default/37.usbdev_fifo_rst.965782060
Short name T1007
Test name
Test status
Simulation time 50013645 ps
CPU time 1.45 seconds
Started Apr 21 04:03:35 PM PDT 24
Finished Apr 21 04:03:37 PM PDT 24
Peak memory 204164 kb
Host smart-7fc678bb-3690-4b04-93a3-ee8f659a6f12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96578
2060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.965782060
Directory /workspace/37.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/37.usbdev_in_iso.1821669902
Short name T877
Test name
Test status
Simulation time 8452767353 ps
CPU time 8.37 seconds
Started Apr 21 04:03:38 PM PDT 24
Finished Apr 21 04:03:47 PM PDT 24
Peak memory 204024 kb
Host smart-8906e368-9a10-4104-b619-d280ec0f6126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18216
69902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.1821669902
Directory /workspace/37.usbdev_in_iso/latest


Test location /workspace/coverage/default/37.usbdev_in_stall.1037071043
Short name T809
Test name
Test status
Simulation time 8359738892 ps
CPU time 8.15 seconds
Started Apr 21 04:03:38 PM PDT 24
Finished Apr 21 04:03:47 PM PDT 24
Peak memory 204064 kb
Host smart-22d3d42e-c177-4aff-a00d-d2256e3f0108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10370
71043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.1037071043
Directory /workspace/37.usbdev_in_stall/latest


Test location /workspace/coverage/default/37.usbdev_in_trans.1305982385
Short name T146
Test name
Test status
Simulation time 8409208155 ps
CPU time 10.62 seconds
Started Apr 21 04:03:33 PM PDT 24
Finished Apr 21 04:03:44 PM PDT 24
Peak memory 204052 kb
Host smart-76da5690-a64c-43da-b4dd-44d66b2df46a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13059
82385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.1305982385
Directory /workspace/37.usbdev_in_trans/latest


Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.4234559235
Short name T1102
Test name
Test status
Simulation time 8421744677 ps
CPU time 9.55 seconds
Started Apr 21 04:03:33 PM PDT 24
Finished Apr 21 04:03:43 PM PDT 24
Peak memory 204040 kb
Host smart-15190c64-349f-4cab-8184-f3b9d7186896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42345
59235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.4234559235
Directory /workspace/37.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.3215607850
Short name T1048
Test name
Test status
Simulation time 8407133486 ps
CPU time 7.9 seconds
Started Apr 21 04:03:35 PM PDT 24
Finished Apr 21 04:03:43 PM PDT 24
Peak memory 204036 kb
Host smart-5c007224-8417-4b8a-a006-25f705cbfe02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32156
07850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.3215607850
Directory /workspace/37.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/37.usbdev_nak_trans.3317527582
Short name T111
Test name
Test status
Simulation time 8471522721 ps
CPU time 8.18 seconds
Started Apr 21 04:03:34 PM PDT 24
Finished Apr 21 04:03:42 PM PDT 24
Peak memory 204068 kb
Host smart-ac0b9cb6-51e6-4e86-809a-35825a0dcf0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33175
27582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3317527582
Directory /workspace/37.usbdev_nak_trans/latest


Test location /workspace/coverage/default/37.usbdev_out_stall.3590511482
Short name T1222
Test name
Test status
Simulation time 8387275008 ps
CPU time 8.14 seconds
Started Apr 21 04:03:32 PM PDT 24
Finished Apr 21 04:03:40 PM PDT 24
Peak memory 203460 kb
Host smart-8ab3b12f-3413-419e-a76a-a8b3d98adbc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35905
11482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.3590511482
Directory /workspace/37.usbdev_out_stall/latest


Test location /workspace/coverage/default/37.usbdev_out_trans_nak.4199125912
Short name T836
Test name
Test status
Simulation time 8375518383 ps
CPU time 7.47 seconds
Started Apr 21 04:03:37 PM PDT 24
Finished Apr 21 04:03:44 PM PDT 24
Peak memory 204032 kb
Host smart-4a63190a-71ac-4d6c-8de3-2497c6e18af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41991
25912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.4199125912
Directory /workspace/37.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/37.usbdev_pending_in_trans.3563408245
Short name T197
Test name
Test status
Simulation time 8421088893 ps
CPU time 9.06 seconds
Started Apr 21 04:03:38 PM PDT 24
Finished Apr 21 04:03:48 PM PDT 24
Peak memory 204032 kb
Host smart-af21ab57-5a2e-4e2d-b0fd-3017cf4147cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35634
08245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.3563408245
Directory /workspace/37.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.1974388613
Short name T617
Test name
Test status
Simulation time 8379008632 ps
CPU time 10.3 seconds
Started Apr 21 04:03:37 PM PDT 24
Finished Apr 21 04:03:48 PM PDT 24
Peak memory 204044 kb
Host smart-104a50bf-0692-4c25-8e9b-006289664368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19743
88613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.1974388613
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.2316191582
Short name T1337
Test name
Test status
Simulation time 42025520 ps
CPU time 0.67 seconds
Started Apr 21 04:03:37 PM PDT 24
Finished Apr 21 04:03:38 PM PDT 24
Peak memory 203940 kb
Host smart-2d43798b-dca0-4315-aa5d-f3ce73deae79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23161
91582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.2316191582
Directory /workspace/37.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/37.usbdev_pkt_buffer.3989998416
Short name T1188
Test name
Test status
Simulation time 21956264222 ps
CPU time 41.11 seconds
Started Apr 21 04:03:35 PM PDT 24
Finished Apr 21 04:04:16 PM PDT 24
Peak memory 204320 kb
Host smart-c0baa67e-bb0e-427d-a120-4806e607cd50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39899
98416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.3989998416
Directory /workspace/37.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/37.usbdev_pkt_received.2901948781
Short name T845
Test name
Test status
Simulation time 8381709708 ps
CPU time 9.29 seconds
Started Apr 21 04:03:37 PM PDT 24
Finished Apr 21 04:03:47 PM PDT 24
Peak memory 204024 kb
Host smart-3ee31c3c-f3c9-463d-9f3d-2f7a98f10754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29019
48781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2901948781
Directory /workspace/37.usbdev_pkt_received/latest


Test location /workspace/coverage/default/37.usbdev_pkt_sent.3521317187
Short name T853
Test name
Test status
Simulation time 8447711214 ps
CPU time 8.67 seconds
Started Apr 21 04:03:37 PM PDT 24
Finished Apr 21 04:03:46 PM PDT 24
Peak memory 204068 kb
Host smart-c3247167-a195-4753-a547-69a62ee07691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35213
17187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.3521317187
Directory /workspace/37.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.1474315567
Short name T1052
Test name
Test status
Simulation time 8394181190 ps
CPU time 9.69 seconds
Started Apr 21 04:03:38 PM PDT 24
Finished Apr 21 04:03:47 PM PDT 24
Peak memory 203992 kb
Host smart-86733e45-f0e9-47f5-aef8-f6161a86aca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14743
15567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.1474315567
Directory /workspace/37.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/37.usbdev_setup_stage.3000603687
Short name T1300
Test name
Test status
Simulation time 8393643536 ps
CPU time 8.88 seconds
Started Apr 21 04:03:38 PM PDT 24
Finished Apr 21 04:03:47 PM PDT 24
Peak memory 204060 kb
Host smart-3f87d9a2-7ff3-4860-b898-78493e3f1cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30006
03687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.3000603687
Directory /workspace/37.usbdev_setup_stage/latest


Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2960243380
Short name T372
Test name
Test status
Simulation time 8404680875 ps
CPU time 8.64 seconds
Started Apr 21 04:03:34 PM PDT 24
Finished Apr 21 04:03:43 PM PDT 24
Peak memory 204040 kb
Host smart-59b86897-3075-4e92-aba0-0f8120bf58cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29602
43380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2960243380
Directory /workspace/37.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/37.usbdev_smoke.2337929096
Short name T742
Test name
Test status
Simulation time 8474387328 ps
CPU time 10.02 seconds
Started Apr 21 04:03:32 PM PDT 24
Finished Apr 21 04:03:42 PM PDT 24
Peak memory 204072 kb
Host smart-aea1e48d-172c-4d96-a56d-f1abc4550eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23379
29096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.2337929096
Directory /workspace/37.usbdev_smoke/latest


Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.4028058844
Short name T278
Test name
Test status
Simulation time 8387581981 ps
CPU time 8.87 seconds
Started Apr 21 04:03:35 PM PDT 24
Finished Apr 21 04:03:45 PM PDT 24
Peak memory 204060 kb
Host smart-c3740213-34e8-4b11-8ff8-3264b5f1d0ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40280
58844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.4028058844
Directory /workspace/37.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/37.usbdev_stall_trans.2997453628
Short name T1278
Test name
Test status
Simulation time 8492908011 ps
CPU time 9.86 seconds
Started Apr 21 04:03:38 PM PDT 24
Finished Apr 21 04:03:48 PM PDT 24
Peak memory 204060 kb
Host smart-8f14e208-fb2b-40ce-bf56-fe4a82828cd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29974
53628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.2997453628
Directory /workspace/37.usbdev_stall_trans/latest


Test location /workspace/coverage/default/38.max_length_in_transaction.1308290942
Short name T998
Test name
Test status
Simulation time 8466134236 ps
CPU time 7.69 seconds
Started Apr 21 04:03:49 PM PDT 24
Finished Apr 21 04:03:57 PM PDT 24
Peak memory 203932 kb
Host smart-2c7b70f6-0179-4cc1-b6f1-04406cef4c85
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1308290942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.1308290942
Directory /workspace/38.max_length_in_transaction/latest


Test location /workspace/coverage/default/38.min_length_in_transaction.242665750
Short name T1343
Test name
Test status
Simulation time 8377844038 ps
CPU time 8.7 seconds
Started Apr 21 04:03:48 PM PDT 24
Finished Apr 21 04:03:57 PM PDT 24
Peak memory 204220 kb
Host smart-703fc272-529d-4e0c-9d77-c03245fa7ba3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=242665750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.242665750
Directory /workspace/38.min_length_in_transaction/latest


Test location /workspace/coverage/default/38.random_length_in_trans.1517807387
Short name T680
Test name
Test status
Simulation time 8441332308 ps
CPU time 8.02 seconds
Started Apr 21 04:03:47 PM PDT 24
Finished Apr 21 04:03:55 PM PDT 24
Peak memory 204020 kb
Host smart-26d7252f-d506-45d7-b430-f6e534d30409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15178
07387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.1517807387
Directory /workspace/38.random_length_in_trans/latest


Test location /workspace/coverage/default/38.usbdev_av_buffer.2008007579
Short name T1316
Test name
Test status
Simulation time 8397710773 ps
CPU time 10.1 seconds
Started Apr 21 04:03:40 PM PDT 24
Finished Apr 21 04:03:51 PM PDT 24
Peak memory 204084 kb
Host smart-841ed649-88d5-4015-8d48-f3a95381ffd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20080
07579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.2008007579
Directory /workspace/38.usbdev_av_buffer/latest


Test location /workspace/coverage/default/38.usbdev_enable.4141229554
Short name T929
Test name
Test status
Simulation time 8395750332 ps
CPU time 7.99 seconds
Started Apr 21 04:03:41 PM PDT 24
Finished Apr 21 04:03:49 PM PDT 24
Peak memory 203936 kb
Host smart-57efac07-b6e6-4efa-abe3-bb6aa15d8871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41412
29554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.4141229554
Directory /workspace/38.usbdev_enable/latest


Test location /workspace/coverage/default/38.usbdev_fifo_rst.2988214232
Short name T729
Test name
Test status
Simulation time 201468562 ps
CPU time 2.08 seconds
Started Apr 21 04:03:44 PM PDT 24
Finished Apr 21 04:03:47 PM PDT 24
Peak memory 204168 kb
Host smart-6272ed51-8242-45e0-b5cc-b1690e204e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29882
14232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2988214232
Directory /workspace/38.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/38.usbdev_in_iso.2811570894
Short name T1133
Test name
Test status
Simulation time 8451320787 ps
CPU time 9.27 seconds
Started Apr 21 04:03:47 PM PDT 24
Finished Apr 21 04:03:57 PM PDT 24
Peak memory 204040 kb
Host smart-245fba8c-7b04-4cca-aaf2-6d90a2b1cab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28115
70894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2811570894
Directory /workspace/38.usbdev_in_iso/latest


Test location /workspace/coverage/default/38.usbdev_in_stall.1823797320
Short name T76
Test name
Test status
Simulation time 8387013390 ps
CPU time 7.59 seconds
Started Apr 21 04:03:48 PM PDT 24
Finished Apr 21 04:03:57 PM PDT 24
Peak memory 204072 kb
Host smart-1068e46b-ba2c-4b4b-96b3-9f0c01fb76c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18237
97320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.1823797320
Directory /workspace/38.usbdev_in_stall/latest


Test location /workspace/coverage/default/38.usbdev_in_trans.3387719243
Short name T140
Test name
Test status
Simulation time 8442577512 ps
CPU time 9.72 seconds
Started Apr 21 04:03:44 PM PDT 24
Finished Apr 21 04:03:54 PM PDT 24
Peak memory 204024 kb
Host smart-b7669fe3-c5eb-43e3-a24c-aea50095d541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33877
19243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.3387719243
Directory /workspace/38.usbdev_in_trans/latest


Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.2780134364
Short name T486
Test name
Test status
Simulation time 8418253050 ps
CPU time 10.64 seconds
Started Apr 21 04:03:42 PM PDT 24
Finished Apr 21 04:03:53 PM PDT 24
Peak memory 204068 kb
Host smart-f09a6269-237c-43a6-84b9-9570ddcbbae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27801
34364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.2780134364
Directory /workspace/38.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3905396418
Short name T451
Test name
Test status
Simulation time 8372262058 ps
CPU time 8.12 seconds
Started Apr 21 04:03:44 PM PDT 24
Finished Apr 21 04:03:52 PM PDT 24
Peak memory 204044 kb
Host smart-408395b7-54ff-4b9d-a595-e3beffd2009a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39053
96418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3905396418
Directory /workspace/38.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/38.usbdev_nak_trans.1274841128
Short name T615
Test name
Test status
Simulation time 8460642434 ps
CPU time 8.07 seconds
Started Apr 21 04:03:44 PM PDT 24
Finished Apr 21 04:03:52 PM PDT 24
Peak memory 204064 kb
Host smart-58e43764-d45e-4748-bea3-f324529010fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12748
41128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.1274841128
Directory /workspace/38.usbdev_nak_trans/latest


Test location /workspace/coverage/default/38.usbdev_out_stall.2780897622
Short name T1194
Test name
Test status
Simulation time 8380978164 ps
CPU time 8.91 seconds
Started Apr 21 04:03:44 PM PDT 24
Finished Apr 21 04:03:53 PM PDT 24
Peak memory 204084 kb
Host smart-9dbdc687-8899-492b-a6e8-45f0139d4b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27808
97622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2780897622
Directory /workspace/38.usbdev_out_stall/latest


Test location /workspace/coverage/default/38.usbdev_out_trans_nak.3874368858
Short name T435
Test name
Test status
Simulation time 8402133259 ps
CPU time 7.55 seconds
Started Apr 21 04:03:43 PM PDT 24
Finished Apr 21 04:03:51 PM PDT 24
Peak memory 204060 kb
Host smart-4dcf7ef4-04c8-44c2-a63b-2f2658cbd48d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38743
68858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.3874368858
Directory /workspace/38.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/38.usbdev_pending_in_trans.1157720492
Short name T1113
Test name
Test status
Simulation time 8410254909 ps
CPU time 9.6 seconds
Started Apr 21 04:03:48 PM PDT 24
Finished Apr 21 04:03:58 PM PDT 24
Peak memory 204044 kb
Host smart-53b8d550-23fb-4331-97fe-69981af0a6d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11577
20492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.1157720492
Directory /workspace/38.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.2834120269
Short name T1159
Test name
Test status
Simulation time 8375615602 ps
CPU time 8.25 seconds
Started Apr 21 04:03:48 PM PDT 24
Finished Apr 21 04:03:57 PM PDT 24
Peak memory 204080 kb
Host smart-e46834f7-1a81-4839-9054-c95f34a3656e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28341
20269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.2834120269
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.2361227687
Short name T1019
Test name
Test status
Simulation time 48908744 ps
CPU time 0.71 seconds
Started Apr 21 04:03:50 PM PDT 24
Finished Apr 21 04:03:51 PM PDT 24
Peak memory 203936 kb
Host smart-ebf9fb74-0d6e-41e8-a7e6-467f3921c795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23612
27687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.2361227687
Directory /workspace/38.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/38.usbdev_pkt_buffer.2423010762
Short name T1039
Test name
Test status
Simulation time 18841237583 ps
CPU time 35.67 seconds
Started Apr 21 04:03:42 PM PDT 24
Finished Apr 21 04:04:18 PM PDT 24
Peak memory 204276 kb
Host smart-d2c6ae32-fe19-49a0-9b59-c4378bef04aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24230
10762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.2423010762
Directory /workspace/38.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/38.usbdev_pkt_received.2248921307
Short name T288
Test name
Test status
Simulation time 8400529654 ps
CPU time 8.54 seconds
Started Apr 21 04:03:43 PM PDT 24
Finished Apr 21 04:03:52 PM PDT 24
Peak memory 204044 kb
Host smart-3698a9d0-3fd4-466d-9023-44239c0f3908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22489
21307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.2248921307
Directory /workspace/38.usbdev_pkt_received/latest


Test location /workspace/coverage/default/38.usbdev_pkt_sent.3893190039
Short name T1080
Test name
Test status
Simulation time 8439558203 ps
CPU time 7.84 seconds
Started Apr 21 04:03:46 PM PDT 24
Finished Apr 21 04:03:54 PM PDT 24
Peak memory 204020 kb
Host smart-f9c1f3ba-899b-4be8-927a-424e99ee2411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38931
90039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.3893190039
Directory /workspace/38.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.3363973988
Short name T1037
Test name
Test status
Simulation time 8375663052 ps
CPU time 8.87 seconds
Started Apr 21 04:03:44 PM PDT 24
Finished Apr 21 04:03:53 PM PDT 24
Peak memory 204084 kb
Host smart-85ce20ac-300c-40b1-b448-eac61c845809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33639
73988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.3363973988
Directory /workspace/38.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/38.usbdev_setup_stage.3404761171
Short name T172
Test name
Test status
Simulation time 8381289511 ps
CPU time 7.8 seconds
Started Apr 21 04:03:49 PM PDT 24
Finished Apr 21 04:03:57 PM PDT 24
Peak memory 204064 kb
Host smart-cc9e9f70-cda4-4c33-ac8c-fa8e69d463f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34047
61171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.3404761171
Directory /workspace/38.usbdev_setup_stage/latest


Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.529793672
Short name T1360
Test name
Test status
Simulation time 8368044242 ps
CPU time 7.79 seconds
Started Apr 21 04:03:45 PM PDT 24
Finished Apr 21 04:03:53 PM PDT 24
Peak memory 204056 kb
Host smart-3c23cc28-bec7-444e-988b-c656984eb4a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52979
3672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.529793672
Directory /workspace/38.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/38.usbdev_smoke.1497157639
Short name T908
Test name
Test status
Simulation time 8424458301 ps
CPU time 7.87 seconds
Started Apr 21 04:03:41 PM PDT 24
Finished Apr 21 04:03:49 PM PDT 24
Peak memory 204052 kb
Host smart-8725fcb4-ecf6-4d06-bfc3-e7fe10e80e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14971
57639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.1497157639
Directory /workspace/38.usbdev_smoke/latest


Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.987417012
Short name T910
Test name
Test status
Simulation time 8406595113 ps
CPU time 8.21 seconds
Started Apr 21 04:03:48 PM PDT 24
Finished Apr 21 04:03:57 PM PDT 24
Peak memory 204040 kb
Host smart-53e68c77-bf5e-4ebf-ad59-68e3a3df863c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98741
7012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.987417012
Directory /workspace/38.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/38.usbdev_stall_trans.1680082803
Short name T452
Test name
Test status
Simulation time 8377307170 ps
CPU time 8.2 seconds
Started Apr 21 04:03:46 PM PDT 24
Finished Apr 21 04:03:54 PM PDT 24
Peak memory 204060 kb
Host smart-a5aeb590-a6fd-454f-901b-07dc37321c9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16800
82803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.1680082803
Directory /workspace/38.usbdev_stall_trans/latest


Test location /workspace/coverage/default/39.max_length_in_transaction.273125575
Short name T915
Test name
Test status
Simulation time 8470248348 ps
CPU time 9.33 seconds
Started Apr 21 04:04:00 PM PDT 24
Finished Apr 21 04:04:10 PM PDT 24
Peak memory 204020 kb
Host smart-420a1a9b-3732-4256-92bf-f044273dc4ec
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=273125575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.273125575
Directory /workspace/39.max_length_in_transaction/latest


Test location /workspace/coverage/default/39.min_length_in_transaction.4019940496
Short name T460
Test name
Test status
Simulation time 8372126486 ps
CPU time 8.91 seconds
Started Apr 21 04:04:00 PM PDT 24
Finished Apr 21 04:04:09 PM PDT 24
Peak memory 204024 kb
Host smart-7b22b0d0-2522-4b85-8e1d-c0e317a53833
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4019940496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.4019940496
Directory /workspace/39.min_length_in_transaction/latest


Test location /workspace/coverage/default/39.random_length_in_trans.551087234
Short name T748
Test name
Test status
Simulation time 8394047146 ps
CPU time 8.19 seconds
Started Apr 21 04:03:58 PM PDT 24
Finished Apr 21 04:04:07 PM PDT 24
Peak memory 204080 kb
Host smart-ab75c943-3e55-46f4-81f3-c3bb476ac715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55108
7234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.551087234
Directory /workspace/39.random_length_in_trans/latest


Test location /workspace/coverage/default/39.usbdev_av_buffer.1228203307
Short name T956
Test name
Test status
Simulation time 8389160263 ps
CPU time 7.4 seconds
Started Apr 21 04:03:56 PM PDT 24
Finished Apr 21 04:04:04 PM PDT 24
Peak memory 204072 kb
Host smart-1903fdcd-40b5-4782-a290-ad42d6c6b36d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12282
03307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1228203307
Directory /workspace/39.usbdev_av_buffer/latest


Test location /workspace/coverage/default/39.usbdev_enable.1347539085
Short name T1329
Test name
Test status
Simulation time 8404985033 ps
CPU time 7.94 seconds
Started Apr 21 04:03:50 PM PDT 24
Finished Apr 21 04:03:59 PM PDT 24
Peak memory 204028 kb
Host smart-3f6202ea-007a-4996-82f4-1005b3a583c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13475
39085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.1347539085
Directory /workspace/39.usbdev_enable/latest


Test location /workspace/coverage/default/39.usbdev_fifo_rst.895474954
Short name T1211
Test name
Test status
Simulation time 95701291 ps
CPU time 1.45 seconds
Started Apr 21 04:03:50 PM PDT 24
Finished Apr 21 04:03:52 PM PDT 24
Peak memory 204160 kb
Host smart-44c24ad1-5b6c-44ef-8b98-adc5473a07ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89547
4954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.895474954
Directory /workspace/39.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/39.usbdev_in_iso.3726818101
Short name T375
Test name
Test status
Simulation time 8403430798 ps
CPU time 7.78 seconds
Started Apr 21 04:04:01 PM PDT 24
Finished Apr 21 04:04:09 PM PDT 24
Peak memory 204064 kb
Host smart-b0ff401e-8199-4c75-8c8c-7fdca6656279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37268
18101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.3726818101
Directory /workspace/39.usbdev_in_iso/latest


Test location /workspace/coverage/default/39.usbdev_in_stall.3392621700
Short name T1140
Test name
Test status
Simulation time 8380480932 ps
CPU time 7.47 seconds
Started Apr 21 04:03:58 PM PDT 24
Finished Apr 21 04:04:06 PM PDT 24
Peak memory 204064 kb
Host smart-31d90099-b620-438c-8666-798b2d1152d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33926
21700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.3392621700
Directory /workspace/39.usbdev_in_stall/latest


Test location /workspace/coverage/default/39.usbdev_in_trans.3456241056
Short name T84
Test name
Test status
Simulation time 8439856689 ps
CPU time 8.63 seconds
Started Apr 21 04:03:58 PM PDT 24
Finished Apr 21 04:04:07 PM PDT 24
Peak memory 204068 kb
Host smart-6650a7cd-a9bd-4793-868e-43a9ff522b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34562
41056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3456241056
Directory /workspace/39.usbdev_in_trans/latest


Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.214010257
Short name T751
Test name
Test status
Simulation time 8443621697 ps
CPU time 8.25 seconds
Started Apr 21 04:04:01 PM PDT 24
Finished Apr 21 04:04:10 PM PDT 24
Peak memory 204040 kb
Host smart-f3976bed-a9f5-4e5a-9754-241b04dccfa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21401
0257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.214010257
Directory /workspace/39.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.450493179
Short name T1312
Test name
Test status
Simulation time 8450714749 ps
CPU time 8.6 seconds
Started Apr 21 04:03:59 PM PDT 24
Finished Apr 21 04:04:08 PM PDT 24
Peak memory 204064 kb
Host smart-28d74449-cdae-4018-83a8-f96e1f9d3e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45049
3179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.450493179
Directory /workspace/39.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/39.usbdev_nak_trans.848653703
Short name T1077
Test name
Test status
Simulation time 8423024432 ps
CPU time 8.93 seconds
Started Apr 21 04:03:51 PM PDT 24
Finished Apr 21 04:04:00 PM PDT 24
Peak memory 204028 kb
Host smart-42f8588d-a2b9-4af0-a6b9-649b72591e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84865
3703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.848653703
Directory /workspace/39.usbdev_nak_trans/latest


Test location /workspace/coverage/default/39.usbdev_out_stall.836085652
Short name T387
Test name
Test status
Simulation time 8386706602 ps
CPU time 8.32 seconds
Started Apr 21 04:03:51 PM PDT 24
Finished Apr 21 04:03:59 PM PDT 24
Peak memory 204044 kb
Host smart-d90473e8-f626-4723-9a0b-49c30c01515a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83608
5652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.836085652
Directory /workspace/39.usbdev_out_stall/latest


Test location /workspace/coverage/default/39.usbdev_out_trans_nak.4028152427
Short name T27
Test name
Test status
Simulation time 8407382639 ps
CPU time 8.46 seconds
Started Apr 21 04:04:00 PM PDT 24
Finished Apr 21 04:04:09 PM PDT 24
Peak memory 204040 kb
Host smart-a199912a-d086-4bfa-ac02-7fe175046d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40281
52427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.4028152427
Directory /workspace/39.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/39.usbdev_pending_in_trans.2454528187
Short name T183
Test name
Test status
Simulation time 8413147308 ps
CPU time 8.78 seconds
Started Apr 21 04:04:01 PM PDT 24
Finished Apr 21 04:04:10 PM PDT 24
Peak memory 204060 kb
Host smart-3db04a10-00f7-4e1d-86e6-389615f8fa30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24545
28187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.2454528187
Directory /workspace/39.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.2430309463
Short name T1347
Test name
Test status
Simulation time 8361686824 ps
CPU time 7.94 seconds
Started Apr 21 04:03:58 PM PDT 24
Finished Apr 21 04:04:07 PM PDT 24
Peak memory 204056 kb
Host smart-cc360d75-c252-48e6-ae32-085b9f693cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24303
09463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.2430309463
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3820704640
Short name T669
Test name
Test status
Simulation time 39751329 ps
CPU time 0.71 seconds
Started Apr 21 04:03:59 PM PDT 24
Finished Apr 21 04:04:00 PM PDT 24
Peak memory 203912 kb
Host smart-0c3ec53c-62b6-4325-ac05-403a03dabdd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38207
04640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3820704640
Directory /workspace/39.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/39.usbdev_pkt_buffer.2241657352
Short name T1367
Test name
Test status
Simulation time 15257327452 ps
CPU time 27.28 seconds
Started Apr 21 04:03:59 PM PDT 24
Finished Apr 21 04:04:27 PM PDT 24
Peak memory 204308 kb
Host smart-9c5661ed-b725-454c-915b-2940b7c76932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22416
57352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.2241657352
Directory /workspace/39.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/39.usbdev_pkt_received.4176099334
Short name T1242
Test name
Test status
Simulation time 8398314606 ps
CPU time 9.15 seconds
Started Apr 21 04:04:00 PM PDT 24
Finished Apr 21 04:04:10 PM PDT 24
Peak memory 204064 kb
Host smart-77120632-eef8-4bd3-bd7e-5a970ee0aaa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41760
99334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.4176099334
Directory /workspace/39.usbdev_pkt_received/latest


Test location /workspace/coverage/default/39.usbdev_pkt_sent.608865647
Short name T18
Test name
Test status
Simulation time 8420853279 ps
CPU time 8.57 seconds
Started Apr 21 04:03:58 PM PDT 24
Finished Apr 21 04:04:06 PM PDT 24
Peak memory 204068 kb
Host smart-50d1db05-799a-4ec7-a02d-76e4f8f20429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60886
5647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.608865647
Directory /workspace/39.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.3718263654
Short name T982
Test name
Test status
Simulation time 8418813780 ps
CPU time 8.41 seconds
Started Apr 21 04:03:59 PM PDT 24
Finished Apr 21 04:04:08 PM PDT 24
Peak memory 204084 kb
Host smart-2a306ca9-d26d-4329-9acc-3b4bc31654fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37182
63654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.3718263654
Directory /workspace/39.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/39.usbdev_setup_stage.3162382258
Short name T482
Test name
Test status
Simulation time 8375431617 ps
CPU time 8.38 seconds
Started Apr 21 04:03:53 PM PDT 24
Finished Apr 21 04:04:02 PM PDT 24
Peak memory 204052 kb
Host smart-c6fa202b-58d9-4273-84bf-e1563602875b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31623
82258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.3162382258
Directory /workspace/39.usbdev_setup_stage/latest


Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.126908488
Short name T1313
Test name
Test status
Simulation time 8366798851 ps
CPU time 8.51 seconds
Started Apr 21 04:03:57 PM PDT 24
Finished Apr 21 04:04:05 PM PDT 24
Peak memory 203956 kb
Host smart-9c5f9ca8-e83a-4683-8606-f061a79185eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12690
8488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.126908488
Directory /workspace/39.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/39.usbdev_smoke.3365952946
Short name T647
Test name
Test status
Simulation time 8446533885 ps
CPU time 9.44 seconds
Started Apr 21 04:03:47 PM PDT 24
Finished Apr 21 04:03:57 PM PDT 24
Peak memory 203968 kb
Host smart-80d582d6-8c2c-48dc-b9ce-00052f762c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33659
52946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3365952946
Directory /workspace/39.usbdev_smoke/latest


Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.249257586
Short name T549
Test name
Test status
Simulation time 8505776376 ps
CPU time 7.75 seconds
Started Apr 21 04:03:58 PM PDT 24
Finished Apr 21 04:04:06 PM PDT 24
Peak memory 204060 kb
Host smart-175e0f15-e48c-4d3b-83a4-0b7a15bb78c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24925
7586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.249257586
Directory /workspace/39.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/39.usbdev_stall_trans.3956028917
Short name T1012
Test name
Test status
Simulation time 8388367609 ps
CPU time 7.99 seconds
Started Apr 21 04:03:58 PM PDT 24
Finished Apr 21 04:04:06 PM PDT 24
Peak memory 204056 kb
Host smart-2c010377-c738-4ef8-a806-02adf58f8989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39560
28917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.3956028917
Directory /workspace/39.usbdev_stall_trans/latest


Test location /workspace/coverage/default/4.max_length_in_transaction.2211066976
Short name T906
Test name
Test status
Simulation time 8491151010 ps
CPU time 7.8 seconds
Started Apr 21 03:57:58 PM PDT 24
Finished Apr 21 03:58:06 PM PDT 24
Peak memory 204084 kb
Host smart-c48d7801-379d-4464-9023-872a665e97e6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2211066976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.2211066976
Directory /workspace/4.max_length_in_transaction/latest


Test location /workspace/coverage/default/4.min_length_in_transaction.4019835323
Short name T1027
Test name
Test status
Simulation time 8396784145 ps
CPU time 7.61 seconds
Started Apr 21 03:57:58 PM PDT 24
Finished Apr 21 03:58:05 PM PDT 24
Peak memory 204036 kb
Host smart-310e5875-8c05-4941-b261-5d46686e8b20
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4019835323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.4019835323
Directory /workspace/4.min_length_in_transaction/latest


Test location /workspace/coverage/default/4.random_length_in_trans.2500718188
Short name T756
Test name
Test status
Simulation time 8423388643 ps
CPU time 7.96 seconds
Started Apr 21 03:57:57 PM PDT 24
Finished Apr 21 03:58:05 PM PDT 24
Peak memory 203992 kb
Host smart-acda19af-d518-49fc-a23e-b8823a8594f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25007
18188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.2500718188
Directory /workspace/4.random_length_in_trans/latest


Test location /workspace/coverage/default/4.usbdev_av_buffer.3930878543
Short name T779
Test name
Test status
Simulation time 8379269586 ps
CPU time 8.07 seconds
Started Apr 21 03:57:46 PM PDT 24
Finished Apr 21 03:57:54 PM PDT 24
Peak memory 204060 kb
Host smart-f52269a2-1cca-49c8-9930-0259ea6e2bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39308
78543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.3930878543
Directory /workspace/4.usbdev_av_buffer/latest


Test location /workspace/coverage/default/4.usbdev_enable.4016576291
Short name T1155
Test name
Test status
Simulation time 8380031083 ps
CPU time 7.49 seconds
Started Apr 21 03:57:48 PM PDT 24
Finished Apr 21 03:57:56 PM PDT 24
Peak memory 204224 kb
Host smart-30f2ee7e-81f4-4d64-85ae-f4075a65f992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40165
76291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.4016576291
Directory /workspace/4.usbdev_enable/latest


Test location /workspace/coverage/default/4.usbdev_fifo_rst.511645280
Short name T1341
Test name
Test status
Simulation time 90495353 ps
CPU time 2.05 seconds
Started Apr 21 03:57:49 PM PDT 24
Finished Apr 21 03:57:51 PM PDT 24
Peak memory 204172 kb
Host smart-b963e44b-f0db-47b8-9d87-31bf3d81f92c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51164
5280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.511645280
Directory /workspace/4.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/4.usbdev_in_iso.3973663043
Short name T734
Test name
Test status
Simulation time 8408637108 ps
CPU time 9.27 seconds
Started Apr 21 03:57:57 PM PDT 24
Finished Apr 21 03:58:07 PM PDT 24
Peak memory 204064 kb
Host smart-560a8389-a40c-4748-8cad-f717cdd42930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39736
63043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.3973663043
Directory /workspace/4.usbdev_in_iso/latest


Test location /workspace/coverage/default/4.usbdev_in_stall.286432026
Short name T189
Test name
Test status
Simulation time 8372557012 ps
CPU time 9.09 seconds
Started Apr 21 03:57:58 PM PDT 24
Finished Apr 21 03:58:07 PM PDT 24
Peak memory 204060 kb
Host smart-ae805dc7-1116-4f2b-965a-24c386bb537e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28643
2026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.286432026
Directory /workspace/4.usbdev_in_stall/latest


Test location /workspace/coverage/default/4.usbdev_in_trans.3321795251
Short name T141
Test name
Test status
Simulation time 8408298376 ps
CPU time 7.69 seconds
Started Apr 21 03:57:48 PM PDT 24
Finished Apr 21 03:57:56 PM PDT 24
Peak memory 204056 kb
Host smart-96a57741-5c12-49a2-be2b-9db532be6d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33217
95251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.3321795251
Directory /workspace/4.usbdev_in_trans/latest


Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.2192323102
Short name T1218
Test name
Test status
Simulation time 8427474947 ps
CPU time 7.5 seconds
Started Apr 21 03:57:49 PM PDT 24
Finished Apr 21 03:57:56 PM PDT 24
Peak memory 204064 kb
Host smart-b529cc11-f180-4380-b695-837511513e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21923
23102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.2192323102
Directory /workspace/4.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.870125595
Short name T965
Test name
Test status
Simulation time 8367693338 ps
CPU time 7.59 seconds
Started Apr 21 03:57:49 PM PDT 24
Finished Apr 21 03:57:57 PM PDT 24
Peak memory 204052 kb
Host smart-601de43f-66b9-415d-8fa5-3211e026b468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87012
5595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.870125595
Directory /workspace/4.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/4.usbdev_nak_trans.4049371356
Short name T135
Test name
Test status
Simulation time 8403050674 ps
CPU time 8 seconds
Started Apr 21 03:57:50 PM PDT 24
Finished Apr 21 03:57:59 PM PDT 24
Peak memory 204036 kb
Host smart-43662561-f5bf-4afd-834d-7863a45ff0c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40493
71356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.4049371356
Directory /workspace/4.usbdev_nak_trans/latest


Test location /workspace/coverage/default/4.usbdev_out_stall.2055872519
Short name T591
Test name
Test status
Simulation time 8412766254 ps
CPU time 7.85 seconds
Started Apr 21 03:57:50 PM PDT 24
Finished Apr 21 03:57:58 PM PDT 24
Peak memory 204060 kb
Host smart-a1754905-89e0-4947-9476-3373c37f7888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20558
72519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2055872519
Directory /workspace/4.usbdev_out_stall/latest


Test location /workspace/coverage/default/4.usbdev_out_trans_nak.1079880038
Short name T1063
Test name
Test status
Simulation time 8422202155 ps
CPU time 9.36 seconds
Started Apr 21 03:57:53 PM PDT 24
Finished Apr 21 03:58:02 PM PDT 24
Peak memory 204084 kb
Host smart-761c1eeb-a68f-4560-b313-d428393585b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10798
80038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.1079880038
Directory /workspace/4.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/4.usbdev_pending_in_trans.3331883371
Short name T792
Test name
Test status
Simulation time 8478989932 ps
CPU time 7.76 seconds
Started Apr 21 03:57:53 PM PDT 24
Finished Apr 21 03:58:01 PM PDT 24
Peak memory 203952 kb
Host smart-cadc6448-f632-4a3f-994a-1d8f2a76a699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33318
83371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.3331883371
Directory /workspace/4.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.2201455843
Short name T296
Test name
Test status
Simulation time 8371342089 ps
CPU time 8.25 seconds
Started Apr 21 03:57:54 PM PDT 24
Finished Apr 21 03:58:02 PM PDT 24
Peak memory 204076 kb
Host smart-f8e686c8-90ba-406d-8104-ae51b293e06b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22014
55843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.2201455843
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.2066490028
Short name T43
Test name
Test status
Simulation time 37379248 ps
CPU time 0.65 seconds
Started Apr 21 03:57:58 PM PDT 24
Finished Apr 21 03:57:59 PM PDT 24
Peak memory 203932 kb
Host smart-2fb48491-f76e-4385-ae4b-7a932279c704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20664
90028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.2066490028
Directory /workspace/4.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/4.usbdev_pkt_buffer.4181194834
Short name T1381
Test name
Test status
Simulation time 17201516948 ps
CPU time 32.02 seconds
Started Apr 21 03:57:50 PM PDT 24
Finished Apr 21 03:58:22 PM PDT 24
Peak memory 204324 kb
Host smart-c618f15c-6d2a-4f72-98b2-8dd877c23b74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41811
94834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.4181194834
Directory /workspace/4.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/4.usbdev_pkt_received.2750529935
Short name T316
Test name
Test status
Simulation time 8412010759 ps
CPU time 8.4 seconds
Started Apr 21 03:57:52 PM PDT 24
Finished Apr 21 03:58:01 PM PDT 24
Peak memory 204048 kb
Host smart-1b6e72b8-73ab-4778-a366-d3a6ce4c93b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27505
29935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.2750529935
Directory /workspace/4.usbdev_pkt_received/latest


Test location /workspace/coverage/default/4.usbdev_pkt_sent.21237950
Short name T1068
Test name
Test status
Simulation time 8422823129 ps
CPU time 7.91 seconds
Started Apr 21 03:57:53 PM PDT 24
Finished Apr 21 03:58:01 PM PDT 24
Peak memory 204036 kb
Host smart-366b478b-d69b-42dc-a48c-a3a2704dffcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21237
950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.21237950
Directory /workspace/4.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.2347417448
Short name T292
Test name
Test status
Simulation time 8407930780 ps
CPU time 9.87 seconds
Started Apr 21 03:57:51 PM PDT 24
Finished Apr 21 03:58:01 PM PDT 24
Peak memory 204060 kb
Host smart-e85f1b6a-d091-49a9-8789-7072645103d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23474
17448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.2347417448
Directory /workspace/4.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/4.usbdev_sec_cm.2288789968
Short name T61
Test name
Test status
Simulation time 233124929 ps
CPU time 1.12 seconds
Started Apr 21 03:57:57 PM PDT 24
Finished Apr 21 03:57:59 PM PDT 24
Peak memory 220264 kb
Host smart-be54e633-97ef-4703-a20d-f07e9f3ecb31
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2288789968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2288789968
Directory /workspace/4.usbdev_sec_cm/latest


Test location /workspace/coverage/default/4.usbdev_setup_stage.2575347928
Short name T1178
Test name
Test status
Simulation time 8380078073 ps
CPU time 7.67 seconds
Started Apr 21 03:57:55 PM PDT 24
Finished Apr 21 03:58:03 PM PDT 24
Peak memory 204064 kb
Host smart-39342554-6e5b-48b3-86be-a91acf22cb32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25753
47928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.2575347928
Directory /workspace/4.usbdev_setup_stage/latest


Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.1052148567
Short name T1244
Test name
Test status
Simulation time 8375181299 ps
CPU time 8.62 seconds
Started Apr 21 03:57:52 PM PDT 24
Finished Apr 21 03:58:01 PM PDT 24
Peak memory 204084 kb
Host smart-0caa3614-8e71-4d11-858a-4fef03b53d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10521
48567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.1052148567
Directory /workspace/4.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/4.usbdev_smoke.4240719119
Short name T720
Test name
Test status
Simulation time 8457209633 ps
CPU time 8.66 seconds
Started Apr 21 03:57:46 PM PDT 24
Finished Apr 21 03:57:55 PM PDT 24
Peak memory 204064 kb
Host smart-50869f33-53d0-4d28-a584-3ab17745b9b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42407
19119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.4240719119
Directory /workspace/4.usbdev_smoke/latest


Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.2528599641
Short name T766
Test name
Test status
Simulation time 8397590425 ps
CPU time 8.09 seconds
Started Apr 21 03:57:51 PM PDT 24
Finished Apr 21 03:58:00 PM PDT 24
Peak memory 203928 kb
Host smart-ceca8b50-fc18-4578-bb8a-00bb19ac0d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25285
99641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.2528599641
Directory /workspace/4.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/4.usbdev_stall_trans.1203028708
Short name T487
Test name
Test status
Simulation time 8425270638 ps
CPU time 7.58 seconds
Started Apr 21 03:57:51 PM PDT 24
Finished Apr 21 03:57:59 PM PDT 24
Peak memory 204064 kb
Host smart-43337723-18bd-4fdf-b4f8-f44b86c6a26e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12030
28708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1203028708
Directory /workspace/4.usbdev_stall_trans/latest


Test location /workspace/coverage/default/40.max_length_in_transaction.1758771888
Short name T47
Test name
Test status
Simulation time 8469687963 ps
CPU time 8.41 seconds
Started Apr 21 04:04:01 PM PDT 24
Finished Apr 21 04:04:10 PM PDT 24
Peak memory 204056 kb
Host smart-795946f9-fd5a-445f-b505-c6881842449a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1758771888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.1758771888
Directory /workspace/40.max_length_in_transaction/latest


Test location /workspace/coverage/default/40.min_length_in_transaction.1971299578
Short name T789
Test name
Test status
Simulation time 8392339892 ps
CPU time 8.23 seconds
Started Apr 21 04:04:02 PM PDT 24
Finished Apr 21 04:04:11 PM PDT 24
Peak memory 204000 kb
Host smart-0fa68eef-2a41-4efe-8ced-21ef3a25a549
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1971299578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.1971299578
Directory /workspace/40.min_length_in_transaction/latest


Test location /workspace/coverage/default/40.random_length_in_trans.2494175120
Short name T739
Test name
Test status
Simulation time 8429991951 ps
CPU time 8.23 seconds
Started Apr 21 04:04:00 PM PDT 24
Finished Apr 21 04:04:08 PM PDT 24
Peak memory 204060 kb
Host smart-105e6feb-d9a9-48a0-a456-eb22d329c8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24941
75120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.2494175120
Directory /workspace/40.random_length_in_trans/latest


Test location /workspace/coverage/default/40.usbdev_av_buffer.160394114
Short name T586
Test name
Test status
Simulation time 8371830347 ps
CPU time 8.04 seconds
Started Apr 21 04:04:00 PM PDT 24
Finished Apr 21 04:04:09 PM PDT 24
Peak memory 204084 kb
Host smart-3b5599ef-a501-49bd-8314-5b3138abc447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16039
4114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.160394114
Directory /workspace/40.usbdev_av_buffer/latest


Test location /workspace/coverage/default/40.usbdev_enable.212159486
Short name T777
Test name
Test status
Simulation time 8374809090 ps
CPU time 8.68 seconds
Started Apr 21 04:03:59 PM PDT 24
Finished Apr 21 04:04:08 PM PDT 24
Peak memory 204076 kb
Host smart-9d549eb2-82c2-4c0c-8139-c5ec278a2d91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21215
9486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.212159486
Directory /workspace/40.usbdev_enable/latest


Test location /workspace/coverage/default/40.usbdev_fifo_rst.2197727313
Short name T1210
Test name
Test status
Simulation time 79505727 ps
CPU time 1.22 seconds
Started Apr 21 04:04:01 PM PDT 24
Finished Apr 21 04:04:02 PM PDT 24
Peak memory 204196 kb
Host smart-5e6c3a9b-9834-48ae-8e14-9fb85daba568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21977
27313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2197727313
Directory /workspace/40.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/40.usbdev_in_iso.2356192276
Short name T822
Test name
Test status
Simulation time 8424187494 ps
CPU time 7.82 seconds
Started Apr 21 04:04:04 PM PDT 24
Finished Apr 21 04:04:12 PM PDT 24
Peak memory 204044 kb
Host smart-2de3d80e-c665-484d-ab52-9c455bb075ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23561
92276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.2356192276
Directory /workspace/40.usbdev_in_iso/latest


Test location /workspace/coverage/default/40.usbdev_in_stall.1301890894
Short name T791
Test name
Test status
Simulation time 8368046175 ps
CPU time 9.74 seconds
Started Apr 21 04:04:04 PM PDT 24
Finished Apr 21 04:04:14 PM PDT 24
Peak memory 204024 kb
Host smart-3c1059bc-039a-495e-84a0-187f676ad43c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13018
90894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.1301890894
Directory /workspace/40.usbdev_in_stall/latest


Test location /workspace/coverage/default/40.usbdev_in_trans.1817313635
Short name T658
Test name
Test status
Simulation time 8432775164 ps
CPU time 8.29 seconds
Started Apr 21 04:04:00 PM PDT 24
Finished Apr 21 04:04:09 PM PDT 24
Peak memory 204036 kb
Host smart-f63f5b6a-7a91-4456-ac0c-14249ed2632c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18173
13635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1817313635
Directory /workspace/40.usbdev_in_trans/latest


Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.2872515251
Short name T616
Test name
Test status
Simulation time 8422859831 ps
CPU time 7.93 seconds
Started Apr 21 04:04:01 PM PDT 24
Finished Apr 21 04:04:09 PM PDT 24
Peak memory 204040 kb
Host smart-10859e02-4637-41da-bb51-7e888ca42c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28725
15251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.2872515251
Directory /workspace/40.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.4184952055
Short name T1236
Test name
Test status
Simulation time 8372641171 ps
CPU time 7.83 seconds
Started Apr 21 04:03:58 PM PDT 24
Finished Apr 21 04:04:06 PM PDT 24
Peak memory 204224 kb
Host smart-a9bbad94-51b7-43de-9000-4a540bbf6c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41849
52055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.4184952055
Directory /workspace/40.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/40.usbdev_out_stall.1933710352
Short name T861
Test name
Test status
Simulation time 8385915887 ps
CPU time 8.48 seconds
Started Apr 21 04:04:00 PM PDT 24
Finished Apr 21 04:04:09 PM PDT 24
Peak memory 204064 kb
Host smart-5a32af07-3162-4a96-b965-9e9d83e5c19f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19337
10352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.1933710352
Directory /workspace/40.usbdev_out_stall/latest


Test location /workspace/coverage/default/40.usbdev_out_trans_nak.2881696147
Short name T607
Test name
Test status
Simulation time 8393419167 ps
CPU time 7.88 seconds
Started Apr 21 04:03:58 PM PDT 24
Finished Apr 21 04:04:07 PM PDT 24
Peak memory 204020 kb
Host smart-c00f4a15-b8e2-4f3d-9729-6f20307bf77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28816
96147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2881696147
Directory /workspace/40.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/40.usbdev_pending_in_trans.871563601
Short name T176
Test name
Test status
Simulation time 8463816199 ps
CPU time 7.83 seconds
Started Apr 21 04:04:05 PM PDT 24
Finished Apr 21 04:04:14 PM PDT 24
Peak memory 204024 kb
Host smart-990a4f7b-40c7-486c-ab1e-d1698bfd228b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87156
3601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.871563601
Directory /workspace/40.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.378817013
Short name T610
Test name
Test status
Simulation time 8374951596 ps
CPU time 8.03 seconds
Started Apr 21 04:04:03 PM PDT 24
Finished Apr 21 04:04:12 PM PDT 24
Peak memory 204044 kb
Host smart-f8dea0ee-290a-4a43-adc5-a02470851bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37881
7013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.378817013
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.4062391496
Short name T32
Test name
Test status
Simulation time 52820786 ps
CPU time 0.71 seconds
Started Apr 21 04:04:04 PM PDT 24
Finished Apr 21 04:04:05 PM PDT 24
Peak memory 203916 kb
Host smart-7ff94079-df71-4364-bc48-87044503ad05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40623
91496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.4062391496
Directory /workspace/40.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/40.usbdev_pkt_buffer.2435823807
Short name T244
Test name
Test status
Simulation time 26391479616 ps
CPU time 52.03 seconds
Started Apr 21 04:04:01 PM PDT 24
Finished Apr 21 04:04:54 PM PDT 24
Peak memory 204328 kb
Host smart-e5e50391-2386-4413-b459-6359613fa7c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24358
23807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.2435823807
Directory /workspace/40.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/40.usbdev_pkt_received.3255444263
Short name T780
Test name
Test status
Simulation time 8417678203 ps
CPU time 7.96 seconds
Started Apr 21 04:04:04 PM PDT 24
Finished Apr 21 04:04:12 PM PDT 24
Peak memory 204032 kb
Host smart-3a400d93-d249-41fd-aa2c-6f7bda373676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32554
44263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.3255444263
Directory /workspace/40.usbdev_pkt_received/latest


Test location /workspace/coverage/default/40.usbdev_pkt_sent.113227482
Short name T821
Test name
Test status
Simulation time 8533578517 ps
CPU time 7.84 seconds
Started Apr 21 04:04:00 PM PDT 24
Finished Apr 21 04:04:08 PM PDT 24
Peak memory 204068 kb
Host smart-1b1e742f-f40b-4f73-acdf-45a4491cf7cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11322
7482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.113227482
Directory /workspace/40.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.543949871
Short name T85
Test name
Test status
Simulation time 8394550390 ps
CPU time 8.65 seconds
Started Apr 21 04:03:59 PM PDT 24
Finished Apr 21 04:04:08 PM PDT 24
Peak memory 204080 kb
Host smart-17b792d5-4224-4a90-9314-2d184b1a12fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54394
9871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.543949871
Directory /workspace/40.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/40.usbdev_setup_stage.1908053378
Short name T168
Test name
Test status
Simulation time 8383539649 ps
CPU time 7.77 seconds
Started Apr 21 04:03:59 PM PDT 24
Finished Apr 21 04:04:07 PM PDT 24
Peak memory 204060 kb
Host smart-f02b1f8c-f960-492c-a6b4-bd2fd76e1b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19080
53378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.1908053378
Directory /workspace/40.usbdev_setup_stage/latest


Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.3202719874
Short name T422
Test name
Test status
Simulation time 8369340972 ps
CPU time 7.71 seconds
Started Apr 21 04:04:03 PM PDT 24
Finished Apr 21 04:04:11 PM PDT 24
Peak memory 204040 kb
Host smart-da0035cb-5b93-4203-85e4-bc05096ced3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32027
19874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.3202719874
Directory /workspace/40.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/40.usbdev_smoke.3742539514
Short name T1003
Test name
Test status
Simulation time 8487469066 ps
CPU time 10.1 seconds
Started Apr 21 04:04:01 PM PDT 24
Finished Apr 21 04:04:11 PM PDT 24
Peak memory 204064 kb
Host smart-8a7273c8-f465-4c69-b9d2-ea3cc9ec671a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37425
39514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.3742539514
Directory /workspace/40.usbdev_smoke/latest


Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.824813933
Short name T913
Test name
Test status
Simulation time 8391114184 ps
CPU time 8.1 seconds
Started Apr 21 04:04:05 PM PDT 24
Finished Apr 21 04:04:14 PM PDT 24
Peak memory 204020 kb
Host smart-43143a6f-c408-43fc-9aff-c939791c9a7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82481
3933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.824813933
Directory /workspace/40.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/40.usbdev_stall_trans.1871793077
Short name T541
Test name
Test status
Simulation time 8407107900 ps
CPU time 7.86 seconds
Started Apr 21 04:03:58 PM PDT 24
Finished Apr 21 04:04:07 PM PDT 24
Peak memory 204060 kb
Host smart-6432c1db-828c-4ccf-aa25-da98a0e3a0fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18717
93077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1871793077
Directory /workspace/40.usbdev_stall_trans/latest


Test location /workspace/coverage/default/41.max_length_in_transaction.2853512445
Short name T993
Test name
Test status
Simulation time 8498388194 ps
CPU time 8.9 seconds
Started Apr 21 04:04:09 PM PDT 24
Finished Apr 21 04:04:19 PM PDT 24
Peak memory 204072 kb
Host smart-141a1ecb-7dad-4988-9bb4-4105d41f74d8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2853512445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.2853512445
Directory /workspace/41.max_length_in_transaction/latest


Test location /workspace/coverage/default/41.min_length_in_transaction.3107526361
Short name T726
Test name
Test status
Simulation time 8422132859 ps
CPU time 8.96 seconds
Started Apr 21 04:04:12 PM PDT 24
Finished Apr 21 04:04:21 PM PDT 24
Peak memory 204068 kb
Host smart-0f908a1d-b19a-4177-98a4-b0b237fb73cd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3107526361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.3107526361
Directory /workspace/41.min_length_in_transaction/latest


Test location /workspace/coverage/default/41.random_length_in_trans.3232485356
Short name T882
Test name
Test status
Simulation time 8485789390 ps
CPU time 8.24 seconds
Started Apr 21 04:04:09 PM PDT 24
Finished Apr 21 04:04:18 PM PDT 24
Peak memory 204012 kb
Host smart-e4f83d6c-3e3c-4777-9c63-92b99e9f3ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32324
85356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.3232485356
Directory /workspace/41.random_length_in_trans/latest


Test location /workspace/coverage/default/41.usbdev_av_buffer.2501570435
Short name T307
Test name
Test status
Simulation time 8405659717 ps
CPU time 7.67 seconds
Started Apr 21 04:04:01 PM PDT 24
Finished Apr 21 04:04:09 PM PDT 24
Peak memory 204088 kb
Host smart-1d0b785a-3090-42d3-9776-097972651aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25015
70435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2501570435
Directory /workspace/41.usbdev_av_buffer/latest


Test location /workspace/coverage/default/41.usbdev_enable.2649832418
Short name T645
Test name
Test status
Simulation time 8390288178 ps
CPU time 10.31 seconds
Started Apr 21 04:04:03 PM PDT 24
Finished Apr 21 04:04:13 PM PDT 24
Peak memory 204048 kb
Host smart-f0b5cd99-169c-4d10-b3a6-253975b6d3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26498
32418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.2649832418
Directory /workspace/41.usbdev_enable/latest


Test location /workspace/coverage/default/41.usbdev_fifo_rst.2713066092
Short name T1215
Test name
Test status
Simulation time 178719360 ps
CPU time 1.6 seconds
Started Apr 21 04:04:07 PM PDT 24
Finished Apr 21 04:04:09 PM PDT 24
Peak memory 204156 kb
Host smart-21b372da-11e4-44d0-8428-e44d6938475b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27130
66092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.2713066092
Directory /workspace/41.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/41.usbdev_in_stall.4260423131
Short name T1243
Test name
Test status
Simulation time 8365056560 ps
CPU time 7.93 seconds
Started Apr 21 04:04:13 PM PDT 24
Finished Apr 21 04:04:21 PM PDT 24
Peak memory 204040 kb
Host smart-70523ddd-058e-4467-87da-ecaf2686f1eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42604
23131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.4260423131
Directory /workspace/41.usbdev_in_stall/latest


Test location /workspace/coverage/default/41.usbdev_in_trans.745667409
Short name T957
Test name
Test status
Simulation time 8456876508 ps
CPU time 7.53 seconds
Started Apr 21 04:04:03 PM PDT 24
Finished Apr 21 04:04:11 PM PDT 24
Peak memory 204056 kb
Host smart-70df7430-a33f-4d4e-baa6-36ded837bb74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74566
7409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.745667409
Directory /workspace/41.usbdev_in_trans/latest


Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.39686984
Short name T949
Test name
Test status
Simulation time 8435108907 ps
CPU time 7.45 seconds
Started Apr 21 04:04:04 PM PDT 24
Finished Apr 21 04:04:11 PM PDT 24
Peak memory 204044 kb
Host smart-636c6e51-cd41-49d9-b1b6-97d108fd5cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39686
984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.39686984
Directory /workspace/41.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.1847573413
Short name T870
Test name
Test status
Simulation time 8373473476 ps
CPU time 8.28 seconds
Started Apr 21 04:04:05 PM PDT 24
Finished Apr 21 04:04:14 PM PDT 24
Peak memory 204068 kb
Host smart-4f0f9f6d-d544-4c6b-94b4-ccbf504006c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18475
73413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.1847573413
Directory /workspace/41.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/41.usbdev_nak_trans.1424327884
Short name T706
Test name
Test status
Simulation time 8437624863 ps
CPU time 8.47 seconds
Started Apr 21 04:04:05 PM PDT 24
Finished Apr 21 04:04:13 PM PDT 24
Peak memory 204028 kb
Host smart-cf8d76a9-a06d-44ba-9a6e-5fbcf7c185b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14243
27884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.1424327884
Directory /workspace/41.usbdev_nak_trans/latest


Test location /workspace/coverage/default/41.usbdev_out_stall.2845807295
Short name T899
Test name
Test status
Simulation time 8448130758 ps
CPU time 9.75 seconds
Started Apr 21 04:04:05 PM PDT 24
Finished Apr 21 04:04:15 PM PDT 24
Peak memory 204068 kb
Host smart-2dc3a086-da51-4d67-9bff-9a7a56ee33e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28458
07295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.2845807295
Directory /workspace/41.usbdev_out_stall/latest


Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3899832099
Short name T651
Test name
Test status
Simulation time 8373808975 ps
CPU time 7.65 seconds
Started Apr 21 04:04:08 PM PDT 24
Finished Apr 21 04:04:16 PM PDT 24
Peak memory 204040 kb
Host smart-68a57b81-450c-4cdf-8d05-7cb769acbc33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38998
32099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3899832099
Directory /workspace/41.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/41.usbdev_pending_in_trans.2960948657
Short name T50
Test name
Test status
Simulation time 8390653476 ps
CPU time 7.84 seconds
Started Apr 21 04:04:08 PM PDT 24
Finished Apr 21 04:04:16 PM PDT 24
Peak memory 204072 kb
Host smart-a86d0d08-b48a-45c7-af9a-699175168c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29609
48657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.2960948657
Directory /workspace/41.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.3434321319
Short name T769
Test name
Test status
Simulation time 8386047145 ps
CPU time 7.64 seconds
Started Apr 21 04:04:08 PM PDT 24
Finished Apr 21 04:04:16 PM PDT 24
Peak memory 204060 kb
Host smart-54434b44-4e21-478d-9b73-f59018ed189d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34343
21319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.3434321319
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3711535851
Short name T41
Test name
Test status
Simulation time 39304085 ps
CPU time 0.67 seconds
Started Apr 21 04:04:12 PM PDT 24
Finished Apr 21 04:04:13 PM PDT 24
Peak memory 203936 kb
Host smart-ef11fc8a-0da0-4d4b-b77b-376d1bfffbb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37115
35851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3711535851
Directory /workspace/41.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/41.usbdev_pkt_buffer.2290089020
Short name T903
Test name
Test status
Simulation time 26443979639 ps
CPU time 51.89 seconds
Started Apr 21 04:04:04 PM PDT 24
Finished Apr 21 04:04:56 PM PDT 24
Peak memory 204336 kb
Host smart-ac47cef6-3a8a-4da0-b23f-8a8c83771868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22900
89020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.2290089020
Directory /workspace/41.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/41.usbdev_pkt_received.3971373172
Short name T793
Test name
Test status
Simulation time 8387819937 ps
CPU time 8.27 seconds
Started Apr 21 04:04:06 PM PDT 24
Finished Apr 21 04:04:14 PM PDT 24
Peak memory 204064 kb
Host smart-ebe00943-591d-42cf-a33c-212255c12245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39713
73172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.3971373172
Directory /workspace/41.usbdev_pkt_received/latest


Test location /workspace/coverage/default/41.usbdev_pkt_sent.4036283380
Short name T955
Test name
Test status
Simulation time 8524246861 ps
CPU time 7.86 seconds
Started Apr 21 04:04:07 PM PDT 24
Finished Apr 21 04:04:15 PM PDT 24
Peak memory 204040 kb
Host smart-02aeff4d-47b7-4f6e-9173-a7e07b001400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40362
83380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.4036283380
Directory /workspace/41.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.2047293711
Short name T1365
Test name
Test status
Simulation time 8367248105 ps
CPU time 7.98 seconds
Started Apr 21 04:04:08 PM PDT 24
Finished Apr 21 04:04:17 PM PDT 24
Peak memory 204064 kb
Host smart-b488d239-6908-4c27-be8a-8d14f194f824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20472
93711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.2047293711
Directory /workspace/41.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/41.usbdev_setup_stage.3194048640
Short name T1325
Test name
Test status
Simulation time 8378803583 ps
CPU time 8.55 seconds
Started Apr 21 04:04:07 PM PDT 24
Finished Apr 21 04:04:16 PM PDT 24
Peak memory 204044 kb
Host smart-d5eb5921-de08-4425-836a-e076ac42d849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31940
48640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.3194048640
Directory /workspace/41.usbdev_setup_stage/latest


Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.1511261310
Short name T314
Test name
Test status
Simulation time 8368652441 ps
CPU time 8.2 seconds
Started Apr 21 04:04:09 PM PDT 24
Finished Apr 21 04:04:17 PM PDT 24
Peak memory 204056 kb
Host smart-db6ecddc-70a8-49c8-b3f1-bcaa9d282e9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15112
61310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.1511261310
Directory /workspace/41.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/41.usbdev_smoke.3685182853
Short name T154
Test name
Test status
Simulation time 8441684036 ps
CPU time 8.15 seconds
Started Apr 21 04:04:01 PM PDT 24
Finished Apr 21 04:04:10 PM PDT 24
Peak memory 204076 kb
Host smart-032fdd37-f244-4b73-92c0-a27542b92363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36851
82853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3685182853
Directory /workspace/41.usbdev_smoke/latest


Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.2481695604
Short name T1279
Test name
Test status
Simulation time 8404562705 ps
CPU time 7.65 seconds
Started Apr 21 04:04:07 PM PDT 24
Finished Apr 21 04:04:15 PM PDT 24
Peak memory 204044 kb
Host smart-3475d740-c1c1-4476-9891-60a675f81121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24816
95604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.2481695604
Directory /workspace/41.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/41.usbdev_stall_trans.616003444
Short name T1209
Test name
Test status
Simulation time 8416751613 ps
CPU time 7.47 seconds
Started Apr 21 04:04:06 PM PDT 24
Finished Apr 21 04:04:13 PM PDT 24
Peak memory 204044 kb
Host smart-758fd615-325f-41b7-b2f0-278872b7c25a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61600
3444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.616003444
Directory /workspace/41.usbdev_stall_trans/latest


Test location /workspace/coverage/default/42.max_length_in_transaction.790575699
Short name T593
Test name
Test status
Simulation time 8459472771 ps
CPU time 7.74 seconds
Started Apr 21 04:04:18 PM PDT 24
Finished Apr 21 04:04:26 PM PDT 24
Peak memory 204048 kb
Host smart-f831389d-ee56-448d-92bc-e57579591105
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=790575699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.790575699
Directory /workspace/42.max_length_in_transaction/latest


Test location /workspace/coverage/default/42.min_length_in_transaction.1182388019
Short name T1233
Test name
Test status
Simulation time 8382209774 ps
CPU time 8.24 seconds
Started Apr 21 04:04:18 PM PDT 24
Finished Apr 21 04:04:26 PM PDT 24
Peak memory 204000 kb
Host smart-1b4c37d3-52e1-4754-b609-54bf77ddb965
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1182388019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.1182388019
Directory /workspace/42.min_length_in_transaction/latest


Test location /workspace/coverage/default/42.random_length_in_trans.3010595151
Short name T320
Test name
Test status
Simulation time 8452152734 ps
CPU time 9.2 seconds
Started Apr 21 04:04:23 PM PDT 24
Finished Apr 21 04:04:32 PM PDT 24
Peak memory 204024 kb
Host smart-dd2db623-b500-432b-b654-9971b8ae2eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30105
95151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.3010595151
Directory /workspace/42.random_length_in_trans/latest


Test location /workspace/coverage/default/42.usbdev_av_buffer.584502106
Short name T327
Test name
Test status
Simulation time 8386306691 ps
CPU time 8.88 seconds
Started Apr 21 04:04:12 PM PDT 24
Finished Apr 21 04:04:21 PM PDT 24
Peak memory 204048 kb
Host smart-97dea3d0-5bec-4969-b2c8-98f848b1ac98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58450
2106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.584502106
Directory /workspace/42.usbdev_av_buffer/latest


Test location /workspace/coverage/default/42.usbdev_enable.761230286
Short name T960
Test name
Test status
Simulation time 8371457065 ps
CPU time 7.5 seconds
Started Apr 21 04:04:12 PM PDT 24
Finished Apr 21 04:04:19 PM PDT 24
Peak memory 203964 kb
Host smart-bdba29ce-4171-4ea2-8ace-b1ad433fdf9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76123
0286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.761230286
Directory /workspace/42.usbdev_enable/latest


Test location /workspace/coverage/default/42.usbdev_fifo_rst.3100350684
Short name T1193
Test name
Test status
Simulation time 88613890 ps
CPU time 1.31 seconds
Started Apr 21 04:04:13 PM PDT 24
Finished Apr 21 04:04:14 PM PDT 24
Peak memory 204192 kb
Host smart-af2b3340-aff8-4e4b-9d21-e41681541280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31003
50684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3100350684
Directory /workspace/42.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/42.usbdev_in_iso.1911859145
Short name T1141
Test name
Test status
Simulation time 8478338794 ps
CPU time 9 seconds
Started Apr 21 04:04:17 PM PDT 24
Finished Apr 21 04:04:26 PM PDT 24
Peak memory 204040 kb
Host smart-4daa81b1-cd08-4be8-8bc7-c7221c195789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19118
59145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.1911859145
Directory /workspace/42.usbdev_in_iso/latest


Test location /workspace/coverage/default/42.usbdev_in_stall.3596575357
Short name T987
Test name
Test status
Simulation time 8377565811 ps
CPU time 7.85 seconds
Started Apr 21 04:04:22 PM PDT 24
Finished Apr 21 04:04:30 PM PDT 24
Peak memory 204020 kb
Host smart-f820a27b-cc51-427e-afb0-910b89d2760f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35965
75357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.3596575357
Directory /workspace/42.usbdev_in_stall/latest


Test location /workspace/coverage/default/42.usbdev_in_trans.738680808
Short name T1109
Test name
Test status
Simulation time 8423524868 ps
CPU time 8.25 seconds
Started Apr 21 04:04:16 PM PDT 24
Finished Apr 21 04:04:24 PM PDT 24
Peak memory 204036 kb
Host smart-12b358af-4a20-4da0-b2cf-c0875632ac41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73868
0808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.738680808
Directory /workspace/42.usbdev_in_trans/latest


Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.786300632
Short name T807
Test name
Test status
Simulation time 8426818896 ps
CPU time 7.79 seconds
Started Apr 21 04:04:12 PM PDT 24
Finished Apr 21 04:04:20 PM PDT 24
Peak memory 204060 kb
Host smart-63d54ca1-1160-492b-a587-849adb98e734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78630
0632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.786300632
Directory /workspace/42.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.3532781469
Short name T698
Test name
Test status
Simulation time 8372810200 ps
CPU time 7.77 seconds
Started Apr 21 04:04:16 PM PDT 24
Finished Apr 21 04:04:24 PM PDT 24
Peak memory 204072 kb
Host smart-7e7fcd56-a557-4e96-8645-8460ff003900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35327
81469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.3532781469
Directory /workspace/42.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/42.usbdev_nak_trans.1226882220
Short name T118
Test name
Test status
Simulation time 8466581783 ps
CPU time 9.38 seconds
Started Apr 21 04:04:15 PM PDT 24
Finished Apr 21 04:04:25 PM PDT 24
Peak memory 204068 kb
Host smart-cad69d34-f921-4dab-ba5c-5678773e88f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12268
82220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.1226882220
Directory /workspace/42.usbdev_nak_trans/latest


Test location /workspace/coverage/default/42.usbdev_out_stall.1267847156
Short name T865
Test name
Test status
Simulation time 8395860372 ps
CPU time 8.36 seconds
Started Apr 21 04:04:18 PM PDT 24
Finished Apr 21 04:04:27 PM PDT 24
Peak memory 204048 kb
Host smart-a5042cd3-ed3b-4eb3-8b40-5a0f343fc8a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12678
47156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.1267847156
Directory /workspace/42.usbdev_out_stall/latest


Test location /workspace/coverage/default/42.usbdev_out_trans_nak.103112351
Short name T927
Test name
Test status
Simulation time 8412281589 ps
CPU time 8.57 seconds
Started Apr 21 04:04:17 PM PDT 24
Finished Apr 21 04:04:26 PM PDT 24
Peak memory 204048 kb
Host smart-b68029e4-7da2-4018-a217-3a21e189bd76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10311
2351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.103112351
Directory /workspace/42.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/42.usbdev_pending_in_trans.727244660
Short name T1087
Test name
Test status
Simulation time 8413168997 ps
CPU time 10.48 seconds
Started Apr 21 04:04:16 PM PDT 24
Finished Apr 21 04:04:27 PM PDT 24
Peak memory 204044 kb
Host smart-949210c2-bcd6-46f5-84af-682b73bbb251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72724
4660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.727244660
Directory /workspace/42.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.3470569158
Short name T944
Test name
Test status
Simulation time 8370996825 ps
CPU time 8.27 seconds
Started Apr 21 04:04:16 PM PDT 24
Finished Apr 21 04:04:25 PM PDT 24
Peak memory 204060 kb
Host smart-8b9ef24d-0eba-420c-94d6-df540b0ff80b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34705
69158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.3470569158
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.156338887
Short name T735
Test name
Test status
Simulation time 164975820 ps
CPU time 0.77 seconds
Started Apr 21 04:04:18 PM PDT 24
Finished Apr 21 04:04:19 PM PDT 24
Peak memory 203888 kb
Host smart-ae6b03a8-a297-4c53-ab42-c2cf11f5d905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15633
8887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.156338887
Directory /workspace/42.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/42.usbdev_pkt_buffer.1856136221
Short name T1091
Test name
Test status
Simulation time 18456169639 ps
CPU time 32.96 seconds
Started Apr 21 04:04:16 PM PDT 24
Finished Apr 21 04:04:50 PM PDT 24
Peak memory 204324 kb
Host smart-3db37dea-ecaf-4402-95a3-fe0557b247e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18561
36221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.1856136221
Directory /workspace/42.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/42.usbdev_pkt_received.3267216846
Short name T363
Test name
Test status
Simulation time 8390492901 ps
CPU time 7.66 seconds
Started Apr 21 04:04:22 PM PDT 24
Finished Apr 21 04:04:30 PM PDT 24
Peak memory 204028 kb
Host smart-92a30122-7de6-4113-8583-47bb21eb1156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32672
16846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.3267216846
Directory /workspace/42.usbdev_pkt_received/latest


Test location /workspace/coverage/default/42.usbdev_pkt_sent.2302729883
Short name T491
Test name
Test status
Simulation time 8394423859 ps
CPU time 7.78 seconds
Started Apr 21 04:04:15 PM PDT 24
Finished Apr 21 04:04:24 PM PDT 24
Peak memory 204056 kb
Host smart-27b560b0-d5ed-491a-a70c-4729e30b4839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23027
29883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2302729883
Directory /workspace/42.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.3717044732
Short name T408
Test name
Test status
Simulation time 8386774808 ps
CPU time 7.87 seconds
Started Apr 21 04:04:16 PM PDT 24
Finished Apr 21 04:04:24 PM PDT 24
Peak memory 204052 kb
Host smart-d6a1cb8f-991c-4d7a-afab-8363df749b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37170
44732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.3717044732
Directory /workspace/42.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/42.usbdev_setup_stage.1305379711
Short name T1232
Test name
Test status
Simulation time 8371509215 ps
CPU time 8.64 seconds
Started Apr 21 04:04:19 PM PDT 24
Finished Apr 21 04:04:28 PM PDT 24
Peak memory 204044 kb
Host smart-6f059582-72ea-4a58-b7cb-016882787652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13053
79711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.1305379711
Directory /workspace/42.usbdev_setup_stage/latest


Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.4138392842
Short name T535
Test name
Test status
Simulation time 8379452835 ps
CPU time 9.49 seconds
Started Apr 21 04:04:23 PM PDT 24
Finished Apr 21 04:04:33 PM PDT 24
Peak memory 204020 kb
Host smart-34a4fe2b-d584-471f-8055-ecb374d0a179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41383
92842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.4138392842
Directory /workspace/42.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.3014473077
Short name T700
Test name
Test status
Simulation time 8374403577 ps
CPU time 8.3 seconds
Started Apr 21 04:04:22 PM PDT 24
Finished Apr 21 04:04:31 PM PDT 24
Peak memory 204024 kb
Host smart-2a3ed4e7-cea0-48c1-a965-43802ce7a00d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30144
73077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.3014473077
Directory /workspace/42.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/42.usbdev_stall_trans.2009999658
Short name T1120
Test name
Test status
Simulation time 8389613121 ps
CPU time 8.26 seconds
Started Apr 21 04:04:16 PM PDT 24
Finished Apr 21 04:04:25 PM PDT 24
Peak memory 204028 kb
Host smart-aea8803a-9ebb-4bfc-9d5e-9172a58ad9c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20099
99658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.2009999658
Directory /workspace/42.usbdev_stall_trans/latest


Test location /workspace/coverage/default/43.max_length_in_transaction.3004940169
Short name T765
Test name
Test status
Simulation time 8468018673 ps
CPU time 8.48 seconds
Started Apr 21 04:04:30 PM PDT 24
Finished Apr 21 04:04:39 PM PDT 24
Peak memory 204060 kb
Host smart-83b0f6a8-568a-4cb7-9c86-e1f7130df5c3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3004940169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.3004940169
Directory /workspace/43.max_length_in_transaction/latest


Test location /workspace/coverage/default/43.min_length_in_transaction.928710287
Short name T343
Test name
Test status
Simulation time 8399519115 ps
CPU time 10.04 seconds
Started Apr 21 04:04:30 PM PDT 24
Finished Apr 21 04:04:41 PM PDT 24
Peak memory 204048 kb
Host smart-ec9d3ae0-f556-4832-8591-9d702dc803c1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=928710287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.928710287
Directory /workspace/43.min_length_in_transaction/latest


Test location /workspace/coverage/default/43.random_length_in_trans.986363780
Short name T967
Test name
Test status
Simulation time 8417557907 ps
CPU time 8.25 seconds
Started Apr 21 04:04:30 PM PDT 24
Finished Apr 21 04:04:38 PM PDT 24
Peak memory 204044 kb
Host smart-b67beb5b-9d2f-4cf6-8f82-de4b050ca660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98636
3780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.986363780
Directory /workspace/43.random_length_in_trans/latest


Test location /workspace/coverage/default/43.usbdev_av_buffer.287344897
Short name T485
Test name
Test status
Simulation time 8392966515 ps
CPU time 7.82 seconds
Started Apr 21 04:04:22 PM PDT 24
Finished Apr 21 04:04:30 PM PDT 24
Peak memory 204088 kb
Host smart-db34302b-9aa5-42af-8f95-31abe1f67b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28734
4897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.287344897
Directory /workspace/43.usbdev_av_buffer/latest


Test location /workspace/coverage/default/43.usbdev_enable.3366046608
Short name T691
Test name
Test status
Simulation time 8370070844 ps
CPU time 8.05 seconds
Started Apr 21 04:04:20 PM PDT 24
Finished Apr 21 04:04:28 PM PDT 24
Peak memory 204240 kb
Host smart-a0527960-8e53-4901-a23b-d6b60af9d4cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33660
46608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.3366046608
Directory /workspace/43.usbdev_enable/latest


Test location /workspace/coverage/default/43.usbdev_fifo_rst.716288810
Short name T57
Test name
Test status
Simulation time 135845567 ps
CPU time 1.36 seconds
Started Apr 21 04:04:20 PM PDT 24
Finished Apr 21 04:04:21 PM PDT 24
Peak memory 204112 kb
Host smart-68abba4c-e3f1-430e-9e01-ab68e4cb78a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71628
8810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.716288810
Directory /workspace/43.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/43.usbdev_in_iso.3946105350
Short name T992
Test name
Test status
Simulation time 8479556024 ps
CPU time 8.51 seconds
Started Apr 21 04:04:29 PM PDT 24
Finished Apr 21 04:04:38 PM PDT 24
Peak memory 204084 kb
Host smart-275ba689-9800-474f-832c-9dcc6ad8e352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39461
05350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.3946105350
Directory /workspace/43.usbdev_in_iso/latest


Test location /workspace/coverage/default/43.usbdev_in_stall.1496904568
Short name T1259
Test name
Test status
Simulation time 8368016462 ps
CPU time 7.48 seconds
Started Apr 21 04:04:28 PM PDT 24
Finished Apr 21 04:04:36 PM PDT 24
Peak memory 204036 kb
Host smart-32d87e79-6b6a-43cb-9c93-e8133bf9faa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14969
04568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.1496904568
Directory /workspace/43.usbdev_in_stall/latest


Test location /workspace/coverage/default/43.usbdev_in_trans.2730233649
Short name T750
Test name
Test status
Simulation time 8454372248 ps
CPU time 8.49 seconds
Started Apr 21 04:04:20 PM PDT 24
Finished Apr 21 04:04:29 PM PDT 24
Peak memory 204048 kb
Host smart-88e40354-3a20-47be-a941-29d777e61f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27302
33649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.2730233649
Directory /workspace/43.usbdev_in_trans/latest


Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.609825889
Short name T339
Test name
Test status
Simulation time 8419598832 ps
CPU time 9.02 seconds
Started Apr 21 04:04:21 PM PDT 24
Finished Apr 21 04:04:30 PM PDT 24
Peak memory 204064 kb
Host smart-3c36c02d-94fd-4776-a713-39753ff940de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60982
5889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.609825889
Directory /workspace/43.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.1724491337
Short name T963
Test name
Test status
Simulation time 8371757298 ps
CPU time 8.4 seconds
Started Apr 21 04:04:25 PM PDT 24
Finished Apr 21 04:04:34 PM PDT 24
Peak memory 204036 kb
Host smart-d811e052-c6d3-4d1f-97a4-37d0b45aa991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17244
91337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1724491337
Directory /workspace/43.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/43.usbdev_nak_trans.2343264564
Short name T128
Test name
Test status
Simulation time 8387783518 ps
CPU time 8.41 seconds
Started Apr 21 04:04:22 PM PDT 24
Finished Apr 21 04:04:31 PM PDT 24
Peak memory 204068 kb
Host smart-06ab44c0-a556-4719-8b15-cfa05517ff45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23432
64564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2343264564
Directory /workspace/43.usbdev_nak_trans/latest


Test location /workspace/coverage/default/43.usbdev_out_stall.2940295423
Short name T880
Test name
Test status
Simulation time 8385657555 ps
CPU time 8.75 seconds
Started Apr 21 04:04:25 PM PDT 24
Finished Apr 21 04:04:34 PM PDT 24
Peak memory 204040 kb
Host smart-818ab125-c218-425e-8f1a-1b4d05a61c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29402
95423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.2940295423
Directory /workspace/43.usbdev_out_stall/latest


Test location /workspace/coverage/default/43.usbdev_out_trans_nak.4053483610
Short name T656
Test name
Test status
Simulation time 8399063162 ps
CPU time 8.01 seconds
Started Apr 21 04:04:21 PM PDT 24
Finished Apr 21 04:04:29 PM PDT 24
Peak memory 204024 kb
Host smart-6220c4b6-5bd0-4537-ba66-7ef3f37856d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40534
83610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.4053483610
Directory /workspace/43.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/43.usbdev_pending_in_trans.216061494
Short name T599
Test name
Test status
Simulation time 8388500766 ps
CPU time 10.37 seconds
Started Apr 21 04:04:23 PM PDT 24
Finished Apr 21 04:04:33 PM PDT 24
Peak memory 204060 kb
Host smart-82e71d98-2b05-428f-b427-9e999cb97217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21606
1494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.216061494
Directory /workspace/43.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.3131517466
Short name T494
Test name
Test status
Simulation time 8366029009 ps
CPU time 9.52 seconds
Started Apr 21 04:04:24 PM PDT 24
Finished Apr 21 04:04:33 PM PDT 24
Peak memory 204044 kb
Host smart-f89045f4-d70b-45d4-8633-d446070af756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31315
17466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.3131517466
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.1744641197
Short name T33
Test name
Test status
Simulation time 96401861 ps
CPU time 0.69 seconds
Started Apr 21 04:04:31 PM PDT 24
Finished Apr 21 04:04:32 PM PDT 24
Peak memory 203916 kb
Host smart-85f18d30-7516-45ee-b456-281364e8bb35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17446
41197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.1744641197
Directory /workspace/43.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/43.usbdev_pkt_buffer.1557299277
Short name T95
Test name
Test status
Simulation time 30773663152 ps
CPU time 70.34 seconds
Started Apr 21 04:04:20 PM PDT 24
Finished Apr 21 04:05:31 PM PDT 24
Peak memory 204328 kb
Host smart-6490ac7b-1112-4761-bd9c-650c8dd8665e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15572
99277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.1557299277
Directory /workspace/43.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/43.usbdev_pkt_received.3883120581
Short name T695
Test name
Test status
Simulation time 8390023603 ps
CPU time 8.44 seconds
Started Apr 21 04:04:22 PM PDT 24
Finished Apr 21 04:04:31 PM PDT 24
Peak memory 204084 kb
Host smart-a06b0eed-9860-49a2-89a8-3871da1f0928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38831
20581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.3883120581
Directory /workspace/43.usbdev_pkt_received/latest


Test location /workspace/coverage/default/43.usbdev_pkt_sent.3900893441
Short name T587
Test name
Test status
Simulation time 8447097879 ps
CPU time 7.94 seconds
Started Apr 21 04:04:22 PM PDT 24
Finished Apr 21 04:04:30 PM PDT 24
Peak memory 204068 kb
Host smart-18d6969b-58ec-416b-b142-41a1dd1a94fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39008
93441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3900893441
Directory /workspace/43.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.1311655974
Short name T526
Test name
Test status
Simulation time 8406735991 ps
CPU time 7.93 seconds
Started Apr 21 04:04:29 PM PDT 24
Finished Apr 21 04:04:37 PM PDT 24
Peak memory 204024 kb
Host smart-1233d4ed-fa6e-4673-89ca-9e108f5c893f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13116
55974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.1311655974
Directory /workspace/43.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/43.usbdev_setup_stage.3306860448
Short name T1179
Test name
Test status
Simulation time 8371430871 ps
CPU time 7.78 seconds
Started Apr 21 04:04:22 PM PDT 24
Finished Apr 21 04:04:30 PM PDT 24
Peak memory 204004 kb
Host smart-35ef4dde-255f-47f5-ab58-b6bb4183b843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33068
60448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.3306860448
Directory /workspace/43.usbdev_setup_stage/latest


Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3273787110
Short name T25
Test name
Test status
Simulation time 8372805714 ps
CPU time 8.01 seconds
Started Apr 21 04:04:22 PM PDT 24
Finished Apr 21 04:04:30 PM PDT 24
Peak memory 204060 kb
Host smart-6904f155-766d-413a-8234-b014a10b39e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32737
87110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3273787110
Directory /workspace/43.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/43.usbdev_smoke.3280161722
Short name T758
Test name
Test status
Simulation time 8465578359 ps
CPU time 8.07 seconds
Started Apr 21 04:04:22 PM PDT 24
Finished Apr 21 04:04:30 PM PDT 24
Peak memory 204072 kb
Host smart-c2e531ed-9040-4fcb-b502-6146b6bb0d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32801
61722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.3280161722
Directory /workspace/43.usbdev_smoke/latest


Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.2745657271
Short name T344
Test name
Test status
Simulation time 8367319215 ps
CPU time 8.65 seconds
Started Apr 21 04:04:22 PM PDT 24
Finished Apr 21 04:04:31 PM PDT 24
Peak memory 204044 kb
Host smart-d2a04fcc-77cd-4e82-b879-f92ffd6601e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27456
57271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.2745657271
Directory /workspace/43.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/43.usbdev_stall_trans.2020232109
Short name T382
Test name
Test status
Simulation time 8393314507 ps
CPU time 9.93 seconds
Started Apr 21 04:04:29 PM PDT 24
Finished Apr 21 04:04:40 PM PDT 24
Peak memory 204024 kb
Host smart-f8ce6709-a915-4cc8-a839-b6d3cc3991d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20202
32109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.2020232109
Directory /workspace/43.usbdev_stall_trans/latest


Test location /workspace/coverage/default/44.max_length_in_transaction.872145336
Short name T1035
Test name
Test status
Simulation time 8467237278 ps
CPU time 7.89 seconds
Started Apr 21 04:04:36 PM PDT 24
Finished Apr 21 04:04:45 PM PDT 24
Peak memory 204040 kb
Host smart-baa6a386-5ecd-46fe-9911-5f84bfca27f8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=872145336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.872145336
Directory /workspace/44.max_length_in_transaction/latest


Test location /workspace/coverage/default/44.min_length_in_transaction.639759125
Short name T1265
Test name
Test status
Simulation time 8387304647 ps
CPU time 7.77 seconds
Started Apr 21 04:04:36 PM PDT 24
Finished Apr 21 04:04:44 PM PDT 24
Peak memory 204024 kb
Host smart-35cf19b2-e66c-4016-bba4-e034b05e0b19
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=639759125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.639759125
Directory /workspace/44.min_length_in_transaction/latest


Test location /workspace/coverage/default/44.random_length_in_trans.2598868947
Short name T1054
Test name
Test status
Simulation time 8410688214 ps
CPU time 8.25 seconds
Started Apr 21 04:04:38 PM PDT 24
Finished Apr 21 04:04:46 PM PDT 24
Peak memory 203936 kb
Host smart-98f91b9e-9705-4b30-b51d-8cbd576bb253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25988
68947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.2598868947
Directory /workspace/44.random_length_in_trans/latest


Test location /workspace/coverage/default/44.usbdev_av_buffer.1448821898
Short name T1103
Test name
Test status
Simulation time 8387889239 ps
CPU time 8.15 seconds
Started Apr 21 04:04:29 PM PDT 24
Finished Apr 21 04:04:37 PM PDT 24
Peak memory 204068 kb
Host smart-e87a37f0-3ef4-4674-945f-ab9586e06dbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14488
21898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.1448821898
Directory /workspace/44.usbdev_av_buffer/latest


Test location /workspace/coverage/default/44.usbdev_enable.345977272
Short name T1227
Test name
Test status
Simulation time 8397096101 ps
CPU time 7.71 seconds
Started Apr 21 04:04:29 PM PDT 24
Finished Apr 21 04:04:37 PM PDT 24
Peak memory 204048 kb
Host smart-8c688bbc-a8a8-41d7-9820-855d4597bbd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34597
7272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.345977272
Directory /workspace/44.usbdev_enable/latest


Test location /workspace/coverage/default/44.usbdev_fifo_rst.2330356467
Short name T82
Test name
Test status
Simulation time 47394043 ps
CPU time 1.32 seconds
Started Apr 21 04:04:28 PM PDT 24
Finished Apr 21 04:04:30 PM PDT 24
Peak memory 204136 kb
Host smart-60188ad8-2ec9-417d-9379-1aa4df0437c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23303
56467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.2330356467
Directory /workspace/44.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/44.usbdev_in_iso.226360787
Short name T560
Test name
Test status
Simulation time 8376864814 ps
CPU time 8.01 seconds
Started Apr 21 04:04:39 PM PDT 24
Finished Apr 21 04:04:47 PM PDT 24
Peak memory 204088 kb
Host smart-016a1516-f8b4-4f69-9bb4-2996f5c01811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22636
0787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.226360787
Directory /workspace/44.usbdev_in_iso/latest


Test location /workspace/coverage/default/44.usbdev_in_stall.1541522225
Short name T530
Test name
Test status
Simulation time 8385121277 ps
CPU time 7.35 seconds
Started Apr 21 04:04:34 PM PDT 24
Finished Apr 21 04:04:42 PM PDT 24
Peak memory 204080 kb
Host smart-8a210e22-8d8b-4777-a845-9cda3e136937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15415
22225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.1541522225
Directory /workspace/44.usbdev_in_stall/latest


Test location /workspace/coverage/default/44.usbdev_in_trans.2094826145
Short name T1009
Test name
Test status
Simulation time 8389305599 ps
CPU time 8.51 seconds
Started Apr 21 04:04:29 PM PDT 24
Finished Apr 21 04:04:38 PM PDT 24
Peak memory 204084 kb
Host smart-ce2f5e4f-a294-41a4-ab3c-c51329284ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20948
26145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.2094826145
Directory /workspace/44.usbdev_in_trans/latest


Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.2655761507
Short name T1110
Test name
Test status
Simulation time 8414883897 ps
CPU time 7.86 seconds
Started Apr 21 04:04:30 PM PDT 24
Finished Apr 21 04:04:38 PM PDT 24
Peak memory 204064 kb
Host smart-e7e48cf9-76a4-4f9c-ad5f-57929bc218fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26557
61507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.2655761507
Directory /workspace/44.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.1200802522
Short name T34
Test name
Test status
Simulation time 8380510407 ps
CPU time 8.01 seconds
Started Apr 21 04:04:29 PM PDT 24
Finished Apr 21 04:04:37 PM PDT 24
Peak memory 204028 kb
Host smart-ad86fede-4fae-4141-9389-d51b717c73ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12008
02522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.1200802522
Directory /workspace/44.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/44.usbdev_nak_trans.2587315762
Short name T122
Test name
Test status
Simulation time 8421463460 ps
CPU time 8.15 seconds
Started Apr 21 04:04:29 PM PDT 24
Finished Apr 21 04:04:38 PM PDT 24
Peak memory 204040 kb
Host smart-9400c0de-0350-4814-8c53-597d3df1d1bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25873
15762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.2587315762
Directory /workspace/44.usbdev_nak_trans/latest


Test location /workspace/coverage/default/44.usbdev_out_stall.1221083991
Short name T407
Test name
Test status
Simulation time 8393983739 ps
CPU time 8.62 seconds
Started Apr 21 04:04:27 PM PDT 24
Finished Apr 21 04:04:35 PM PDT 24
Peak memory 204064 kb
Host smart-df42684f-6868-48ae-9c08-8f806c8445dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12210
83991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.1221083991
Directory /workspace/44.usbdev_out_stall/latest


Test location /workspace/coverage/default/44.usbdev_out_trans_nak.2284631577
Short name T1163
Test name
Test status
Simulation time 8377286683 ps
CPU time 7.65 seconds
Started Apr 21 04:04:29 PM PDT 24
Finished Apr 21 04:04:37 PM PDT 24
Peak memory 204064 kb
Host smart-babe48de-c9e0-4b30-ba99-78baa5d607d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22846
31577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.2284631577
Directory /workspace/44.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/44.usbdev_pending_in_trans.1135168381
Short name T828
Test name
Test status
Simulation time 8465983145 ps
CPU time 8.22 seconds
Started Apr 21 04:04:32 PM PDT 24
Finished Apr 21 04:04:40 PM PDT 24
Peak memory 204020 kb
Host smart-18d188e9-cc51-4d55-9001-b44bf1c3dc78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11351
68381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.1135168381
Directory /workspace/44.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.3736144431
Short name T579
Test name
Test status
Simulation time 8372905074 ps
CPU time 9.96 seconds
Started Apr 21 04:04:34 PM PDT 24
Finished Apr 21 04:04:44 PM PDT 24
Peak memory 204044 kb
Host smart-de1d2477-5f48-4b2e-8b60-559d07bee17a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37361
44431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.3736144431
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.493465762
Short name T1250
Test name
Test status
Simulation time 38395732 ps
CPU time 0.68 seconds
Started Apr 21 04:04:33 PM PDT 24
Finished Apr 21 04:04:34 PM PDT 24
Peak memory 203912 kb
Host smart-edb5b59d-ec08-45df-9e97-c95f83e1dfda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49346
5762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.493465762
Directory /workspace/44.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/44.usbdev_pkt_buffer.3475462534
Short name T227
Test name
Test status
Simulation time 27531582831 ps
CPU time 67.08 seconds
Started Apr 21 04:04:29 PM PDT 24
Finished Apr 21 04:05:36 PM PDT 24
Peak memory 204368 kb
Host smart-75e129c0-750e-4274-b89d-9d4d5fc937b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34754
62534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.3475462534
Directory /workspace/44.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/44.usbdev_pkt_received.3432867276
Short name T1006
Test name
Test status
Simulation time 8378946038 ps
CPU time 9.11 seconds
Started Apr 21 04:04:29 PM PDT 24
Finished Apr 21 04:04:38 PM PDT 24
Peak memory 203940 kb
Host smart-3bddeb98-36e5-4763-b929-c93d42b1fa8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34328
67276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.3432867276
Directory /workspace/44.usbdev_pkt_received/latest


Test location /workspace/coverage/default/44.usbdev_pkt_sent.2758305556
Short name T640
Test name
Test status
Simulation time 8386311841 ps
CPU time 8.23 seconds
Started Apr 21 04:04:30 PM PDT 24
Finished Apr 21 04:04:38 PM PDT 24
Peak memory 204084 kb
Host smart-ff8634c3-5450-468e-8b06-df3916a98602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27583
05556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2758305556
Directory /workspace/44.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.53255451
Short name T968
Test name
Test status
Simulation time 8411340429 ps
CPU time 9.25 seconds
Started Apr 21 04:04:32 PM PDT 24
Finished Apr 21 04:04:41 PM PDT 24
Peak memory 204224 kb
Host smart-342e826c-2bc4-4220-9800-0b76d4fe70db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53255
451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.53255451
Directory /workspace/44.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/44.usbdev_setup_stage.2976516565
Short name T1334
Test name
Test status
Simulation time 8374215906 ps
CPU time 9.37 seconds
Started Apr 21 04:04:32 PM PDT 24
Finished Apr 21 04:04:42 PM PDT 24
Peak memory 204056 kb
Host smart-8a603c69-8489-432a-a40b-b4f479605d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29765
16565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.2976516565
Directory /workspace/44.usbdev_setup_stage/latest


Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3249309979
Short name T489
Test name
Test status
Simulation time 8372987166 ps
CPU time 7.81 seconds
Started Apr 21 04:04:32 PM PDT 24
Finished Apr 21 04:04:41 PM PDT 24
Peak memory 204012 kb
Host smart-b6e3741c-778b-4b61-bc8d-a81765ab43c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32493
09979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3249309979
Directory /workspace/44.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/44.usbdev_smoke.4036602636
Short name T866
Test name
Test status
Simulation time 8426324281 ps
CPU time 9.6 seconds
Started Apr 21 04:04:31 PM PDT 24
Finished Apr 21 04:04:40 PM PDT 24
Peak memory 204028 kb
Host smart-8b49ad0b-b78f-464a-93d9-0ce8d2eecc30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40366
02636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.4036602636
Directory /workspace/44.usbdev_smoke/latest


Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.3836814880
Short name T1092
Test name
Test status
Simulation time 8466854159 ps
CPU time 7.53 seconds
Started Apr 21 04:04:33 PM PDT 24
Finished Apr 21 04:04:41 PM PDT 24
Peak memory 204076 kb
Host smart-7adba490-be3d-464b-9476-20d84bb549e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38368
14880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.3836814880
Directory /workspace/44.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/44.usbdev_stall_trans.2008805582
Short name T642
Test name
Test status
Simulation time 8405341823 ps
CPU time 8.68 seconds
Started Apr 21 04:04:33 PM PDT 24
Finished Apr 21 04:04:42 PM PDT 24
Peak memory 204052 kb
Host smart-610fdf0c-ce0b-4216-a3b0-29fd6cfca4ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20088
05582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.2008805582
Directory /workspace/44.usbdev_stall_trans/latest


Test location /workspace/coverage/default/45.max_length_in_transaction.2034364746
Short name T503
Test name
Test status
Simulation time 8467073185 ps
CPU time 9.21 seconds
Started Apr 21 04:04:42 PM PDT 24
Finished Apr 21 04:04:51 PM PDT 24
Peak memory 204028 kb
Host smart-8380cccd-654e-4b75-a1bd-594376fec085
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2034364746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.2034364746
Directory /workspace/45.max_length_in_transaction/latest


Test location /workspace/coverage/default/45.min_length_in_transaction.3704444788
Short name T1171
Test name
Test status
Simulation time 8382861765 ps
CPU time 8.42 seconds
Started Apr 21 04:04:51 PM PDT 24
Finished Apr 21 04:05:00 PM PDT 24
Peak memory 204036 kb
Host smart-8943486f-e4a1-40db-b900-cfac9edac4e5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3704444788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.3704444788
Directory /workspace/45.min_length_in_transaction/latest


Test location /workspace/coverage/default/45.random_length_in_trans.3738018991
Short name T614
Test name
Test status
Simulation time 8408833090 ps
CPU time 9.98 seconds
Started Apr 21 04:04:40 PM PDT 24
Finished Apr 21 04:04:51 PM PDT 24
Peak memory 204080 kb
Host smart-9f297a66-7225-4e85-aa2f-af727d66519a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37380
18991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.3738018991
Directory /workspace/45.random_length_in_trans/latest


Test location /workspace/coverage/default/45.usbdev_av_buffer.561597300
Short name T580
Test name
Test status
Simulation time 8397663163 ps
CPU time 8.72 seconds
Started Apr 21 04:04:36 PM PDT 24
Finished Apr 21 04:04:45 PM PDT 24
Peak memory 204036 kb
Host smart-970a7dae-db71-43c4-8ffe-a38332bc12b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56159
7300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.561597300
Directory /workspace/45.usbdev_av_buffer/latest


Test location /workspace/coverage/default/45.usbdev_enable.1264967734
Short name T649
Test name
Test status
Simulation time 8376908900 ps
CPU time 8.02 seconds
Started Apr 21 04:04:38 PM PDT 24
Finished Apr 21 04:04:46 PM PDT 24
Peak memory 204028 kb
Host smart-adee4e0f-fa8a-4c81-a78d-83f6e0675a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12649
67734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.1264967734
Directory /workspace/45.usbdev_enable/latest


Test location /workspace/coverage/default/45.usbdev_fifo_rst.664800707
Short name T730
Test name
Test status
Simulation time 82593674 ps
CPU time 1.15 seconds
Started Apr 21 04:04:37 PM PDT 24
Finished Apr 21 04:04:38 PM PDT 24
Peak memory 204124 kb
Host smart-6996d77c-352a-48fb-af55-d255ad329970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66480
0707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.664800707
Directory /workspace/45.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/45.usbdev_in_iso.4202813925
Short name T1010
Test name
Test status
Simulation time 8489902585 ps
CPU time 8.53 seconds
Started Apr 21 04:04:44 PM PDT 24
Finished Apr 21 04:04:52 PM PDT 24
Peak memory 204040 kb
Host smart-ff33c975-af08-4973-bcb4-52c895daa7d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42028
13925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.4202813925
Directory /workspace/45.usbdev_in_iso/latest


Test location /workspace/coverage/default/45.usbdev_in_stall.2312118028
Short name T547
Test name
Test status
Simulation time 8365781277 ps
CPU time 8.55 seconds
Started Apr 21 04:04:40 PM PDT 24
Finished Apr 21 04:04:49 PM PDT 24
Peak memory 204040 kb
Host smart-b560b3dc-5b23-4e87-a9be-0791810fd5e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23121
18028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.2312118028
Directory /workspace/45.usbdev_in_stall/latest


Test location /workspace/coverage/default/45.usbdev_in_trans.3321361803
Short name T1375
Test name
Test status
Simulation time 8463519182 ps
CPU time 8.73 seconds
Started Apr 21 04:04:36 PM PDT 24
Finished Apr 21 04:04:46 PM PDT 24
Peak memory 203960 kb
Host smart-3692ccfc-b756-4fa4-bfba-8519c39efa0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33213
61803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3321361803
Directory /workspace/45.usbdev_in_trans/latest


Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.2994978556
Short name T895
Test name
Test status
Simulation time 8432341204 ps
CPU time 10.2 seconds
Started Apr 21 04:04:36 PM PDT 24
Finished Apr 21 04:04:47 PM PDT 24
Peak memory 204048 kb
Host smart-dedfe3e4-caaf-4ca2-8a4f-71d97758fa9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29949
78556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.2994978556
Directory /workspace/45.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.3715081455
Short name T888
Test name
Test status
Simulation time 8372721983 ps
CPU time 8.38 seconds
Started Apr 21 04:04:36 PM PDT 24
Finished Apr 21 04:04:45 PM PDT 24
Peak memory 204052 kb
Host smart-fdc3ff19-86c4-430f-9712-90fe1300b2f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37150
81455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.3715081455
Directory /workspace/45.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/45.usbdev_nak_trans.776787055
Short name T105
Test name
Test status
Simulation time 8427214613 ps
CPU time 8.86 seconds
Started Apr 21 04:04:37 PM PDT 24
Finished Apr 21 04:04:46 PM PDT 24
Peak memory 204068 kb
Host smart-85228156-3997-4322-a922-adb8c243ade6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77678
7055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.776787055
Directory /workspace/45.usbdev_nak_trans/latest


Test location /workspace/coverage/default/45.usbdev_out_stall.1604556288
Short name T867
Test name
Test status
Simulation time 8390850572 ps
CPU time 7.66 seconds
Started Apr 21 04:04:40 PM PDT 24
Finished Apr 21 04:04:48 PM PDT 24
Peak memory 204052 kb
Host smart-11f48a35-eb2f-407f-b76b-3de4e452d3f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16045
56288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.1604556288
Directory /workspace/45.usbdev_out_stall/latest


Test location /workspace/coverage/default/45.usbdev_out_trans_nak.1981559028
Short name T1189
Test name
Test status
Simulation time 8428469949 ps
CPU time 7.76 seconds
Started Apr 21 04:04:40 PM PDT 24
Finished Apr 21 04:04:48 PM PDT 24
Peak memory 204024 kb
Host smart-b22e7c2c-5f1a-44a5-9f84-5777d3504c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19815
59028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.1981559028
Directory /workspace/45.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/45.usbdev_pending_in_trans.484588997
Short name T744
Test name
Test status
Simulation time 8378636259 ps
CPU time 7.8 seconds
Started Apr 21 04:04:41 PM PDT 24
Finished Apr 21 04:04:49 PM PDT 24
Peak memory 204064 kb
Host smart-5ad8c708-ca63-49cd-ba6d-30e228c72910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48458
8997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.484588997
Directory /workspace/45.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.1245352837
Short name T421
Test name
Test status
Simulation time 8371618206 ps
CPU time 9.92 seconds
Started Apr 21 04:04:39 PM PDT 24
Finished Apr 21 04:04:49 PM PDT 24
Peak memory 204028 kb
Host smart-8300292b-341d-48ae-b86c-87daf949ec49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12453
52837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.1245352837
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.235876430
Short name T1357
Test name
Test status
Simulation time 127862024 ps
CPU time 0.78 seconds
Started Apr 21 04:04:40 PM PDT 24
Finished Apr 21 04:04:41 PM PDT 24
Peak memory 203936 kb
Host smart-e4e47886-9204-4e31-a373-16ae2553f0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23587
6430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.235876430
Directory /workspace/45.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/45.usbdev_pkt_buffer.3554194001
Short name T689
Test name
Test status
Simulation time 16888452529 ps
CPU time 33.54 seconds
Started Apr 21 04:04:39 PM PDT 24
Finished Apr 21 04:05:13 PM PDT 24
Peak memory 204312 kb
Host smart-b0671427-048c-44d1-bff8-ed4e1a7edc3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35541
94001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.3554194001
Directory /workspace/45.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/45.usbdev_pkt_received.4051068754
Short name T613
Test name
Test status
Simulation time 8378419458 ps
CPU time 7.77 seconds
Started Apr 21 04:04:41 PM PDT 24
Finished Apr 21 04:04:49 PM PDT 24
Peak memory 204064 kb
Host smart-42fdd53a-d362-4362-b6ca-e5d2eb397235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40510
68754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.4051068754
Directory /workspace/45.usbdev_pkt_received/latest


Test location /workspace/coverage/default/45.usbdev_pkt_sent.1820361165
Short name T1277
Test name
Test status
Simulation time 8413533205 ps
CPU time 8.5 seconds
Started Apr 21 04:04:40 PM PDT 24
Finished Apr 21 04:04:49 PM PDT 24
Peak memory 204060 kb
Host smart-57fc4f13-797c-4f6f-b446-21d0ce42fc43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18203
61165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.1820361165
Directory /workspace/45.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.571738049
Short name T1147
Test name
Test status
Simulation time 8373252609 ps
CPU time 8.02 seconds
Started Apr 21 04:04:42 PM PDT 24
Finished Apr 21 04:04:51 PM PDT 24
Peak memory 204064 kb
Host smart-62e2a6c4-6a51-43cf-bcf0-6367d2e69e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57173
8049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.571738049
Directory /workspace/45.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/45.usbdev_setup_stage.4270721425
Short name T89
Test name
Test status
Simulation time 8373192052 ps
CPU time 8.9 seconds
Started Apr 21 04:04:40 PM PDT 24
Finished Apr 21 04:04:50 PM PDT 24
Peak memory 203936 kb
Host smart-f794eb00-8e7d-4ca9-ab8c-457d3f3399cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42707
21425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.4270721425
Directory /workspace/45.usbdev_setup_stage/latest


Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.2860452720
Short name T1351
Test name
Test status
Simulation time 8373024717 ps
CPU time 7.82 seconds
Started Apr 21 04:04:40 PM PDT 24
Finished Apr 21 04:04:48 PM PDT 24
Peak memory 204056 kb
Host smart-0a0794c9-e802-434d-be01-8738eb3612dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28604
52720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.2860452720
Directory /workspace/45.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/45.usbdev_smoke.323929232
Short name T825
Test name
Test status
Simulation time 8532414429 ps
CPU time 8.07 seconds
Started Apr 21 04:04:37 PM PDT 24
Finished Apr 21 04:04:45 PM PDT 24
Peak memory 204024 kb
Host smart-e8a14849-5557-4852-98a2-8f3f715c9b26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32392
9232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.323929232
Directory /workspace/45.usbdev_smoke/latest


Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.2251238714
Short name T297
Test name
Test status
Simulation time 8367961222 ps
CPU time 8.41 seconds
Started Apr 21 04:04:40 PM PDT 24
Finished Apr 21 04:04:49 PM PDT 24
Peak memory 204068 kb
Host smart-ef1d89af-388b-4188-99af-d7c3e6c81fc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22512
38714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.2251238714
Directory /workspace/45.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/45.usbdev_stall_trans.1413424877
Short name T1246
Test name
Test status
Simulation time 8404725438 ps
CPU time 7.51 seconds
Started Apr 21 04:04:39 PM PDT 24
Finished Apr 21 04:04:47 PM PDT 24
Peak memory 204060 kb
Host smart-475467c3-0543-46a2-9708-18e913fc156a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14134
24877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.1413424877
Directory /workspace/45.usbdev_stall_trans/latest


Test location /workspace/coverage/default/46.max_length_in_transaction.3540938645
Short name T722
Test name
Test status
Simulation time 8465545156 ps
CPU time 8.84 seconds
Started Apr 21 04:04:47 PM PDT 24
Finished Apr 21 04:04:56 PM PDT 24
Peak memory 204044 kb
Host smart-1f434cbb-f3d2-43d1-afbf-41ab31a16575
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3540938645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.3540938645
Directory /workspace/46.max_length_in_transaction/latest


Test location /workspace/coverage/default/46.min_length_in_transaction.2332149062
Short name T994
Test name
Test status
Simulation time 8398988718 ps
CPU time 7.83 seconds
Started Apr 21 04:04:46 PM PDT 24
Finished Apr 21 04:04:54 PM PDT 24
Peak memory 204044 kb
Host smart-609b86f4-d419-4804-8e67-5426644d8fbc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2332149062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.2332149062
Directory /workspace/46.min_length_in_transaction/latest


Test location /workspace/coverage/default/46.random_length_in_trans.1009324365
Short name T1322
Test name
Test status
Simulation time 8381650792 ps
CPU time 8.18 seconds
Started Apr 21 04:04:46 PM PDT 24
Finished Apr 21 04:04:54 PM PDT 24
Peak memory 204080 kb
Host smart-6ccacf21-55e3-4930-90fd-d1ea1474016c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10093
24365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.1009324365
Directory /workspace/46.random_length_in_trans/latest


Test location /workspace/coverage/default/46.usbdev_av_buffer.671948237
Short name T1090
Test name
Test status
Simulation time 8401641175 ps
CPU time 7.56 seconds
Started Apr 21 04:04:42 PM PDT 24
Finished Apr 21 04:04:50 PM PDT 24
Peak memory 204224 kb
Host smart-1417ccb0-7c12-4d22-a7f0-8c34648cc51e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67194
8237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.671948237
Directory /workspace/46.usbdev_av_buffer/latest


Test location /workspace/coverage/default/46.usbdev_enable.2671017467
Short name T1335
Test name
Test status
Simulation time 8444159218 ps
CPU time 8.12 seconds
Started Apr 21 04:04:52 PM PDT 24
Finished Apr 21 04:05:00 PM PDT 24
Peak memory 204036 kb
Host smart-c26c6a5b-80b0-4ef5-9cf4-a58f813b71ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26710
17467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2671017467
Directory /workspace/46.usbdev_enable/latest


Test location /workspace/coverage/default/46.usbdev_fifo_rst.4005665165
Short name T840
Test name
Test status
Simulation time 300804711 ps
CPU time 2.45 seconds
Started Apr 21 04:04:52 PM PDT 24
Finished Apr 21 04:04:54 PM PDT 24
Peak memory 204164 kb
Host smart-905afb04-19c5-4915-a3b9-96cab24593ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40056
65165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.4005665165
Directory /workspace/46.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/46.usbdev_in_iso.741913329
Short name T1029
Test name
Test status
Simulation time 8406397437 ps
CPU time 8.97 seconds
Started Apr 21 04:04:46 PM PDT 24
Finished Apr 21 04:04:55 PM PDT 24
Peak memory 204032 kb
Host smart-1487164f-7ca6-4a39-a061-9feb7d26b24a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74191
3329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.741913329
Directory /workspace/46.usbdev_in_iso/latest


Test location /workspace/coverage/default/46.usbdev_in_stall.1724061698
Short name T5
Test name
Test status
Simulation time 8371560937 ps
CPU time 8.04 seconds
Started Apr 21 04:04:45 PM PDT 24
Finished Apr 21 04:04:53 PM PDT 24
Peak memory 204064 kb
Host smart-b3d3c74b-efa7-4efd-980b-a9acedaba3ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17240
61698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.1724061698
Directory /workspace/46.usbdev_in_stall/latest


Test location /workspace/coverage/default/46.usbdev_in_trans.2619057339
Short name T704
Test name
Test status
Simulation time 8405024618 ps
CPU time 7.86 seconds
Started Apr 21 04:04:52 PM PDT 24
Finished Apr 21 04:05:00 PM PDT 24
Peak memory 204036 kb
Host smart-ef71c366-aa49-4558-927e-ffc543fa4d66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26190
57339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.2619057339
Directory /workspace/46.usbdev_in_trans/latest


Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.683766816
Short name T646
Test name
Test status
Simulation time 8412660797 ps
CPU time 8.06 seconds
Started Apr 21 04:04:43 PM PDT 24
Finished Apr 21 04:04:51 PM PDT 24
Peak memory 204068 kb
Host smart-987ac677-b75d-4acb-8b90-0d4615f17e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68376
6816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.683766816
Directory /workspace/46.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.4045300263
Short name T412
Test name
Test status
Simulation time 8366978372 ps
CPU time 7.67 seconds
Started Apr 21 04:04:42 PM PDT 24
Finished Apr 21 04:04:50 PM PDT 24
Peak memory 204048 kb
Host smart-0e6b176e-620f-47b4-8ffb-dddf39d81790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40453
00263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.4045300263
Directory /workspace/46.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/46.usbdev_nak_trans.405726122
Short name T131
Test name
Test status
Simulation time 8434452181 ps
CPU time 10.09 seconds
Started Apr 21 04:04:44 PM PDT 24
Finished Apr 21 04:04:54 PM PDT 24
Peak memory 204040 kb
Host smart-b90a6293-2702-459d-be0e-7ffba19e3fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40572
6122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.405726122
Directory /workspace/46.usbdev_nak_trans/latest


Test location /workspace/coverage/default/46.usbdev_out_stall.173720927
Short name T1305
Test name
Test status
Simulation time 8393629496 ps
CPU time 8.73 seconds
Started Apr 21 04:04:53 PM PDT 24
Finished Apr 21 04:05:02 PM PDT 24
Peak memory 204036 kb
Host smart-c7ad3e2f-51f7-4c50-81e2-497590d98067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17372
0927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.173720927
Directory /workspace/46.usbdev_out_stall/latest


Test location /workspace/coverage/default/46.usbdev_out_trans_nak.1389862447
Short name T670
Test name
Test status
Simulation time 8373482589 ps
CPU time 8.08 seconds
Started Apr 21 04:04:43 PM PDT 24
Finished Apr 21 04:04:52 PM PDT 24
Peak memory 203456 kb
Host smart-414b5e56-948f-4be7-845c-78b2f02764e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13898
62447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.1389862447
Directory /workspace/46.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/46.usbdev_pending_in_trans.1250241694
Short name T188
Test name
Test status
Simulation time 8390050946 ps
CPU time 7.61 seconds
Started Apr 21 04:04:44 PM PDT 24
Finished Apr 21 04:04:52 PM PDT 24
Peak memory 204024 kb
Host smart-d070d399-8e9b-407d-b273-e238fa918e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12502
41694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.1250241694
Directory /workspace/46.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3682459013
Short name T539
Test name
Test status
Simulation time 8367542801 ps
CPU time 7.48 seconds
Started Apr 21 04:04:53 PM PDT 24
Finished Apr 21 04:05:01 PM PDT 24
Peak memory 204028 kb
Host smart-da94603d-84e0-4107-8c4c-e29c040d5276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36824
59013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3682459013
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.1781159078
Short name T1011
Test name
Test status
Simulation time 37337942 ps
CPU time 0.68 seconds
Started Apr 21 04:04:44 PM PDT 24
Finished Apr 21 04:04:45 PM PDT 24
Peak memory 203932 kb
Host smart-38b18450-1a41-49e7-90ae-5040b2f8cbce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17811
59078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.1781159078
Directory /workspace/46.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/46.usbdev_pkt_buffer.2680616087
Short name T804
Test name
Test status
Simulation time 16325261838 ps
CPU time 31.03 seconds
Started Apr 21 04:04:44 PM PDT 24
Finished Apr 21 04:05:15 PM PDT 24
Peak memory 204324 kb
Host smart-0cb58d44-8041-4e92-bf4c-44b6b75267b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26806
16087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.2680616087
Directory /workspace/46.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/46.usbdev_pkt_received.455711858
Short name T681
Test name
Test status
Simulation time 8402067506 ps
CPU time 7.98 seconds
Started Apr 21 04:04:51 PM PDT 24
Finished Apr 21 04:05:00 PM PDT 24
Peak memory 204032 kb
Host smart-fba00ce3-c401-42c1-9488-f736b6b24582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45571
1858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.455711858
Directory /workspace/46.usbdev_pkt_received/latest


Test location /workspace/coverage/default/46.usbdev_pkt_sent.779295900
Short name T160
Test name
Test status
Simulation time 8386035583 ps
CPU time 9.12 seconds
Started Apr 21 04:04:45 PM PDT 24
Finished Apr 21 04:04:55 PM PDT 24
Peak memory 204076 kb
Host smart-03821d1d-27aa-4b66-a600-fcc7edee8528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77929
5900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.779295900
Directory /workspace/46.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.1933827900
Short name T990
Test name
Test status
Simulation time 8392163531 ps
CPU time 7.81 seconds
Started Apr 21 04:04:44 PM PDT 24
Finished Apr 21 04:04:52 PM PDT 24
Peak memory 204060 kb
Host smart-d395c8c1-b611-4067-bc19-87f59a5caeba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19338
27900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.1933827900
Directory /workspace/46.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/46.usbdev_setup_stage.1031582395
Short name T974
Test name
Test status
Simulation time 8374732252 ps
CPU time 8.3 seconds
Started Apr 21 04:04:44 PM PDT 24
Finished Apr 21 04:04:53 PM PDT 24
Peak memory 204080 kb
Host smart-4b25baa4-67c3-415c-a77b-ad5a2a9ba1e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10315
82395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.1031582395
Directory /workspace/46.usbdev_setup_stage/latest


Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.1423273333
Short name T732
Test name
Test status
Simulation time 8432727303 ps
CPU time 9.03 seconds
Started Apr 21 04:04:46 PM PDT 24
Finished Apr 21 04:04:55 PM PDT 24
Peak memory 204076 kb
Host smart-f471e5bf-7c8a-4253-930f-46bfb4250cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14232
73333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.1423273333
Directory /workspace/46.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/46.usbdev_smoke.3764314522
Short name T155
Test name
Test status
Simulation time 8446071059 ps
CPU time 7.77 seconds
Started Apr 21 04:04:42 PM PDT 24
Finished Apr 21 04:04:50 PM PDT 24
Peak memory 203456 kb
Host smart-4b5cd328-ca94-410c-b4f5-660640510b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37643
14522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3764314522
Directory /workspace/46.usbdev_smoke/latest


Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.2925201066
Short name T1353
Test name
Test status
Simulation time 8395195236 ps
CPU time 8.06 seconds
Started Apr 21 04:04:44 PM PDT 24
Finished Apr 21 04:04:53 PM PDT 24
Peak memory 204048 kb
Host smart-da788244-de81-4930-81ac-fa5b2dcdd5ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29252
01066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.2925201066
Directory /workspace/46.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/46.usbdev_stall_trans.3508989632
Short name T1352
Test name
Test status
Simulation time 8390484286 ps
CPU time 7.56 seconds
Started Apr 21 04:04:46 PM PDT 24
Finished Apr 21 04:04:53 PM PDT 24
Peak memory 204060 kb
Host smart-3a4daeab-76e9-4d8b-a41b-6372cff8169e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35089
89632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.3508989632
Directory /workspace/46.usbdev_stall_trans/latest


Test location /workspace/coverage/default/47.max_length_in_transaction.385710738
Short name T583
Test name
Test status
Simulation time 8460621431 ps
CPU time 8.51 seconds
Started Apr 21 04:04:56 PM PDT 24
Finished Apr 21 04:05:04 PM PDT 24
Peak memory 204044 kb
Host smart-65db280c-3703-41ad-9ad2-895a93fc46ce
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=385710738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.385710738
Directory /workspace/47.max_length_in_transaction/latest


Test location /workspace/coverage/default/47.min_length_in_transaction.462634161
Short name T342
Test name
Test status
Simulation time 8381788359 ps
CPU time 8.18 seconds
Started Apr 21 04:04:55 PM PDT 24
Finished Apr 21 04:05:03 PM PDT 24
Peak memory 204020 kb
Host smart-d4bf0c2a-018c-4b01-bdba-bb25ce777c0a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=462634161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.462634161
Directory /workspace/47.min_length_in_transaction/latest


Test location /workspace/coverage/default/47.random_length_in_trans.895260669
Short name T1059
Test name
Test status
Simulation time 8402873291 ps
CPU time 8.17 seconds
Started Apr 21 04:04:55 PM PDT 24
Finished Apr 21 04:05:04 PM PDT 24
Peak memory 204016 kb
Host smart-b558df41-bf05-491e-9182-30971ffa918a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89526
0669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.895260669
Directory /workspace/47.random_length_in_trans/latest


Test location /workspace/coverage/default/47.usbdev_av_buffer.2261286456
Short name T564
Test name
Test status
Simulation time 8379496634 ps
CPU time 8.01 seconds
Started Apr 21 04:04:51 PM PDT 24
Finished Apr 21 04:04:59 PM PDT 24
Peak memory 204068 kb
Host smart-1d26fd25-5ba7-4f60-a548-eb853615ec9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22612
86456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2261286456
Directory /workspace/47.usbdev_av_buffer/latest


Test location /workspace/coverage/default/47.usbdev_enable.1397358891
Short name T774
Test name
Test status
Simulation time 8382405276 ps
CPU time 7.9 seconds
Started Apr 21 04:04:47 PM PDT 24
Finished Apr 21 04:04:55 PM PDT 24
Peak memory 203948 kb
Host smart-dabc9163-8f1b-404a-814c-cdde3b366e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13973
58891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.1397358891
Directory /workspace/47.usbdev_enable/latest


Test location /workspace/coverage/default/47.usbdev_fifo_rst.3944675912
Short name T1328
Test name
Test status
Simulation time 306225797 ps
CPU time 2.65 seconds
Started Apr 21 04:04:47 PM PDT 24
Finished Apr 21 04:04:50 PM PDT 24
Peak memory 204204 kb
Host smart-c2259994-87f8-46a7-836c-314d13fbe24b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39446
75912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3944675912
Directory /workspace/47.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/47.usbdev_in_iso.3212558495
Short name T1321
Test name
Test status
Simulation time 8382475292 ps
CPU time 8.14 seconds
Started Apr 21 04:04:54 PM PDT 24
Finished Apr 21 04:05:03 PM PDT 24
Peak memory 203988 kb
Host smart-b0e855d2-5c8f-4e4c-b882-c9c793b20a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32125
58495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.3212558495
Directory /workspace/47.usbdev_in_iso/latest


Test location /workspace/coverage/default/47.usbdev_in_stall.459981242
Short name T1143
Test name
Test status
Simulation time 8368132079 ps
CPU time 7.76 seconds
Started Apr 21 04:04:54 PM PDT 24
Finished Apr 21 04:05:02 PM PDT 24
Peak memory 204056 kb
Host smart-07904756-0960-41e5-a54b-5a0f7eced884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45998
1242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.459981242
Directory /workspace/47.usbdev_in_stall/latest


Test location /workspace/coverage/default/47.usbdev_in_trans.1756068208
Short name T619
Test name
Test status
Simulation time 8459064141 ps
CPU time 8.28 seconds
Started Apr 21 04:04:47 PM PDT 24
Finished Apr 21 04:04:56 PM PDT 24
Peak memory 204060 kb
Host smart-4faf6b15-5bee-47b2-b948-ed2622504d48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17560
68208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.1756068208
Directory /workspace/47.usbdev_in_trans/latest


Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.2314891532
Short name T952
Test name
Test status
Simulation time 8413344780 ps
CPU time 8.39 seconds
Started Apr 21 04:04:49 PM PDT 24
Finished Apr 21 04:04:58 PM PDT 24
Peak memory 204064 kb
Host smart-9123c948-e536-43d8-aee4-d277e781b41e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23148
91532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.2314891532
Directory /workspace/47.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.3595204945
Short name T796
Test name
Test status
Simulation time 8371809025 ps
CPU time 8.16 seconds
Started Apr 21 04:04:50 PM PDT 24
Finished Apr 21 04:04:59 PM PDT 24
Peak memory 204080 kb
Host smart-93886cb1-a67d-404b-b7fb-99bb30301f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35952
04945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.3595204945
Directory /workspace/47.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/47.usbdev_nak_trans.2078114276
Short name T1062
Test name
Test status
Simulation time 8425486919 ps
CPU time 7.88 seconds
Started Apr 21 04:04:51 PM PDT 24
Finished Apr 21 04:04:59 PM PDT 24
Peak memory 204028 kb
Host smart-65aa740f-eb61-4699-93a2-fec8d0e04f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20781
14276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.2078114276
Directory /workspace/47.usbdev_nak_trans/latest


Test location /workspace/coverage/default/47.usbdev_out_stall.435794698
Short name T844
Test name
Test status
Simulation time 8396823791 ps
CPU time 9.72 seconds
Started Apr 21 04:04:50 PM PDT 24
Finished Apr 21 04:05:00 PM PDT 24
Peak memory 204040 kb
Host smart-8c07faec-a91d-40dd-a58a-1aa994724b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43579
4698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.435794698
Directory /workspace/47.usbdev_out_stall/latest


Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1535782068
Short name T224
Test name
Test status
Simulation time 8384954525 ps
CPU time 8.88 seconds
Started Apr 21 04:04:49 PM PDT 24
Finished Apr 21 04:04:58 PM PDT 24
Peak memory 204032 kb
Host smart-e87480a4-115c-4a14-9250-657cf212bde9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15357
82068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1535782068
Directory /workspace/47.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/47.usbdev_pending_in_trans.627911264
Short name T767
Test name
Test status
Simulation time 8401972120 ps
CPU time 10.55 seconds
Started Apr 21 04:04:53 PM PDT 24
Finished Apr 21 04:05:04 PM PDT 24
Peak memory 204064 kb
Host smart-d2bb1c8a-5ff4-4d10-93e6-ab7b45f38bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62791
1264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.627911264
Directory /workspace/47.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.3122433837
Short name T736
Test name
Test status
Simulation time 8383027389 ps
CPU time 10.04 seconds
Started Apr 21 04:04:53 PM PDT 24
Finished Apr 21 04:05:04 PM PDT 24
Peak memory 204060 kb
Host smart-8954ffa2-764c-4e2b-9421-bf43269202f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31224
33837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.3122433837
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2472354002
Short name T453
Test name
Test status
Simulation time 45249960 ps
CPU time 0.75 seconds
Started Apr 21 04:04:56 PM PDT 24
Finished Apr 21 04:04:57 PM PDT 24
Peak memory 203932 kb
Host smart-3c7db301-cab7-4386-9b20-c5d74bb1b2eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24723
54002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2472354002
Directory /workspace/47.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/47.usbdev_pkt_buffer.2108348137
Short name T414
Test name
Test status
Simulation time 25789449403 ps
CPU time 53.07 seconds
Started Apr 21 04:04:51 PM PDT 24
Finished Apr 21 04:05:44 PM PDT 24
Peak memory 204348 kb
Host smart-b84cdce1-af4d-4eeb-ae14-d383ee91af54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21083
48137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.2108348137
Directory /workspace/47.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/47.usbdev_pkt_received.2769743776
Short name T515
Test name
Test status
Simulation time 8425185070 ps
CPU time 7.52 seconds
Started Apr 21 04:04:52 PM PDT 24
Finished Apr 21 04:05:00 PM PDT 24
Peak memory 204064 kb
Host smart-b45bcad4-e058-47c0-9e72-ecf8212cc1d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27697
43776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.2769743776
Directory /workspace/47.usbdev_pkt_received/latest


Test location /workspace/coverage/default/47.usbdev_pkt_sent.3590594945
Short name T747
Test name
Test status
Simulation time 8468469571 ps
CPU time 8.33 seconds
Started Apr 21 04:04:51 PM PDT 24
Finished Apr 21 04:04:59 PM PDT 24
Peak memory 204028 kb
Host smart-3ee357c5-e43d-40a8-bcec-e8b4fbe05b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35905
94945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3590594945
Directory /workspace/47.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.3447267595
Short name T590
Test name
Test status
Simulation time 8406953641 ps
CPU time 8.98 seconds
Started Apr 21 04:04:50 PM PDT 24
Finished Apr 21 04:04:59 PM PDT 24
Peak memory 204040 kb
Host smart-3e0dbe23-b29f-4004-836b-1e4db6e9f04f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34472
67595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.3447267595
Directory /workspace/47.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/47.usbdev_setup_stage.1577121389
Short name T773
Test name
Test status
Simulation time 8375584326 ps
CPU time 8.43 seconds
Started Apr 21 04:04:54 PM PDT 24
Finished Apr 21 04:05:02 PM PDT 24
Peak memory 204040 kb
Host smart-48f2e880-e057-4f61-8dde-dae9382c33a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15771
21389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1577121389
Directory /workspace/47.usbdev_setup_stage/latest


Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.4205215559
Short name T459
Test name
Test status
Simulation time 8369867190 ps
CPU time 10 seconds
Started Apr 21 04:04:53 PM PDT 24
Finished Apr 21 04:05:03 PM PDT 24
Peak memory 204000 kb
Host smart-48890935-982a-49cd-b05c-bdaadcbbd9d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42052
15559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.4205215559
Directory /workspace/47.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/47.usbdev_smoke.3956884977
Short name T909
Test name
Test status
Simulation time 8410287023 ps
CPU time 7.83 seconds
Started Apr 21 04:04:50 PM PDT 24
Finished Apr 21 04:04:58 PM PDT 24
Peak memory 204068 kb
Host smart-4503955c-20d5-4f80-8827-805eb6077d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39568
84977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.3956884977
Directory /workspace/47.usbdev_smoke/latest


Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.3197959234
Short name T604
Test name
Test status
Simulation time 8415410538 ps
CPU time 8.37 seconds
Started Apr 21 04:04:52 PM PDT 24
Finished Apr 21 04:05:01 PM PDT 24
Peak memory 204036 kb
Host smart-c698682d-c18d-44f3-918c-3b65ca540697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31979
59234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.3197959234
Directory /workspace/47.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/47.usbdev_stall_trans.1945311142
Short name T524
Test name
Test status
Simulation time 8415256797 ps
CPU time 8.32 seconds
Started Apr 21 04:04:53 PM PDT 24
Finished Apr 21 04:05:02 PM PDT 24
Peak memory 204060 kb
Host smart-48938fa7-40b7-4cad-bea5-2a8e17944672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19453
11142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.1945311142
Directory /workspace/47.usbdev_stall_trans/latest


Test location /workspace/coverage/default/48.max_length_in_transaction.2314395268
Short name T1339
Test name
Test status
Simulation time 8515304613 ps
CPU time 7.78 seconds
Started Apr 21 04:05:05 PM PDT 24
Finished Apr 21 04:05:13 PM PDT 24
Peak memory 204048 kb
Host smart-a7b25f0b-1c93-4d34-8a86-ef5fe4578b93
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2314395268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.2314395268
Directory /workspace/48.max_length_in_transaction/latest


Test location /workspace/coverage/default/48.min_length_in_transaction.1999934831
Short name T328
Test name
Test status
Simulation time 8377569986 ps
CPU time 8.31 seconds
Started Apr 21 04:05:04 PM PDT 24
Finished Apr 21 04:05:13 PM PDT 24
Peak memory 204000 kb
Host smart-578b29be-c647-4b99-9f80-af062d5b8c23
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1999934831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.1999934831
Directory /workspace/48.min_length_in_transaction/latest


Test location /workspace/coverage/default/48.random_length_in_trans.759602229
Short name T752
Test name
Test status
Simulation time 8439545154 ps
CPU time 9.04 seconds
Started Apr 21 04:05:01 PM PDT 24
Finished Apr 21 04:05:10 PM PDT 24
Peak memory 204016 kb
Host smart-24bfe72d-4acf-42d5-b689-d1914ac73762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75960
2229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.759602229
Directory /workspace/48.random_length_in_trans/latest


Test location /workspace/coverage/default/48.usbdev_av_buffer.2669483202
Short name T537
Test name
Test status
Simulation time 8390618196 ps
CPU time 7.68 seconds
Started Apr 21 04:04:57 PM PDT 24
Finished Apr 21 04:05:05 PM PDT 24
Peak memory 204040 kb
Host smart-0906684d-4e00-4c1c-9e67-da44a2b43c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26694
83202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.2669483202
Directory /workspace/48.usbdev_av_buffer/latest


Test location /workspace/coverage/default/48.usbdev_enable.2482257992
Short name T626
Test name
Test status
Simulation time 8403612321 ps
CPU time 8.34 seconds
Started Apr 21 04:04:58 PM PDT 24
Finished Apr 21 04:05:07 PM PDT 24
Peak memory 204088 kb
Host smart-9eb628a4-e4e6-4971-b564-5b7f8b0b093c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24822
57992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.2482257992
Directory /workspace/48.usbdev_enable/latest


Test location /workspace/coverage/default/48.usbdev_fifo_rst.3469591524
Short name T1086
Test name
Test status
Simulation time 74301338 ps
CPU time 1.95 seconds
Started Apr 21 04:04:57 PM PDT 24
Finished Apr 21 04:04:59 PM PDT 24
Peak memory 204152 kb
Host smart-7b894e36-9a75-491b-8758-480a6243f55b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34695
91524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3469591524
Directory /workspace/48.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/48.usbdev_in_iso.3569254797
Short name T687
Test name
Test status
Simulation time 8456590458 ps
CPU time 8.36 seconds
Started Apr 21 04:05:03 PM PDT 24
Finished Apr 21 04:05:12 PM PDT 24
Peak memory 204024 kb
Host smart-573f9d8b-d652-4a32-9717-5d961284a549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35692
54797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3569254797
Directory /workspace/48.usbdev_in_iso/latest


Test location /workspace/coverage/default/48.usbdev_in_stall.894364437
Short name T193
Test name
Test status
Simulation time 8365875547 ps
CPU time 8.74 seconds
Started Apr 21 04:05:05 PM PDT 24
Finished Apr 21 04:05:14 PM PDT 24
Peak memory 204048 kb
Host smart-6914c509-ece9-430f-8683-ac884f147ee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89436
4437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.894364437
Directory /workspace/48.usbdev_in_stall/latest


Test location /workspace/coverage/default/48.usbdev_in_trans.885915677
Short name T158
Test name
Test status
Simulation time 8406374329 ps
CPU time 9.36 seconds
Started Apr 21 04:04:58 PM PDT 24
Finished Apr 21 04:05:08 PM PDT 24
Peak memory 204056 kb
Host smart-984db64c-0a10-4de5-9c3f-c9c151dbf9ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88591
5677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.885915677
Directory /workspace/48.usbdev_in_trans/latest


Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3104409056
Short name T1093
Test name
Test status
Simulation time 8441005839 ps
CPU time 9.2 seconds
Started Apr 21 04:05:00 PM PDT 24
Finished Apr 21 04:05:09 PM PDT 24
Peak memory 204064 kb
Host smart-4856120e-fa16-423e-8433-8ceec0356614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31044
09056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3104409056
Directory /workspace/48.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2951811991
Short name T335
Test name
Test status
Simulation time 8434241907 ps
CPU time 8.4 seconds
Started Apr 21 04:04:57 PM PDT 24
Finished Apr 21 04:05:06 PM PDT 24
Peak memory 204052 kb
Host smart-4731f767-aafa-4932-84c7-5a5fba71ec41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29518
11991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2951811991
Directory /workspace/48.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/48.usbdev_nak_trans.2277209147
Short name T115
Test name
Test status
Simulation time 8459502485 ps
CPU time 8.58 seconds
Started Apr 21 04:05:00 PM PDT 24
Finished Apr 21 04:05:09 PM PDT 24
Peak memory 204068 kb
Host smart-777cc154-64d2-4d58-a914-a12cd112a7f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22772
09147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.2277209147
Directory /workspace/48.usbdev_nak_trans/latest


Test location /workspace/coverage/default/48.usbdev_out_stall.1553225645
Short name T1156
Test name
Test status
Simulation time 8388430237 ps
CPU time 8.65 seconds
Started Apr 21 04:05:02 PM PDT 24
Finished Apr 21 04:05:11 PM PDT 24
Peak memory 204056 kb
Host smart-d5d81236-0dee-4523-ab7c-a24b1ff0c6dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15532
25645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.1553225645
Directory /workspace/48.usbdev_out_stall/latest


Test location /workspace/coverage/default/48.usbdev_out_trans_nak.3240404438
Short name T997
Test name
Test status
Simulation time 8384301411 ps
CPU time 7.83 seconds
Started Apr 21 04:04:59 PM PDT 24
Finished Apr 21 04:05:08 PM PDT 24
Peak memory 204068 kb
Host smart-1962fc48-995d-4c91-96ec-8d65b897cef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32404
04438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.3240404438
Directory /workspace/48.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/48.usbdev_pending_in_trans.2343671684
Short name T507
Test name
Test status
Simulation time 8392934231 ps
CPU time 8.56 seconds
Started Apr 21 04:05:02 PM PDT 24
Finished Apr 21 04:05:11 PM PDT 24
Peak memory 204044 kb
Host smart-26a42b61-6c89-4d1c-828e-7aa795df43fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23436
71684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.2343671684
Directory /workspace/48.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.1605855864
Short name T21
Test name
Test status
Simulation time 8385622047 ps
CPU time 9.54 seconds
Started Apr 21 04:05:03 PM PDT 24
Finished Apr 21 04:05:13 PM PDT 24
Peak memory 204060 kb
Host smart-30541273-83ca-4a0d-8dfa-4f38a163e73f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16058
55864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.1605855864
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.4005915064
Short name T801
Test name
Test status
Simulation time 58903096 ps
CPU time 0.69 seconds
Started Apr 21 04:05:03 PM PDT 24
Finished Apr 21 04:05:04 PM PDT 24
Peak memory 203912 kb
Host smart-757d6e73-17ab-44a8-ab2e-0791640c5089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40059
15064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.4005915064
Directory /workspace/48.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/48.usbdev_pkt_buffer.3948616339
Short name T939
Test name
Test status
Simulation time 14856284604 ps
CPU time 28 seconds
Started Apr 21 04:05:01 PM PDT 24
Finished Apr 21 04:05:29 PM PDT 24
Peak memory 204352 kb
Host smart-ecacb68f-daa9-455a-9793-9dede0194dc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39486
16339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.3948616339
Directory /workspace/48.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/48.usbdev_pkt_received.7845568
Short name T1237
Test name
Test status
Simulation time 8413055730 ps
CPU time 9.36 seconds
Started Apr 21 04:04:59 PM PDT 24
Finished Apr 21 04:05:08 PM PDT 24
Peak memory 204076 kb
Host smart-edde2e55-1bbe-487c-a818-79391baf77e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78455
68 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.7845568
Directory /workspace/48.usbdev_pkt_received/latest


Test location /workspace/coverage/default/48.usbdev_pkt_sent.1750979303
Short name T446
Test name
Test status
Simulation time 8469785572 ps
CPU time 10.18 seconds
Started Apr 21 04:05:00 PM PDT 24
Finished Apr 21 04:05:11 PM PDT 24
Peak memory 204068 kb
Host smart-3acbae9c-4fa4-43b0-8c4b-5d830f3fc3e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17509
79303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.1750979303
Directory /workspace/48.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.3854040391
Short name T398
Test name
Test status
Simulation time 8416250685 ps
CPU time 7.48 seconds
Started Apr 21 04:05:02 PM PDT 24
Finished Apr 21 04:05:09 PM PDT 24
Peak memory 204052 kb
Host smart-8b036bf2-b6ea-474e-b71e-46486891b54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38540
40391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.3854040391
Directory /workspace/48.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/48.usbdev_setup_stage.3928634450
Short name T1354
Test name
Test status
Simulation time 8392561796 ps
CPU time 9.75 seconds
Started Apr 21 04:05:04 PM PDT 24
Finished Apr 21 04:05:14 PM PDT 24
Peak memory 204056 kb
Host smart-a303eb84-010b-4c80-8924-16ebbede1817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39286
34450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3928634450
Directory /workspace/48.usbdev_setup_stage/latest


Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.3092409647
Short name T699
Test name
Test status
Simulation time 8384825275 ps
CPU time 7.47 seconds
Started Apr 21 04:05:04 PM PDT 24
Finished Apr 21 04:05:12 PM PDT 24
Peak memory 204028 kb
Host smart-8e71835c-d775-4887-ac34-40fb47bc2070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30924
09647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.3092409647
Directory /workspace/48.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/48.usbdev_smoke.1791640481
Short name T150
Test name
Test status
Simulation time 8450550628 ps
CPU time 8.66 seconds
Started Apr 21 04:04:58 PM PDT 24
Finished Apr 21 04:05:07 PM PDT 24
Peak memory 204088 kb
Host smart-0b9a2e71-4a87-4f1e-a628-e059f5ad5aa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17916
40481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1791640481
Directory /workspace/48.usbdev_smoke/latest


Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.1025274458
Short name T504
Test name
Test status
Simulation time 8386913455 ps
CPU time 9.03 seconds
Started Apr 21 04:05:00 PM PDT 24
Finished Apr 21 04:05:10 PM PDT 24
Peak memory 204048 kb
Host smart-681da3ca-d8bf-498f-bf7f-0ba4d2bd6c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10252
74458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.1025274458
Directory /workspace/48.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/48.usbdev_stall_trans.895358234
Short name T1379
Test name
Test status
Simulation time 8402288075 ps
CPU time 8.05 seconds
Started Apr 21 04:05:02 PM PDT 24
Finished Apr 21 04:05:10 PM PDT 24
Peak memory 204040 kb
Host smart-cccecc00-02d2-472d-83f8-441fb6b0daec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89535
8234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.895358234
Directory /workspace/48.usbdev_stall_trans/latest


Test location /workspace/coverage/default/49.max_length_in_transaction.2350246428
Short name T851
Test name
Test status
Simulation time 8470353441 ps
CPU time 8.15 seconds
Started Apr 21 04:05:14 PM PDT 24
Finished Apr 21 04:05:22 PM PDT 24
Peak memory 204088 kb
Host smart-d944ac03-3d30-4c4b-9345-18625c2fce5b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2350246428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.2350246428
Directory /workspace/49.max_length_in_transaction/latest


Test location /workspace/coverage/default/49.min_length_in_transaction.3255371475
Short name T498
Test name
Test status
Simulation time 8373654557 ps
CPU time 9.29 seconds
Started Apr 21 04:05:11 PM PDT 24
Finished Apr 21 04:05:21 PM PDT 24
Peak memory 204064 kb
Host smart-443eade9-992b-4269-b8ac-2c3858276df4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3255371475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.3255371475
Directory /workspace/49.min_length_in_transaction/latest


Test location /workspace/coverage/default/49.random_length_in_trans.1143545198
Short name T595
Test name
Test status
Simulation time 8432611594 ps
CPU time 8.4 seconds
Started Apr 21 04:05:11 PM PDT 24
Finished Apr 21 04:05:20 PM PDT 24
Peak memory 204060 kb
Host smart-e57c18ac-8988-46d7-843f-fcc6d44ba912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11435
45198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.1143545198
Directory /workspace/49.random_length_in_trans/latest


Test location /workspace/coverage/default/49.usbdev_av_buffer.507764970
Short name T1216
Test name
Test status
Simulation time 8374922024 ps
CPU time 7.85 seconds
Started Apr 21 04:05:04 PM PDT 24
Finished Apr 21 04:05:12 PM PDT 24
Peak memory 204068 kb
Host smart-7e38ee12-56a7-43cb-9164-e1bba4655c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50776
4970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.507764970
Directory /workspace/49.usbdev_av_buffer/latest


Test location /workspace/coverage/default/49.usbdev_enable.2470492836
Short name T914
Test name
Test status
Simulation time 8388741023 ps
CPU time 8.75 seconds
Started Apr 21 04:05:04 PM PDT 24
Finished Apr 21 04:05:13 PM PDT 24
Peak memory 204048 kb
Host smart-311414d0-3200-4ba2-b73d-0884274909be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24704
92836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.2470492836
Directory /workspace/49.usbdev_enable/latest


Test location /workspace/coverage/default/49.usbdev_in_iso.3728541943
Short name T364
Test name
Test status
Simulation time 8402546511 ps
CPU time 8.52 seconds
Started Apr 21 04:05:11 PM PDT 24
Finished Apr 21 04:05:20 PM PDT 24
Peak memory 204068 kb
Host smart-6d93fbfd-00e6-47f5-a88a-7313e8cec047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37285
41943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.3728541943
Directory /workspace/49.usbdev_in_iso/latest


Test location /workspace/coverage/default/49.usbdev_in_stall.3524587210
Short name T1160
Test name
Test status
Simulation time 8363779782 ps
CPU time 8.87 seconds
Started Apr 21 04:05:14 PM PDT 24
Finished Apr 21 04:05:23 PM PDT 24
Peak memory 204084 kb
Host smart-51b10235-dde9-4635-9ba3-a277968e25ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35245
87210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.3524587210
Directory /workspace/49.usbdev_in_stall/latest


Test location /workspace/coverage/default/49.usbdev_in_trans.2138453729
Short name T674
Test name
Test status
Simulation time 8426908559 ps
CPU time 8.27 seconds
Started Apr 21 04:05:07 PM PDT 24
Finished Apr 21 04:05:15 PM PDT 24
Peak memory 204064 kb
Host smart-91ba1e4a-4b57-46c0-a057-365e1c3761d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21384
53729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.2138453729
Directory /workspace/49.usbdev_in_trans/latest


Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.3090547048
Short name T696
Test name
Test status
Simulation time 8414789306 ps
CPU time 8.99 seconds
Started Apr 21 04:05:06 PM PDT 24
Finished Apr 21 04:05:15 PM PDT 24
Peak memory 204024 kb
Host smart-4dda81aa-3c3a-499d-986d-5d07434c2a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30905
47048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.3090547048
Directory /workspace/49.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.913134636
Short name T1055
Test name
Test status
Simulation time 8369904025 ps
CPU time 7.65 seconds
Started Apr 21 04:05:05 PM PDT 24
Finished Apr 21 04:05:13 PM PDT 24
Peak memory 204080 kb
Host smart-d0069672-952f-422f-b262-fd404d32127e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91313
4636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.913134636
Directory /workspace/49.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/49.usbdev_nak_trans.1581030722
Short name T123
Test name
Test status
Simulation time 8460718390 ps
CPU time 8.74 seconds
Started Apr 21 04:05:06 PM PDT 24
Finished Apr 21 04:05:15 PM PDT 24
Peak memory 204048 kb
Host smart-794acfd2-ff5a-4c43-8018-101907b23568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15810
30722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.1581030722
Directory /workspace/49.usbdev_nak_trans/latest


Test location /workspace/coverage/default/49.usbdev_out_stall.1270811960
Short name T315
Test name
Test status
Simulation time 8383617978 ps
CPU time 8.3 seconds
Started Apr 21 04:05:05 PM PDT 24
Finished Apr 21 04:05:14 PM PDT 24
Peak memory 204060 kb
Host smart-e2343dd1-ef64-499f-ab94-24d72bd79948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12708
11960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1270811960
Directory /workspace/49.usbdev_out_stall/latest


Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2597344529
Short name T934
Test name
Test status
Simulation time 8399630577 ps
CPU time 9.58 seconds
Started Apr 21 04:05:09 PM PDT 24
Finished Apr 21 04:05:19 PM PDT 24
Peak memory 204064 kb
Host smart-2bcc212c-d9b9-4436-b099-d6999279ebaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25973
44529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2597344529
Directory /workspace/49.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/49.usbdev_pending_in_trans.1033196368
Short name T633
Test name
Test status
Simulation time 8380648586 ps
CPU time 8.65 seconds
Started Apr 21 04:05:12 PM PDT 24
Finished Apr 21 04:05:21 PM PDT 24
Peak memory 204040 kb
Host smart-c36bdccd-939e-43ca-9e62-0d1c718cec1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10331
96368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.1033196368
Directory /workspace/49.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.227150480
Short name T703
Test name
Test status
Simulation time 8372542444 ps
CPU time 9.87 seconds
Started Apr 21 04:05:10 PM PDT 24
Finished Apr 21 04:05:21 PM PDT 24
Peak memory 204064 kb
Host smart-ff8c4123-3ad2-4f02-9532-13ef5aa353b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22715
0480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.227150480
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.3496650467
Short name T44
Test name
Test status
Simulation time 108496310 ps
CPU time 0.72 seconds
Started Apr 21 04:05:10 PM PDT 24
Finished Apr 21 04:05:11 PM PDT 24
Peak memory 203928 kb
Host smart-201a0e32-11cb-483b-ac25-531c4fceb402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34966
50467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.3496650467
Directory /workspace/49.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/49.usbdev_pkt_buffer.2997565734
Short name T1200
Test name
Test status
Simulation time 28590608134 ps
CPU time 62.1 seconds
Started Apr 21 04:05:08 PM PDT 24
Finished Apr 21 04:06:10 PM PDT 24
Peak memory 204344 kb
Host smart-abb3d74a-70a2-4875-9e5c-cc3c6ec6adaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29975
65734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.2997565734
Directory /workspace/49.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/49.usbdev_pkt_received.4258609816
Short name T533
Test name
Test status
Simulation time 8479327098 ps
CPU time 8.13 seconds
Started Apr 21 04:05:10 PM PDT 24
Finished Apr 21 04:05:18 PM PDT 24
Peak memory 204044 kb
Host smart-2f1f305e-59da-4e52-a002-76098860ee30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42586
09816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.4258609816
Directory /workspace/49.usbdev_pkt_received/latest


Test location /workspace/coverage/default/49.usbdev_pkt_sent.512485842
Short name T942
Test name
Test status
Simulation time 8457271084 ps
CPU time 7.9 seconds
Started Apr 21 04:05:07 PM PDT 24
Finished Apr 21 04:05:16 PM PDT 24
Peak memory 204072 kb
Host smart-7efb710b-6cc0-400e-9135-b5ce85ed14bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51248
5842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.512485842
Directory /workspace/49.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.1596893639
Short name T849
Test name
Test status
Simulation time 8402879004 ps
CPU time 7.84 seconds
Started Apr 21 04:05:09 PM PDT 24
Finished Apr 21 04:05:17 PM PDT 24
Peak memory 204040 kb
Host smart-43bdd347-684e-4e3b-803a-bbd58a083b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15968
93639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.1596893639
Directory /workspace/49.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/49.usbdev_setup_stage.4114694999
Short name T165
Test name
Test status
Simulation time 8374268061 ps
CPU time 9.1 seconds
Started Apr 21 04:05:14 PM PDT 24
Finished Apr 21 04:05:23 PM PDT 24
Peak memory 204080 kb
Host smart-97286d01-1150-42b6-8d4c-a28ce15178e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41146
94999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.4114694999
Directory /workspace/49.usbdev_setup_stage/latest


Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.2241857916
Short name T1175
Test name
Test status
Simulation time 8372964038 ps
CPU time 10.06 seconds
Started Apr 21 04:05:08 PM PDT 24
Finished Apr 21 04:05:18 PM PDT 24
Peak memory 204060 kb
Host smart-81034e03-1a34-421d-8f8e-2165cf8245ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22418
57916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.2241857916
Directory /workspace/49.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/49.usbdev_smoke.4019944454
Short name T926
Test name
Test status
Simulation time 8462373979 ps
CPU time 7.89 seconds
Started Apr 21 04:05:04 PM PDT 24
Finished Apr 21 04:05:12 PM PDT 24
Peak memory 204044 kb
Host smart-53f24ef6-f000-42dd-908c-888242ce45be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40199
44454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.4019944454
Directory /workspace/49.usbdev_smoke/latest


Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.2240677127
Short name T377
Test name
Test status
Simulation time 8375493990 ps
CPU time 7.42 seconds
Started Apr 21 04:05:08 PM PDT 24
Finished Apr 21 04:05:15 PM PDT 24
Peak memory 203996 kb
Host smart-dd615bd1-e429-441e-b2ff-719bc7fbd76b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22406
77127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.2240677127
Directory /workspace/49.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/49.usbdev_stall_trans.4166558747
Short name T476
Test name
Test status
Simulation time 8409050509 ps
CPU time 8.8 seconds
Started Apr 21 04:05:06 PM PDT 24
Finished Apr 21 04:05:15 PM PDT 24
Peak memory 204024 kb
Host smart-9e569ed6-0527-4408-9820-fdbe5da62884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41665
58747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.4166558747
Directory /workspace/49.usbdev_stall_trans/latest


Test location /workspace/coverage/default/5.max_length_in_transaction.1604259755
Short name T337
Test name
Test status
Simulation time 8458564936 ps
CPU time 7.59 seconds
Started Apr 21 03:58:15 PM PDT 24
Finished Apr 21 03:58:22 PM PDT 24
Peak memory 204020 kb
Host smart-028e8e83-d16f-4bf5-ba54-09312e209057
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1604259755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.1604259755
Directory /workspace/5.max_length_in_transaction/latest


Test location /workspace/coverage/default/5.min_length_in_transaction.2093288602
Short name T671
Test name
Test status
Simulation time 8385595252 ps
CPU time 10.35 seconds
Started Apr 21 03:58:14 PM PDT 24
Finished Apr 21 03:58:25 PM PDT 24
Peak memory 204044 kb
Host smart-fbacced6-122d-4bed-9871-2ee8a3eb204d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2093288602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.2093288602
Directory /workspace/5.min_length_in_transaction/latest


Test location /workspace/coverage/default/5.random_length_in_trans.2449796267
Short name T627
Test name
Test status
Simulation time 8412525945 ps
CPU time 7.62 seconds
Started Apr 21 03:58:14 PM PDT 24
Finished Apr 21 03:58:22 PM PDT 24
Peak memory 204040 kb
Host smart-507b5bac-ddda-44bd-a151-064694ce0d75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24497
96267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.2449796267
Directory /workspace/5.random_length_in_trans/latest


Test location /workspace/coverage/default/5.usbdev_av_buffer.2913376343
Short name T652
Test name
Test status
Simulation time 8379128743 ps
CPU time 7.9 seconds
Started Apr 21 03:58:01 PM PDT 24
Finished Apr 21 03:58:09 PM PDT 24
Peak memory 204088 kb
Host smart-05ea225f-b166-4d6a-a30e-3a83b4881dd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29133
76343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.2913376343
Directory /workspace/5.usbdev_av_buffer/latest


Test location /workspace/coverage/default/5.usbdev_enable.1942064857
Short name T718
Test name
Test status
Simulation time 8381972210 ps
CPU time 7.54 seconds
Started Apr 21 03:57:59 PM PDT 24
Finished Apr 21 03:58:07 PM PDT 24
Peak memory 204088 kb
Host smart-2cfcc844-1723-432e-bb9f-d462df0eb526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19420
64857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.1942064857
Directory /workspace/5.usbdev_enable/latest


Test location /workspace/coverage/default/5.usbdev_fifo_rst.859003791
Short name T1136
Test name
Test status
Simulation time 168235455 ps
CPU time 2.12 seconds
Started Apr 21 03:58:00 PM PDT 24
Finished Apr 21 03:58:02 PM PDT 24
Peak memory 204176 kb
Host smart-e10a6585-f5bd-442f-8991-4f4d330b6099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85900
3791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.859003791
Directory /workspace/5.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/5.usbdev_in_iso.4250237902
Short name T561
Test name
Test status
Simulation time 8431697685 ps
CPU time 8.12 seconds
Started Apr 21 03:58:14 PM PDT 24
Finished Apr 21 03:58:22 PM PDT 24
Peak memory 204028 kb
Host smart-24780b3c-9d94-4646-9a34-fb9fceefe208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42502
37902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.4250237902
Directory /workspace/5.usbdev_in_iso/latest


Test location /workspace/coverage/default/5.usbdev_in_stall.2824517512
Short name T1031
Test name
Test status
Simulation time 8373334061 ps
CPU time 7.64 seconds
Started Apr 21 03:58:14 PM PDT 24
Finished Apr 21 03:58:22 PM PDT 24
Peak memory 204072 kb
Host smart-44ea2b26-a75c-489d-86c8-f3c1d3a86231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28245
17512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.2824517512
Directory /workspace/5.usbdev_in_stall/latest


Test location /workspace/coverage/default/5.usbdev_in_trans.2093347617
Short name T1192
Test name
Test status
Simulation time 8411480771 ps
CPU time 8.17 seconds
Started Apr 21 03:58:01 PM PDT 24
Finished Apr 21 03:58:10 PM PDT 24
Peak memory 204064 kb
Host smart-7a56579c-ece7-4097-bbb9-c1673b2f3f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20933
47617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.2093347617
Directory /workspace/5.usbdev_in_trans/latest


Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.1503101339
Short name T285
Test name
Test status
Simulation time 8423602440 ps
CPU time 8.26 seconds
Started Apr 21 03:58:01 PM PDT 24
Finished Apr 21 03:58:10 PM PDT 24
Peak memory 204064 kb
Host smart-98f8d6de-ca4a-43bf-937c-e667c8a8280e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15031
01339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.1503101339
Directory /workspace/5.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.2988995478
Short name T707
Test name
Test status
Simulation time 8401783424 ps
CPU time 10.14 seconds
Started Apr 21 03:58:00 PM PDT 24
Finished Apr 21 03:58:11 PM PDT 24
Peak memory 204068 kb
Host smart-a008f405-4793-4fa8-b7b0-fd0c64842747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29889
95478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.2988995478
Directory /workspace/5.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/5.usbdev_nak_trans.1772231355
Short name T120
Test name
Test status
Simulation time 8452410230 ps
CPU time 8.01 seconds
Started Apr 21 03:58:03 PM PDT 24
Finished Apr 21 03:58:12 PM PDT 24
Peak memory 204084 kb
Host smart-2ef574db-7515-4370-843b-344a57f3d11f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17722
31355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1772231355
Directory /workspace/5.usbdev_nak_trans/latest


Test location /workspace/coverage/default/5.usbdev_out_stall.2339629558
Short name T30
Test name
Test status
Simulation time 8387122598 ps
CPU time 8.17 seconds
Started Apr 21 03:58:04 PM PDT 24
Finished Apr 21 03:58:12 PM PDT 24
Peak memory 204068 kb
Host smart-ad851673-2b07-48af-9c17-6da49cd79834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23396
29558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.2339629558
Directory /workspace/5.usbdev_out_stall/latest


Test location /workspace/coverage/default/5.usbdev_out_trans_nak.1336546272
Short name T1073
Test name
Test status
Simulation time 8389460401 ps
CPU time 8.42 seconds
Started Apr 21 03:58:03 PM PDT 24
Finished Apr 21 03:58:12 PM PDT 24
Peak memory 203968 kb
Host smart-50fb2d6a-4ee0-475c-81cb-1a689b02525e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13365
46272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.1336546272
Directory /workspace/5.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/5.usbdev_pending_in_trans.4159368209
Short name T1299
Test name
Test status
Simulation time 8381066534 ps
CPU time 8.5 seconds
Started Apr 21 03:58:12 PM PDT 24
Finished Apr 21 03:58:21 PM PDT 24
Peak memory 204036 kb
Host smart-034d3cfa-afd6-45d5-bcbe-f7c27d806b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41593
68209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.4159368209
Directory /workspace/5.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.2598791954
Short name T1122
Test name
Test status
Simulation time 8376362891 ps
CPU time 9.05 seconds
Started Apr 21 03:58:11 PM PDT 24
Finished Apr 21 03:58:20 PM PDT 24
Peak memory 204060 kb
Host smart-e1b78861-ef7e-4fa1-8769-a55dbfb7a0d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25987
91954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.2598791954
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.634714627
Short name T1173
Test name
Test status
Simulation time 45891168 ps
CPU time 0.7 seconds
Started Apr 21 03:58:15 PM PDT 24
Finished Apr 21 03:58:16 PM PDT 24
Peak memory 203932 kb
Host smart-b2d0b14f-0b53-4373-9a06-3d204d92a02f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63471
4627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.634714627
Directory /workspace/5.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/5.usbdev_pkt_received.3949879381
Short name T817
Test name
Test status
Simulation time 8423166708 ps
CPU time 7.59 seconds
Started Apr 21 03:58:06 PM PDT 24
Finished Apr 21 03:58:14 PM PDT 24
Peak memory 204064 kb
Host smart-13fddcfc-7dd5-4920-93c4-df630d9f2374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39498
79381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.3949879381
Directory /workspace/5.usbdev_pkt_received/latest


Test location /workspace/coverage/default/5.usbdev_pkt_sent.886863033
Short name T637
Test name
Test status
Simulation time 8382436025 ps
CPU time 8.03 seconds
Started Apr 21 03:58:06 PM PDT 24
Finished Apr 21 03:58:14 PM PDT 24
Peak memory 204072 kb
Host smart-21da6cdf-8dd2-4c6e-bead-a0a492520711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88686
3033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.886863033
Directory /workspace/5.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.3390812510
Short name T981
Test name
Test status
Simulation time 8407291978 ps
CPU time 7.81 seconds
Started Apr 21 03:58:09 PM PDT 24
Finished Apr 21 03:58:17 PM PDT 24
Peak memory 204036 kb
Host smart-7a681fd0-3438-4f63-9af4-5160ec121522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33908
12510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.3390812510
Directory /workspace/5.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/5.usbdev_setup_stage.3818407529
Short name T1078
Test name
Test status
Simulation time 8376487056 ps
CPU time 7.79 seconds
Started Apr 21 03:58:10 PM PDT 24
Finished Apr 21 03:58:18 PM PDT 24
Peak memory 204064 kb
Host smart-b368e452-9875-4c9c-968e-dcfbedc28464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38184
07529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.3818407529
Directory /workspace/5.usbdev_setup_stage/latest


Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3193291960
Short name T380
Test name
Test status
Simulation time 8374017750 ps
CPU time 8.81 seconds
Started Apr 21 03:58:11 PM PDT 24
Finished Apr 21 03:58:20 PM PDT 24
Peak memory 204056 kb
Host smart-4084a2b5-a11b-455f-a351-1fe8a4f82b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31932
91960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3193291960
Directory /workspace/5.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/5.usbdev_smoke.179357900
Short name T178
Test name
Test status
Simulation time 8450318926 ps
CPU time 10.6 seconds
Started Apr 21 03:58:02 PM PDT 24
Finished Apr 21 03:58:13 PM PDT 24
Peak memory 204088 kb
Host smart-3b47c43f-7aee-432a-97a1-498b15df17f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17935
7900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.179357900
Directory /workspace/5.usbdev_smoke/latest


Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.4167383111
Short name T369
Test name
Test status
Simulation time 8382996196 ps
CPU time 7.76 seconds
Started Apr 21 03:58:09 PM PDT 24
Finished Apr 21 03:58:17 PM PDT 24
Peak memory 203984 kb
Host smart-2fce67a5-93c7-4d2d-91ba-07c9f063b666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41673
83111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.4167383111
Directory /workspace/5.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/5.usbdev_stall_trans.4279834113
Short name T883
Test name
Test status
Simulation time 8393164355 ps
CPU time 8.04 seconds
Started Apr 21 03:58:10 PM PDT 24
Finished Apr 21 03:58:18 PM PDT 24
Peak memory 204016 kb
Host smart-f21db35c-c58c-47c3-a38b-347cc1c3d5f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42798
34113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.4279834113
Directory /workspace/5.usbdev_stall_trans/latest


Test location /workspace/coverage/default/6.max_length_in_transaction.2599907360
Short name T1378
Test name
Test status
Simulation time 8467939437 ps
CPU time 8.04 seconds
Started Apr 21 03:58:29 PM PDT 24
Finished Apr 21 03:58:37 PM PDT 24
Peak memory 204036 kb
Host smart-883ad59d-2fae-4a2b-a6d9-609e24fde09a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2599907360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.2599907360
Directory /workspace/6.max_length_in_transaction/latest


Test location /workspace/coverage/default/6.min_length_in_transaction.3199491183
Short name T1017
Test name
Test status
Simulation time 8376330361 ps
CPU time 8.05 seconds
Started Apr 21 03:58:29 PM PDT 24
Finished Apr 21 03:58:37 PM PDT 24
Peak memory 204036 kb
Host smart-56e405c0-9f74-4227-9ce0-254216b78cee
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3199491183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.3199491183
Directory /workspace/6.min_length_in_transaction/latest


Test location /workspace/coverage/default/6.random_length_in_trans.477391160
Short name T345
Test name
Test status
Simulation time 8407580568 ps
CPU time 9.49 seconds
Started Apr 21 03:58:28 PM PDT 24
Finished Apr 21 03:58:38 PM PDT 24
Peak memory 204056 kb
Host smart-27ea3dec-ab9f-4e89-af36-51fcf756d9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47739
1160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.477391160
Directory /workspace/6.random_length_in_trans/latest


Test location /workspace/coverage/default/6.usbdev_av_buffer.1194240301
Short name T810
Test name
Test status
Simulation time 8420747693 ps
CPU time 8.01 seconds
Started Apr 21 03:58:21 PM PDT 24
Finished Apr 21 03:58:29 PM PDT 24
Peak memory 204012 kb
Host smart-b8f6f674-1d83-4ea0-968e-53db5b0c5cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11942
40301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.1194240301
Directory /workspace/6.usbdev_av_buffer/latest


Test location /workspace/coverage/default/6.usbdev_enable.2146204073
Short name T1045
Test name
Test status
Simulation time 8370926821 ps
CPU time 9 seconds
Started Apr 21 03:58:19 PM PDT 24
Finished Apr 21 03:58:28 PM PDT 24
Peak memory 203944 kb
Host smart-fbb2077f-762a-4eec-b7e6-6b97ec715da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21462
04073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.2146204073
Directory /workspace/6.usbdev_enable/latest


Test location /workspace/coverage/default/6.usbdev_fifo_rst.2718451072
Short name T1303
Test name
Test status
Simulation time 159098798 ps
CPU time 1.48 seconds
Started Apr 21 03:58:22 PM PDT 24
Finished Apr 21 03:58:23 PM PDT 24
Peak memory 204196 kb
Host smart-f9105b4c-a578-4066-866d-dc9652425e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27184
51072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2718451072
Directory /workspace/6.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/6.usbdev_in_iso.3707913813
Short name T156
Test name
Test status
Simulation time 8437896203 ps
CPU time 8.05 seconds
Started Apr 21 03:58:28 PM PDT 24
Finished Apr 21 03:58:36 PM PDT 24
Peak memory 204056 kb
Host smart-98425b9c-1700-4e6f-a667-e7d32e90b3c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37079
13813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.3707913813
Directory /workspace/6.usbdev_in_iso/latest


Test location /workspace/coverage/default/6.usbdev_in_stall.1990703266
Short name T1212
Test name
Test status
Simulation time 8380351955 ps
CPU time 7.96 seconds
Started Apr 21 03:58:30 PM PDT 24
Finished Apr 21 03:58:38 PM PDT 24
Peak memory 203972 kb
Host smart-9a41630d-2a57-4067-825e-e6e662e67e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19907
03266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.1990703266
Directory /workspace/6.usbdev_in_stall/latest


Test location /workspace/coverage/default/6.usbdev_in_trans.1504821701
Short name T762
Test name
Test status
Simulation time 8407159726 ps
CPU time 8.24 seconds
Started Apr 21 03:58:23 PM PDT 24
Finished Apr 21 03:58:32 PM PDT 24
Peak memory 204008 kb
Host smart-54a81f5c-bcd2-441b-8d6f-04d29b92f2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15048
21701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.1504821701
Directory /workspace/6.usbdev_in_trans/latest


Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1590014427
Short name T858
Test name
Test status
Simulation time 8416586071 ps
CPU time 8.04 seconds
Started Apr 21 03:58:21 PM PDT 24
Finished Apr 21 03:58:29 PM PDT 24
Peak memory 204044 kb
Host smart-10a5cb2e-4406-4326-a131-300f98cf1ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15900
14427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1590014427
Directory /workspace/6.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.1586240278
Short name T900
Test name
Test status
Simulation time 8380902893 ps
CPU time 8.34 seconds
Started Apr 21 03:58:23 PM PDT 24
Finished Apr 21 03:58:32 PM PDT 24
Peak memory 204084 kb
Host smart-7e87ef96-b1bf-4fc3-9ad8-c43e93a59255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15862
40278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.1586240278
Directory /workspace/6.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/6.usbdev_nak_trans.270600895
Short name T116
Test name
Test status
Simulation time 8394939633 ps
CPU time 9.55 seconds
Started Apr 21 03:58:24 PM PDT 24
Finished Apr 21 03:58:34 PM PDT 24
Peak memory 204224 kb
Host smart-5ca5f11e-3b8a-459c-8d89-600a66441e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27060
0895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.270600895
Directory /workspace/6.usbdev_nak_trans/latest


Test location /workspace/coverage/default/6.usbdev_out_stall.46317288
Short name T1164
Test name
Test status
Simulation time 8410451531 ps
CPU time 8.91 seconds
Started Apr 21 03:58:24 PM PDT 24
Finished Apr 21 03:58:33 PM PDT 24
Peak memory 204044 kb
Host smart-bd8b2d89-9d52-4c7c-a766-bcef075bc3f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46317
288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.46317288
Directory /workspace/6.usbdev_out_stall/latest


Test location /workspace/coverage/default/6.usbdev_out_trans_nak.3577373733
Short name T495
Test name
Test status
Simulation time 8411564946 ps
CPU time 7.54 seconds
Started Apr 21 03:58:23 PM PDT 24
Finished Apr 21 03:58:31 PM PDT 24
Peak memory 204080 kb
Host smart-f02dcba6-f8dd-430d-a494-9f55c1343b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35773
73733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.3577373733
Directory /workspace/6.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/6.usbdev_pending_in_trans.3518310517
Short name T1142
Test name
Test status
Simulation time 8408693910 ps
CPU time 8.71 seconds
Started Apr 21 03:58:29 PM PDT 24
Finished Apr 21 03:58:38 PM PDT 24
Peak memory 204060 kb
Host smart-c7e8d009-285a-454d-a425-1931acb9cc88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35183
10517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.3518310517
Directory /workspace/6.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.4227410553
Short name T1286
Test name
Test status
Simulation time 8403839573 ps
CPU time 7.81 seconds
Started Apr 21 03:58:26 PM PDT 24
Finished Apr 21 03:58:34 PM PDT 24
Peak memory 204060 kb
Host smart-0ad8bda6-fd8c-4634-a6ce-5ee8095c46f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42274
10553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.4227410553
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.2679008852
Short name T1002
Test name
Test status
Simulation time 35146544 ps
CPU time 0.63 seconds
Started Apr 21 03:58:28 PM PDT 24
Finished Apr 21 03:58:29 PM PDT 24
Peak memory 203912 kb
Host smart-522e88e6-9e09-4674-a244-3ffd2e018f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26790
08852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.2679008852
Directory /workspace/6.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/6.usbdev_pkt_buffer.3379613761
Short name T78
Test name
Test status
Simulation time 23225651483 ps
CPU time 47.31 seconds
Started Apr 21 03:58:24 PM PDT 24
Finished Apr 21 03:59:12 PM PDT 24
Peak memory 204304 kb
Host smart-298894c4-a423-4479-94ae-16db7363cac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33796
13761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.3379613761
Directory /workspace/6.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/6.usbdev_pkt_received.442592771
Short name T1270
Test name
Test status
Simulation time 8385067569 ps
CPU time 7.61 seconds
Started Apr 21 03:58:24 PM PDT 24
Finished Apr 21 03:58:32 PM PDT 24
Peak memory 204076 kb
Host smart-470e33ff-c7f6-4c51-865e-0aa6e6678e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44259
2771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.442592771
Directory /workspace/6.usbdev_pkt_received/latest


Test location /workspace/coverage/default/6.usbdev_pkt_sent.1142139441
Short name T1195
Test name
Test status
Simulation time 8409473412 ps
CPU time 7.71 seconds
Started Apr 21 03:58:24 PM PDT 24
Finished Apr 21 03:58:32 PM PDT 24
Peak memory 204028 kb
Host smart-0d7d1e59-7a5f-4954-8db1-f0e4c58fae9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11421
39441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1142139441
Directory /workspace/6.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.1325910017
Short name T1257
Test name
Test status
Simulation time 8400136783 ps
CPU time 8.16 seconds
Started Apr 21 03:58:26 PM PDT 24
Finished Apr 21 03:58:34 PM PDT 24
Peak memory 204036 kb
Host smart-8a9f1891-67af-418b-b587-847170cac645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13259
10017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.1325910017
Directory /workspace/6.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/6.usbdev_setup_stage.2405003572
Short name T837
Test name
Test status
Simulation time 8374246463 ps
CPU time 7.85 seconds
Started Apr 21 03:58:27 PM PDT 24
Finished Apr 21 03:58:35 PM PDT 24
Peak memory 204048 kb
Host smart-a27b6def-247b-4101-b285-c6733e2790c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24050
03572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.2405003572
Directory /workspace/6.usbdev_setup_stage/latest


Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.2791257863
Short name T813
Test name
Test status
Simulation time 8399125010 ps
CPU time 7.62 seconds
Started Apr 21 03:58:26 PM PDT 24
Finished Apr 21 03:58:34 PM PDT 24
Peak memory 204236 kb
Host smart-80fa4127-d0c0-4f9f-9589-e3f40a0a9eda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27912
57863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.2791257863
Directory /workspace/6.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/6.usbdev_smoke.3449538008
Short name T1199
Test name
Test status
Simulation time 8461435106 ps
CPU time 8.06 seconds
Started Apr 21 03:58:18 PM PDT 24
Finished Apr 21 03:58:27 PM PDT 24
Peak memory 204088 kb
Host smart-2b864c55-99ee-41f1-94f1-92d19007cb8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34495
38008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3449538008
Directory /workspace/6.usbdev_smoke/latest


Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.958413461
Short name T1036
Test name
Test status
Simulation time 8414703303 ps
CPU time 8.43 seconds
Started Apr 21 03:58:27 PM PDT 24
Finished Apr 21 03:58:36 PM PDT 24
Peak memory 204036 kb
Host smart-aa0b5080-53ab-4304-81fe-de2cf2d87c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95841
3461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.958413461
Directory /workspace/6.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/6.usbdev_stall_trans.617988591
Short name T946
Test name
Test status
Simulation time 8399415906 ps
CPU time 7.64 seconds
Started Apr 21 03:58:26 PM PDT 24
Finished Apr 21 03:58:34 PM PDT 24
Peak memory 204052 kb
Host smart-8417f77e-6acd-4587-aa84-4522b4457a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61798
8591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.617988591
Directory /workspace/6.usbdev_stall_trans/latest


Test location /workspace/coverage/default/7.max_length_in_transaction.3683068867
Short name T834
Test name
Test status
Simulation time 8471306113 ps
CPU time 9.2 seconds
Started Apr 21 03:58:41 PM PDT 24
Finished Apr 21 03:58:51 PM PDT 24
Peak memory 204068 kb
Host smart-c5986b7b-8fc2-4436-a88f-240f5cfbc82a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3683068867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.3683068867
Directory /workspace/7.max_length_in_transaction/latest


Test location /workspace/coverage/default/7.min_length_in_transaction.90655256
Short name T1196
Test name
Test status
Simulation time 8378236351 ps
CPU time 10.55 seconds
Started Apr 21 03:58:43 PM PDT 24
Finished Apr 21 03:58:54 PM PDT 24
Peak memory 204088 kb
Host smart-42f53a77-303c-46e4-99d5-4afc6b36d8a7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=90655256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.90655256
Directory /workspace/7.min_length_in_transaction/latest


Test location /workspace/coverage/default/7.random_length_in_trans.1137417510
Short name T854
Test name
Test status
Simulation time 8392414487 ps
CPU time 7.75 seconds
Started Apr 21 03:58:43 PM PDT 24
Finished Apr 21 03:58:51 PM PDT 24
Peak memory 204080 kb
Host smart-9deab045-5f5b-46d7-85a8-2bcf6564ccb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11374
17510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.1137417510
Directory /workspace/7.random_length_in_trans/latest


Test location /workspace/coverage/default/7.usbdev_av_buffer.2223302455
Short name T806
Test name
Test status
Simulation time 8377183893 ps
CPU time 9.49 seconds
Started Apr 21 03:58:34 PM PDT 24
Finished Apr 21 03:58:44 PM PDT 24
Peak memory 204036 kb
Host smart-136ab18d-36a7-425e-8031-e762095acef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22233
02455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2223302455
Directory /workspace/7.usbdev_av_buffer/latest


Test location /workspace/coverage/default/7.usbdev_enable.941210716
Short name T794
Test name
Test status
Simulation time 8375456800 ps
CPU time 8.17 seconds
Started Apr 21 03:58:34 PM PDT 24
Finished Apr 21 03:58:43 PM PDT 24
Peak memory 204068 kb
Host smart-6f889cfe-70ea-44db-a3a2-419e35b34b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94121
0716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.941210716
Directory /workspace/7.usbdev_enable/latest


Test location /workspace/coverage/default/7.usbdev_fifo_rst.2914735714
Short name T551
Test name
Test status
Simulation time 211143497 ps
CPU time 1.67 seconds
Started Apr 21 03:58:31 PM PDT 24
Finished Apr 21 03:58:33 PM PDT 24
Peak memory 204184 kb
Host smart-94d145e4-67bb-49f9-b94f-f423dce768d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29147
35714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2914735714
Directory /workspace/7.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/7.usbdev_in_iso.151200109
Short name T52
Test name
Test status
Simulation time 8418351563 ps
CPU time 7.82 seconds
Started Apr 21 03:58:37 PM PDT 24
Finished Apr 21 03:58:45 PM PDT 24
Peak memory 204084 kb
Host smart-ee10daa4-9ebb-4e11-87df-192fc3cab77b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15120
0109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.151200109
Directory /workspace/7.usbdev_in_iso/latest


Test location /workspace/coverage/default/7.usbdev_in_stall.3927545195
Short name T864
Test name
Test status
Simulation time 8392785769 ps
CPU time 7.73 seconds
Started Apr 21 03:58:39 PM PDT 24
Finished Apr 21 03:58:47 PM PDT 24
Peak memory 204044 kb
Host smart-3ccd779e-d303-41b2-ae41-92f9e91b8bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39275
45195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3927545195
Directory /workspace/7.usbdev_in_stall/latest


Test location /workspace/coverage/default/7.usbdev_in_trans.2840086009
Short name T1135
Test name
Test status
Simulation time 8395843641 ps
CPU time 8.59 seconds
Started Apr 21 03:58:32 PM PDT 24
Finished Apr 21 03:58:41 PM PDT 24
Peak memory 204064 kb
Host smart-e42a856a-fe59-4550-811c-048ac928e155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28400
86009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2840086009
Directory /workspace/7.usbdev_in_trans/latest


Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.4051186745
Short name T863
Test name
Test status
Simulation time 8425937853 ps
CPU time 8.31 seconds
Started Apr 21 03:58:33 PM PDT 24
Finished Apr 21 03:58:41 PM PDT 24
Peak memory 204224 kb
Host smart-4f51fdae-adbf-4f02-9675-b4a58fb25bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40511
86745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.4051186745
Directory /workspace/7.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2479979366
Short name T814
Test name
Test status
Simulation time 8376625553 ps
CPU time 7.99 seconds
Started Apr 21 03:58:31 PM PDT 24
Finished Apr 21 03:58:40 PM PDT 24
Peak memory 204024 kb
Host smart-e398c944-a6bd-4a9e-928c-2cdba9ecaf8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24799
79366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2479979366
Directory /workspace/7.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/7.usbdev_nak_trans.1573717341
Short name T1255
Test name
Test status
Simulation time 8465124274 ps
CPU time 7.84 seconds
Started Apr 21 03:58:32 PM PDT 24
Finished Apr 21 03:58:40 PM PDT 24
Peak memory 204052 kb
Host smart-2c57999e-9964-44c2-a15d-c01f577b6a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15737
17341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.1573717341
Directory /workspace/7.usbdev_nak_trans/latest


Test location /workspace/coverage/default/7.usbdev_out_stall.2691305564
Short name T1104
Test name
Test status
Simulation time 8381569168 ps
CPU time 7.83 seconds
Started Apr 21 03:58:31 PM PDT 24
Finished Apr 21 03:58:39 PM PDT 24
Peak memory 204052 kb
Host smart-59c4cc62-e5c1-4449-a66f-4053bf1d1059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26913
05564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2691305564
Directory /workspace/7.usbdev_out_stall/latest


Test location /workspace/coverage/default/7.usbdev_out_trans_nak.446147087
Short name T565
Test name
Test status
Simulation time 8419144921 ps
CPU time 7.81 seconds
Started Apr 21 03:58:32 PM PDT 24
Finished Apr 21 03:58:40 PM PDT 24
Peak memory 204048 kb
Host smart-c1385f03-73ec-4067-ba1d-065580a505c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44614
7087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.446147087
Directory /workspace/7.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/7.usbdev_pending_in_trans.3663196067
Short name T23
Test name
Test status
Simulation time 8401080363 ps
CPU time 8.24 seconds
Started Apr 21 03:58:39 PM PDT 24
Finished Apr 21 03:58:48 PM PDT 24
Peak memory 204060 kb
Host smart-1d2b613f-3871-43b3-b818-a9252c6f1300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36631
96067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.3663196067
Directory /workspace/7.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.1330535437
Short name T918
Test name
Test status
Simulation time 8369924962 ps
CPU time 10.69 seconds
Started Apr 21 03:58:41 PM PDT 24
Finished Apr 21 03:58:52 PM PDT 24
Peak memory 204028 kb
Host smart-c1d9dfc4-161d-46a6-bfd2-ef71619830bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13305
35437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.1330535437
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.4164770120
Short name T1096
Test name
Test status
Simulation time 130166701 ps
CPU time 0.78 seconds
Started Apr 21 03:58:40 PM PDT 24
Finished Apr 21 03:58:41 PM PDT 24
Peak memory 203916 kb
Host smart-e5afbb4f-ca14-4e27-8d69-cd66da8d6b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41647
70120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.4164770120
Directory /workspace/7.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/7.usbdev_pkt_buffer.2328674193
Short name T228
Test name
Test status
Simulation time 15936627138 ps
CPU time 32.59 seconds
Started Apr 21 03:58:34 PM PDT 24
Finished Apr 21 03:59:06 PM PDT 24
Peak memory 204352 kb
Host smart-9b71dc4c-7951-4bc1-b68d-de6e9008beba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23286
74193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.2328674193
Directory /workspace/7.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/7.usbdev_pkt_received.1001554785
Short name T940
Test name
Test status
Simulation time 8408850232 ps
CPU time 8 seconds
Started Apr 21 03:58:33 PM PDT 24
Finished Apr 21 03:58:41 PM PDT 24
Peak memory 204060 kb
Host smart-2b2377af-ec2f-455e-99fe-c5d0ad5f828a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10015
54785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1001554785
Directory /workspace/7.usbdev_pkt_received/latest


Test location /workspace/coverage/default/7.usbdev_pkt_sent.636462071
Short name T389
Test name
Test status
Simulation time 8387541783 ps
CPU time 8.21 seconds
Started Apr 21 03:58:35 PM PDT 24
Finished Apr 21 03:58:44 PM PDT 24
Peak memory 204064 kb
Host smart-e826cfa5-6d4a-400d-9338-cf2ea6661a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63646
2071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.636462071
Directory /workspace/7.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.57033783
Short name T332
Test name
Test status
Simulation time 8382555193 ps
CPU time 7.85 seconds
Started Apr 21 03:58:38 PM PDT 24
Finished Apr 21 03:58:46 PM PDT 24
Peak memory 204064 kb
Host smart-cdefa4fd-facb-4ec5-8503-ea4f7cfd121f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57033
783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.57033783
Directory /workspace/7.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/7.usbdev_setup_stage.2860545249
Short name T180
Test name
Test status
Simulation time 8383577228 ps
CPU time 7.62 seconds
Started Apr 21 03:58:37 PM PDT 24
Finished Apr 21 03:58:44 PM PDT 24
Peak memory 203952 kb
Host smart-f225da51-1911-4268-ab5f-6be0cc83ec19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28605
45249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.2860545249
Directory /workspace/7.usbdev_setup_stage/latest


Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.133563210
Short name T1204
Test name
Test status
Simulation time 8367506262 ps
CPU time 7.65 seconds
Started Apr 21 03:58:37 PM PDT 24
Finished Apr 21 03:58:45 PM PDT 24
Peak memory 204060 kb
Host smart-82062e2c-1e77-4faf-b43e-20656f55f313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13356
3210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.133563210
Directory /workspace/7.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/7.usbdev_smoke.2865111014
Short name T159
Test name
Test status
Simulation time 8407434485 ps
CPU time 8.06 seconds
Started Apr 21 03:58:31 PM PDT 24
Finished Apr 21 03:58:40 PM PDT 24
Peak memory 204036 kb
Host smart-d919269d-9c68-4601-b265-d6b3975e9a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28651
11014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2865111014
Directory /workspace/7.usbdev_smoke/latest


Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.3289667805
Short name T783
Test name
Test status
Simulation time 8391586517 ps
CPU time 9.36 seconds
Started Apr 21 03:58:37 PM PDT 24
Finished Apr 21 03:58:47 PM PDT 24
Peak memory 204044 kb
Host smart-45006cb0-0d77-4f66-83a8-6cbff67d049f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32896
67805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.3289667805
Directory /workspace/7.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/7.usbdev_stall_trans.4253226774
Short name T1101
Test name
Test status
Simulation time 8397654279 ps
CPU time 9.66 seconds
Started Apr 21 03:58:37 PM PDT 24
Finished Apr 21 03:58:46 PM PDT 24
Peak memory 203940 kb
Host smart-11526a60-4260-4c09-b394-c56052b8ac97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42532
26774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.4253226774
Directory /workspace/7.usbdev_stall_trans/latest


Test location /workspace/coverage/default/8.max_length_in_transaction.2824417058
Short name T872
Test name
Test status
Simulation time 8470572269 ps
CPU time 10.28 seconds
Started Apr 21 03:58:53 PM PDT 24
Finished Apr 21 03:59:03 PM PDT 24
Peak memory 204044 kb
Host smart-e3e0b398-a31c-4269-8480-ce5192c8d2b0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2824417058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.2824417058
Directory /workspace/8.max_length_in_transaction/latest


Test location /workspace/coverage/default/8.min_length_in_transaction.2480673870
Short name T1186
Test name
Test status
Simulation time 8375763190 ps
CPU time 8.15 seconds
Started Apr 21 03:58:53 PM PDT 24
Finished Apr 21 03:59:01 PM PDT 24
Peak memory 204040 kb
Host smart-fb3f3a75-6b63-4e11-8bb4-290baf96061b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2480673870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.2480673870
Directory /workspace/8.min_length_in_transaction/latest


Test location /workspace/coverage/default/8.random_length_in_trans.2429587179
Short name T506
Test name
Test status
Simulation time 8444761635 ps
CPU time 8.23 seconds
Started Apr 21 03:58:56 PM PDT 24
Finished Apr 21 03:59:05 PM PDT 24
Peak memory 204028 kb
Host smart-a5615bfb-9f84-4d17-9d92-e3dfb40fc8a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24295
87179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.2429587179
Directory /workspace/8.random_length_in_trans/latest


Test location /workspace/coverage/default/8.usbdev_av_buffer.371029946
Short name T1167
Test name
Test status
Simulation time 8372071166 ps
CPU time 8.77 seconds
Started Apr 21 03:58:45 PM PDT 24
Finished Apr 21 03:58:54 PM PDT 24
Peak memory 203996 kb
Host smart-ae21a5c6-617a-4923-a926-5bb13cee3ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37102
9946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.371029946
Directory /workspace/8.usbdev_av_buffer/latest


Test location /workspace/coverage/default/8.usbdev_enable.3742657839
Short name T943
Test name
Test status
Simulation time 8385873245 ps
CPU time 9.01 seconds
Started Apr 21 03:58:46 PM PDT 24
Finished Apr 21 03:58:55 PM PDT 24
Peak memory 204052 kb
Host smart-15331747-1487-43b7-b82f-2e8a39e1c79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37426
57839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3742657839
Directory /workspace/8.usbdev_enable/latest


Test location /workspace/coverage/default/8.usbdev_fifo_rst.137341046
Short name T497
Test name
Test status
Simulation time 46986747 ps
CPU time 1.11 seconds
Started Apr 21 03:58:45 PM PDT 24
Finished Apr 21 03:58:46 PM PDT 24
Peak memory 204132 kb
Host smart-721386b4-25f4-4ee6-8468-4eaa5edbe366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13734
1046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.137341046
Directory /workspace/8.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/8.usbdev_in_iso.3876387051
Short name T505
Test name
Test status
Simulation time 8441771942 ps
CPU time 9.63 seconds
Started Apr 21 03:58:54 PM PDT 24
Finished Apr 21 03:59:03 PM PDT 24
Peak memory 204000 kb
Host smart-b68bf6f9-7dea-43ad-a2bb-a3f360225207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38763
87051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.3876387051
Directory /workspace/8.usbdev_in_iso/latest


Test location /workspace/coverage/default/8.usbdev_in_stall.3236065877
Short name T630
Test name
Test status
Simulation time 8374005057 ps
CPU time 7.75 seconds
Started Apr 21 03:58:55 PM PDT 24
Finished Apr 21 03:59:03 PM PDT 24
Peak memory 204032 kb
Host smart-ccb67bbd-63ad-45f4-9bd7-e35a2211c3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32360
65877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.3236065877
Directory /workspace/8.usbdev_in_stall/latest


Test location /workspace/coverage/default/8.usbdev_in_trans.520872120
Short name T1022
Test name
Test status
Simulation time 8391360953 ps
CPU time 8.47 seconds
Started Apr 21 03:58:47 PM PDT 24
Finished Apr 21 03:58:56 PM PDT 24
Peak memory 203968 kb
Host smart-1d46968f-f29d-4188-9522-b25bd626cde8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52087
2120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.520872120
Directory /workspace/8.usbdev_in_trans/latest


Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.288784581
Short name T632
Test name
Test status
Simulation time 8410530277 ps
CPU time 8.41 seconds
Started Apr 21 03:58:48 PM PDT 24
Finished Apr 21 03:58:57 PM PDT 24
Peak memory 204040 kb
Host smart-15ded2bb-b42b-4da0-985e-581da731e248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28878
4581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.288784581
Directory /workspace/8.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.3060909717
Short name T675
Test name
Test status
Simulation time 8382900906 ps
CPU time 7.8 seconds
Started Apr 21 03:58:47 PM PDT 24
Finished Apr 21 03:58:56 PM PDT 24
Peak memory 204068 kb
Host smart-0aded67f-eb02-4cab-bce6-80c27aa8a3be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30609
09717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3060909717
Directory /workspace/8.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/8.usbdev_nak_trans.3854049683
Short name T127
Test name
Test status
Simulation time 8448736991 ps
CPU time 7.82 seconds
Started Apr 21 03:58:49 PM PDT 24
Finished Apr 21 03:58:57 PM PDT 24
Peak memory 204088 kb
Host smart-c2fc2119-adda-4602-a482-2449f66a5dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38540
49683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3854049683
Directory /workspace/8.usbdev_nak_trans/latest


Test location /workspace/coverage/default/8.usbdev_out_stall.592482805
Short name T841
Test name
Test status
Simulation time 8387482549 ps
CPU time 7.96 seconds
Started Apr 21 03:58:48 PM PDT 24
Finished Apr 21 03:58:56 PM PDT 24
Peak memory 204068 kb
Host smart-ecb14f48-078d-4ca6-a61d-fced29a08a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59248
2805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.592482805
Directory /workspace/8.usbdev_out_stall/latest


Test location /workspace/coverage/default/8.usbdev_out_trans_nak.338869545
Short name T423
Test name
Test status
Simulation time 8393208988 ps
CPU time 7.53 seconds
Started Apr 21 03:58:49 PM PDT 24
Finished Apr 21 03:58:56 PM PDT 24
Peak memory 204080 kb
Host smart-d7a68899-5cb9-49d3-80cf-639dc5bae13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33886
9545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.338869545
Directory /workspace/8.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/8.usbdev_pending_in_trans.3565917726
Short name T181
Test name
Test status
Simulation time 8400908931 ps
CPU time 8.64 seconds
Started Apr 21 03:58:53 PM PDT 24
Finished Apr 21 03:59:02 PM PDT 24
Peak memory 204040 kb
Host smart-78a448ec-c659-4a82-bfaa-a4ec75cabf4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35659
17726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.3565917726
Directory /workspace/8.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.3557095134
Short name T464
Test name
Test status
Simulation time 8375816734 ps
CPU time 10.62 seconds
Started Apr 21 03:58:51 PM PDT 24
Finished Apr 21 03:59:02 PM PDT 24
Peak memory 204060 kb
Host smart-b9993d56-8aa2-4471-99d4-35a35c5c90fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35570
95134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.3557095134
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2186584846
Short name T1293
Test name
Test status
Simulation time 37565974 ps
CPU time 0.66 seconds
Started Apr 21 03:58:53 PM PDT 24
Finished Apr 21 03:58:54 PM PDT 24
Peak memory 203932 kb
Host smart-e14b5266-3e63-43e1-af15-831e15760fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21865
84846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2186584846
Directory /workspace/8.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/8.usbdev_pkt_buffer.1212403110
Short name T1108
Test name
Test status
Simulation time 15142618880 ps
CPU time 31.01 seconds
Started Apr 21 03:58:48 PM PDT 24
Finished Apr 21 03:59:20 PM PDT 24
Peak memory 204360 kb
Host smart-f13b1196-77b1-4d4c-ad62-0664aae9fab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12124
03110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.1212403110
Directory /workspace/8.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/8.usbdev_pkt_received.3653585580
Short name T86
Test name
Test status
Simulation time 8402767376 ps
CPU time 7.86 seconds
Started Apr 21 03:58:55 PM PDT 24
Finished Apr 21 03:59:04 PM PDT 24
Peak memory 204032 kb
Host smart-5188e840-df3e-45e9-9b9d-2df0306ebbbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36535
85580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.3653585580
Directory /workspace/8.usbdev_pkt_received/latest


Test location /workspace/coverage/default/8.usbdev_pkt_sent.1076044166
Short name T1098
Test name
Test status
Simulation time 8383830639 ps
CPU time 7.46 seconds
Started Apr 21 03:58:50 PM PDT 24
Finished Apr 21 03:58:58 PM PDT 24
Peak memory 204072 kb
Host smart-8ebd3b05-9112-47a8-873d-8de09423b74a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10760
44166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1076044166
Directory /workspace/8.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.243483052
Short name T1346
Test name
Test status
Simulation time 8397383977 ps
CPU time 8.17 seconds
Started Apr 21 03:58:49 PM PDT 24
Finished Apr 21 03:58:58 PM PDT 24
Peak memory 204080 kb
Host smart-4252d457-d649-4172-bd48-6c15d5e76151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24348
3052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.243483052
Directory /workspace/8.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/8.usbdev_setup_stage.1862102846
Short name T164
Test name
Test status
Simulation time 8415046579 ps
CPU time 9.58 seconds
Started Apr 21 03:58:53 PM PDT 24
Finished Apr 21 03:59:03 PM PDT 24
Peak memory 204064 kb
Host smart-aa93a513-d71b-4b7c-9106-957e78e96e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18621
02846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.1862102846
Directory /workspace/8.usbdev_setup_stage/latest


Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.1362661806
Short name T24
Test name
Test status
Simulation time 8377463876 ps
CPU time 8.47 seconds
Started Apr 21 03:58:53 PM PDT 24
Finished Apr 21 03:59:01 PM PDT 24
Peak memory 204056 kb
Host smart-1a92236f-07be-4585-8235-e977b15c3c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13626
61806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.1362661806
Directory /workspace/8.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/8.usbdev_smoke.2920191860
Short name T427
Test name
Test status
Simulation time 8427449956 ps
CPU time 7.76 seconds
Started Apr 21 03:58:46 PM PDT 24
Finished Apr 21 03:58:54 PM PDT 24
Peak memory 204068 kb
Host smart-27228dd7-cc76-4881-93ce-be86ccfaa9f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29201
91860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.2920191860
Directory /workspace/8.usbdev_smoke/latest


Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.1217772673
Short name T312
Test name
Test status
Simulation time 8411383230 ps
CPU time 8.43 seconds
Started Apr 21 03:58:55 PM PDT 24
Finished Apr 21 03:59:04 PM PDT 24
Peak memory 204024 kb
Host smart-b8e8c097-77bd-4763-93b6-5f7da455e36e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12177
72673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.1217772673
Directory /workspace/8.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/8.usbdev_stall_trans.2946939686
Short name T290
Test name
Test status
Simulation time 8412500253 ps
CPU time 9.58 seconds
Started Apr 21 03:58:50 PM PDT 24
Finished Apr 21 03:59:00 PM PDT 24
Peak memory 204064 kb
Host smart-84f07397-405a-40d3-9453-9a5b33a873ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29469
39686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2946939686
Directory /workspace/8.usbdev_stall_trans/latest


Test location /workspace/coverage/default/9.max_length_in_transaction.2588856502
Short name T1262
Test name
Test status
Simulation time 8459251924 ps
CPU time 9.57 seconds
Started Apr 21 03:59:11 PM PDT 24
Finished Apr 21 03:59:21 PM PDT 24
Peak memory 204040 kb
Host smart-b6750efa-51f8-4970-a266-44f47627f310
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2588856502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.2588856502
Directory /workspace/9.max_length_in_transaction/latest


Test location /workspace/coverage/default/9.min_length_in_transaction.3197895597
Short name T892
Test name
Test status
Simulation time 8413704237 ps
CPU time 8.99 seconds
Started Apr 21 03:59:12 PM PDT 24
Finished Apr 21 03:59:21 PM PDT 24
Peak memory 204036 kb
Host smart-74259359-748f-4ef7-817f-4103951df13b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3197895597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.3197895597
Directory /workspace/9.min_length_in_transaction/latest


Test location /workspace/coverage/default/9.random_length_in_trans.3935803427
Short name T532
Test name
Test status
Simulation time 8418321056 ps
CPU time 7.62 seconds
Started Apr 21 03:59:11 PM PDT 24
Finished Apr 21 03:59:19 PM PDT 24
Peak memory 204044 kb
Host smart-17634e84-c0a1-41c7-96f7-c09fcc14a961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39358
03427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.3935803427
Directory /workspace/9.random_length_in_trans/latest


Test location /workspace/coverage/default/9.usbdev_av_buffer.2846696441
Short name T1064
Test name
Test status
Simulation time 8407796919 ps
CPU time 9.79 seconds
Started Apr 21 03:58:59 PM PDT 24
Finished Apr 21 03:59:09 PM PDT 24
Peak memory 204012 kb
Host smart-607b828b-b4de-475f-a400-2bbc4f64169f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28466
96441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2846696441
Directory /workspace/9.usbdev_av_buffer/latest


Test location /workspace/coverage/default/9.usbdev_enable.3273607440
Short name T857
Test name
Test status
Simulation time 8370640769 ps
CPU time 9.08 seconds
Started Apr 21 03:58:59 PM PDT 24
Finished Apr 21 03:59:08 PM PDT 24
Peak memory 204068 kb
Host smart-a41efe5f-88e0-4b0c-8527-e0200a9fd201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32736
07440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.3273607440
Directory /workspace/9.usbdev_enable/latest


Test location /workspace/coverage/default/9.usbdev_fifo_rst.208539217
Short name T1081
Test name
Test status
Simulation time 272916676 ps
CPU time 2.33 seconds
Started Apr 21 03:58:59 PM PDT 24
Finished Apr 21 03:59:01 PM PDT 24
Peak memory 204148 kb
Host smart-afcd0f30-70d2-4dd8-85df-8535bf5e6877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20853
9217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.208539217
Directory /workspace/9.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/9.usbdev_in_iso.1213494701
Short name T662
Test name
Test status
Simulation time 8403135413 ps
CPU time 7.9 seconds
Started Apr 21 03:59:11 PM PDT 24
Finished Apr 21 03:59:19 PM PDT 24
Peak memory 204048 kb
Host smart-b46cbe76-44bb-45fa-bffe-485f1e75faed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12134
94701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.1213494701
Directory /workspace/9.usbdev_in_iso/latest


Test location /workspace/coverage/default/9.usbdev_in_stall.3262186312
Short name T1105
Test name
Test status
Simulation time 8388558787 ps
CPU time 8.64 seconds
Started Apr 21 03:59:08 PM PDT 24
Finished Apr 21 03:59:17 PM PDT 24
Peak memory 204064 kb
Host smart-08724856-c4b2-4729-88f4-9d20a2b70bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32621
86312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.3262186312
Directory /workspace/9.usbdev_in_stall/latest


Test location /workspace/coverage/default/9.usbdev_in_trans.2167515292
Short name T1137
Test name
Test status
Simulation time 8454867940 ps
CPU time 7.82 seconds
Started Apr 21 03:58:57 PM PDT 24
Finished Apr 21 03:59:06 PM PDT 24
Peak memory 204028 kb
Host smart-3db1f4e8-8389-45df-ba11-46eed3552113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21675
15292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.2167515292
Directory /workspace/9.usbdev_in_trans/latest


Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.752561020
Short name T847
Test name
Test status
Simulation time 8428797006 ps
CPU time 8.22 seconds
Started Apr 21 03:58:58 PM PDT 24
Finished Apr 21 03:59:06 PM PDT 24
Peak memory 204064 kb
Host smart-0ee4872b-8c1a-4a4a-a517-18ba37ae18ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75256
1020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.752561020
Directory /workspace/9.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.640407256
Short name T832
Test name
Test status
Simulation time 8373718830 ps
CPU time 8.5 seconds
Started Apr 21 03:59:00 PM PDT 24
Finished Apr 21 03:59:08 PM PDT 24
Peak memory 204024 kb
Host smart-9acded96-ea0d-456b-810e-32519a7cde67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64040
7256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.640407256
Directory /workspace/9.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/9.usbdev_nak_trans.1408484504
Short name T133
Test name
Test status
Simulation time 8490699535 ps
CPU time 8.67 seconds
Started Apr 21 03:59:11 PM PDT 24
Finished Apr 21 03:59:20 PM PDT 24
Peak memory 204064 kb
Host smart-e09d4600-e2c8-4438-b1d6-774648a992fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14084
84504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1408484504
Directory /workspace/9.usbdev_nak_trans/latest


Test location /workspace/coverage/default/9.usbdev_out_stall.2426909159
Short name T1324
Test name
Test status
Simulation time 8416087761 ps
CPU time 7.99 seconds
Started Apr 21 03:59:03 PM PDT 24
Finished Apr 21 03:59:12 PM PDT 24
Peak memory 204068 kb
Host smart-45a7ea15-864a-48ee-81c7-040bc26b635f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24269
09159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2426909159
Directory /workspace/9.usbdev_out_stall/latest


Test location /workspace/coverage/default/9.usbdev_out_trans_nak.1505720593
Short name T294
Test name
Test status
Simulation time 8390673381 ps
CPU time 7.67 seconds
Started Apr 21 03:59:00 PM PDT 24
Finished Apr 21 03:59:08 PM PDT 24
Peak memory 204040 kb
Host smart-3786ea30-aca6-4b08-adde-37d8f7f084c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15057
20593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.1505720593
Directory /workspace/9.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/9.usbdev_pending_in_trans.2307208009
Short name T1201
Test name
Test status
Simulation time 8384788759 ps
CPU time 8.06 seconds
Started Apr 21 03:59:05 PM PDT 24
Finished Apr 21 03:59:13 PM PDT 24
Peak memory 204036 kb
Host smart-8f3d34a8-09cb-4d0b-90f9-0227de9bdbf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23072
08009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.2307208009
Directory /workspace/9.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.624940151
Short name T1202
Test name
Test status
Simulation time 45308332 ps
CPU time 0.67 seconds
Started Apr 21 03:59:04 PM PDT 24
Finished Apr 21 03:59:05 PM PDT 24
Peak memory 203864 kb
Host smart-b4b0bc47-16f2-482a-8c5f-a4587fd0b953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62494
0151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.624940151
Directory /workspace/9.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/9.usbdev_pkt_buffer.2616253982
Short name T933
Test name
Test status
Simulation time 25882757861 ps
CPU time 47.02 seconds
Started Apr 21 03:59:01 PM PDT 24
Finished Apr 21 03:59:48 PM PDT 24
Peak memory 204320 kb
Host smart-f02a64d3-ca4e-478f-9b4e-71a1fba378c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26162
53982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.2616253982
Directory /workspace/9.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/9.usbdev_pkt_received.2203367808
Short name T295
Test name
Test status
Simulation time 8422461920 ps
CPU time 8.1 seconds
Started Apr 21 03:59:04 PM PDT 24
Finished Apr 21 03:59:12 PM PDT 24
Peak memory 204064 kb
Host smart-6af8f567-2db6-448d-b122-26e4461548e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22033
67808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.2203367808
Directory /workspace/9.usbdev_pkt_received/latest


Test location /workspace/coverage/default/9.usbdev_pkt_sent.1915142183
Short name T731
Test name
Test status
Simulation time 8455551318 ps
CPU time 9.04 seconds
Started Apr 21 03:59:04 PM PDT 24
Finished Apr 21 03:59:13 PM PDT 24
Peak memory 204044 kb
Host smart-fca80080-bc64-4f6e-9020-d1061dd56981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19151
42183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1915142183
Directory /workspace/9.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.184039466
Short name T1046
Test name
Test status
Simulation time 8458651204 ps
CPU time 8.21 seconds
Started Apr 21 03:59:06 PM PDT 24
Finished Apr 21 03:59:15 PM PDT 24
Peak memory 204064 kb
Host smart-10ef99d0-cbec-4293-a668-1949cd57e0d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18403
9466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.184039466
Directory /workspace/9.usbdev_random_length_out_trans/latest


Test location /workspace/coverage/default/9.usbdev_setup_stage.75128103
Short name T639
Test name
Test status
Simulation time 8418191080 ps
CPU time 7.4 seconds
Started Apr 21 03:59:04 PM PDT 24
Finished Apr 21 03:59:12 PM PDT 24
Peak memory 204036 kb
Host smart-11c4352f-8ea0-4922-9b82-4fb26fd05385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75128
103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.75128103
Directory /workspace/9.usbdev_setup_stage/latest


Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2742322349
Short name T303
Test name
Test status
Simulation time 8378381560 ps
CPU time 7.58 seconds
Started Apr 21 03:59:05 PM PDT 24
Finished Apr 21 03:59:13 PM PDT 24
Peak memory 204032 kb
Host smart-37697939-ec7d-413a-aa72-dd7d1b5adb50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27423
22349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2742322349
Directory /workspace/9.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/9.usbdev_smoke.2868108455
Short name T760
Test name
Test status
Simulation time 8425264757 ps
CPU time 7.8 seconds
Started Apr 21 03:59:01 PM PDT 24
Finished Apr 21 03:59:09 PM PDT 24
Peak memory 204076 kb
Host smart-e744f56a-b079-4aed-8a7d-8aa57dc42b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28681
08455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2868108455
Directory /workspace/9.usbdev_smoke/latest


Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.1735232290
Short name T755
Test name
Test status
Simulation time 8401569600 ps
CPU time 8.84 seconds
Started Apr 21 03:59:05 PM PDT 24
Finished Apr 21 03:59:14 PM PDT 24
Peak memory 204076 kb
Host smart-c3b7e66a-c6e9-4b99-99e8-1e8ea4a87a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17352
32290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.1735232290
Directory /workspace/9.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/9.usbdev_stall_trans.410787328
Short name T403
Test name
Test status
Simulation time 8383131038 ps
CPU time 8.09 seconds
Started Apr 21 03:59:04 PM PDT 24
Finished Apr 21 03:59:13 PM PDT 24
Peak memory 204084 kb
Host smart-8ea2e307-658b-49ee-8c80-679a675f8c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41078
7328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.410787328
Directory /workspace/9.usbdev_stall_trans/latest
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