Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	25466	1		T1	2		T2	2		T3	3
all_values[1]	25466	1		T1	2		T2	2		T3	3
all_values[2]	25466	1		T1	2		T2	2		T3	3
all_values[3]	25466	1		T1	2		T2	2		T3	3
all_values[4]	25466	1		T1	2		T2	2		T3	3
all_values[5]	25466	1		T1	2		T2	2		T3	3
all_values[6]	25466	1		T1	2		T2	2		T3	3
all_values[7]	25466	1		T1	2		T2	2		T3	3
all_values[8]	25466	1		T1	2		T2	2		T3	3
all_values[9]	25466	1		T1	2		T2	2		T3	3
all_values[10]	25466	1		T1	2		T2	2		T3	3
all_values[11]	25466	1		T1	2		T2	2		T3	3
all_values[12]	25466	1		T1	2		T2	2		T3	3
all_values[13]	25466	1		T1	2		T2	2		T3	3
all_values[14]	25466	1		T1	2		T2	2		T3	3
all_values[15]	25466	1		T1	2		T2	2		T3	3
all_values[16]	25466	1		T1	2		T2	2		T3	3
all_values[17]	25466	1		T1	2		T2	2		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	454423	1		T1	36		T2	36		T3	54
auto[1]	3965	1		T18	3		T19	3		T39	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	453261	1		T1	36		T2	36		T3	54
auto[1]	5127	1		T65	82		T66	135		T67	125

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	24463	1		T1	2		T2	2		T3	3
all_values[0]	auto[0]	auto[1]	144	1		T66	6		T67	2		T68	1
all_values[0]	auto[1]	auto[0]	720	1		T19	3		T48	4		T49	4
all_values[0]	auto[1]	auto[1]	139	1		T65	4		T66	2		T67	4
all_values[1]	auto[0]	auto[0]	24857	1		T1	2		T2	2		T3	3
all_values[1]	auto[0]	auto[1]	158	1		T65	4		T66	1		T67	3
all_values[1]	auto[1]	auto[0]	320	1		T18	3		T39	3		T50	3
all_values[1]	auto[1]	auto[1]	131	1		T65	1		T66	6		T69	4
all_values[2]	auto[0]	auto[0]	25157	1		T1	2		T2	2		T3	3
all_values[2]	auto[0]	auto[1]	138	1		T65	1		T66	4		T67	8
all_values[2]	auto[1]	auto[0]	19	1		T69	1		T71	2		T269	1
all_values[2]	auto[1]	auto[1]	152	1		T65	4		T66	3		T68	4
all_values[3]	auto[0]	auto[0]	25153	1		T1	2		T2	2		T3	3
all_values[3]	auto[0]	auto[1]	133	1		T65	4		T66	6		T67	1
all_values[3]	auto[1]	auto[0]	18	1		T268	1		T269	1		T270	1
all_values[3]	auto[1]	auto[1]	162	1		T65	1		T66	2		T67	7
all_values[4]	auto[0]	auto[0]	25159	1		T1	2		T2	2		T3	3
all_values[4]	auto[0]	auto[1]	158	1		T65	4		T66	5		T67	2
all_values[4]	auto[1]	auto[0]	27	1		T68	1		T271	1		T268	1
all_values[4]	auto[1]	auto[1]	122	1		T65	1		T66	2		T67	6
all_values[5]	auto[0]	auto[0]	25172	1		T1	2		T2	2		T3	3
all_values[5]	auto[0]	auto[1]	122	1		T65	1		T66	5		T67	2
all_values[5]	auto[1]	auto[0]	35	1		T65	1		T68	5		T69	2
all_values[5]	auto[1]	auto[1]	137	1		T65	3		T66	3		T67	6
all_values[6]	auto[0]	auto[0]	25147	1		T1	2		T2	2		T3	3
all_values[6]	auto[0]	auto[1]	177	1		T66	5		T67	8		T68	1
all_values[6]	auto[1]	auto[0]	30	1		T65	1		T69	1		T268	1
all_values[6]	auto[1]	auto[1]	112	1		T65	4		T66	2		T68	4
all_values[7]	auto[0]	auto[0]	25146	1		T1	2		T2	2		T3	3
all_values[7]	auto[0]	auto[1]	174	1		T65	5		T66	5		T67	4
all_values[7]	auto[1]	auto[0]	23	1		T67	1		T71	2		T270	1
all_values[7]	auto[1]	auto[1]	123	1		T66	3		T67	2		T68	2
all_values[8]	auto[0]	auto[0]	25148	1		T1	2		T2	2		T3	3
all_values[8]	auto[0]	auto[1]	132	1		T65	4		T66	1		T67	3
all_values[8]	auto[1]	auto[0]	30	1		T272	2		T71	1		T273	1
all_values[8]	auto[1]	auto[1]	156	1		T65	1		T66	7		T67	5
all_values[9]	auto[0]	auto[0]	25146	1		T1	2		T2	2		T3	3
all_values[9]	auto[0]	auto[1]	149	1		T65	3		T66	2		T67	2
all_values[9]	auto[1]	auto[0]	18	1		T67	1		T71	2		T270	1
all_values[9]	auto[1]	auto[1]	153	1		T65	2		T66	6		T67	4
all_values[10]	auto[0]	auto[0]	25168	1		T1	2		T2	2		T3	3
all_values[10]	auto[0]	auto[1]	153	1		T65	5		T66	3		T67	6
all_values[10]	auto[1]	auto[0]	25	1		T68	3		T69	2		T271	2
all_values[10]	auto[1]	auto[1]	120	1		T66	5		T67	1		T71	2
all_values[11]	auto[0]	auto[0]	25160	1		T1	2		T2	2		T3	3
all_values[11]	auto[0]	auto[1]	149	1		T65	3		T66	1		T67	2
all_values[11]	auto[1]	auto[0]	33	1		T65	1		T66	1		T67	1
all_values[11]	auto[1]	auto[1]	124	1		T66	3		T67	4		T68	1
all_values[12]	auto[0]	auto[0]	25159	1		T1	2		T2	2		T3	3
all_values[12]	auto[0]	auto[1]	130	1		T66	6		T67	3		T68	4
all_values[12]	auto[1]	auto[0]	39	1		T69	1		T272	2		T71	2
all_values[12]	auto[1]	auto[1]	138	1		T65	5		T66	2		T67	3
all_values[13]	auto[0]	auto[0]	25154	1		T1	2		T2	2		T3	3
all_values[13]	auto[0]	auto[1]	157	1		T65	3		T66	5		T67	4
all_values[13]	auto[1]	auto[0]	18	1		T69	1		T271	1		T273	1
all_values[13]	auto[1]	auto[1]	137	1		T65	2		T66	3		T67	3
all_values[14]	auto[0]	auto[0]	25162	1		T1	2		T2	2		T3	3
all_values[14]	auto[0]	auto[1]	138	1		T65	1		T66	6		T67	5
all_values[14]	auto[1]	auto[0]	28	1		T65	1		T271	1		T268	1
all_values[14]	auto[1]	auto[1]	138	1		T65	3		T66	2		T67	3
all_values[15]	auto[0]	auto[0]	25143	1		T1	2		T2	2		T3	3
all_values[15]	auto[0]	auto[1]	138	1		T65	1		T66	1		T67	2
all_values[15]	auto[1]	auto[0]	22	1		T68	5		T69	2		T71	1
all_values[15]	auto[1]	auto[1]	163	1		T65	4		T66	7		T67	6
all_values[16]	auto[0]	auto[0]	25160	1		T1	2		T2	2		T3	3
all_values[16]	auto[0]	auto[1]	145	1		T65	4		T66	5		T67	5
all_values[16]	auto[1]	auto[0]	23	1		T67	1		T69	1		T268	1
all_values[16]	auto[1]	auto[1]	138	1		T66	3		T67	1		T68	1
all_values[17]	auto[0]	auto[0]	25162	1		T1	2		T2	2		T3	3
all_values[17]	auto[0]	auto[1]	112	1		T65	1		T66	3		T67	4
all_values[17]	auto[1]	auto[0]	17	1		T65	1		T270	2		T274	3
all_values[17]	auto[1]	auto[1]	175	1		T65	3		T66	4		T67	4