Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	25466	1		T1	2		T2	2		T3	3
all_pins[1]	25466	1		T1	2		T2	2		T3	3
all_pins[2]	25466	1		T1	2		T2	2		T3	3
all_pins[3]	25466	1		T1	2		T2	2		T3	3
all_pins[4]	25466	1		T1	2		T2	2		T3	3
all_pins[5]	25466	1		T1	2		T2	2		T3	3
all_pins[6]	25466	1		T1	2		T2	2		T3	3
all_pins[7]	25466	1		T1	2		T2	2		T3	3
all_pins[8]	25466	1		T1	2		T2	2		T3	3
all_pins[9]	25466	1		T1	2		T2	2		T3	3
all_pins[10]	25466	1		T1	2		T2	2		T3	3
all_pins[11]	25466	1		T1	2		T2	2		T3	3
all_pins[12]	25466	1		T1	2		T2	2		T3	3
all_pins[13]	25466	1		T1	2		T2	2		T3	3
all_pins[14]	25466	1		T1	2		T2	2		T3	3
all_pins[15]	25466	1		T1	2		T2	2		T3	3
all_pins[16]	25466	1		T1	2		T2	2		T3	3
all_pins[17]	25466	1		T1	2		T2	2		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	457017	1		T1	36		T2	36		T3	54
values[0x1]	1371	1		T18	1		T39	1		T50	1
transitions[0x0=>0x1]	1079	1		T18	1		T39	1		T50	1
transitions[0x1=>0x0]	1089	1		T18	1		T39	1		T50	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	25308	1		T1	2		T2	2		T3	3
all_pins[0]	values[0x1]	158	1		T48	1		T49	1		T84	1
all_pins[0]	transitions[0x0=>0x1]	145	1		T48	1		T49	1		T84	1
all_pins[0]	transitions[0x1=>0x0]	149	1		T18	1		T39	1		T50	1
all_pins[1]	values[0x0]	25304	1		T1	2		T2	2		T3	3
all_pins[1]	values[0x1]	162	1		T18	1		T39	1		T50	1
all_pins[1]	transitions[0x0=>0x1]	141	1		T18	1		T39	1		T50	1
all_pins[1]	transitions[0x1=>0x0]	63	1		T65	1		T66	2		T272	1
all_pins[2]	values[0x0]	25382	1		T1	2		T2	2		T3	3
all_pins[2]	values[0x1]	84	1		T65	1		T66	3		T272	1
all_pins[2]	transitions[0x0=>0x1]	61	1		T65	1		T66	2		T272	1
all_pins[2]	transitions[0x1=>0x0]	59	1		T66	1		T67	1		T69	1
all_pins[3]	values[0x0]	25384	1		T1	2		T2	2		T3	3
all_pins[3]	values[0x1]	82	1		T66	2		T67	1		T69	1
all_pins[3]	transitions[0x0=>0x1]	65	1		T66	1		T67	1		T69	1
all_pins[3]	transitions[0x1=>0x0]	33	1		T67	1		T69	1		T71	2
all_pins[4]	values[0x0]	25416	1		T1	2		T2	2		T3	3
all_pins[4]	values[0x1]	50	1		T66	1		T67	1		T69	1
all_pins[4]	transitions[0x0=>0x1]	39	1		T66	1		T67	1		T69	1
all_pins[4]	transitions[0x1=>0x0]	55	1		T65	2		T66	1		T67	3
all_pins[5]	values[0x0]	25400	1		T1	2		T2	2		T3	3
all_pins[5]	values[0x1]	66	1		T65	2		T66	1		T67	3
all_pins[5]	transitions[0x0=>0x1]	54	1		T66	1		T67	3		T272	4
all_pins[5]	transitions[0x1=>0x0]	55	1		T65	1		T66	2		T69	3
all_pins[6]	values[0x0]	25399	1		T1	2		T2	2		T3	3
all_pins[6]	values[0x1]	67	1		T65	3		T66	2		T69	3
all_pins[6]	transitions[0x0=>0x1]	56	1		T65	3		T66	2		T69	3
all_pins[6]	transitions[0x1=>0x0]	48	1		T66	1		T67	2		T68	1
all_pins[7]	values[0x0]	25407	1		T1	2		T2	2		T3	3
all_pins[7]	values[0x1]	59	1		T66	1		T67	2		T68	1
all_pins[7]	transitions[0x0=>0x1]	38	1		T272	2		T71	1		T268	1
all_pins[7]	transitions[0x1=>0x0]	39	1		T65	1		T66	1		T67	2
all_pins[8]	values[0x0]	25406	1		T1	2		T2	2		T3	3
all_pins[8]	values[0x1]	60	1		T65	1		T66	2		T67	4
all_pins[8]	transitions[0x0=>0x1]	47	1		T66	2		T67	3		T68	1
all_pins[8]	transitions[0x1=>0x0]	46	1		T66	4		T69	2		T272	2
all_pins[9]	values[0x0]	25407	1		T1	2		T2	2		T3	3
all_pins[9]	values[0x1]	59	1		T65	1		T66	4		T67	1
all_pins[9]	transitions[0x0=>0x1]	43	1		T65	1		T66	2		T67	1
all_pins[9]	transitions[0x1=>0x0]	50	1		T67	1		T71	2		T268	1
all_pins[10]	values[0x0]	25400	1		T1	2		T2	2		T3	3
all_pins[10]	values[0x1]	66	1		T66	2		T67	1		T71	2
all_pins[10]	transitions[0x0=>0x1]	53	1		T66	2		T67	1		T71	1
all_pins[10]	transitions[0x1=>0x0]	37	1		T66	2		T68	1		T272	1
all_pins[11]	values[0x0]	25416	1		T1	2		T2	2		T3	3
all_pins[11]	values[0x1]	50	1		T66	2		T68	1		T272	1
all_pins[11]	transitions[0x0=>0x1]	38	1		T66	2		T68	1		T272	1
all_pins[11]	transitions[0x1=>0x0]	61	1		T65	2		T66	1		T67	1
all_pins[12]	values[0x0]	25393	1		T1	2		T2	2		T3	3
all_pins[12]	values[0x1]	73	1		T65	2		T66	1		T67	1
all_pins[12]	transitions[0x0=>0x1]	51	1		T65	1		T66	1		T71	1
all_pins[12]	transitions[0x1=>0x0]	49	1		T66	1		T67	2		T69	3
all_pins[13]	values[0x0]	25395	1		T1	2		T2	2		T3	3
all_pins[13]	values[0x1]	71	1		T65	1		T66	1		T67	3
all_pins[13]	transitions[0x0=>0x1]	58	1		T65	1		T66	1		T67	3
all_pins[13]	transitions[0x1=>0x0]	40	1		T67	1		T272	1		T271	1
all_pins[14]	values[0x0]	25413	1		T1	2		T2	2		T3	3
all_pins[14]	values[0x1]	53	1		T67	1		T69	3		T272	1
all_pins[14]	transitions[0x0=>0x1]	32	1		T69	3		T272	1		T271	1
all_pins[14]	transitions[0x1=>0x0]	63	1		T65	3		T66	1		T67	4
all_pins[15]	values[0x0]	25382	1		T1	2		T2	2		T3	3
all_pins[15]	values[0x1]	84	1		T65	3		T66	1		T67	5
all_pins[15]	transitions[0x0=>0x1]	65	1		T65	3		T66	1		T67	4
all_pins[15]	transitions[0x1=>0x0]	43	1		T68	1		T69	1		T272	1
all_pins[16]	values[0x0]	25404	1		T1	2		T2	2		T3	3
all_pins[16]	values[0x1]	62	1		T67	1		T68	1		T69	1
all_pins[16]	transitions[0x0=>0x1]	48	1		T67	1		T68	1		T272	1
all_pins[16]	transitions[0x1=>0x0]	51	1		T66	2		T67	2		T69	1
all_pins[17]	values[0x0]	25401	1		T1	2		T2	2		T3	3
all_pins[17]	values[0x1]	65	1		T66	2		T67	2		T69	2
all_pins[17]	transitions[0x0=>0x1]	45	1		T66	2		T67	2		T69	2
all_pins[17]	transitions[0x1=>0x0]	148	1		T48	1		T49	1		T84	1