Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1		T65	4		T66	7		T67	7
all_values[1]	284	1		T65	4		T66	7		T67	7
all_values[2]	284	1		T65	4		T66	7		T67	7
all_values[3]	284	1		T65	4		T66	7		T67	7
all_values[4]	284	1		T65	4		T66	7		T67	7
all_values[5]	284	1		T65	4		T66	7		T67	7
all_values[6]	284	1		T65	4		T66	7		T67	7
all_values[7]	284	1		T65	4		T66	7		T67	7
all_values[8]	284	1		T65	4		T66	7		T67	7
all_values[9]	284	1		T65	4		T66	7		T67	7
all_values[10]	284	1		T65	4		T66	7		T67	7
all_values[11]	284	1		T65	4		T66	7		T67	7
all_values[12]	284	1		T65	4		T66	7		T67	7
all_values[13]	284	1		T65	4		T66	7		T67	7
all_values[14]	284	1		T65	4		T66	7		T67	7
all_values[15]	284	1		T65	4		T66	7		T67	7
all_values[16]	284	1		T65	4		T66	7		T67	7
all_values[17]	284	1		T65	4		T66	7		T67	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2743	1		T65	48		T66	69		T67	71
auto[1]	2369	1		T65	24		T66	57		T67	55

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	839	1		T65	8		T66	9		T67	19
auto[1]	4273	1		T65	64		T66	117		T67	107

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2988	1		T65	38		T66	70		T67	74
auto[1]	2124	1		T65	34		T66	56		T67	52

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	36	1		T65	1		T67	1		T69	1
all_values[0]	auto[0]	auto[0]	auto[1]	54	1		T66	3		T67	2		T271	1
all_values[0]	auto[0]	auto[1]	auto[0]	13	1		T67	1		T71	1		T275	1
all_values[0]	auto[0]	auto[1]	auto[1]	60	1		T65	2		T66	1		T67	2
all_values[0]	auto[1]	auto[0]	auto[1]	60	1		T66	2		T67	1		T68	1
all_values[0]	auto[1]	auto[1]	auto[1]	61	1		T65	1		T66	1		T68	2
all_values[1]	auto[0]	auto[0]	auto[0]	27	1		T67	4		T68	2		T69	1
all_values[1]	auto[0]	auto[0]	auto[1]	67	1		T65	2		T67	1		T68	1
all_values[1]	auto[0]	auto[1]	auto[0]	15	1		T66	1		T67	1		T71	1
all_values[1]	auto[0]	auto[1]	auto[1]	47	1		T66	4		T69	2		T272	2
all_values[1]	auto[1]	auto[0]	auto[1]	71	1		T65	2		T67	1		T68	1
all_values[1]	auto[1]	auto[1]	auto[1]	57	1		T66	2		T71	2		T271	1
all_values[2]	auto[0]	auto[0]	auto[0]	27	1		T66	1		T68	1		T69	2
all_values[2]	auto[0]	auto[0]	auto[1]	64	1		T66	1		T67	3		T69	1
all_values[2]	auto[0]	auto[1]	auto[0]	16	1		T71	2		T269	1		T274	1
all_values[2]	auto[0]	auto[1]	auto[1]	59	1		T65	2		T66	1		T68	2
all_values[2]	auto[1]	auto[0]	auto[1]	62	1		T65	1		T66	4		T67	4
all_values[2]	auto[1]	auto[1]	auto[1]	56	1		T65	1		T68	1		T69	1
all_values[3]	auto[0]	auto[0]	auto[0]	25	1		T271	1		T270	1		T275	2
all_values[3]	auto[0]	auto[0]	auto[1]	50	1		T65	1		T66	2		T68	2
all_values[3]	auto[0]	auto[1]	auto[0]	13	1		T268	1		T269	1		T276	1
all_values[3]	auto[0]	auto[1]	auto[1]	74	1		T66	1		T67	5		T68	1
all_values[3]	auto[1]	auto[0]	auto[1]	73	1		T65	3		T66	3		T67	1
all_values[3]	auto[1]	auto[1]	auto[1]	49	1		T66	1		T67	1		T68	1
all_values[4]	auto[0]	auto[0]	auto[0]	30	1		T66	1		T68	1		T271	1
all_values[4]	auto[0]	auto[0]	auto[1]	61	1		T65	2		T66	1		T68	1
all_values[4]	auto[0]	auto[1]	auto[0]	19	1		T68	1		T273	1		T275	1
all_values[4]	auto[0]	auto[1]	auto[1]	58	1		T67	5		T272	2		T71	1
all_values[4]	auto[1]	auto[0]	auto[1]	71	1		T65	2		T66	5		T67	1
all_values[4]	auto[1]	auto[1]	auto[1]	45	1		T67	1		T69	1		T272	2
all_values[5]	auto[0]	auto[0]	auto[0]	38	1		T65	1		T269	3		T274	2
all_values[5]	auto[0]	auto[0]	auto[1]	50	1		T66	2		T67	2		T272	1
all_values[5]	auto[0]	auto[1]	auto[0]	30	1		T68	4		T69	2		T71	1
all_values[5]	auto[0]	auto[1]	auto[1]	56	1		T65	1		T66	1		T67	2
all_values[5]	auto[1]	auto[0]	auto[1]	64	1		T65	1		T66	2		T67	1
all_values[5]	auto[1]	auto[1]	auto[1]	46	1		T65	1		T66	2		T67	2
all_values[6]	auto[0]	auto[0]	auto[0]	19	1		T65	1		T66	1		T272	1
all_values[6]	auto[0]	auto[0]	auto[1]	72	1		T66	4		T67	3		T272	4
all_values[6]	auto[0]	auto[1]	auto[0]	25	1		T69	1		T268	1		T269	2
all_values[6]	auto[0]	auto[1]	auto[1]	45	1		T65	1		T68	1		T69	2
all_values[6]	auto[1]	auto[0]	auto[1]	75	1		T66	2		T67	4		T68	1
all_values[6]	auto[1]	auto[1]	auto[1]	48	1		T65	2		T68	2		T69	1
all_values[7]	auto[0]	auto[0]	auto[0]	22	1		T67	2		T71	1		T271	1
all_values[7]	auto[0]	auto[0]	auto[1]	78	1		T65	2		T66	1		T67	1
all_values[7]	auto[0]	auto[1]	auto[0]	15	1		T71	2		T274	1		T277	3
all_values[7]	auto[0]	auto[1]	auto[1]	51	1		T66	3		T68	1		T272	3
all_values[7]	auto[1]	auto[0]	auto[1]	60	1		T65	2		T66	2		T67	1
all_values[7]	auto[1]	auto[1]	auto[1]	58	1		T66	1		T67	3		T68	1
all_values[8]	auto[0]	auto[0]	auto[0]	24	1		T272	1		T277	1		T278	2
all_values[8]	auto[0]	auto[0]	auto[1]	64	1		T65	1		T67	2		T69	1
all_values[8]	auto[0]	auto[1]	auto[0]	19	1		T272	1		T71	1		T273	1
all_values[8]	auto[0]	auto[1]	auto[1]	67	1		T66	4		T67	1		T68	2
all_values[8]	auto[1]	auto[0]	auto[1]	54	1		T65	3		T67	1		T69	3
all_values[8]	auto[1]	auto[1]	auto[1]	56	1		T66	3		T67	3		T68	2
all_values[9]	auto[0]	auto[0]	auto[0]	18	1		T67	2		T71	1		T270	1
all_values[9]	auto[0]	auto[0]	auto[1]	68	1		T65	2		T66	2		T68	2
all_values[9]	auto[0]	auto[1]	auto[0]	12	1		T71	2		T274	1		T279	1
all_values[9]	auto[0]	auto[1]	auto[1]	68	1		T65	1		T66	1		T67	2
all_values[9]	auto[1]	auto[0]	auto[1]	66	1		T65	1		T66	1		T67	3
all_values[9]	auto[1]	auto[1]	auto[1]	52	1		T66	3		T68	1		T69	2
all_values[10]	auto[0]	auto[0]	auto[0]	36	1		T67	1		T68	2		T69	1
all_values[10]	auto[0]	auto[0]	auto[1]	60	1		T65	1		T67	2		T272	3
all_values[10]	auto[0]	auto[1]	auto[0]	20	1		T68	2		T69	3		T271	1
all_values[10]	auto[0]	auto[1]	auto[1]	55	1		T66	4		T67	1		T273	3
all_values[10]	auto[1]	auto[0]	auto[1]	63	1		T65	3		T66	3		T67	2
all_values[10]	auto[1]	auto[1]	auto[1]	50	1		T67	1		T71	2		T268	1
all_values[11]	auto[0]	auto[0]	auto[0]	34	1		T65	1		T66	3		T67	2
all_values[11]	auto[0]	auto[0]	auto[1]	58	1		T65	1		T68	2		T69	1
all_values[11]	auto[0]	auto[1]	auto[0]	24	1		T65	1		T66	1		T272	1
all_values[11]	auto[0]	auto[1]	auto[1]	52	1		T66	1		T67	2		T69	2
all_values[11]	auto[1]	auto[0]	auto[1]	69	1		T65	1		T67	2		T68	1
all_values[11]	auto[1]	auto[1]	auto[1]	47	1		T66	2		T67	1		T68	1
all_values[12]	auto[0]	auto[0]	auto[0]	30	1		T67	2		T272	2		T273	1
all_values[12]	auto[0]	auto[0]	auto[1]	54	1		T66	3		T67	1		T68	2
all_values[12]	auto[0]	auto[1]	auto[0]	31	1		T69	1		T272	1		T71	2
all_values[12]	auto[0]	auto[1]	auto[1]	54	1		T65	2		T66	1		T67	1
all_values[12]	auto[1]	auto[0]	auto[1]	50	1		T65	1		T66	1		T67	1
all_values[12]	auto[1]	auto[1]	auto[1]	65	1		T65	1		T66	2		T67	2
all_values[13]	auto[0]	auto[0]	auto[0]	31	1		T67	1		T272	2		T271	2
all_values[13]	auto[0]	auto[0]	auto[1]	74	1		T65	2		T66	2		T67	2
all_values[13]	auto[0]	auto[1]	auto[0]	8	1		T69	1		T273	1		T276	2
all_values[13]	auto[0]	auto[1]	auto[1]	54	1		T65	1		T66	2		T67	1
all_values[13]	auto[1]	auto[0]	auto[1]	57	1		T65	1		T68	2		T71	1
all_values[13]	auto[1]	auto[1]	auto[1]	60	1		T66	3		T67	3		T69	2
all_values[14]	auto[0]	auto[0]	auto[0]	30	1		T65	1		T71	1		T271	1
all_values[14]	auto[0]	auto[0]	auto[1]	63	1		T66	3		T67	2		T68	1
all_values[14]	auto[0]	auto[1]	auto[0]	25	1		T268	1		T269	4		T274	3
all_values[14]	auto[0]	auto[1]	auto[1]	54	1		T65	1		T66	1		T67	2
all_values[14]	auto[1]	auto[0]	auto[1]	64	1		T65	1		T66	3		T67	2
all_values[14]	auto[1]	auto[1]	auto[1]	48	1		T65	1		T67	1		T69	1
all_values[15]	auto[0]	auto[0]	auto[0]	10	1		T268	1		T269	1		T270	1
all_values[15]	auto[0]	auto[0]	auto[1]	51	1		T66	1		T69	1		T272	3
all_values[15]	auto[0]	auto[1]	auto[0]	22	1		T68	4		T69	2		T71	1
all_values[15]	auto[0]	auto[1]	auto[1]	65	1		T65	1		T66	3		T67	4
all_values[15]	auto[1]	auto[0]	auto[1]	67	1		T65	1		T66	1		T67	2
all_values[15]	auto[1]	auto[1]	auto[1]	69	1		T65	2		T66	2		T67	1
all_values[16]	auto[0]	auto[0]	auto[0]	30	1		T65	1		T67	1		T272	1
all_values[16]	auto[0]	auto[0]	auto[1]	59	1		T65	2		T66	2		T67	2
all_values[16]	auto[0]	auto[1]	auto[0]	21	1		T67	1		T69	1		T268	1
all_values[16]	auto[0]	auto[1]	auto[1]	53	1		T66	2		T272	2		T71	3
all_values[16]	auto[1]	auto[0]	auto[1]	62	1		T65	1		T66	2		T67	1
all_values[16]	auto[1]	auto[1]	auto[1]	59	1		T66	1		T67	2		T68	1
all_values[17]	auto[0]	auto[0]	auto[0]	32	1		T65	1		T66	1		T272	1
all_values[17]	auto[0]	auto[0]	auto[1]	50	1		T66	3		T67	3		T68	2
all_values[17]	auto[0]	auto[1]	auto[0]	12	1		T270	2		T274	3		T275	2
all_values[17]	auto[0]	auto[1]	auto[1]	80	1		T65	2		T66	1		T67	1
all_values[17]	auto[1]	auto[0]	auto[1]	59	1		T65	1		T66	1		T67	1
all_values[17]	auto[1]	auto[1]	auto[1]	51	1		T66	1		T67	2		T69	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal