Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.39 95.60 88.87 96.25 50.00 94.10 97.35 96.58


Total test records in report: 1478
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T1326 /workspace/coverage/default/13.usbdev_stall_priority_over_nak.2536986179 Apr 23 02:36:13 PM PDT 24 Apr 23 02:36:22 PM PDT 24 8392608395 ps
T1327 /workspace/coverage/default/44.usbdev_in_trans.3134587839 Apr 23 02:38:24 PM PDT 24 Apr 23 02:38:35 PM PDT 24 8393757645 ps
T1328 /workspace/coverage/default/7.usbdev_enable.2338707165 Apr 23 02:35:38 PM PDT 24 Apr 23 02:35:46 PM PDT 24 8387923280 ps
T1329 /workspace/coverage/default/19.usbdev_pkt_sent.3800535887 Apr 23 02:36:40 PM PDT 24 Apr 23 02:36:51 PM PDT 24 8434907526 ps
T1330 /workspace/coverage/default/4.usbdev_phy_pins_sense.3133278512 Apr 23 02:35:27 PM PDT 24 Apr 23 02:35:28 PM PDT 24 38574615 ps
T1331 /workspace/coverage/default/33.usbdev_random_length_out_trans.1724974310 Apr 23 02:37:43 PM PDT 24 Apr 23 02:37:52 PM PDT 24 8406231230 ps
T1332 /workspace/coverage/default/1.usbdev_pending_in_trans.2244560703 Apr 23 02:35:11 PM PDT 24 Apr 23 02:35:20 PM PDT 24 8401021188 ps
T1333 /workspace/coverage/default/30.usbdev_out_trans_nak.2926773830 Apr 23 02:37:35 PM PDT 24 Apr 23 02:37:45 PM PDT 24 8377386750 ps
T1334 /workspace/coverage/default/21.usbdev_setup_stage.354235076 Apr 23 02:36:49 PM PDT 24 Apr 23 02:36:57 PM PDT 24 8399864397 ps
T1335 /workspace/coverage/default/1.usbdev_pkt_buffer.3171972215 Apr 23 02:35:09 PM PDT 24 Apr 23 02:35:54 PM PDT 24 24581688157 ps
T1336 /workspace/coverage/default/22.usbdev_setup_trans_ignored.1488647316 Apr 23 02:36:51 PM PDT 24 Apr 23 02:36:58 PM PDT 24 8370839406 ps
T1337 /workspace/coverage/default/45.usbdev_stall_trans.1470025570 Apr 23 02:38:35 PM PDT 24 Apr 23 02:38:43 PM PDT 24 8389626976 ps
T1338 /workspace/coverage/default/19.usbdev_phy_pins_sense.2722523930 Apr 23 02:36:46 PM PDT 24 Apr 23 02:36:48 PM PDT 24 206380639 ps
T1339 /workspace/coverage/default/14.usbdev_out_trans_nak.794140608 Apr 23 02:36:12 PM PDT 24 Apr 23 02:36:20 PM PDT 24 8409370837 ps
T1340 /workspace/coverage/default/34.usbdev_pkt_buffer.147364471 Apr 23 02:37:54 PM PDT 24 Apr 23 02:38:55 PM PDT 24 29512600547 ps
T1341 /workspace/coverage/default/18.usbdev_out_stall.1962912683 Apr 23 02:36:36 PM PDT 24 Apr 23 02:36:45 PM PDT 24 8425124509 ps
T1342 /workspace/coverage/default/2.usbdev_enable.1634115896 Apr 23 02:35:13 PM PDT 24 Apr 23 02:35:22 PM PDT 24 8373907808 ps
T1343 /workspace/coverage/default/34.usbdev_in_stall.1074842901 Apr 23 02:37:47 PM PDT 24 Apr 23 02:37:59 PM PDT 24 8375443417 ps
T1344 /workspace/coverage/default/23.usbdev_pkt_sent.2453611742 Apr 23 02:36:54 PM PDT 24 Apr 23 02:37:03 PM PDT 24 8404829161 ps
T1345 /workspace/coverage/default/44.usbdev_phy_pins_sense.3923199461 Apr 23 02:38:28 PM PDT 24 Apr 23 02:38:29 PM PDT 24 37858032 ps
T1346 /workspace/coverage/default/44.usbdev_stall_trans.3167451432 Apr 23 02:38:24 PM PDT 24 Apr 23 02:38:34 PM PDT 24 8388823113 ps
T1347 /workspace/coverage/default/24.usbdev_phy_pins_sense.3165769681 Apr 23 02:37:03 PM PDT 24 Apr 23 02:37:04 PM PDT 24 32783493 ps
T1348 /workspace/coverage/default/49.usbdev_av_buffer.1086561232 Apr 23 02:38:54 PM PDT 24 Apr 23 02:39:03 PM PDT 24 8381347234 ps
T1349 /workspace/coverage/default/48.usbdev_in_trans.311584656 Apr 23 02:38:45 PM PDT 24 Apr 23 02:38:54 PM PDT 24 8420638606 ps
T1350 /workspace/coverage/default/21.usbdev_pkt_buffer.3008767618 Apr 23 02:36:51 PM PDT 24 Apr 23 02:37:21 PM PDT 24 14994367824 ps
T1351 /workspace/coverage/default/23.usbdev_max_length_out_transaction.199209779 Apr 23 02:36:57 PM PDT 24 Apr 23 02:37:06 PM PDT 24 8412180945 ps
T1352 /workspace/coverage/default/29.usbdev_out_trans_nak.3102688635 Apr 23 02:37:21 PM PDT 24 Apr 23 02:37:30 PM PDT 24 8395074366 ps
T1353 /workspace/coverage/default/24.usbdev_pkt_buffer.1996944672 Apr 23 02:37:00 PM PDT 24 Apr 23 02:37:43 PM PDT 24 20837528189 ps
T112 /workspace/coverage/default/39.usbdev_nak_trans.3576348461 Apr 23 02:38:03 PM PDT 24 Apr 23 02:38:12 PM PDT 24 8472263869 ps
T1354 /workspace/coverage/default/6.usbdev_enable.1180479741 Apr 23 02:35:31 PM PDT 24 Apr 23 02:35:39 PM PDT 24 8394428642 ps
T1355 /workspace/coverage/default/32.usbdev_pkt_received.4231757906 Apr 23 02:37:36 PM PDT 24 Apr 23 02:37:45 PM PDT 24 8391470653 ps
T1356 /workspace/coverage/default/9.usbdev_pkt_received.747044222 Apr 23 02:35:55 PM PDT 24 Apr 23 02:36:04 PM PDT 24 8376871228 ps
T1357 /workspace/coverage/default/13.usbdev_in_stall.2617186459 Apr 23 02:36:12 PM PDT 24 Apr 23 02:36:22 PM PDT 24 8398872750 ps
T1358 /workspace/coverage/default/39.usbdev_out_trans_nak.3245562541 Apr 23 02:38:05 PM PDT 24 Apr 23 02:38:15 PM PDT 24 8407723704 ps
T1359 /workspace/coverage/default/44.usbdev_random_length_out_trans.39577290 Apr 23 02:38:26 PM PDT 24 Apr 23 02:38:34 PM PDT 24 8406690279 ps
T1360 /workspace/coverage/default/7.usbdev_nak_trans.94514393 Apr 23 02:35:42 PM PDT 24 Apr 23 02:35:50 PM PDT 24 8447573829 ps
T1361 /workspace/coverage/default/40.usbdev_fifo_rst.4124110048 Apr 23 02:38:06 PM PDT 24 Apr 23 02:38:09 PM PDT 24 65318406 ps
T1362 /workspace/coverage/default/24.usbdev_in_iso.1226992125 Apr 23 02:37:01 PM PDT 24 Apr 23 02:37:11 PM PDT 24 8474887738 ps
T1363 /workspace/coverage/default/21.usbdev_out_stall.726623713 Apr 23 02:36:47 PM PDT 24 Apr 23 02:36:55 PM PDT 24 8393260984 ps
T1364 /workspace/coverage/default/22.usbdev_setup_stage.3806872356 Apr 23 02:36:52 PM PDT 24 Apr 23 02:37:00 PM PDT 24 8371506784 ps
T1365 /workspace/coverage/default/34.max_length_in_transaction.2194103426 Apr 23 02:37:42 PM PDT 24 Apr 23 02:37:53 PM PDT 24 8471101536 ps
T1366 /workspace/coverage/default/9.usbdev_pending_in_trans.1909850564 Apr 23 02:35:55 PM PDT 24 Apr 23 02:36:03 PM PDT 24 8398458347 ps
T1367 /workspace/coverage/default/17.usbdev_pkt_buffer.3884542250 Apr 23 02:36:31 PM PDT 24 Apr 23 02:37:03 PM PDT 24 18123210172 ps
T1368 /workspace/coverage/default/17.usbdev_setup_trans_ignored.2431978006 Apr 23 02:36:33 PM PDT 24 Apr 23 02:36:42 PM PDT 24 8372035479 ps
T1369 /workspace/coverage/default/11.usbdev_av_buffer.2250816522 Apr 23 02:35:58 PM PDT 24 Apr 23 02:36:07 PM PDT 24 8398414131 ps
T1370 /workspace/coverage/default/8.usbdev_pending_in_trans.1512977592 Apr 23 02:35:51 PM PDT 24 Apr 23 02:36:01 PM PDT 24 8388389460 ps
T73 /workspace/coverage/default/2.usbdev_sec_cm.522482293 Apr 23 02:35:18 PM PDT 24 Apr 23 02:35:20 PM PDT 24 292896011 ps
T1371 /workspace/coverage/default/45.usbdev_stall_priority_over_nak.410300858 Apr 23 02:38:29 PM PDT 24 Apr 23 02:38:37 PM PDT 24 8375140755 ps
T1372 /workspace/coverage/default/26.usbdev_av_buffer.3110901511 Apr 23 02:37:05 PM PDT 24 Apr 23 02:37:14 PM PDT 24 8419266348 ps
T1373 /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.1756130089 Apr 23 02:37:39 PM PDT 24 Apr 23 02:37:50 PM PDT 24 8396350091 ps
T1374 /workspace/coverage/default/10.usbdev_min_length_out_transaction.288018042 Apr 23 02:35:59 PM PDT 24 Apr 23 02:36:08 PM PDT 24 8374069810 ps
T1375 /workspace/coverage/default/19.usbdev_nak_trans.1104481953 Apr 23 02:36:36 PM PDT 24 Apr 23 02:36:46 PM PDT 24 8437289392 ps
T1376 /workspace/coverage/default/39.usbdev_random_length_out_trans.3411661778 Apr 23 02:38:04 PM PDT 24 Apr 23 02:38:13 PM PDT 24 8391381052 ps
T61 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1299046768 Apr 23 02:24:43 PM PDT 24 Apr 23 02:24:45 PM PDT 24 61810920 ps
T65 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3098903222 Apr 23 02:25:08 PM PDT 24 Apr 23 02:25:10 PM PDT 24 30924593 ps
T64 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1464731234 Apr 23 02:24:47 PM PDT 24 Apr 23 02:24:49 PM PDT 24 76430275 ps
T62 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3879612488 Apr 23 02:24:54 PM PDT 24 Apr 23 02:24:56 PM PDT 24 89776839 ps
T63 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.915702458 Apr 23 02:24:49 PM PDT 24 Apr 23 02:24:53 PM PDT 24 320678445 ps
T91 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.106916602 Apr 23 02:24:41 PM PDT 24 Apr 23 02:24:43 PM PDT 24 51328836 ps
T55 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1499525305 Apr 23 02:24:58 PM PDT 24 Apr 23 02:25:03 PM PDT 24 844684145 ps
T70 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.488115732 Apr 23 02:24:33 PM PDT 24 Apr 23 02:24:35 PM PDT 24 82614885 ps
T56 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.678975851 Apr 23 02:24:34 PM PDT 24 Apr 23 02:24:39 PM PDT 24 351543336 ps
T57 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1713081053 Apr 23 02:25:03 PM PDT 24 Apr 23 02:25:07 PM PDT 24 202246566 ps
T66 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.289480305 Apr 23 02:25:02 PM PDT 24 Apr 23 02:25:03 PM PDT 24 30828837 ps
T92 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3250036740 Apr 23 02:24:59 PM PDT 24 Apr 23 02:25:00 PM PDT 24 94099770 ps
T205 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3769885750 Apr 23 02:24:56 PM PDT 24 Apr 23 02:24:59 PM PDT 24 212870276 ps
T93 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.766258604 Apr 23 02:24:57 PM PDT 24 Apr 23 02:24:59 PM PDT 24 112923347 ps
T67 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3989590320 Apr 23 02:24:59 PM PDT 24 Apr 23 02:25:00 PM PDT 24 41320097 ps
T94 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.187120826 Apr 23 02:24:36 PM PDT 24 Apr 23 02:24:37 PM PDT 24 33516059 ps
T209 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3876097029 Apr 23 02:24:55 PM PDT 24 Apr 23 02:24:58 PM PDT 24 407811704 ps
T1377 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2097294025 Apr 23 02:24:41 PM PDT 24 Apr 23 02:24:45 PM PDT 24 365758000 ps
T206 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3749791027 Apr 23 02:24:45 PM PDT 24 Apr 23 02:24:47 PM PDT 24 111025611 ps
T68 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3273628932 Apr 23 02:24:38 PM PDT 24 Apr 23 02:24:39 PM PDT 24 31496758 ps
T232 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3150932165 Apr 23 02:24:58 PM PDT 24 Apr 23 02:25:03 PM PDT 24 631606842 ps
T235 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.252145047 Apr 23 02:24:37 PM PDT 24 Apr 23 02:24:40 PM PDT 24 463922880 ps
T69 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2621640007 Apr 23 02:25:11 PM PDT 24 Apr 23 02:25:13 PM PDT 24 34642637 ps
T261 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3872499750 Apr 23 02:24:46 PM PDT 24 Apr 23 02:24:47 PM PDT 24 38730108 ps
T233 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.40912024 Apr 23 02:24:53 PM PDT 24 Apr 23 02:24:56 PM PDT 24 96798728 ps
T272 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1425694528 Apr 23 02:24:47 PM PDT 24 Apr 23 02:24:48 PM PDT 24 34923266 ps
T262 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3707397579 Apr 23 02:24:57 PM PDT 24 Apr 23 02:24:58 PM PDT 24 94921051 ps
T210 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.990719077 Apr 23 02:24:58 PM PDT 24 Apr 23 02:25:00 PM PDT 24 116595295 ps
T230 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.638125159 Apr 23 02:24:39 PM PDT 24 Apr 23 02:24:40 PM PDT 24 318854748 ps
T257 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.337825140 Apr 23 02:24:34 PM PDT 24 Apr 23 02:24:36 PM PDT 24 60796454 ps
T223 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3946205822 Apr 23 02:24:47 PM PDT 24 Apr 23 02:24:50 PM PDT 24 120542702 ps
T224 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.4111939016 Apr 23 02:24:54 PM PDT 24 Apr 23 02:24:56 PM PDT 24 152586642 ps
T71 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.787332291 Apr 23 02:25:11 PM PDT 24 Apr 23 02:25:12 PM PDT 24 46032650 ps
T1378 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3114748154 Apr 23 02:24:38 PM PDT 24 Apr 23 02:24:43 PM PDT 24 156023642 ps
T271 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2382478831 Apr 23 02:25:06 PM PDT 24 Apr 23 02:25:08 PM PDT 24 28207523 ps
T234 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3602754421 Apr 23 02:24:41 PM PDT 24 Apr 23 02:24:44 PM PDT 24 127531564 ps
T1379 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3864764581 Apr 23 02:24:50 PM PDT 24 Apr 23 02:24:53 PM PDT 24 210601760 ps
T268 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2140938032 Apr 23 02:24:42 PM PDT 24 Apr 23 02:24:43 PM PDT 24 31464108 ps
T236 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.212229166 Apr 23 02:24:48 PM PDT 24 Apr 23 02:24:51 PM PDT 24 207931544 ps
T273 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2789790607 Apr 23 02:25:07 PM PDT 24 Apr 23 02:25:08 PM PDT 24 34043286 ps
T250 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2531466164 Apr 23 02:24:36 PM PDT 24 Apr 23 02:24:40 PM PDT 24 360856974 ps
T237 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2039857996 Apr 23 02:24:34 PM PDT 24 Apr 23 02:24:37 PM PDT 24 135129946 ps
T207 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2856004034 Apr 23 02:24:49 PM PDT 24 Apr 23 02:24:52 PM PDT 24 189183517 ps
T225 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1819308194 Apr 23 02:24:47 PM PDT 24 Apr 23 02:24:49 PM PDT 24 128200876 ps
T251 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1320032345 Apr 23 02:24:35 PM PDT 24 Apr 23 02:24:37 PM PDT 24 61976645 ps
T1380 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.617405139 Apr 23 02:24:32 PM PDT 24 Apr 23 02:24:35 PM PDT 24 314678241 ps
T1381 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1551346169 Apr 23 02:24:30 PM PDT 24 Apr 23 02:24:31 PM PDT 24 124038890 ps
T208 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2301736205 Apr 23 02:24:54 PM PDT 24 Apr 23 02:24:57 PM PDT 24 489624276 ps
T269 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2301105153 Apr 23 02:25:08 PM PDT 24 Apr 23 02:25:09 PM PDT 24 51265182 ps
T252 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4053330521 Apr 23 02:24:33 PM PDT 24 Apr 23 02:24:35 PM PDT 24 119814452 ps
T1382 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.989156132 Apr 23 02:24:54 PM PDT 24 Apr 23 02:24:56 PM PDT 24 54420880 ps
T270 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.668943114 Apr 23 02:24:50 PM PDT 24 Apr 23 02:24:51 PM PDT 24 34585410 ps
T274 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1606341426 Apr 23 02:24:54 PM PDT 24 Apr 23 02:24:56 PM PDT 24 36666061 ps
T253 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.958986294 Apr 23 02:24:41 PM PDT 24 Apr 23 02:24:44 PM PDT 24 180567422 ps
T254 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1862368320 Apr 23 02:24:30 PM PDT 24 Apr 23 02:24:32 PM PDT 24 84697712 ps
T1383 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4284002193 Apr 23 02:24:32 PM PDT 24 Apr 23 02:24:34 PM PDT 24 125441139 ps
T229 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2037631799 Apr 23 02:24:53 PM PDT 24 Apr 23 02:24:56 PM PDT 24 87861121 ps
T275 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1276519039 Apr 23 02:25:04 PM PDT 24 Apr 23 02:25:06 PM PDT 24 45470295 ps
T283 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3709433970 Apr 23 02:24:45 PM PDT 24 Apr 23 02:24:48 PM PDT 24 361321381 ps
T277 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2595655994 Apr 23 02:25:13 PM PDT 24 Apr 23 02:25:15 PM PDT 24 60698491 ps
T255 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1531539112 Apr 23 02:24:57 PM PDT 24 Apr 23 02:24:58 PM PDT 24 71909349 ps
T267 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1050317205 Apr 23 02:25:05 PM PDT 24 Apr 23 02:25:07 PM PDT 24 139345942 ps
T278 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3300233218 Apr 23 02:25:07 PM PDT 24 Apr 23 02:25:08 PM PDT 24 41439345 ps
T284 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1143654035 Apr 23 02:24:55 PM PDT 24 Apr 23 02:25:01 PM PDT 24 1347283723 ps
T1384 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3729447014 Apr 23 02:24:44 PM PDT 24 Apr 23 02:24:46 PM PDT 24 76490884 ps
T1385 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1121312152 Apr 23 02:24:50 PM PDT 24 Apr 23 02:24:52 PM PDT 24 85807255 ps
T1386 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2236832036 Apr 23 02:24:42 PM PDT 24 Apr 23 02:24:45 PM PDT 24 92744131 ps
T226 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1099255110 Apr 23 02:24:37 PM PDT 24 Apr 23 02:24:39 PM PDT 24 121128749 ps
T1387 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3435935029 Apr 23 02:24:50 PM PDT 24 Apr 23 02:24:52 PM PDT 24 158011158 ps
T227 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2390630484 Apr 23 02:24:45 PM PDT 24 Apr 23 02:24:48 PM PDT 24 206380605 ps
T287 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3300351895 Apr 23 02:24:40 PM PDT 24 Apr 23 02:24:46 PM PDT 24 1103819017 ps
T1388 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.398557476 Apr 23 02:24:41 PM PDT 24 Apr 23 02:24:43 PM PDT 24 129434689 ps
T1389 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3844587197 Apr 23 02:24:37 PM PDT 24 Apr 23 02:24:40 PM PDT 24 84607951 ps
T256 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1679612803 Apr 23 02:24:38 PM PDT 24 Apr 23 02:24:47 PM PDT 24 1044813849 ps
T258 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4294555428 Apr 23 02:24:38 PM PDT 24 Apr 23 02:24:41 PM PDT 24 159577484 ps
T228 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1981875321 Apr 23 02:24:46 PM PDT 24 Apr 23 02:24:50 PM PDT 24 324302818 ps
T1390 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.4059924978 Apr 23 02:24:46 PM PDT 24 Apr 23 02:24:47 PM PDT 24 37451455 ps
T276 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.647287816 Apr 23 02:25:07 PM PDT 24 Apr 23 02:25:08 PM PDT 24 27510269 ps
T285 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.397762094 Apr 23 02:24:34 PM PDT 24 Apr 23 02:24:40 PM PDT 24 755623758 ps
T1391 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3481093735 Apr 23 02:25:10 PM PDT 24 Apr 23 02:25:11 PM PDT 24 45297539 ps
T1392 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2129697504 Apr 23 02:24:34 PM PDT 24 Apr 23 02:24:39 PM PDT 24 733756769 ps
T1393 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.552212841 Apr 23 02:25:07 PM PDT 24 Apr 23 02:25:09 PM PDT 24 60242036 ps
T1394 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.4020278375 Apr 23 02:24:34 PM PDT 24 Apr 23 02:24:38 PM PDT 24 157303470 ps
T259 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2912887211 Apr 23 02:24:38 PM PDT 24 Apr 23 02:24:49 PM PDT 24 1868076745 ps
T1395 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4058124728 Apr 23 02:24:50 PM PDT 24 Apr 23 02:24:54 PM PDT 24 189091411 ps
T1396 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.4061303273 Apr 23 02:25:06 PM PDT 24 Apr 23 02:25:07 PM PDT 24 34147483 ps
T1397 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.944548339 Apr 23 02:25:06 PM PDT 24 Apr 23 02:25:07 PM PDT 24 36725932 ps
T1398 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1380918035 Apr 23 02:24:47 PM PDT 24 Apr 23 02:24:48 PM PDT 24 43486388 ps
T1399 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2706994567 Apr 23 02:24:48 PM PDT 24 Apr 23 02:24:50 PM PDT 24 59450926 ps
T1400 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3553745302 Apr 23 02:24:46 PM PDT 24 Apr 23 02:24:51 PM PDT 24 306653602 ps
T1401 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.360884609 Apr 23 02:24:39 PM PDT 24 Apr 23 02:24:41 PM PDT 24 61302904 ps
T1402 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.662148359 Apr 23 02:24:29 PM PDT 24 Apr 23 02:24:31 PM PDT 24 56848927 ps
T1403 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.727464606 Apr 23 02:25:03 PM PDT 24 Apr 23 02:25:05 PM PDT 24 31216291 ps
T1404 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.174328413 Apr 23 02:25:07 PM PDT 24 Apr 23 02:25:08 PM PDT 24 31642714 ps
T279 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1066329911 Apr 23 02:24:56 PM PDT 24 Apr 23 02:24:57 PM PDT 24 38436891 ps
T1405 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.981406115 Apr 23 02:24:33 PM PDT 24 Apr 23 02:24:38 PM PDT 24 291742218 ps
T1406 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.632233789 Apr 23 02:24:33 PM PDT 24 Apr 23 02:24:35 PM PDT 24 153063098 ps
T1407 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2684611617 Apr 23 02:24:57 PM PDT 24 Apr 23 02:25:00 PM PDT 24 102919254 ps
T280 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3704887929 Apr 23 02:24:49 PM PDT 24 Apr 23 02:24:55 PM PDT 24 830741018 ps
T1408 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1843662190 Apr 23 02:25:09 PM PDT 24 Apr 23 02:25:11 PM PDT 24 32404683 ps
T1409 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.788984557 Apr 23 02:25:04 PM PDT 24 Apr 23 02:25:05 PM PDT 24 42065958 ps
T1410 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2588618043 Apr 23 02:24:31 PM PDT 24 Apr 23 02:24:33 PM PDT 24 81394503 ps
T1411 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1726862952 Apr 23 02:24:45 PM PDT 24 Apr 23 02:24:48 PM PDT 24 78623499 ps
T1412 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1295671346 Apr 23 02:25:09 PM PDT 24 Apr 23 02:25:11 PM PDT 24 96781545 ps
T1413 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2324258716 Apr 23 02:24:42 PM PDT 24 Apr 23 02:24:43 PM PDT 24 32054579 ps
T1414 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2945817472 Apr 23 02:25:13 PM PDT 24 Apr 23 02:25:14 PM PDT 24 33835005 ps
T1415 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.828005925 Apr 23 02:25:04 PM PDT 24 Apr 23 02:25:06 PM PDT 24 188313008 ps
T281 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3171654055 Apr 23 02:24:58 PM PDT 24 Apr 23 02:25:01 PM PDT 24 305837837 ps
T282 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.7404185 Apr 23 02:24:45 PM PDT 24 Apr 23 02:24:51 PM PDT 24 1410632283 ps
T260 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2259858489 Apr 23 02:24:35 PM PDT 24 Apr 23 02:24:37 PM PDT 24 108402261 ps
T1416 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2744741258 Apr 23 02:25:07 PM PDT 24 Apr 23 02:25:08 PM PDT 24 31954025 ps
T1417 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3758711689 Apr 23 02:24:33 PM PDT 24 Apr 23 02:24:34 PM PDT 24 42233084 ps
T1418 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.723871032 Apr 23 02:24:59 PM PDT 24 Apr 23 02:25:01 PM PDT 24 196405843 ps
T1419 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2829463514 Apr 23 02:24:48 PM PDT 24 Apr 23 02:24:50 PM PDT 24 71710157 ps
T1420 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3363467600 Apr 23 02:24:32 PM PDT 24 Apr 23 02:24:34 PM PDT 24 156770003 ps
T1421 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.380145543 Apr 23 02:24:37 PM PDT 24 Apr 23 02:24:40 PM PDT 24 200410981 ps
T231 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.4014428413 Apr 23 02:24:40 PM PDT 24 Apr 23 02:24:41 PM PDT 24 94028774 ps
T1422 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3923698693 Apr 23 02:24:59 PM PDT 24 Apr 23 02:25:01 PM PDT 24 148995098 ps
T1423 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2893152297 Apr 23 02:25:00 PM PDT 24 Apr 23 02:25:02 PM PDT 24 198328862 ps
T1424 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1231248704 Apr 23 02:24:50 PM PDT 24 Apr 23 02:24:51 PM PDT 24 53820853 ps
T1425 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3917538845 Apr 23 02:24:46 PM PDT 24 Apr 23 02:24:51 PM PDT 24 411285955 ps
T1426 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2482824200 Apr 23 02:24:50 PM PDT 24 Apr 23 02:24:52 PM PDT 24 140128543 ps
T1427 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.330673395 Apr 23 02:24:39 PM PDT 24 Apr 23 02:24:41 PM PDT 24 139895626 ps
T1428 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1002855394 Apr 23 02:24:45 PM PDT 24 Apr 23 02:24:48 PM PDT 24 194911919 ps
T1429 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2694385326 Apr 23 02:24:50 PM PDT 24 Apr 23 02:24:53 PM PDT 24 198055808 ps
T1430 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3304231577 Apr 23 02:24:30 PM PDT 24 Apr 23 02:24:33 PM PDT 24 344811209 ps
T1431 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.575858302 Apr 23 02:24:37 PM PDT 24 Apr 23 02:24:38 PM PDT 24 27148176 ps
T1432 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.4128966677 Apr 23 02:24:55 PM PDT 24 Apr 23 02:24:57 PM PDT 24 63681322 ps
T1433 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3309043162 Apr 23 02:24:54 PM PDT 24 Apr 23 02:24:55 PM PDT 24 63475724 ps
T1434 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1255427109 Apr 23 02:24:49 PM PDT 24 Apr 23 02:24:51 PM PDT 24 57623281 ps
T1435 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2703055648 Apr 23 02:25:12 PM PDT 24 Apr 23 02:25:13 PM PDT 24 67508671 ps
T1436 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.637442616 Apr 23 02:25:07 PM PDT 24 Apr 23 02:25:09 PM PDT 24 39454986 ps
T1437 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.4094413058 Apr 23 02:24:51 PM PDT 24 Apr 23 02:24:53 PM PDT 24 87913018 ps
T1438 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2183629874 Apr 23 02:24:47 PM PDT 24 Apr 23 02:24:49 PM PDT 24 106428380 ps
T1439 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2118941598 Apr 23 02:24:55 PM PDT 24 Apr 23 02:24:56 PM PDT 24 102708889 ps
T1440 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3992200220 Apr 23 02:25:10 PM PDT 24 Apr 23 02:25:12 PM PDT 24 31548723 ps
T1441 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3621511102 Apr 23 02:24:48 PM PDT 24 Apr 23 02:24:50 PM PDT 24 60914625 ps
T1442 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2214765801 Apr 23 02:24:48 PM PDT 24 Apr 23 02:24:49 PM PDT 24 28134952 ps
T1443 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.114154506 Apr 23 02:25:07 PM PDT 24 Apr 23 02:25:08 PM PDT 24 33984893 ps
T1444 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.497947536 Apr 23 02:24:50 PM PDT 24 Apr 23 02:24:53 PM PDT 24 204445537 ps
T1445 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.274673249 Apr 23 02:25:11 PM PDT 24 Apr 23 02:25:12 PM PDT 24 50418945 ps
T1446 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1074893709 Apr 23 02:24:33 PM PDT 24 Apr 23 02:24:35 PM PDT 24 37604014 ps
T1447 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2762106961 Apr 23 02:24:41 PM PDT 24 Apr 23 02:24:44 PM PDT 24 143178896 ps
T1448 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2978748683 Apr 23 02:24:42 PM PDT 24 Apr 23 02:24:46 PM PDT 24 96848387 ps
T286 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1352268504 Apr 23 02:24:53 PM PDT 24 Apr 23 02:24:57 PM PDT 24 265868685 ps
T1449 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.860994542 Apr 23 02:25:03 PM PDT 24 Apr 23 02:25:04 PM PDT 24 48717467 ps
T1450 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.105662571 Apr 23 02:24:53 PM PDT 24 Apr 23 02:24:54 PM PDT 24 110300174 ps
T1451 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2361380887 Apr 23 02:24:43 PM PDT 24 Apr 23 02:24:45 PM PDT 24 113767033 ps
T1452 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3570811531 Apr 23 02:24:41 PM PDT 24 Apr 23 02:24:49 PM PDT 24 545822656 ps
T1453 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.621006044 Apr 23 02:24:33 PM PDT 24 Apr 23 02:24:36 PM PDT 24 172729881 ps
T1454 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.4017826802 Apr 23 02:24:51 PM PDT 24 Apr 23 02:24:54 PM PDT 24 74896791 ps
T1455 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3177644513 Apr 23 02:24:54 PM PDT 24 Apr 23 02:24:55 PM PDT 24 75999141 ps
T1456 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3690783225 Apr 23 02:24:57 PM PDT 24 Apr 23 02:24:58 PM PDT 24 35881813 ps
T1457 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1789086743 Apr 23 02:24:41 PM PDT 24 Apr 23 02:24:43 PM PDT 24 65055594 ps
T1458 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2257650019 Apr 23 02:24:35 PM PDT 24 Apr 23 02:24:36 PM PDT 24 24936655 ps
T1459 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1803934224 Apr 23 02:24:32 PM PDT 24 Apr 23 02:24:34 PM PDT 24 146057060 ps
T1460 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3372932025 Apr 23 02:24:57 PM PDT 24 Apr 23 02:24:59 PM PDT 24 118783781 ps
T1461 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1563700928 Apr 23 02:24:42 PM PDT 24 Apr 23 02:24:44 PM PDT 24 60046665 ps
T1462 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2903857937 Apr 23 02:24:34 PM PDT 24 Apr 23 02:24:39 PM PDT 24 482310719 ps
T1463 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1995667830 Apr 23 02:24:49 PM PDT 24 Apr 23 02:24:50 PM PDT 24 71147848 ps
T1464 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3304435676 Apr 23 02:24:33 PM PDT 24 Apr 23 02:24:42 PM PDT 24 1302143385 ps
T1465 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1874666333 Apr 23 02:24:46 PM PDT 24 Apr 23 02:24:48 PM PDT 24 154351014 ps
T1466 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1415477336 Apr 23 02:25:04 PM PDT 24 Apr 23 02:25:07 PM PDT 24 360563561 ps
T1467 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2593694302 Apr 23 02:25:11 PM PDT 24 Apr 23 02:25:13 PM PDT 24 46374465 ps
T1468 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3080882430 Apr 23 02:24:32 PM PDT 24 Apr 23 02:24:33 PM PDT 24 107520215 ps
T1469 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2764504623 Apr 23 02:25:03 PM PDT 24 Apr 23 02:25:04 PM PDT 24 43659654 ps
T1470 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1486472168 Apr 23 02:24:54 PM PDT 24 Apr 23 02:24:55 PM PDT 24 53372894 ps
T1471 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2119456448 Apr 23 02:24:49 PM PDT 24 Apr 23 02:24:55 PM PDT 24 867490502 ps
T1472 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.286754684 Apr 23 02:24:53 PM PDT 24 Apr 23 02:24:54 PM PDT 24 63240401 ps
T1473 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.780194819 Apr 23 02:24:58 PM PDT 24 Apr 23 02:24:59 PM PDT 24 30234557 ps
T1474 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2615867006 Apr 23 02:24:58 PM PDT 24 Apr 23 02:24:59 PM PDT 24 64383830 ps
T1475 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1980115178 Apr 23 02:25:08 PM PDT 24 Apr 23 02:25:10 PM PDT 24 33536297 ps
T1476 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1078434437 Apr 23 02:25:08 PM PDT 24 Apr 23 02:25:10 PM PDT 24 101446388 ps
T1477 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.823943436 Apr 23 02:24:52 PM PDT 24 Apr 23 02:24:53 PM PDT 24 39315020 ps
T1478 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2693804609 Apr 23 02:24:48 PM PDT 24 Apr 23 02:24:50 PM PDT 24 53523680 ps

Test location /workspace/coverage/default/24.max_length_in_transaction.1207049874
Short name T3
Test name
Test status
Simulation time 8482499790 ps
CPU time 8.62 seconds
Started Apr 23 02:37:07 PM PDT 24
Finished Apr 23 02:37:17 PM PDT 24
Peak memory 203968 kb
Host smart-a5580deb-5fea-4f54-a67b-b41f3ae83b1c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1207049874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.1207049874
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.127256251
Short name T13
Test name
Test status
Simulation time 22861593614 ps
CPU time 42.27 seconds
Started Apr 23 02:37:57 PM PDT 24
Finished Apr 23 02:38:41 PM PDT 24
Peak memory 204320 kb
Host smart-018955a5-b047-4c5d-9789-1936276bca12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12725
6251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.127256251
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2140938032
Short name T268
Test name
Test status
Simulation time 31464108 ps
CPU time 0.65 seconds
Started Apr 23 02:24:42 PM PDT 24
Finished Apr 23 02:24:43 PM PDT 24
Peak memory 202912 kb
Host smart-cb4d0551-201e-430c-acb2-236be8deb72f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2140938032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2140938032
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/default/41.usbdev_smoke.3509827758
Short name T19
Test name
Test status
Simulation time 8439297398 ps
CPU time 9.53 seconds
Started Apr 23 02:38:14 PM PDT 24
Finished Apr 23 02:38:24 PM PDT 24
Peak memory 204032 kb
Host smart-fa3617d4-5388-4062-9d5f-4a7723545637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35098
27758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3509827758
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.678975851
Short name T56
Test name
Test status
Simulation time 351543336 ps
CPU time 4.24 seconds
Started Apr 23 02:24:34 PM PDT 24
Finished Apr 23 02:24:39 PM PDT 24
Peak memory 203660 kb
Host smart-d622ca46-9cac-4842-b3df-ba3cf6b41cee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=678975851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.678975851
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1425694528
Short name T272
Test name
Test status
Simulation time 34923266 ps
CPU time 0.76 seconds
Started Apr 23 02:24:47 PM PDT 24
Finished Apr 23 02:24:48 PM PDT 24
Peak memory 203008 kb
Host smart-711996ac-4ff3-45d1-8318-c6502e102270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1425694528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1425694528
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.694745307
Short name T2
Test name
Test status
Simulation time 37794633 ps
CPU time 0.65 seconds
Started Apr 23 02:38:48 PM PDT 24
Finished Apr 23 02:38:50 PM PDT 24
Peak memory 203912 kb
Host smart-4165dc1f-aa7f-44cf-a421-5ea4a988785c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69474
5307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.694745307
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.64489299
Short name T38
Test name
Test status
Simulation time 8412469979 ps
CPU time 8.4 seconds
Started Apr 23 02:36:28 PM PDT 24
Finished Apr 23 02:36:37 PM PDT 24
Peak memory 204004 kb
Host smart-1bc73ef0-57a8-4d14-9bf5-888bc7c049f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64489
299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.64489299
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.49308493
Short name T58
Test name
Test status
Simulation time 615219411 ps
CPU time 1.37 seconds
Started Apr 23 02:35:11 PM PDT 24
Finished Apr 23 02:35:12 PM PDT 24
Peak memory 220216 kb
Host smart-16dbbc8e-2d32-4a89-a5b3-6331409536a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=49308493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.49308493
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.79943778
Short name T6
Test name
Test status
Simulation time 8371943013 ps
CPU time 8.29 seconds
Started Apr 23 02:36:02 PM PDT 24
Finished Apr 23 02:36:10 PM PDT 24
Peak memory 204076 kb
Host smart-c3f2f2ef-d7d9-42be-b1da-d9314053a900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79943
778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.79943778
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.3807107107
Short name T23
Test name
Test status
Simulation time 8374459896 ps
CPU time 8.35 seconds
Started Apr 23 02:36:16 PM PDT 24
Finished Apr 23 02:36:25 PM PDT 24
Peak memory 203968 kb
Host smart-4010414a-942e-4780-afc9-9713f5b1351d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38071
07107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.3807107107
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.40912024
Short name T233
Test name
Test status
Simulation time 96798728 ps
CPU time 1.42 seconds
Started Apr 23 02:24:53 PM PDT 24
Finished Apr 23 02:24:56 PM PDT 24
Peak memory 211952 kb
Host smart-65bff86e-b4fa-4f71-94b5-0233b6121d73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40912024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev
_csr_mem_rw_with_rand_reset.40912024
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.947278436
Short name T125
Test name
Test status
Simulation time 8403083028 ps
CPU time 9.67 seconds
Started Apr 23 02:34:58 PM PDT 24
Finished Apr 23 02:35:08 PM PDT 24
Peak memory 203956 kb
Host smart-e0b682e8-817b-470a-9afd-6fad3186721c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94727
8436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.947278436
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.787332291
Short name T71
Test name
Test status
Simulation time 46032650 ps
CPU time 0.66 seconds
Started Apr 23 02:25:11 PM PDT 24
Finished Apr 23 02:25:12 PM PDT 24
Peak memory 202916 kb
Host smart-0311a889-9a96-4cf9-9bea-e9f20fe35332
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=787332291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.787332291
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.432640599
Short name T211
Test name
Test status
Simulation time 203732839 ps
CPU time 1.75 seconds
Started Apr 23 02:37:45 PM PDT 24
Finished Apr 23 02:37:49 PM PDT 24
Peak memory 204100 kb
Host smart-b5b37ce6-0dea-469e-8784-842529c153bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43264
0599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.432640599
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3946205822
Short name T223
Test name
Test status
Simulation time 120542702 ps
CPU time 2.57 seconds
Started Apr 23 02:24:47 PM PDT 24
Finished Apr 23 02:24:50 PM PDT 24
Peak memory 203788 kb
Host smart-644c244e-88e9-4bf1-a8c2-a793aa8f96f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3946205822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3946205822
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.3285183267
Short name T39
Test name
Test status
Simulation time 8380928658 ps
CPU time 7.85 seconds
Started Apr 23 02:37:01 PM PDT 24
Finished Apr 23 02:37:10 PM PDT 24
Peak memory 204020 kb
Host smart-7ace2779-4d3b-4243-941e-bc462e9b2026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32851
83267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3285183267
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1464731234
Short name T64
Test name
Test status
Simulation time 76430275 ps
CPU time 1.01 seconds
Started Apr 23 02:24:47 PM PDT 24
Finished Apr 23 02:24:49 PM PDT 24
Peak memory 203604 kb
Host smart-9c444180-6602-48a1-a527-795769390bb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1464731234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1464731234
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1276519039
Short name T275
Test name
Test status
Simulation time 45470295 ps
CPU time 0.7 seconds
Started Apr 23 02:25:04 PM PDT 24
Finished Apr 23 02:25:06 PM PDT 24
Peak memory 202944 kb
Host smart-e76efc6b-9a99-40ae-9623-20cfd80f03a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1276519039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.1276519039
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3150932165
Short name T232
Test name
Test status
Simulation time 631606842 ps
CPU time 5.03 seconds
Started Apr 23 02:24:58 PM PDT 24
Finished Apr 23 02:25:03 PM PDT 24
Peak memory 203760 kb
Host smart-f9e34c22-1545-4a29-bb5f-c5870a26bcc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3150932165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3150932165
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2621640007
Short name T69
Test name
Test status
Simulation time 34642637 ps
CPU time 0.63 seconds
Started Apr 23 02:25:11 PM PDT 24
Finished Apr 23 02:25:13 PM PDT 24
Peak memory 202920 kb
Host smart-74296bdb-2390-497c-9e7c-fd0320d5b997
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2621640007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2621640007
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.686265879
Short name T305
Test name
Test status
Simulation time 8389310745 ps
CPU time 8.19 seconds
Started Apr 23 02:36:10 PM PDT 24
Finished Apr 23 02:36:19 PM PDT 24
Peak memory 204060 kb
Host smart-04dde54f-8426-490d-a05d-a79dc41747e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68626
5879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.686265879
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.72200818
Short name T98
Test name
Test status
Simulation time 5124152024 ps
CPU time 31.27 seconds
Started Apr 23 02:34:58 PM PDT 24
Finished Apr 23 02:35:31 PM PDT 24
Peak memory 204256 kb
Host smart-4a46f1d8-3bc0-4a79-bd0e-d331cea0a42c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72200
818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.72200818
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.1723978893
Short name T218
Test name
Test status
Simulation time 27218604930 ps
CPU time 58.47 seconds
Started Apr 23 02:36:20 PM PDT 24
Finished Apr 23 02:37:19 PM PDT 24
Peak memory 204320 kb
Host smart-84f7bb69-8f93-4d55-bc15-fa5a31bdc7a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17239
78893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.1723978893
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2301736205
Short name T208
Test name
Test status
Simulation time 489624276 ps
CPU time 2.71 seconds
Started Apr 23 02:24:54 PM PDT 24
Finished Apr 23 02:24:57 PM PDT 24
Peak memory 203680 kb
Host smart-408d0fb2-ee4b-4d25-8232-8449c19f5324
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2301736205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.2301736205
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.397762094
Short name T285
Test name
Test status
Simulation time 755623758 ps
CPU time 5.33 seconds
Started Apr 23 02:24:34 PM PDT 24
Finished Apr 23 02:24:40 PM PDT 24
Peak memory 203756 kb
Host smart-f21801ee-6c23-47ce-bd9c-1f74240e1f3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=397762094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.397762094
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1380918035
Short name T1398
Test name
Test status
Simulation time 43486388 ps
CPU time 0.66 seconds
Started Apr 23 02:24:47 PM PDT 24
Finished Apr 23 02:24:48 PM PDT 24
Peak memory 202976 kb
Host smart-8a9793e4-4f59-490f-a226-4898ba7234f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1380918035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1380918035
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3879612488
Short name T62
Test name
Test status
Simulation time 89776839 ps
CPU time 1.14 seconds
Started Apr 23 02:24:54 PM PDT 24
Finished Apr 23 02:24:56 PM PDT 24
Peak memory 203776 kb
Host smart-bc6a9732-b154-47d7-ad13-5d3c31805617
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3879612488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.3879612488
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.2244560703
Short name T1332
Test name
Test status
Simulation time 8401021188 ps
CPU time 7.96 seconds
Started Apr 23 02:35:11 PM PDT 24
Finished Apr 23 02:35:20 PM PDT 24
Peak memory 204032 kb
Host smart-007097a3-6f6f-4ed8-85bc-3d850479d982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22445
60703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.2244560703
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.84638988
Short name T632
Test name
Test status
Simulation time 8382829979 ps
CPU time 8.53 seconds
Started Apr 23 02:35:56 PM PDT 24
Finished Apr 23 02:36:05 PM PDT 24
Peak memory 203968 kb
Host smart-8ea7be03-7d21-40dc-b25c-5961d058236a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84638
988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.84638988
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.504301722
Short name T964
Test name
Test status
Simulation time 8376923984 ps
CPU time 8.32 seconds
Started Apr 23 02:36:06 PM PDT 24
Finished Apr 23 02:36:15 PM PDT 24
Peak memory 204016 kb
Host smart-ebe8692f-de22-48a7-a978-6a5b64efc337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50430
1722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.504301722
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_smoke.3154469200
Short name T20
Test name
Test status
Simulation time 8440520144 ps
CPU time 8.03 seconds
Started Apr 23 02:36:08 PM PDT 24
Finished Apr 23 02:36:17 PM PDT 24
Peak memory 204016 kb
Host smart-0e655c89-ca25-44cf-af21-b14d26e6f6f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31544
69200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.3154469200
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.2591077014
Short name T179
Test name
Test status
Simulation time 8408248030 ps
CPU time 8.79 seconds
Started Apr 23 02:36:16 PM PDT 24
Finished Apr 23 02:36:26 PM PDT 24
Peak memory 204044 kb
Host smart-66b15594-6811-4d1c-b09f-406f8f91c804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25910
77014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.2591077014
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3119540532
Short name T461
Test name
Test status
Simulation time 8455908185 ps
CPU time 7.62 seconds
Started Apr 23 02:36:16 PM PDT 24
Finished Apr 23 02:36:24 PM PDT 24
Peak memory 204028 kb
Host smart-41bdc556-6ec9-47cd-adcb-3536dd0ba5aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31195
40532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3119540532
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.2566476840
Short name T191
Test name
Test status
Simulation time 8411951820 ps
CPU time 7.82 seconds
Started Apr 23 02:36:28 PM PDT 24
Finished Apr 23 02:36:36 PM PDT 24
Peak memory 203968 kb
Host smart-7c8be7b5-9174-4f50-9cac-19d81d117de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25664
76840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.2566476840
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.2796771669
Short name T526
Test name
Test status
Simulation time 8385634688 ps
CPU time 8.13 seconds
Started Apr 23 02:36:36 PM PDT 24
Finished Apr 23 02:36:45 PM PDT 24
Peak memory 204028 kb
Host smart-4308bd03-c8fe-441e-a564-2a1c1955dd3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27967
71669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.2796771669
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.3900015023
Short name T438
Test name
Test status
Simulation time 64677565 ps
CPU time 0.68 seconds
Started Apr 23 02:35:18 PM PDT 24
Finished Apr 23 02:35:19 PM PDT 24
Peak memory 203824 kb
Host smart-82a62e2b-2864-41cf-b90c-d4d9b1cc034a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39000
15023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.3900015023
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_smoke.4275941837
Short name T185
Test name
Test status
Simulation time 8419303999 ps
CPU time 7.81 seconds
Started Apr 23 02:35:13 PM PDT 24
Finished Apr 23 02:35:21 PM PDT 24
Peak memory 204032 kb
Host smart-ab058f68-a426-453d-bd7c-3f7f8ace2ef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42759
41837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.4275941837
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.258533413
Short name T638
Test name
Test status
Simulation time 8398951641 ps
CPU time 7.92 seconds
Started Apr 23 02:37:04 PM PDT 24
Finished Apr 23 02:37:13 PM PDT 24
Peak memory 203976 kb
Host smart-209e4508-befc-480c-9750-0c5df326ba95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25853
3413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.258533413
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.3090829917
Short name T297
Test name
Test status
Simulation time 8409056535 ps
CPU time 8.31 seconds
Started Apr 23 02:35:02 PM PDT 24
Finished Apr 23 02:35:11 PM PDT 24
Peak memory 204004 kb
Host smart-7c5b8efd-58f6-45c6-a64b-ce66294f3c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30908
29917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3090829917
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.488115732
Short name T70
Test name
Test status
Simulation time 82614885 ps
CPU time 0.76 seconds
Started Apr 23 02:24:33 PM PDT 24
Finished Apr 23 02:24:35 PM PDT 24
Peak memory 203368 kb
Host smart-f7b86bb6-6ff3-4620-9eab-e91a36c94629
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=488115732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.488115732
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.2815083221
Short name T26
Test name
Test status
Simulation time 8379561380 ps
CPU time 8.06 seconds
Started Apr 23 02:36:44 PM PDT 24
Finished Apr 23 02:36:52 PM PDT 24
Peak memory 204012 kb
Host smart-d212eec3-59a2-4b97-933c-0dcbe227fa41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28150
83221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.2815083221
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.583246267
Short name T688
Test name
Test status
Simulation time 8380702523 ps
CPU time 7.8 seconds
Started Apr 23 02:35:11 PM PDT 24
Finished Apr 23 02:35:20 PM PDT 24
Peak memory 204008 kb
Host smart-0a68fd54-29f0-411b-b308-c0a5a1bff200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58324
6267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.583246267
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.3150110872
Short name T905
Test name
Test status
Simulation time 29005491196 ps
CPU time 58.09 seconds
Started Apr 23 02:35:02 PM PDT 24
Finished Apr 23 02:36:01 PM PDT 24
Peak memory 204360 kb
Host smart-0bae968d-b119-438c-a2ac-34c5f1be5e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31501
10872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.3150110872
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.3753445888
Short name T617
Test name
Test status
Simulation time 8406314787 ps
CPU time 7.8 seconds
Started Apr 23 02:35:03 PM PDT 24
Finished Apr 23 02:35:12 PM PDT 24
Peak memory 203984 kb
Host smart-354d60e5-ebf6-4919-82da-4138c733bad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37534
45888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.3753445888
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.1192425148
Short name T716
Test name
Test status
Simulation time 8454388244 ps
CPU time 7.86 seconds
Started Apr 23 02:35:11 PM PDT 24
Finished Apr 23 02:35:19 PM PDT 24
Peak memory 204060 kb
Host smart-64386673-cb1a-4c9c-a4a2-544b820bc73c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11924
25148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.1192425148
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.3736154046
Short name T1212
Test name
Test status
Simulation time 8411900510 ps
CPU time 8.41 seconds
Started Apr 23 02:35:12 PM PDT 24
Finished Apr 23 02:35:21 PM PDT 24
Peak memory 204012 kb
Host smart-226ddc64-03a9-4d22-82f5-013c3535fac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37361
54046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.3736154046
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.4001996582
Short name T186
Test name
Test status
Simulation time 8363607540 ps
CPU time 9.5 seconds
Started Apr 23 02:35:58 PM PDT 24
Finished Apr 23 02:36:08 PM PDT 24
Peak memory 204028 kb
Host smart-f7b0f961-b049-4fcf-bee4-912ae1046139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40019
96582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.4001996582
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.2879699230
Short name T80
Test name
Test status
Simulation time 8387597886 ps
CPU time 8.44 seconds
Started Apr 23 02:35:59 PM PDT 24
Finished Apr 23 02:36:08 PM PDT 24
Peak memory 204032 kb
Host smart-7c373291-6b7e-4559-a80a-62929dea5106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28796
99230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2879699230
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.2823395541
Short name T25
Test name
Test status
Simulation time 8368954760 ps
CPU time 8.34 seconds
Started Apr 23 02:35:57 PM PDT 24
Finished Apr 23 02:36:06 PM PDT 24
Peak memory 204056 kb
Host smart-39e528ae-8a96-41fc-923f-778633195cef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28233
95541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.2823395541
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.3823442177
Short name T108
Test name
Test status
Simulation time 8426481332 ps
CPU time 9.23 seconds
Started Apr 23 02:35:58 PM PDT 24
Finished Apr 23 02:36:08 PM PDT 24
Peak memory 203956 kb
Host smart-c76a5411-cce5-4093-a1fb-425190be14d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38234
42177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.3823442177
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.216988884
Short name T151
Test name
Test status
Simulation time 8450514740 ps
CPU time 8.02 seconds
Started Apr 23 02:36:03 PM PDT 24
Finished Apr 23 02:36:12 PM PDT 24
Peak memory 204048 kb
Host smart-f2bc5fa8-223a-46a4-b872-8e902a6e3360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21698
8884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.216988884
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.2105257987
Short name T99
Test name
Test status
Simulation time 8400661586 ps
CPU time 8.15 seconds
Started Apr 23 02:36:04 PM PDT 24
Finished Apr 23 02:36:13 PM PDT 24
Peak memory 204008 kb
Host smart-99dbf989-9e77-4bf6-b284-31f7f8244d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21052
57987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.2105257987
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.1308526058
Short name T146
Test name
Test status
Simulation time 8473982389 ps
CPU time 7.92 seconds
Started Apr 23 02:36:04 PM PDT 24
Finished Apr 23 02:36:12 PM PDT 24
Peak memory 204016 kb
Host smart-10635113-879c-4dda-9a6e-80dbd39ffd7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13085
26058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.1308526058
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.1627714994
Short name T104
Test name
Test status
Simulation time 8407818748 ps
CPU time 7.86 seconds
Started Apr 23 02:36:10 PM PDT 24
Finished Apr 23 02:36:18 PM PDT 24
Peak memory 204060 kb
Host smart-d383001e-a373-4a6b-a60d-e51bc6fe015c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16277
14994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.1627714994
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.725339060
Short name T116
Test name
Test status
Simulation time 8422055750 ps
CPU time 10.09 seconds
Started Apr 23 02:36:16 PM PDT 24
Finished Apr 23 02:36:27 PM PDT 24
Peak memory 204020 kb
Host smart-661da53e-cb74-453b-9454-5ff24d55c5df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72533
9060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.725339060
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.1407700666
Short name T605
Test name
Test status
Simulation time 8442799404 ps
CPU time 8.34 seconds
Started Apr 23 02:36:22 PM PDT 24
Finished Apr 23 02:36:31 PM PDT 24
Peak memory 204060 kb
Host smart-9cd8a3ed-7d00-4539-899d-d51ac6186f0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14077
00666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.1407700666
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.876774380
Short name T115
Test name
Test status
Simulation time 8386790193 ps
CPU time 7.5 seconds
Started Apr 23 02:36:24 PM PDT 24
Finished Apr 23 02:36:32 PM PDT 24
Peak memory 204008 kb
Host smart-bcb84b6b-d2fd-4831-a12f-fb688fd69a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87677
4380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.876774380
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.2912639200
Short name T1022
Test name
Test status
Simulation time 8436840752 ps
CPU time 7.73 seconds
Started Apr 23 02:36:35 PM PDT 24
Finished Apr 23 02:36:44 PM PDT 24
Peak memory 204004 kb
Host smart-6c76d3d5-9824-458b-8b32-a6ef538049e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29126
39200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2912639200
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.1072804207
Short name T933
Test name
Test status
Simulation time 8395363098 ps
CPU time 8.2 seconds
Started Apr 23 02:36:36 PM PDT 24
Finished Apr 23 02:36:45 PM PDT 24
Peak memory 203980 kb
Host smart-21c8f163-c90b-40ff-9184-8e6b1b3bd469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10728
04207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.1072804207
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.969843844
Short name T163
Test name
Test status
Simulation time 8392899642 ps
CPU time 8.12 seconds
Started Apr 23 02:36:42 PM PDT 24
Finished Apr 23 02:36:50 PM PDT 24
Peak memory 203984 kb
Host smart-7d602f80-6bbc-4c08-8730-017d93a9c0c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96984
3844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.969843844
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.2670699552
Short name T109
Test name
Test status
Simulation time 8400248255 ps
CPU time 7.94 seconds
Started Apr 23 02:36:54 PM PDT 24
Finished Apr 23 02:37:03 PM PDT 24
Peak memory 204000 kb
Host smart-2af1a463-1bde-4748-95d0-36b6305214bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26706
99552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.2670699552
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.2040799354
Short name T111
Test name
Test status
Simulation time 8446248581 ps
CPU time 8.42 seconds
Started Apr 23 02:36:54 PM PDT 24
Finished Apr 23 02:37:04 PM PDT 24
Peak memory 203996 kb
Host smart-7ee690c3-2d11-453a-a4f5-29020cccca28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20407
99354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2040799354
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.3763093754
Short name T97
Test name
Test status
Simulation time 8490770008 ps
CPU time 9.46 seconds
Started Apr 23 02:37:01 PM PDT 24
Finished Apr 23 02:37:11 PM PDT 24
Peak memory 204032 kb
Host smart-ea7ea7b8-d201-4ffc-aab0-ab7ab07a3b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37630
93754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.3763093754
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.621006044
Short name T1453
Test name
Test status
Simulation time 172729881 ps
CPU time 2.08 seconds
Started Apr 23 02:24:33 PM PDT 24
Finished Apr 23 02:24:36 PM PDT 24
Peak memory 203724 kb
Host smart-6fb3688b-eea1-4b38-a3f8-8c0262801eb3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=621006044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.621006044
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3304435676
Short name T1464
Test name
Test status
Simulation time 1302143385 ps
CPU time 8.46 seconds
Started Apr 23 02:24:33 PM PDT 24
Finished Apr 23 02:24:42 PM PDT 24
Peak memory 203680 kb
Host smart-04af2893-2880-47da-a4d1-e8fab70b83c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3304435676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.3304435676
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1551346169
Short name T1381
Test name
Test status
Simulation time 124038890 ps
CPU time 1.18 seconds
Started Apr 23 02:24:30 PM PDT 24
Finished Apr 23 02:24:31 PM PDT 24
Peak memory 212100 kb
Host smart-33870941-cc81-4216-b4f9-e8bd42863a39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551346169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.1551346169
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1862368320
Short name T254
Test name
Test status
Simulation time 84697712 ps
CPU time 1.02 seconds
Started Apr 23 02:24:30 PM PDT 24
Finished Apr 23 02:24:32 PM PDT 24
Peak memory 203708 kb
Host smart-6dcc1a8e-fe43-40fd-b78f-77f4654aa3c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1862368320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1862368320
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.662148359
Short name T1402
Test name
Test status
Simulation time 56848927 ps
CPU time 0.66 seconds
Started Apr 23 02:24:29 PM PDT 24
Finished Apr 23 02:24:31 PM PDT 24
Peak memory 202856 kb
Host smart-5410ac78-a9d8-4a28-89e8-267a5606dc6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=662148359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.662148359
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3080882430
Short name T1468
Test name
Test status
Simulation time 107520215 ps
CPU time 1.45 seconds
Started Apr 23 02:24:32 PM PDT 24
Finished Apr 23 02:24:33 PM PDT 24
Peak memory 203800 kb
Host smart-3ff432c9-383e-482b-8983-8b85e5e8b57e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3080882430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3080882430
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.617405139
Short name T1380
Test name
Test status
Simulation time 314678241 ps
CPU time 2.48 seconds
Started Apr 23 02:24:32 PM PDT 24
Finished Apr 23 02:24:35 PM PDT 24
Peak memory 203648 kb
Host smart-2f4df160-a5ad-4635-ba52-d351e04cf647
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=617405139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.617405139
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2588618043
Short name T1410
Test name
Test status
Simulation time 81394503 ps
CPU time 1.14 seconds
Started Apr 23 02:24:31 PM PDT 24
Finished Apr 23 02:24:33 PM PDT 24
Peak memory 203664 kb
Host smart-d6fc0a89-80b6-49fb-8277-1f8cf9f68e7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2588618043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.2588618043
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1803934224
Short name T1459
Test name
Test status
Simulation time 146057060 ps
CPU time 2.04 seconds
Started Apr 23 02:24:32 PM PDT 24
Finished Apr 23 02:24:34 PM PDT 24
Peak memory 203652 kb
Host smart-772e4e4d-af0e-4694-a2ba-427c5413c6b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1803934224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1803934224
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3304231577
Short name T1430
Test name
Test status
Simulation time 344811209 ps
CPU time 2.77 seconds
Started Apr 23 02:24:30 PM PDT 24
Finished Apr 23 02:24:33 PM PDT 24
Peak memory 203748 kb
Host smart-b53820cc-6ef4-4edc-aae3-79438df7150c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3304231577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.3304231577
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.981406115
Short name T1405
Test name
Test status
Simulation time 291742218 ps
CPU time 3.74 seconds
Started Apr 23 02:24:33 PM PDT 24
Finished Apr 23 02:24:38 PM PDT 24
Peak memory 203652 kb
Host smart-e30450f5-a29c-447e-9f8c-0002d00571ee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=981406115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.981406115
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2129697504
Short name T1392
Test name
Test status
Simulation time 733756769 ps
CPU time 4.45 seconds
Started Apr 23 02:24:34 PM PDT 24
Finished Apr 23 02:24:39 PM PDT 24
Peak memory 203616 kb
Host smart-3e66afa3-f2d5-4dbc-8b6f-cc88f6629de0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2129697504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.2129697504
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1074893709
Short name T1446
Test name
Test status
Simulation time 37604014 ps
CPU time 0.75 seconds
Started Apr 23 02:24:33 PM PDT 24
Finished Apr 23 02:24:35 PM PDT 24
Peak memory 203396 kb
Host smart-5628c279-54fa-4bb4-82f1-25739343f6cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1074893709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.1074893709
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2039857996
Short name T237
Test name
Test status
Simulation time 135129946 ps
CPU time 1.74 seconds
Started Apr 23 02:24:34 PM PDT 24
Finished Apr 23 02:24:37 PM PDT 24
Peak memory 211904 kb
Host smart-b0cf162e-60f4-49a3-ba83-2cbe169730e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039857996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.2039857996
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.337825140
Short name T257
Test name
Test status
Simulation time 60796454 ps
CPU time 1.04 seconds
Started Apr 23 02:24:34 PM PDT 24
Finished Apr 23 02:24:36 PM PDT 24
Peak memory 203684 kb
Host smart-ba08f088-e013-4358-bafd-8900894a3257
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=337825140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.337825140
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2257650019
Short name T1458
Test name
Test status
Simulation time 24936655 ps
CPU time 0.62 seconds
Started Apr 23 02:24:35 PM PDT 24
Finished Apr 23 02:24:36 PM PDT 24
Peak memory 202932 kb
Host smart-2f7f2f9c-155f-4006-9b64-ab152de72b55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2257650019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2257650019
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3363467600
Short name T1420
Test name
Test status
Simulation time 156770003 ps
CPU time 1.42 seconds
Started Apr 23 02:24:32 PM PDT 24
Finished Apr 23 02:24:34 PM PDT 24
Peak memory 203700 kb
Host smart-f706c96a-e4ee-4a7d-954b-511fddbcf4ac
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3363467600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.3363467600
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2903857937
Short name T1462
Test name
Test status
Simulation time 482310719 ps
CPU time 4.5 seconds
Started Apr 23 02:24:34 PM PDT 24
Finished Apr 23 02:24:39 PM PDT 24
Peak memory 203540 kb
Host smart-4a7903f8-87a5-4e21-9b6c-889fc438df8c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2903857937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2903857937
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4284002193
Short name T1383
Test name
Test status
Simulation time 125441139 ps
CPU time 1.07 seconds
Started Apr 23 02:24:32 PM PDT 24
Finished Apr 23 02:24:34 PM PDT 24
Peak memory 203740 kb
Host smart-a6f5a479-4847-479e-bf9a-ca618ef1616b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4284002193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.4284002193
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.632233789
Short name T1406
Test name
Test status
Simulation time 153063098 ps
CPU time 1.74 seconds
Started Apr 23 02:24:33 PM PDT 24
Finished Apr 23 02:24:35 PM PDT 24
Peak memory 203816 kb
Host smart-9b3a43bd-0d59-4172-94e1-32debe73d16e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=632233789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.632233789
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2856004034
Short name T207
Test name
Test status
Simulation time 189183517 ps
CPU time 2.32 seconds
Started Apr 23 02:24:49 PM PDT 24
Finished Apr 23 02:24:52 PM PDT 24
Peak memory 211976 kb
Host smart-c0a98c6f-a6c8-4870-b548-871e646f76b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856004034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.2856004034
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.286754684
Short name T1472
Test name
Test status
Simulation time 63240401 ps
CPU time 0.92 seconds
Started Apr 23 02:24:53 PM PDT 24
Finished Apr 23 02:24:54 PM PDT 24
Peak memory 203708 kb
Host smart-c3f0607d-b46b-4509-8574-f4787856b951
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=286754684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.286754684
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2214765801
Short name T1442
Test name
Test status
Simulation time 28134952 ps
CPU time 0.62 seconds
Started Apr 23 02:24:48 PM PDT 24
Finished Apr 23 02:24:49 PM PDT 24
Peak memory 202980 kb
Host smart-9a5d8225-d5ed-492a-a655-15baac80541a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2214765801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2214765801
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.4094413058
Short name T1437
Test name
Test status
Simulation time 87913018 ps
CPU time 1.51 seconds
Started Apr 23 02:24:51 PM PDT 24
Finished Apr 23 02:24:53 PM PDT 24
Peak memory 203716 kb
Host smart-5ed66cbe-4903-4f05-9b1b-81e31f22c8df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4094413058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.4094413058
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1352268504
Short name T286
Test name
Test status
Simulation time 265868685 ps
CPU time 2.61 seconds
Started Apr 23 02:24:53 PM PDT 24
Finished Apr 23 02:24:57 PM PDT 24
Peak memory 203764 kb
Host smart-60c1169b-885f-42ee-bf49-8fa7e7722909
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1352268504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1352268504
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.4017826802
Short name T1454
Test name
Test status
Simulation time 74896791 ps
CPU time 2.26 seconds
Started Apr 23 02:24:51 PM PDT 24
Finished Apr 23 02:24:54 PM PDT 24
Peak memory 220232 kb
Host smart-5233cf76-d865-43a4-8f0f-64562c83e32d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017826802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.4017826802
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2829463514
Short name T1419
Test name
Test status
Simulation time 71710157 ps
CPU time 0.94 seconds
Started Apr 23 02:24:48 PM PDT 24
Finished Apr 23 02:24:50 PM PDT 24
Peak memory 203336 kb
Host smart-c3f48aca-f3d7-4f29-85f0-9cdbb1da7fd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2829463514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2829463514
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3864764581
Short name T1379
Test name
Test status
Simulation time 210601760 ps
CPU time 1.53 seconds
Started Apr 23 02:24:50 PM PDT 24
Finished Apr 23 02:24:53 PM PDT 24
Peak memory 203776 kb
Host smart-ab8221b7-ce07-4200-9747-f9792f53a913
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3864764581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3864764581
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.497947536
Short name T1444
Test name
Test status
Simulation time 204445537 ps
CPU time 2.69 seconds
Started Apr 23 02:24:50 PM PDT 24
Finished Apr 23 02:24:53 PM PDT 24
Peak memory 203824 kb
Host smart-38b4c6f7-00cf-44ea-b2dc-eb024452c107
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=497947536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.497947536
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2119456448
Short name T1471
Test name
Test status
Simulation time 867490502 ps
CPU time 5.29 seconds
Started Apr 23 02:24:49 PM PDT 24
Finished Apr 23 02:24:55 PM PDT 24
Peak memory 203752 kb
Host smart-050a824f-253f-4698-b9d4-7c067eec3d02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2119456448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.2119456448
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2482824200
Short name T1426
Test name
Test status
Simulation time 140128543 ps
CPU time 1.82 seconds
Started Apr 23 02:24:50 PM PDT 24
Finished Apr 23 02:24:52 PM PDT 24
Peak memory 212048 kb
Host smart-f1529001-5608-465d-b8ab-a38df700bb2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482824200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.2482824200
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1231248704
Short name T1424
Test name
Test status
Simulation time 53820853 ps
CPU time 0.84 seconds
Started Apr 23 02:24:50 PM PDT 24
Finished Apr 23 02:24:51 PM PDT 24
Peak memory 203380 kb
Host smart-18461986-b7dc-4707-8a73-6c32f8a9d99a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1231248704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1231248704
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.823943436
Short name T1477
Test name
Test status
Simulation time 39315020 ps
CPU time 0.67 seconds
Started Apr 23 02:24:52 PM PDT 24
Finished Apr 23 02:24:53 PM PDT 24
Peak memory 203004 kb
Host smart-d8104fe6-8a7f-40cc-b755-ada339538d5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=823943436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.823943436
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3177644513
Short name T1455
Test name
Test status
Simulation time 75999141 ps
CPU time 1.06 seconds
Started Apr 23 02:24:54 PM PDT 24
Finished Apr 23 02:24:55 PM PDT 24
Peak memory 203712 kb
Host smart-be8dee70-ed3c-4e24-987e-a03576c31e4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3177644513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3177644513
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2694385326
Short name T1429
Test name
Test status
Simulation time 198055808 ps
CPU time 2.12 seconds
Started Apr 23 02:24:50 PM PDT 24
Finished Apr 23 02:24:53 PM PDT 24
Peak memory 203828 kb
Host smart-fc5bc777-dee6-4d5b-b1c7-dd350dd8cff9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2694385326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2694385326
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3704887929
Short name T280
Test name
Test status
Simulation time 830741018 ps
CPU time 4.85 seconds
Started Apr 23 02:24:49 PM PDT 24
Finished Apr 23 02:24:55 PM PDT 24
Peak memory 203772 kb
Host smart-63993ef7-bd31-4dcb-8039-8600238a1e3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3704887929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.3704887929
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1121312152
Short name T1385
Test name
Test status
Simulation time 85807255 ps
CPU time 1.19 seconds
Started Apr 23 02:24:50 PM PDT 24
Finished Apr 23 02:24:52 PM PDT 24
Peak memory 211916 kb
Host smart-2f99fc02-acb4-4d21-8f4f-c4fdf03bc920
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121312152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1121312152
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.105662571
Short name T1450
Test name
Test status
Simulation time 110300174 ps
CPU time 1.04 seconds
Started Apr 23 02:24:53 PM PDT 24
Finished Apr 23 02:24:54 PM PDT 24
Peak memory 203708 kb
Host smart-b76d7d3b-97e9-488b-94c6-6d48304a3993
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=105662571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.105662571
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3309043162
Short name T1433
Test name
Test status
Simulation time 63475724 ps
CPU time 0.68 seconds
Started Apr 23 02:24:54 PM PDT 24
Finished Apr 23 02:24:55 PM PDT 24
Peak memory 202908 kb
Host smart-8ecd5cd6-975c-443a-be29-686c3ae9816f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3309043162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3309043162
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3435935029
Short name T1387
Test name
Test status
Simulation time 158011158 ps
CPU time 1.55 seconds
Started Apr 23 02:24:50 PM PDT 24
Finished Apr 23 02:24:52 PM PDT 24
Peak memory 203756 kb
Host smart-c453ed68-8906-46df-8a36-1bae7b260c4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3435935029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.3435935029
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4058124728
Short name T1395
Test name
Test status
Simulation time 189091411 ps
CPU time 2.53 seconds
Started Apr 23 02:24:50 PM PDT 24
Finished Apr 23 02:24:54 PM PDT 24
Peak memory 203808 kb
Host smart-ad9bb9f9-6f7a-455d-bc64-384b21abf505
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4058124728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.4058124728
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1531539112
Short name T255
Test name
Test status
Simulation time 71909349 ps
CPU time 1 seconds
Started Apr 23 02:24:57 PM PDT 24
Finished Apr 23 02:24:58 PM PDT 24
Peak memory 203708 kb
Host smart-b3f56a91-00de-41f9-84e8-a7149fd584b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1531539112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1531539112
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1066329911
Short name T279
Test name
Test status
Simulation time 38436891 ps
CPU time 0.68 seconds
Started Apr 23 02:24:56 PM PDT 24
Finished Apr 23 02:24:57 PM PDT 24
Peak memory 202980 kb
Host smart-ae1060c6-1c23-403f-a14b-c908e92baccb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1066329911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1066329911
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.4111939016
Short name T224
Test name
Test status
Simulation time 152586642 ps
CPU time 1.99 seconds
Started Apr 23 02:24:54 PM PDT 24
Finished Apr 23 02:24:56 PM PDT 24
Peak memory 203888 kb
Host smart-a237a4bb-f1c1-47f0-9287-1032015db87a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4111939016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.4111939016
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1143654035
Short name T284
Test name
Test status
Simulation time 1347283723 ps
CPU time 5.14 seconds
Started Apr 23 02:24:55 PM PDT 24
Finished Apr 23 02:25:01 PM PDT 24
Peak memory 203872 kb
Host smart-7cd275ad-5362-4a07-9d94-c9a5d0725d13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1143654035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1143654035
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.989156132
Short name T1382
Test name
Test status
Simulation time 54420880 ps
CPU time 1.55 seconds
Started Apr 23 02:24:54 PM PDT 24
Finished Apr 23 02:24:56 PM PDT 24
Peak memory 211996 kb
Host smart-1c277502-ffed-4172-914c-31de85155a89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989156132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.989156132
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2118941598
Short name T1439
Test name
Test status
Simulation time 102708889 ps
CPU time 0.88 seconds
Started Apr 23 02:24:55 PM PDT 24
Finished Apr 23 02:24:56 PM PDT 24
Peak memory 203392 kb
Host smart-b5095c26-2e43-4336-8dd2-d98394ad2d33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2118941598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2118941598
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.780194819
Short name T1473
Test name
Test status
Simulation time 30234557 ps
CPU time 0.69 seconds
Started Apr 23 02:24:58 PM PDT 24
Finished Apr 23 02:24:59 PM PDT 24
Peak memory 202884 kb
Host smart-d326b42e-8745-460b-b5d8-bff774ad3dd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=780194819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.780194819
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.4128966677
Short name T1432
Test name
Test status
Simulation time 63681322 ps
CPU time 1.08 seconds
Started Apr 23 02:24:55 PM PDT 24
Finished Apr 23 02:24:57 PM PDT 24
Peak memory 203744 kb
Host smart-fe4b919b-f640-4388-8e77-1c59e3a96f26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4128966677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.4128966677
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2037631799
Short name T229
Test name
Test status
Simulation time 87861121 ps
CPU time 2.27 seconds
Started Apr 23 02:24:53 PM PDT 24
Finished Apr 23 02:24:56 PM PDT 24
Peak memory 203716 kb
Host smart-1fc8125f-e597-4aba-b55c-12b017795f93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2037631799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2037631799
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3876097029
Short name T209
Test name
Test status
Simulation time 407811704 ps
CPU time 2.83 seconds
Started Apr 23 02:24:55 PM PDT 24
Finished Apr 23 02:24:58 PM PDT 24
Peak memory 203780 kb
Host smart-5a2667e2-1ea8-423e-aaf1-8d12f00c0a2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3876097029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.3876097029
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3923698693
Short name T1422
Test name
Test status
Simulation time 148995098 ps
CPU time 1.72 seconds
Started Apr 23 02:24:59 PM PDT 24
Finished Apr 23 02:25:01 PM PDT 24
Peak memory 212016 kb
Host smart-e794d83b-1c54-42bd-8b0f-e435e07bd010
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923698693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.3923698693
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.766258604
Short name T93
Test name
Test status
Simulation time 112923347 ps
CPU time 0.98 seconds
Started Apr 23 02:24:57 PM PDT 24
Finished Apr 23 02:24:59 PM PDT 24
Peak memory 203484 kb
Host smart-cdce01a3-3992-4348-8288-65011122f7d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=766258604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.766258604
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1606341426
Short name T274
Test name
Test status
Simulation time 36666061 ps
CPU time 0.69 seconds
Started Apr 23 02:24:54 PM PDT 24
Finished Apr 23 02:24:56 PM PDT 24
Peak memory 203028 kb
Host smart-943d803a-7728-431a-b047-c37c289db6d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1606341426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1606341426
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3250036740
Short name T92
Test name
Test status
Simulation time 94099770 ps
CPU time 1.12 seconds
Started Apr 23 02:24:59 PM PDT 24
Finished Apr 23 02:25:00 PM PDT 24
Peak memory 203772 kb
Host smart-4dbb1ad0-3395-4b9f-bb42-58430806ce36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3250036740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3250036740
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3769885750
Short name T205
Test name
Test status
Simulation time 212870276 ps
CPU time 2.35 seconds
Started Apr 23 02:24:56 PM PDT 24
Finished Apr 23 02:24:59 PM PDT 24
Peak memory 212008 kb
Host smart-a4872549-4f2e-456d-8478-1af9ac9a4f86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3769885750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3769885750
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3372932025
Short name T1460
Test name
Test status
Simulation time 118783781 ps
CPU time 1.35 seconds
Started Apr 23 02:24:57 PM PDT 24
Finished Apr 23 02:24:59 PM PDT 24
Peak memory 211964 kb
Host smart-8994dbc4-6446-48b4-ab90-ad0521d7bd66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372932025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.3372932025
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1486472168
Short name T1470
Test name
Test status
Simulation time 53372894 ps
CPU time 0.82 seconds
Started Apr 23 02:24:54 PM PDT 24
Finished Apr 23 02:24:55 PM PDT 24
Peak memory 203408 kb
Host smart-11aba86d-6376-4766-aed6-ed09d0490190
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1486472168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.1486472168
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3690783225
Short name T1456
Test name
Test status
Simulation time 35881813 ps
CPU time 0.65 seconds
Started Apr 23 02:24:57 PM PDT 24
Finished Apr 23 02:24:58 PM PDT 24
Peak memory 202900 kb
Host smart-ae0c7a9e-8e38-4b6a-a627-72e4713186ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3690783225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.3690783225
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.723871032
Short name T1418
Test name
Test status
Simulation time 196405843 ps
CPU time 1.61 seconds
Started Apr 23 02:24:59 PM PDT 24
Finished Apr 23 02:25:01 PM PDT 24
Peak memory 203712 kb
Host smart-95b344c0-7b53-48f8-831f-d096149171f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=723871032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.723871032
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2684611617
Short name T1407
Test name
Test status
Simulation time 102919254 ps
CPU time 2.46 seconds
Started Apr 23 02:24:57 PM PDT 24
Finished Apr 23 02:25:00 PM PDT 24
Peak memory 203676 kb
Host smart-23d94287-c926-4dc9-b2f3-5de7b79d798a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2684611617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2684611617
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3171654055
Short name T281
Test name
Test status
Simulation time 305837837 ps
CPU time 2.52 seconds
Started Apr 23 02:24:58 PM PDT 24
Finished Apr 23 02:25:01 PM PDT 24
Peak memory 203808 kb
Host smart-7f7b5d76-a26e-47e6-b78b-8f23124c9a4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3171654055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3171654055
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2893152297
Short name T1423
Test name
Test status
Simulation time 198328862 ps
CPU time 1.53 seconds
Started Apr 23 02:25:00 PM PDT 24
Finished Apr 23 02:25:02 PM PDT 24
Peak memory 213000 kb
Host smart-55e24a82-af00-4543-9c33-bc5dc16b9354
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893152297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2893152297
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2615867006
Short name T1474
Test name
Test status
Simulation time 64383830 ps
CPU time 1.04 seconds
Started Apr 23 02:24:58 PM PDT 24
Finished Apr 23 02:24:59 PM PDT 24
Peak memory 203680 kb
Host smart-f94f003c-d01f-4b62-819c-6470b7be72da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2615867006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2615867006
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3989590320
Short name T67
Test name
Test status
Simulation time 41320097 ps
CPU time 0.69 seconds
Started Apr 23 02:24:59 PM PDT 24
Finished Apr 23 02:25:00 PM PDT 24
Peak memory 202944 kb
Host smart-87d144ca-cd51-4bd5-9b1c-4e92dc12a550
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3989590320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.3989590320
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3707397579
Short name T262
Test name
Test status
Simulation time 94921051 ps
CPU time 1.09 seconds
Started Apr 23 02:24:57 PM PDT 24
Finished Apr 23 02:24:58 PM PDT 24
Peak memory 203744 kb
Host smart-077b7bb1-6240-438e-84b5-c5c3193e7ff4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3707397579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3707397579
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.990719077
Short name T210
Test name
Test status
Simulation time 116595295 ps
CPU time 1.63 seconds
Started Apr 23 02:24:58 PM PDT 24
Finished Apr 23 02:25:00 PM PDT 24
Peak memory 203744 kb
Host smart-526fa75a-d880-4909-a8db-47392663d5ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=990719077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.990719077
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1499525305
Short name T55
Test name
Test status
Simulation time 844684145 ps
CPU time 4.9 seconds
Started Apr 23 02:24:58 PM PDT 24
Finished Apr 23 02:25:03 PM PDT 24
Peak memory 203692 kb
Host smart-6267a872-78a3-4eaa-86ff-cfa07408c6da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1499525305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1499525305
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1050317205
Short name T267
Test name
Test status
Simulation time 139345942 ps
CPU time 1.7 seconds
Started Apr 23 02:25:05 PM PDT 24
Finished Apr 23 02:25:07 PM PDT 24
Peak memory 212028 kb
Host smart-3e9e2ed4-b5af-4f27-baf7-f2d2c35f3093
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050317205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.1050317205
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.727464606
Short name T1403
Test name
Test status
Simulation time 31216291 ps
CPU time 0.97 seconds
Started Apr 23 02:25:03 PM PDT 24
Finished Apr 23 02:25:05 PM PDT 24
Peak memory 203652 kb
Host smart-d6f4c78f-71d3-4ee5-a475-4c1d76c9d6f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=727464606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.727464606
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.828005925
Short name T1415
Test name
Test status
Simulation time 188313008 ps
CPU time 1.74 seconds
Started Apr 23 02:25:04 PM PDT 24
Finished Apr 23 02:25:06 PM PDT 24
Peak memory 203744 kb
Host smart-c9dfe554-535c-4153-8bda-aefda7923468
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=828005925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.828005925
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1713081053
Short name T57
Test name
Test status
Simulation time 202246566 ps
CPU time 2.77 seconds
Started Apr 23 02:25:03 PM PDT 24
Finished Apr 23 02:25:07 PM PDT 24
Peak memory 203844 kb
Host smart-a7b84762-f29e-4212-bd7a-1c85e6f843e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1713081053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1713081053
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1415477336
Short name T1466
Test name
Test status
Simulation time 360563561 ps
CPU time 2.75 seconds
Started Apr 23 02:25:04 PM PDT 24
Finished Apr 23 02:25:07 PM PDT 24
Peak memory 203688 kb
Host smart-e71cb6f3-5ec7-4d86-beeb-34bc7670fd5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1415477336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.1415477336
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2531466164
Short name T250
Test name
Test status
Simulation time 360856974 ps
CPU time 3.61 seconds
Started Apr 23 02:24:36 PM PDT 24
Finished Apr 23 02:24:40 PM PDT 24
Peak memory 203608 kb
Host smart-fc52cfa2-3911-45b5-98d1-3758c28b7150
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2531466164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2531466164
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2912887211
Short name T259
Test name
Test status
Simulation time 1868076745 ps
CPU time 9.75 seconds
Started Apr 23 02:24:38 PM PDT 24
Finished Apr 23 02:24:49 PM PDT 24
Peak memory 203696 kb
Host smart-0d68eb11-bc56-43e1-9901-1b77b04b1f30
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2912887211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.2912887211
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.638125159
Short name T230
Test name
Test status
Simulation time 318854748 ps
CPU time 1.17 seconds
Started Apr 23 02:24:39 PM PDT 24
Finished Apr 23 02:24:40 PM PDT 24
Peak memory 203428 kb
Host smart-601fa623-a38e-4aec-9c92-16d318aa6e34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=638125159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.638125159
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3844587197
Short name T1389
Test name
Test status
Simulation time 84607951 ps
CPU time 2.22 seconds
Started Apr 23 02:24:37 PM PDT 24
Finished Apr 23 02:24:40 PM PDT 24
Peak memory 211912 kb
Host smart-0d1e6e60-0c6d-4e6e-9fc3-88f996fd9652
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844587197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.3844587197
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1320032345
Short name T251
Test name
Test status
Simulation time 61976645 ps
CPU time 0.95 seconds
Started Apr 23 02:24:35 PM PDT 24
Finished Apr 23 02:24:37 PM PDT 24
Peak memory 203748 kb
Host smart-3a9c1caf-8104-4bad-a3b5-c2f19563e74f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1320032345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1320032345
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3758711689
Short name T1417
Test name
Test status
Simulation time 42233084 ps
CPU time 0.67 seconds
Started Apr 23 02:24:33 PM PDT 24
Finished Apr 23 02:24:34 PM PDT 24
Peak memory 202912 kb
Host smart-5d94e8d6-3105-48fa-95a9-b3af3dbd0738
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3758711689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3758711689
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4053330521
Short name T252
Test name
Test status
Simulation time 119814452 ps
CPU time 1.45 seconds
Started Apr 23 02:24:33 PM PDT 24
Finished Apr 23 02:24:35 PM PDT 24
Peak memory 203808 kb
Host smart-ca71a181-6a1b-4c87-adac-c53fd146d15a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4053330521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.4053330521
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.4020278375
Short name T1394
Test name
Test status
Simulation time 157303470 ps
CPU time 3.7 seconds
Started Apr 23 02:24:34 PM PDT 24
Finished Apr 23 02:24:38 PM PDT 24
Peak memory 203672 kb
Host smart-c47cbf9b-de41-4c7f-b51e-dafe4cfec9f6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4020278375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.4020278375
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.330673395
Short name T1427
Test name
Test status
Simulation time 139895626 ps
CPU time 1.55 seconds
Started Apr 23 02:24:39 PM PDT 24
Finished Apr 23 02:24:41 PM PDT 24
Peak memory 203732 kb
Host smart-38b146f1-107f-4da3-819c-a5740b1c4c77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=330673395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.330673395
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.380145543
Short name T1421
Test name
Test status
Simulation time 200410981 ps
CPU time 2.42 seconds
Started Apr 23 02:24:37 PM PDT 24
Finished Apr 23 02:24:40 PM PDT 24
Peak memory 203828 kb
Host smart-36696c35-aa48-4c35-b256-d3c73c50315c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=380145543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.380145543
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.4061303273
Short name T1396
Test name
Test status
Simulation time 34147483 ps
CPU time 0.7 seconds
Started Apr 23 02:25:06 PM PDT 24
Finished Apr 23 02:25:07 PM PDT 24
Peak memory 202984 kb
Host smart-5959202c-bb63-4525-ae05-22d7971530ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4061303273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.4061303273
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2764504623
Short name T1469
Test name
Test status
Simulation time 43659654 ps
CPU time 0.72 seconds
Started Apr 23 02:25:03 PM PDT 24
Finished Apr 23 02:25:04 PM PDT 24
Peak memory 202944 kb
Host smart-f2d601fb-5fa9-4c77-9228-27bbb2346d7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2764504623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2764504623
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.289480305
Short name T66
Test name
Test status
Simulation time 30828837 ps
CPU time 0.68 seconds
Started Apr 23 02:25:02 PM PDT 24
Finished Apr 23 02:25:03 PM PDT 24
Peak memory 202916 kb
Host smart-684be4aa-f8f0-49e2-85af-b7606acaa9dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=289480305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.289480305
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.860994542
Short name T1449
Test name
Test status
Simulation time 48717467 ps
CPU time 0.69 seconds
Started Apr 23 02:25:03 PM PDT 24
Finished Apr 23 02:25:04 PM PDT 24
Peak memory 202880 kb
Host smart-6864562d-d5d4-4c34-a6fb-9840e34f52bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=860994542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.860994542
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.788984557
Short name T1409
Test name
Test status
Simulation time 42065958 ps
CPU time 0.67 seconds
Started Apr 23 02:25:04 PM PDT 24
Finished Apr 23 02:25:05 PM PDT 24
Peak memory 202980 kb
Host smart-637ab207-744d-4c5d-84ff-e4bcc4afda34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=788984557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.788984557
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2382478831
Short name T271
Test name
Test status
Simulation time 28207523 ps
CPU time 0.63 seconds
Started Apr 23 02:25:06 PM PDT 24
Finished Apr 23 02:25:08 PM PDT 24
Peak memory 202956 kb
Host smart-2ec8c0f1-ccca-410a-b33d-fd7179aed9b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2382478831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2382478831
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2789790607
Short name T273
Test name
Test status
Simulation time 34043286 ps
CPU time 0.65 seconds
Started Apr 23 02:25:07 PM PDT 24
Finished Apr 23 02:25:08 PM PDT 24
Peak memory 202980 kb
Host smart-e26dbe81-a4b2-404c-abe0-db4d1e4ede43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2789790607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.2789790607
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.637442616
Short name T1436
Test name
Test status
Simulation time 39454986 ps
CPU time 0.68 seconds
Started Apr 23 02:25:07 PM PDT 24
Finished Apr 23 02:25:09 PM PDT 24
Peak memory 202932 kb
Host smart-4d411d66-2cc8-460a-b595-00ae001444f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=637442616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.637442616
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1295671346
Short name T1412
Test name
Test status
Simulation time 96781545 ps
CPU time 0.74 seconds
Started Apr 23 02:25:09 PM PDT 24
Finished Apr 23 02:25:11 PM PDT 24
Peak memory 202920 kb
Host smart-1cc353bd-84f7-4357-8841-2ec201ee65f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1295671346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.1295671346
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.944548339
Short name T1397
Test name
Test status
Simulation time 36725932 ps
CPU time 0.66 seconds
Started Apr 23 02:25:06 PM PDT 24
Finished Apr 23 02:25:07 PM PDT 24
Peak memory 203016 kb
Host smart-cde0bf10-17f8-4398-8256-298ccfac65fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=944548339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.944548339
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.958986294
Short name T253
Test name
Test status
Simulation time 180567422 ps
CPU time 2.03 seconds
Started Apr 23 02:24:41 PM PDT 24
Finished Apr 23 02:24:44 PM PDT 24
Peak memory 203664 kb
Host smart-b0fcb2ed-87dd-422f-b416-7d50f8e119fe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=958986294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.958986294
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3570811531
Short name T1452
Test name
Test status
Simulation time 545822656 ps
CPU time 7.07 seconds
Started Apr 23 02:24:41 PM PDT 24
Finished Apr 23 02:24:49 PM PDT 24
Peak memory 203600 kb
Host smart-cbf29d59-93b7-4767-b847-110efa87fab2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3570811531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3570811531
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.4014428413
Short name T231
Test name
Test status
Simulation time 94028774 ps
CPU time 0.93 seconds
Started Apr 23 02:24:40 PM PDT 24
Finished Apr 23 02:24:41 PM PDT 24
Peak memory 203320 kb
Host smart-48a466dc-5ea1-4c7c-9e00-da6ae7518574
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4014428413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.4014428413
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2762106961
Short name T1447
Test name
Test status
Simulation time 143178896 ps
CPU time 1.78 seconds
Started Apr 23 02:24:41 PM PDT 24
Finished Apr 23 02:24:44 PM PDT 24
Peak memory 212024 kb
Host smart-5816b72b-6f4a-4e1c-9899-f0f66e7ed6fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762106961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2762106961
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.187120826
Short name T94
Test name
Test status
Simulation time 33516059 ps
CPU time 0.75 seconds
Started Apr 23 02:24:36 PM PDT 24
Finished Apr 23 02:24:37 PM PDT 24
Peak memory 203404 kb
Host smart-16a38cbf-09fa-470e-8499-3e4965c946f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=187120826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.187120826
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.575858302
Short name T1431
Test name
Test status
Simulation time 27148176 ps
CPU time 0.64 seconds
Started Apr 23 02:24:37 PM PDT 24
Finished Apr 23 02:24:38 PM PDT 24
Peak memory 202856 kb
Host smart-bf86bcd4-1f76-4bbb-9168-6a30c633a189
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=575858302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.575858302
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2259858489
Short name T260
Test name
Test status
Simulation time 108402261 ps
CPU time 1.38 seconds
Started Apr 23 02:24:35 PM PDT 24
Finished Apr 23 02:24:37 PM PDT 24
Peak memory 211936 kb
Host smart-23c5f5c4-1943-47c7-b88f-3e0e04841c19
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2259858489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2259858489
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3114748154
Short name T1378
Test name
Test status
Simulation time 156023642 ps
CPU time 3.82 seconds
Started Apr 23 02:24:38 PM PDT 24
Finished Apr 23 02:24:43 PM PDT 24
Peak memory 203708 kb
Host smart-ae5e4816-9436-4ae3-81fb-bf1217ccff8e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3114748154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3114748154
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.398557476
Short name T1388
Test name
Test status
Simulation time 129434689 ps
CPU time 1.49 seconds
Started Apr 23 02:24:41 PM PDT 24
Finished Apr 23 02:24:43 PM PDT 24
Peak memory 203692 kb
Host smart-e7eb918b-f12d-40fd-b7a4-d63b4ad2b82a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=398557476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.398557476
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1099255110
Short name T226
Test name
Test status
Simulation time 121128749 ps
CPU time 1.7 seconds
Started Apr 23 02:24:37 PM PDT 24
Finished Apr 23 02:24:39 PM PDT 24
Peak memory 203844 kb
Host smart-8a8c27ce-1770-4e7c-b0fe-6abf1cff64c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1099255110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.1099255110
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.252145047
Short name T235
Test name
Test status
Simulation time 463922880 ps
CPU time 2.72 seconds
Started Apr 23 02:24:37 PM PDT 24
Finished Apr 23 02:24:40 PM PDT 24
Peak memory 203752 kb
Host smart-262ae550-5919-4e03-8bf7-a4caa3a5f310
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=252145047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.252145047
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1078434437
Short name T1476
Test name
Test status
Simulation time 101446388 ps
CPU time 0.7 seconds
Started Apr 23 02:25:08 PM PDT 24
Finished Apr 23 02:25:10 PM PDT 24
Peak memory 202932 kb
Host smart-f5bba47e-838c-4136-8f7a-c3504925a15b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1078434437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1078434437
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3481093735
Short name T1391
Test name
Test status
Simulation time 45297539 ps
CPU time 0.66 seconds
Started Apr 23 02:25:10 PM PDT 24
Finished Apr 23 02:25:11 PM PDT 24
Peak memory 202948 kb
Host smart-906a27bf-b559-4025-94cb-e045c2be587c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3481093735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3481093735
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2301105153
Short name T269
Test name
Test status
Simulation time 51265182 ps
CPU time 0.67 seconds
Started Apr 23 02:25:08 PM PDT 24
Finished Apr 23 02:25:09 PM PDT 24
Peak memory 202932 kb
Host smart-756b1a95-e547-46b3-ac1d-831c6ff1d652
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2301105153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2301105153
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1843662190
Short name T1408
Test name
Test status
Simulation time 32404683 ps
CPU time 0.7 seconds
Started Apr 23 02:25:09 PM PDT 24
Finished Apr 23 02:25:11 PM PDT 24
Peak memory 202984 kb
Host smart-e8ef797c-6e61-4b82-934a-7f4d13081a97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1843662190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.1843662190
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.552212841
Short name T1393
Test name
Test status
Simulation time 60242036 ps
CPU time 0.74 seconds
Started Apr 23 02:25:07 PM PDT 24
Finished Apr 23 02:25:09 PM PDT 24
Peak memory 202856 kb
Host smart-14a9acc9-fa72-497f-90ff-e6d6455ce44b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=552212841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.552212841
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2593694302
Short name T1467
Test name
Test status
Simulation time 46374465 ps
CPU time 0.71 seconds
Started Apr 23 02:25:11 PM PDT 24
Finished Apr 23 02:25:13 PM PDT 24
Peak memory 202948 kb
Host smart-e93fe406-3cf5-4c54-94fa-64ca4683dd8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2593694302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.2593694302
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3992200220
Short name T1440
Test name
Test status
Simulation time 31548723 ps
CPU time 0.63 seconds
Started Apr 23 02:25:10 PM PDT 24
Finished Apr 23 02:25:12 PM PDT 24
Peak memory 202952 kb
Host smart-a949f07c-a1b2-4f6a-94d2-1221ef7dde45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3992200220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3992200220
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.647287816
Short name T276
Test name
Test status
Simulation time 27510269 ps
CPU time 0.63 seconds
Started Apr 23 02:25:07 PM PDT 24
Finished Apr 23 02:25:08 PM PDT 24
Peak memory 202964 kb
Host smart-df1159d0-45d0-460b-a113-d39f797ab073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=647287816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.647287816
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.114154506
Short name T1443
Test name
Test status
Simulation time 33984893 ps
CPU time 0.67 seconds
Started Apr 23 02:25:07 PM PDT 24
Finished Apr 23 02:25:08 PM PDT 24
Peak memory 202844 kb
Host smart-ecb66447-b09f-44e3-84c8-4feed560d227
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=114154506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.114154506
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3300233218
Short name T278
Test name
Test status
Simulation time 41439345 ps
CPU time 0.67 seconds
Started Apr 23 02:25:07 PM PDT 24
Finished Apr 23 02:25:08 PM PDT 24
Peak memory 203028 kb
Host smart-c194de2b-62d6-43a9-82d8-218798db150d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3300233218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3300233218
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.915702458
Short name T63
Test name
Test status
Simulation time 320678445 ps
CPU time 3.39 seconds
Started Apr 23 02:24:49 PM PDT 24
Finished Apr 23 02:24:53 PM PDT 24
Peak memory 203596 kb
Host smart-810ed26b-7e35-4535-ad02-5e4245c5bba3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=915702458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.915702458
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1679612803
Short name T256
Test name
Test status
Simulation time 1044813849 ps
CPU time 7.97 seconds
Started Apr 23 02:24:38 PM PDT 24
Finished Apr 23 02:24:47 PM PDT 24
Peak memory 203660 kb
Host smart-1a9abec3-1d90-496b-bb04-c34018bc1092
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1679612803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1679612803
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1789086743
Short name T1457
Test name
Test status
Simulation time 65055594 ps
CPU time 0.87 seconds
Started Apr 23 02:24:41 PM PDT 24
Finished Apr 23 02:24:43 PM PDT 24
Peak memory 203332 kb
Host smart-318d161c-4a3f-4819-90e4-bc50e7e74f52
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1789086743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1789086743
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3602754421
Short name T234
Test name
Test status
Simulation time 127531564 ps
CPU time 2.34 seconds
Started Apr 23 02:24:41 PM PDT 24
Finished Apr 23 02:24:44 PM PDT 24
Peak memory 212028 kb
Host smart-f0beb6c2-03f7-420e-9237-0414bf36e8c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602754421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.3602754421
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.106916602
Short name T91
Test name
Test status
Simulation time 51328836 ps
CPU time 0.8 seconds
Started Apr 23 02:24:41 PM PDT 24
Finished Apr 23 02:24:43 PM PDT 24
Peak memory 203448 kb
Host smart-3c0ede6c-84bf-4bf4-ac7e-08f46fbd03dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=106916602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.106916602
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3273628932
Short name T68
Test name
Test status
Simulation time 31496758 ps
CPU time 0.63 seconds
Started Apr 23 02:24:38 PM PDT 24
Finished Apr 23 02:24:39 PM PDT 24
Peak memory 202844 kb
Host smart-5f4f4eaf-544b-4d21-b849-9e39f85db7c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3273628932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3273628932
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4294555428
Short name T258
Test name
Test status
Simulation time 159577484 ps
CPU time 2.3 seconds
Started Apr 23 02:24:38 PM PDT 24
Finished Apr 23 02:24:41 PM PDT 24
Peak memory 211936 kb
Host smart-c2059ee1-b436-4327-bf04-84ccd9909bb0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4294555428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.4294555428
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2097294025
Short name T1377
Test name
Test status
Simulation time 365758000 ps
CPU time 2.61 seconds
Started Apr 23 02:24:41 PM PDT 24
Finished Apr 23 02:24:45 PM PDT 24
Peak memory 203564 kb
Host smart-8e6e5f46-4e3b-4e0e-81bd-7cdb6c177f42
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2097294025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.2097294025
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3729447014
Short name T1384
Test name
Test status
Simulation time 76490884 ps
CPU time 1.4 seconds
Started Apr 23 02:24:44 PM PDT 24
Finished Apr 23 02:24:46 PM PDT 24
Peak memory 203684 kb
Host smart-2390672d-041c-4e0e-8dfb-a8764abf1396
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3729447014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.3729447014
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.360884609
Short name T1401
Test name
Test status
Simulation time 61302904 ps
CPU time 1.66 seconds
Started Apr 23 02:24:39 PM PDT 24
Finished Apr 23 02:24:41 PM PDT 24
Peak memory 203808 kb
Host smart-b4acac8a-de01-4c50-8184-fc14f2916f97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=360884609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.360884609
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3300351895
Short name T287
Test name
Test status
Simulation time 1103819017 ps
CPU time 5.52 seconds
Started Apr 23 02:24:40 PM PDT 24
Finished Apr 23 02:24:46 PM PDT 24
Peak memory 203712 kb
Host smart-8d9f3a19-c6af-4c44-96b3-ed9b5039f641
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3300351895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3300351895
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2945817472
Short name T1414
Test name
Test status
Simulation time 33835005 ps
CPU time 0.63 seconds
Started Apr 23 02:25:13 PM PDT 24
Finished Apr 23 02:25:14 PM PDT 24
Peak memory 202948 kb
Host smart-901994d4-ec43-41dd-b0b2-b147ab917aab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2945817472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2945817472
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2595655994
Short name T277
Test name
Test status
Simulation time 60698491 ps
CPU time 0.68 seconds
Started Apr 23 02:25:13 PM PDT 24
Finished Apr 23 02:25:15 PM PDT 24
Peak memory 202940 kb
Host smart-816df9a8-c13f-4635-a368-4f296c1b6fa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2595655994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2595655994
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2744741258
Short name T1416
Test name
Test status
Simulation time 31954025 ps
CPU time 0.64 seconds
Started Apr 23 02:25:07 PM PDT 24
Finished Apr 23 02:25:08 PM PDT 24
Peak memory 202888 kb
Host smart-0eb47977-a54d-4610-a2d5-9a01630481d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2744741258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2744741258
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.174328413
Short name T1404
Test name
Test status
Simulation time 31642714 ps
CPU time 0.72 seconds
Started Apr 23 02:25:07 PM PDT 24
Finished Apr 23 02:25:08 PM PDT 24
Peak memory 202848 kb
Host smart-2d316d76-7979-4205-90d6-59d749f99b2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=174328413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.174328413
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1980115178
Short name T1475
Test name
Test status
Simulation time 33536297 ps
CPU time 0.67 seconds
Started Apr 23 02:25:08 PM PDT 24
Finished Apr 23 02:25:10 PM PDT 24
Peak memory 202980 kb
Host smart-88343143-d577-41f6-ae8e-85ca11a970fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1980115178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1980115178
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3098903222
Short name T65
Test name
Test status
Simulation time 30924593 ps
CPU time 0.62 seconds
Started Apr 23 02:25:08 PM PDT 24
Finished Apr 23 02:25:10 PM PDT 24
Peak memory 202928 kb
Host smart-cfadbf8f-5983-42df-8403-f15795432db3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3098903222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.3098903222
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.274673249
Short name T1445
Test name
Test status
Simulation time 50418945 ps
CPU time 0.67 seconds
Started Apr 23 02:25:11 PM PDT 24
Finished Apr 23 02:25:12 PM PDT 24
Peak memory 202988 kb
Host smart-cb85bcf9-1ed1-4a26-9a23-1206c3d2869d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=274673249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.274673249
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2703055648
Short name T1435
Test name
Test status
Simulation time 67508671 ps
CPU time 0.71 seconds
Started Apr 23 02:25:12 PM PDT 24
Finished Apr 23 02:25:13 PM PDT 24
Peak memory 202904 kb
Host smart-75ad89cb-6bb3-4783-873f-915079e1addc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2703055648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2703055648
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1874666333
Short name T1465
Test name
Test status
Simulation time 154351014 ps
CPU time 1.6 seconds
Started Apr 23 02:24:46 PM PDT 24
Finished Apr 23 02:24:48 PM PDT 24
Peak memory 215196 kb
Host smart-ef6fd52b-10c3-4589-9910-e362a4869cb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874666333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.1874666333
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1299046768
Short name T61
Test name
Test status
Simulation time 61810920 ps
CPU time 1.1 seconds
Started Apr 23 02:24:43 PM PDT 24
Finished Apr 23 02:24:45 PM PDT 24
Peak memory 203624 kb
Host smart-dcdf2361-ff43-45df-9975-a77cb1b9dbee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1299046768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1299046768
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2693804609
Short name T1478
Test name
Test status
Simulation time 53523680 ps
CPU time 0.67 seconds
Started Apr 23 02:24:48 PM PDT 24
Finished Apr 23 02:24:50 PM PDT 24
Peak memory 202888 kb
Host smart-979c01b2-9aaf-496c-afce-03c448d51698
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2693804609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2693804609
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1563700928
Short name T1461
Test name
Test status
Simulation time 60046665 ps
CPU time 1.01 seconds
Started Apr 23 02:24:42 PM PDT 24
Finished Apr 23 02:24:44 PM PDT 24
Peak memory 203724 kb
Host smart-4846d6bc-4581-4137-be30-75789d74dc09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1563700928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1563700928
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2390630484
Short name T227
Test name
Test status
Simulation time 206380605 ps
CPU time 2.35 seconds
Started Apr 23 02:24:45 PM PDT 24
Finished Apr 23 02:24:48 PM PDT 24
Peak memory 203836 kb
Host smart-3aa04ff4-fe52-40c1-95f7-9a29be297f31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2390630484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2390630484
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.212229166
Short name T236
Test name
Test status
Simulation time 207931544 ps
CPU time 2.33 seconds
Started Apr 23 02:24:48 PM PDT 24
Finished Apr 23 02:24:51 PM PDT 24
Peak memory 203760 kb
Host smart-c32c182e-7cc3-45a5-bf69-8fe9b6708cb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=212229166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.212229166
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2236832036
Short name T1386
Test name
Test status
Simulation time 92744131 ps
CPU time 2.17 seconds
Started Apr 23 02:24:42 PM PDT 24
Finished Apr 23 02:24:45 PM PDT 24
Peak memory 212016 kb
Host smart-90041080-438a-4e35-a7a9-ca786358e56a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236832036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.2236832036
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2324258716
Short name T1413
Test name
Test status
Simulation time 32054579 ps
CPU time 0.78 seconds
Started Apr 23 02:24:42 PM PDT 24
Finished Apr 23 02:24:43 PM PDT 24
Peak memory 203408 kb
Host smart-4a27452a-4aa6-4bed-89b9-89623673da51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2324258716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2324258716
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1726862952
Short name T1411
Test name
Test status
Simulation time 78623499 ps
CPU time 1.52 seconds
Started Apr 23 02:24:45 PM PDT 24
Finished Apr 23 02:24:48 PM PDT 24
Peak memory 203744 kb
Host smart-1f61d661-e7eb-43df-8d1a-ff95a768c6ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1726862952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.1726862952
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2978748683
Short name T1448
Test name
Test status
Simulation time 96848387 ps
CPU time 2.82 seconds
Started Apr 23 02:24:42 PM PDT 24
Finished Apr 23 02:24:46 PM PDT 24
Peak memory 203848 kb
Host smart-1ff32176-8dea-48c9-9cfe-431819caf0c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2978748683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2978748683
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3709433970
Short name T283
Test name
Test status
Simulation time 361321381 ps
CPU time 2.37 seconds
Started Apr 23 02:24:45 PM PDT 24
Finished Apr 23 02:24:48 PM PDT 24
Peak memory 203796 kb
Host smart-3ad453e1-4ff4-45e7-97c0-08cee25db8bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3709433970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3709433970
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3749791027
Short name T206
Test name
Test status
Simulation time 111025611 ps
CPU time 1.5 seconds
Started Apr 23 02:24:45 PM PDT 24
Finished Apr 23 02:24:47 PM PDT 24
Peak memory 211856 kb
Host smart-637246ec-038c-40a1-825b-93dcbf31fcd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749791027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.3749791027
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.668943114
Short name T270
Test name
Test status
Simulation time 34585410 ps
CPU time 0.74 seconds
Started Apr 23 02:24:50 PM PDT 24
Finished Apr 23 02:24:51 PM PDT 24
Peak memory 202972 kb
Host smart-e8818db9-4e47-40ac-8c73-e7af28a36a2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=668943114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.668943114
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3872499750
Short name T261
Test name
Test status
Simulation time 38730108 ps
CPU time 0.97 seconds
Started Apr 23 02:24:46 PM PDT 24
Finished Apr 23 02:24:47 PM PDT 24
Peak memory 203744 kb
Host smart-7bad6a75-ae9b-43ee-959c-1efae6f8938c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3872499750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.3872499750
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1981875321
Short name T228
Test name
Test status
Simulation time 324302818 ps
CPU time 3.49 seconds
Started Apr 23 02:24:46 PM PDT 24
Finished Apr 23 02:24:50 PM PDT 24
Peak memory 211972 kb
Host smart-c79d3832-53a0-4b21-b4b8-48005b405d5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1981875321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1981875321
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.7404185
Short name T282
Test name
Test status
Simulation time 1410632283 ps
CPU time 5.48 seconds
Started Apr 23 02:24:45 PM PDT 24
Finished Apr 23 02:24:51 PM PDT 24
Peak memory 203740 kb
Host smart-9ccca807-7af6-4ce9-bc7e-48acf8431723
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=7404185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.7404185
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1002855394
Short name T1428
Test name
Test status
Simulation time 194911919 ps
CPU time 2.15 seconds
Started Apr 23 02:24:45 PM PDT 24
Finished Apr 23 02:24:48 PM PDT 24
Peak memory 211964 kb
Host smart-e3420164-3173-4ac9-a2e0-fe9602c75dd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002855394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.1002855394
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3621511102
Short name T1441
Test name
Test status
Simulation time 60914625 ps
CPU time 0.95 seconds
Started Apr 23 02:24:48 PM PDT 24
Finished Apr 23 02:24:50 PM PDT 24
Peak memory 203652 kb
Host smart-9d8f7790-8c8c-426e-bf4c-cc0b86e0d46f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3621511102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.3621511102
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.4059924978
Short name T1390
Test name
Test status
Simulation time 37451455 ps
CPU time 0.62 seconds
Started Apr 23 02:24:46 PM PDT 24
Finished Apr 23 02:24:47 PM PDT 24
Peak memory 202956 kb
Host smart-17019c38-bdb5-486c-b127-0fdcadda41a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4059924978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.4059924978
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2183629874
Short name T1438
Test name
Test status
Simulation time 106428380 ps
CPU time 1.14 seconds
Started Apr 23 02:24:47 PM PDT 24
Finished Apr 23 02:24:49 PM PDT 24
Peak memory 203752 kb
Host smart-895607c2-70be-480b-9233-97004321b724
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2183629874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.2183629874
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1819308194
Short name T225
Test name
Test status
Simulation time 128200876 ps
CPU time 1.73 seconds
Started Apr 23 02:24:47 PM PDT 24
Finished Apr 23 02:24:49 PM PDT 24
Peak memory 203796 kb
Host smart-f9b12e89-e440-4d24-917a-acee2a96c908
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1819308194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1819308194
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3917538845
Short name T1425
Test name
Test status
Simulation time 411285955 ps
CPU time 4.03 seconds
Started Apr 23 02:24:46 PM PDT 24
Finished Apr 23 02:24:51 PM PDT 24
Peak memory 203680 kb
Host smart-33833a54-692a-4709-ad39-ba52b6df2c78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3917538845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3917538845
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1255427109
Short name T1434
Test name
Test status
Simulation time 57623281 ps
CPU time 1.14 seconds
Started Apr 23 02:24:49 PM PDT 24
Finished Apr 23 02:24:51 PM PDT 24
Peak memory 212032 kb
Host smart-56be8a70-d205-48ef-a24c-7b23518b9263
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255427109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.1255427109
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1995667830
Short name T1463
Test name
Test status
Simulation time 71147848 ps
CPU time 1 seconds
Started Apr 23 02:24:49 PM PDT 24
Finished Apr 23 02:24:50 PM PDT 24
Peak memory 203692 kb
Host smart-ab7fe889-d353-4838-98ea-8ad638d3dd3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1995667830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1995667830
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2706994567
Short name T1399
Test name
Test status
Simulation time 59450926 ps
CPU time 1.49 seconds
Started Apr 23 02:24:48 PM PDT 24
Finished Apr 23 02:24:50 PM PDT 24
Peak memory 203784 kb
Host smart-138488cd-2668-4e5b-bfad-32d62125bc9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2706994567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.2706994567
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2361380887
Short name T1451
Test name
Test status
Simulation time 113767033 ps
CPU time 1.61 seconds
Started Apr 23 02:24:43 PM PDT 24
Finished Apr 23 02:24:45 PM PDT 24
Peak memory 203748 kb
Host smart-83598f99-9aed-4ce4-8177-260cb72f5473
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2361380887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2361380887
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3553745302
Short name T1400
Test name
Test status
Simulation time 306653602 ps
CPU time 4 seconds
Started Apr 23 02:24:46 PM PDT 24
Finished Apr 23 02:24:51 PM PDT 24
Peak memory 203656 kb
Host smart-3192f13b-beb1-404a-9dff-51a63b3da41e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3553745302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3553745302
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.4123561275
Short name T562
Test name
Test status
Simulation time 8560023306 ps
CPU time 8.19 seconds
Started Apr 23 02:35:05 PM PDT 24
Finished Apr 23 02:35:14 PM PDT 24
Peak memory 204048 kb
Host smart-a1761c23-2db6-46ff-b4c0-dee200389b18
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4123561275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.4123561275
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.137102572
Short name T650
Test name
Test status
Simulation time 8384269094 ps
CPU time 8.21 seconds
Started Apr 23 02:35:04 PM PDT 24
Finished Apr 23 02:35:14 PM PDT 24
Peak memory 204064 kb
Host smart-cb6bddcb-7c17-48ca-b759-b9c544836802
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=137102572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.137102572
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.2376798737
Short name T1243
Test name
Test status
Simulation time 8403446752 ps
CPU time 9.83 seconds
Started Apr 23 02:35:04 PM PDT 24
Finished Apr 23 02:35:15 PM PDT 24
Peak memory 204000 kb
Host smart-5600b966-dcb6-45f6-a2ce-5cc684d7ae6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23767
98737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.2376798737
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.2707257686
Short name T626
Test name
Test status
Simulation time 8381802442 ps
CPU time 7.68 seconds
Started Apr 23 02:34:58 PM PDT 24
Finished Apr 23 02:35:07 PM PDT 24
Peak memory 203988 kb
Host smart-e48db20e-195b-4a33-bbb1-5abb945e220f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27072
57686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.2707257686
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_enable.1785240553
Short name T1170
Test name
Test status
Simulation time 8378598974 ps
CPU time 9.49 seconds
Started Apr 23 02:34:59 PM PDT 24
Finished Apr 23 02:35:09 PM PDT 24
Peak memory 203972 kb
Host smart-20c074fc-b259-46fa-9f08-ab4b385d8d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17852
40553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1785240553
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.1008508255
Short name T1293
Test name
Test status
Simulation time 74327522 ps
CPU time 1.97 seconds
Started Apr 23 02:34:59 PM PDT 24
Finished Apr 23 02:35:02 PM PDT 24
Peak memory 204080 kb
Host smart-cc06d8b3-b0e2-4a3f-b6c0-5d139ab1a907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10085
08255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.1008508255
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.1547713497
Short name T723
Test name
Test status
Simulation time 8459451201 ps
CPU time 10.44 seconds
Started Apr 23 02:35:11 PM PDT 24
Finished Apr 23 02:35:23 PM PDT 24
Peak memory 204012 kb
Host smart-45aa8cb9-7f13-469e-bda1-4552c7b76af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15477
13497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.1547713497
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.1646897137
Short name T1095
Test name
Test status
Simulation time 8463776200 ps
CPU time 9.13 seconds
Started Apr 23 02:34:59 PM PDT 24
Finished Apr 23 02:35:09 PM PDT 24
Peak memory 204012 kb
Host smart-8281435f-b74e-46a9-8d4c-5be88335987c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16468
97137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.1646897137
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.3810980368
Short name T1047
Test name
Test status
Simulation time 8427018538 ps
CPU time 9.07 seconds
Started Apr 23 02:34:59 PM PDT 24
Finished Apr 23 02:35:09 PM PDT 24
Peak memory 204060 kb
Host smart-d699f66a-5bfd-49df-bea6-cb40b3d0005c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38109
80368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.3810980368
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.1436608785
Short name T443
Test name
Test status
Simulation time 8370666215 ps
CPU time 7.91 seconds
Started Apr 23 02:35:00 PM PDT 24
Finished Apr 23 02:35:09 PM PDT 24
Peak memory 204060 kb
Host smart-a3c422f7-0f33-4c01-b975-aa3f5a50c6ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14366
08785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.1436608785
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3814503979
Short name T469
Test name
Test status
Simulation time 8387748847 ps
CPU time 7.82 seconds
Started Apr 23 02:35:04 PM PDT 24
Finished Apr 23 02:35:13 PM PDT 24
Peak memory 204048 kb
Host smart-f815c8ed-82c7-4706-a1e1-a18e94229828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38145
03979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3814503979
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2043930894
Short name T339
Test name
Test status
Simulation time 8406478817 ps
CPU time 7.4 seconds
Started Apr 23 02:35:03 PM PDT 24
Finished Apr 23 02:35:11 PM PDT 24
Peak memory 203992 kb
Host smart-ab3e6d62-25dc-4bf8-a33a-27d0a421acb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20439
30894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2043930894
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.1820876104
Short name T1070
Test name
Test status
Simulation time 8461747467 ps
CPU time 7.59 seconds
Started Apr 23 02:35:06 PM PDT 24
Finished Apr 23 02:35:14 PM PDT 24
Peak memory 203992 kb
Host smart-db6d3b74-5dfb-4855-8892-5656a4ce72e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18208
76104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.1820876104
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.1317040010
Short name T952
Test name
Test status
Simulation time 8380261293 ps
CPU time 9.48 seconds
Started Apr 23 02:35:06 PM PDT 24
Finished Apr 23 02:35:16 PM PDT 24
Peak memory 203988 kb
Host smart-16520789-9ca5-4be9-8ba8-690004eef10c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13170
40010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.1317040010
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.949908780
Short name T7
Test name
Test status
Simulation time 53277403 ps
CPU time 0.68 seconds
Started Apr 23 02:35:01 PM PDT 24
Finished Apr 23 02:35:03 PM PDT 24
Peak memory 203888 kb
Host smart-e3460d0f-01a5-4242-92ad-b4ed00c279f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94990
8780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.949908780
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.3087068554
Short name T516
Test name
Test status
Simulation time 8436444324 ps
CPU time 8 seconds
Started Apr 23 02:35:01 PM PDT 24
Finished Apr 23 02:35:10 PM PDT 24
Peak memory 204004 kb
Host smart-1cc3ef2a-dfeb-4ce0-839a-fb4b92c34f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30870
68554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.3087068554
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.1419403151
Short name T582
Test name
Test status
Simulation time 8400772154 ps
CPU time 8.16 seconds
Started Apr 23 02:35:06 PM PDT 24
Finished Apr 23 02:35:15 PM PDT 24
Peak memory 203992 kb
Host smart-db36796c-bcbc-4984-a57e-b4b61971650e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14194
03151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.1419403151
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.3375436118
Short name T474
Test name
Test status
Simulation time 8381734333 ps
CPU time 8.31 seconds
Started Apr 23 02:35:10 PM PDT 24
Finished Apr 23 02:35:19 PM PDT 24
Peak memory 204008 kb
Host smart-331408f5-d6ce-4cc3-b0c1-33350db6eba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33754
36118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.3375436118
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.511910503
Short name T649
Test name
Test status
Simulation time 8379053116 ps
CPU time 9.35 seconds
Started Apr 23 02:35:06 PM PDT 24
Finished Apr 23 02:35:16 PM PDT 24
Peak memory 204012 kb
Host smart-d5f1f224-db04-4452-aa2f-1f0f228cd59a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51191
0503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.511910503
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.3700107777
Short name T1252
Test name
Test status
Simulation time 8446091318 ps
CPU time 8.32 seconds
Started Apr 23 02:35:00 PM PDT 24
Finished Apr 23 02:35:09 PM PDT 24
Peak memory 204036 kb
Host smart-6d591842-95ab-4e74-9723-3d93d5b04714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37001
07777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3700107777
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.153426542
Short name T426
Test name
Test status
Simulation time 8402941653 ps
CPU time 9.28 seconds
Started Apr 23 02:35:03 PM PDT 24
Finished Apr 23 02:35:13 PM PDT 24
Peak memory 204008 kb
Host smart-69cd8169-0b94-4285-a3bf-de95638528c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15342
6542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.153426542
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.612511481
Short name T736
Test name
Test status
Simulation time 8462898728 ps
CPU time 8.31 seconds
Started Apr 23 02:35:18 PM PDT 24
Finished Apr 23 02:35:27 PM PDT 24
Peak memory 204064 kb
Host smart-a58e0c7c-f8ba-4a3e-9109-4640ea8b6c18
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=612511481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.612511481
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.679089393
Short name T1005
Test name
Test status
Simulation time 8379002804 ps
CPU time 8.12 seconds
Started Apr 23 02:35:12 PM PDT 24
Finished Apr 23 02:35:21 PM PDT 24
Peak memory 204048 kb
Host smart-556b0365-fbdb-4a44-8681-606ab1f6b958
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=679089393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.679089393
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.695862436
Short name T388
Test name
Test status
Simulation time 8434120575 ps
CPU time 8.6 seconds
Started Apr 23 02:35:14 PM PDT 24
Finished Apr 23 02:35:24 PM PDT 24
Peak memory 204016 kb
Host smart-f9f21d9c-7479-4041-b3e7-2817e46d5212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69586
2436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.695862436
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.2544266695
Short name T508
Test name
Test status
Simulation time 8395494079 ps
CPU time 7.98 seconds
Started Apr 23 02:35:06 PM PDT 24
Finished Apr 23 02:35:15 PM PDT 24
Peak memory 204024 kb
Host smart-00a3afdd-6247-4685-a14d-bfd31318a39a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25442
66695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.2544266695
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_enable.1518799301
Short name T519
Test name
Test status
Simulation time 8389326593 ps
CPU time 8.06 seconds
Started Apr 23 02:35:05 PM PDT 24
Finished Apr 23 02:35:14 PM PDT 24
Peak memory 203984 kb
Host smart-306ba1c6-39fb-4439-ad90-7f2244166aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15187
99301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.1518799301
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.3788083976
Short name T560
Test name
Test status
Simulation time 105063395 ps
CPU time 1.12 seconds
Started Apr 23 02:35:10 PM PDT 24
Finished Apr 23 02:35:12 PM PDT 24
Peak memory 204144 kb
Host smart-51d6c8e9-53be-4fba-887c-2e832540a393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37880
83976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.3788083976
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.1407405526
Short name T735
Test name
Test status
Simulation time 8374491797 ps
CPU time 8.38 seconds
Started Apr 23 02:35:15 PM PDT 24
Finished Apr 23 02:35:24 PM PDT 24
Peak memory 204076 kb
Host smart-56e66341-943f-4c61-949d-f5d6badd6e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14074
05526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.1407405526
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.2313984586
Short name T1177
Test name
Test status
Simulation time 8418340782 ps
CPU time 8.04 seconds
Started Apr 23 02:35:14 PM PDT 24
Finished Apr 23 02:35:23 PM PDT 24
Peak memory 204016 kb
Host smart-f8520397-2063-4970-994f-827cf6b144d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23139
84586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.2313984586
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.1748365616
Short name T894
Test name
Test status
Simulation time 8416434128 ps
CPU time 8.83 seconds
Started Apr 23 02:35:09 PM PDT 24
Finished Apr 23 02:35:18 PM PDT 24
Peak memory 204028 kb
Host smart-e242a59c-b0b7-4cd1-997d-1451aa34c9f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17483
65616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.1748365616
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.1139185504
Short name T989
Test name
Test status
Simulation time 8381672331 ps
CPU time 7.98 seconds
Started Apr 23 02:35:08 PM PDT 24
Finished Apr 23 02:35:17 PM PDT 24
Peak memory 203968 kb
Host smart-11849de9-e6fa-44a2-a89d-c167ad5bf619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11391
85504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.1139185504
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.3145156278
Short name T1135
Test name
Test status
Simulation time 8405662118 ps
CPU time 7.53 seconds
Started Apr 23 02:35:08 PM PDT 24
Finished Apr 23 02:35:16 PM PDT 24
Peak memory 204064 kb
Host smart-c5b7ee7d-b072-4a38-898f-6220f41164f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31451
56278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3145156278
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.3416554494
Short name T1099
Test name
Test status
Simulation time 8408822596 ps
CPU time 7.6 seconds
Started Apr 23 02:35:07 PM PDT 24
Finished Apr 23 02:35:15 PM PDT 24
Peak memory 203988 kb
Host smart-860e772a-177c-47c6-9353-f919be96f013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34165
54494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3416554494
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.3646876946
Short name T1314
Test name
Test status
Simulation time 8372806013 ps
CPU time 8.1 seconds
Started Apr 23 02:35:14 PM PDT 24
Finished Apr 23 02:35:22 PM PDT 24
Peak memory 203980 kb
Host smart-050040f8-0a20-4304-bd83-6861846f07cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36468
76946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.3646876946
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1982839217
Short name T931
Test name
Test status
Simulation time 29775957 ps
CPU time 0.62 seconds
Started Apr 23 02:35:11 PM PDT 24
Finished Apr 23 02:35:13 PM PDT 24
Peak memory 203904 kb
Host smart-fb767dd2-74ba-4b15-97e2-5e633973137d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19828
39217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1982839217
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.3171972215
Short name T1335
Test name
Test status
Simulation time 24581688157 ps
CPU time 43.72 seconds
Started Apr 23 02:35:09 PM PDT 24
Finished Apr 23 02:35:54 PM PDT 24
Peak memory 204292 kb
Host smart-80947fa3-818e-4ea4-93ba-e6d26ee0060e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31719
72215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.3171972215
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.838303287
Short name T240
Test name
Test status
Simulation time 8401293824 ps
CPU time 8.9 seconds
Started Apr 23 02:35:10 PM PDT 24
Finished Apr 23 02:35:20 PM PDT 24
Peak memory 204036 kb
Host smart-6493a8f9-a7c5-45d4-8604-4c513250a115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83830
3287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.838303287
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.859510425
Short name T903
Test name
Test status
Simulation time 8450550364 ps
CPU time 9.11 seconds
Started Apr 23 02:35:07 PM PDT 24
Finished Apr 23 02:35:17 PM PDT 24
Peak memory 204052 kb
Host smart-408e4d8f-4d89-4c44-839d-bcafdee88ddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85951
0425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.859510425
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.3306300455
Short name T935
Test name
Test status
Simulation time 8414667668 ps
CPU time 8.19 seconds
Started Apr 23 02:35:09 PM PDT 24
Finished Apr 23 02:35:18 PM PDT 24
Peak memory 204016 kb
Host smart-e608cb5b-a27f-42e9-8f0d-b9f79fa47b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33063
00455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.3306300455
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.1115936397
Short name T72
Test name
Test status
Simulation time 562268255 ps
CPU time 1.38 seconds
Started Apr 23 02:35:14 PM PDT 24
Finished Apr 23 02:35:16 PM PDT 24
Peak memory 221376 kb
Host smart-cbcb0889-4902-445d-b209-605e5bddd6b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1115936397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1115936397
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.241311197
Short name T183
Test name
Test status
Simulation time 8376032071 ps
CPU time 9.64 seconds
Started Apr 23 02:35:14 PM PDT 24
Finished Apr 23 02:35:25 PM PDT 24
Peak memory 204076 kb
Host smart-4017dc74-4525-47ab-bc4a-5aafab81d20d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24131
1197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.241311197
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.2447380461
Short name T76
Test name
Test status
Simulation time 8368882293 ps
CPU time 10.64 seconds
Started Apr 23 02:35:11 PM PDT 24
Finished Apr 23 02:35:22 PM PDT 24
Peak memory 204008 kb
Host smart-60fdb793-c3f4-488b-947c-56a0b579cfd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24473
80461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.2447380461
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3576967405
Short name T1004
Test name
Test status
Simulation time 8447803640 ps
CPU time 10.44 seconds
Started Apr 23 02:35:09 PM PDT 24
Finished Apr 23 02:35:20 PM PDT 24
Peak memory 203996 kb
Host smart-09317261-31c9-4875-97c2-7c2b54b1dd49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35769
67405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3576967405
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.55610273
Short name T471
Test name
Test status
Simulation time 8398783696 ps
CPU time 8.05 seconds
Started Apr 23 02:35:14 PM PDT 24
Finished Apr 23 02:35:23 PM PDT 24
Peak memory 204020 kb
Host smart-67437797-ea3b-4c9c-a84a-815f3b4cc00c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55610
273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.55610273
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.1380556932
Short name T544
Test name
Test status
Simulation time 8408694383 ps
CPU time 7.95 seconds
Started Apr 23 02:35:08 PM PDT 24
Finished Apr 23 02:35:17 PM PDT 24
Peak memory 204028 kb
Host smart-c2eaf76e-3913-4613-b1aa-0a590dd314ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13805
56932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.1380556932
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.3792204169
Short name T534
Test name
Test status
Simulation time 8463755522 ps
CPU time 8.85 seconds
Started Apr 23 02:35:58 PM PDT 24
Finished Apr 23 02:36:08 PM PDT 24
Peak memory 204060 kb
Host smart-f15af78d-152f-4326-8f13-530a346e73a1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3792204169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.3792204169
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.4251240188
Short name T1008
Test name
Test status
Simulation time 8392290044 ps
CPU time 7.84 seconds
Started Apr 23 02:35:58 PM PDT 24
Finished Apr 23 02:36:07 PM PDT 24
Peak memory 203996 kb
Host smart-bb878c1d-3c74-4050-ad73-acf10f4508af
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4251240188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.4251240188
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.2314244391
Short name T918
Test name
Test status
Simulation time 8390476513 ps
CPU time 8.44 seconds
Started Apr 23 02:35:58 PM PDT 24
Finished Apr 23 02:36:07 PM PDT 24
Peak memory 204040 kb
Host smart-697bf03c-80ec-4efb-9c7c-4f566b3afc32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23142
44391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.2314244391
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.819943078
Short name T1002
Test name
Test status
Simulation time 8374047940 ps
CPU time 9.09 seconds
Started Apr 23 02:35:53 PM PDT 24
Finished Apr 23 02:36:03 PM PDT 24
Peak memory 203972 kb
Host smart-1b894244-8100-403b-9448-8c0241c466d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81994
3078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.819943078
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_enable.73533572
Short name T324
Test name
Test status
Simulation time 8376762984 ps
CPU time 8.08 seconds
Started Apr 23 02:35:54 PM PDT 24
Finished Apr 23 02:36:02 PM PDT 24
Peak memory 203968 kb
Host smart-491bcebd-59d2-4cdc-9a09-991bd6392dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73533
572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.73533572
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.2457311258
Short name T722
Test name
Test status
Simulation time 159548392 ps
CPU time 1.82 seconds
Started Apr 23 02:35:59 PM PDT 24
Finished Apr 23 02:36:02 PM PDT 24
Peak memory 204160 kb
Host smart-67100dbb-63ca-4383-b1f9-7c91a079744c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24573
11258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.2457311258
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.3360958623
Short name T900
Test name
Test status
Simulation time 8393759946 ps
CPU time 7.49 seconds
Started Apr 23 02:35:58 PM PDT 24
Finished Apr 23 02:36:06 PM PDT 24
Peak memory 204012 kb
Host smart-54db4861-b9bb-4c51-9580-37df1551c0c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33609
58623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.3360958623
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.2991385529
Short name T410
Test name
Test status
Simulation time 8426513859 ps
CPU time 7.92 seconds
Started Apr 23 02:35:56 PM PDT 24
Finished Apr 23 02:36:05 PM PDT 24
Peak memory 204016 kb
Host smart-3e8bab31-408e-42bf-a416-42128ad3287f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29913
85529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.2991385529
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.2072847253
Short name T1276
Test name
Test status
Simulation time 8429200268 ps
CPU time 10.41 seconds
Started Apr 23 02:35:57 PM PDT 24
Finished Apr 23 02:36:08 PM PDT 24
Peak memory 204008 kb
Host smart-3991aecd-91ee-40e7-b20d-6dd8faa52784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20728
47253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2072847253
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.288018042
Short name T1374
Test name
Test status
Simulation time 8374069810 ps
CPU time 7.87 seconds
Started Apr 23 02:35:59 PM PDT 24
Finished Apr 23 02:36:08 PM PDT 24
Peak memory 204028 kb
Host smart-462fa625-0211-4cf2-b89b-13b370a07420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28801
8042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.288018042
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.2059941229
Short name T527
Test name
Test status
Simulation time 8376472021 ps
CPU time 8.45 seconds
Started Apr 23 02:35:59 PM PDT 24
Finished Apr 23 02:36:08 PM PDT 24
Peak memory 204032 kb
Host smart-29af364e-06d0-44e8-b682-e031be3db7fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20599
41229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2059941229
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2992386699
Short name T29
Test name
Test status
Simulation time 8403549804 ps
CPU time 9.5 seconds
Started Apr 23 02:35:55 PM PDT 24
Finished Apr 23 02:36:05 PM PDT 24
Peak memory 204020 kb
Host smart-e28bb614-0ee9-48b1-b671-250bedb75b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29923
86699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2992386699
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2561045733
Short name T1145
Test name
Test status
Simulation time 55438829 ps
CPU time 0.64 seconds
Started Apr 23 02:35:58 PM PDT 24
Finished Apr 23 02:36:00 PM PDT 24
Peak memory 203888 kb
Host smart-fb44a0fc-dda2-4a66-aa22-59b47503823e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25610
45733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2561045733
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.949931471
Short name T244
Test name
Test status
Simulation time 16246964359 ps
CPU time 28.46 seconds
Started Apr 23 02:35:55 PM PDT 24
Finished Apr 23 02:36:24 PM PDT 24
Peak memory 204304 kb
Host smart-fa4fa05c-8e72-454d-9693-3efa57e26eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94993
1471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.949931471
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.2425486403
Short name T1239
Test name
Test status
Simulation time 8406898017 ps
CPU time 10.22 seconds
Started Apr 23 02:35:55 PM PDT 24
Finished Apr 23 02:36:06 PM PDT 24
Peak memory 203988 kb
Host smart-fa527517-e515-4d75-a027-1dae75e92bc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24254
86403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.2425486403
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.2421190926
Short name T385
Test name
Test status
Simulation time 8406650874 ps
CPU time 8.74 seconds
Started Apr 23 02:35:54 PM PDT 24
Finished Apr 23 02:36:03 PM PDT 24
Peak memory 204016 kb
Host smart-b6b5b78b-82dc-4ffb-a534-265d7a326dc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24211
90926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.2421190926
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.1736623680
Short name T82
Test name
Test status
Simulation time 8466880098 ps
CPU time 8.6 seconds
Started Apr 23 02:35:54 PM PDT 24
Finished Apr 23 02:36:03 PM PDT 24
Peak memory 204016 kb
Host smart-5a82f1bf-b255-4e31-aa8b-eef7337b2a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17366
23680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.1736623680
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.2025688487
Short name T1273
Test name
Test status
Simulation time 8434587779 ps
CPU time 8.47 seconds
Started Apr 23 02:35:58 PM PDT 24
Finished Apr 23 02:36:08 PM PDT 24
Peak memory 204016 kb
Host smart-c3f52cf6-a300-4f03-a57c-3a7a785ecdbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20256
88487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.2025688487
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.4193216254
Short name T947
Test name
Test status
Simulation time 8363123767 ps
CPU time 8.79 seconds
Started Apr 23 02:35:56 PM PDT 24
Finished Apr 23 02:36:05 PM PDT 24
Peak memory 203968 kb
Host smart-5a2a8a25-57f7-460c-a563-1598b25ec216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41932
16254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.4193216254
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.3405332692
Short name T1217
Test name
Test status
Simulation time 8418550780 ps
CPU time 7.92 seconds
Started Apr 23 02:35:53 PM PDT 24
Finished Apr 23 02:36:02 PM PDT 24
Peak memory 204028 kb
Host smart-3ab170da-177d-487a-bb85-00682d4f943f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34053
32692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.3405332692
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.1135403593
Short name T833
Test name
Test status
Simulation time 8373327538 ps
CPU time 8.29 seconds
Started Apr 23 02:35:57 PM PDT 24
Finished Apr 23 02:36:06 PM PDT 24
Peak memory 204020 kb
Host smart-758fb542-d57b-40cd-b086-9b298a74a069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11354
03593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.1135403593
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.1240584021
Short name T559
Test name
Test status
Simulation time 8376342730 ps
CPU time 7.74 seconds
Started Apr 23 02:35:56 PM PDT 24
Finished Apr 23 02:36:04 PM PDT 24
Peak memory 204056 kb
Host smart-ad57c39a-5ea8-4589-83b1-697e5c8f83cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12405
84021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.1240584021
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.3385187837
Short name T1125
Test name
Test status
Simulation time 8468491759 ps
CPU time 9.94 seconds
Started Apr 23 02:35:59 PM PDT 24
Finished Apr 23 02:36:10 PM PDT 24
Peak memory 204064 kb
Host smart-07a387d9-c700-4cb9-bde8-22c84e65e07e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3385187837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.3385187837
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.3339322153
Short name T656
Test name
Test status
Simulation time 8391814860 ps
CPU time 8.42 seconds
Started Apr 23 02:36:00 PM PDT 24
Finished Apr 23 02:36:09 PM PDT 24
Peak memory 204048 kb
Host smart-259e3feb-a237-4dfe-bdb1-025fb3bd1d2a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3339322153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.3339322153
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.1148015053
Short name T358
Test name
Test status
Simulation time 8454928231 ps
CPU time 8.05 seconds
Started Apr 23 02:36:05 PM PDT 24
Finished Apr 23 02:36:13 PM PDT 24
Peak memory 204004 kb
Host smart-fe396b10-4f92-40d5-aa14-8a590fe1d9a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11480
15053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.1148015053
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.2250816522
Short name T1369
Test name
Test status
Simulation time 8398414131 ps
CPU time 8.35 seconds
Started Apr 23 02:35:58 PM PDT 24
Finished Apr 23 02:36:07 PM PDT 24
Peak memory 204020 kb
Host smart-34f794ee-4a80-4471-9ee5-74350c166e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22508
16522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.2250816522
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_enable.3332110253
Short name T308
Test name
Test status
Simulation time 8382167477 ps
CPU time 7.81 seconds
Started Apr 23 02:35:57 PM PDT 24
Finished Apr 23 02:36:05 PM PDT 24
Peak memory 204024 kb
Host smart-10f40b3b-378b-4356-8029-bc3f2859bedf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33321
10253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3332110253
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.3675991686
Short name T857
Test name
Test status
Simulation time 50246393 ps
CPU time 1.16 seconds
Started Apr 23 02:35:57 PM PDT 24
Finished Apr 23 02:35:59 PM PDT 24
Peak memory 204076 kb
Host smart-78aebf77-7d8c-45dd-9a36-30eb957a36cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36759
91686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3675991686
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.3835678236
Short name T1108
Test name
Test status
Simulation time 8469403365 ps
CPU time 7.95 seconds
Started Apr 23 02:35:59 PM PDT 24
Finished Apr 23 02:36:08 PM PDT 24
Peak memory 204016 kb
Host smart-57c6e9e8-22b7-4c7e-a55b-587df3df37ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38356
78236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.3835678236
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.3664342023
Short name T133
Test name
Test status
Simulation time 8422246198 ps
CPU time 8.13 seconds
Started Apr 23 02:36:03 PM PDT 24
Finished Apr 23 02:36:12 PM PDT 24
Peak memory 204012 kb
Host smart-7832b690-3171-4a25-8a21-e72d87f5f295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36643
42023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.3664342023
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.1386851599
Short name T1140
Test name
Test status
Simulation time 8433611035 ps
CPU time 7.8 seconds
Started Apr 23 02:35:55 PM PDT 24
Finished Apr 23 02:36:04 PM PDT 24
Peak memory 204020 kb
Host smart-1f547760-55dd-4620-ab26-8d1c007c8918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13868
51599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.1386851599
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.840881153
Short name T536
Test name
Test status
Simulation time 8376526753 ps
CPU time 8.52 seconds
Started Apr 23 02:35:56 PM PDT 24
Finished Apr 23 02:36:05 PM PDT 24
Peak memory 204028 kb
Host smart-5e5e7568-76bd-4e1c-b480-7fb5ea176ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84088
1153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.840881153
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.530480573
Short name T792
Test name
Test status
Simulation time 8403987566 ps
CPU time 10.04 seconds
Started Apr 23 02:36:00 PM PDT 24
Finished Apr 23 02:36:11 PM PDT 24
Peak memory 204032 kb
Host smart-f235514e-3354-4a35-b981-1d2f48e9e2fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53048
0573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.530480573
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.2505723385
Short name T1156
Test name
Test status
Simulation time 8374992045 ps
CPU time 7.88 seconds
Started Apr 23 02:36:05 PM PDT 24
Finished Apr 23 02:36:13 PM PDT 24
Peak memory 204008 kb
Host smart-486a3d70-7acd-4454-8f44-b880d81d5cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25057
23385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.2505723385
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.138638370
Short name T752
Test name
Test status
Simulation time 8412656553 ps
CPU time 8.51 seconds
Started Apr 23 02:36:05 PM PDT 24
Finished Apr 23 02:36:14 PM PDT 24
Peak memory 203988 kb
Host smart-ec711eb8-cf2d-412b-8468-b5d48b552325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13863
8370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.138638370
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.173517532
Short name T1046
Test name
Test status
Simulation time 8366868622 ps
CPU time 8.09 seconds
Started Apr 23 02:36:01 PM PDT 24
Finished Apr 23 02:36:09 PM PDT 24
Peak memory 204044 kb
Host smart-b32e5286-3f5d-4568-a03b-cb9fdb150423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17351
7532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.173517532
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.2352105923
Short name T1153
Test name
Test status
Simulation time 93982146 ps
CPU time 0.83 seconds
Started Apr 23 02:36:01 PM PDT 24
Finished Apr 23 02:36:02 PM PDT 24
Peak memory 203892 kb
Host smart-4bfa8988-efa6-4b65-917e-8324cee79d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23521
05923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.2352105923
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.1963645039
Short name T1297
Test name
Test status
Simulation time 23065444330 ps
CPU time 45.42 seconds
Started Apr 23 02:35:58 PM PDT 24
Finished Apr 23 02:36:44 PM PDT 24
Peak memory 204292 kb
Host smart-a6c853b7-d146-4a6a-95b4-64fb1108cf65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19636
45039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.1963645039
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.3847670664
Short name T647
Test name
Test status
Simulation time 8380515856 ps
CPU time 7.94 seconds
Started Apr 23 02:36:01 PM PDT 24
Finished Apr 23 02:36:09 PM PDT 24
Peak memory 203964 kb
Host smart-90bf92b6-d631-4837-98ff-ce4fbf574d55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38476
70664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3847670664
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.551355733
Short name T1169
Test name
Test status
Simulation time 8434518100 ps
CPU time 7.88 seconds
Started Apr 23 02:35:57 PM PDT 24
Finished Apr 23 02:36:06 PM PDT 24
Peak memory 204076 kb
Host smart-7fbb2e7d-b413-4489-8fe7-539a16e96a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55135
5733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.551355733
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.2136230989
Short name T674
Test name
Test status
Simulation time 8451504739 ps
CPU time 8.66 seconds
Started Apr 23 02:36:00 PM PDT 24
Finished Apr 23 02:36:10 PM PDT 24
Peak memory 204060 kb
Host smart-9025a1d5-a85b-4632-b649-c4c1610f703f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21362
30989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.2136230989
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.3843476123
Short name T828
Test name
Test status
Simulation time 8434440972 ps
CPU time 9.23 seconds
Started Apr 23 02:36:00 PM PDT 24
Finished Apr 23 02:36:10 PM PDT 24
Peak memory 204052 kb
Host smart-68768e3b-b73d-4933-b541-3dde36c6e64b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38434
76123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.3843476123
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.1034327034
Short name T481
Test name
Test status
Simulation time 8369956579 ps
CPU time 7.87 seconds
Started Apr 23 02:36:01 PM PDT 24
Finished Apr 23 02:36:10 PM PDT 24
Peak memory 204036 kb
Host smart-55d541fd-0f50-4f97-acb3-c565a9639a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10343
27034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.1034327034
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.263232393
Short name T577
Test name
Test status
Simulation time 8430234099 ps
CPU time 9.55 seconds
Started Apr 23 02:36:00 PM PDT 24
Finished Apr 23 02:36:10 PM PDT 24
Peak memory 204036 kb
Host smart-41385f61-4023-4235-b79e-ab5d67ce8716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26323
2393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.263232393
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.2676344143
Short name T294
Test name
Test status
Simulation time 8377439592 ps
CPU time 8.24 seconds
Started Apr 23 02:36:00 PM PDT 24
Finished Apr 23 02:36:09 PM PDT 24
Peak memory 203996 kb
Host smart-176c505e-4a7a-41dc-a12c-fb7eb9a5f2b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26763
44143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.2676344143
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.3867087782
Short name T1313
Test name
Test status
Simulation time 8384550079 ps
CPU time 8.85 seconds
Started Apr 23 02:36:01 PM PDT 24
Finished Apr 23 02:36:10 PM PDT 24
Peak memory 203988 kb
Host smart-b0faae67-6ae5-400b-8328-94371d076e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38670
87782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.3867087782
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.3817233585
Short name T1214
Test name
Test status
Simulation time 8491369722 ps
CPU time 8.29 seconds
Started Apr 23 02:36:03 PM PDT 24
Finished Apr 23 02:36:11 PM PDT 24
Peak memory 203968 kb
Host smart-423d6c75-a219-4913-bf87-633e3a6d0900
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3817233585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.3817233585
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/12.min_length_in_transaction.1338966257
Short name T701
Test name
Test status
Simulation time 8375990879 ps
CPU time 9.16 seconds
Started Apr 23 02:36:07 PM PDT 24
Finished Apr 23 02:36:17 PM PDT 24
Peak memory 203988 kb
Host smart-5313a1cc-6c4c-45da-9e02-7b5bf0fb526b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1338966257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.1338966257
Directory /workspace/12.min_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.4044468177
Short name T462
Test name
Test status
Simulation time 8392464697 ps
CPU time 7.84 seconds
Started Apr 23 02:36:08 PM PDT 24
Finished Apr 23 02:36:17 PM PDT 24
Peak memory 204056 kb
Host smart-00485f47-d52c-490c-8936-5a5ec10a0201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40444
68177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.4044468177
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.1118604325
Short name T204
Test name
Test status
Simulation time 8389538768 ps
CPU time 7.46 seconds
Started Apr 23 02:36:04 PM PDT 24
Finished Apr 23 02:36:12 PM PDT 24
Peak memory 204000 kb
Host smart-afac1201-d781-48ca-935d-2dc178d6287b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11186
04325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.1118604325
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_enable.1735199119
Short name T369
Test name
Test status
Simulation time 8375529211 ps
CPU time 7.38 seconds
Started Apr 23 02:36:02 PM PDT 24
Finished Apr 23 02:36:10 PM PDT 24
Peak memory 204040 kb
Host smart-8316d255-fd8a-4725-b0b2-8721f53c028d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17351
99119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.1735199119
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.3045657134
Short name T1139
Test name
Test status
Simulation time 223462769 ps
CPU time 1.84 seconds
Started Apr 23 02:36:03 PM PDT 24
Finished Apr 23 02:36:06 PM PDT 24
Peak memory 204084 kb
Host smart-b5537459-580a-4610-a48b-173d6292e45d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30456
57134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3045657134
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.4152779486
Short name T1201
Test name
Test status
Simulation time 8457795514 ps
CPU time 9.06 seconds
Started Apr 23 02:36:03 PM PDT 24
Finished Apr 23 02:36:13 PM PDT 24
Peak memory 204032 kb
Host smart-6f2df190-2440-4453-96a6-dc9879c36b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41527
79486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.4152779486
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.408774734
Short name T768
Test name
Test status
Simulation time 8392441855 ps
CPU time 7.74 seconds
Started Apr 23 02:36:05 PM PDT 24
Finished Apr 23 02:36:13 PM PDT 24
Peak memory 203956 kb
Host smart-8b4e29e1-e884-43d3-8b97-3deec3924ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40877
4734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.408774734
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1222761524
Short name T660
Test name
Test status
Simulation time 8428296023 ps
CPU time 7.97 seconds
Started Apr 23 02:36:05 PM PDT 24
Finished Apr 23 02:36:14 PM PDT 24
Peak memory 204008 kb
Host smart-d8fe4124-bb25-4548-9938-c6733d2bcee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12227
61524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1222761524
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.1912009852
Short name T1258
Test name
Test status
Simulation time 8370973231 ps
CPU time 7.85 seconds
Started Apr 23 02:36:03 PM PDT 24
Finished Apr 23 02:36:12 PM PDT 24
Peak memory 203964 kb
Host smart-0bcf4eaf-b6a9-433f-b9d8-3e32b9a76976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19120
09852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.1912009852
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.2607652783
Short name T1133
Test name
Test status
Simulation time 8389219265 ps
CPU time 7.71 seconds
Started Apr 23 02:36:03 PM PDT 24
Finished Apr 23 02:36:11 PM PDT 24
Peak memory 204080 kb
Host smart-80451e70-658e-4513-8fc0-8073d114b6ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26076
52783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.2607652783
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.1690010562
Short name T1226
Test name
Test status
Simulation time 8402104411 ps
CPU time 10.31 seconds
Started Apr 23 02:36:07 PM PDT 24
Finished Apr 23 02:36:17 PM PDT 24
Peak memory 203964 kb
Host smart-bd14a803-53f9-45f0-8655-d9d10e1be263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16900
10562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.1690010562
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.86320703
Short name T910
Test name
Test status
Simulation time 8385992846 ps
CPU time 10.16 seconds
Started Apr 23 02:36:08 PM PDT 24
Finished Apr 23 02:36:18 PM PDT 24
Peak memory 204012 kb
Host smart-b3b49982-925b-42dc-9bf0-ab7e6ec08e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86320
703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.86320703
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.325673192
Short name T472
Test name
Test status
Simulation time 34121149 ps
CPU time 0.66 seconds
Started Apr 23 02:36:04 PM PDT 24
Finished Apr 23 02:36:05 PM PDT 24
Peak memory 203920 kb
Host smart-fdfad257-6a56-46e9-b789-d1f1d43ceb1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32567
3192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.325673192
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.1087021772
Short name T245
Test name
Test status
Simulation time 28911770770 ps
CPU time 63.33 seconds
Started Apr 23 02:36:04 PM PDT 24
Finished Apr 23 02:37:08 PM PDT 24
Peak memory 204316 kb
Host smart-d0b475ff-c4f5-4a2a-a651-603937babce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10870
21772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.1087021772
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.2191076474
Short name T779
Test name
Test status
Simulation time 8389161169 ps
CPU time 7.9 seconds
Started Apr 23 02:36:08 PM PDT 24
Finished Apr 23 02:36:16 PM PDT 24
Peak memory 204016 kb
Host smart-29571f84-aeba-46f6-85d3-2b1fe6b330f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21910
76474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.2191076474
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.714742590
Short name T1220
Test name
Test status
Simulation time 8463070348 ps
CPU time 7.87 seconds
Started Apr 23 02:36:04 PM PDT 24
Finished Apr 23 02:36:13 PM PDT 24
Peak memory 203984 kb
Host smart-c5b4196b-7d2a-4540-876e-62fc43e57792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71474
2590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.714742590
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.141039228
Short name T896
Test name
Test status
Simulation time 8376001373 ps
CPU time 8.35 seconds
Started Apr 23 02:36:06 PM PDT 24
Finished Apr 23 02:36:15 PM PDT 24
Peak memory 203956 kb
Host smart-bbbbcd22-61bc-4542-b660-e00759961a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14103
9228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.141039228
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3971636978
Short name T657
Test name
Test status
Simulation time 8375209397 ps
CPU time 8.72 seconds
Started Apr 23 02:36:04 PM PDT 24
Finished Apr 23 02:36:14 PM PDT 24
Peak memory 204012 kb
Host smart-90b34416-20d0-463e-98dc-40d2eb7f346b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39716
36978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3971636978
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.3127609478
Short name T1173
Test name
Test status
Simulation time 8465318973 ps
CPU time 7.82 seconds
Started Apr 23 02:36:05 PM PDT 24
Finished Apr 23 02:36:13 PM PDT 24
Peak memory 204000 kb
Host smart-41c16027-675d-449c-b942-1c866ae623f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31276
09478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.3127609478
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.1295121936
Short name T1288
Test name
Test status
Simulation time 8405560217 ps
CPU time 10.02 seconds
Started Apr 23 02:36:05 PM PDT 24
Finished Apr 23 02:36:15 PM PDT 24
Peak memory 204008 kb
Host smart-4818e363-a942-4415-92b7-197aafdb23a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12951
21936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.1295121936
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.1734270817
Short name T707
Test name
Test status
Simulation time 8467967397 ps
CPU time 8.11 seconds
Started Apr 23 02:36:03 PM PDT 24
Finished Apr 23 02:36:12 PM PDT 24
Peak memory 204056 kb
Host smart-463b1bb5-cf7d-4daa-889c-bf1d3e1e50d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17342
70817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1734270817
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.1279172114
Short name T445
Test name
Test status
Simulation time 8465114642 ps
CPU time 7.79 seconds
Started Apr 23 02:36:15 PM PDT 24
Finished Apr 23 02:36:23 PM PDT 24
Peak memory 204012 kb
Host smart-0e794216-3743-4c67-b39d-a9b5f53b1a18
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1279172114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.1279172114
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.2725587137
Short name T740
Test name
Test status
Simulation time 8384457500 ps
CPU time 7.7 seconds
Started Apr 23 02:36:12 PM PDT 24
Finished Apr 23 02:36:20 PM PDT 24
Peak memory 204004 kb
Host smart-6cf64319-5020-4d17-bc6e-202e358faf11
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2725587137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.2725587137
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.4261912682
Short name T597
Test name
Test status
Simulation time 8390979398 ps
CPU time 8.67 seconds
Started Apr 23 02:36:19 PM PDT 24
Finished Apr 23 02:36:28 PM PDT 24
Peak memory 203960 kb
Host smart-eb5aee80-cdd1-45e1-8bc6-49371e84338b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42619
12682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.4261912682
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.1750610671
Short name T437
Test name
Test status
Simulation time 8455225231 ps
CPU time 8.46 seconds
Started Apr 23 02:36:09 PM PDT 24
Finished Apr 23 02:36:18 PM PDT 24
Peak memory 204016 kb
Host smart-465ebf1b-1aa6-4c0b-ab4f-fce67de6ec7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17506
10671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.1750610671
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_enable.2476819506
Short name T321
Test name
Test status
Simulation time 8376321591 ps
CPU time 10.27 seconds
Started Apr 23 02:36:10 PM PDT 24
Finished Apr 23 02:36:21 PM PDT 24
Peak memory 203972 kb
Host smart-cc68dfd8-0aca-471b-85df-5f7d60755965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24768
19506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.2476819506
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.2155674762
Short name T507
Test name
Test status
Simulation time 144394709 ps
CPU time 1.52 seconds
Started Apr 23 02:36:08 PM PDT 24
Finished Apr 23 02:36:10 PM PDT 24
Peak memory 204176 kb
Host smart-c8fdb08c-9383-41b7-bcb6-fb6422e8ff4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21556
74762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.2155674762
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.3392349265
Short name T840
Test name
Test status
Simulation time 8398973393 ps
CPU time 7.34 seconds
Started Apr 23 02:36:12 PM PDT 24
Finished Apr 23 02:36:20 PM PDT 24
Peak memory 204096 kb
Host smart-d75246c0-7ebd-4bad-95f9-8812ed53a8bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33923
49265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.3392349265
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.2617186459
Short name T1357
Test name
Test status
Simulation time 8398872750 ps
CPU time 9.24 seconds
Started Apr 23 02:36:12 PM PDT 24
Finished Apr 23 02:36:22 PM PDT 24
Peak memory 204060 kb
Host smart-4ee0f150-b774-481e-bef9-7fe485a5e4b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26171
86459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.2617186459
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.971881416
Short name T741
Test name
Test status
Simulation time 8472158152 ps
CPU time 7.64 seconds
Started Apr 23 02:36:08 PM PDT 24
Finished Apr 23 02:36:17 PM PDT 24
Peak memory 204020 kb
Host smart-c89b8308-28b7-479f-99a0-6615c191d526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97188
1416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.971881416
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3349727225
Short name T1263
Test name
Test status
Simulation time 8418914755 ps
CPU time 10.36 seconds
Started Apr 23 02:36:09 PM PDT 24
Finished Apr 23 02:36:20 PM PDT 24
Peak memory 204008 kb
Host smart-d99f4496-bbd4-47a5-81f2-c3a69f6684df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33497
27225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3349727225
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.2464772774
Short name T696
Test name
Test status
Simulation time 8372766125 ps
CPU time 8.85 seconds
Started Apr 23 02:36:09 PM PDT 24
Finished Apr 23 02:36:19 PM PDT 24
Peak memory 204056 kb
Host smart-cea96d80-d672-4fb1-8d51-c9c1a8f47118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24647
72774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.2464772774
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.3782391275
Short name T954
Test name
Test status
Simulation time 8408801265 ps
CPU time 7.62 seconds
Started Apr 23 02:36:09 PM PDT 24
Finished Apr 23 02:36:18 PM PDT 24
Peak memory 204064 kb
Host smart-c4e56f85-8937-4c46-9d54-2be7dc1885ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37823
91275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3782391275
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1514930349
Short name T620
Test name
Test status
Simulation time 8376727005 ps
CPU time 8.26 seconds
Started Apr 23 02:36:10 PM PDT 24
Finished Apr 23 02:36:19 PM PDT 24
Peak memory 204044 kb
Host smart-bd625cb3-1aa6-4b08-a32f-56a3075ba0ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15149
30349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1514930349
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.1332133938
Short name T1283
Test name
Test status
Simulation time 8433957385 ps
CPU time 8.4 seconds
Started Apr 23 02:36:11 PM PDT 24
Finished Apr 23 02:36:20 PM PDT 24
Peak memory 204044 kb
Host smart-255f0cd2-a113-4e1c-b0c3-89a041978da0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13321
33938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.1332133938
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.2739499394
Short name T1090
Test name
Test status
Simulation time 38728201 ps
CPU time 0.65 seconds
Started Apr 23 02:36:11 PM PDT 24
Finished Apr 23 02:36:12 PM PDT 24
Peak memory 203904 kb
Host smart-1b73f0fa-597f-4707-8852-d59aae61a122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27394
99394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.2739499394
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.4204879434
Short name T265
Test name
Test status
Simulation time 25291381174 ps
CPU time 49.8 seconds
Started Apr 23 02:36:10 PM PDT 24
Finished Apr 23 02:37:00 PM PDT 24
Peak memory 204344 kb
Host smart-9683fd4b-2dc9-4194-ab66-d2e578309527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42048
79434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.4204879434
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.1013481022
Short name T616
Test name
Test status
Simulation time 8419743562 ps
CPU time 9.35 seconds
Started Apr 23 02:36:14 PM PDT 24
Finished Apr 23 02:36:24 PM PDT 24
Peak memory 203980 kb
Host smart-9db01b37-abf9-41f7-a156-2bca6a3320b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10134
81022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1013481022
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.1134177267
Short name T978
Test name
Test status
Simulation time 8390202949 ps
CPU time 8.51 seconds
Started Apr 23 02:36:13 PM PDT 24
Finished Apr 23 02:36:22 PM PDT 24
Peak memory 204016 kb
Host smart-6d819439-556b-4186-9a75-e8212b4f7b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11341
77267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.1134177267
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.3581381288
Short name T1136
Test name
Test status
Simulation time 8375078991 ps
CPU time 10.14 seconds
Started Apr 23 02:36:14 PM PDT 24
Finished Apr 23 02:36:24 PM PDT 24
Peak memory 204092 kb
Host smart-bf16b03d-2cfa-4049-a17f-da9e0bd77d1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35813
81288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.3581381288
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.2183270149
Short name T966
Test name
Test status
Simulation time 8366745712 ps
CPU time 8.31 seconds
Started Apr 23 02:36:09 PM PDT 24
Finished Apr 23 02:36:18 PM PDT 24
Peak memory 204024 kb
Host smart-66fb31c8-f952-4e0f-b30d-76eb6330b92f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21832
70149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.2183270149
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.2536986179
Short name T1326
Test name
Test status
Simulation time 8392608395 ps
CPU time 8.43 seconds
Started Apr 23 02:36:13 PM PDT 24
Finished Apr 23 02:36:22 PM PDT 24
Peak memory 204056 kb
Host smart-189137c5-3106-4980-99cc-d99f70e52c0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25369
86179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.2536986179
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.1444972383
Short name T359
Test name
Test status
Simulation time 8385723882 ps
CPU time 7.98 seconds
Started Apr 23 02:36:18 PM PDT 24
Finished Apr 23 02:36:26 PM PDT 24
Peak memory 203960 kb
Host smart-562da9da-db2f-496a-86df-ae61a0d2d28f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14449
72383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.1444972383
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.max_length_in_transaction.1910039264
Short name T901
Test name
Test status
Simulation time 8499363267 ps
CPU time 9.1 seconds
Started Apr 23 02:36:14 PM PDT 24
Finished Apr 23 02:36:24 PM PDT 24
Peak memory 203976 kb
Host smart-e2a70de4-c53a-4761-b36f-753a6d1c25a4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1910039264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.1910039264
Directory /workspace/14.max_length_in_transaction/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.3760859233
Short name T552
Test name
Test status
Simulation time 8376262415 ps
CPU time 7.95 seconds
Started Apr 23 02:36:14 PM PDT 24
Finished Apr 23 02:36:23 PM PDT 24
Peak memory 204024 kb
Host smart-c98192bf-9c42-4fba-95ed-67548d3eba1f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3760859233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.3760859233
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.2615027098
Short name T528
Test name
Test status
Simulation time 8386467113 ps
CPU time 9.29 seconds
Started Apr 23 02:36:18 PM PDT 24
Finished Apr 23 02:36:28 PM PDT 24
Peak memory 203692 kb
Host smart-82b00f0a-7a00-4e4b-82f1-771f394a64d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26150
27098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.2615027098
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.3354332338
Short name T948
Test name
Test status
Simulation time 8374790165 ps
CPU time 8.12 seconds
Started Apr 23 02:36:19 PM PDT 24
Finished Apr 23 02:36:28 PM PDT 24
Peak memory 203968 kb
Host smart-beff9501-3422-40c7-9f9c-a57d9f764a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33543
32338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3354332338
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_enable.417425066
Short name T758
Test name
Test status
Simulation time 8390619451 ps
CPU time 8.22 seconds
Started Apr 23 02:36:18 PM PDT 24
Finished Apr 23 02:36:27 PM PDT 24
Peak memory 203968 kb
Host smart-82665142-de89-45ce-a519-6d84aa7e4405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41742
5066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.417425066
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.3078715302
Short name T731
Test name
Test status
Simulation time 61424423 ps
CPU time 1.15 seconds
Started Apr 23 02:36:14 PM PDT 24
Finished Apr 23 02:36:15 PM PDT 24
Peak memory 204108 kb
Host smart-cd0d1347-22ea-4b99-b545-85cc579b8c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30787
15302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.3078715302
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.416405294
Short name T1299
Test name
Test status
Simulation time 8471443036 ps
CPU time 7.85 seconds
Started Apr 23 02:36:15 PM PDT 24
Finished Apr 23 02:36:23 PM PDT 24
Peak memory 203972 kb
Host smart-f52939a5-95ef-476c-bb06-29f2afd0dedb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41640
5294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.416405294
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.1527587357
Short name T690
Test name
Test status
Simulation time 8373692074 ps
CPU time 7.82 seconds
Started Apr 23 02:36:15 PM PDT 24
Finished Apr 23 02:36:23 PM PDT 24
Peak memory 204092 kb
Host smart-0260ff92-6dfa-4576-9207-e393aa228d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15275
87357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1527587357
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2458597308
Short name T1092
Test name
Test status
Simulation time 8407494131 ps
CPU time 8.32 seconds
Started Apr 23 02:36:13 PM PDT 24
Finished Apr 23 02:36:22 PM PDT 24
Peak memory 204056 kb
Host smart-6c8e9743-a153-436f-965a-64703d7ed748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24585
97308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2458597308
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.353788269
Short name T487
Test name
Test status
Simulation time 8470179902 ps
CPU time 9.32 seconds
Started Apr 23 02:36:15 PM PDT 24
Finished Apr 23 02:36:25 PM PDT 24
Peak memory 204024 kb
Host smart-1106428e-2fc1-4d70-8deb-4efdbfaf9103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35378
8269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.353788269
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.1554202656
Short name T312
Test name
Test status
Simulation time 8368316666 ps
CPU time 7.73 seconds
Started Apr 23 02:36:19 PM PDT 24
Finished Apr 23 02:36:27 PM PDT 24
Peak memory 203964 kb
Host smart-04d939a4-a9e5-4583-849b-094a32283505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15542
02656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.1554202656
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.424456224
Short name T908
Test name
Test status
Simulation time 8407583143 ps
CPU time 8.81 seconds
Started Apr 23 02:36:14 PM PDT 24
Finished Apr 23 02:36:23 PM PDT 24
Peak memory 203972 kb
Host smart-f6de239d-7255-4436-96bd-7496b0d9c024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42445
6224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.424456224
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.794140608
Short name T1339
Test name
Test status
Simulation time 8409370837 ps
CPU time 8.04 seconds
Started Apr 23 02:36:12 PM PDT 24
Finished Apr 23 02:36:20 PM PDT 24
Peak memory 203996 kb
Host smart-40a5e03e-755f-4c45-84c3-8b8ab2984467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79414
0608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.794140608
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.243343002
Short name T483
Test name
Test status
Simulation time 8381138302 ps
CPU time 8.35 seconds
Started Apr 23 02:36:15 PM PDT 24
Finished Apr 23 02:36:24 PM PDT 24
Peak memory 204004 kb
Host smart-cc5a2b07-38cc-4eda-9f2a-146ae8e4681d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24334
3002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.243343002
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2595354259
Short name T851
Test name
Test status
Simulation time 37107307 ps
CPU time 0.62 seconds
Started Apr 23 02:36:16 PM PDT 24
Finished Apr 23 02:36:17 PM PDT 24
Peak memory 203944 kb
Host smart-7ba09ea8-f74c-4a7d-a54d-e4c67745866e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25953
54259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2595354259
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3856098034
Short name T1208
Test name
Test status
Simulation time 19678740641 ps
CPU time 34.68 seconds
Started Apr 23 02:36:14 PM PDT 24
Finished Apr 23 02:36:49 PM PDT 24
Peak memory 204316 kb
Host smart-c4b46dd9-6c87-458b-b980-509e0895e259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38560
98034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3856098034
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.4045634850
Short name T1186
Test name
Test status
Simulation time 8415237040 ps
CPU time 8.91 seconds
Started Apr 23 02:36:14 PM PDT 24
Finished Apr 23 02:36:24 PM PDT 24
Peak memory 204060 kb
Host smart-f93f9844-80c9-4b6e-9b24-58dd55fb2403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40456
34850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.4045634850
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.2712894114
Short name T669
Test name
Test status
Simulation time 8411607764 ps
CPU time 7.49 seconds
Started Apr 23 02:36:13 PM PDT 24
Finished Apr 23 02:36:21 PM PDT 24
Peak memory 204024 kb
Host smart-8af75f7b-9115-44db-841c-164bc46335b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27128
94114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.2712894114
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.1243512009
Short name T1083
Test name
Test status
Simulation time 8413880786 ps
CPU time 7.98 seconds
Started Apr 23 02:36:16 PM PDT 24
Finished Apr 23 02:36:25 PM PDT 24
Peak memory 203980 kb
Host smart-6bfcb0d6-28cb-4eb4-9c0e-27abc95b825b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12435
12009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.1243512009
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.4031300192
Short name T436
Test name
Test status
Simulation time 8395306200 ps
CPU time 9.71 seconds
Started Apr 23 02:36:15 PM PDT 24
Finished Apr 23 02:36:26 PM PDT 24
Peak memory 204004 kb
Host smart-e15da38e-fd92-488a-ae24-4a5dc964befa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40313
00192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.4031300192
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.1992564778
Short name T824
Test name
Test status
Simulation time 8372921975 ps
CPU time 8.54 seconds
Started Apr 23 02:36:15 PM PDT 24
Finished Apr 23 02:36:25 PM PDT 24
Peak memory 204024 kb
Host smart-f1407720-7b55-4d17-b373-93a347177bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19925
64778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.1992564778
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.812018900
Short name T147
Test name
Test status
Simulation time 8432708528 ps
CPU time 7.81 seconds
Started Apr 23 02:36:13 PM PDT 24
Finished Apr 23 02:36:21 PM PDT 24
Peak memory 204032 kb
Host smart-add223bc-1877-4f9d-a1d4-3f3d8f4b63ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81201
8900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.812018900
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2401271326
Short name T1216
Test name
Test status
Simulation time 8399646313 ps
CPU time 8.51 seconds
Started Apr 23 02:36:17 PM PDT 24
Finished Apr 23 02:36:26 PM PDT 24
Peak memory 204044 kb
Host smart-4e68b3c3-2899-4c00-bf78-e4910bf7b3a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24012
71326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2401271326
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.3078172258
Short name T1132
Test name
Test status
Simulation time 8380018882 ps
CPU time 7.68 seconds
Started Apr 23 02:36:16 PM PDT 24
Finished Apr 23 02:36:24 PM PDT 24
Peak memory 204008 kb
Host smart-1b873b7c-8b6a-4098-a72b-659a90859f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30781
72258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.3078172258
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.2503989014
Short name T861
Test name
Test status
Simulation time 8464829648 ps
CPU time 8.62 seconds
Started Apr 23 02:36:21 PM PDT 24
Finished Apr 23 02:36:30 PM PDT 24
Peak memory 204024 kb
Host smart-3bed6235-4ea0-4b51-9ca7-39f31bb8e455
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2503989014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.2503989014
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.747207777
Short name T506
Test name
Test status
Simulation time 8376884967 ps
CPU time 9.3 seconds
Started Apr 23 02:36:21 PM PDT 24
Finished Apr 23 02:36:31 PM PDT 24
Peak memory 203996 kb
Host smart-54749f3a-5318-4cd5-b939-d7e0664c6f8c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=747207777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.747207777
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.2711915149
Short name T1000
Test name
Test status
Simulation time 8495413920 ps
CPU time 8.49 seconds
Started Apr 23 02:36:23 PM PDT 24
Finished Apr 23 02:36:32 PM PDT 24
Peak memory 203964 kb
Host smart-b287e216-3c65-44bb-b7eb-e5172510c193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27119
15149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.2711915149
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.3392722723
Short name T348
Test name
Test status
Simulation time 8400324939 ps
CPU time 8.09 seconds
Started Apr 23 02:36:20 PM PDT 24
Finished Apr 23 02:36:29 PM PDT 24
Peak memory 203988 kb
Host smart-8c300d4a-9559-40eb-a10d-f831ca62a758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33927
22723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.3392722723
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_enable.3709019722
Short name T675
Test name
Test status
Simulation time 8372606989 ps
CPU time 8.31 seconds
Started Apr 23 02:36:17 PM PDT 24
Finished Apr 23 02:36:26 PM PDT 24
Peak memory 204024 kb
Host smart-fa07fb6b-ebd5-4bc2-8aad-ad5cdb536faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37090
19722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.3709019722
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.3343644646
Short name T430
Test name
Test status
Simulation time 81595200 ps
CPU time 1.4 seconds
Started Apr 23 02:36:17 PM PDT 24
Finished Apr 23 02:36:19 PM PDT 24
Peak memory 204040 kb
Host smart-28c2b458-3152-469a-bf65-398ec113f373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33436
44646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.3343644646
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.1864841729
Short name T606
Test name
Test status
Simulation time 8450960005 ps
CPU time 8.03 seconds
Started Apr 23 02:36:22 PM PDT 24
Finished Apr 23 02:36:30 PM PDT 24
Peak memory 204028 kb
Host smart-f86457a0-a37a-402c-b3d5-f498a7c737c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18648
41729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.1864841729
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.3993393908
Short name T878
Test name
Test status
Simulation time 8370909783 ps
CPU time 7.98 seconds
Started Apr 23 02:36:24 PM PDT 24
Finished Apr 23 02:36:33 PM PDT 24
Peak memory 203980 kb
Host smart-4e48f6d9-f4dc-4c66-bb9c-130a201b9005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39933
93908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.3993393908
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3738636865
Short name T1138
Test name
Test status
Simulation time 8437470232 ps
CPU time 9.52 seconds
Started Apr 23 02:36:17 PM PDT 24
Finished Apr 23 02:36:27 PM PDT 24
Peak memory 204012 kb
Host smart-79d536f8-55c2-4d2d-b157-12daa0628db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37386
36865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3738636865
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.130979260
Short name T820
Test name
Test status
Simulation time 8369774248 ps
CPU time 8.89 seconds
Started Apr 23 02:36:19 PM PDT 24
Finished Apr 23 02:36:29 PM PDT 24
Peak memory 204024 kb
Host smart-9bbae0b3-2bc9-47bd-aa0e-fd1255fbbd6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13097
9260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.130979260
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.1514664869
Short name T106
Test name
Test status
Simulation time 8452288732 ps
CPU time 10.17 seconds
Started Apr 23 02:36:20 PM PDT 24
Finished Apr 23 02:36:31 PM PDT 24
Peak memory 204036 kb
Host smart-d7feeb0f-0ce5-4c92-8ff6-0e038866ca1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15146
64869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1514664869
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.2617985697
Short name T549
Test name
Test status
Simulation time 8391529000 ps
CPU time 8.6 seconds
Started Apr 23 02:36:19 PM PDT 24
Finished Apr 23 02:36:28 PM PDT 24
Peak memory 203992 kb
Host smart-8ef66839-39b5-4b6f-8dbc-83ddb85341e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26179
85697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.2617985697
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.3922693413
Short name T313
Test name
Test status
Simulation time 8386710739 ps
CPU time 8.5 seconds
Started Apr 23 02:36:19 PM PDT 24
Finished Apr 23 02:36:29 PM PDT 24
Peak memory 204068 kb
Host smart-30b1867a-3be6-43c4-a1a4-b739744ddb44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39226
93413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.3922693413
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.2653233645
Short name T172
Test name
Test status
Simulation time 8417808977 ps
CPU time 9.64 seconds
Started Apr 23 02:36:23 PM PDT 24
Finished Apr 23 02:36:33 PM PDT 24
Peak memory 204012 kb
Host smart-d1f048eb-d9f4-45b0-a169-fd6564158b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26532
33645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.2653233645
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.878009649
Short name T581
Test name
Test status
Simulation time 8424186717 ps
CPU time 7.59 seconds
Started Apr 23 02:36:24 PM PDT 24
Finished Apr 23 02:36:32 PM PDT 24
Peak memory 204008 kb
Host smart-ff0ae026-76e7-4bea-9206-7109ea8984a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87800
9649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.878009649
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.2502636745
Short name T468
Test name
Test status
Simulation time 127159000 ps
CPU time 0.72 seconds
Started Apr 23 02:36:24 PM PDT 24
Finished Apr 23 02:36:25 PM PDT 24
Peak memory 203892 kb
Host smart-13cd9bd3-f919-43c6-9b4c-ea29ac5e81cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25026
36745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.2502636745
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.1911703103
Short name T424
Test name
Test status
Simulation time 8410506073 ps
CPU time 7.57 seconds
Started Apr 23 02:36:18 PM PDT 24
Finished Apr 23 02:36:26 PM PDT 24
Peak memory 203668 kb
Host smart-32dcc6dc-6afb-4af4-bd5d-93427de2eb5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19117
03103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.1911703103
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.2424583313
Short name T852
Test name
Test status
Simulation time 8444790885 ps
CPU time 9.6 seconds
Started Apr 23 02:36:25 PM PDT 24
Finished Apr 23 02:36:35 PM PDT 24
Peak memory 203968 kb
Host smart-4832f0b1-da4b-42e8-ad03-615ad83f9a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24245
83313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.2424583313
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.172793103
Short name T292
Test name
Test status
Simulation time 8385251251 ps
CPU time 8.1 seconds
Started Apr 23 02:36:16 PM PDT 24
Finished Apr 23 02:36:25 PM PDT 24
Peak memory 204028 kb
Host smart-9a2fb3f8-43af-4366-8f0b-99ed4b0affe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17279
3103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.172793103
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.3499166240
Short name T180
Test name
Test status
Simulation time 8379004932 ps
CPU time 8.17 seconds
Started Apr 23 02:36:23 PM PDT 24
Finished Apr 23 02:36:32 PM PDT 24
Peak memory 204052 kb
Host smart-95b76736-8753-4d6d-ad8c-bd4a161b09df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34991
66240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.3499166240
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.2828505126
Short name T1207
Test name
Test status
Simulation time 8450577890 ps
CPU time 9.16 seconds
Started Apr 23 02:36:23 PM PDT 24
Finished Apr 23 02:36:33 PM PDT 24
Peak memory 203960 kb
Host smart-dca5af1e-19c8-4b12-83f7-44da35d8e3ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28285
05126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.2828505126
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.2482931945
Short name T320
Test name
Test status
Simulation time 8430945227 ps
CPU time 8.47 seconds
Started Apr 23 02:36:21 PM PDT 24
Finished Apr 23 02:36:29 PM PDT 24
Peak memory 203944 kb
Host smart-464d7d82-e6b8-46cf-beee-1850e45dccd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24829
31945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.2482931945
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.3395320534
Short name T718
Test name
Test status
Simulation time 8415383776 ps
CPU time 7.88 seconds
Started Apr 23 02:36:19 PM PDT 24
Finished Apr 23 02:36:27 PM PDT 24
Peak memory 203988 kb
Host smart-09f89102-7dbd-4520-b151-5e8f76a166ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33953
20534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.3395320534
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.2925822600
Short name T1307
Test name
Test status
Simulation time 8520818263 ps
CPU time 7.86 seconds
Started Apr 23 02:36:28 PM PDT 24
Finished Apr 23 02:36:36 PM PDT 24
Peak memory 203960 kb
Host smart-04e9a31a-5469-4e79-b35d-319fdfacbd3e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2925822600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.2925822600
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.min_length_in_transaction.2263636513
Short name T767
Test name
Test status
Simulation time 8377445059 ps
CPU time 9.24 seconds
Started Apr 23 02:36:28 PM PDT 24
Finished Apr 23 02:36:37 PM PDT 24
Peak memory 204064 kb
Host smart-b7e46ced-5c3e-430c-92f7-bea7513c97aa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2263636513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.2263636513
Directory /workspace/16.min_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.69588621
Short name T148
Test name
Test status
Simulation time 8407725688 ps
CPU time 8.17 seconds
Started Apr 23 02:36:29 PM PDT 24
Finished Apr 23 02:36:37 PM PDT 24
Peak memory 204012 kb
Host smart-7babfb57-9cbf-4881-b0db-3fcdd813df74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69588
621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.69588621
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2700984782
Short name T1257
Test name
Test status
Simulation time 8385393815 ps
CPU time 8.73 seconds
Started Apr 23 02:36:26 PM PDT 24
Finished Apr 23 02:36:35 PM PDT 24
Peak memory 203976 kb
Host smart-09a13bca-2380-4c00-8e32-716f193f1e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27009
84782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2700984782
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_enable.2718720127
Short name T865
Test name
Test status
Simulation time 8375830557 ps
CPU time 8.12 seconds
Started Apr 23 02:36:26 PM PDT 24
Finished Apr 23 02:36:35 PM PDT 24
Peak memory 204052 kb
Host smart-54e56bcf-967e-456f-a58a-a9da1f618406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27187
20127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.2718720127
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.464339747
Short name T755
Test name
Test status
Simulation time 222223275 ps
CPU time 2.11 seconds
Started Apr 23 02:36:24 PM PDT 24
Finished Apr 23 02:36:27 PM PDT 24
Peak memory 204128 kb
Host smart-fbbb86a8-0c46-4a02-9641-12ad94337621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46433
9747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.464339747
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.4113314946
Short name T835
Test name
Test status
Simulation time 8367336746 ps
CPU time 8.34 seconds
Started Apr 23 02:36:24 PM PDT 24
Finished Apr 23 02:36:33 PM PDT 24
Peak memory 203976 kb
Host smart-a3f31c1b-651a-49d3-aaab-af9511f97314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41133
14946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.4113314946
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.4206957602
Short name T87
Test name
Test status
Simulation time 8463288011 ps
CPU time 10.6 seconds
Started Apr 23 02:36:24 PM PDT 24
Finished Apr 23 02:36:35 PM PDT 24
Peak memory 204048 kb
Host smart-ed30a7eb-50b5-4ae5-a5d2-86fdb0852b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42069
57602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.4206957602
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.1486144851
Short name T368
Test name
Test status
Simulation time 8414528218 ps
CPU time 7.77 seconds
Started Apr 23 02:36:25 PM PDT 24
Finished Apr 23 02:36:33 PM PDT 24
Peak memory 204036 kb
Host smart-479c0f47-ef27-4d6b-8879-01d77c5f1f63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14861
44851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1486144851
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.2877834791
Short name T448
Test name
Test status
Simulation time 8373700196 ps
CPU time 8.06 seconds
Started Apr 23 02:36:25 PM PDT 24
Finished Apr 23 02:36:34 PM PDT 24
Peak memory 204032 kb
Host smart-acf630b1-ac42-4a3d-b04e-c52bfd0db1cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28778
34791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.2877834791
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.2805966809
Short name T1274
Test name
Test status
Simulation time 8411986674 ps
CPU time 7.93 seconds
Started Apr 23 02:36:26 PM PDT 24
Finished Apr 23 02:36:34 PM PDT 24
Peak memory 204008 kb
Host smart-3b8c691c-e4c3-4721-84af-28bee1a0630d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28059
66809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.2805966809
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.4038774741
Short name T1087
Test name
Test status
Simulation time 8411585588 ps
CPU time 9.72 seconds
Started Apr 23 02:36:25 PM PDT 24
Finished Apr 23 02:36:35 PM PDT 24
Peak memory 204028 kb
Host smart-c6b9875e-1bd5-490a-a94a-032da8827577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40387
74741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.4038774741
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.2554186524
Short name T957
Test name
Test status
Simulation time 53791554 ps
CPU time 0.62 seconds
Started Apr 23 02:36:26 PM PDT 24
Finished Apr 23 02:36:27 PM PDT 24
Peak memory 203872 kb
Host smart-12e8c6e1-0974-4ba8-9151-e338f3ee3219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25541
86524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.2554186524
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.2334104908
Short name T1015
Test name
Test status
Simulation time 26634062300 ps
CPU time 50.2 seconds
Started Apr 23 02:36:28 PM PDT 24
Finished Apr 23 02:37:19 PM PDT 24
Peak memory 204324 kb
Host smart-deaf3fc3-6d5c-46b3-912e-61d7f38c4f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23341
04908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.2334104908
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.1177477369
Short name T515
Test name
Test status
Simulation time 8379428222 ps
CPU time 8.23 seconds
Started Apr 23 02:36:26 PM PDT 24
Finished Apr 23 02:36:35 PM PDT 24
Peak memory 204048 kb
Host smart-3366d1b5-f106-4b1b-9727-651c58ca6e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11774
77369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.1177477369
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.94571492
Short name T737
Test name
Test status
Simulation time 8491818623 ps
CPU time 7.79 seconds
Started Apr 23 02:36:28 PM PDT 24
Finished Apr 23 02:36:37 PM PDT 24
Peak memory 203976 kb
Host smart-fb71a838-a38d-4a07-9079-32238cf0b2de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94571
492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.94571492
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.3010303897
Short name T522
Test name
Test status
Simulation time 8400227060 ps
CPU time 7.69 seconds
Started Apr 23 02:36:28 PM PDT 24
Finished Apr 23 02:36:36 PM PDT 24
Peak memory 203972 kb
Host smart-28a22ef4-3191-4526-8f5e-df605684fa33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30103
03897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.3010303897
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.1707899062
Short name T570
Test name
Test status
Simulation time 8400416285 ps
CPU time 9.41 seconds
Started Apr 23 02:36:25 PM PDT 24
Finished Apr 23 02:36:35 PM PDT 24
Peak memory 204000 kb
Host smart-64b2bf51-ac88-46c7-ba8a-286f0f7d0629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17078
99062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.1707899062
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.1581648146
Short name T1268
Test name
Test status
Simulation time 8375386754 ps
CPU time 7.26 seconds
Started Apr 23 02:36:23 PM PDT 24
Finished Apr 23 02:36:31 PM PDT 24
Peak memory 203948 kb
Host smart-b4e6616e-5b95-4876-8677-04178f7c0a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15816
48146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.1581648146
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.2813559292
Short name T1130
Test name
Test status
Simulation time 8488134429 ps
CPU time 8.59 seconds
Started Apr 23 02:36:22 PM PDT 24
Finished Apr 23 02:36:31 PM PDT 24
Peak memory 204064 kb
Host smart-821d5a0c-d9fd-4297-91b9-ab766487a8b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28135
59292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2813559292
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2132154637
Short name T698
Test name
Test status
Simulation time 8416955079 ps
CPU time 8.01 seconds
Started Apr 23 02:36:26 PM PDT 24
Finished Apr 23 02:36:34 PM PDT 24
Peak memory 203952 kb
Host smart-e5548d00-30b5-49bd-98af-15541a09b8d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21321
54637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2132154637
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.1091204844
Short name T1121
Test name
Test status
Simulation time 8381646231 ps
CPU time 8.19 seconds
Started Apr 23 02:36:33 PM PDT 24
Finished Apr 23 02:36:42 PM PDT 24
Peak memory 204052 kb
Host smart-1213b1d9-a84f-4b7f-8094-73a643938569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10912
04844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.1091204844
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.max_length_in_transaction.2813572889
Short name T695
Test name
Test status
Simulation time 8477403899 ps
CPU time 9.95 seconds
Started Apr 23 02:36:33 PM PDT 24
Finished Apr 23 02:36:43 PM PDT 24
Peak memory 204024 kb
Host smart-4674095a-fdb5-412a-8dc5-b1d94bef852c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2813572889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.2813572889
Directory /workspace/17.max_length_in_transaction/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.2508016878
Short name T892
Test name
Test status
Simulation time 8375232676 ps
CPU time 8.37 seconds
Started Apr 23 02:36:31 PM PDT 24
Finished Apr 23 02:36:40 PM PDT 24
Peak memory 204052 kb
Host smart-ca36292e-2a20-454b-b32b-755f8615ad8e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2508016878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.2508016878
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.1633244011
Short name T794
Test name
Test status
Simulation time 8423006259 ps
CPU time 7.48 seconds
Started Apr 23 02:36:34 PM PDT 24
Finished Apr 23 02:36:43 PM PDT 24
Peak memory 203988 kb
Host smart-226c4058-ca08-490d-b40b-09bf06ccf849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16332
44011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.1633244011
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.1572247281
Short name T572
Test name
Test status
Simulation time 8407464673 ps
CPU time 7.86 seconds
Started Apr 23 02:36:34 PM PDT 24
Finished Apr 23 02:36:43 PM PDT 24
Peak memory 203880 kb
Host smart-8533c468-7a66-4460-9009-5863a0c9fac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15722
47281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.1572247281
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_enable.1702169952
Short name T498
Test name
Test status
Simulation time 8382823650 ps
CPU time 7.98 seconds
Started Apr 23 02:36:34 PM PDT 24
Finished Apr 23 02:36:43 PM PDT 24
Peak memory 203928 kb
Host smart-20175a1c-56ca-41e3-98ef-29a57258a1a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17021
69952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.1702169952
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.1038243921
Short name T406
Test name
Test status
Simulation time 56952800 ps
CPU time 1.14 seconds
Started Apr 23 02:36:33 PM PDT 24
Finished Apr 23 02:36:35 PM PDT 24
Peak memory 204188 kb
Host smart-512b7f8e-01e7-4baf-8d67-ae85608e506f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10382
43921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.1038243921
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.1319069462
Short name T417
Test name
Test status
Simulation time 8381438188 ps
CPU time 9.05 seconds
Started Apr 23 02:36:33 PM PDT 24
Finished Apr 23 02:36:43 PM PDT 24
Peak memory 204008 kb
Host smart-41d111c5-80c1-4e3e-8d23-3497ceb4d5be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13190
69462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.1319069462
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3436108364
Short name T589
Test name
Test status
Simulation time 8372942768 ps
CPU time 10.06 seconds
Started Apr 23 02:36:34 PM PDT 24
Finished Apr 23 02:36:45 PM PDT 24
Peak memory 203988 kb
Host smart-7665058c-86e0-422e-b445-46a1efa3fdd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34361
08364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3436108364
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1997818018
Short name T644
Test name
Test status
Simulation time 8428337345 ps
CPU time 7.82 seconds
Started Apr 23 02:36:34 PM PDT 24
Finished Apr 23 02:36:43 PM PDT 24
Peak memory 204060 kb
Host smart-9e85f44d-2bad-4245-a930-4e91c7d89521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19978
18018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1997818018
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.243626250
Short name T939
Test name
Test status
Simulation time 8437958929 ps
CPU time 7.74 seconds
Started Apr 23 02:36:28 PM PDT 24
Finished Apr 23 02:36:36 PM PDT 24
Peak memory 204028 kb
Host smart-277a933d-2504-44a4-88f9-12c9ded80a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24362
6250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.243626250
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.982860284
Short name T1080
Test name
Test status
Simulation time 8383295477 ps
CPU time 8.46 seconds
Started Apr 23 02:36:29 PM PDT 24
Finished Apr 23 02:36:38 PM PDT 24
Peak memory 204036 kb
Host smart-445a4ad2-a381-4b11-91ba-8737e6dc20c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98286
0284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.982860284
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.3844119192
Short name T887
Test name
Test status
Simulation time 8431481921 ps
CPU time 9.2 seconds
Started Apr 23 02:36:31 PM PDT 24
Finished Apr 23 02:36:41 PM PDT 24
Peak memory 204020 kb
Host smart-75342720-e432-49eb-9079-805835cf7d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38441
19192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.3844119192
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.374814484
Short name T1129
Test name
Test status
Simulation time 8468355861 ps
CPU time 7.51 seconds
Started Apr 23 02:36:29 PM PDT 24
Finished Apr 23 02:36:37 PM PDT 24
Peak memory 204056 kb
Host smart-e0409e4f-0126-46c3-b426-bf39b550a1d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37481
4484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.374814484
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.3942433889
Short name T671
Test name
Test status
Simulation time 8430251638 ps
CPU time 7.59 seconds
Started Apr 23 02:36:28 PM PDT 24
Finished Apr 23 02:36:37 PM PDT 24
Peak memory 203984 kb
Host smart-db75b928-a8f0-4516-b6af-e33e72f347ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39424
33889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.3942433889
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1119951673
Short name T1122
Test name
Test status
Simulation time 8407117440 ps
CPU time 8.18 seconds
Started Apr 23 02:36:32 PM PDT 24
Finished Apr 23 02:36:41 PM PDT 24
Peak memory 204060 kb
Host smart-7c6a20b1-c108-4e0a-9c2f-504be46b97d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11199
51673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1119951673
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.600378373
Short name T979
Test name
Test status
Simulation time 8387771180 ps
CPU time 7.8 seconds
Started Apr 23 02:36:31 PM PDT 24
Finished Apr 23 02:36:39 PM PDT 24
Peak memory 204008 kb
Host smart-3a9c04e0-942c-4b05-a82c-1e453bf0c617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60037
8373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.600378373
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.4018817358
Short name T1105
Test name
Test status
Simulation time 52971042 ps
CPU time 0.67 seconds
Started Apr 23 02:36:32 PM PDT 24
Finished Apr 23 02:36:33 PM PDT 24
Peak memory 203864 kb
Host smart-02ba8ad4-a6ff-409d-b6ed-c9e92397dd40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40188
17358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.4018817358
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3884542250
Short name T1367
Test name
Test status
Simulation time 18123210172 ps
CPU time 31.45 seconds
Started Apr 23 02:36:31 PM PDT 24
Finished Apr 23 02:37:03 PM PDT 24
Peak memory 204312 kb
Host smart-b1565338-8050-4fc9-a9fe-e7c37f507e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38845
42250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3884542250
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.2940558140
Short name T986
Test name
Test status
Simulation time 8384559082 ps
CPU time 8.82 seconds
Started Apr 23 02:36:33 PM PDT 24
Finished Apr 23 02:36:42 PM PDT 24
Peak memory 203968 kb
Host smart-52b5bea0-9c64-4e45-8e5c-b0852200b165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29405
58140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.2940558140
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.566963513
Short name T909
Test name
Test status
Simulation time 8420294109 ps
CPU time 7.98 seconds
Started Apr 23 02:36:34 PM PDT 24
Finished Apr 23 02:36:43 PM PDT 24
Peak memory 204012 kb
Host smart-dea7fa6b-fe21-4c2b-b098-96181c7c5b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56696
3513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.566963513
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.3070018523
Short name T609
Test name
Test status
Simulation time 8423422647 ps
CPU time 8.82 seconds
Started Apr 23 02:36:34 PM PDT 24
Finished Apr 23 02:36:43 PM PDT 24
Peak memory 204040 kb
Host smart-6ad8853f-bb09-4891-837d-1f6f10ec2fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30700
18523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.3070018523
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.1647056049
Short name T177
Test name
Test status
Simulation time 8371926428 ps
CPU time 8.57 seconds
Started Apr 23 02:36:33 PM PDT 24
Finished Apr 23 02:36:42 PM PDT 24
Peak memory 203980 kb
Host smart-46ef5033-5257-4ebe-8f1d-f532fbd8bb12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16470
56049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.1647056049
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.2431978006
Short name T1368
Test name
Test status
Simulation time 8372035479 ps
CPU time 8.12 seconds
Started Apr 23 02:36:33 PM PDT 24
Finished Apr 23 02:36:42 PM PDT 24
Peak memory 204008 kb
Host smart-5b9ca0f0-d6ec-4867-b6ee-48998f844792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24319
78006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2431978006
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.1548837497
Short name T1147
Test name
Test status
Simulation time 8476668115 ps
CPU time 8.02 seconds
Started Apr 23 02:36:28 PM PDT 24
Finished Apr 23 02:36:36 PM PDT 24
Peak memory 204032 kb
Host smart-3d27c5ad-9e5a-46ce-b679-e06f2c077422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15488
37497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.1548837497
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.4167397445
Short name T608
Test name
Test status
Simulation time 8401498322 ps
CPU time 8.05 seconds
Started Apr 23 02:36:31 PM PDT 24
Finished Apr 23 02:36:39 PM PDT 24
Peak memory 204000 kb
Host smart-e0f41fd7-77f4-435d-afca-ef9a017ecab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41673
97445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.4167397445
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.1241087967
Short name T1006
Test name
Test status
Simulation time 8427276641 ps
CPU time 9.98 seconds
Started Apr 23 02:36:34 PM PDT 24
Finished Apr 23 02:36:45 PM PDT 24
Peak memory 204056 kb
Host smart-be91ad3b-4d79-4577-a5be-d796114dbe3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12410
87967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.1241087967
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.2225944076
Short name T827
Test name
Test status
Simulation time 8463145881 ps
CPU time 8.02 seconds
Started Apr 23 02:36:38 PM PDT 24
Finished Apr 23 02:36:47 PM PDT 24
Peak memory 204008 kb
Host smart-eb2c67af-0bb5-4ce3-9142-d0e9c7aedc0c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2225944076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.2225944076
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.4225169463
Short name T766
Test name
Test status
Simulation time 8381206477 ps
CPU time 8.11 seconds
Started Apr 23 02:36:34 PM PDT 24
Finished Apr 23 02:36:44 PM PDT 24
Peak memory 203948 kb
Host smart-bc6f2079-e696-4b0e-af12-27bbdd536900
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4225169463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.4225169463
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.1002945426
Short name T299
Test name
Test status
Simulation time 8405143079 ps
CPU time 8.26 seconds
Started Apr 23 02:36:37 PM PDT 24
Finished Apr 23 02:36:46 PM PDT 24
Peak memory 203352 kb
Host smart-fec77c08-ae05-4bc0-bbdf-9b7cfa76e842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10029
45426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.1002945426
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2038600375
Short name T478
Test name
Test status
Simulation time 8407742035 ps
CPU time 7.61 seconds
Started Apr 23 02:36:39 PM PDT 24
Finished Apr 23 02:36:48 PM PDT 24
Peak memory 204060 kb
Host smart-7baab653-3448-4fb5-9af2-d29aaf484efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20386
00375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2038600375
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_enable.2455311320
Short name T816
Test name
Test status
Simulation time 8385186781 ps
CPU time 7.65 seconds
Started Apr 23 02:36:32 PM PDT 24
Finished Apr 23 02:36:40 PM PDT 24
Peak memory 204024 kb
Host smart-2978b857-90aa-404c-b990-9139dfab725e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24553
11320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.2455311320
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.1859755884
Short name T546
Test name
Test status
Simulation time 70592407 ps
CPU time 1.81 seconds
Started Apr 23 02:36:39 PM PDT 24
Finished Apr 23 02:36:42 PM PDT 24
Peak memory 204148 kb
Host smart-39ef1de8-aab6-47ce-9c07-bc96cdadfc3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18597
55884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.1859755884
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.3787308466
Short name T1320
Test name
Test status
Simulation time 8479104304 ps
CPU time 8.04 seconds
Started Apr 23 02:36:35 PM PDT 24
Finished Apr 23 02:36:44 PM PDT 24
Peak memory 204028 kb
Host smart-88859cdb-b439-457a-a90f-5e5f51c738ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37873
08466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.3787308466
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.3467170043
Short name T190
Test name
Test status
Simulation time 8394899521 ps
CPU time 10.39 seconds
Started Apr 23 02:36:35 PM PDT 24
Finished Apr 23 02:36:46 PM PDT 24
Peak memory 204016 kb
Host smart-5e164a21-29a4-430b-a202-99292a62431a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34671
70043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3467170043
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.128544206
Short name T414
Test name
Test status
Simulation time 8417474451 ps
CPU time 7.75 seconds
Started Apr 23 02:36:34 PM PDT 24
Finished Apr 23 02:36:42 PM PDT 24
Peak memory 203988 kb
Host smart-076c33b4-0224-4f06-ada9-4e419435a550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12854
4206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.128544206
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.1935820192
Short name T444
Test name
Test status
Simulation time 8410350487 ps
CPU time 8.16 seconds
Started Apr 23 02:36:34 PM PDT 24
Finished Apr 23 02:36:44 PM PDT 24
Peak memory 204008 kb
Host smart-2553ca83-8e53-429b-ad8c-aa4249630946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19358
20192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1935820192
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.647822192
Short name T479
Test name
Test status
Simulation time 8369366379 ps
CPU time 7.59 seconds
Started Apr 23 02:36:37 PM PDT 24
Finished Apr 23 02:36:46 PM PDT 24
Peak memory 203356 kb
Host smart-ce2ad7b1-e3b3-4eb8-aabf-00ed0d6c3e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64782
2192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.647822192
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1962912683
Short name T1341
Test name
Test status
Simulation time 8425124509 ps
CPU time 7.75 seconds
Started Apr 23 02:36:36 PM PDT 24
Finished Apr 23 02:36:45 PM PDT 24
Peak memory 204048 kb
Host smart-62a7cf4f-3a56-4bb5-9cba-924300111555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19629
12683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1962912683
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.4070398765
Short name T31
Test name
Test status
Simulation time 8401023059 ps
CPU time 8.52 seconds
Started Apr 23 02:36:37 PM PDT 24
Finished Apr 23 02:36:46 PM PDT 24
Peak memory 203356 kb
Host smart-9097449b-05fe-4b08-8050-25c6ea0e7ea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40703
98765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.4070398765
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.4120890286
Short name T484
Test name
Test status
Simulation time 8397351858 ps
CPU time 8.35 seconds
Started Apr 23 02:36:37 PM PDT 24
Finished Apr 23 02:36:47 PM PDT 24
Peak memory 204044 kb
Host smart-09dcbf55-c58b-4467-9d44-d71627b8fad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41208
90286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.4120890286
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3548715206
Short name T44
Test name
Test status
Simulation time 51266220 ps
CPU time 0.68 seconds
Started Apr 23 02:36:37 PM PDT 24
Finished Apr 23 02:36:38 PM PDT 24
Peak memory 203872 kb
Host smart-f1bfac89-c51a-4175-badf-8a1cb4f302ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35487
15206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3548715206
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.550737947
Short name T1182
Test name
Test status
Simulation time 15917648021 ps
CPU time 29.9 seconds
Started Apr 23 02:36:35 PM PDT 24
Finished Apr 23 02:37:06 PM PDT 24
Peak memory 204308 kb
Host smart-70f3e3e7-8695-446d-809e-c6c66b76db06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55073
7947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.550737947
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.1577348028
Short name T1100
Test name
Test status
Simulation time 8395607347 ps
CPU time 9.25 seconds
Started Apr 23 02:36:35 PM PDT 24
Finished Apr 23 02:36:45 PM PDT 24
Peak memory 204032 kb
Host smart-83076928-c32b-4781-9746-af9e1d1d55c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15773
48028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.1577348028
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.2518036496
Short name T1250
Test name
Test status
Simulation time 8435443122 ps
CPU time 8.02 seconds
Started Apr 23 02:36:37 PM PDT 24
Finished Apr 23 02:36:46 PM PDT 24
Peak memory 204052 kb
Host smart-94abf9ef-9723-42d4-9cff-f45918d517ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25180
36496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.2518036496
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.3054185551
Short name T1244
Test name
Test status
Simulation time 8409430507 ps
CPU time 7.82 seconds
Started Apr 23 02:36:36 PM PDT 24
Finished Apr 23 02:36:44 PM PDT 24
Peak memory 204032 kb
Host smart-1f34e39a-5aad-4f54-980f-3903ca164c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30541
85551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.3054185551
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.2441257715
Short name T407
Test name
Test status
Simulation time 8413762595 ps
CPU time 7.64 seconds
Started Apr 23 02:36:34 PM PDT 24
Finished Apr 23 02:36:43 PM PDT 24
Peak memory 203988 kb
Host smart-b263c668-1913-49c3-a72e-cb10a40daf93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24412
57715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.2441257715
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.4292714071
Short name T396
Test name
Test status
Simulation time 8367999236 ps
CPU time 7.67 seconds
Started Apr 23 02:36:35 PM PDT 24
Finished Apr 23 02:36:44 PM PDT 24
Peak memory 204012 kb
Host smart-604faf46-bdd1-48b0-8c93-335e9a6e94ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42927
14071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.4292714071
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.1674049553
Short name T611
Test name
Test status
Simulation time 8440957837 ps
CPU time 9.1 seconds
Started Apr 23 02:36:32 PM PDT 24
Finished Apr 23 02:36:41 PM PDT 24
Peak memory 204064 kb
Host smart-f12d47f5-4fa3-429c-ae63-5cb403817d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16740
49553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.1674049553
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.557245989
Short name T1265
Test name
Test status
Simulation time 8395645435 ps
CPU time 8.48 seconds
Started Apr 23 02:36:38 PM PDT 24
Finished Apr 23 02:36:47 PM PDT 24
Peak memory 203984 kb
Host smart-7b89e699-0c39-485a-93ed-5951c4cfd35b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55724
5989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.557245989
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.524479960
Short name T485
Test name
Test status
Simulation time 8440201115 ps
CPU time 8.35 seconds
Started Apr 23 02:36:37 PM PDT 24
Finished Apr 23 02:36:47 PM PDT 24
Peak memory 204044 kb
Host smart-560e0bd4-010a-44aa-ae47-1639ee7c9b01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52447
9960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.524479960
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.3825788207
Short name T1287
Test name
Test status
Simulation time 8475753355 ps
CPU time 8.24 seconds
Started Apr 23 02:36:41 PM PDT 24
Finished Apr 23 02:36:50 PM PDT 24
Peak memory 204036 kb
Host smart-797175f6-fc4a-406e-892d-16a65bef6569
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3825788207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.3825788207
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.4229246659
Short name T995
Test name
Test status
Simulation time 8384298029 ps
CPU time 7.77 seconds
Started Apr 23 02:36:39 PM PDT 24
Finished Apr 23 02:36:48 PM PDT 24
Peak memory 204004 kb
Host smart-1bdc312f-bb24-4e30-a914-097bb781f1f6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4229246659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.4229246659
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.119591037
Short name T937
Test name
Test status
Simulation time 8483723033 ps
CPU time 8.15 seconds
Started Apr 23 02:36:40 PM PDT 24
Finished Apr 23 02:36:49 PM PDT 24
Peak memory 204056 kb
Host smart-1f16d4d5-db8e-4b18-bb76-cff87a38aa46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11959
1037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.119591037
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.2532909325
Short name T16
Test name
Test status
Simulation time 8387861500 ps
CPU time 7.64 seconds
Started Apr 23 02:36:35 PM PDT 24
Finished Apr 23 02:36:44 PM PDT 24
Peak memory 204020 kb
Host smart-c0c8864b-cd47-46e2-8a28-51ee6c79905a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25329
09325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.2532909325
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_enable.3598997288
Short name T1248
Test name
Test status
Simulation time 8405156350 ps
CPU time 8.2 seconds
Started Apr 23 02:36:36 PM PDT 24
Finished Apr 23 02:36:45 PM PDT 24
Peak memory 204024 kb
Host smart-7fefecdb-fafc-4d2c-a095-20eef24ffb96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35989
97288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.3598997288
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.1345563152
Short name T1026
Test name
Test status
Simulation time 92624343 ps
CPU time 1.08 seconds
Started Apr 23 02:36:38 PM PDT 24
Finished Apr 23 02:36:40 PM PDT 24
Peak memory 204048 kb
Host smart-d9caf9e8-a8d5-49e6-9709-e85e9d802ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13455
63152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.1345563152
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.2902067412
Short name T1072
Test name
Test status
Simulation time 8440497280 ps
CPU time 8.21 seconds
Started Apr 23 02:36:41 PM PDT 24
Finished Apr 23 02:36:50 PM PDT 24
Peak memory 204008 kb
Host smart-4f4fc9bb-a0e0-4ebc-b457-61ee5ec580ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29020
67412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.2902067412
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.767825795
Short name T197
Test name
Test status
Simulation time 8369443014 ps
CPU time 7.45 seconds
Started Apr 23 02:36:38 PM PDT 24
Finished Apr 23 02:36:47 PM PDT 24
Peak memory 204024 kb
Host smart-3d7036d1-80b0-489d-8c08-112e89fd22cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76782
5795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.767825795
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.1945855855
Short name T1267
Test name
Test status
Simulation time 8464059910 ps
CPU time 8.23 seconds
Started Apr 23 02:36:40 PM PDT 24
Finished Apr 23 02:36:49 PM PDT 24
Peak memory 204064 kb
Host smart-9bddc42d-90db-454a-ab37-f87c0680d626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19458
55855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.1945855855
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.3507223333
Short name T799
Test name
Test status
Simulation time 8419333586 ps
CPU time 7.84 seconds
Started Apr 23 02:36:39 PM PDT 24
Finished Apr 23 02:36:48 PM PDT 24
Peak memory 204048 kb
Host smart-c331961d-fe2f-4e8b-9a71-c182afeb27dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35072
23333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.3507223333
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.1603737508
Short name T683
Test name
Test status
Simulation time 8372018013 ps
CPU time 7.79 seconds
Started Apr 23 02:36:39 PM PDT 24
Finished Apr 23 02:36:48 PM PDT 24
Peak memory 203988 kb
Host smart-5c19b5b9-5743-4fb5-a28a-83a6be811dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16037
37508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.1603737508
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.1104481953
Short name T1375
Test name
Test status
Simulation time 8437289392 ps
CPU time 8.83 seconds
Started Apr 23 02:36:36 PM PDT 24
Finished Apr 23 02:36:46 PM PDT 24
Peak memory 204048 kb
Host smart-6a67fc7e-4435-4048-b4cc-59ef503a688a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11044
81953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.1104481953
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.3928847598
Short name T489
Test name
Test status
Simulation time 8448409132 ps
CPU time 7.85 seconds
Started Apr 23 02:36:37 PM PDT 24
Finished Apr 23 02:36:46 PM PDT 24
Peak memory 203968 kb
Host smart-a4cca36e-3890-49d7-b182-78f7eee12133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39288
47598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.3928847598
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.4175642213
Short name T352
Test name
Test status
Simulation time 8404716679 ps
CPU time 8.7 seconds
Started Apr 23 02:36:37 PM PDT 24
Finished Apr 23 02:36:47 PM PDT 24
Peak memory 204028 kb
Host smart-1274ad75-46ca-4424-8a45-fafe0f1e5524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41756
42213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.4175642213
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.3914008810
Short name T639
Test name
Test status
Simulation time 8382967170 ps
CPU time 7.48 seconds
Started Apr 23 02:36:39 PM PDT 24
Finished Apr 23 02:36:48 PM PDT 24
Peak memory 203964 kb
Host smart-b9c0a949-a411-4690-b28a-6551486c088f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39140
08810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.3914008810
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.2722523930
Short name T1338
Test name
Test status
Simulation time 206380639 ps
CPU time 0.83 seconds
Started Apr 23 02:36:46 PM PDT 24
Finished Apr 23 02:36:48 PM PDT 24
Peak memory 203836 kb
Host smart-719e9dad-a99e-40f9-b825-fbd2f804a37a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27225
23930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.2722523930
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.1274231333
Short name T1001
Test name
Test status
Simulation time 27862554072 ps
CPU time 53.99 seconds
Started Apr 23 02:36:39 PM PDT 24
Finished Apr 23 02:37:34 PM PDT 24
Peak memory 204360 kb
Host smart-47f6b5d8-3860-4888-ac47-5dd6d111f5e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12742
31333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.1274231333
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.180932909
Short name T1219
Test name
Test status
Simulation time 8384018494 ps
CPU time 8 seconds
Started Apr 23 02:36:39 PM PDT 24
Finished Apr 23 02:36:48 PM PDT 24
Peak memory 203956 kb
Host smart-c2627e2a-7668-4b4b-93d1-4f27a4e4207a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18093
2909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.180932909
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.3800535887
Short name T1329
Test name
Test status
Simulation time 8434907526 ps
CPU time 9.96 seconds
Started Apr 23 02:36:40 PM PDT 24
Finished Apr 23 02:36:51 PM PDT 24
Peak memory 204016 kb
Host smart-c6daebe2-bcbe-4e6c-9159-cc9081713b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38005
35887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.3800535887
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.3468629134
Short name T745
Test name
Test status
Simulation time 8393075096 ps
CPU time 8.19 seconds
Started Apr 23 02:36:38 PM PDT 24
Finished Apr 23 02:36:48 PM PDT 24
Peak memory 204016 kb
Host smart-83066fb0-b687-4f8b-9ab2-a00e80f3f920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34686
29134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.3468629134
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.1481947621
Short name T520
Test name
Test status
Simulation time 8381447318 ps
CPU time 7.95 seconds
Started Apr 23 02:36:38 PM PDT 24
Finished Apr 23 02:36:47 PM PDT 24
Peak memory 204016 kb
Host smart-72668fce-e457-47a1-aba6-097f4771b59a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14819
47621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.1481947621
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.2480586852
Short name T1025
Test name
Test status
Simulation time 8377243992 ps
CPU time 9.64 seconds
Started Apr 23 02:36:38 PM PDT 24
Finished Apr 23 02:36:49 PM PDT 24
Peak memory 204056 kb
Host smart-7e886938-d32e-48b9-8f35-424b32c6f654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24805
86852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.2480586852
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.3870895389
Short name T1157
Test name
Test status
Simulation time 8469003692 ps
CPU time 7.7 seconds
Started Apr 23 02:36:37 PM PDT 24
Finished Apr 23 02:36:46 PM PDT 24
Peak memory 203984 kb
Host smart-9456466d-215a-48f0-b36e-1b137733c794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38708
95389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.3870895389
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.3178048625
Short name T832
Test name
Test status
Simulation time 8418623470 ps
CPU time 8.15 seconds
Started Apr 23 02:36:39 PM PDT 24
Finished Apr 23 02:36:48 PM PDT 24
Peak memory 204032 kb
Host smart-32400aae-ca4a-42ed-84b1-b7d9aac23681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31780
48625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.3178048625
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.4113847757
Short name T1183
Test name
Test status
Simulation time 8423088965 ps
CPU time 7.58 seconds
Started Apr 23 02:36:38 PM PDT 24
Finished Apr 23 02:36:46 PM PDT 24
Peak memory 204000 kb
Host smart-1545b238-242a-4a89-9851-99a34a0b5e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41138
47757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.4113847757
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.422681616
Short name T746
Test name
Test status
Simulation time 8501083718 ps
CPU time 7.66 seconds
Started Apr 23 02:35:21 PM PDT 24
Finished Apr 23 02:35:30 PM PDT 24
Peak memory 203972 kb
Host smart-703d75aa-40af-4bd6-a7df-c25c8c0b7504
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=422681616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.422681616
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.395145315
Short name T1196
Test name
Test status
Simulation time 8381601610 ps
CPU time 8.24 seconds
Started Apr 23 02:35:15 PM PDT 24
Finished Apr 23 02:35:24 PM PDT 24
Peak memory 204036 kb
Host smart-9d97a0d1-37dd-47b0-83d1-276d7912c3dc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=395145315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.395145315
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.454956604
Short name T1039
Test name
Test status
Simulation time 8464745094 ps
CPU time 9.1 seconds
Started Apr 23 02:35:16 PM PDT 24
Finished Apr 23 02:35:26 PM PDT 24
Peak memory 203992 kb
Host smart-2ac1200d-3804-4814-9099-405a3737abd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45495
6604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.454956604
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.1982864118
Short name T513
Test name
Test status
Simulation time 8376387542 ps
CPU time 7.45 seconds
Started Apr 23 02:35:14 PM PDT 24
Finished Apr 23 02:35:22 PM PDT 24
Peak memory 203996 kb
Host smart-62bd05e2-ddb9-4e91-adfc-f5e8ebdebcf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19828
64118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.1982864118
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_enable.1634115896
Short name T1342
Test name
Test status
Simulation time 8373907808 ps
CPU time 7.71 seconds
Started Apr 23 02:35:13 PM PDT 24
Finished Apr 23 02:35:22 PM PDT 24
Peak memory 204036 kb
Host smart-c79f62e7-9cd3-4377-aafa-eee40e9066bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16341
15896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.1634115896
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.4181432742
Short name T415
Test name
Test status
Simulation time 274335310 ps
CPU time 2.11 seconds
Started Apr 23 02:35:12 PM PDT 24
Finished Apr 23 02:35:14 PM PDT 24
Peak memory 204156 kb
Host smart-f1dc586b-5967-49fe-96e0-86a4288b1282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41814
32742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.4181432742
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.1870942286
Short name T1118
Test name
Test status
Simulation time 8430732839 ps
CPU time 7.61 seconds
Started Apr 23 02:35:17 PM PDT 24
Finished Apr 23 02:35:25 PM PDT 24
Peak memory 204048 kb
Host smart-93417288-26c8-43ec-a023-86e388f3561b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18709
42286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.1870942286
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.2237242448
Short name T715
Test name
Test status
Simulation time 8374984695 ps
CPU time 7.74 seconds
Started Apr 23 02:35:23 PM PDT 24
Finished Apr 23 02:35:31 PM PDT 24
Peak memory 203968 kb
Host smart-8b1f1c7a-76c0-42bc-b294-0ae4802a2091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22372
42448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2237242448
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.816441648
Short name T1234
Test name
Test status
Simulation time 8418241153 ps
CPU time 9.02 seconds
Started Apr 23 02:35:13 PM PDT 24
Finished Apr 23 02:35:23 PM PDT 24
Peak memory 204020 kb
Host smart-a0d36264-4e4a-45a4-afcb-52520e7a34d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81644
1648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.816441648
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.427361685
Short name T1164
Test name
Test status
Simulation time 8417581476 ps
CPU time 7.86 seconds
Started Apr 23 02:35:14 PM PDT 24
Finished Apr 23 02:35:22 PM PDT 24
Peak memory 203956 kb
Host smart-7f3d59fa-0ced-4a3c-b7a6-f7c34fe09009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42736
1685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.427361685
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.1112020244
Short name T1063
Test name
Test status
Simulation time 8369076978 ps
CPU time 9.49 seconds
Started Apr 23 02:35:16 PM PDT 24
Finished Apr 23 02:35:26 PM PDT 24
Peak memory 204024 kb
Host smart-8e546c52-a6ae-49ce-870b-962f1cde2828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11120
20244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.1112020244
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.3568540409
Short name T127
Test name
Test status
Simulation time 8422932842 ps
CPU time 8.75 seconds
Started Apr 23 02:35:15 PM PDT 24
Finished Apr 23 02:35:24 PM PDT 24
Peak memory 203996 kb
Host smart-f09e4ffe-bf3a-4be6-8f21-52e2f57c4fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35685
40409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.3568540409
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.280299751
Short name T1236
Test name
Test status
Simulation time 8418471502 ps
CPU time 8.16 seconds
Started Apr 23 02:35:20 PM PDT 24
Finished Apr 23 02:35:30 PM PDT 24
Peak memory 203964 kb
Host smart-2e79c6e6-b5c8-4a54-9dc2-0b9f6771915f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28029
9751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.280299751
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.3077274334
Short name T243
Test name
Test status
Simulation time 8379438465 ps
CPU time 7.73 seconds
Started Apr 23 02:35:17 PM PDT 24
Finished Apr 23 02:35:26 PM PDT 24
Peak memory 203956 kb
Host smart-4d479107-8e64-4828-acbe-1eb1c276bef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30772
74334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.3077274334
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.3191946150
Short name T167
Test name
Test status
Simulation time 8368884647 ps
CPU time 9.74 seconds
Started Apr 23 02:35:23 PM PDT 24
Finished Apr 23 02:35:33 PM PDT 24
Peak memory 203964 kb
Host smart-67f189fb-5ae6-45c1-9df2-7266cdbd1b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31919
46150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.3191946150
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.3347968982
Short name T943
Test name
Test status
Simulation time 8368821353 ps
CPU time 7.88 seconds
Started Apr 23 02:35:17 PM PDT 24
Finished Apr 23 02:35:25 PM PDT 24
Peak memory 203992 kb
Host smart-85e31b22-c0e4-4222-9763-f127d509132e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33479
68982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.3347968982
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.2906811422
Short name T1158
Test name
Test status
Simulation time 31373037765 ps
CPU time 62.96 seconds
Started Apr 23 02:35:20 PM PDT 24
Finished Apr 23 02:36:24 PM PDT 24
Peak memory 204240 kb
Host smart-1e360812-e9e8-49fd-bea5-bf41456446ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29068
11422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.2906811422
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.787199768
Short name T525
Test name
Test status
Simulation time 8446594535 ps
CPU time 7.74 seconds
Started Apr 23 02:35:20 PM PDT 24
Finished Apr 23 02:35:29 PM PDT 24
Peak memory 203900 kb
Host smart-f45691fb-12b3-4c34-b7c4-c2d0cbace92f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78719
9768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.787199768
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3971282187
Short name T157
Test name
Test status
Simulation time 8462678400 ps
CPU time 8.4 seconds
Started Apr 23 02:35:16 PM PDT 24
Finished Apr 23 02:35:25 PM PDT 24
Peak memory 204060 kb
Host smart-0ce5f86e-b282-49af-9e01-3463c4ed959d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39712
82187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3971282187
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.3148180750
Short name T1305
Test name
Test status
Simulation time 8425032188 ps
CPU time 10.31 seconds
Started Apr 23 02:35:14 PM PDT 24
Finished Apr 23 02:35:25 PM PDT 24
Peak memory 204012 kb
Host smart-ba32edef-8c83-4f31-aba8-3e77dd21d44a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31481
80750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.3148180750
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.522482293
Short name T73
Test name
Test status
Simulation time 292896011 ps
CPU time 1.07 seconds
Started Apr 23 02:35:18 PM PDT 24
Finished Apr 23 02:35:20 PM PDT 24
Peak memory 220132 kb
Host smart-d555ba94-6493-44aa-8a1f-69f87c3aeb29
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=522482293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.522482293
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.1359512447
Short name T904
Test name
Test status
Simulation time 8374777279 ps
CPU time 8.88 seconds
Started Apr 23 02:35:16 PM PDT 24
Finished Apr 23 02:35:26 PM PDT 24
Peak memory 204044 kb
Host smart-79bd2855-51ed-419e-82c7-4444fcd054c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13595
12447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.1359512447
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.4073217372
Short name T1198
Test name
Test status
Simulation time 8373159233 ps
CPU time 9.4 seconds
Started Apr 23 02:35:16 PM PDT 24
Finished Apr 23 02:35:26 PM PDT 24
Peak memory 203960 kb
Host smart-6d563639-0892-4eaf-93c1-618cb4f5427b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40732
17372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.4073217372
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.2340410329
Short name T924
Test name
Test status
Simulation time 8391337474 ps
CPU time 7.96 seconds
Started Apr 23 02:35:15 PM PDT 24
Finished Apr 23 02:35:23 PM PDT 24
Peak memory 204048 kb
Host smart-89b0f161-08be-4f29-9596-7e9e35a7cfa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23404
10329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.2340410329
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.2056792011
Short name T921
Test name
Test status
Simulation time 8387294062 ps
CPU time 8.97 seconds
Started Apr 23 02:35:16 PM PDT 24
Finished Apr 23 02:35:26 PM PDT 24
Peak memory 203996 kb
Host smart-8c48c790-89d6-4163-97a1-5e91ac33f4ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20567
92011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.2056792011
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.924158142
Short name T711
Test name
Test status
Simulation time 8463129017 ps
CPU time 9.02 seconds
Started Apr 23 02:36:52 PM PDT 24
Finished Apr 23 02:37:02 PM PDT 24
Peak memory 204032 kb
Host smart-2729aec3-3a17-42f2-b062-a4c5b88e35b4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=924158142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.924158142
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.1854341861
Short name T470
Test name
Test status
Simulation time 8378532274 ps
CPU time 8.07 seconds
Started Apr 23 02:36:43 PM PDT 24
Finished Apr 23 02:36:52 PM PDT 24
Peak memory 204016 kb
Host smart-991f7e83-3c4a-49f1-b589-951319b8da3a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1854341861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.1854341861
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.588633083
Short name T702
Test name
Test status
Simulation time 8475034637 ps
CPU time 7.91 seconds
Started Apr 23 02:36:46 PM PDT 24
Finished Apr 23 02:36:55 PM PDT 24
Peak memory 204052 kb
Host smart-1828136b-e59d-4b42-9084-276bc9c9192a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58863
3083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.588633083
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.187050236
Short name T440
Test name
Test status
Simulation time 8376304274 ps
CPU time 8.28 seconds
Started Apr 23 02:36:42 PM PDT 24
Finished Apr 23 02:36:51 PM PDT 24
Peak memory 204048 kb
Host smart-27708f86-0e35-4899-8e29-d4e88dbe9b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18705
0236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.187050236
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_enable.82085343
Short name T627
Test name
Test status
Simulation time 8392162255 ps
CPU time 7.68 seconds
Started Apr 23 02:36:42 PM PDT 24
Finished Apr 23 02:36:51 PM PDT 24
Peak memory 204032 kb
Host smart-15fb97a3-6a30-477b-81bb-c27a68235dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82085
343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.82085343
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.351657239
Short name T739
Test name
Test status
Simulation time 156468298 ps
CPU time 1.34 seconds
Started Apr 23 02:36:46 PM PDT 24
Finished Apr 23 02:36:48 PM PDT 24
Peak memory 204192 kb
Host smart-4564e05f-5c1b-4412-8067-b5baa1150399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35165
7239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.351657239
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.2105168364
Short name T457
Test name
Test status
Simulation time 8404811826 ps
CPU time 8.33 seconds
Started Apr 23 02:36:41 PM PDT 24
Finished Apr 23 02:36:50 PM PDT 24
Peak memory 204056 kb
Host smart-1130c305-7951-4963-bba9-5c4c3d9f5593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21051
68364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.2105168364
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.1911639790
Short name T192
Test name
Test status
Simulation time 8381313131 ps
CPU time 8.14 seconds
Started Apr 23 02:36:41 PM PDT 24
Finished Apr 23 02:36:49 PM PDT 24
Peak memory 204004 kb
Host smart-da200e5a-a1c9-4042-a66c-eacde73641aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19116
39790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.1911639790
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.692207419
Short name T925
Test name
Test status
Simulation time 8481351056 ps
CPU time 9.54 seconds
Started Apr 23 02:36:46 PM PDT 24
Finished Apr 23 02:36:57 PM PDT 24
Peak memory 204064 kb
Host smart-54c59cc5-ceeb-4e2f-8e12-38379b42faa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69220
7419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.692207419
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1489952920
Short name T1053
Test name
Test status
Simulation time 8466804148 ps
CPU time 7.77 seconds
Started Apr 23 02:36:41 PM PDT 24
Finished Apr 23 02:36:50 PM PDT 24
Peak memory 204060 kb
Host smart-20ee2bc8-df16-496c-b253-e8e32356bc95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14899
52920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1489952920
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.152290739
Short name T354
Test name
Test status
Simulation time 8424769143 ps
CPU time 8.62 seconds
Started Apr 23 02:36:41 PM PDT 24
Finished Apr 23 02:36:50 PM PDT 24
Peak memory 204072 kb
Host smart-c1b568b2-cecd-4d80-bd6d-6a8b60d1c7d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15229
0739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.152290739
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.3050445254
Short name T1230
Test name
Test status
Simulation time 8455362014 ps
CPU time 8.68 seconds
Started Apr 23 02:36:44 PM PDT 24
Finished Apr 23 02:36:53 PM PDT 24
Peak memory 203996 kb
Host smart-0bb236b9-2b65-4f3b-ab42-7e4b4e5ea77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30504
45254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.3050445254
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.4243747763
Short name T907
Test name
Test status
Simulation time 8403691046 ps
CPU time 8.59 seconds
Started Apr 23 02:36:40 PM PDT 24
Finished Apr 23 02:36:49 PM PDT 24
Peak memory 204028 kb
Host smart-8ed76cac-e2a3-44ba-adcd-e4db71e0fa68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42437
47763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.4243747763
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.206483511
Short name T383
Test name
Test status
Simulation time 8415609434 ps
CPU time 8.99 seconds
Started Apr 23 02:36:41 PM PDT 24
Finished Apr 23 02:36:51 PM PDT 24
Peak memory 204048 kb
Host smart-e45e6add-f1e1-4dfc-b126-8625eefe7e84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20648
3511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.206483511
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.874593814
Short name T1050
Test name
Test status
Simulation time 8371020986 ps
CPU time 7.77 seconds
Started Apr 23 02:36:42 PM PDT 24
Finished Apr 23 02:36:50 PM PDT 24
Peak memory 204024 kb
Host smart-9a4afa94-3e98-4a92-bfb3-cc43f84b6678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87459
3814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.874593814
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.2584447388
Short name T916
Test name
Test status
Simulation time 80669573 ps
CPU time 0.68 seconds
Started Apr 23 02:36:41 PM PDT 24
Finished Apr 23 02:36:42 PM PDT 24
Peak memory 203888 kb
Host smart-76283568-db6d-4a49-9bed-9093c4769fc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25844
47388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.2584447388
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3351835651
Short name T15
Test name
Test status
Simulation time 28447545705 ps
CPU time 56.64 seconds
Started Apr 23 02:36:43 PM PDT 24
Finished Apr 23 02:37:40 PM PDT 24
Peak memory 204252 kb
Host smart-6d9b304f-0773-4dbd-8a45-70dcbf7f49ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33518
35651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3351835651
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.1434345801
Short name T846
Test name
Test status
Simulation time 8413453380 ps
CPU time 10.35 seconds
Started Apr 23 02:36:41 PM PDT 24
Finished Apr 23 02:36:52 PM PDT 24
Peak memory 203976 kb
Host smart-00c7d1e9-9b4c-4623-a99e-85414bb33ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14343
45801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.1434345801
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.228471037
Short name T693
Test name
Test status
Simulation time 8401792371 ps
CPU time 7.61 seconds
Started Apr 23 02:36:43 PM PDT 24
Finished Apr 23 02:36:51 PM PDT 24
Peak memory 204036 kb
Host smart-4c0ffd3a-086c-4a3d-b475-b2e8ed32e2fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22847
1037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.228471037
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.177445992
Short name T346
Test name
Test status
Simulation time 8416564228 ps
CPU time 7.66 seconds
Started Apr 23 02:36:45 PM PDT 24
Finished Apr 23 02:36:53 PM PDT 24
Peak memory 203992 kb
Host smart-28c7be34-8ca1-4a42-bdf4-394529ccabe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17744
5992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.177445992
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.3757814979
Short name T21
Test name
Test status
Simulation time 8379242812 ps
CPU time 7.36 seconds
Started Apr 23 02:36:41 PM PDT 24
Finished Apr 23 02:36:49 PM PDT 24
Peak memory 203964 kb
Host smart-8c881cc9-aec8-4643-8f29-b6d13061a269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37578
14979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.3757814979
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1459541951
Short name T1199
Test name
Test status
Simulation time 8477814607 ps
CPU time 7.68 seconds
Started Apr 23 02:36:40 PM PDT 24
Finished Apr 23 02:36:48 PM PDT 24
Peak memory 204076 kb
Host smart-d4403a1d-3492-4692-81c5-ab4e77280e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14595
41951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1459541951
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.368779703
Short name T679
Test name
Test status
Simulation time 8438760602 ps
CPU time 7.8 seconds
Started Apr 23 02:36:43 PM PDT 24
Finished Apr 23 02:36:51 PM PDT 24
Peak memory 204008 kb
Host smart-45d479e4-b922-4cf6-b185-1cd8e8724ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36877
9703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.368779703
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.3606746226
Short name T808
Test name
Test status
Simulation time 8405041819 ps
CPU time 8.24 seconds
Started Apr 23 02:36:40 PM PDT 24
Finished Apr 23 02:36:49 PM PDT 24
Peak memory 204000 kb
Host smart-a4794428-a35e-4836-901b-3547d9690a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36067
46226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.3606746226
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.1540792778
Short name T499
Test name
Test status
Simulation time 8462687401 ps
CPU time 9.22 seconds
Started Apr 23 02:36:49 PM PDT 24
Finished Apr 23 02:36:58 PM PDT 24
Peak memory 204048 kb
Host smart-ddefece5-cb8c-47f4-9ea1-a160e42744b4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1540792778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.1540792778
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.3847744484
Short name T836
Test name
Test status
Simulation time 8385748494 ps
CPU time 7.66 seconds
Started Apr 23 02:36:49 PM PDT 24
Finished Apr 23 02:36:57 PM PDT 24
Peak memory 203968 kb
Host smart-f86d4760-4a12-442e-a475-b43d2dbba676
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3847744484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.3847744484
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.49604768
Short name T849
Test name
Test status
Simulation time 8417657125 ps
CPU time 9.25 seconds
Started Apr 23 02:36:48 PM PDT 24
Finished Apr 23 02:36:58 PM PDT 24
Peak memory 203956 kb
Host smart-a67b9981-e9be-47e2-a316-9ae2ee18e54f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49604
768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.49604768
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.730265552
Short name T558
Test name
Test status
Simulation time 8395147965 ps
CPU time 10.08 seconds
Started Apr 23 02:36:44 PM PDT 24
Finished Apr 23 02:36:55 PM PDT 24
Peak memory 204064 kb
Host smart-94a9f443-f112-4f24-aa7a-726778ae807d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73026
5552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.730265552
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_enable.4240403906
Short name T856
Test name
Test status
Simulation time 8372592684 ps
CPU time 7.62 seconds
Started Apr 23 02:36:52 PM PDT 24
Finished Apr 23 02:37:00 PM PDT 24
Peak memory 204040 kb
Host smart-c63ab8bc-2943-406c-99a9-ff1c0c49d8bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42404
03906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.4240403906
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1666466666
Short name T621
Test name
Test status
Simulation time 180393614 ps
CPU time 1.88 seconds
Started Apr 23 02:36:43 PM PDT 24
Finished Apr 23 02:36:45 PM PDT 24
Peak memory 204128 kb
Host smart-e4e2697d-1c3e-49b1-904d-2d77fa97f7cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16664
66666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1666466666
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.33236026
Short name T47
Test name
Test status
Simulation time 8414244778 ps
CPU time 8.21 seconds
Started Apr 23 02:36:51 PM PDT 24
Finished Apr 23 02:36:59 PM PDT 24
Peak memory 203996 kb
Host smart-1b5aba8e-66a2-4760-8cf9-026637d8f5f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33236
026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.33236026
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.498099825
Short name T1011
Test name
Test status
Simulation time 8370232781 ps
CPU time 7.56 seconds
Started Apr 23 02:36:46 PM PDT 24
Finished Apr 23 02:36:55 PM PDT 24
Peak memory 204036 kb
Host smart-8e5c4edf-81b4-46b4-91c9-dec400d88eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49809
9825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.498099825
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.1017428336
Short name T1035
Test name
Test status
Simulation time 8435218930 ps
CPU time 7.56 seconds
Started Apr 23 02:36:43 PM PDT 24
Finished Apr 23 02:36:51 PM PDT 24
Peak memory 203952 kb
Host smart-7c22a039-5300-4228-9e6c-6e11d0a00449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10174
28336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.1017428336
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.2659032180
Short name T998
Test name
Test status
Simulation time 8441721679 ps
CPU time 7.99 seconds
Started Apr 23 02:36:51 PM PDT 24
Finished Apr 23 02:37:00 PM PDT 24
Peak memory 204044 kb
Host smart-3c3c01c7-7121-4924-8c2d-5106899162a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26590
32180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.2659032180
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3760670767
Short name T1180
Test name
Test status
Simulation time 8390321295 ps
CPU time 10.15 seconds
Started Apr 23 02:36:45 PM PDT 24
Finished Apr 23 02:36:56 PM PDT 24
Peak memory 204020 kb
Host smart-0bbda87e-1847-4de0-979d-3f2ba66c3cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37606
70767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3760670767
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1237432389
Short name T119
Test name
Test status
Simulation time 8403894477 ps
CPU time 9.43 seconds
Started Apr 23 02:36:45 PM PDT 24
Finished Apr 23 02:36:55 PM PDT 24
Peak memory 204016 kb
Host smart-0a8f5fe2-8dff-45b1-a8a9-778e9db55092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12374
32389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1237432389
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.726623713
Short name T1363
Test name
Test status
Simulation time 8393260984 ps
CPU time 7.7 seconds
Started Apr 23 02:36:47 PM PDT 24
Finished Apr 23 02:36:55 PM PDT 24
Peak memory 204012 kb
Host smart-e302ec5a-0356-4d0a-bf9c-2491947e9e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72662
3713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.726623713
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3158558783
Short name T30
Test name
Test status
Simulation time 8383130811 ps
CPU time 8.19 seconds
Started Apr 23 02:36:44 PM PDT 24
Finished Apr 23 02:36:52 PM PDT 24
Peak memory 204004 kb
Host smart-6973b362-5a8f-470b-8657-34ad5bc8bc49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31585
58783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3158558783
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.1343756625
Short name T1275
Test name
Test status
Simulation time 8448949532 ps
CPU time 7.63 seconds
Started Apr 23 02:36:47 PM PDT 24
Finished Apr 23 02:36:55 PM PDT 24
Peak memory 204044 kb
Host smart-34e2635a-fb38-4c6f-a31f-cba18fe18ea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13437
56625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.1343756625
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.1554860849
Short name T1066
Test name
Test status
Simulation time 8369380507 ps
CPU time 7.9 seconds
Started Apr 23 02:36:46 PM PDT 24
Finished Apr 23 02:36:54 PM PDT 24
Peak memory 204056 kb
Host smart-458e198d-e615-4f04-b34d-b7a545bcf802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15548
60849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.1554860849
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.942583461
Short name T1084
Test name
Test status
Simulation time 143890025 ps
CPU time 0.73 seconds
Started Apr 23 02:36:48 PM PDT 24
Finished Apr 23 02:36:49 PM PDT 24
Peak memory 203916 kb
Host smart-01ce3e51-a585-4f03-a9e7-c7aa8f0bfc95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94258
3461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.942583461
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.3008767618
Short name T1350
Test name
Test status
Simulation time 14994367824 ps
CPU time 29.15 seconds
Started Apr 23 02:36:51 PM PDT 24
Finished Apr 23 02:37:21 PM PDT 24
Peak memory 204332 kb
Host smart-a8741c0e-9149-4891-b3a0-659d4a70bf1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30087
67618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.3008767618
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.1067483898
Short name T322
Test name
Test status
Simulation time 8433085959 ps
CPU time 7.96 seconds
Started Apr 23 02:36:45 PM PDT 24
Finished Apr 23 02:36:54 PM PDT 24
Peak memory 204020 kb
Host smart-5f4efd2b-191f-488e-98ab-d22bc9683d66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10674
83898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.1067483898
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.1199219506
Short name T635
Test name
Test status
Simulation time 8428092265 ps
CPU time 7.7 seconds
Started Apr 23 02:36:46 PM PDT 24
Finished Apr 23 02:36:55 PM PDT 24
Peak memory 204016 kb
Host smart-9f320ca6-6732-4489-85cd-e85716ea127a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11992
19506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1199219506
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.2692319321
Short name T785
Test name
Test status
Simulation time 8405188056 ps
CPU time 8.94 seconds
Started Apr 23 02:36:52 PM PDT 24
Finished Apr 23 02:37:01 PM PDT 24
Peak memory 204040 kb
Host smart-5aa553ba-a1cb-4959-8ea8-e306c58423cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26923
19321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.2692319321
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.354235076
Short name T1334
Test name
Test status
Simulation time 8399864397 ps
CPU time 8.26 seconds
Started Apr 23 02:36:49 PM PDT 24
Finished Apr 23 02:36:57 PM PDT 24
Peak memory 204020 kb
Host smart-a88007d1-8ac7-4bb6-8392-062c44fbba5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35423
5076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.354235076
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.705605940
Short name T467
Test name
Test status
Simulation time 8370344347 ps
CPU time 8.45 seconds
Started Apr 23 02:36:45 PM PDT 24
Finished Apr 23 02:36:54 PM PDT 24
Peak memory 203960 kb
Host smart-5815cced-6801-4556-ad78-b3abaee8682d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70560
5940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.705605940
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.2387157189
Short name T160
Test name
Test status
Simulation time 8420583503 ps
CPU time 8.37 seconds
Started Apr 23 02:36:45 PM PDT 24
Finished Apr 23 02:36:54 PM PDT 24
Peak memory 204032 kb
Host smart-750eaf98-9b68-480c-b444-5c41b2f4905e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23871
57189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.2387157189
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.3848745452
Short name T35
Test name
Test status
Simulation time 8431921100 ps
CPU time 9.17 seconds
Started Apr 23 02:36:46 PM PDT 24
Finished Apr 23 02:36:56 PM PDT 24
Peak memory 203988 kb
Host smart-f2e9deae-59d8-407b-9fcb-4d2b1dbfe2bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38487
45452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.3848745452
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.3863219629
Short name T1031
Test name
Test status
Simulation time 8383504800 ps
CPU time 7.62 seconds
Started Apr 23 02:36:46 PM PDT 24
Finished Apr 23 02:36:54 PM PDT 24
Peak memory 204056 kb
Host smart-ef240f71-102f-4010-b461-58123124d697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38632
19629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.3863219629
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.4184936291
Short name T421
Test name
Test status
Simulation time 8469562947 ps
CPU time 8.21 seconds
Started Apr 23 02:36:56 PM PDT 24
Finished Apr 23 02:37:05 PM PDT 24
Peak memory 204020 kb
Host smart-f6b5da3d-f5a8-4290-91e7-c08f03b6e16e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4184936291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.4184936291
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.3834744280
Short name T1229
Test name
Test status
Simulation time 8377404087 ps
CPU time 8.8 seconds
Started Apr 23 02:36:55 PM PDT 24
Finished Apr 23 02:37:05 PM PDT 24
Peak memory 204016 kb
Host smart-ede3dcc7-4fbc-4e49-a93e-d9dc1cd54572
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3834744280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.3834744280
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.2111638391
Short name T40
Test name
Test status
Simulation time 8411427477 ps
CPU time 8.75 seconds
Started Apr 23 02:36:58 PM PDT 24
Finished Apr 23 02:37:07 PM PDT 24
Peak memory 204040 kb
Host smart-28c70832-184d-4f63-9e3c-9230cbe6c65c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21116
38391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.2111638391
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.982486155
Short name T1225
Test name
Test status
Simulation time 8388961740 ps
CPU time 8.23 seconds
Started Apr 23 02:36:52 PM PDT 24
Finished Apr 23 02:37:01 PM PDT 24
Peak memory 204040 kb
Host smart-eb0b9ebb-a413-4354-aee5-7d7fa5f8db27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98248
6155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.982486155
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_enable.2736741236
Short name T329
Test name
Test status
Simulation time 8384929824 ps
CPU time 8.27 seconds
Started Apr 23 02:36:54 PM PDT 24
Finished Apr 23 02:37:03 PM PDT 24
Peak memory 204040 kb
Host smart-aa8ad32a-5dc3-4fbf-814d-845da8f31cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27367
41236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.2736741236
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.1850649853
Short name T51
Test name
Test status
Simulation time 191016350 ps
CPU time 1.79 seconds
Started Apr 23 02:36:52 PM PDT 24
Finished Apr 23 02:36:54 PM PDT 24
Peak memory 204112 kb
Host smart-d3ed0766-cc7b-4929-8f0d-7310ba61c822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18506
49853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1850649853
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.3206285065
Short name T512
Test name
Test status
Simulation time 8460436955 ps
CPU time 7.76 seconds
Started Apr 23 02:36:57 PM PDT 24
Finished Apr 23 02:37:06 PM PDT 24
Peak memory 203996 kb
Host smart-ad4145c5-5d5b-4460-8a33-3ee669b96eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32062
85065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.3206285065
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2414943451
Short name T697
Test name
Test status
Simulation time 8369811057 ps
CPU time 8.32 seconds
Started Apr 23 02:36:56 PM PDT 24
Finished Apr 23 02:37:05 PM PDT 24
Peak memory 204060 kb
Host smart-61166bab-8473-426b-9c6c-a8f1319a4cd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24149
43451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2414943451
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.1481464317
Short name T510
Test name
Test status
Simulation time 8397357494 ps
CPU time 7.88 seconds
Started Apr 23 02:36:50 PM PDT 24
Finished Apr 23 02:36:58 PM PDT 24
Peak memory 204064 kb
Host smart-b315a120-ac59-44ba-97bf-625857b55f02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14814
64317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.1481464317
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.1014725441
Short name T456
Test name
Test status
Simulation time 8411989318 ps
CPU time 9.32 seconds
Started Apr 23 02:36:54 PM PDT 24
Finished Apr 23 02:37:04 PM PDT 24
Peak memory 203996 kb
Host smart-6cbe2394-c5d8-458f-b23d-07c1d85152b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10147
25441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.1014725441
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.859000681
Short name T1266
Test name
Test status
Simulation time 8385663287 ps
CPU time 7.84 seconds
Started Apr 23 02:36:55 PM PDT 24
Finished Apr 23 02:37:04 PM PDT 24
Peak memory 204044 kb
Host smart-377c82aa-4e89-4153-83c5-c60ce6abaa80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85900
0681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.859000681
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.3597282613
Short name T1041
Test name
Test status
Simulation time 8450372365 ps
CPU time 8.15 seconds
Started Apr 23 02:36:51 PM PDT 24
Finished Apr 23 02:37:00 PM PDT 24
Peak memory 204024 kb
Host smart-cd0e5b4a-b111-424d-a787-fb40b676b938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35972
82613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.3597282613
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.3620284402
Short name T460
Test name
Test status
Simulation time 8400006630 ps
CPU time 8.93 seconds
Started Apr 23 02:36:56 PM PDT 24
Finished Apr 23 02:37:05 PM PDT 24
Peak memory 203956 kb
Host smart-a1ab7986-ee58-49e6-9835-07b2004d1668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36202
84402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.3620284402
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.182987482
Short name T775
Test name
Test status
Simulation time 8416882560 ps
CPU time 8.41 seconds
Started Apr 23 02:36:52 PM PDT 24
Finished Apr 23 02:37:01 PM PDT 24
Peak memory 204004 kb
Host smart-aee5987b-1422-4e8f-bafa-d23d9b95f72d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18298
7482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.182987482
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.3474476654
Short name T433
Test name
Test status
Simulation time 8366149985 ps
CPU time 7.5 seconds
Started Apr 23 02:36:55 PM PDT 24
Finished Apr 23 02:37:03 PM PDT 24
Peak memory 203952 kb
Host smart-fc71324c-3a1e-4bcc-9966-444af9e8b7c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34744
76654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.3474476654
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.4012496801
Short name T1282
Test name
Test status
Simulation time 41106971 ps
CPU time 0.65 seconds
Started Apr 23 02:36:51 PM PDT 24
Finished Apr 23 02:36:52 PM PDT 24
Peak memory 203904 kb
Host smart-6bf39b06-15e0-47c7-90e0-6bc7b874a247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40124
96801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.4012496801
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.2676024764
Short name T1304
Test name
Test status
Simulation time 30794913475 ps
CPU time 63.66 seconds
Started Apr 23 02:36:51 PM PDT 24
Finished Apr 23 02:37:55 PM PDT 24
Peak memory 204312 kb
Host smart-686b1e7c-6f63-41c3-ab22-7fb2cb77e5a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26760
24764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.2676024764
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.3344954291
Short name T541
Test name
Test status
Simulation time 8378116611 ps
CPU time 7.87 seconds
Started Apr 23 02:36:52 PM PDT 24
Finished Apr 23 02:37:00 PM PDT 24
Peak memory 204020 kb
Host smart-0eb0f0cf-15fd-4a81-a71a-7c42ed59fe31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33449
54291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.3344954291
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.1080315873
Short name T1137
Test name
Test status
Simulation time 8424378850 ps
CPU time 9.04 seconds
Started Apr 23 02:36:50 PM PDT 24
Finished Apr 23 02:37:00 PM PDT 24
Peak memory 204032 kb
Host smart-1804dae8-8cc5-4af9-ae6c-430a6b63b534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10803
15873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1080315873
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.950555993
Short name T612
Test name
Test status
Simulation time 8402798625 ps
CPU time 8.75 seconds
Started Apr 23 02:36:52 PM PDT 24
Finished Apr 23 02:37:01 PM PDT 24
Peak memory 204044 kb
Host smart-871511b0-211e-4620-99bc-79c3348b705a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95055
5993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.950555993
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.3806872356
Short name T1364
Test name
Test status
Simulation time 8371506784 ps
CPU time 7.7 seconds
Started Apr 23 02:36:52 PM PDT 24
Finished Apr 23 02:37:00 PM PDT 24
Peak memory 203988 kb
Host smart-dd718643-a67f-48ec-acbb-c6104204ecda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38068
72356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.3806872356
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1488647316
Short name T1336
Test name
Test status
Simulation time 8370839406 ps
CPU time 7.42 seconds
Started Apr 23 02:36:51 PM PDT 24
Finished Apr 23 02:36:58 PM PDT 24
Peak memory 203976 kb
Host smart-ab0d2ee7-9e3d-4494-9ab2-9fe58fbbde64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14886
47316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1488647316
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.3368391602
Short name T1056
Test name
Test status
Simulation time 8434309230 ps
CPU time 7.96 seconds
Started Apr 23 02:36:49 PM PDT 24
Finished Apr 23 02:36:58 PM PDT 24
Peak memory 203996 kb
Host smart-d21fe1fd-18ca-422c-a989-6cf13c9dd371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33683
91602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.3368391602
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.2424563372
Short name T803
Test name
Test status
Simulation time 8407512074 ps
CPU time 7.66 seconds
Started Apr 23 02:36:55 PM PDT 24
Finished Apr 23 02:37:03 PM PDT 24
Peak memory 204032 kb
Host smart-c182f6a9-c920-40ce-b459-a6f26d11ef56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24245
63372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.2424563372
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.1730475180
Short name T1127
Test name
Test status
Simulation time 8417479116 ps
CPU time 8.16 seconds
Started Apr 23 02:36:54 PM PDT 24
Finished Apr 23 02:37:03 PM PDT 24
Peak memory 204040 kb
Host smart-e6b96be8-3a76-4a21-b4cc-cf04b1036cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17304
75180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.1730475180
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.3466487601
Short name T397
Test name
Test status
Simulation time 8465780344 ps
CPU time 10.53 seconds
Started Apr 23 02:36:59 PM PDT 24
Finished Apr 23 02:37:10 PM PDT 24
Peak memory 204092 kb
Host smart-eb5e0cae-3564-4893-85ee-c6def779c80f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3466487601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.3466487601
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.1270290855
Short name T847
Test name
Test status
Simulation time 8398144502 ps
CPU time 7.6 seconds
Started Apr 23 02:36:58 PM PDT 24
Finished Apr 23 02:37:06 PM PDT 24
Peak memory 204020 kb
Host smart-96078ff6-9945-4b9a-8cc9-edec6c0d263a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1270290855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.1270290855
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.2727481310
Short name T1166
Test name
Test status
Simulation time 8457125344 ps
CPU time 7.75 seconds
Started Apr 23 02:36:59 PM PDT 24
Finished Apr 23 02:37:07 PM PDT 24
Peak memory 204056 kb
Host smart-35544c04-66e5-4e58-bf18-24b215085331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27274
81310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.2727481310
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.1646335248
Short name T429
Test name
Test status
Simulation time 8378034952 ps
CPU time 8.18 seconds
Started Apr 23 02:36:56 PM PDT 24
Finished Apr 23 02:37:04 PM PDT 24
Peak memory 204036 kb
Host smart-ffd75d04-6d52-40dd-9919-ff036cd867b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16463
35248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.1646335248
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_enable.3613268283
Short name T1194
Test name
Test status
Simulation time 8377451441 ps
CPU time 8.69 seconds
Started Apr 23 02:36:54 PM PDT 24
Finished Apr 23 02:37:04 PM PDT 24
Peak memory 204008 kb
Host smart-75dd3025-563e-4471-8d8d-0f67c1046508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36132
68283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.3613268283
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3044123553
Short name T1106
Test name
Test status
Simulation time 219433497 ps
CPU time 2.02 seconds
Started Apr 23 02:36:55 PM PDT 24
Finished Apr 23 02:36:57 PM PDT 24
Peak memory 204152 kb
Host smart-939330d6-9ed9-4060-aca0-69b60be4a318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30441
23553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3044123553
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.494758103
Short name T1295
Test name
Test status
Simulation time 8518114184 ps
CPU time 7.76 seconds
Started Apr 23 02:37:01 PM PDT 24
Finished Apr 23 02:37:10 PM PDT 24
Peak memory 204032 kb
Host smart-f48892db-5cb6-4eb8-8acb-41ff11fd0a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49475
8103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.494758103
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.2027430756
Short name T201
Test name
Test status
Simulation time 8368233242 ps
CPU time 7.62 seconds
Started Apr 23 02:36:58 PM PDT 24
Finished Apr 23 02:37:07 PM PDT 24
Peak memory 204012 kb
Host smart-4f1c3610-b40a-47e3-839b-ff417708d283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20274
30756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.2027430756
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.2506569316
Short name T759
Test name
Test status
Simulation time 8470848246 ps
CPU time 8.35 seconds
Started Apr 23 02:36:59 PM PDT 24
Finished Apr 23 02:37:09 PM PDT 24
Peak memory 203996 kb
Host smart-e5cdfda6-6a6b-42f5-bca5-99a54eb2786b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25065
69316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.2506569316
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.199209779
Short name T1351
Test name
Test status
Simulation time 8412180945 ps
CPU time 7.51 seconds
Started Apr 23 02:36:57 PM PDT 24
Finished Apr 23 02:37:06 PM PDT 24
Peak memory 204076 kb
Host smart-49f733cd-80f2-4427-8406-0f0a8274662d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19920
9779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.199209779
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.1378490806
Short name T380
Test name
Test status
Simulation time 8369084091 ps
CPU time 7.68 seconds
Started Apr 23 02:36:57 PM PDT 24
Finished Apr 23 02:37:06 PM PDT 24
Peak memory 204008 kb
Host smart-4bc17f02-a73f-4fae-980c-9fe4d159c3c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13784
90806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.1378490806
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.1927734563
Short name T33
Test name
Test status
Simulation time 8395368307 ps
CPU time 10.18 seconds
Started Apr 23 02:36:56 PM PDT 24
Finished Apr 23 02:37:07 PM PDT 24
Peak memory 204064 kb
Host smart-5e318d99-8ade-495a-96bd-3d530c963976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19277
34563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.1927734563
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.1823886506
Short name T984
Test name
Test status
Simulation time 8381363205 ps
CPU time 9.26 seconds
Started Apr 23 02:36:54 PM PDT 24
Finished Apr 23 02:37:03 PM PDT 24
Peak memory 204012 kb
Host smart-307cdd6e-d05b-4514-bbf7-31603984268b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18238
86506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.1823886506
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.2077956336
Short name T863
Test name
Test status
Simulation time 8428580490 ps
CPU time 7.72 seconds
Started Apr 23 02:36:57 PM PDT 24
Finished Apr 23 02:37:06 PM PDT 24
Peak memory 203992 kb
Host smart-401c8d6c-16a7-4536-b6d6-9e8ea404c0e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20779
56336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.2077956336
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.3874055660
Short name T1161
Test name
Test status
Simulation time 8370586470 ps
CPU time 7.55 seconds
Started Apr 23 02:36:57 PM PDT 24
Finished Apr 23 02:37:06 PM PDT 24
Peak memory 203996 kb
Host smart-7ebbf145-115c-4c2a-a0d8-4d2d047b5cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38740
55660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.3874055660
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2681305488
Short name T770
Test name
Test status
Simulation time 35622267 ps
CPU time 0.68 seconds
Started Apr 23 02:36:57 PM PDT 24
Finished Apr 23 02:36:58 PM PDT 24
Peak memory 203848 kb
Host smart-ec6b370c-917b-415d-b209-10d59fe10a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26813
05488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2681305488
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.684216805
Short name T968
Test name
Test status
Simulation time 16599274933 ps
CPU time 28.03 seconds
Started Apr 23 02:36:59 PM PDT 24
Finished Apr 23 02:37:28 PM PDT 24
Peak memory 204348 kb
Host smart-5a2f7b8f-0998-4f15-ac4b-d38762c27a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68421
6805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.684216805
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.2312083822
Short name T871
Test name
Test status
Simulation time 8387872017 ps
CPU time 7.69 seconds
Started Apr 23 02:36:57 PM PDT 24
Finished Apr 23 02:37:06 PM PDT 24
Peak memory 204008 kb
Host smart-35dcd221-36be-4ca1-80e8-b6f533312eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23120
83822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.2312083822
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2453611742
Short name T1344
Test name
Test status
Simulation time 8404829161 ps
CPU time 8.34 seconds
Started Apr 23 02:36:54 PM PDT 24
Finished Apr 23 02:37:03 PM PDT 24
Peak memory 203984 kb
Host smart-4d5bfbcb-cb97-4491-a1f9-bd66497a1c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24536
11742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2453611742
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.3911007847
Short name T615
Test name
Test status
Simulation time 8460949578 ps
CPU time 8.64 seconds
Started Apr 23 02:36:57 PM PDT 24
Finished Apr 23 02:37:06 PM PDT 24
Peak memory 204044 kb
Host smart-ab099147-7a6f-4a15-a197-eeb7965706eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39110
07847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.3911007847
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.1213137769
Short name T972
Test name
Test status
Simulation time 8383392664 ps
CPU time 8.02 seconds
Started Apr 23 02:36:57 PM PDT 24
Finished Apr 23 02:37:06 PM PDT 24
Peak memory 204072 kb
Host smart-9fe9ece8-10b0-4f4c-9578-0c930f95dbba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12131
37769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.1213137769
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.528176042
Short name T809
Test name
Test status
Simulation time 8403040985 ps
CPU time 8.2 seconds
Started Apr 23 02:36:57 PM PDT 24
Finished Apr 23 02:37:06 PM PDT 24
Peak memory 204072 kb
Host smart-a4d742a2-cc2e-412a-bb3f-743cb338e080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52817
6042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.528176042
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.448246428
Short name T561
Test name
Test status
Simulation time 8421299494 ps
CPU time 8.64 seconds
Started Apr 23 02:36:56 PM PDT 24
Finished Apr 23 02:37:05 PM PDT 24
Peak memory 204036 kb
Host smart-cff4a9b5-5e5f-4458-99cf-3b808f178c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44824
6428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.448246428
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.4281059713
Short name T1010
Test name
Test status
Simulation time 8376609893 ps
CPU time 7.72 seconds
Started Apr 23 02:36:56 PM PDT 24
Finished Apr 23 02:37:04 PM PDT 24
Peak memory 204004 kb
Host smart-f3d25886-33a8-45d9-8203-b97e3f03e5ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42810
59713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.4281059713
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.1894003597
Short name T1319
Test name
Test status
Simulation time 8374115034 ps
CPU time 7.91 seconds
Started Apr 23 02:36:57 PM PDT 24
Finished Apr 23 02:37:06 PM PDT 24
Peak memory 204012 kb
Host smart-27c65454-4dcc-40ab-bc50-946dcc56eb22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18940
03597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.1894003597
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.3878528846
Short name T79
Test name
Test status
Simulation time 8376823643 ps
CPU time 8.33 seconds
Started Apr 23 02:37:02 PM PDT 24
Finished Apr 23 02:37:11 PM PDT 24
Peak memory 204012 kb
Host smart-7c59fea5-05e0-4041-bb00-206f17eac02f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3878528846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.3878528846
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.546744550
Short name T1296
Test name
Test status
Simulation time 8454809271 ps
CPU time 10.04 seconds
Started Apr 23 02:37:07 PM PDT 24
Finished Apr 23 02:37:18 PM PDT 24
Peak memory 204008 kb
Host smart-a4a8b3c6-1e41-47d3-95d1-c7957bc929ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54674
4550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.546744550
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.2858828980
Short name T316
Test name
Test status
Simulation time 8379903342 ps
CPU time 9.91 seconds
Started Apr 23 02:36:59 PM PDT 24
Finished Apr 23 02:37:09 PM PDT 24
Peak memory 204096 kb
Host smart-167babc4-6c89-4f13-9855-83575256680b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28588
28980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2858828980
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_enable.1760731263
Short name T1174
Test name
Test status
Simulation time 8383500680 ps
CPU time 7.79 seconds
Started Apr 23 02:36:58 PM PDT 24
Finished Apr 23 02:37:07 PM PDT 24
Peak memory 204060 kb
Host smart-9a33ce2e-9fb1-4308-be04-1e226532cffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17607
31263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.1760731263
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2293973016
Short name T945
Test name
Test status
Simulation time 159966025 ps
CPU time 1.39 seconds
Started Apr 23 02:37:00 PM PDT 24
Finished Apr 23 02:37:02 PM PDT 24
Peak memory 204120 kb
Host smart-77d57c3e-a1a0-464b-aef0-a82f582a76b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22939
73016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2293973016
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.1226992125
Short name T1362
Test name
Test status
Simulation time 8474887738 ps
CPU time 8.7 seconds
Started Apr 23 02:37:01 PM PDT 24
Finished Apr 23 02:37:11 PM PDT 24
Peak memory 204052 kb
Host smart-9388cde0-dfc6-4af1-ad5b-625490de69cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12269
92125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.1226992125
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.306113368
Short name T1102
Test name
Test status
Simulation time 8367987893 ps
CPU time 8.58 seconds
Started Apr 23 02:37:02 PM PDT 24
Finished Apr 23 02:37:11 PM PDT 24
Peak memory 204060 kb
Host smart-1eb3e8dd-95f1-4a39-af82-742fe7f45fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30611
3368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.306113368
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2436075790
Short name T83
Test name
Test status
Simulation time 8419145916 ps
CPU time 8.01 seconds
Started Apr 23 02:36:58 PM PDT 24
Finished Apr 23 02:37:07 PM PDT 24
Peak memory 204060 kb
Host smart-e6e90cd6-8525-468e-939a-b6068839c585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24360
75790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2436075790
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.2009877067
Short name T726
Test name
Test status
Simulation time 8389134288 ps
CPU time 8.2 seconds
Started Apr 23 02:36:57 PM PDT 24
Finished Apr 23 02:37:06 PM PDT 24
Peak memory 203996 kb
Host smart-62305663-64a5-44e1-ae1b-ef8aa3b9e795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20098
77067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2009877067
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.3334437288
Short name T75
Test name
Test status
Simulation time 8400256410 ps
CPU time 8.22 seconds
Started Apr 23 02:36:58 PM PDT 24
Finished Apr 23 02:37:07 PM PDT 24
Peak memory 204028 kb
Host smart-54055491-be2a-4307-a5c5-7c9a9cd50f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33344
37288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.3334437288
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.745835318
Short name T811
Test name
Test status
Simulation time 8417573190 ps
CPU time 9.13 seconds
Started Apr 23 02:37:00 PM PDT 24
Finished Apr 23 02:37:10 PM PDT 24
Peak memory 204028 kb
Host smart-99f0fa2d-0aeb-4dea-b703-df6521bd9138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74583
5318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.745835318
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.1356803051
Short name T46
Test name
Test status
Simulation time 8409271251 ps
CPU time 7.8 seconds
Started Apr 23 02:37:01 PM PDT 24
Finished Apr 23 02:37:10 PM PDT 24
Peak memory 204008 kb
Host smart-c26cc615-5907-4871-9836-b59890a8bf79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13568
03051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.1356803051
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.2604140749
Short name T614
Test name
Test status
Simulation time 8367532755 ps
CPU time 7.33 seconds
Started Apr 23 02:37:01 PM PDT 24
Finished Apr 23 02:37:09 PM PDT 24
Peak memory 203964 kb
Host smart-d5f289f6-982b-46e7-80e2-ec4f7cc8f51d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26041
40749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.2604140749
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.3165769681
Short name T1347
Test name
Test status
Simulation time 32783493 ps
CPU time 0.66 seconds
Started Apr 23 02:37:03 PM PDT 24
Finished Apr 23 02:37:04 PM PDT 24
Peak memory 203892 kb
Host smart-5b0ddf59-03a0-4c2d-b952-342c7c891719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31657
69681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.3165769681
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.1996944672
Short name T1353
Test name
Test status
Simulation time 20837528189 ps
CPU time 42.47 seconds
Started Apr 23 02:37:00 PM PDT 24
Finished Apr 23 02:37:43 PM PDT 24
Peak memory 204296 kb
Host smart-7be40d41-a9a0-4e19-86a6-25e973120441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19969
44672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.1996944672
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.2299636185
Short name T834
Test name
Test status
Simulation time 8380237776 ps
CPU time 8.34 seconds
Started Apr 23 02:36:58 PM PDT 24
Finished Apr 23 02:37:07 PM PDT 24
Peak memory 204020 kb
Host smart-0f3adb26-c6ba-4abf-8622-1ec910507624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22996
36185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.2299636185
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.3417330300
Short name T1028
Test name
Test status
Simulation time 8452122131 ps
CPU time 8.08 seconds
Started Apr 23 02:36:59 PM PDT 24
Finished Apr 23 02:37:08 PM PDT 24
Peak memory 204020 kb
Host smart-bfabf4f8-1ff6-4d2a-8cdf-3462e29663f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34173
30300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.3417330300
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.1095424751
Short name T518
Test name
Test status
Simulation time 8408024110 ps
CPU time 9.92 seconds
Started Apr 23 02:37:01 PM PDT 24
Finished Apr 23 02:37:12 PM PDT 24
Peak memory 204028 kb
Host smart-a5a0286e-254b-428c-8960-d508a5bce404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10954
24751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.1095424751
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.2455872647
Short name T81
Test name
Test status
Simulation time 8374311497 ps
CPU time 7.82 seconds
Started Apr 23 02:37:01 PM PDT 24
Finished Apr 23 02:37:10 PM PDT 24
Peak memory 204016 kb
Host smart-75d90934-e6ee-43cf-aa6a-d2a74a8975c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24558
72647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.2455872647
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.80423031
Short name T613
Test name
Test status
Simulation time 8367607246 ps
CPU time 9.54 seconds
Started Apr 23 02:37:01 PM PDT 24
Finished Apr 23 02:37:12 PM PDT 24
Peak memory 204016 kb
Host smart-873b82b6-ae84-43a3-b349-c0f8d27c98af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80423
031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.80423031
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.3176728870
Short name T586
Test name
Test status
Simulation time 8485458164 ps
CPU time 9.06 seconds
Started Apr 23 02:36:59 PM PDT 24
Finished Apr 23 02:37:09 PM PDT 24
Peak memory 203968 kb
Host smart-771feb36-7277-4101-9998-4a4a9a78b55c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31767
28870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3176728870
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.2971007689
Short name T1321
Test name
Test status
Simulation time 8378910845 ps
CPU time 7.45 seconds
Started Apr 23 02:37:02 PM PDT 24
Finished Apr 23 02:37:10 PM PDT 24
Peak memory 203980 kb
Host smart-2a8695a6-19fb-4996-a5c2-d3ff6b43d0f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29710
07689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.2971007689
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.1706892324
Short name T791
Test name
Test status
Simulation time 8381997847 ps
CPU time 7.95 seconds
Started Apr 23 02:37:00 PM PDT 24
Finished Apr 23 02:37:09 PM PDT 24
Peak memory 204092 kb
Host smart-9e348faa-0201-4bbd-b88e-85175faefb35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17068
92324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.1706892324
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.3030381046
Short name T955
Test name
Test status
Simulation time 8393413758 ps
CPU time 10.42 seconds
Started Apr 23 02:37:09 PM PDT 24
Finished Apr 23 02:37:20 PM PDT 24
Peak memory 204024 kb
Host smart-8c39331c-2def-4e2d-8885-119d69764c97
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3030381046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.3030381046
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.787028982
Short name T347
Test name
Test status
Simulation time 8420189552 ps
CPU time 7.86 seconds
Started Apr 23 02:37:08 PM PDT 24
Finished Apr 23 02:37:17 PM PDT 24
Peak memory 204028 kb
Host smart-5296b2a4-3ca5-4968-a9e0-e0dcac5b49cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78702
8982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.787028982
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.1477212933
Short name T371
Test name
Test status
Simulation time 8389002487 ps
CPU time 10.02 seconds
Started Apr 23 02:37:00 PM PDT 24
Finished Apr 23 02:37:11 PM PDT 24
Peak memory 204028 kb
Host smart-a19b87be-af22-42e7-89a3-ad12be9cdaa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14772
12933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.1477212933
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_enable.2531840107
Short name T84
Test name
Test status
Simulation time 8375151044 ps
CPU time 9.19 seconds
Started Apr 23 02:37:00 PM PDT 24
Finished Apr 23 02:37:10 PM PDT 24
Peak memory 204064 kb
Host smart-a30c4bd7-735c-414b-aeaf-a11eaa63f0d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25318
40107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.2531840107
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.3789255326
Short name T990
Test name
Test status
Simulation time 148031241 ps
CPU time 1.65 seconds
Started Apr 23 02:37:04 PM PDT 24
Finished Apr 23 02:37:06 PM PDT 24
Peak memory 204172 kb
Host smart-772aa966-7768-416d-aa80-f473667cfa18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37892
55326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.3789255326
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.193433187
Short name T490
Test name
Test status
Simulation time 8411601639 ps
CPU time 8.07 seconds
Started Apr 23 02:37:07 PM PDT 24
Finished Apr 23 02:37:16 PM PDT 24
Peak memory 204028 kb
Host smart-a1283720-55b9-42ae-aec4-15245fe66877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19343
3187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.193433187
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.4067154581
Short name T412
Test name
Test status
Simulation time 8361754841 ps
CPU time 7.58 seconds
Started Apr 23 02:37:10 PM PDT 24
Finished Apr 23 02:37:18 PM PDT 24
Peak memory 203960 kb
Host smart-75b66068-8a42-4d18-bbbd-4465c12cf607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40671
54581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.4067154581
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.2263437321
Short name T953
Test name
Test status
Simulation time 8468273623 ps
CPU time 10.46 seconds
Started Apr 23 02:37:05 PM PDT 24
Finished Apr 23 02:37:16 PM PDT 24
Peak memory 203996 kb
Host smart-2480c4a2-fcaa-4677-97d5-283a83b8c5ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22634
37321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.2263437321
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1607079047
Short name T595
Test name
Test status
Simulation time 8414605621 ps
CPU time 8.47 seconds
Started Apr 23 02:37:05 PM PDT 24
Finished Apr 23 02:37:15 PM PDT 24
Peak memory 204024 kb
Host smart-507d8489-0192-405c-8acc-b92a615dfdeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16070
79047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1607079047
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.593671646
Short name T708
Test name
Test status
Simulation time 8374664920 ps
CPU time 8.28 seconds
Started Apr 23 02:37:04 PM PDT 24
Finished Apr 23 02:37:13 PM PDT 24
Peak memory 204012 kb
Host smart-99d1e694-9946-479a-9c1b-27fcf2e41aed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59367
1646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.593671646
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.536073118
Short name T110
Test name
Test status
Simulation time 8450398219 ps
CPU time 7.51 seconds
Started Apr 23 02:37:04 PM PDT 24
Finished Apr 23 02:37:12 PM PDT 24
Peak memory 204000 kb
Host smart-f4ea0a55-67ed-4a7d-9469-94ab3a72df5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53607
3118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.536073118
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.513226671
Short name T1262
Test name
Test status
Simulation time 8426180578 ps
CPU time 9.52 seconds
Started Apr 23 02:37:03 PM PDT 24
Finished Apr 23 02:37:13 PM PDT 24
Peak memory 204012 kb
Host smart-21f6096e-c253-4c33-abbb-f6168c697313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51322
6671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.513226671
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.2466035703
Short name T780
Test name
Test status
Simulation time 8388569807 ps
CPU time 8.15 seconds
Started Apr 23 02:37:06 PM PDT 24
Finished Apr 23 02:37:14 PM PDT 24
Peak memory 204028 kb
Host smart-59ef9c8c-63e4-4e65-bf33-c63db495c105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24660
35703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.2466035703
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.3493979086
Short name T665
Test name
Test status
Simulation time 8406937483 ps
CPU time 8.54 seconds
Started Apr 23 02:37:06 PM PDT 24
Finished Apr 23 02:37:16 PM PDT 24
Peak memory 203984 kb
Host smart-bc766aef-c408-4838-9854-a25c172cbd7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34939
79086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.3493979086
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2472706641
Short name T884
Test name
Test status
Simulation time 42573281 ps
CPU time 0.68 seconds
Started Apr 23 02:37:08 PM PDT 24
Finished Apr 23 02:37:10 PM PDT 24
Peak memory 203872 kb
Host smart-55186c57-43f0-40d7-bef6-cf690a0fa152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24727
06641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2472706641
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.941190022
Short name T870
Test name
Test status
Simulation time 18949252710 ps
CPU time 32.81 seconds
Started Apr 23 02:37:03 PM PDT 24
Finished Apr 23 02:37:36 PM PDT 24
Peak memory 204360 kb
Host smart-c84da99f-8631-4181-bc25-b923189246a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94119
0022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.941190022
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.1062827615
Short name T1233
Test name
Test status
Simulation time 8410027837 ps
CPU time 7.77 seconds
Started Apr 23 02:37:04 PM PDT 24
Finished Apr 23 02:37:12 PM PDT 24
Peak memory 204032 kb
Host smart-3aeaf790-1a55-40b5-bcbc-cc8bcbc49ef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10628
27615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.1062827615
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.3268729088
Short name T1292
Test name
Test status
Simulation time 8403334047 ps
CPU time 7.68 seconds
Started Apr 23 02:37:03 PM PDT 24
Finished Apr 23 02:37:11 PM PDT 24
Peak memory 204016 kb
Host smart-47d3e247-05f8-4580-8c32-102da974dbbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32687
29088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.3268729088
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.1027418938
Short name T622
Test name
Test status
Simulation time 8418794770 ps
CPU time 7.96 seconds
Started Apr 23 02:37:07 PM PDT 24
Finished Apr 23 02:37:16 PM PDT 24
Peak memory 204012 kb
Host smart-274eae12-95ae-4768-95ed-71ef56c9b4cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10274
18938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.1027418938
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.1728717660
Short name T353
Test name
Test status
Simulation time 8373327827 ps
CPU time 7.56 seconds
Started Apr 23 02:37:03 PM PDT 24
Finished Apr 23 02:37:11 PM PDT 24
Peak memory 204016 kb
Host smart-a0e77e4a-0b91-45dc-a957-8be525d924fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17287
17660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.1728717660
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.3028424923
Short name T850
Test name
Test status
Simulation time 8364613962 ps
CPU time 7.62 seconds
Started Apr 23 02:37:08 PM PDT 24
Finished Apr 23 02:37:16 PM PDT 24
Peak memory 204008 kb
Host smart-c82de243-5ffb-498a-94d3-2a7a7883eb89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30284
24923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.3028424923
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2579108781
Short name T891
Test name
Test status
Simulation time 8474453041 ps
CPU time 9.11 seconds
Started Apr 23 02:37:01 PM PDT 24
Finished Apr 23 02:37:11 PM PDT 24
Peak memory 204012 kb
Host smart-c7b1be21-b3c4-4af4-9113-99639988ba5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25791
08781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2579108781
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3498332386
Short name T326
Test name
Test status
Simulation time 8406454022 ps
CPU time 7.86 seconds
Started Apr 23 02:37:04 PM PDT 24
Finished Apr 23 02:37:13 PM PDT 24
Peak memory 204040 kb
Host smart-c4f1c16c-7e75-473f-a644-fd6cf4885b0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34983
32386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3498332386
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.3477870425
Short name T928
Test name
Test status
Simulation time 8382416872 ps
CPU time 10.14 seconds
Started Apr 23 02:37:06 PM PDT 24
Finished Apr 23 02:37:17 PM PDT 24
Peak memory 203980 kb
Host smart-25a67f0d-2dd7-4160-9f2e-43c75d2119a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34778
70425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.3477870425
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.max_length_in_transaction.2041174485
Short name T524
Test name
Test status
Simulation time 8502667621 ps
CPU time 8.4 seconds
Started Apr 23 02:37:09 PM PDT 24
Finished Apr 23 02:37:18 PM PDT 24
Peak memory 204024 kb
Host smart-7820e9b3-0477-4b7f-b797-da3a58ed1873
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2041174485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.2041174485
Directory /workspace/26.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.2369434889
Short name T1272
Test name
Test status
Simulation time 8379561476 ps
CPU time 8.32 seconds
Started Apr 23 02:37:09 PM PDT 24
Finished Apr 23 02:37:18 PM PDT 24
Peak memory 204064 kb
Host smart-896c817e-a8b4-49d0-8062-b096208761ab
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2369434889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.2369434889
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.1086074329
Short name T404
Test name
Test status
Simulation time 8407304775 ps
CPU time 7.84 seconds
Started Apr 23 02:37:10 PM PDT 24
Finished Apr 23 02:37:19 PM PDT 24
Peak memory 204020 kb
Host smart-b40ae9b0-248a-486e-b470-156276b491a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10860
74329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.1086074329
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.3110901511
Short name T1372
Test name
Test status
Simulation time 8419266348 ps
CPU time 8.19 seconds
Started Apr 23 02:37:05 PM PDT 24
Finished Apr 23 02:37:14 PM PDT 24
Peak memory 203956 kb
Host smart-5af1691f-0e2e-4fcb-ba52-226ac437b74b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31109
01511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.3110901511
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_enable.3636325678
Short name T1059
Test name
Test status
Simulation time 8392529180 ps
CPU time 10.14 seconds
Started Apr 23 02:37:07 PM PDT 24
Finished Apr 23 02:37:18 PM PDT 24
Peak memory 204064 kb
Host smart-d69433a4-4a83-4020-a122-17afea6839a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36363
25678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.3636325678
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.3460423202
Short name T576
Test name
Test status
Simulation time 238000595 ps
CPU time 1.93 seconds
Started Apr 23 02:37:08 PM PDT 24
Finished Apr 23 02:37:11 PM PDT 24
Peak memory 204080 kb
Host smart-e8cf79c7-d197-49d6-99db-b3abacf4d3d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34604
23202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.3460423202
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.3905082652
Short name T633
Test name
Test status
Simulation time 8372492944 ps
CPU time 7.61 seconds
Started Apr 23 02:37:09 PM PDT 24
Finished Apr 23 02:37:17 PM PDT 24
Peak memory 204036 kb
Host smart-a12d9969-a38b-4963-8272-da9d43583046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39050
82652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.3905082652
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.3663617273
Short name T193
Test name
Test status
Simulation time 8363610724 ps
CPU time 7.73 seconds
Started Apr 23 02:37:10 PM PDT 24
Finished Apr 23 02:37:19 PM PDT 24
Peak memory 203976 kb
Host smart-4a37f17f-6c2a-4bec-8c74-dba7a6b94c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36636
17273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.3663617273
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3965185189
Short name T1211
Test name
Test status
Simulation time 8469283397 ps
CPU time 8.23 seconds
Started Apr 23 02:37:07 PM PDT 24
Finished Apr 23 02:37:16 PM PDT 24
Peak memory 203984 kb
Host smart-20bfbed1-322c-49e3-ac77-4de65cafd4dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39651
85189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3965185189
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3484063146
Short name T818
Test name
Test status
Simulation time 8426340743 ps
CPU time 8.39 seconds
Started Apr 23 02:37:07 PM PDT 24
Finished Apr 23 02:37:16 PM PDT 24
Peak memory 204020 kb
Host smart-a70c33c6-ef7d-467a-9c31-d05fdb689152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34840
63146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3484063146
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2188180609
Short name T598
Test name
Test status
Simulation time 8464945013 ps
CPU time 10.16 seconds
Started Apr 23 02:37:06 PM PDT 24
Finished Apr 23 02:37:17 PM PDT 24
Peak memory 204004 kb
Host smart-dfd51003-4287-47e9-bdbe-0ece45a422ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21881
80609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2188180609
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.2588725883
Short name T122
Test name
Test status
Simulation time 8426274276 ps
CPU time 8.32 seconds
Started Apr 23 02:37:07 PM PDT 24
Finished Apr 23 02:37:16 PM PDT 24
Peak memory 204040 kb
Host smart-49b3219f-b606-4080-a823-5efc1eac85ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25887
25883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2588725883
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.457025253
Short name T786
Test name
Test status
Simulation time 8411669620 ps
CPU time 8.36 seconds
Started Apr 23 02:37:08 PM PDT 24
Finished Apr 23 02:37:17 PM PDT 24
Peak memory 203968 kb
Host smart-69aad957-39a2-40f3-817c-1e1baf011192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45702
5253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.457025253
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.3255941291
Short name T888
Test name
Test status
Simulation time 8399205273 ps
CPU time 7.76 seconds
Started Apr 23 02:37:09 PM PDT 24
Finished Apr 23 02:37:17 PM PDT 24
Peak memory 204032 kb
Host smart-572628e7-0f69-42a2-b7ca-3747dc1a1028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32559
41291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3255941291
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.1277390984
Short name T175
Test name
Test status
Simulation time 8440115587 ps
CPU time 8.69 seconds
Started Apr 23 02:37:10 PM PDT 24
Finished Apr 23 02:37:20 PM PDT 24
Peak memory 204008 kb
Host smart-0945ff4b-aa5f-456e-9a22-d01ae8401b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12773
90984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.1277390984
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.2165058783
Short name T482
Test name
Test status
Simulation time 8366603347 ps
CPU time 8.39 seconds
Started Apr 23 02:37:12 PM PDT 24
Finished Apr 23 02:37:21 PM PDT 24
Peak memory 204052 kb
Host smart-c697c06f-d6bb-4213-9fbb-8d77d3590215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21650
58783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2165058783
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.2285009723
Short name T12
Test name
Test status
Simulation time 66879029 ps
CPU time 0.67 seconds
Started Apr 23 02:37:10 PM PDT 24
Finished Apr 23 02:37:12 PM PDT 24
Peak memory 203892 kb
Host smart-84d4534d-3ba2-4278-8270-f5a4e25ae992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22850
09723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.2285009723
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.1351720202
Short name T1103
Test name
Test status
Simulation time 20969746592 ps
CPU time 38.93 seconds
Started Apr 23 02:37:09 PM PDT 24
Finished Apr 23 02:37:49 PM PDT 24
Peak memory 204252 kb
Host smart-3d7f2fa3-27bd-44e0-95b3-937a028b38a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13517
20202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.1351720202
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.3882756883
Short name T1071
Test name
Test status
Simulation time 8373883924 ps
CPU time 9.26 seconds
Started Apr 23 02:37:09 PM PDT 24
Finished Apr 23 02:37:19 PM PDT 24
Peak memory 204056 kb
Host smart-5d86d607-e2d3-44b4-a10f-a48309a3331b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38827
56883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.3882756883
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.1534840254
Short name T802
Test name
Test status
Simulation time 8425801802 ps
CPU time 8.42 seconds
Started Apr 23 02:37:10 PM PDT 24
Finished Apr 23 02:37:20 PM PDT 24
Peak memory 203968 kb
Host smart-7bb2a7e4-4107-40d0-bc48-c2ae83071501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15348
40254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1534840254
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.271502919
Short name T831
Test name
Test status
Simulation time 8388728350 ps
CPU time 7.67 seconds
Started Apr 23 02:37:10 PM PDT 24
Finished Apr 23 02:37:19 PM PDT 24
Peak memory 203964 kb
Host smart-0db7340e-c800-42b2-845a-0b141988148b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27150
2919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.271502919
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.2116806062
Short name T1120
Test name
Test status
Simulation time 8376689436 ps
CPU time 8.29 seconds
Started Apr 23 02:37:09 PM PDT 24
Finished Apr 23 02:37:18 PM PDT 24
Peak memory 203952 kb
Host smart-dc8d0de0-8a3c-4510-8e14-c0b022ee7930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21168
06062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.2116806062
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.1130255547
Short name T1213
Test name
Test status
Simulation time 8373446004 ps
CPU time 8.68 seconds
Started Apr 23 02:37:10 PM PDT 24
Finished Apr 23 02:37:19 PM PDT 24
Peak memory 203984 kb
Host smart-93530357-6062-42b0-87af-c3e4c936c401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11302
55547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.1130255547
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.4101752728
Short name T1089
Test name
Test status
Simulation time 8482023419 ps
CPU time 7.88 seconds
Started Apr 23 02:37:08 PM PDT 24
Finished Apr 23 02:37:17 PM PDT 24
Peak memory 204060 kb
Host smart-ac8be8fa-7526-4109-9142-e44be18a169d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41017
52728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.4101752728
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.3981789839
Short name T405
Test name
Test status
Simulation time 8375058786 ps
CPU time 7.74 seconds
Started Apr 23 02:37:10 PM PDT 24
Finished Apr 23 02:37:19 PM PDT 24
Peak memory 204012 kb
Host smart-6dcef4c9-4543-4585-bb97-d6c362263bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39817
89839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.3981789839
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.1942545888
Short name T713
Test name
Test status
Simulation time 8369040321 ps
CPU time 7.56 seconds
Started Apr 23 02:37:06 PM PDT 24
Finished Apr 23 02:37:14 PM PDT 24
Peak memory 204008 kb
Host smart-2a716204-9d98-4e68-9692-3263edfe1a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19425
45888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.1942545888
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.4019542108
Short name T139
Test name
Test status
Simulation time 8468458606 ps
CPU time 7.69 seconds
Started Apr 23 02:37:17 PM PDT 24
Finished Apr 23 02:37:26 PM PDT 24
Peak memory 204068 kb
Host smart-43a503e7-a8fa-4d63-ae6a-a11fa704754b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4019542108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.4019542108
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.876597185
Short name T1218
Test name
Test status
Simulation time 8374953406 ps
CPU time 7.61 seconds
Started Apr 23 02:37:20 PM PDT 24
Finished Apr 23 02:37:28 PM PDT 24
Peak memory 203960 kb
Host smart-40f0f87e-a2d5-43ce-a7f1-7f4771c25f4b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=876597185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.876597185
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.3136782463
Short name T930
Test name
Test status
Simulation time 8456470182 ps
CPU time 7.93 seconds
Started Apr 23 02:37:16 PM PDT 24
Finished Apr 23 02:37:25 PM PDT 24
Peak memory 204008 kb
Host smart-c8ba70d0-16b1-48cf-8b7a-66624a918bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31367
82463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.3136782463
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.679210427
Short name T895
Test name
Test status
Simulation time 8384859260 ps
CPU time 8.92 seconds
Started Apr 23 02:37:13 PM PDT 24
Finished Apr 23 02:37:23 PM PDT 24
Peak memory 204004 kb
Host smart-74ac831e-7fc0-40dd-b864-2d812ec1b1dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67921
0427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.679210427
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_enable.380741996
Short name T1317
Test name
Test status
Simulation time 8379484425 ps
CPU time 7.77 seconds
Started Apr 23 02:37:14 PM PDT 24
Finished Apr 23 02:37:22 PM PDT 24
Peak memory 204032 kb
Host smart-a7f65600-aae3-4dd8-a6b9-3b6c81713177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38074
1996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.380741996
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.2884200082
Short name T629
Test name
Test status
Simulation time 117231262 ps
CPU time 1.46 seconds
Started Apr 23 02:37:13 PM PDT 24
Finished Apr 23 02:37:15 PM PDT 24
Peak memory 204168 kb
Host smart-7ca86f70-005d-4c5f-8247-cad6f2d373b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28842
00082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2884200082
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.127799475
Short name T1189
Test name
Test status
Simulation time 8423776773 ps
CPU time 8.53 seconds
Started Apr 23 02:37:24 PM PDT 24
Finished Apr 23 02:37:34 PM PDT 24
Peak memory 204060 kb
Host smart-f3f68332-e765-4aea-bb2f-972843fc5bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12779
9475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.127799475
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.4173457445
Short name T189
Test name
Test status
Simulation time 8367374144 ps
CPU time 8.35 seconds
Started Apr 23 02:37:18 PM PDT 24
Finished Apr 23 02:37:27 PM PDT 24
Peak memory 203996 kb
Host smart-03c8308e-fae3-4dd7-a214-3251dd2a0da0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41734
57445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.4173457445
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.1066936599
Short name T149
Test name
Test status
Simulation time 8517766191 ps
CPU time 8.94 seconds
Started Apr 23 02:37:15 PM PDT 24
Finished Apr 23 02:37:24 PM PDT 24
Peak memory 203980 kb
Host smart-77af2850-6f4b-47d8-92e3-f28a6ce16d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10669
36599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.1066936599
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.4094528245
Short name T634
Test name
Test status
Simulation time 8417347038 ps
CPU time 7.7 seconds
Started Apr 23 02:37:12 PM PDT 24
Finished Apr 23 02:37:21 PM PDT 24
Peak memory 204060 kb
Host smart-b6d788c7-329c-49e2-8ec2-3aaec522b54e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40945
28245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.4094528245
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.1341879365
Short name T685
Test name
Test status
Simulation time 8382862923 ps
CPU time 9.69 seconds
Started Apr 23 02:37:16 PM PDT 24
Finished Apr 23 02:37:26 PM PDT 24
Peak memory 204004 kb
Host smart-a27c3460-cad3-47d1-b91f-b6ddad801007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13418
79365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.1341879365
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.2563742990
Short name T113
Test name
Test status
Simulation time 8416066973 ps
CPU time 8.34 seconds
Started Apr 23 02:37:17 PM PDT 24
Finished Apr 23 02:37:26 PM PDT 24
Peak memory 203996 kb
Host smart-09ff3886-ac76-4391-a698-113efbe2cc78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25637
42990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2563742990
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.3333265596
Short name T1036
Test name
Test status
Simulation time 8427235881 ps
CPU time 7.74 seconds
Started Apr 23 02:37:12 PM PDT 24
Finished Apr 23 02:37:20 PM PDT 24
Peak memory 204024 kb
Host smart-49ea88c3-b4a2-4e20-8a5f-57b3371ab556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33332
65596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.3333265596
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.2461346425
Short name T325
Test name
Test status
Simulation time 8380292755 ps
CPU time 8.35 seconds
Started Apr 23 02:37:12 PM PDT 24
Finished Apr 23 02:37:21 PM PDT 24
Peak memory 204004 kb
Host smart-47850bd5-897f-48df-92a3-b81f8025003b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24613
46425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.2461346425
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.3943923788
Short name T1094
Test name
Test status
Simulation time 8399362501 ps
CPU time 7.86 seconds
Started Apr 23 02:37:23 PM PDT 24
Finished Apr 23 02:37:31 PM PDT 24
Peak memory 204016 kb
Host smart-f110fa50-0902-406d-b715-79c84777736c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39439
23788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.3943923788
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.1300014970
Short name T628
Test name
Test status
Simulation time 8366353134 ps
CPU time 7.96 seconds
Started Apr 23 02:37:13 PM PDT 24
Finished Apr 23 02:37:22 PM PDT 24
Peak memory 204024 kb
Host smart-e822a591-a7e2-417e-a210-88e6d1b4cd3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13000
14970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.1300014970
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.2554771076
Short name T1057
Test name
Test status
Simulation time 66015896 ps
CPU time 0.68 seconds
Started Apr 23 02:37:21 PM PDT 24
Finished Apr 23 02:37:23 PM PDT 24
Peak memory 203884 kb
Host smart-e731c0a9-3393-4fb1-8ea7-a1cfabc7734b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25547
71076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.2554771076
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.975978992
Short name T266
Test name
Test status
Simulation time 27972199370 ps
CPU time 52.35 seconds
Started Apr 23 02:37:12 PM PDT 24
Finished Apr 23 02:38:05 PM PDT 24
Peak memory 204348 kb
Host smart-9b6463d6-7785-4015-a9dd-279a1f87b102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97597
8992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.975978992
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.4110812965
Short name T684
Test name
Test status
Simulation time 8407774515 ps
CPU time 7.87 seconds
Started Apr 23 02:37:12 PM PDT 24
Finished Apr 23 02:37:20 PM PDT 24
Peak memory 204028 kb
Host smart-dd9e03dd-7a25-498f-a503-8b36793b340b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41108
12965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.4110812965
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.4290376518
Short name T50
Test name
Test status
Simulation time 8453078107 ps
CPU time 8.21 seconds
Started Apr 23 02:37:14 PM PDT 24
Finished Apr 23 02:37:23 PM PDT 24
Peak memory 204056 kb
Host smart-da627c83-242b-4590-86bf-0b4564ec31ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42903
76518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.4290376518
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.1746816458
Short name T557
Test name
Test status
Simulation time 8413590465 ps
CPU time 8.79 seconds
Started Apr 23 02:37:14 PM PDT 24
Finished Apr 23 02:37:23 PM PDT 24
Peak memory 204020 kb
Host smart-e8a33f82-9de4-44f8-a90f-8b7feb378c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17468
16458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.1746816458
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.1973979476
Short name T169
Test name
Test status
Simulation time 8376031706 ps
CPU time 9.37 seconds
Started Apr 23 02:37:16 PM PDT 24
Finished Apr 23 02:37:26 PM PDT 24
Peak memory 204000 kb
Host smart-c1c87975-d101-4780-8e27-4e050446adb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19739
79476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.1973979476
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.3147009551
Short name T914
Test name
Test status
Simulation time 8374458612 ps
CPU time 9.29 seconds
Started Apr 23 02:37:18 PM PDT 24
Finished Apr 23 02:37:28 PM PDT 24
Peak memory 204052 kb
Host smart-ad6c3a5f-932a-439f-b97c-d2ef42646da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31470
09551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.3147009551
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2808133818
Short name T178
Test name
Test status
Simulation time 8458253203 ps
CPU time 9 seconds
Started Apr 23 02:37:13 PM PDT 24
Finished Apr 23 02:37:23 PM PDT 24
Peak memory 204048 kb
Host smart-35d6efa6-70e3-412d-b069-0026e50ccc1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28081
33818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2808133818
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3984662050
Short name T610
Test name
Test status
Simulation time 8391297031 ps
CPU time 8.26 seconds
Started Apr 23 02:37:12 PM PDT 24
Finished Apr 23 02:37:21 PM PDT 24
Peak memory 204056 kb
Host smart-707491af-a3df-4c25-8763-2f80f71b3982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39846
62050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3984662050
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.2643703615
Short name T830
Test name
Test status
Simulation time 8378196270 ps
CPU time 8.02 seconds
Started Apr 23 02:37:14 PM PDT 24
Finished Apr 23 02:37:22 PM PDT 24
Peak memory 204040 kb
Host smart-24e0968c-7788-4480-aa7c-2e49c859b5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26437
03615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.2643703615
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.2044992164
Short name T1151
Test name
Test status
Simulation time 8464171837 ps
CPU time 8.15 seconds
Started Apr 23 02:37:19 PM PDT 24
Finished Apr 23 02:37:28 PM PDT 24
Peak memory 204020 kb
Host smart-06b62723-2950-4113-be69-b9baef45ca20
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2044992164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.2044992164
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.1910556354
Short name T505
Test name
Test status
Simulation time 8419659543 ps
CPU time 7.64 seconds
Started Apr 23 02:37:19 PM PDT 24
Finished Apr 23 02:37:28 PM PDT 24
Peak memory 203948 kb
Host smart-4a316b1f-69a5-48cf-b35a-bd9655a3136b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1910556354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.1910556354
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.3244686227
Short name T1192
Test name
Test status
Simulation time 8383911619 ps
CPU time 8.21 seconds
Started Apr 23 02:37:17 PM PDT 24
Finished Apr 23 02:37:26 PM PDT 24
Peak memory 204008 kb
Host smart-e54b18fc-74ce-415f-8ac2-8ae1e987f85b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32446
86227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.3244686227
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.713478379
Short name T705
Test name
Test status
Simulation time 8371603533 ps
CPU time 9.64 seconds
Started Apr 23 02:37:20 PM PDT 24
Finished Apr 23 02:37:30 PM PDT 24
Peak memory 204040 kb
Host smart-46850e84-3437-4155-b7e4-2d45333a01d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71347
8379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.713478379
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_enable.1604469450
Short name T376
Test name
Test status
Simulation time 8373873973 ps
CPU time 8.1 seconds
Started Apr 23 02:37:26 PM PDT 24
Finished Apr 23 02:37:35 PM PDT 24
Peak memory 204060 kb
Host smart-1067cb32-c624-4fcf-a2a5-372f28605048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16044
69450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.1604469450
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.2421528480
Short name T1109
Test name
Test status
Simulation time 144904228 ps
CPU time 1.6 seconds
Started Apr 23 02:37:18 PM PDT 24
Finished Apr 23 02:37:20 PM PDT 24
Peak memory 204108 kb
Host smart-222a2847-69bd-4036-895a-4fce1dfe0ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24215
28480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2421528480
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.2048287622
Short name T987
Test name
Test status
Simulation time 8402486212 ps
CPU time 9.73 seconds
Started Apr 23 02:37:24 PM PDT 24
Finished Apr 23 02:37:35 PM PDT 24
Peak memory 204060 kb
Host smart-925efc32-7023-49b7-911d-62aeb224a2b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20482
87622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.2048287622
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.497048861
Short name T906
Test name
Test status
Simulation time 8363655370 ps
CPU time 10.2 seconds
Started Apr 23 02:37:17 PM PDT 24
Finished Apr 23 02:37:28 PM PDT 24
Peak memory 204020 kb
Host smart-a4a8dd9b-19d0-4bf6-a809-0fcad0a5230f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49704
8861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.497048861
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.4274799669
Short name T807
Test name
Test status
Simulation time 8446031548 ps
CPU time 9.75 seconds
Started Apr 23 02:37:21 PM PDT 24
Finished Apr 23 02:37:32 PM PDT 24
Peak memory 203964 kb
Host smart-d7880189-de48-41d5-943f-a39252928267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42747
99669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.4274799669
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.3380336977
Short name T291
Test name
Test status
Simulation time 8430413441 ps
CPU time 7.88 seconds
Started Apr 23 02:37:20 PM PDT 24
Finished Apr 23 02:37:28 PM PDT 24
Peak memory 203992 kb
Host smart-557af4dc-5349-4bde-b16e-c892e9d4a0bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33803
36977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3380336977
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.1360387739
Short name T554
Test name
Test status
Simulation time 8382294166 ps
CPU time 9.03 seconds
Started Apr 23 02:37:18 PM PDT 24
Finished Apr 23 02:37:28 PM PDT 24
Peak memory 204060 kb
Host smart-a376ffba-25a1-4ac8-90a4-de91840dc0a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13603
87739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.1360387739
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.2966287604
Short name T670
Test name
Test status
Simulation time 8475373989 ps
CPU time 9.28 seconds
Started Apr 23 02:37:25 PM PDT 24
Finished Apr 23 02:37:35 PM PDT 24
Peak memory 204060 kb
Host smart-b3c1292b-4610-463e-b010-60f0efb077f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29662
87604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.2966287604
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.465595335
Short name T1245
Test name
Test status
Simulation time 8383016769 ps
CPU time 8.2 seconds
Started Apr 23 02:37:17 PM PDT 24
Finished Apr 23 02:37:26 PM PDT 24
Peak memory 204012 kb
Host smart-935a9386-75d6-47bb-a52d-7012e48a4dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46559
5335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.465595335
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.3415206801
Short name T317
Test name
Test status
Simulation time 8413448470 ps
CPU time 8.09 seconds
Started Apr 23 02:37:19 PM PDT 24
Finished Apr 23 02:37:28 PM PDT 24
Peak memory 204012 kb
Host smart-fd46e853-6afc-4c30-9b1e-d60c7ef0951e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34152
06801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.3415206801
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.3235785613
Short name T571
Test name
Test status
Simulation time 8374877160 ps
CPU time 8.02 seconds
Started Apr 23 02:37:18 PM PDT 24
Finished Apr 23 02:37:26 PM PDT 24
Peak memory 204012 kb
Host smart-d0b88e17-c6ec-4aeb-901d-984839741313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32357
85613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.3235785613
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.1723989095
Short name T922
Test name
Test status
Simulation time 8375130258 ps
CPU time 7.48 seconds
Started Apr 23 02:37:30 PM PDT 24
Finished Apr 23 02:37:38 PM PDT 24
Peak memory 203960 kb
Host smart-01e2f975-3335-4c47-b5b9-01daca5eb393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17239
89095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1723989095
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.1884297109
Short name T1308
Test name
Test status
Simulation time 54939006 ps
CPU time 0.69 seconds
Started Apr 23 02:37:19 PM PDT 24
Finished Apr 23 02:37:21 PM PDT 24
Peak memory 203868 kb
Host smart-954ba0b0-e5a5-445a-8c49-6202ee6e49c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18842
97109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.1884297109
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.3258415757
Short name T1067
Test name
Test status
Simulation time 23077359731 ps
CPU time 47.37 seconds
Started Apr 23 02:37:22 PM PDT 24
Finished Apr 23 02:38:10 PM PDT 24
Peak memory 204336 kb
Host smart-18261621-6f78-460a-807e-98b16a48d856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32584
15757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.3258415757
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.38421994
Short name T309
Test name
Test status
Simulation time 8402298758 ps
CPU time 10.26 seconds
Started Apr 23 02:37:25 PM PDT 24
Finished Apr 23 02:37:35 PM PDT 24
Peak memory 203968 kb
Host smart-f8349637-a599-4b9d-b08a-f2265a69a557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38421
994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.38421994
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.784746214
Short name T446
Test name
Test status
Simulation time 8497807017 ps
CPU time 7.47 seconds
Started Apr 23 02:37:22 PM PDT 24
Finished Apr 23 02:37:30 PM PDT 24
Peak memory 204052 kb
Host smart-2aa66033-b359-4b4c-bb4a-bc7cbe6f8f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78474
6214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.784746214
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.274536096
Short name T772
Test name
Test status
Simulation time 8385913683 ps
CPU time 7.49 seconds
Started Apr 23 02:37:19 PM PDT 24
Finished Apr 23 02:37:27 PM PDT 24
Peak memory 203984 kb
Host smart-aaa8f773-60d0-41dc-ba2e-d4b388c823fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27453
6096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.274536096
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.854830413
Short name T790
Test name
Test status
Simulation time 8385047051 ps
CPU time 8.28 seconds
Started Apr 23 02:37:24 PM PDT 24
Finished Apr 23 02:37:33 PM PDT 24
Peak memory 203968 kb
Host smart-bb6961a4-7d03-43f5-9a87-ad731e55829f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85483
0413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.854830413
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.2126940123
Short name T535
Test name
Test status
Simulation time 8379392713 ps
CPU time 8.06 seconds
Started Apr 23 02:37:26 PM PDT 24
Finished Apr 23 02:37:34 PM PDT 24
Peak memory 203960 kb
Host smart-e450486e-ef9f-4686-b6cd-f0388cfccfbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21269
40123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.2126940123
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.2690737366
Short name T532
Test name
Test status
Simulation time 8455888480 ps
CPU time 8.5 seconds
Started Apr 23 02:37:23 PM PDT 24
Finished Apr 23 02:37:32 PM PDT 24
Peak memory 204020 kb
Host smart-35ffacb5-6e15-48c9-a12e-e06b9c108125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26907
37366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2690737366
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.2811166494
Short name T129
Test name
Test status
Simulation time 8401463866 ps
CPU time 7.81 seconds
Started Apr 23 02:37:18 PM PDT 24
Finished Apr 23 02:37:26 PM PDT 24
Peak memory 203996 kb
Host smart-ad35bd2c-af46-4563-bf2b-8c3ad996c5ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28111
66494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.2811166494
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.2675274428
Short name T539
Test name
Test status
Simulation time 8406186384 ps
CPU time 8.19 seconds
Started Apr 23 02:37:21 PM PDT 24
Finished Apr 23 02:37:30 PM PDT 24
Peak memory 204004 kb
Host smart-15170729-0d67-4912-bae2-bdc7aaa4e91c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26752
74428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.2675274428
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.398350725
Short name T458
Test name
Test status
Simulation time 8497042626 ps
CPU time 7.81 seconds
Started Apr 23 02:37:29 PM PDT 24
Finished Apr 23 02:37:37 PM PDT 24
Peak memory 204048 kb
Host smart-382da756-c6b4-479f-8553-e68e335e1021
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=398350725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.398350725
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.2252110618
Short name T958
Test name
Test status
Simulation time 8380042768 ps
CPU time 8.7 seconds
Started Apr 23 02:37:24 PM PDT 24
Finished Apr 23 02:37:33 PM PDT 24
Peak memory 203988 kb
Host smart-b580c2d4-9b04-4367-bae2-84a2df14331d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2252110618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.2252110618
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.2936845281
Short name T769
Test name
Test status
Simulation time 8398083843 ps
CPU time 7.86 seconds
Started Apr 23 02:37:19 PM PDT 24
Finished Apr 23 02:37:28 PM PDT 24
Peak memory 203980 kb
Host smart-d3bec438-2fac-409e-bca9-2b262b6801cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29368
45281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.2936845281
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.1865088018
Short name T1085
Test name
Test status
Simulation time 8386333349 ps
CPU time 9.78 seconds
Started Apr 23 02:37:22 PM PDT 24
Finished Apr 23 02:37:32 PM PDT 24
Peak memory 204012 kb
Host smart-670da91a-02eb-4166-a87c-19656c2620b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18650
88018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1865088018
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_enable.3589450470
Short name T1023
Test name
Test status
Simulation time 8377309121 ps
CPU time 8.2 seconds
Started Apr 23 02:37:35 PM PDT 24
Finished Apr 23 02:37:45 PM PDT 24
Peak memory 204048 kb
Host smart-3ca26f3e-bc14-4b4c-8794-86e94da32cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35894
50470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3589450470
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.2253228065
Short name T1279
Test name
Test status
Simulation time 121243574 ps
CPU time 1.39 seconds
Started Apr 23 02:37:20 PM PDT 24
Finished Apr 23 02:37:22 PM PDT 24
Peak memory 204048 kb
Host smart-0f6031ac-a25c-48dd-9a71-4538a1f320cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22532
28065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.2253228065
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.85318028
Short name T1009
Test name
Test status
Simulation time 8470210571 ps
CPU time 8.32 seconds
Started Apr 23 02:37:35 PM PDT 24
Finished Apr 23 02:37:44 PM PDT 24
Peak memory 204060 kb
Host smart-a1f1d098-fe36-4359-8597-2ce0d7fe8ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85318
028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.85318028
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.1593709444
Short name T568
Test name
Test status
Simulation time 8424456888 ps
CPU time 9.37 seconds
Started Apr 23 02:37:19 PM PDT 24
Finished Apr 23 02:37:29 PM PDT 24
Peak memory 204060 kb
Host smart-ee6d5a0b-5593-4ccf-838e-d0dc0bcf4b4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15937
09444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.1593709444
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.3330333373
Short name T591
Test name
Test status
Simulation time 8432512243 ps
CPU time 8.13 seconds
Started Apr 23 02:37:23 PM PDT 24
Finished Apr 23 02:37:31 PM PDT 24
Peak memory 204024 kb
Host smart-46b2dbdb-0521-49ce-9a0a-5795c2f5884d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33303
33373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3330333373
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.2112671336
Short name T1030
Test name
Test status
Simulation time 8411736091 ps
CPU time 7.77 seconds
Started Apr 23 02:37:33 PM PDT 24
Finished Apr 23 02:37:42 PM PDT 24
Peak memory 204056 kb
Host smart-01dbdbaa-84f8-4208-b821-90a2225cc5a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21126
71336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.2112671336
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.1916090659
Short name T566
Test name
Test status
Simulation time 8384383669 ps
CPU time 7.55 seconds
Started Apr 23 02:37:24 PM PDT 24
Finished Apr 23 02:37:33 PM PDT 24
Peak memory 203976 kb
Host smart-6909b310-f012-46ce-abc6-d05daf74c074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19160
90659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.1916090659
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.2815211146
Short name T1316
Test name
Test status
Simulation time 8435721131 ps
CPU time 7.6 seconds
Started Apr 23 02:37:35 PM PDT 24
Finished Apr 23 02:37:44 PM PDT 24
Peak memory 204060 kb
Host smart-4fbbd4f4-2bb3-4374-bc3f-11f91c58008f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28152
11146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.2815211146
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.5206674
Short name T431
Test name
Test status
Simulation time 8403594766 ps
CPU time 7.8 seconds
Started Apr 23 02:37:22 PM PDT 24
Finished Apr 23 02:37:31 PM PDT 24
Peak memory 204052 kb
Host smart-10d1c37a-12cd-4c24-877d-b23c34f20ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52066
74 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.5206674
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.3102688635
Short name T1352
Test name
Test status
Simulation time 8395074366 ps
CPU time 8.01 seconds
Started Apr 23 02:37:21 PM PDT 24
Finished Apr 23 02:37:30 PM PDT 24
Peak memory 204032 kb
Host smart-a76ab264-bb71-4ac1-87ae-d0f6bec1a129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31026
88635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3102688635
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.1029376906
Short name T1280
Test name
Test status
Simulation time 8421998643 ps
CPU time 8.1 seconds
Started Apr 23 02:37:21 PM PDT 24
Finished Apr 23 02:37:29 PM PDT 24
Peak memory 203984 kb
Host smart-b77bbcc0-6463-4064-bf6b-fa767969d7c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10293
76906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.1029376906
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.56947332
Short name T960
Test name
Test status
Simulation time 8373095402 ps
CPU time 8 seconds
Started Apr 23 02:37:25 PM PDT 24
Finished Apr 23 02:37:34 PM PDT 24
Peak memory 204040 kb
Host smart-d12c35bb-f690-4828-a951-a6149e95edfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56947
332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.56947332
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.4215607259
Short name T687
Test name
Test status
Simulation time 62327011 ps
CPU time 0.73 seconds
Started Apr 23 02:37:24 PM PDT 24
Finished Apr 23 02:37:26 PM PDT 24
Peak memory 203848 kb
Host smart-d0a428b9-d1de-40fb-818f-440e11abaf58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42156
07259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.4215607259
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.3779005296
Short name T1285
Test name
Test status
Simulation time 27265145878 ps
CPU time 52.23 seconds
Started Apr 23 02:37:24 PM PDT 24
Finished Apr 23 02:38:17 PM PDT 24
Peak memory 204260 kb
Host smart-be37a180-ff05-4212-84fa-74b05d55860f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37790
05296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.3779005296
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.373458375
Short name T800
Test name
Test status
Simulation time 8409076520 ps
CPU time 7.66 seconds
Started Apr 23 02:37:21 PM PDT 24
Finished Apr 23 02:37:30 PM PDT 24
Peak memory 204024 kb
Host smart-40f7f21d-7679-4f61-a1cc-4933b9e696ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37345
8375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.373458375
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.1790607955
Short name T648
Test name
Test status
Simulation time 8391604155 ps
CPU time 8.07 seconds
Started Apr 23 02:37:33 PM PDT 24
Finished Apr 23 02:37:42 PM PDT 24
Peak memory 204060 kb
Host smart-ecafe057-60a6-4645-a157-a86690513d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17906
07955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.1790607955
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.150968263
Short name T1013
Test name
Test status
Simulation time 8390671336 ps
CPU time 8.11 seconds
Started Apr 23 02:37:22 PM PDT 24
Finished Apr 23 02:37:30 PM PDT 24
Peak memory 204008 kb
Host smart-71fc4d39-1335-4df1-8f70-31ee80431e0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15096
8263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.150968263
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.336875940
Short name T1309
Test name
Test status
Simulation time 8376699728 ps
CPU time 7.72 seconds
Started Apr 23 02:37:20 PM PDT 24
Finished Apr 23 02:37:28 PM PDT 24
Peak memory 204004 kb
Host smart-a0648050-c00a-4438-a928-2db27cfeaaf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33687
5940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.336875940
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.3822462237
Short name T1253
Test name
Test status
Simulation time 8367310392 ps
CPU time 8.38 seconds
Started Apr 23 02:37:34 PM PDT 24
Finished Apr 23 02:37:44 PM PDT 24
Peak memory 204040 kb
Host smart-33c4785f-9935-449d-9a6f-81d7c4a97894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38224
62237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3822462237
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.3458339018
Short name T529
Test name
Test status
Simulation time 8435080524 ps
CPU time 7.98 seconds
Started Apr 23 02:37:34 PM PDT 24
Finished Apr 23 02:37:43 PM PDT 24
Peak memory 204048 kb
Host smart-06f9edc2-5836-4ab1-b6d7-8d840ac56091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34583
39018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.3458339018
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.3268181357
Short name T663
Test name
Test status
Simulation time 8372867987 ps
CPU time 8.05 seconds
Started Apr 23 02:37:33 PM PDT 24
Finished Apr 23 02:37:42 PM PDT 24
Peak memory 204052 kb
Host smart-08d92171-e049-418d-8baf-b0fd1c81f117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32681
81357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.3268181357
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.3037675655
Short name T298
Test name
Test status
Simulation time 8423673567 ps
CPU time 8.66 seconds
Started Apr 23 02:37:19 PM PDT 24
Finished Apr 23 02:37:28 PM PDT 24
Peak memory 204056 kb
Host smart-cbd01783-98f9-40ed-98e7-dc9e4690fff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30376
75655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.3037675655
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.1315308659
Short name T17
Test name
Test status
Simulation time 8458395831 ps
CPU time 8.89 seconds
Started Apr 23 02:35:20 PM PDT 24
Finished Apr 23 02:35:30 PM PDT 24
Peak memory 204004 kb
Host smart-2862f7d6-25b4-4168-b99a-be0e11f27a28
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1315308659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.1315308659
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.3229951392
Short name T449
Test name
Test status
Simulation time 8397094931 ps
CPU time 7.67 seconds
Started Apr 23 02:35:20 PM PDT 24
Finished Apr 23 02:35:29 PM PDT 24
Peak memory 203980 kb
Host smart-729282f0-71b3-49ac-a3e9-56e878ae4629
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3229951392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.3229951392
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.1822807351
Short name T400
Test name
Test status
Simulation time 8473875852 ps
CPU time 9.19 seconds
Started Apr 23 02:35:21 PM PDT 24
Finished Apr 23 02:35:31 PM PDT 24
Peak memory 204052 kb
Host smart-cd6c5fea-47ba-425c-8916-692b33d6bc6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18228
07351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.1822807351
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1968249029
Short name T781
Test name
Test status
Simulation time 8377046668 ps
CPU time 7.95 seconds
Started Apr 23 02:35:17 PM PDT 24
Finished Apr 23 02:35:26 PM PDT 24
Peak memory 204052 kb
Host smart-8238ff6d-6c01-47a4-9cfc-7e1bc08efb85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19682
49029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1968249029
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_enable.2758289484
Short name T1012
Test name
Test status
Simulation time 8399423654 ps
CPU time 8.34 seconds
Started Apr 23 02:35:16 PM PDT 24
Finished Apr 23 02:35:26 PM PDT 24
Peak memory 204048 kb
Host smart-98436b49-5b1d-44ee-8923-7c44a9544786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27582
89484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.2758289484
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.1075549027
Short name T1007
Test name
Test status
Simulation time 231542373 ps
CPU time 2.15 seconds
Started Apr 23 02:35:17 PM PDT 24
Finished Apr 23 02:35:20 PM PDT 24
Peak memory 204144 kb
Host smart-3ecfd648-e1a9-46d7-bd5d-12b90a4733ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10755
49027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.1075549027
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1549214141
Short name T1171
Test name
Test status
Simulation time 8406054291 ps
CPU time 8.04 seconds
Started Apr 23 02:35:20 PM PDT 24
Finished Apr 23 02:35:29 PM PDT 24
Peak memory 204064 kb
Host smart-1b98e1c2-cdcc-4ccc-b5e9-9e238b4d980d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15492
14141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1549214141
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.4035218584
Short name T841
Test name
Test status
Simulation time 8440930394 ps
CPU time 8.31 seconds
Started Apr 23 02:35:21 PM PDT 24
Finished Apr 23 02:35:30 PM PDT 24
Peak memory 203992 kb
Host smart-ceffa3a9-bb15-4e50-92e1-05e1cd3e7328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40352
18584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.4035218584
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.3900005829
Short name T531
Test name
Test status
Simulation time 8436963851 ps
CPU time 9.05 seconds
Started Apr 23 02:35:17 PM PDT 24
Finished Apr 23 02:35:27 PM PDT 24
Peak memory 204024 kb
Host smart-f36d91e4-e0ef-4d73-9dc2-85097c2e70c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39000
05829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.3900005829
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.150402680
Short name T919
Test name
Test status
Simulation time 8434044358 ps
CPU time 8.39 seconds
Started Apr 23 02:35:20 PM PDT 24
Finished Apr 23 02:35:30 PM PDT 24
Peak memory 203976 kb
Host smart-4380ea0d-52db-473b-b99c-240a5cea3019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15040
2680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.150402680
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.4025707573
Short name T78
Test name
Test status
Simulation time 8380876443 ps
CPU time 8.69 seconds
Started Apr 23 02:35:18 PM PDT 24
Finished Apr 23 02:35:27 PM PDT 24
Peak memory 203984 kb
Host smart-d51b86aa-38f0-4623-8a0c-19f5c2065789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40257
07573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.4025707573
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.1024715889
Short name T872
Test name
Test status
Simulation time 8401983887 ps
CPU time 8.33 seconds
Started Apr 23 02:35:16 PM PDT 24
Finished Apr 23 02:35:24 PM PDT 24
Peak memory 203988 kb
Host smart-f94c7a03-d3d8-474b-976a-85f19bff8612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10247
15889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.1024715889
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3363442187
Short name T307
Test name
Test status
Simulation time 8389989011 ps
CPU time 7.57 seconds
Started Apr 23 02:35:18 PM PDT 24
Finished Apr 23 02:35:26 PM PDT 24
Peak memory 204012 kb
Host smart-12d91612-d0e1-45be-980b-069534c01d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33634
42187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3363442187
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3192775635
Short name T1107
Test name
Test status
Simulation time 8399038831 ps
CPU time 7.86 seconds
Started Apr 23 02:35:17 PM PDT 24
Finished Apr 23 02:35:26 PM PDT 24
Peak memory 204044 kb
Host smart-46093388-e8f2-41b5-9850-c1b62cf4a461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31927
75635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3192775635
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.2081900834
Short name T464
Test name
Test status
Simulation time 8410392111 ps
CPU time 8.87 seconds
Started Apr 23 02:35:21 PM PDT 24
Finished Apr 23 02:35:31 PM PDT 24
Peak memory 204060 kb
Host smart-f8084a88-47ad-47d4-8624-0c64908284fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20819
00834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.2081900834
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.483811774
Short name T24
Test name
Test status
Simulation time 8370376754 ps
CPU time 8.22 seconds
Started Apr 23 02:35:17 PM PDT 24
Finished Apr 23 02:35:26 PM PDT 24
Peak memory 204056 kb
Host smart-56e20ac6-e61e-40b0-9a7f-1efa55b21ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48381
1774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.483811774
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.4243716888
Short name T982
Test name
Test status
Simulation time 61191326 ps
CPU time 0.67 seconds
Started Apr 23 02:35:21 PM PDT 24
Finished Apr 23 02:35:22 PM PDT 24
Peak memory 203896 kb
Host smart-3451d57c-306e-4d89-951e-8e02de003602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42437
16888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.4243716888
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.2740691247
Short name T248
Test name
Test status
Simulation time 24016486702 ps
CPU time 42.11 seconds
Started Apr 23 02:35:19 PM PDT 24
Finished Apr 23 02:36:01 PM PDT 24
Peak memory 204292 kb
Host smart-8d00ea26-30c4-4ab2-b34d-80d125a6672f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27406
91247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.2740691247
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.4207105166
Short name T1294
Test name
Test status
Simulation time 8419044992 ps
CPU time 7.75 seconds
Started Apr 23 02:35:16 PM PDT 24
Finished Apr 23 02:35:25 PM PDT 24
Peak memory 204044 kb
Host smart-b61eaf44-8e89-4110-be3a-d5e2ec63e9ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42071
05166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.4207105166
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.4270006951
Short name T1277
Test name
Test status
Simulation time 8421897235 ps
CPU time 9.02 seconds
Started Apr 23 02:35:20 PM PDT 24
Finished Apr 23 02:35:30 PM PDT 24
Peak memory 204024 kb
Host smart-4e24ec4f-3ab4-4803-9985-a5b8a2c243a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42700
06951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.4270006951
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.2925528783
Short name T547
Test name
Test status
Simulation time 8410729668 ps
CPU time 7.97 seconds
Started Apr 23 02:35:20 PM PDT 24
Finished Apr 23 02:35:28 PM PDT 24
Peak memory 204016 kb
Host smart-1dc88f43-c01d-471c-9d45-305cea020b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29255
28783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.2925528783
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2943266846
Short name T59
Test name
Test status
Simulation time 332497383 ps
CPU time 1.16 seconds
Started Apr 23 02:35:20 PM PDT 24
Finished Apr 23 02:35:22 PM PDT 24
Peak memory 220144 kb
Host smart-4ad6e217-b55e-4950-8171-e842ed5a0d98
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2943266846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2943266846
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.1145295913
Short name T929
Test name
Test status
Simulation time 8408719804 ps
CPU time 7.78 seconds
Started Apr 23 02:35:20 PM PDT 24
Finished Apr 23 02:35:29 PM PDT 24
Peak memory 203872 kb
Host smart-f8518817-287d-4ee9-8633-20f446d0ca80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11452
95913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.1145295913
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.643771189
Short name T545
Test name
Test status
Simulation time 8365067104 ps
CPU time 7.72 seconds
Started Apr 23 02:35:20 PM PDT 24
Finished Apr 23 02:35:28 PM PDT 24
Peak memory 204008 kb
Host smart-682d0fa8-7ca0-4338-be9f-9e4fde65392b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64377
1189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.643771189
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.2734268980
Short name T1301
Test name
Test status
Simulation time 8425713225 ps
CPU time 10.22 seconds
Started Apr 23 02:35:16 PM PDT 24
Finished Apr 23 02:35:26 PM PDT 24
Peak memory 204024 kb
Host smart-d530cb89-491a-4aa2-bbff-e04fdc2b48df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27342
68980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2734268980
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.1548262235
Short name T337
Test name
Test status
Simulation time 8392242785 ps
CPU time 8.3 seconds
Started Apr 23 02:35:17 PM PDT 24
Finished Apr 23 02:35:26 PM PDT 24
Peak memory 204068 kb
Host smart-ba0e41a3-fc8c-49f8-bb88-4fcbb100e9e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15482
62235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.1548262235
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.2948538593
Short name T592
Test name
Test status
Simulation time 8401664214 ps
CPU time 7.58 seconds
Started Apr 23 02:35:19 PM PDT 24
Finished Apr 23 02:35:27 PM PDT 24
Peak memory 204016 kb
Host smart-4b4049a8-123b-43ba-80e3-69c595628d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29485
38593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.2948538593
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.3108444627
Short name T1298
Test name
Test status
Simulation time 8469007664 ps
CPU time 9.53 seconds
Started Apr 23 02:37:27 PM PDT 24
Finished Apr 23 02:37:37 PM PDT 24
Peak memory 204012 kb
Host smart-47709825-e352-4f06-95f6-aa8bd35aa9b8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3108444627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.3108444627
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.2345897562
Short name T806
Test name
Test status
Simulation time 8379894830 ps
CPU time 8.2 seconds
Started Apr 23 02:37:34 PM PDT 24
Finished Apr 23 02:37:43 PM PDT 24
Peak memory 204040 kb
Host smart-5f2a5c35-8df8-4b9c-87e7-17e45a3d09b4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2345897562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.2345897562
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.2280836534
Short name T542
Test name
Test status
Simulation time 8395117361 ps
CPU time 8.65 seconds
Started Apr 23 02:37:37 PM PDT 24
Finished Apr 23 02:37:47 PM PDT 24
Peak memory 204044 kb
Host smart-ab80c3c7-557c-445e-8a38-e4674f16f02d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22808
36534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.2280836534
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.3493829696
Short name T999
Test name
Test status
Simulation time 8418725234 ps
CPU time 7.75 seconds
Started Apr 23 02:37:23 PM PDT 24
Finished Apr 23 02:37:32 PM PDT 24
Peak memory 204024 kb
Host smart-75e4329c-ab34-4647-9517-e305cedf808a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34938
29696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.3493829696
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_enable.1576625324
Short name T787
Test name
Test status
Simulation time 8384783299 ps
CPU time 8.06 seconds
Started Apr 23 02:37:24 PM PDT 24
Finished Apr 23 02:37:32 PM PDT 24
Peak memory 203984 kb
Host smart-7ff31808-15aa-4018-8e23-916049919567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15766
25324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.1576625324
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.797954836
Short name T425
Test name
Test status
Simulation time 63469285 ps
CPU time 1.7 seconds
Started Apr 23 02:37:24 PM PDT 24
Finished Apr 23 02:37:27 PM PDT 24
Peak memory 204096 kb
Host smart-e5a72f73-324f-4530-8db1-023ab24d0843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79795
4836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.797954836
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.141322229
Short name T1044
Test name
Test status
Simulation time 8388220294 ps
CPU time 7.7 seconds
Started Apr 23 02:37:35 PM PDT 24
Finished Apr 23 02:37:44 PM PDT 24
Peak memory 204052 kb
Host smart-6a951051-efa3-49d6-af90-b0bf560d3123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14132
2229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.141322229
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.2313890078
Short name T1073
Test name
Test status
Simulation time 8364789959 ps
CPU time 9.54 seconds
Started Apr 23 02:37:35 PM PDT 24
Finished Apr 23 02:37:46 PM PDT 24
Peak memory 204060 kb
Host smart-7f2f5173-0902-499e-a905-c37c255a5d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23138
90078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.2313890078
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1151927093
Short name T607
Test name
Test status
Simulation time 8429986389 ps
CPU time 9.54 seconds
Started Apr 23 02:37:24 PM PDT 24
Finished Apr 23 02:37:34 PM PDT 24
Peak memory 204028 kb
Host smart-d2e3d226-6929-4aad-810d-c92140377ced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11519
27093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1151927093
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.1827965001
Short name T1202
Test name
Test status
Simulation time 8417065775 ps
CPU time 7.78 seconds
Started Apr 23 02:37:32 PM PDT 24
Finished Apr 23 02:37:40 PM PDT 24
Peak memory 204060 kb
Host smart-0e113c42-0de2-4252-ba1c-c6f00dd36ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18279
65001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1827965001
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.3460379871
Short name T1076
Test name
Test status
Simulation time 8374164890 ps
CPU time 10.04 seconds
Started Apr 23 02:37:23 PM PDT 24
Finished Apr 23 02:37:33 PM PDT 24
Peak memory 204020 kb
Host smart-a73f323e-1d11-43ae-8fcc-d5b1f3f989af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34603
79871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.3460379871
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3836829938
Short name T963
Test name
Test status
Simulation time 8433914865 ps
CPU time 8.34 seconds
Started Apr 23 02:37:33 PM PDT 24
Finished Apr 23 02:37:42 PM PDT 24
Peak memory 204060 kb
Host smart-05736d5b-0fdc-4517-b706-a39fa099651b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38368
29938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3836829938
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.385170110
Short name T1014
Test name
Test status
Simulation time 8380913583 ps
CPU time 7.98 seconds
Started Apr 23 02:37:31 PM PDT 24
Finished Apr 23 02:37:40 PM PDT 24
Peak memory 204004 kb
Host smart-ddf3f037-58d7-423d-8f0a-8b4517185ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38517
0110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.385170110
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.2926773830
Short name T1333
Test name
Test status
Simulation time 8377386750 ps
CPU time 7.96 seconds
Started Apr 23 02:37:35 PM PDT 24
Finished Apr 23 02:37:45 PM PDT 24
Peak memory 203968 kb
Host smart-890ae26c-3d21-462e-a8a8-e3deeab7c2d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29267
73830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.2926773830
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.4292161666
Short name T1163
Test name
Test status
Simulation time 8386425894 ps
CPU time 9.93 seconds
Started Apr 23 02:37:34 PM PDT 24
Finished Apr 23 02:37:45 PM PDT 24
Peak memory 204036 kb
Host smart-6fffdede-5ac3-4870-9862-d174098d4368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42921
61666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.4292161666
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.47524493
Short name T1064
Test name
Test status
Simulation time 8370413023 ps
CPU time 7.62 seconds
Started Apr 23 02:37:23 PM PDT 24
Finished Apr 23 02:37:32 PM PDT 24
Peak memory 204024 kb
Host smart-8813e968-b69e-4cd2-8f0b-a69826949f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47524
493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.47524493
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1942371556
Short name T750
Test name
Test status
Simulation time 42433536 ps
CPU time 0.64 seconds
Started Apr 23 02:37:40 PM PDT 24
Finished Apr 23 02:37:41 PM PDT 24
Peak memory 203872 kb
Host smart-39036a2f-3063-43d7-bcab-348527dc3aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19423
71556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1942371556
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.1119363884
Short name T90
Test name
Test status
Simulation time 23686704179 ps
CPU time 44.92 seconds
Started Apr 23 02:37:22 PM PDT 24
Finished Apr 23 02:38:08 PM PDT 24
Peak memory 204292 kb
Host smart-fb4fe20c-5b09-4f9a-82b9-3c6110183bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11193
63884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.1119363884
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.3521526047
Short name T1045
Test name
Test status
Simulation time 8409342296 ps
CPU time 8.58 seconds
Started Apr 23 02:37:36 PM PDT 24
Finished Apr 23 02:37:46 PM PDT 24
Peak memory 204012 kb
Host smart-d21a5539-b11d-43d5-b0b1-968f15a603d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35215
26047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.3521526047
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.873967611
Short name T495
Test name
Test status
Simulation time 8378280309 ps
CPU time 8.15 seconds
Started Apr 23 02:37:34 PM PDT 24
Finished Apr 23 02:37:43 PM PDT 24
Peak memory 204032 kb
Host smart-bd5c7580-7b03-4b3f-8d62-6575c4ab68c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87396
7611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.873967611
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.2781733390
Short name T805
Test name
Test status
Simulation time 8377430839 ps
CPU time 10.08 seconds
Started Apr 23 02:37:36 PM PDT 24
Finished Apr 23 02:37:47 PM PDT 24
Peak memory 204056 kb
Host smart-7fbad792-d419-4700-93e1-c6936525aabe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27817
33390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.2781733390
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.4135251171
Short name T951
Test name
Test status
Simulation time 8379450317 ps
CPU time 10.73 seconds
Started Apr 23 02:37:27 PM PDT 24
Finished Apr 23 02:37:38 PM PDT 24
Peak memory 204020 kb
Host smart-9bef1da7-e91c-41d5-9d60-26570ad3f768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41352
51171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.4135251171
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.3016007661
Short name T860
Test name
Test status
Simulation time 8369748302 ps
CPU time 7.73 seconds
Started Apr 23 02:37:24 PM PDT 24
Finished Apr 23 02:37:32 PM PDT 24
Peak memory 204004 kb
Host smart-72a1aa26-0e5e-4489-9f55-11175d8610ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30160
07661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.3016007661
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.2073973457
Short name T959
Test name
Test status
Simulation time 8482937354 ps
CPU time 8.01 seconds
Started Apr 23 02:37:34 PM PDT 24
Finished Apr 23 02:37:43 PM PDT 24
Peak memory 203960 kb
Host smart-18b2a47c-eb9a-4cd9-96a1-5711f2f7acc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20739
73457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2073973457
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.430260663
Short name T1179
Test name
Test status
Simulation time 8387563308 ps
CPU time 10.45 seconds
Started Apr 23 02:37:32 PM PDT 24
Finished Apr 23 02:37:43 PM PDT 24
Peak memory 204056 kb
Host smart-ba0c2814-d41c-4444-834d-a527df1d3ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43026
0663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.430260663
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.192216268
Short name T623
Test name
Test status
Simulation time 8370903314 ps
CPU time 8.75 seconds
Started Apr 23 02:37:26 PM PDT 24
Finished Apr 23 02:37:35 PM PDT 24
Peak memory 203996 kb
Host smart-6b114875-e197-4399-896b-7e3e1e71b190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19221
6268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.192216268
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.2891620464
Short name T822
Test name
Test status
Simulation time 8461475176 ps
CPU time 7.73 seconds
Started Apr 23 02:37:34 PM PDT 24
Finished Apr 23 02:37:43 PM PDT 24
Peak memory 204048 kb
Host smart-44723e5c-e782-40b0-8cb8-5a82eb2b6c12
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2891620464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.2891620464
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.min_length_in_transaction.3610259797
Short name T395
Test name
Test status
Simulation time 8375983619 ps
CPU time 8.2 seconds
Started Apr 23 02:37:36 PM PDT 24
Finished Apr 23 02:37:46 PM PDT 24
Peak memory 204048 kb
Host smart-c1cd267f-5e07-415c-bbc7-58b7fcff7c00
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3610259797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.3610259797
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.2137191852
Short name T1325
Test name
Test status
Simulation time 8450090967 ps
CPU time 7.82 seconds
Started Apr 23 02:37:36 PM PDT 24
Finished Apr 23 02:37:45 PM PDT 24
Peak memory 204044 kb
Host smart-ab2b189d-a0db-47a6-8aa5-cb527a727610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21371
91852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.2137191852
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.4035084598
Short name T997
Test name
Test status
Simulation time 8386877610 ps
CPU time 7.81 seconds
Started Apr 23 02:37:38 PM PDT 24
Finished Apr 23 02:37:47 PM PDT 24
Peak memory 204064 kb
Host smart-0d5413b5-100c-4888-b4d0-943c41baa213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40350
84598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.4035084598
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_enable.209987617
Short name T868
Test name
Test status
Simulation time 8407624737 ps
CPU time 7.9 seconds
Started Apr 23 02:37:33 PM PDT 24
Finished Apr 23 02:37:42 PM PDT 24
Peak memory 204024 kb
Host smart-7ebb03d4-e225-4cae-89e1-9b09572ca36d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20998
7617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.209987617
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.2666707412
Short name T588
Test name
Test status
Simulation time 88386465 ps
CPU time 1.35 seconds
Started Apr 23 02:37:38 PM PDT 24
Finished Apr 23 02:37:40 PM PDT 24
Peak memory 204144 kb
Host smart-df6c64fd-8da0-473e-9c2c-864ed47e79cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26667
07412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.2666707412
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.2118578224
Short name T1176
Test name
Test status
Simulation time 8379198671 ps
CPU time 8.09 seconds
Started Apr 23 02:37:39 PM PDT 24
Finished Apr 23 02:37:48 PM PDT 24
Peak memory 203968 kb
Host smart-d9ddc996-35db-4877-89de-108e87895812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21185
78224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.2118578224
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.2148479153
Short name T810
Test name
Test status
Simulation time 8367899773 ps
CPU time 7.77 seconds
Started Apr 23 02:37:34 PM PDT 24
Finished Apr 23 02:37:43 PM PDT 24
Peak memory 204044 kb
Host smart-adc5e843-ddee-46c2-9ef1-52615b38d1d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21484
79153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.2148479153
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.2412353129
Short name T144
Test name
Test status
Simulation time 8405359638 ps
CPU time 8.02 seconds
Started Apr 23 02:37:34 PM PDT 24
Finished Apr 23 02:37:44 PM PDT 24
Peak memory 204064 kb
Host smart-76aa3830-453c-4dc1-883b-c8da6fdae00f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24123
53129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.2412353129
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.1684331377
Short name T374
Test name
Test status
Simulation time 8410345496 ps
CPU time 7.99 seconds
Started Apr 23 02:37:35 PM PDT 24
Finished Apr 23 02:37:44 PM PDT 24
Peak memory 204028 kb
Host smart-da53906f-cdca-43e6-aad7-b66cd3f47a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16843
31377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.1684331377
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.801508300
Short name T975
Test name
Test status
Simulation time 8376844799 ps
CPU time 7.78 seconds
Started Apr 23 02:37:35 PM PDT 24
Finished Apr 23 02:37:45 PM PDT 24
Peak memory 203968 kb
Host smart-eac2684e-7580-42f1-8ca4-789c0227bb0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80150
8300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.801508300
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.3933171973
Short name T100
Test name
Test status
Simulation time 8399696572 ps
CPU time 8.22 seconds
Started Apr 23 02:37:33 PM PDT 24
Finished Apr 23 02:37:42 PM PDT 24
Peak memory 203960 kb
Host smart-4e5bbf91-77e9-4a26-9fa7-ef7c8f6de373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39331
71973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.3933171973
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.1885600721
Short name T1069
Test name
Test status
Simulation time 8384461035 ps
CPU time 8.26 seconds
Started Apr 23 02:37:27 PM PDT 24
Finished Apr 23 02:37:36 PM PDT 24
Peak memory 203992 kb
Host smart-1aaf7239-7241-4d3c-9961-2037aa99f696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18856
00721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1885600721
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.347017009
Short name T216
Test name
Test status
Simulation time 8399824910 ps
CPU time 8.09 seconds
Started Apr 23 02:37:39 PM PDT 24
Finished Apr 23 02:37:48 PM PDT 24
Peak memory 204028 kb
Host smart-92ad9361-5d6b-4633-bd94-422bebeaa61e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34701
7009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.347017009
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.397816046
Short name T1152
Test name
Test status
Simulation time 8417073609 ps
CPU time 8.23 seconds
Started Apr 23 02:37:34 PM PDT 24
Finished Apr 23 02:37:43 PM PDT 24
Peak memory 204024 kb
Host smart-29d283b7-e361-4fac-825c-e136d27da9ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39781
6046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.397816046
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.2436529670
Short name T22
Test name
Test status
Simulation time 8366398775 ps
CPU time 8.16 seconds
Started Apr 23 02:37:36 PM PDT 24
Finished Apr 23 02:37:45 PM PDT 24
Peak memory 204040 kb
Host smart-d1a8bea0-736b-4bf2-ad40-5fe1647bc3b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24365
29670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.2436529670
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.4021830744
Short name T917
Test name
Test status
Simulation time 52744866 ps
CPU time 0.65 seconds
Started Apr 23 02:37:34 PM PDT 24
Finished Apr 23 02:37:36 PM PDT 24
Peak memory 203904 kb
Host smart-9e39f4cb-8686-4173-b4bf-8d4f28e79080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40218
30744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.4021830744
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.374698193
Short name T1123
Test name
Test status
Simulation time 22037601852 ps
CPU time 39.49 seconds
Started Apr 23 02:37:34 PM PDT 24
Finished Apr 23 02:38:15 PM PDT 24
Peak memory 204332 kb
Host smart-2d611ded-e57e-4e6a-9b4e-9077bfbd6594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37469
8193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.374698193
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.4198507964
Short name T1115
Test name
Test status
Simulation time 8403632244 ps
CPU time 7.78 seconds
Started Apr 23 02:37:33 PM PDT 24
Finished Apr 23 02:37:42 PM PDT 24
Peak memory 204036 kb
Host smart-961298d3-52ea-48a6-bb48-a654b5936f83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41985
07964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.4198507964
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.1960448122
Short name T817
Test name
Test status
Simulation time 8490674635 ps
CPU time 7.75 seconds
Started Apr 23 02:37:34 PM PDT 24
Finished Apr 23 02:37:43 PM PDT 24
Peak memory 204076 kb
Host smart-b9391b7e-223b-4550-9bab-7d5d53225782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19604
48122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1960448122
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.2281120916
Short name T77
Test name
Test status
Simulation time 8476047699 ps
CPU time 7.67 seconds
Started Apr 23 02:37:35 PM PDT 24
Finished Apr 23 02:37:44 PM PDT 24
Peak memory 204060 kb
Host smart-cfc3b310-9303-403d-a8ee-e7c9540b897c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22811
20916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.2281120916
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.1513474075
Short name T166
Test name
Test status
Simulation time 8381094602 ps
CPU time 7.88 seconds
Started Apr 23 02:37:36 PM PDT 24
Finished Apr 23 02:37:45 PM PDT 24
Peak memory 204000 kb
Host smart-e6af902d-6d88-4256-b8a9-d63902af94f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15134
74075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.1513474075
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.1148340113
Short name T584
Test name
Test status
Simulation time 8395553779 ps
CPU time 7.52 seconds
Started Apr 23 02:37:33 PM PDT 24
Finished Apr 23 02:37:42 PM PDT 24
Peak memory 204056 kb
Host smart-3f9c229b-b897-4bdb-ac47-eacf8da50a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11483
40113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.1148340113
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.3679260801
Short name T1302
Test name
Test status
Simulation time 8443413418 ps
CPU time 7.61 seconds
Started Apr 23 02:37:38 PM PDT 24
Finished Apr 23 02:37:46 PM PDT 24
Peak memory 204048 kb
Host smart-0d91972e-6a7c-4424-a3bd-80ae59e00b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36792
60801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.3679260801
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.4213717331
Short name T1193
Test name
Test status
Simulation time 8381947064 ps
CPU time 8.12 seconds
Started Apr 23 02:37:35 PM PDT 24
Finished Apr 23 02:37:44 PM PDT 24
Peak memory 203972 kb
Host smart-afa95773-0bf3-4d1e-b3df-5a43049ccd4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42137
17331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.4213717331
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.2262592195
Short name T765
Test name
Test status
Simulation time 8429201240 ps
CPU time 8.2 seconds
Started Apr 23 02:37:33 PM PDT 24
Finished Apr 23 02:37:43 PM PDT 24
Peak memory 204016 kb
Host smart-b0fe89bd-9641-452c-aadc-007ba86cf989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22625
92195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.2262592195
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.max_length_in_transaction.1575188903
Short name T742
Test name
Test status
Simulation time 8502269966 ps
CPU time 8.55 seconds
Started Apr 23 02:37:39 PM PDT 24
Finished Apr 23 02:37:48 PM PDT 24
Peak memory 204012 kb
Host smart-5870a095-6620-4a06-893c-bd8614fc780e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1575188903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.1575188903
Directory /workspace/32.max_length_in_transaction/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.2073810962
Short name T336
Test name
Test status
Simulation time 8381183639 ps
CPU time 7.71 seconds
Started Apr 23 02:37:43 PM PDT 24
Finished Apr 23 02:37:52 PM PDT 24
Peak memory 204032 kb
Host smart-8d7b4be1-1bbf-408a-a269-5eb218c40d9a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2073810962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.2073810962
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.random_length_in_trans.3818039660
Short name T879
Test name
Test status
Simulation time 8421052363 ps
CPU time 8.86 seconds
Started Apr 23 02:37:41 PM PDT 24
Finished Apr 23 02:37:51 PM PDT 24
Peak memory 204016 kb
Host smart-9feb80d1-63e4-45e6-ba17-d80a4543bec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38180
39660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.3818039660
Directory /workspace/32.random_length_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.4118405681
Short name T985
Test name
Test status
Simulation time 8383254773 ps
CPU time 8.34 seconds
Started Apr 23 02:37:36 PM PDT 24
Finished Apr 23 02:37:46 PM PDT 24
Peak memory 204020 kb
Host smart-c35a27c3-d1b2-4a9e-abcf-91126bf0ffcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41184
05681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.4118405681
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_enable.825804793
Short name T1322
Test name
Test status
Simulation time 8380686124 ps
CPU time 7.65 seconds
Started Apr 23 02:37:34 PM PDT 24
Finished Apr 23 02:37:43 PM PDT 24
Peak memory 204024 kb
Host smart-526bbd52-f46d-46c4-a9c9-bac6884698af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82580
4793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.825804793
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3935671302
Short name T573
Test name
Test status
Simulation time 136738806 ps
CPU time 1.35 seconds
Started Apr 23 02:37:36 PM PDT 24
Finished Apr 23 02:37:39 PM PDT 24
Peak memory 204172 kb
Host smart-e634ff31-7c05-4cb3-b098-d60300781878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39356
71302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3935671302
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.1293883149
Short name T897
Test name
Test status
Simulation time 8389665760 ps
CPU time 9.05 seconds
Started Apr 23 02:37:37 PM PDT 24
Finished Apr 23 02:37:47 PM PDT 24
Peak memory 203992 kb
Host smart-8ab91421-c692-4d96-ba96-3c34db354c7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12938
83149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.1293883149
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.788192860
Short name T776
Test name
Test status
Simulation time 8437599185 ps
CPU time 9.3 seconds
Started Apr 23 02:37:39 PM PDT 24
Finished Apr 23 02:37:49 PM PDT 24
Peak memory 203976 kb
Host smart-db16fdf6-a0c0-420d-8dd8-fc84c3f3d6b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78819
2860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.788192860
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.3515862556
Short name T1203
Test name
Test status
Simulation time 8441778044 ps
CPU time 7.81 seconds
Started Apr 23 02:37:35 PM PDT 24
Finished Apr 23 02:37:44 PM PDT 24
Peak memory 204016 kb
Host smart-2ab159ba-46ae-4e87-a22e-1cf59e17618a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35158
62556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.3515862556
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.3415751929
Short name T1172
Test name
Test status
Simulation time 8409598480 ps
CPU time 8.03 seconds
Started Apr 23 02:37:40 PM PDT 24
Finished Apr 23 02:37:48 PM PDT 24
Peak memory 203976 kb
Host smart-de76136e-d138-48dd-a5e1-57f28b975227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34157
51929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.3415751929
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.2616177471
Short name T427
Test name
Test status
Simulation time 8372171263 ps
CPU time 9.65 seconds
Started Apr 23 02:37:35 PM PDT 24
Finished Apr 23 02:37:47 PM PDT 24
Peak memory 204060 kb
Host smart-59cfffa2-88c7-42a1-ba4d-882815de9bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26161
77471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.2616177471
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.4165651114
Short name T778
Test name
Test status
Simulation time 8433548995 ps
CPU time 7.84 seconds
Started Apr 23 02:37:35 PM PDT 24
Finished Apr 23 02:37:45 PM PDT 24
Peak memory 204024 kb
Host smart-ccfb3a36-75cb-43c8-8542-70aeb5fdcf23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41656
51114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.4165651114
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.3781129202
Short name T356
Test name
Test status
Simulation time 8413495326 ps
CPU time 10.07 seconds
Started Apr 23 02:37:35 PM PDT 24
Finished Apr 23 02:37:47 PM PDT 24
Peak memory 204048 kb
Host smart-6110e6d7-d58d-44bc-a3bd-121e1dcb7b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37811
29202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.3781129202
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.3847341630
Short name T912
Test name
Test status
Simulation time 8412309835 ps
CPU time 8.02 seconds
Started Apr 23 02:37:36 PM PDT 24
Finished Apr 23 02:37:46 PM PDT 24
Peak memory 204032 kb
Host smart-6bd7e086-a2dd-4e12-98b9-d0af593bae7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38473
41630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.3847341630
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.3870028595
Short name T174
Test name
Test status
Simulation time 8371791862 ps
CPU time 7.98 seconds
Started Apr 23 02:37:36 PM PDT 24
Finished Apr 23 02:37:45 PM PDT 24
Peak memory 204024 kb
Host smart-fb4474b8-794b-4176-87cc-f4cb461099a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38700
28595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.3870028595
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.1756130089
Short name T1373
Test name
Test status
Simulation time 8396350091 ps
CPU time 9.79 seconds
Started Apr 23 02:37:39 PM PDT 24
Finished Apr 23 02:37:50 PM PDT 24
Peak memory 203504 kb
Host smart-2d1bcbeb-2b11-4968-885f-d8bd2962f10c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17561
30089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.1756130089
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.1682757952
Short name T475
Test name
Test status
Simulation time 50116147 ps
CPU time 0.69 seconds
Started Apr 23 02:37:37 PM PDT 24
Finished Apr 23 02:37:39 PM PDT 24
Peak memory 203836 kb
Host smart-cbed52da-1818-4ed8-a332-ea7d21016d11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16827
57952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.1682757952
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.3762597835
Short name T1021
Test name
Test status
Simulation time 22901659294 ps
CPU time 46.32 seconds
Started Apr 23 02:37:35 PM PDT 24
Finished Apr 23 02:38:23 PM PDT 24
Peak memory 204276 kb
Host smart-0d5ea52f-ce19-41db-a88c-d3da79405fdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37625
97835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.3762597835
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.4231757906
Short name T1355
Test name
Test status
Simulation time 8391470653 ps
CPU time 8.24 seconds
Started Apr 23 02:37:36 PM PDT 24
Finished Apr 23 02:37:45 PM PDT 24
Peak memory 203992 kb
Host smart-eb5e2db4-580c-4aa1-8c4f-225fb1ecfa60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42317
57906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.4231757906
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3215784044
Short name T153
Test name
Test status
Simulation time 8485619871 ps
CPU time 9.73 seconds
Started Apr 23 02:37:37 PM PDT 24
Finished Apr 23 02:37:47 PM PDT 24
Peak memory 203988 kb
Host smart-8c7b6e45-c537-4ea1-aaaf-3d78a224e5bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32157
84044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3215784044
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.1047291402
Short name T1184
Test name
Test status
Simulation time 8413171570 ps
CPU time 10.31 seconds
Started Apr 23 02:37:37 PM PDT 24
Finished Apr 23 02:37:48 PM PDT 24
Peak memory 203964 kb
Host smart-23ea41da-fd8f-47a2-a3a7-62da9dd5a5d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10472
91402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.1047291402
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.4231198776
Short name T993
Test name
Test status
Simulation time 8421995622 ps
CPU time 7.96 seconds
Started Apr 23 02:37:36 PM PDT 24
Finished Apr 23 02:37:45 PM PDT 24
Peak memory 204056 kb
Host smart-e23bf898-53b8-4f0f-bc03-83264a3922da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42311
98776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.4231198776
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2263352550
Short name T459
Test name
Test status
Simulation time 8377695316 ps
CPU time 8.97 seconds
Started Apr 23 02:37:38 PM PDT 24
Finished Apr 23 02:37:47 PM PDT 24
Peak memory 203988 kb
Host smart-a7a402e2-90d4-4815-9db3-8045b4e3d1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22633
52550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2263352550
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.1338302372
Short name T603
Test name
Test status
Simulation time 8494944386 ps
CPU time 10.36 seconds
Started Apr 23 02:37:35 PM PDT 24
Finished Apr 23 02:37:47 PM PDT 24
Peak memory 204012 kb
Host smart-48fbf9a2-1a5d-4cdb-9d11-23b906871f8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13383
02372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.1338302372
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.521622175
Short name T319
Test name
Test status
Simulation time 8375351469 ps
CPU time 8.36 seconds
Started Apr 23 02:37:39 PM PDT 24
Finished Apr 23 02:37:48 PM PDT 24
Peak memory 202948 kb
Host smart-a2c1e09c-82dc-4b7a-84f3-307f99363ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52162
2175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.521622175
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.1985832577
Short name T1206
Test name
Test status
Simulation time 8405591873 ps
CPU time 8.82 seconds
Started Apr 23 02:37:37 PM PDT 24
Finished Apr 23 02:37:47 PM PDT 24
Peak memory 203988 kb
Host smart-93fb7102-61b9-43e1-82dd-cc58f32f93d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19858
32577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.1985832577
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.2586643614
Short name T600
Test name
Test status
Simulation time 8460238212 ps
CPU time 9.11 seconds
Started Apr 23 02:37:40 PM PDT 24
Finished Apr 23 02:37:50 PM PDT 24
Peak memory 204036 kb
Host smart-682c99d0-5fcf-43dd-9c50-6acbced9d6f3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2586643614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.2586643614
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.147547009
Short name T296
Test name
Test status
Simulation time 8382294731 ps
CPU time 8.18 seconds
Started Apr 23 02:37:41 PM PDT 24
Finished Apr 23 02:37:50 PM PDT 24
Peak memory 204020 kb
Host smart-c5773849-47bb-4f47-adc2-632253f64c24
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=147547009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.147547009
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.1098689093
Short name T719
Test name
Test status
Simulation time 8389806889 ps
CPU time 8.73 seconds
Started Apr 23 02:37:41 PM PDT 24
Finished Apr 23 02:37:51 PM PDT 24
Peak memory 204040 kb
Host smart-2367dfb4-80d4-4ac7-a53d-1780134268b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10986
89093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.1098689093
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.69690196
Short name T838
Test name
Test status
Simulation time 8472572079 ps
CPU time 8.52 seconds
Started Apr 23 02:37:40 PM PDT 24
Finished Apr 23 02:37:49 PM PDT 24
Peak memory 204044 kb
Host smart-d955ff54-4e54-4c60-9708-0afd857f927e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69690
196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.69690196
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_enable.1174774397
Short name T1040
Test name
Test status
Simulation time 8391614560 ps
CPU time 7.94 seconds
Started Apr 23 02:37:42 PM PDT 24
Finished Apr 23 02:37:51 PM PDT 24
Peak memory 204008 kb
Host smart-bef197a5-28ff-4209-9a83-53d501388723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11747
74397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1174774397
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.555053826
Short name T826
Test name
Test status
Simulation time 165116032 ps
CPU time 1.93 seconds
Started Apr 23 02:37:41 PM PDT 24
Finished Apr 23 02:37:44 PM PDT 24
Peak memory 204176 kb
Host smart-33a427ab-c23e-4608-9a85-a8dcd2a9897b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55505
3826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.555053826
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.170771448
Short name T511
Test name
Test status
Simulation time 8443754168 ps
CPU time 7.75 seconds
Started Apr 23 02:37:37 PM PDT 24
Finished Apr 23 02:37:46 PM PDT 24
Peak memory 204016 kb
Host smart-1432baed-a8c1-4e3a-af85-8ae73593bae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17077
1448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.170771448
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2736173207
Short name T203
Test name
Test status
Simulation time 8367914884 ps
CPU time 8.08 seconds
Started Apr 23 02:37:39 PM PDT 24
Finished Apr 23 02:37:47 PM PDT 24
Peak memory 204020 kb
Host smart-4a8503f1-9bac-4a3f-b4a7-515e85562640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27361
73207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2736173207
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.1866224078
Short name T136
Test name
Test status
Simulation time 8426680858 ps
CPU time 9.47 seconds
Started Apr 23 02:37:38 PM PDT 24
Finished Apr 23 02:37:48 PM PDT 24
Peak memory 204012 kb
Host smart-ab21efcf-719f-4465-8594-ecd6782f0899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18662
24078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.1866224078
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.3370187126
Short name T823
Test name
Test status
Simulation time 8420803377 ps
CPU time 8.04 seconds
Started Apr 23 02:37:40 PM PDT 24
Finished Apr 23 02:37:49 PM PDT 24
Peak memory 203980 kb
Host smart-b8b89619-7530-4bd1-8b25-d7e37499cac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33701
87126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3370187126
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.2873398923
Short name T642
Test name
Test status
Simulation time 8378999727 ps
CPU time 7.97 seconds
Started Apr 23 02:37:41 PM PDT 24
Finished Apr 23 02:37:50 PM PDT 24
Peak memory 204020 kb
Host smart-3d8e0b1d-7747-4bfc-9a2d-59f806db9718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28733
98923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.2873398923
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3068806642
Short name T95
Test name
Test status
Simulation time 8417130013 ps
CPU time 9.71 seconds
Started Apr 23 02:37:41 PM PDT 24
Finished Apr 23 02:37:51 PM PDT 24
Peak memory 204024 kb
Host smart-d55f464a-96ae-4a96-aebb-f736fff606b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30688
06642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3068806642
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.1033434604
Short name T804
Test name
Test status
Simulation time 8395964914 ps
CPU time 7.85 seconds
Started Apr 23 02:37:52 PM PDT 24
Finished Apr 23 02:38:02 PM PDT 24
Peak memory 204048 kb
Host smart-dea9b911-85be-498f-a69e-a9100bfef936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10334
34604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.1033434604
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.202218175
Short name T1150
Test name
Test status
Simulation time 8415810243 ps
CPU time 8.13 seconds
Started Apr 23 02:37:39 PM PDT 24
Finished Apr 23 02:37:47 PM PDT 24
Peak memory 204028 kb
Host smart-344291bd-9ac5-4b98-92da-73509c4483bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20221
8175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.202218175
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.4174802028
Short name T548
Test name
Test status
Simulation time 8392117607 ps
CPU time 7.83 seconds
Started Apr 23 02:37:38 PM PDT 24
Finished Apr 23 02:37:46 PM PDT 24
Peak memory 204028 kb
Host smart-8bc98596-b45a-4d8c-aa52-9b2f1420a8b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41748
02028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.4174802028
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.1843330246
Short name T848
Test name
Test status
Simulation time 8363475886 ps
CPU time 8.06 seconds
Started Apr 23 02:37:42 PM PDT 24
Finished Apr 23 02:37:51 PM PDT 24
Peak memory 204052 kb
Host smart-abea26bb-70bc-4611-a2e2-1ff4556f4b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18433
30246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.1843330246
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.2423492523
Short name T1110
Test name
Test status
Simulation time 46814545 ps
CPU time 0.68 seconds
Started Apr 23 02:37:39 PM PDT 24
Finished Apr 23 02:37:41 PM PDT 24
Peak memory 203888 kb
Host smart-57edde0f-5c45-4cd5-a3b2-1e500a90074a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24234
92523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.2423492523
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.3037745397
Short name T220
Test name
Test status
Simulation time 25017792835 ps
CPU time 43.36 seconds
Started Apr 23 02:37:36 PM PDT 24
Finished Apr 23 02:38:21 PM PDT 24
Peak memory 204316 kb
Host smart-1165986b-9316-47d7-b41e-7c9c54730b0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30377
45397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.3037745397
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.706916202
Short name T496
Test name
Test status
Simulation time 8384371091 ps
CPU time 8.46 seconds
Started Apr 23 02:37:39 PM PDT 24
Finished Apr 23 02:37:48 PM PDT 24
Peak memory 204056 kb
Host smart-7086862d-6100-42b7-b071-b1f639b76e0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70691
6202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.706916202
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2274264248
Short name T1159
Test name
Test status
Simulation time 8445507613 ps
CPU time 7.89 seconds
Started Apr 23 02:37:37 PM PDT 24
Finished Apr 23 02:37:46 PM PDT 24
Peak memory 204032 kb
Host smart-f88812a6-9e4b-44e4-aa54-0b06ec1016eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22742
64248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2274264248
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.1724974310
Short name T1331
Test name
Test status
Simulation time 8406231230 ps
CPU time 7.72 seconds
Started Apr 23 02:37:43 PM PDT 24
Finished Apr 23 02:37:52 PM PDT 24
Peak memory 203956 kb
Host smart-abd11baf-581e-4695-90d5-c5f9bc83f835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17249
74310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.1724974310
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.3673775499
Short name T763
Test name
Test status
Simulation time 8377724789 ps
CPU time 8.67 seconds
Started Apr 23 02:37:42 PM PDT 24
Finished Apr 23 02:37:51 PM PDT 24
Peak memory 204040 kb
Host smart-294332b9-01b0-4c09-8dda-cc4339022308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36737
75499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.3673775499
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.381829254
Short name T1038
Test name
Test status
Simulation time 8406424719 ps
CPU time 7.97 seconds
Started Apr 23 02:37:42 PM PDT 24
Finished Apr 23 02:37:51 PM PDT 24
Peak memory 204032 kb
Host smart-19baa2dc-7981-4627-a81b-552148bdae17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38182
9254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.381829254
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2533969444
Short name T913
Test name
Test status
Simulation time 8444696118 ps
CPU time 8.09 seconds
Started Apr 23 02:37:39 PM PDT 24
Finished Apr 23 02:37:48 PM PDT 24
Peak memory 204024 kb
Host smart-37200289-312d-43b5-baeb-faebf2d3f600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25339
69444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2533969444
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.4008841302
Short name T751
Test name
Test status
Simulation time 8404297457 ps
CPU time 8.61 seconds
Started Apr 23 02:37:38 PM PDT 24
Finished Apr 23 02:37:47 PM PDT 24
Peak memory 204016 kb
Host smart-9859a722-cd17-46d3-b526-7ec4c595216d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40088
41302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.4008841302
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.3446628795
Short name T801
Test name
Test status
Simulation time 8387887110 ps
CPU time 8.83 seconds
Started Apr 23 02:37:39 PM PDT 24
Finished Apr 23 02:37:48 PM PDT 24
Peak memory 203980 kb
Host smart-fdf57cb9-8cb6-411d-ae0b-f2e225a05c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34466
28795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.3446628795
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.2194103426
Short name T1365
Test name
Test status
Simulation time 8471101536 ps
CPU time 9.71 seconds
Started Apr 23 02:37:42 PM PDT 24
Finished Apr 23 02:37:53 PM PDT 24
Peak memory 204024 kb
Host smart-c44b5593-64a9-4002-ae7b-f181d8493bd9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2194103426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.2194103426
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.639545114
Short name T1091
Test name
Test status
Simulation time 8383264667 ps
CPU time 9.3 seconds
Started Apr 23 02:37:46 PM PDT 24
Finished Apr 23 02:37:57 PM PDT 24
Peak memory 204048 kb
Host smart-f1080467-dded-47bc-943b-5c25f703aa0a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=639545114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.639545114
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.1945177676
Short name T709
Test name
Test status
Simulation time 8506926363 ps
CPU time 8.18 seconds
Started Apr 23 02:37:45 PM PDT 24
Finished Apr 23 02:37:55 PM PDT 24
Peak memory 203992 kb
Host smart-df714541-389b-4636-96ad-3e1630735bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19451
77676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.1945177676
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.1086479056
Short name T885
Test name
Test status
Simulation time 8376520913 ps
CPU time 9.65 seconds
Started Apr 23 02:37:41 PM PDT 24
Finished Apr 23 02:37:52 PM PDT 24
Peak memory 204064 kb
Host smart-782fe3ad-c088-4e3f-8d06-e1639c834b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10864
79056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.1086479056
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_enable.116753880
Short name T537
Test name
Test status
Simulation time 8396503520 ps
CPU time 9.6 seconds
Started Apr 23 02:37:42 PM PDT 24
Finished Apr 23 02:37:52 PM PDT 24
Peak memory 204016 kb
Host smart-3d29af8c-c0ac-47c7-aba7-4cd9c0700131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11675
3880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.116753880
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.2377639376
Short name T217
Test name
Test status
Simulation time 257818899 ps
CPU time 2.07 seconds
Started Apr 23 02:37:48 PM PDT 24
Finished Apr 23 02:37:52 PM PDT 24
Peak memory 204088 kb
Host smart-036b777d-05cd-4d30-baf2-23c3b3244d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23776
39376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2377639376
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.97695191
Short name T1114
Test name
Test status
Simulation time 8466144055 ps
CPU time 8.32 seconds
Started Apr 23 02:37:57 PM PDT 24
Finished Apr 23 02:38:07 PM PDT 24
Peak memory 204080 kb
Host smart-96cb5690-9596-45b5-88b7-d8fbc66af133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97695
191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.97695191
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.1074842901
Short name T1343
Test name
Test status
Simulation time 8375443417 ps
CPU time 9.13 seconds
Started Apr 23 02:37:47 PM PDT 24
Finished Apr 23 02:37:59 PM PDT 24
Peak memory 204092 kb
Host smart-183b71a3-8a26-415b-b876-caf4205ddd1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10748
42901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.1074842901
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.1662234141
Short name T1093
Test name
Test status
Simulation time 8390535561 ps
CPU time 8.05 seconds
Started Apr 23 02:37:56 PM PDT 24
Finished Apr 23 02:38:06 PM PDT 24
Peak memory 203960 kb
Host smart-ccfdb756-2e0a-4bcd-a346-a74e46eaff6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16622
34141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.1662234141
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.1666716466
Short name T565
Test name
Test status
Simulation time 8420767635 ps
CPU time 9.07 seconds
Started Apr 23 02:37:42 PM PDT 24
Finished Apr 23 02:37:52 PM PDT 24
Peak memory 203988 kb
Host smart-a94e57d8-5b4f-4506-98ec-1b17dfc57124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16667
16466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.1666716466
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.610739679
Short name T345
Test name
Test status
Simulation time 8388112538 ps
CPU time 8.29 seconds
Started Apr 23 02:37:45 PM PDT 24
Finished Apr 23 02:37:55 PM PDT 24
Peak memory 204012 kb
Host smart-39f77a08-c746-4e55-8209-1ba733237291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61073
9679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.610739679
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.2942115053
Short name T413
Test name
Test status
Simulation time 8442057609 ps
CPU time 7.55 seconds
Started Apr 23 02:37:41 PM PDT 24
Finished Apr 23 02:37:50 PM PDT 24
Peak memory 204012 kb
Host smart-2d35a2a8-ec8b-4c3e-befe-36d490a7dadc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29421
15053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2942115053
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.175704065
Short name T1052
Test name
Test status
Simulation time 8406559927 ps
CPU time 8.06 seconds
Started Apr 23 02:37:44 PM PDT 24
Finished Apr 23 02:37:53 PM PDT 24
Peak memory 204060 kb
Host smart-af8f3b39-e8df-4590-8afa-3a73fd5ff441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17570
4065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.175704065
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.2840566222
Short name T1300
Test name
Test status
Simulation time 8384005279 ps
CPU time 8.07 seconds
Started Apr 23 02:37:43 PM PDT 24
Finished Apr 23 02:37:52 PM PDT 24
Peak memory 204024 kb
Host smart-6b1c2d46-303b-4666-8c76-94a5381af740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28405
66222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.2840566222
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.2849845030
Short name T923
Test name
Test status
Simulation time 8421908952 ps
CPU time 8.3 seconds
Started Apr 23 02:37:47 PM PDT 24
Finished Apr 23 02:37:58 PM PDT 24
Peak memory 203992 kb
Host smart-863af7ff-be87-413d-a0d0-0735a71c49f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28498
45030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.2849845030
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.3096355573
Short name T874
Test name
Test status
Simulation time 8363718018 ps
CPU time 7.74 seconds
Started Apr 23 02:37:42 PM PDT 24
Finished Apr 23 02:37:51 PM PDT 24
Peak memory 204028 kb
Host smart-8681a636-d596-4816-97a0-b9aab322b871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30963
55573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.3096355573
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.1657741949
Short name T1060
Test name
Test status
Simulation time 49192151 ps
CPU time 0.68 seconds
Started Apr 23 02:37:51 PM PDT 24
Finished Apr 23 02:37:55 PM PDT 24
Peak memory 203884 kb
Host smart-f70d2ae2-8b25-465f-a5a0-0d62d0228e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16577
41949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.1657741949
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.147364471
Short name T1340
Test name
Test status
Simulation time 29512600547 ps
CPU time 57.94 seconds
Started Apr 23 02:37:54 PM PDT 24
Finished Apr 23 02:38:55 PM PDT 24
Peak memory 204320 kb
Host smart-56600648-6be4-4d41-9ac5-e07760da9b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14736
4471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.147364471
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.4147945123
Short name T350
Test name
Test status
Simulation time 8408384128 ps
CPU time 7.74 seconds
Started Apr 23 02:37:43 PM PDT 24
Finished Apr 23 02:37:51 PM PDT 24
Peak memory 204020 kb
Host smart-2c97a1e0-30e2-4dd5-bc79-c76f0ad4e73d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41479
45123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.4147945123
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.258440616
Short name T1223
Test name
Test status
Simulation time 8451364558 ps
CPU time 7.62 seconds
Started Apr 23 02:37:53 PM PDT 24
Finished Apr 23 02:38:04 PM PDT 24
Peak memory 204060 kb
Host smart-2fc522e3-2917-46d1-9502-c53089ff17b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25844
0616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.258440616
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.2887330452
Short name T1259
Test name
Test status
Simulation time 8402402165 ps
CPU time 8.45 seconds
Started Apr 23 02:37:45 PM PDT 24
Finished Apr 23 02:37:55 PM PDT 24
Peak memory 204024 kb
Host smart-6522cf03-d93b-4bd9-8150-46ae7c67e161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28873
30452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.2887330452
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.3802498130
Short name T1264
Test name
Test status
Simulation time 8368685482 ps
CPU time 8.74 seconds
Started Apr 23 02:37:45 PM PDT 24
Finished Apr 23 02:37:54 PM PDT 24
Peak memory 204024 kb
Host smart-e471c54e-8a55-4ee4-93bc-fb23bc04e693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38024
98130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.3802498130
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1403242451
Short name T28
Test name
Test status
Simulation time 8374533510 ps
CPU time 7.63 seconds
Started Apr 23 02:37:47 PM PDT 24
Finished Apr 23 02:37:57 PM PDT 24
Peak memory 203992 kb
Host smart-c8d52e41-b81c-452a-bac6-e57c0b85ee71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14032
42451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1403242451
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.572794199
Short name T1228
Test name
Test status
Simulation time 8460906481 ps
CPU time 10.26 seconds
Started Apr 23 02:37:50 PM PDT 24
Finished Apr 23 02:38:03 PM PDT 24
Peak memory 204032 kb
Host smart-130a96c6-57cf-4341-ab9b-4d430dd4c70e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57279
4199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.572794199
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.1358810482
Short name T1016
Test name
Test status
Simulation time 8416984293 ps
CPU time 9.23 seconds
Started Apr 23 02:37:48 PM PDT 24
Finished Apr 23 02:37:59 PM PDT 24
Peak memory 203988 kb
Host smart-00ef9d56-b448-4903-b68f-d3c74a94a8e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13588
10482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.1358810482
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.2955025237
Short name T738
Test name
Test status
Simulation time 8427546027 ps
CPU time 7.89 seconds
Started Apr 23 02:37:42 PM PDT 24
Finished Apr 23 02:37:51 PM PDT 24
Peak memory 204016 kb
Host smart-08b8f6cd-91f9-4a4c-9256-779a3dd550e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29550
25237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.2955025237
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.2688131333
Short name T969
Test name
Test status
Simulation time 8468471352 ps
CPU time 8.37 seconds
Started Apr 23 02:37:45 PM PDT 24
Finished Apr 23 02:37:55 PM PDT 24
Peak memory 203948 kb
Host smart-b8cf7cd5-638d-49ad-9bc3-f12fbb310f1c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2688131333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.2688131333
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.2973109690
Short name T744
Test name
Test status
Simulation time 8379273014 ps
CPU time 9.65 seconds
Started Apr 23 02:37:54 PM PDT 24
Finished Apr 23 02:38:06 PM PDT 24
Peak memory 204064 kb
Host smart-dcd073ac-6f38-43e2-8d8d-0f77e890d6de
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2973109690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.2973109690
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.4123691812
Short name T1318
Test name
Test status
Simulation time 8417896200 ps
CPU time 8.14 seconds
Started Apr 23 02:37:46 PM PDT 24
Finished Apr 23 02:37:56 PM PDT 24
Peak memory 204016 kb
Host smart-5e27a4c0-ff38-49c4-9d44-bb4036af6a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41236
91812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.4123691812
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.3552819058
Short name T323
Test name
Test status
Simulation time 8377547596 ps
CPU time 7.74 seconds
Started Apr 23 02:37:46 PM PDT 24
Finished Apr 23 02:37:55 PM PDT 24
Peak memory 203996 kb
Host smart-24ac598c-0383-4bfc-99b3-d3bf7589fa8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35528
19058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.3552819058
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_enable.2322380113
Short name T1238
Test name
Test status
Simulation time 8382391597 ps
CPU time 9.14 seconds
Started Apr 23 02:37:50 PM PDT 24
Finished Apr 23 02:38:02 PM PDT 24
Peak memory 204080 kb
Host smart-17e4a174-3c21-457e-a324-a1a5c9a342fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23223
80113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.2322380113
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.3435793367
Short name T553
Test name
Test status
Simulation time 8462423356 ps
CPU time 7.72 seconds
Started Apr 23 02:37:48 PM PDT 24
Finished Apr 23 02:37:57 PM PDT 24
Peak memory 204096 kb
Host smart-e8fe2b5d-254e-4d30-b60c-ca1114dfd61f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34357
93367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.3435793367
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.1219179307
Short name T699
Test name
Test status
Simulation time 8362301214 ps
CPU time 7.78 seconds
Started Apr 23 02:37:47 PM PDT 24
Finished Apr 23 02:37:57 PM PDT 24
Peak memory 204012 kb
Host smart-5b8578e8-3714-458b-8ac0-5f0661315f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12191
79307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.1219179307
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.1269937382
Short name T18
Test name
Test status
Simulation time 8432543039 ps
CPU time 7.88 seconds
Started Apr 23 02:37:45 PM PDT 24
Finished Apr 23 02:37:55 PM PDT 24
Peak memory 204048 kb
Host smart-fd44fe05-59cf-493c-a86c-bc524e8ba479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12699
37382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.1269937382
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.1733993345
Short name T1131
Test name
Test status
Simulation time 8419803676 ps
CPU time 9.33 seconds
Started Apr 23 02:37:53 PM PDT 24
Finished Apr 23 02:38:05 PM PDT 24
Peak memory 204060 kb
Host smart-850916d0-71c6-4d8a-a3f1-2d43febc98f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17339
93345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.1733993345
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.824689620
Short name T864
Test name
Test status
Simulation time 8383360851 ps
CPU time 8.42 seconds
Started Apr 23 02:37:43 PM PDT 24
Finished Apr 23 02:37:52 PM PDT 24
Peak memory 203956 kb
Host smart-173e058c-0ebb-4ed8-b0c9-e86b4c6a1d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82468
9620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.824689620
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2454750375
Short name T114
Test name
Test status
Simulation time 8426704656 ps
CPU time 9.44 seconds
Started Apr 23 02:37:45 PM PDT 24
Finished Apr 23 02:37:55 PM PDT 24
Peak memory 204020 kb
Host smart-3b8fd2c2-f3cb-4ceb-8e91-eac3384b2c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24547
50375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2454750375
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.960465397
Short name T213
Test name
Test status
Simulation time 8447730349 ps
CPU time 8.4 seconds
Started Apr 23 02:37:46 PM PDT 24
Finished Apr 23 02:37:56 PM PDT 24
Peak memory 204048 kb
Host smart-f7a5b479-eee8-4c83-8c9a-3d18a61121be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96046
5397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.960465397
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.2741558585
Short name T392
Test name
Test status
Simulation time 8394183571 ps
CPU time 8.43 seconds
Started Apr 23 02:37:49 PM PDT 24
Finished Apr 23 02:37:59 PM PDT 24
Peak memory 203996 kb
Host smart-855d7363-7e37-4574-a20f-fef9eb2be0df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27415
58585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.2741558585
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.4248571636
Short name T1210
Test name
Test status
Simulation time 8442967702 ps
CPU time 8.04 seconds
Started Apr 23 02:37:47 PM PDT 24
Finished Apr 23 02:37:57 PM PDT 24
Peak memory 204000 kb
Host smart-1afe30eb-9af0-44d9-9010-85bb546442fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42485
71636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.4248571636
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.456053878
Short name T9
Test name
Test status
Simulation time 8372799177 ps
CPU time 7.76 seconds
Started Apr 23 02:37:47 PM PDT 24
Finished Apr 23 02:37:57 PM PDT 24
Peak memory 204004 kb
Host smart-cd669475-7724-4532-ac3c-eafa9e8f27ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45605
3878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.456053878
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.3349879544
Short name T1160
Test name
Test status
Simulation time 71019156 ps
CPU time 0.72 seconds
Started Apr 23 02:37:48 PM PDT 24
Finished Apr 23 02:37:51 PM PDT 24
Peak memory 203852 kb
Host smart-421abcdf-5e86-47e2-b28f-38bf4f39a717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33498
79544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.3349879544
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.601333041
Short name T825
Test name
Test status
Simulation time 28739170298 ps
CPU time 61.7 seconds
Started Apr 23 02:37:50 PM PDT 24
Finished Apr 23 02:38:54 PM PDT 24
Peak memory 204316 kb
Host smart-dc713820-8f7a-47d3-b317-4b197b098b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60133
3041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.601333041
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.2207010270
Short name T653
Test name
Test status
Simulation time 8391658021 ps
CPU time 7.6 seconds
Started Apr 23 02:37:46 PM PDT 24
Finished Apr 23 02:37:56 PM PDT 24
Peak memory 203996 kb
Host smart-bfcbc0de-babd-47c1-a2d2-f8127c96df63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22070
10270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.2207010270
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.1464810317
Short name T156
Test name
Test status
Simulation time 8392631662 ps
CPU time 8.49 seconds
Started Apr 23 02:37:51 PM PDT 24
Finished Apr 23 02:38:02 PM PDT 24
Peak memory 204040 kb
Host smart-6316d4ea-17a6-44bc-b1a0-63eb72dedc08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14648
10317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.1464810317
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.2733884125
Short name T882
Test name
Test status
Simulation time 8384265666 ps
CPU time 7.79 seconds
Started Apr 23 02:37:53 PM PDT 24
Finished Apr 23 02:38:04 PM PDT 24
Peak memory 203968 kb
Host smart-fb4de55e-bccc-4498-b948-54d63e7c8d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27338
84125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.2733884125
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.1863392
Short name T452
Test name
Test status
Simulation time 8376261037 ps
CPU time 8.39 seconds
Started Apr 23 02:37:45 PM PDT 24
Finished Apr 23 02:37:55 PM PDT 24
Peak memory 204004 kb
Host smart-69d26f5d-b7f2-42e3-b618-2f8399f9dddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18633
92 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.1863392
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.3923508982
Short name T363
Test name
Test status
Simulation time 8374950489 ps
CPU time 9.04 seconds
Started Apr 23 02:37:48 PM PDT 24
Finished Apr 23 02:37:59 PM PDT 24
Peak memory 204016 kb
Host smart-b5bebfd2-40c2-4705-b5c8-82c54e8e978a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39235
08982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3923508982
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.626244678
Short name T733
Test name
Test status
Simulation time 8423892207 ps
CPU time 8.67 seconds
Started Apr 23 02:37:53 PM PDT 24
Finished Apr 23 02:38:04 PM PDT 24
Peak memory 204064 kb
Host smart-3ac38b9a-9aa1-4aa1-981d-e1a7a0902cac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62624
4678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.626244678
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.2140379368
Short name T579
Test name
Test status
Simulation time 8397582805 ps
CPU time 7.95 seconds
Started Apr 23 02:37:51 PM PDT 24
Finished Apr 23 02:38:01 PM PDT 24
Peak memory 204032 kb
Host smart-59ba1e1f-da42-468f-9273-4d26eab15ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21403
79368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.2140379368
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.1309987243
Short name T492
Test name
Test status
Simulation time 8381657468 ps
CPU time 7.79 seconds
Started Apr 23 02:37:49 PM PDT 24
Finished Apr 23 02:37:58 PM PDT 24
Peak memory 204092 kb
Host smart-bd47517a-cb4e-4f06-999f-a07ec506280b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13099
87243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.1309987243
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.4182445138
Short name T594
Test name
Test status
Simulation time 8474664162 ps
CPU time 8.24 seconds
Started Apr 23 02:37:51 PM PDT 24
Finished Apr 23 02:38:02 PM PDT 24
Peak memory 204016 kb
Host smart-496dd313-84dd-4e6c-9987-a7a91ab4179c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4182445138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.4182445138
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.3251467402
Short name T893
Test name
Test status
Simulation time 8385126235 ps
CPU time 7.85 seconds
Started Apr 23 02:37:50 PM PDT 24
Finished Apr 23 02:38:00 PM PDT 24
Peak memory 204012 kb
Host smart-80d9effb-817f-496f-b8f7-3df2260c9fd5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3251467402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.3251467402
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.3180153191
Short name T636
Test name
Test status
Simulation time 8385095688 ps
CPU time 7.7 seconds
Started Apr 23 02:37:56 PM PDT 24
Finished Apr 23 02:38:06 PM PDT 24
Peak memory 204044 kb
Host smart-a7e35d69-0874-4948-afa5-50d6e414b782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31801
53191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.3180153191
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.739043603
Short name T883
Test name
Test status
Simulation time 8376102641 ps
CPU time 9.24 seconds
Started Apr 23 02:37:57 PM PDT 24
Finished Apr 23 02:38:08 PM PDT 24
Peak memory 204012 kb
Host smart-f745a91c-73cb-4de4-a87b-71a248d60d1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73904
3603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.739043603
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_enable.3045735449
Short name T970
Test name
Test status
Simulation time 8374523769 ps
CPU time 7.84 seconds
Started Apr 23 02:37:50 PM PDT 24
Finished Apr 23 02:38:00 PM PDT 24
Peak memory 204032 kb
Host smart-40c8053f-8ca0-45c4-a9d8-b6981d520ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30457
35449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.3045735449
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1964471141
Short name T1312
Test name
Test status
Simulation time 222242155 ps
CPU time 2.05 seconds
Started Apr 23 02:37:50 PM PDT 24
Finished Apr 23 02:37:54 PM PDT 24
Peak memory 204108 kb
Host smart-3667a37e-dcc4-4e4c-b9f1-d470f1568bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19644
71141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1964471141
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.3862201611
Short name T654
Test name
Test status
Simulation time 8460182009 ps
CPU time 7.84 seconds
Started Apr 23 02:37:54 PM PDT 24
Finished Apr 23 02:38:05 PM PDT 24
Peak memory 203976 kb
Host smart-49a22c37-38a3-4a55-9bd6-2f4747e0d978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38622
01611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.3862201611
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.720203483
Short name T188
Test name
Test status
Simulation time 8369416352 ps
CPU time 8.15 seconds
Started Apr 23 02:37:55 PM PDT 24
Finished Apr 23 02:38:06 PM PDT 24
Peak memory 204044 kb
Host smart-00a9852b-0883-499a-adb5-5d02d3174281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72020
3483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.720203483
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.3417879570
Short name T159
Test name
Test status
Simulation time 8445511262 ps
CPU time 8.02 seconds
Started Apr 23 02:37:47 PM PDT 24
Finished Apr 23 02:37:57 PM PDT 24
Peak memory 204024 kb
Host smart-dd423a15-321e-4d2b-a288-4fed072011e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34178
79570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.3417879570
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.3460194595
Short name T1181
Test name
Test status
Simulation time 8420329059 ps
CPU time 8.14 seconds
Started Apr 23 02:37:56 PM PDT 24
Finished Apr 23 02:38:06 PM PDT 24
Peak memory 204016 kb
Host smart-a4c372cd-bf36-4240-92de-534de16311c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34601
94595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.3460194595
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.1895929985
Short name T338
Test name
Test status
Simulation time 8369560747 ps
CPU time 8.07 seconds
Started Apr 23 02:37:56 PM PDT 24
Finished Apr 23 02:38:06 PM PDT 24
Peak memory 204048 kb
Host smart-39489deb-c7bd-41c4-ac9c-36c2b6f28838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18959
29985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.1895929985
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.2064387774
Short name T96
Test name
Test status
Simulation time 8415439853 ps
CPU time 8.43 seconds
Started Apr 23 02:37:56 PM PDT 24
Finished Apr 23 02:38:07 PM PDT 24
Peak memory 204064 kb
Host smart-a13da61a-0198-4337-8de0-40a78eff1544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20643
87774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.2064387774
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.4190023510
Short name T1078
Test name
Test status
Simulation time 8400645694 ps
CPU time 7.78 seconds
Started Apr 23 02:37:56 PM PDT 24
Finished Apr 23 02:38:06 PM PDT 24
Peak memory 204016 kb
Host smart-2459e556-a884-40ee-a976-c5cebe236577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41900
23510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.4190023510
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1881950855
Short name T381
Test name
Test status
Simulation time 8407925944 ps
CPU time 7.78 seconds
Started Apr 23 02:37:52 PM PDT 24
Finished Apr 23 02:38:02 PM PDT 24
Peak memory 203988 kb
Host smart-ed19e883-e563-4fe1-ac00-ca731c33a26f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18819
50855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1881950855
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.1552108374
Short name T184
Test name
Test status
Simulation time 8417232873 ps
CPU time 8.25 seconds
Started Apr 23 02:37:54 PM PDT 24
Finished Apr 23 02:38:05 PM PDT 24
Peak memory 204028 kb
Host smart-e7d4dc44-9ae9-42cf-b030-337f89282388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15521
08374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.1552108374
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.3201933752
Short name T961
Test name
Test status
Simulation time 8373412648 ps
CPU time 8.33 seconds
Started Apr 23 02:37:50 PM PDT 24
Finished Apr 23 02:38:01 PM PDT 24
Peak memory 204020 kb
Host smart-967fc934-f04f-4dd7-8a63-03e4bcdd1c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32019
33752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.3201933752
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.44043501
Short name T940
Test name
Test status
Simulation time 40929594 ps
CPU time 0.74 seconds
Started Apr 23 02:37:52 PM PDT 24
Finished Apr 23 02:37:55 PM PDT 24
Peak memory 203876 kb
Host smart-dcc6ac19-7e49-4c08-bb99-870fca095d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44043
501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.44043501
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3613603391
Short name T88
Test name
Test status
Simulation time 22719422681 ps
CPU time 42.01 seconds
Started Apr 23 02:37:58 PM PDT 24
Finished Apr 23 02:38:41 PM PDT 24
Peak memory 204316 kb
Host smart-408f81f9-7509-4c99-a646-ccc0d47f4cd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36136
03391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3613603391
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.773530048
Short name T473
Test name
Test status
Simulation time 8429151617 ps
CPU time 7.51 seconds
Started Apr 23 02:37:48 PM PDT 24
Finished Apr 23 02:37:58 PM PDT 24
Peak memory 203948 kb
Host smart-21bb9921-759d-4475-ad82-f97919b2a537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77353
0048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.773530048
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.1820880944
Short name T1165
Test name
Test status
Simulation time 8416324425 ps
CPU time 8.12 seconds
Started Apr 23 02:37:53 PM PDT 24
Finished Apr 23 02:38:04 PM PDT 24
Peak memory 204008 kb
Host smart-699dc881-f0db-47be-94fb-177e12ac53c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18208
80944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1820880944
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.3095930871
Short name T749
Test name
Test status
Simulation time 8438410260 ps
CPU time 8.7 seconds
Started Apr 23 02:37:49 PM PDT 24
Finished Apr 23 02:37:59 PM PDT 24
Peak memory 203964 kb
Host smart-0d081d7d-c541-4f6c-8533-c22e662207af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30959
30871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.3095930871
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.1190510854
Short name T1200
Test name
Test status
Simulation time 8380748147 ps
CPU time 8.32 seconds
Started Apr 23 02:37:53 PM PDT 24
Finished Apr 23 02:38:04 PM PDT 24
Peak memory 203980 kb
Host smart-6f250b43-31c8-4d7e-95a9-4618681215b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11905
10854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.1190510854
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.3244136953
Short name T27
Test name
Test status
Simulation time 8373892008 ps
CPU time 7.58 seconds
Started Apr 23 02:37:50 PM PDT 24
Finished Apr 23 02:38:00 PM PDT 24
Peak memory 203952 kb
Host smart-013f6a8a-a617-4cdc-a260-7f4645e39fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32441
36953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.3244136953
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.2836964636
Short name T942
Test name
Test status
Simulation time 8436232984 ps
CPU time 8.02 seconds
Started Apr 23 02:37:56 PM PDT 24
Finished Apr 23 02:38:06 PM PDT 24
Peak memory 204020 kb
Host smart-538cf791-bc16-4f81-a5d3-de62cebf49a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28369
64636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2836964636
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.2477620513
Short name T880
Test name
Test status
Simulation time 8430660360 ps
CPU time 7.93 seconds
Started Apr 23 02:37:58 PM PDT 24
Finished Apr 23 02:38:07 PM PDT 24
Peak memory 204004 kb
Host smart-f70f4187-81e0-47ce-a0ba-e52ec306a765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24776
20513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.2477620513
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.3384983698
Short name T420
Test name
Test status
Simulation time 8383898566 ps
CPU time 8.47 seconds
Started Apr 23 02:37:51 PM PDT 24
Finished Apr 23 02:38:02 PM PDT 24
Peak memory 204016 kb
Host smart-c7a5ec60-bf2b-43c4-a42b-a145eff38f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33849
83698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.3384983698
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.1432714919
Short name T355
Test name
Test status
Simulation time 8463105254 ps
CPU time 10.33 seconds
Started Apr 23 02:37:56 PM PDT 24
Finished Apr 23 02:38:08 PM PDT 24
Peak memory 203976 kb
Host smart-4bc454c2-245f-47dc-baf1-f0daa8286aac
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1432714919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.1432714919
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.3153379791
Short name T521
Test name
Test status
Simulation time 8379051044 ps
CPU time 10.23 seconds
Started Apr 23 02:38:07 PM PDT 24
Finished Apr 23 02:38:18 PM PDT 24
Peak memory 204008 kb
Host smart-8ef6cfa5-88ac-48fd-9a5a-524fae830a25
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3153379791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.3153379791
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.random_length_in_trans.1665663590
Short name T1231
Test name
Test status
Simulation time 8444966663 ps
CPU time 7.81 seconds
Started Apr 23 02:37:59 PM PDT 24
Finished Apr 23 02:38:07 PM PDT 24
Peak memory 204024 kb
Host smart-2bdd3d84-4a2b-455c-b111-7c0d1846e849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16656
63590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.1665663590
Directory /workspace/37.random_length_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.1319778276
Short name T980
Test name
Test status
Simulation time 8402632338 ps
CPU time 9.28 seconds
Started Apr 23 02:37:54 PM PDT 24
Finished Apr 23 02:38:06 PM PDT 24
Peak memory 204024 kb
Host smart-e173faaa-d61c-4ea7-af0e-da18a32f5794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13197
78276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.1319778276
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_enable.724482371
Short name T1079
Test name
Test status
Simulation time 8378055338 ps
CPU time 7.73 seconds
Started Apr 23 02:37:54 PM PDT 24
Finished Apr 23 02:38:04 PM PDT 24
Peak memory 203988 kb
Host smart-b008e9b4-a299-476d-9461-65e9e040a0e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72448
2371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.724482371
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2326110904
Short name T517
Test name
Test status
Simulation time 109054438 ps
CPU time 1.32 seconds
Started Apr 23 02:37:53 PM PDT 24
Finished Apr 23 02:37:57 PM PDT 24
Peak memory 204128 kb
Host smart-2a136c94-37a1-4086-b09d-78ecc413468d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23261
10904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2326110904
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.420890579
Short name T664
Test name
Test status
Simulation time 8493034401 ps
CPU time 8.27 seconds
Started Apr 23 02:37:57 PM PDT 24
Finished Apr 23 02:38:07 PM PDT 24
Peak memory 203960 kb
Host smart-11e8a937-1c12-4f73-99e6-c08a875a67e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42089
0579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.420890579
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.1939351945
Short name T4
Test name
Test status
Simulation time 8363450764 ps
CPU time 8.32 seconds
Started Apr 23 02:37:57 PM PDT 24
Finished Apr 23 02:38:07 PM PDT 24
Peak memory 204024 kb
Host smart-add0b085-38ab-4b47-8db5-e07806b3ec4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19393
51945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.1939351945
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.928089118
Short name T441
Test name
Test status
Simulation time 8447300195 ps
CPU time 9.94 seconds
Started Apr 23 02:37:55 PM PDT 24
Finished Apr 23 02:38:08 PM PDT 24
Peak memory 204036 kb
Host smart-b55d271f-df53-49f0-824d-31b541d161d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92808
9118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.928089118
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.3899009116
Short name T812
Test name
Test status
Simulation time 8422633529 ps
CPU time 9.07 seconds
Started Apr 23 02:37:56 PM PDT 24
Finished Apr 23 02:38:07 PM PDT 24
Peak memory 204028 kb
Host smart-6b8d7512-87dd-47aa-adb7-983e7e61f533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38990
09116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.3899009116
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.548863914
Short name T886
Test name
Test status
Simulation time 8370698765 ps
CPU time 10.11 seconds
Started Apr 23 02:37:59 PM PDT 24
Finished Apr 23 02:38:10 PM PDT 24
Peak memory 203976 kb
Host smart-220baf59-a190-4f5f-bf8e-78d28544fa27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54886
3914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.548863914
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.1149379395
Short name T120
Test name
Test status
Simulation time 8403783513 ps
CPU time 9.83 seconds
Started Apr 23 02:37:59 PM PDT 24
Finished Apr 23 02:38:10 PM PDT 24
Peak memory 204016 kb
Host smart-5a337c05-568d-4ce4-9739-8445cf310bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11493
79395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.1149379395
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.4210943248
Short name T1242
Test name
Test status
Simulation time 8393453992 ps
CPU time 9.71 seconds
Started Apr 23 02:37:54 PM PDT 24
Finished Apr 23 02:38:07 PM PDT 24
Peak memory 204064 kb
Host smart-e45f859a-6dea-4fb8-b54d-edafac887e1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42109
43248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.4210943248
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.518006233
Short name T290
Test name
Test status
Simulation time 8388069255 ps
CPU time 7.46 seconds
Started Apr 23 02:37:54 PM PDT 24
Finished Apr 23 02:38:04 PM PDT 24
Peak memory 203988 kb
Host smart-5f94ba9a-f537-4d56-9e41-f2944e880702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51800
6233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.518006233
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.1238597704
Short name T1149
Test name
Test status
Simulation time 8423021504 ps
CPU time 8.9 seconds
Started Apr 23 02:37:55 PM PDT 24
Finished Apr 23 02:38:06 PM PDT 24
Peak memory 204060 kb
Host smart-bcfd3d44-7948-4405-a65c-bbf3b3208c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12385
97704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.1238597704
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3871263148
Short name T8
Test name
Test status
Simulation time 8366987733 ps
CPU time 7.66 seconds
Started Apr 23 02:37:59 PM PDT 24
Finished Apr 23 02:38:08 PM PDT 24
Peak memory 204012 kb
Host smart-bb7b2ec0-7579-480c-be89-93c29c773c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38712
63148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.3871263148
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.3388836697
Short name T902
Test name
Test status
Simulation time 92575407 ps
CPU time 0.67 seconds
Started Apr 23 02:37:56 PM PDT 24
Finished Apr 23 02:37:59 PM PDT 24
Peak memory 203904 kb
Host smart-d0207773-205b-4721-8731-fbc684be23de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33888
36697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.3388836697
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.2215058756
Short name T310
Test name
Test status
Simulation time 8396509855 ps
CPU time 8.98 seconds
Started Apr 23 02:37:53 PM PDT 24
Finished Apr 23 02:38:05 PM PDT 24
Peak memory 204012 kb
Host smart-c939c33a-f84c-4b13-acd6-87096e354a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22150
58756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2215058756
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.2078391432
Short name T643
Test name
Test status
Simulation time 8433728339 ps
CPU time 10.16 seconds
Started Apr 23 02:37:54 PM PDT 24
Finished Apr 23 02:38:07 PM PDT 24
Peak memory 204064 kb
Host smart-05229b21-bb67-4a38-8e23-6a05b83e3d55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20783
91432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.2078391432
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.2409094632
Short name T875
Test name
Test status
Simulation time 8400627273 ps
CPU time 7.72 seconds
Started Apr 23 02:37:53 PM PDT 24
Finished Apr 23 02:38:04 PM PDT 24
Peak memory 203980 kb
Host smart-158ba421-fba8-462f-b969-e9efa2508a89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24090
94632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.2409094632
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.573296195
Short name T596
Test name
Test status
Simulation time 8449457453 ps
CPU time 7.89 seconds
Started Apr 23 02:38:00 PM PDT 24
Finished Apr 23 02:38:09 PM PDT 24
Peak memory 204000 kb
Host smart-057a4ec3-91ee-4c5b-b44a-90dc9429116e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57329
6195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.573296195
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.973490364
Short name T569
Test name
Test status
Simulation time 8373065508 ps
CPU time 7.92 seconds
Started Apr 23 02:37:55 PM PDT 24
Finished Apr 23 02:38:05 PM PDT 24
Peak memory 204020 kb
Host smart-7431139a-17bb-4aad-a51f-d8b73b45c227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97349
0364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.973490364
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.2912196050
Short name T604
Test name
Test status
Simulation time 8415387868 ps
CPU time 8.22 seconds
Started Apr 23 02:37:50 PM PDT 24
Finished Apr 23 02:38:01 PM PDT 24
Peak memory 204016 kb
Host smart-8be5e503-0014-481e-9ffb-8558d177a645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29121
96050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.2912196050
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.2707718905
Short name T1019
Test name
Test status
Simulation time 8398964754 ps
CPU time 7.9 seconds
Started Apr 23 02:38:00 PM PDT 24
Finished Apr 23 02:38:09 PM PDT 24
Peak memory 203984 kb
Host smart-8a6834ec-bbce-4921-8223-764b3f7e2c73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27077
18905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.2707718905
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.1453637688
Short name T862
Test name
Test status
Simulation time 8401508988 ps
CPU time 7.94 seconds
Started Apr 23 02:37:53 PM PDT 24
Finished Apr 23 02:38:04 PM PDT 24
Peak memory 203980 kb
Host smart-7fd26614-6e24-4ef7-b8e5-ba7cda5abb4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14536
37688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.1453637688
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.3566622967
Short name T1065
Test name
Test status
Simulation time 8467117759 ps
CPU time 8.52 seconds
Started Apr 23 02:38:00 PM PDT 24
Finished Apr 23 02:38:09 PM PDT 24
Peak memory 204028 kb
Host smart-ed12d1a1-5e51-47f9-b35c-2483722d8729
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3566622967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.3566622967
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.4150811323
Short name T839
Test name
Test status
Simulation time 8381923017 ps
CPU time 8.11 seconds
Started Apr 23 02:38:00 PM PDT 24
Finished Apr 23 02:38:09 PM PDT 24
Peak memory 203996 kb
Host smart-a385bfb0-f29f-4f89-9035-77edaecb7e83
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4150811323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.4150811323
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.495987806
Short name T393
Test name
Test status
Simulation time 8402071057 ps
CPU time 8.07 seconds
Started Apr 23 02:38:00 PM PDT 24
Finished Apr 23 02:38:09 PM PDT 24
Peak memory 204056 kb
Host smart-7b9d1fb4-423b-4c8a-9322-6536f063aeaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49598
7806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.495987806
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.1924590958
Short name T327
Test name
Test status
Simulation time 8421738950 ps
CPU time 10.04 seconds
Started Apr 23 02:37:58 PM PDT 24
Finished Apr 23 02:38:10 PM PDT 24
Peak memory 203968 kb
Host smart-a9398bfa-7b4d-411a-bdbd-f8e2559cafc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19245
90958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.1924590958
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_enable.2517739105
Short name T301
Test name
Test status
Simulation time 8399725079 ps
CPU time 7.8 seconds
Started Apr 23 02:37:57 PM PDT 24
Finished Apr 23 02:38:07 PM PDT 24
Peak memory 204060 kb
Host smart-942c377f-f76d-4b38-a450-3bfc9883f8cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25177
39105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.2517739105
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.3756265822
Short name T944
Test name
Test status
Simulation time 209957003 ps
CPU time 2.09 seconds
Started Apr 23 02:38:05 PM PDT 24
Finished Apr 23 02:38:08 PM PDT 24
Peak memory 204156 kb
Host smart-5bacaf5b-53c5-4622-ae3d-8eaaf664b019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37562
65822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.3756265822
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2519087686
Short name T655
Test name
Test status
Simulation time 8462520220 ps
CPU time 8.56 seconds
Started Apr 23 02:38:04 PM PDT 24
Finished Apr 23 02:38:14 PM PDT 24
Peak memory 203996 kb
Host smart-e7f6b296-5922-4481-8743-c5a8fcc466a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25190
87686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2519087686
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.3317716754
Short name T676
Test name
Test status
Simulation time 8365040113 ps
CPU time 7.55 seconds
Started Apr 23 02:38:03 PM PDT 24
Finished Apr 23 02:38:11 PM PDT 24
Peak memory 204060 kb
Host smart-8383529c-d773-4eab-9b57-c8620cbfd75d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33177
16754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.3317716754
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.3861374768
Short name T390
Test name
Test status
Simulation time 8451966999 ps
CPU time 8.36 seconds
Started Apr 23 02:38:02 PM PDT 24
Finished Apr 23 02:38:10 PM PDT 24
Peak memory 204016 kb
Host smart-81de1ce0-6fa3-48cd-9d81-a5f43a532059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38613
74768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.3861374768
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.4146021254
Short name T927
Test name
Test status
Simulation time 8420817878 ps
CPU time 8.2 seconds
Started Apr 23 02:38:06 PM PDT 24
Finished Apr 23 02:38:15 PM PDT 24
Peak memory 204016 kb
Host smart-534835ff-337d-4731-a00a-536a5a84e538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41460
21254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.4146021254
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3886322964
Short name T1097
Test name
Test status
Simulation time 8393544421 ps
CPU time 7.61 seconds
Started Apr 23 02:38:01 PM PDT 24
Finished Apr 23 02:38:09 PM PDT 24
Peak memory 204028 kb
Host smart-4db413c1-cf56-471f-8b84-a630f6350e35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38863
22964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3886322964
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.1971715162
Short name T117
Test name
Test status
Simulation time 8435830227 ps
CPU time 9.03 seconds
Started Apr 23 02:38:01 PM PDT 24
Finished Apr 23 02:38:11 PM PDT 24
Peak memory 204024 kb
Host smart-71faa0ac-e800-4d30-bb7b-476494a99092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19717
15162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.1971715162
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2105367795
Short name T1286
Test name
Test status
Simulation time 8427053883 ps
CPU time 10 seconds
Started Apr 23 02:38:02 PM PDT 24
Finished Apr 23 02:38:13 PM PDT 24
Peak memory 204020 kb
Host smart-f6751071-33d3-48e4-af96-5ccdbae844b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21053
67795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2105367795
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.1426767512
Short name T408
Test name
Test status
Simulation time 8388367853 ps
CPU time 8.59 seconds
Started Apr 23 02:37:59 PM PDT 24
Finished Apr 23 02:38:09 PM PDT 24
Peak memory 204028 kb
Host smart-0e052f88-23ea-48ec-a7f5-18ec5e2a5cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14267
67512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.1426767512
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.358691524
Short name T583
Test name
Test status
Simulation time 8380687704 ps
CPU time 7.99 seconds
Started Apr 23 02:38:10 PM PDT 24
Finished Apr 23 02:38:19 PM PDT 24
Peak memory 203992 kb
Host smart-ba14f4be-c1e2-4952-a64a-189232140b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35869
1524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.358691524
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.3032921757
Short name T1188
Test name
Test status
Simulation time 8377122636 ps
CPU time 8.1 seconds
Started Apr 23 02:38:03 PM PDT 24
Finished Apr 23 02:38:12 PM PDT 24
Peak memory 203996 kb
Host smart-0c1f7bea-2a90-4f2c-b2a4-91e9d5dd8305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30329
21757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.3032921757
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.573745252
Short name T637
Test name
Test status
Simulation time 46904147 ps
CPU time 0.68 seconds
Started Apr 23 02:38:00 PM PDT 24
Finished Apr 23 02:38:02 PM PDT 24
Peak memory 203892 kb
Host smart-392b6edd-e42b-46fd-bc15-b30a618afda7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57374
5252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.573745252
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1270094201
Short name T14
Test name
Test status
Simulation time 27425931156 ps
CPU time 53.83 seconds
Started Apr 23 02:38:03 PM PDT 24
Finished Apr 23 02:38:57 PM PDT 24
Peak memory 204332 kb
Host smart-785c3729-af7e-4937-b3d6-d6f5b696a9ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12700
94201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1270094201
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.4036731156
Short name T372
Test name
Test status
Simulation time 8384063746 ps
CPU time 7.56 seconds
Started Apr 23 02:37:59 PM PDT 24
Finished Apr 23 02:38:08 PM PDT 24
Peak memory 204008 kb
Host smart-2ff887d4-832b-4781-9155-094a23cd549c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40367
31156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.4036731156
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.3135412733
Short name T538
Test name
Test status
Simulation time 8411156044 ps
CPU time 9.24 seconds
Started Apr 23 02:38:08 PM PDT 24
Finished Apr 23 02:38:19 PM PDT 24
Peak memory 204048 kb
Host smart-9297efb6-8d11-4826-934b-0d0b077325a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31354
12733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.3135412733
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.2779818109
Short name T640
Test name
Test status
Simulation time 8408724857 ps
CPU time 9.82 seconds
Started Apr 23 02:38:09 PM PDT 24
Finished Apr 23 02:38:20 PM PDT 24
Peak memory 204028 kb
Host smart-56c38adf-ebb3-43cf-b6fb-b783a140f75e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27798
18109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.2779818109
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.4115627879
Short name T1290
Test name
Test status
Simulation time 8388552651 ps
CPU time 10.19 seconds
Started Apr 23 02:38:02 PM PDT 24
Finished Apr 23 02:38:13 PM PDT 24
Peak memory 204092 kb
Host smart-00189261-f096-476a-ba56-432fa152bb09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41156
27879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.4115627879
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.4253436144
Short name T580
Test name
Test status
Simulation time 8365281145 ps
CPU time 8.93 seconds
Started Apr 23 02:38:02 PM PDT 24
Finished Apr 23 02:38:11 PM PDT 24
Peak memory 204028 kb
Host smart-e4f387e1-2f91-4702-8aa2-d2f5949895c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42534
36144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.4253436144
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.482086566
Short name T651
Test name
Test status
Simulation time 8457540671 ps
CPU time 8.37 seconds
Started Apr 23 02:37:57 PM PDT 24
Finished Apr 23 02:38:07 PM PDT 24
Peak memory 203984 kb
Host smart-1e48ab2c-71a8-417e-b1bb-0d6dfa351590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48208
6566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.482086566
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.2348072057
Short name T652
Test name
Test status
Simulation time 8402109782 ps
CPU time 8.08 seconds
Started Apr 23 02:38:08 PM PDT 24
Finished Apr 23 02:38:17 PM PDT 24
Peak memory 204004 kb
Host smart-02335863-d71e-4226-a555-5ac0cba9a4dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23480
72057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.2348072057
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.647639901
Short name T556
Test name
Test status
Simulation time 8410927720 ps
CPU time 7.63 seconds
Started Apr 23 02:37:59 PM PDT 24
Finished Apr 23 02:38:08 PM PDT 24
Peak memory 204012 kb
Host smart-a9f53dea-6b2a-4f69-8b9c-52260fa1b3d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64763
9901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.647639901
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.1192124274
Short name T703
Test name
Test status
Simulation time 8464957554 ps
CPU time 7.99 seconds
Started Apr 23 02:38:06 PM PDT 24
Finished Apr 23 02:38:15 PM PDT 24
Peak memory 204036 kb
Host smart-7f2c3808-d2d3-4965-87a9-0d32bfc8a5d7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1192124274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.1192124274
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.2239647596
Short name T1146
Test name
Test status
Simulation time 8397880681 ps
CPU time 8.27 seconds
Started Apr 23 02:38:07 PM PDT 24
Finished Apr 23 02:38:16 PM PDT 24
Peak memory 203984 kb
Host smart-2acfd7d7-451d-4b47-94d2-f25763c9a3b9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2239647596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.2239647596
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.1823033938
Short name T796
Test name
Test status
Simulation time 8389539086 ps
CPU time 9.14 seconds
Started Apr 23 02:38:08 PM PDT 24
Finished Apr 23 02:38:19 PM PDT 24
Peak memory 204040 kb
Host smart-6d64a9c5-6390-4a37-b7ed-68f22317f8a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18230
33938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.1823033938
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.1116208103
Short name T938
Test name
Test status
Simulation time 8377958374 ps
CPU time 8.49 seconds
Started Apr 23 02:38:05 PM PDT 24
Finished Apr 23 02:38:14 PM PDT 24
Peak memory 203984 kb
Host smart-1b36f40d-89db-44b4-83f6-63e97eb01398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11162
08103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1116208103
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_enable.3312680791
Short name T49
Test name
Test status
Simulation time 8376931959 ps
CPU time 8.61 seconds
Started Apr 23 02:38:09 PM PDT 24
Finished Apr 23 02:38:18 PM PDT 24
Peak memory 203964 kb
Host smart-c7a81de3-301c-4add-9abf-f12fb973fd45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33126
80791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.3312680791
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.2944895473
Short name T215
Test name
Test status
Simulation time 207256504 ps
CPU time 2.13 seconds
Started Apr 23 02:38:04 PM PDT 24
Finished Apr 23 02:38:07 PM PDT 24
Peak memory 204064 kb
Host smart-35d3c2b7-cc15-4308-9d92-0d040bf6ac0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29448
95473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.2944895473
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.3004471897
Short name T1086
Test name
Test status
Simulation time 8492048767 ps
CPU time 8.4 seconds
Started Apr 23 02:38:09 PM PDT 24
Finished Apr 23 02:38:18 PM PDT 24
Peak memory 204012 kb
Host smart-bfa5f279-426c-400f-b23c-5419f91280ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30044
71897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.3004471897
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.352108037
Short name T202
Test name
Test status
Simulation time 8366078412 ps
CPU time 8.1 seconds
Started Apr 23 02:38:10 PM PDT 24
Finished Apr 23 02:38:19 PM PDT 24
Peak memory 204056 kb
Host smart-3636d7ee-1d8d-464b-992f-333bd3eaa33c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35210
8037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.352108037
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.3366961800
Short name T364
Test name
Test status
Simulation time 8437645264 ps
CPU time 8.74 seconds
Started Apr 23 02:38:04 PM PDT 24
Finished Apr 23 02:38:13 PM PDT 24
Peak memory 204016 kb
Host smart-e6be1fc3-9e3c-4529-b04b-7e0ca19548c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33669
61800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3366961800
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.1803066824
Short name T504
Test name
Test status
Simulation time 8412383448 ps
CPU time 9.67 seconds
Started Apr 23 02:38:08 PM PDT 24
Finished Apr 23 02:38:18 PM PDT 24
Peak memory 204060 kb
Host smart-457585e6-958f-429c-b6f0-22eb16118bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18030
66824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.1803066824
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3419291377
Short name T551
Test name
Test status
Simulation time 8368535978 ps
CPU time 8.04 seconds
Started Apr 23 02:38:04 PM PDT 24
Finished Apr 23 02:38:13 PM PDT 24
Peak memory 203992 kb
Host smart-029d2bf0-8684-408d-bdca-e874654a0f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34192
91377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3419291377
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.3576348461
Short name T112
Test name
Test status
Simulation time 8472263869 ps
CPU time 8.09 seconds
Started Apr 23 02:38:03 PM PDT 24
Finished Apr 23 02:38:12 PM PDT 24
Peak memory 203956 kb
Host smart-916c6eac-6fc2-4bef-8d73-807db7d9d7a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35763
48461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3576348461
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.303507997
Short name T1020
Test name
Test status
Simulation time 8412041247 ps
CPU time 9.77 seconds
Started Apr 23 02:38:03 PM PDT 24
Finished Apr 23 02:38:13 PM PDT 24
Peak memory 203972 kb
Host smart-5b466401-9175-4b92-8e88-f759d1653373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30350
7997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.303507997
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.3245562541
Short name T1358
Test name
Test status
Simulation time 8407723704 ps
CPU time 9.57 seconds
Started Apr 23 02:38:05 PM PDT 24
Finished Apr 23 02:38:15 PM PDT 24
Peak memory 204060 kb
Host smart-1c24a152-f1cb-4267-bf2c-11b8ea285745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32455
62541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.3245562541
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1150402805
Short name T161
Test name
Test status
Simulation time 8374423967 ps
CPU time 7.89 seconds
Started Apr 23 02:38:10 PM PDT 24
Finished Apr 23 02:38:19 PM PDT 24
Peak memory 203992 kb
Host smart-90e5ba02-9efe-420d-bcba-d8d1729115a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11504
02805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1150402805
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.163834526
Short name T500
Test name
Test status
Simulation time 8402592955 ps
CPU time 9.35 seconds
Started Apr 23 02:38:04 PM PDT 24
Finished Apr 23 02:38:14 PM PDT 24
Peak memory 204000 kb
Host smart-83cd9db7-b63b-42b9-b17e-49387b1d022e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16383
4526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.163834526
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.1423276248
Short name T42
Test name
Test status
Simulation time 36966129 ps
CPU time 0.66 seconds
Started Apr 23 02:38:06 PM PDT 24
Finished Apr 23 02:38:08 PM PDT 24
Peak memory 203904 kb
Host smart-044a9822-315f-4db9-8d05-5f09a0ce4163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14232
76248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.1423276248
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.1653589706
Short name T89
Test name
Test status
Simulation time 27646567074 ps
CPU time 55.06 seconds
Started Apr 23 02:38:05 PM PDT 24
Finished Apr 23 02:39:00 PM PDT 24
Peak memory 204300 kb
Host smart-dd8e521c-0282-413e-8e59-70654b1e1c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16535
89706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.1653589706
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.559263730
Short name T333
Test name
Test status
Simulation time 8395749384 ps
CPU time 8.43 seconds
Started Apr 23 02:38:06 PM PDT 24
Finished Apr 23 02:38:15 PM PDT 24
Peak memory 204004 kb
Host smart-e7f25391-bd67-4dc7-8a6f-f45b5b3444d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55926
3730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.559263730
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.490248626
Short name T1062
Test name
Test status
Simulation time 8391040331 ps
CPU time 8.35 seconds
Started Apr 23 02:38:02 PM PDT 24
Finished Apr 23 02:38:11 PM PDT 24
Peak memory 204032 kb
Host smart-87e5b43c-caf4-4836-81f4-de1ac83216c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49024
8626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.490248626
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.3411661778
Short name T1376
Test name
Test status
Simulation time 8391381052 ps
CPU time 7.96 seconds
Started Apr 23 02:38:04 PM PDT 24
Finished Apr 23 02:38:13 PM PDT 24
Peak memory 203980 kb
Host smart-6c44ad88-aea9-4a78-af6b-a1e109c0c1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34116
61778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.3411661778
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.4236078736
Short name T1141
Test name
Test status
Simulation time 8444711167 ps
CPU time 8.57 seconds
Started Apr 23 02:38:04 PM PDT 24
Finished Apr 23 02:38:13 PM PDT 24
Peak memory 204056 kb
Host smart-cf0c7381-8d63-4f98-b64d-0b0709f6b835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42360
78736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.4236078736
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.2228966586
Short name T585
Test name
Test status
Simulation time 8376057321 ps
CPU time 9.86 seconds
Started Apr 23 02:38:09 PM PDT 24
Finished Apr 23 02:38:20 PM PDT 24
Peak memory 204028 kb
Host smart-de30197f-5fd8-4e07-8fbf-708ec4a141fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22289
66586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.2228966586
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.1612307900
Short name T131
Test name
Test status
Simulation time 8470404809 ps
CPU time 8.31 seconds
Started Apr 23 02:38:02 PM PDT 24
Finished Apr 23 02:38:11 PM PDT 24
Peak memory 204032 kb
Host smart-369ac227-a93d-4d40-9aa5-4eb3877c3c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16123
07900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1612307900
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.1704233555
Short name T389
Test name
Test status
Simulation time 8376922632 ps
CPU time 9.59 seconds
Started Apr 23 02:38:12 PM PDT 24
Finished Apr 23 02:38:22 PM PDT 24
Peak memory 204052 kb
Host smart-18a382c7-3bb8-41eb-8ef8-85e7ac771485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17042
33555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.1704233555
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1792062914
Short name T401
Test name
Test status
Simulation time 8389160625 ps
CPU time 7.82 seconds
Started Apr 23 02:38:10 PM PDT 24
Finished Apr 23 02:38:19 PM PDT 24
Peak memory 204052 kb
Host smart-e5d5dcfe-df82-4a50-b288-9a6c323a9f0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17920
62914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1792062914
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.777026316
Short name T311
Test name
Test status
Simulation time 8466967362 ps
CPU time 7.97 seconds
Started Apr 23 02:35:30 PM PDT 24
Finished Apr 23 02:35:38 PM PDT 24
Peak memory 204012 kb
Host smart-91d005b2-8ba8-4711-b600-87c59b0fbfc9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=777026316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.777026316
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.448620332
Short name T341
Test name
Test status
Simulation time 8381070841 ps
CPU time 7.58 seconds
Started Apr 23 02:35:27 PM PDT 24
Finished Apr 23 02:35:35 PM PDT 24
Peak memory 203996 kb
Host smart-9911827a-d17f-456c-b9fc-470c16ce95c1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=448620332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.448620332
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.3082217221
Short name T1221
Test name
Test status
Simulation time 8434412593 ps
CPU time 7.36 seconds
Started Apr 23 02:35:25 PM PDT 24
Finished Apr 23 02:35:33 PM PDT 24
Peak memory 204024 kb
Host smart-ae52f884-e1fd-410f-bd99-6150101898dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30822
17221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.3082217221
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.3656380177
Short name T465
Test name
Test status
Simulation time 8386937281 ps
CPU time 7.75 seconds
Started Apr 23 02:35:20 PM PDT 24
Finished Apr 23 02:35:29 PM PDT 24
Peak memory 204052 kb
Host smart-86af4974-be1e-4a7f-9f99-a9a191f7bd25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36563
80177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.3656380177
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_enable.1916904960
Short name T777
Test name
Test status
Simulation time 8375045511 ps
CPU time 9.05 seconds
Started Apr 23 02:35:21 PM PDT 24
Finished Apr 23 02:35:31 PM PDT 24
Peak memory 204036 kb
Host smart-76dc5013-fc8f-4b28-aced-ccbcd03c72b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19169
04960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1916904960
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.1547161472
Short name T727
Test name
Test status
Simulation time 116040189 ps
CPU time 1.18 seconds
Started Apr 23 02:35:20 PM PDT 24
Finished Apr 23 02:35:22 PM PDT 24
Peak memory 204136 kb
Host smart-cae19da9-7671-4013-b860-4c37992f15af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15471
61472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1547161472
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.677301099
Short name T386
Test name
Test status
Simulation time 8404432689 ps
CPU time 8.23 seconds
Started Apr 23 02:35:24 PM PDT 24
Finished Apr 23 02:35:33 PM PDT 24
Peak memory 204064 kb
Host smart-c87ae450-613d-4f51-b303-2bd90578a4dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67730
1099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.677301099
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.2476412617
Short name T198
Test name
Test status
Simulation time 8370630114 ps
CPU time 8.55 seconds
Started Apr 23 02:35:23 PM PDT 24
Finished Apr 23 02:35:31 PM PDT 24
Peak memory 204092 kb
Host smart-9044d98f-b958-4e0a-8321-1e3e892dc54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24764
12617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.2476412617
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1951204339
Short name T137
Test name
Test status
Simulation time 8437834898 ps
CPU time 8.79 seconds
Started Apr 23 02:35:24 PM PDT 24
Finished Apr 23 02:35:33 PM PDT 24
Peak memory 204044 kb
Host smart-8d7f9a39-b3b3-478b-b38f-123aaaaa04d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19512
04339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1951204339
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.3697600818
Short name T1003
Test name
Test status
Simulation time 8418603497 ps
CPU time 8.97 seconds
Started Apr 23 02:35:19 PM PDT 24
Finished Apr 23 02:35:28 PM PDT 24
Peak memory 204028 kb
Host smart-e4f27f78-11c2-48c0-a174-0af2b499477b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36976
00818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.3697600818
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.877666612
Short name T288
Test name
Test status
Simulation time 8368677112 ps
CPU time 9.53 seconds
Started Apr 23 02:35:25 PM PDT 24
Finished Apr 23 02:35:35 PM PDT 24
Peak memory 204044 kb
Host smart-045f081f-1281-48ca-82d7-c0dbf65f28ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87766
6612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.877666612
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3553947924
Short name T123
Test name
Test status
Simulation time 8409863330 ps
CPU time 9.92 seconds
Started Apr 23 02:35:24 PM PDT 24
Finished Apr 23 02:35:34 PM PDT 24
Peak memory 204028 kb
Host smart-7b0b64eb-8460-487c-98f4-4ec6787290a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35539
47924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3553947924
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2127161235
Short name T34
Test name
Test status
Simulation time 8407293384 ps
CPU time 7.94 seconds
Started Apr 23 02:35:25 PM PDT 24
Finished Apr 23 02:35:34 PM PDT 24
Peak memory 204028 kb
Host smart-13d17c64-b39d-4fd7-8e07-f39a502951c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21271
61235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2127161235
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.1445143866
Short name T659
Test name
Test status
Simulation time 8420591569 ps
CPU time 8.31 seconds
Started Apr 23 02:35:25 PM PDT 24
Finished Apr 23 02:35:34 PM PDT 24
Peak memory 204036 kb
Host smart-f24c5a89-f6a6-4c83-911a-1844b09afa7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14451
43866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.1445143866
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.3794568773
Short name T555
Test name
Test status
Simulation time 8416240516 ps
CPU time 7.59 seconds
Started Apr 23 02:35:25 PM PDT 24
Finished Apr 23 02:35:33 PM PDT 24
Peak memory 204028 kb
Host smart-3767e317-9bbb-4675-aa01-0db728ca4614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37945
68773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.3794568773
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.1638514882
Short name T361
Test name
Test status
Simulation time 8431730986 ps
CPU time 7.84 seconds
Started Apr 23 02:35:26 PM PDT 24
Finished Apr 23 02:35:34 PM PDT 24
Peak memory 204052 kb
Host smart-0ed69ba4-5b7c-47e7-a511-a10eb213c3a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16385
14882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.1638514882
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3133278512
Short name T1330
Test name
Test status
Simulation time 38574615 ps
CPU time 0.63 seconds
Started Apr 23 02:35:27 PM PDT 24
Finished Apr 23 02:35:28 PM PDT 24
Peak memory 203928 kb
Host smart-078c5418-4823-4128-b08a-f5e49e8ed5dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31332
78512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3133278512
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.46398412
Short name T1215
Test name
Test status
Simulation time 17509428031 ps
CPU time 33.63 seconds
Started Apr 23 02:35:26 PM PDT 24
Finished Apr 23 02:36:00 PM PDT 24
Peak memory 204328 kb
Host smart-e447ba55-f02c-4f83-9395-e666ea89e78b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46398
412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.46398412
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.162363386
Short name T898
Test name
Test status
Simulation time 8407161378 ps
CPU time 7.77 seconds
Started Apr 23 02:35:23 PM PDT 24
Finished Apr 23 02:35:31 PM PDT 24
Peak memory 204012 kb
Host smart-aa27068a-1cd6-4037-ab7d-4c3e2932b2f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16236
3386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.162363386
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2739478373
Short name T477
Test name
Test status
Simulation time 8395098449 ps
CPU time 7.67 seconds
Started Apr 23 02:35:24 PM PDT 24
Finished Apr 23 02:35:32 PM PDT 24
Peak memory 203984 kb
Host smart-80866f1a-54ad-430d-af5a-e69916d763b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27394
78373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2739478373
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.2213885152
Short name T757
Test name
Test status
Simulation time 8391394958 ps
CPU time 8.3 seconds
Started Apr 23 02:35:23 PM PDT 24
Finished Apr 23 02:35:32 PM PDT 24
Peak memory 204012 kb
Host smart-0b0a9ee3-64e4-4abe-ad36-c98f4deffba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22138
85152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.2213885152
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.3622280270
Short name T60
Test name
Test status
Simulation time 929711138 ps
CPU time 1.66 seconds
Started Apr 23 02:35:35 PM PDT 24
Finished Apr 23 02:35:38 PM PDT 24
Peak memory 221260 kb
Host smart-5922d38f-cf21-4e7d-90a1-7203db6eacfb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3622280270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3622280270
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.3384707990
Short name T1037
Test name
Test status
Simulation time 8371296730 ps
CPU time 7.66 seconds
Started Apr 23 02:35:24 PM PDT 24
Finished Apr 23 02:35:32 PM PDT 24
Peak memory 204060 kb
Host smart-61b1d9f8-ede6-414d-839e-58dc4ccfd449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33847
07990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.3384707990
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.1952430545
Short name T700
Test name
Test status
Simulation time 8364067535 ps
CPU time 7.76 seconds
Started Apr 23 02:35:26 PM PDT 24
Finished Apr 23 02:35:35 PM PDT 24
Peak memory 204016 kb
Host smart-3818792f-9844-4100-9848-86c2ab60c228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19524
30545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.1952430545
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.1476250007
Short name T946
Test name
Test status
Simulation time 8410073612 ps
CPU time 8.25 seconds
Started Apr 23 02:35:21 PM PDT 24
Finished Apr 23 02:35:30 PM PDT 24
Peak memory 204048 kb
Host smart-015996e1-827a-4c35-86a6-bae375d15b5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14762
50007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.1476250007
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.4083181656
Short name T289
Test name
Test status
Simulation time 8403036777 ps
CPU time 7.62 seconds
Started Apr 23 02:35:25 PM PDT 24
Finished Apr 23 02:35:34 PM PDT 24
Peak memory 204036 kb
Host smart-4d29723c-539c-4344-b56b-8a740638efed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40831
81656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.4083181656
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.2081950226
Short name T416
Test name
Test status
Simulation time 8371626058 ps
CPU time 8.06 seconds
Started Apr 23 02:35:24 PM PDT 24
Finished Apr 23 02:35:32 PM PDT 24
Peak memory 204060 kb
Host smart-1a8965db-b509-451e-bf28-a0d8a85ca3f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20819
50226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.2081950226
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.3368926312
Short name T706
Test name
Test status
Simulation time 8472653471 ps
CPU time 7.98 seconds
Started Apr 23 02:38:13 PM PDT 24
Finished Apr 23 02:38:22 PM PDT 24
Peak memory 203992 kb
Host smart-30add84d-b53e-4668-808d-ac6d2b1e11f1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3368926312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.3368926312
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.2117431
Short name T1289
Test name
Test status
Simulation time 8377813253 ps
CPU time 9.79 seconds
Started Apr 23 02:38:10 PM PDT 24
Finished Apr 23 02:38:21 PM PDT 24
Peak memory 204016 kb
Host smart-a6a70456-bcab-447a-b113-9b97d4172a67
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2117431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.2117431
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.341877462
Short name T130
Test name
Test status
Simulation time 8408447279 ps
CPU time 8.06 seconds
Started Apr 23 02:38:10 PM PDT 24
Finished Apr 23 02:38:19 PM PDT 24
Peak memory 203984 kb
Host smart-d76815bd-4e14-4faa-a849-4bb53643cbbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34187
7462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.341877462
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.2488366066
Short name T241
Test name
Test status
Simulation time 8374169819 ps
CPU time 9.59 seconds
Started Apr 23 02:38:08 PM PDT 24
Finished Apr 23 02:38:19 PM PDT 24
Peak memory 204036 kb
Host smart-bd9ca1a1-6ffa-41a5-8060-c98af986eb8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24883
66066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.2488366066
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_enable.3664577664
Short name T1205
Test name
Test status
Simulation time 8408877365 ps
CPU time 10.17 seconds
Started Apr 23 02:38:09 PM PDT 24
Finished Apr 23 02:38:20 PM PDT 24
Peak memory 203964 kb
Host smart-fe1e5b16-3a29-43cf-bc73-9d8867cde12c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36645
77664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.3664577664
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.4124110048
Short name T1361
Test name
Test status
Simulation time 65318406 ps
CPU time 1.76 seconds
Started Apr 23 02:38:06 PM PDT 24
Finished Apr 23 02:38:09 PM PDT 24
Peak memory 204140 kb
Host smart-1f8d25c1-2ccd-4890-b4ae-1a96ece289ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41241
10048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.4124110048
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.2068201284
Short name T501
Test name
Test status
Simulation time 8447320339 ps
CPU time 8.21 seconds
Started Apr 23 02:38:11 PM PDT 24
Finished Apr 23 02:38:20 PM PDT 24
Peak memory 204060 kb
Host smart-454c19d0-43a9-4aad-bfc7-c45d8142a57b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20682
01284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.2068201284
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.2830651610
Short name T869
Test name
Test status
Simulation time 8363237510 ps
CPU time 8.87 seconds
Started Apr 23 02:38:12 PM PDT 24
Finished Apr 23 02:38:21 PM PDT 24
Peak memory 204056 kb
Host smart-7e3282fd-8056-4148-b8c1-6cdb533132ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28306
51610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.2830651610
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.1265436818
Short name T587
Test name
Test status
Simulation time 8434261381 ps
CPU time 7.62 seconds
Started Apr 23 02:38:07 PM PDT 24
Finished Apr 23 02:38:15 PM PDT 24
Peak memory 204020 kb
Host smart-2f74d978-5983-428a-9979-fd629beedcfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12654
36818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1265436818
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.1609899671
Short name T1075
Test name
Test status
Simulation time 8435251956 ps
CPU time 10.09 seconds
Started Apr 23 02:38:09 PM PDT 24
Finished Apr 23 02:38:20 PM PDT 24
Peak memory 204020 kb
Host smart-2e93461f-6942-41a5-ae78-0a6dfd1eb62f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16098
99671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1609899671
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3029204874
Short name T1162
Test name
Test status
Simulation time 8369458083 ps
CPU time 9.9 seconds
Started Apr 23 02:38:07 PM PDT 24
Finished Apr 23 02:38:18 PM PDT 24
Peak memory 204016 kb
Host smart-7bb6c717-1069-4dd8-a4bd-2ba2a2b049dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30292
04874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3029204874
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.2600249609
Short name T760
Test name
Test status
Simulation time 8468482719 ps
CPU time 8.76 seconds
Started Apr 23 02:38:08 PM PDT 24
Finished Apr 23 02:38:18 PM PDT 24
Peak memory 204024 kb
Host smart-c3e5e493-8f9d-4a3e-9cc0-f2001030d4ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26002
49609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.2600249609
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.2269378417
Short name T331
Test name
Test status
Simulation time 8380683275 ps
CPU time 9.25 seconds
Started Apr 23 02:38:08 PM PDT 24
Finished Apr 23 02:38:19 PM PDT 24
Peak memory 204012 kb
Host smart-4284e86b-c3fc-4b77-a615-d294885e6e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22693
78417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.2269378417
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.3347018712
Short name T550
Test name
Test status
Simulation time 8393362957 ps
CPU time 10.57 seconds
Started Apr 23 02:38:08 PM PDT 24
Finished Apr 23 02:38:19 PM PDT 24
Peak memory 204016 kb
Host smart-ffd66b64-8185-4d74-b21f-68559e5a13a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33470
18712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.3347018712
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.2217987379
Short name T753
Test name
Test status
Simulation time 8407486524 ps
CPU time 9.04 seconds
Started Apr 23 02:38:09 PM PDT 24
Finished Apr 23 02:38:19 PM PDT 24
Peak memory 204072 kb
Host smart-ca119393-17e1-4ad7-9109-47908b8c55be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22179
87379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.2217987379
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.3901891549
Short name T1240
Test name
Test status
Simulation time 8366166314 ps
CPU time 7.93 seconds
Started Apr 23 02:38:09 PM PDT 24
Finished Apr 23 02:38:18 PM PDT 24
Peak memory 203972 kb
Host smart-b4ae7d4a-f9a9-4d60-9131-fc2f94c840fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39018
91549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.3901891549
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.3489585707
Short name T43
Test name
Test status
Simulation time 47955914 ps
CPU time 0.71 seconds
Started Apr 23 02:38:12 PM PDT 24
Finished Apr 23 02:38:13 PM PDT 24
Peak memory 203904 kb
Host smart-45bccb75-8999-4224-9a64-5700811d85b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34895
85707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.3489585707
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.2933712947
Short name T249
Test name
Test status
Simulation time 18188822766 ps
CPU time 32.23 seconds
Started Apr 23 02:38:08 PM PDT 24
Finished Apr 23 02:38:41 PM PDT 24
Peak memory 204252 kb
Host smart-9bcc0935-7c0b-415a-95ab-72c4fc2af226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29337
12947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.2933712947
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.2596913519
Short name T384
Test name
Test status
Simulation time 8376951861 ps
CPU time 7.78 seconds
Started Apr 23 02:38:09 PM PDT 24
Finished Apr 23 02:38:18 PM PDT 24
Peak memory 204044 kb
Host smart-018ced41-2780-434d-a7a3-ed8f5caecc6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25969
13519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.2596913519
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.368560973
Short name T365
Test name
Test status
Simulation time 8380556105 ps
CPU time 7.86 seconds
Started Apr 23 02:38:10 PM PDT 24
Finished Apr 23 02:38:18 PM PDT 24
Peak memory 203960 kb
Host smart-b3262870-7a54-4942-967c-a4f4d211c97e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36856
0973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.368560973
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.2840824476
Short name T399
Test name
Test status
Simulation time 8384095938 ps
CPU time 8.73 seconds
Started Apr 23 02:38:09 PM PDT 24
Finished Apr 23 02:38:19 PM PDT 24
Peak memory 204008 kb
Host smart-27173766-7725-4773-b3b7-8845a20e4d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28408
24476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.2840824476
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.2803509307
Short name T934
Test name
Test status
Simulation time 8408004312 ps
CPU time 8.09 seconds
Started Apr 23 02:38:12 PM PDT 24
Finished Apr 23 02:38:21 PM PDT 24
Peak memory 204032 kb
Host smart-c3c55f66-48cc-42f3-a863-caba094a4311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28035
09307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.2803509307
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.2615245367
Short name T1191
Test name
Test status
Simulation time 8368295609 ps
CPU time 7.52 seconds
Started Apr 23 02:38:10 PM PDT 24
Finished Apr 23 02:38:18 PM PDT 24
Peak memory 204024 kb
Host smart-9eec5ab7-aa23-47c8-800f-4cdb9d0a3122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26152
45367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.2615245367
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.3895104857
Short name T435
Test name
Test status
Simulation time 8422546674 ps
CPU time 9.5 seconds
Started Apr 23 02:38:08 PM PDT 24
Finished Apr 23 02:38:19 PM PDT 24
Peak memory 204012 kb
Host smart-aa961574-5ce8-497f-8e2d-288d62b0790f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38951
04857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.3895104857
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.2081070403
Short name T574
Test name
Test status
Simulation time 8413861084 ps
CPU time 10.03 seconds
Started Apr 23 02:38:09 PM PDT 24
Finished Apr 23 02:38:20 PM PDT 24
Peak memory 203992 kb
Host smart-eec7b9a1-e295-48a3-915a-9d39870f5a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20810
70403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.2081070403
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.2432111623
Short name T1074
Test name
Test status
Simulation time 8393804082 ps
CPU time 7.71 seconds
Started Apr 23 02:38:11 PM PDT 24
Finished Apr 23 02:38:19 PM PDT 24
Peak memory 204040 kb
Host smart-7b81debe-7b17-487c-be01-b70744fd1d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24321
11623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.2432111623
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.1811302816
Short name T1185
Test name
Test status
Simulation time 8467173438 ps
CPU time 8.71 seconds
Started Apr 23 02:38:28 PM PDT 24
Finished Apr 23 02:38:37 PM PDT 24
Peak memory 204008 kb
Host smart-dc4f59d0-1cf0-4b1c-a4c5-9e964b97b28b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1811302816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.1811302816
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.2224771635
Short name T814
Test name
Test status
Simulation time 8383008308 ps
CPU time 7.95 seconds
Started Apr 23 02:38:15 PM PDT 24
Finished Apr 23 02:38:23 PM PDT 24
Peak memory 204012 kb
Host smart-f5a49376-7061-419b-a511-ab6520be6d16
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2224771635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.2224771635
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.random_length_in_trans.207441940
Short name T463
Test name
Test status
Simulation time 8452445823 ps
CPU time 7.75 seconds
Started Apr 23 02:38:22 PM PDT 24
Finished Apr 23 02:38:40 PM PDT 24
Peak memory 204056 kb
Host smart-bf2561f4-af8f-4716-afcd-cff389f7e295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20744
1940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.207441940
Directory /workspace/41.random_length_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2196990191
Short name T315
Test name
Test status
Simulation time 8385594412 ps
CPU time 8.3 seconds
Started Apr 23 02:38:12 PM PDT 24
Finished Apr 23 02:38:21 PM PDT 24
Peak memory 204076 kb
Host smart-06e5d0ff-54b2-4cd8-94e6-942f5c6d2dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21969
90191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2196990191
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_enable.2158356235
Short name T854
Test name
Test status
Simulation time 8407155367 ps
CPU time 10.37 seconds
Started Apr 23 02:38:12 PM PDT 24
Finished Apr 23 02:38:23 PM PDT 24
Peak memory 204000 kb
Host smart-62e55927-f3c4-454f-a4aa-fecc71b54fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21583
56235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.2158356235
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3736570857
Short name T212
Test name
Test status
Simulation time 218211158 ps
CPU time 1.87 seconds
Started Apr 23 02:38:16 PM PDT 24
Finished Apr 23 02:38:19 PM PDT 24
Peak memory 204120 kb
Host smart-2ea97304-f42d-4831-b7d7-64c7c3b0e14c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37365
70857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3736570857
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.2542252520
Short name T1222
Test name
Test status
Simulation time 8432233770 ps
CPU time 10.01 seconds
Started Apr 23 02:38:13 PM PDT 24
Finished Apr 23 02:38:23 PM PDT 24
Peak memory 204024 kb
Host smart-ca2cb65e-ebfb-44cb-ba17-fd9614afd78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25422
52520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.2542252520
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1127163736
Short name T949
Test name
Test status
Simulation time 8373753507 ps
CPU time 7.59 seconds
Started Apr 23 02:38:16 PM PDT 24
Finished Apr 23 02:38:24 PM PDT 24
Peak memory 204048 kb
Host smart-a41a8ee1-e19f-4d26-b487-62b8df8abaa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11271
63736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1127163736
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.2557683512
Short name T1281
Test name
Test status
Simulation time 8469402766 ps
CPU time 10.31 seconds
Started Apr 23 02:38:12 PM PDT 24
Finished Apr 23 02:38:23 PM PDT 24
Peak memory 204020 kb
Host smart-4f107bc5-8d0f-4a65-8a75-e766c14c9836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25576
83512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.2557683512
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.976103177
Short name T447
Test name
Test status
Simulation time 8418470141 ps
CPU time 9.39 seconds
Started Apr 23 02:38:18 PM PDT 24
Finished Apr 23 02:38:28 PM PDT 24
Peak memory 203996 kb
Host smart-c8e75948-b748-4596-8d5f-e3329dc39536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97610
3177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.976103177
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.4060131952
Short name T795
Test name
Test status
Simulation time 8370050865 ps
CPU time 7.64 seconds
Started Apr 23 02:38:21 PM PDT 24
Finished Apr 23 02:38:30 PM PDT 24
Peak memory 204012 kb
Host smart-e0e393c9-8f19-46b5-a567-b69d7aa12565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40601
31952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.4060131952
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.1112864826
Short name T102
Test name
Test status
Simulation time 8465843384 ps
CPU time 9.36 seconds
Started Apr 23 02:38:18 PM PDT 24
Finished Apr 23 02:38:28 PM PDT 24
Peak memory 203996 kb
Host smart-fe839f54-3fb8-4f86-b74c-17efdcd8d4c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11128
64826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.1112864826
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.2779722095
Short name T859
Test name
Test status
Simulation time 8374252459 ps
CPU time 7.69 seconds
Started Apr 23 02:38:15 PM PDT 24
Finished Apr 23 02:38:24 PM PDT 24
Peak memory 204040 kb
Host smart-1ab9939a-0033-47bd-8064-2228312963a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27797
22095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.2779722095
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.1435305800
Short name T306
Test name
Test status
Simulation time 8479776616 ps
CPU time 8.69 seconds
Started Apr 23 02:38:36 PM PDT 24
Finished Apr 23 02:38:45 PM PDT 24
Peak memory 204044 kb
Host smart-b718126e-e69d-41c1-9b23-81a4e09bc26e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14353
05800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.1435305800
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.4037719554
Short name T173
Test name
Test status
Simulation time 8400223226 ps
CPU time 8.41 seconds
Started Apr 23 02:38:13 PM PDT 24
Finished Apr 23 02:38:22 PM PDT 24
Peak memory 203968 kb
Host smart-a2c61c97-6c54-4917-847c-5beb67688823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40377
19554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.4037719554
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.353991373
Short name T1
Test name
Test status
Simulation time 8363679561 ps
CPU time 7.54 seconds
Started Apr 23 02:38:19 PM PDT 24
Finished Apr 23 02:38:27 PM PDT 24
Peak memory 204008 kb
Host smart-8d11fa21-dcda-4efb-8df8-5a87eacd0ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35399
1373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.353991373
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.1319230113
Short name T41
Test name
Test status
Simulation time 40234878 ps
CPU time 0.66 seconds
Started Apr 23 02:38:18 PM PDT 24
Finished Apr 23 02:38:20 PM PDT 24
Peak memory 203880 kb
Host smart-a7e24eb9-942a-4420-8a37-a7826e050577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13192
30113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.1319230113
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.724724098
Short name T1048
Test name
Test status
Simulation time 17586512775 ps
CPU time 31.04 seconds
Started Apr 23 02:38:13 PM PDT 24
Finished Apr 23 02:38:45 PM PDT 24
Peak memory 204280 kb
Host smart-47c5035a-8cb1-432d-b41d-06e81391fcba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72472
4098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.724724098
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1579392902
Short name T619
Test name
Test status
Simulation time 8429266514 ps
CPU time 8.47 seconds
Started Apr 23 02:38:16 PM PDT 24
Finished Apr 23 02:38:25 PM PDT 24
Peak memory 204048 kb
Host smart-67365fd7-b54a-40f8-bf59-f7111aff35dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15793
92902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1579392902
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.922425574
Short name T143
Test name
Test status
Simulation time 8460850299 ps
CPU time 8.1 seconds
Started Apr 23 02:38:19 PM PDT 24
Finished Apr 23 02:38:28 PM PDT 24
Peak memory 204048 kb
Host smart-e37a060c-eb3d-4ce3-a0ab-f00ca3c6c68c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92242
5574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.922425574
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.2035402051
Short name T754
Test name
Test status
Simulation time 8396673539 ps
CPU time 8.07 seconds
Started Apr 23 02:38:27 PM PDT 24
Finished Apr 23 02:38:36 PM PDT 24
Peak memory 204056 kb
Host smart-d264cdbe-9be1-4e21-8b02-5335da0e210d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20354
02051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.2035402051
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.4094935911
Short name T450
Test name
Test status
Simulation time 8399448327 ps
CPU time 8.28 seconds
Started Apr 23 02:38:13 PM PDT 24
Finished Apr 23 02:38:21 PM PDT 24
Peak memory 204032 kb
Host smart-c8fc959a-d205-4473-b342-066d7c6efb56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40949
35911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.4094935911
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.835459846
Short name T362
Test name
Test status
Simulation time 8363036455 ps
CPU time 8.18 seconds
Started Apr 23 02:38:16 PM PDT 24
Finished Apr 23 02:38:24 PM PDT 24
Peak memory 204008 kb
Host smart-8e0d2838-2ef7-478e-ad74-842724e5b0ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83545
9846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.835459846
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.2326234769
Short name T631
Test name
Test status
Simulation time 8380521751 ps
CPU time 8.16 seconds
Started Apr 23 02:38:23 PM PDT 24
Finished Apr 23 02:38:32 PM PDT 24
Peak memory 203980 kb
Host smart-91b1bedf-aa1c-475e-8082-459cad2761f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23262
34769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.2326234769
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.1438279183
Short name T409
Test name
Test status
Simulation time 8371350021 ps
CPU time 8.24 seconds
Started Apr 23 02:38:22 PM PDT 24
Finished Apr 23 02:38:31 PM PDT 24
Peak memory 204008 kb
Host smart-d99bdbf1-ff8d-46b0-89bf-99520d0f349d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14382
79183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.1438279183
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.1706720829
Short name T366
Test name
Test status
Simulation time 8467156349 ps
CPU time 10.51 seconds
Started Apr 23 02:38:23 PM PDT 24
Finished Apr 23 02:38:34 PM PDT 24
Peak memory 204060 kb
Host smart-c5c1bf0f-c497-4633-8fc5-31323f7f3340
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1706720829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.1706720829
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.2741148051
Short name T1049
Test name
Test status
Simulation time 8378640237 ps
CPU time 9.87 seconds
Started Apr 23 02:38:27 PM PDT 24
Finished Apr 23 02:38:37 PM PDT 24
Peak memory 204060 kb
Host smart-7076c9cc-549c-4262-ba43-b57175463f74
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2741148051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.2741148051
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.3819665260
Short name T1077
Test name
Test status
Simulation time 8382138289 ps
CPU time 9.02 seconds
Started Apr 23 02:38:17 PM PDT 24
Finished Apr 23 02:38:26 PM PDT 24
Peak memory 204008 kb
Host smart-93aac4b2-0c6a-4d6d-ad04-0b1b56af99ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38196
65260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.3819665260
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2917507953
Short name T314
Test name
Test status
Simulation time 8377795020 ps
CPU time 7.51 seconds
Started Apr 23 02:38:18 PM PDT 24
Finished Apr 23 02:38:26 PM PDT 24
Peak memory 203972 kb
Host smart-c0002fca-0828-48cd-97ee-d579b5146a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29175
07953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2917507953
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_enable.1727676938
Short name T335
Test name
Test status
Simulation time 8379106567 ps
CPU time 7.78 seconds
Started Apr 23 02:38:24 PM PDT 24
Finished Apr 23 02:38:33 PM PDT 24
Peak memory 204048 kb
Host smart-ed34988e-4a7b-480b-9d5c-eec0c6b30a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17276
76938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.1727676938
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.2043707028
Short name T486
Test name
Test status
Simulation time 84087154 ps
CPU time 1.85 seconds
Started Apr 23 02:38:16 PM PDT 24
Finished Apr 23 02:38:18 PM PDT 24
Peak memory 204152 kb
Host smart-3a7059ad-d870-421e-9a40-877f332a7427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20437
07028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.2043707028
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.364460527
Short name T732
Test name
Test status
Simulation time 8417507106 ps
CPU time 7.67 seconds
Started Apr 23 02:38:25 PM PDT 24
Finished Apr 23 02:38:33 PM PDT 24
Peak memory 203644 kb
Host smart-115b0df2-fc3a-4711-9ea1-3c3878fdc892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36446
0527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.364460527
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.3987819806
Short name T1246
Test name
Test status
Simulation time 8369919500 ps
CPU time 7.92 seconds
Started Apr 23 02:38:24 PM PDT 24
Finished Apr 23 02:38:33 PM PDT 24
Peak memory 203976 kb
Host smart-be3e8a3a-2777-4f7e-833d-84d646995feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39878
19806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.3987819806
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.1244199812
Short name T842
Test name
Test status
Simulation time 8459108139 ps
CPU time 8.3 seconds
Started Apr 23 02:38:20 PM PDT 24
Finished Apr 23 02:38:29 PM PDT 24
Peak memory 204060 kb
Host smart-612f5658-b4d5-4ef9-a112-4515b27889ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12441
99812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1244199812
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.1897838133
Short name T293
Test name
Test status
Simulation time 8413016609 ps
CPU time 9.12 seconds
Started Apr 23 02:38:21 PM PDT 24
Finished Apr 23 02:38:31 PM PDT 24
Peak memory 204060 kb
Host smart-b48044bb-e283-4224-85ef-b660eb19314a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18978
38133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1897838133
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.2058819892
Short name T784
Test name
Test status
Simulation time 8375002808 ps
CPU time 10.36 seconds
Started Apr 23 02:38:17 PM PDT 24
Finished Apr 23 02:38:28 PM PDT 24
Peak memory 204020 kb
Host smart-f2be9804-d3be-45e6-8b73-2685bb42405b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20588
19892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.2058819892
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.4188092179
Short name T126
Test name
Test status
Simulation time 8434845506 ps
CPU time 8.01 seconds
Started Apr 23 02:38:22 PM PDT 24
Finished Apr 23 02:38:30 PM PDT 24
Peak memory 204012 kb
Host smart-72c919f0-45d2-4ecb-839a-79f15f30a098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41880
92179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.4188092179
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.329028272
Short name T712
Test name
Test status
Simulation time 8425294158 ps
CPU time 7.89 seconds
Started Apr 23 02:38:24 PM PDT 24
Finished Apr 23 02:38:33 PM PDT 24
Peak memory 203976 kb
Host smart-e42ddaaf-2c90-4a83-96ab-d3aa900aeda9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32902
8272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.329028272
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.2845478305
Short name T1251
Test name
Test status
Simulation time 8413640962 ps
CPU time 8.34 seconds
Started Apr 23 02:38:29 PM PDT 24
Finished Apr 23 02:38:38 PM PDT 24
Peak memory 204056 kb
Host smart-0f03b4cc-c03f-43ec-9e6e-56faf034b8a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28454
78305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.2845478305
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.1284911939
Short name T164
Test name
Test status
Simulation time 8377583245 ps
CPU time 8.62 seconds
Started Apr 23 02:38:25 PM PDT 24
Finished Apr 23 02:38:35 PM PDT 24
Peak memory 204044 kb
Host smart-946f07df-5025-4f58-855b-297560391ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12849
11939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.1284911939
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.1679081466
Short name T590
Test name
Test status
Simulation time 8374590197 ps
CPU time 7.91 seconds
Started Apr 23 02:38:16 PM PDT 24
Finished Apr 23 02:38:25 PM PDT 24
Peak memory 204016 kb
Host smart-517bcb06-fc71-4c32-af58-ee24e2963e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16790
81466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.1679081466
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.583172497
Short name T858
Test name
Test status
Simulation time 49384155 ps
CPU time 0.67 seconds
Started Apr 23 02:38:19 PM PDT 24
Finished Apr 23 02:38:20 PM PDT 24
Peak memory 203900 kb
Host smart-41112050-68fd-4ebc-abba-b4a02bfade9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58317
2497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.583172497
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.1810369761
Short name T246
Test name
Test status
Simulation time 29974488692 ps
CPU time 55.59 seconds
Started Apr 23 02:38:16 PM PDT 24
Finished Apr 23 02:39:12 PM PDT 24
Peak memory 204312 kb
Host smart-54b039d1-34c9-41e9-a5d6-c76ed4862bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18103
69761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.1810369761
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.426896053
Short name T382
Test name
Test status
Simulation time 8379798755 ps
CPU time 7.91 seconds
Started Apr 23 02:38:23 PM PDT 24
Finished Apr 23 02:38:32 PM PDT 24
Peak memory 204060 kb
Host smart-e3114351-e7ce-4861-8f9c-3067aa7c22c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42689
6053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.426896053
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.1197243499
Short name T132
Test name
Test status
Simulation time 8442667859 ps
CPU time 8.02 seconds
Started Apr 23 02:38:22 PM PDT 24
Finished Apr 23 02:38:30 PM PDT 24
Peak memory 204012 kb
Host smart-443fceb0-fb78-4dbe-add3-bbd61b2a7b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11972
43499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.1197243499
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.583489309
Short name T1256
Test name
Test status
Simulation time 8421244256 ps
CPU time 7.81 seconds
Started Apr 23 02:38:29 PM PDT 24
Finished Apr 23 02:38:37 PM PDT 24
Peak memory 204036 kb
Host smart-4687cade-fcfb-482b-bffc-dd99141ce736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58348
9309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.583489309
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.287622554
Short name T168
Test name
Test status
Simulation time 8379829800 ps
CPU time 7.38 seconds
Started Apr 23 02:38:24 PM PDT 24
Finished Apr 23 02:38:33 PM PDT 24
Peak memory 204056 kb
Host smart-296d33ba-dced-4ede-a94d-1df77e25095a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28762
2554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.287622554
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.405571700
Short name T455
Test name
Test status
Simulation time 8368484699 ps
CPU time 8.89 seconds
Started Apr 23 02:38:22 PM PDT 24
Finished Apr 23 02:38:32 PM PDT 24
Peak memory 204040 kb
Host smart-fc4974ef-98a2-445d-bfe1-92cab47ce7d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40557
1700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.405571700
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2340612199
Short name T1254
Test name
Test status
Simulation time 8484013876 ps
CPU time 8.6 seconds
Started Apr 23 02:38:24 PM PDT 24
Finished Apr 23 02:38:34 PM PDT 24
Peak memory 203988 kb
Host smart-361b5f5b-36dc-499e-ab3e-134327056fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23406
12199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2340612199
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.1469607538
Short name T304
Test name
Test status
Simulation time 8379853853 ps
CPU time 7.69 seconds
Started Apr 23 02:38:18 PM PDT 24
Finished Apr 23 02:38:27 PM PDT 24
Peak memory 204016 kb
Host smart-16cf2e36-3ef5-44ea-b805-cad6b9d25457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14696
07538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.1469607538
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.2465912514
Short name T1324
Test name
Test status
Simulation time 8401027158 ps
CPU time 10.09 seconds
Started Apr 23 02:38:29 PM PDT 24
Finished Apr 23 02:38:40 PM PDT 24
Peak memory 204004 kb
Host smart-deefff2c-7105-4153-a533-966c7c90d686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24659
12514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.2465912514
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.3263345459
Short name T1024
Test name
Test status
Simulation time 8468818239 ps
CPU time 8.95 seconds
Started Apr 23 02:38:21 PM PDT 24
Finished Apr 23 02:38:31 PM PDT 24
Peak memory 204016 kb
Host smart-7875b2a1-a8c3-4425-9fc1-683b8d946167
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3263345459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.3263345459
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.183182593
Short name T10
Test name
Test status
Simulation time 8382449678 ps
CPU time 7.77 seconds
Started Apr 23 02:38:25 PM PDT 24
Finished Apr 23 02:38:33 PM PDT 24
Peak memory 204060 kb
Host smart-978628fa-bd2f-435c-afe4-55404de93a57
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=183182593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.183182593
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.2547698217
Short name T502
Test name
Test status
Simulation time 8453880829 ps
CPU time 7.88 seconds
Started Apr 23 02:38:22 PM PDT 24
Finished Apr 23 02:38:30 PM PDT 24
Peak memory 203988 kb
Host smart-072d88d1-46ef-4fc6-9927-a4291a740e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25476
98217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.2547698217
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.1466430055
Short name T710
Test name
Test status
Simulation time 8417639075 ps
CPU time 7.88 seconds
Started Apr 23 02:38:16 PM PDT 24
Finished Apr 23 02:38:25 PM PDT 24
Peak memory 204052 kb
Host smart-026f1740-f197-4676-a01f-0af9385fa88f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14664
30055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1466430055
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_enable.4120017410
Short name T977
Test name
Test status
Simulation time 8379697390 ps
CPU time 8.34 seconds
Started Apr 23 02:38:22 PM PDT 24
Finished Apr 23 02:38:31 PM PDT 24
Peak memory 204012 kb
Host smart-3bfd8677-66cc-420a-8593-7aa7e9a92bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41200
17410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.4120017410
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.2975911288
Short name T52
Test name
Test status
Simulation time 82960680 ps
CPU time 1.4 seconds
Started Apr 23 02:38:24 PM PDT 24
Finished Apr 23 02:38:26 PM PDT 24
Peak memory 204044 kb
Host smart-2b3f7efb-57f2-427d-a2b5-3608d8f3255c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29759
11288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.2975911288
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.1160639864
Short name T1310
Test name
Test status
Simulation time 8410323395 ps
CPU time 8.12 seconds
Started Apr 23 02:38:23 PM PDT 24
Finished Apr 23 02:38:32 PM PDT 24
Peak memory 204056 kb
Host smart-7a1c455e-0bfd-4a27-86c5-68dd80569591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11606
39864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.1160639864
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.2700479337
Short name T1303
Test name
Test status
Simulation time 8363970396 ps
CPU time 8.05 seconds
Started Apr 23 02:38:23 PM PDT 24
Finished Apr 23 02:38:31 PM PDT 24
Peak memory 204044 kb
Host smart-0fde1909-17f3-4b38-a958-1729d551483e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27004
79337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.2700479337
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.3780215876
Short name T1116
Test name
Test status
Simulation time 8434153473 ps
CPU time 8.65 seconds
Started Apr 23 02:38:18 PM PDT 24
Finished Apr 23 02:38:27 PM PDT 24
Peak memory 203964 kb
Host smart-ab53ea3d-d67b-4384-a8d0-cf477066da0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37802
15876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3780215876
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.307938422
Short name T973
Test name
Test status
Simulation time 8428642232 ps
CPU time 9.19 seconds
Started Apr 23 02:38:16 PM PDT 24
Finished Apr 23 02:38:26 PM PDT 24
Peak memory 204008 kb
Host smart-5ffcf867-7506-40a0-ae76-c9f138e512b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30793
8422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.307938422
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.1232078900
Short name T340
Test name
Test status
Simulation time 8372206691 ps
CPU time 10.24 seconds
Started Apr 23 02:38:18 PM PDT 24
Finished Apr 23 02:38:29 PM PDT 24
Peak memory 203996 kb
Host smart-49c3857a-51a2-4360-8454-6ce312ef476b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12320
78900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1232078900
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.325766043
Short name T1167
Test name
Test status
Simulation time 8397288418 ps
CPU time 8.15 seconds
Started Apr 23 02:38:21 PM PDT 24
Finished Apr 23 02:38:30 PM PDT 24
Peak memory 204032 kb
Host smart-dd267365-13c0-4a8f-833f-50b9a6fc15d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32576
6043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.325766043
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.731226789
Short name T567
Test name
Test status
Simulation time 8403971448 ps
CPU time 9.14 seconds
Started Apr 23 02:38:16 PM PDT 24
Finished Apr 23 02:38:25 PM PDT 24
Peak memory 204024 kb
Host smart-5915a5f1-9d25-4a81-9633-2a485b207d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73122
6789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.731226789
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.2930733530
Short name T239
Test name
Test status
Simulation time 8392649817 ps
CPU time 8.15 seconds
Started Apr 23 02:38:21 PM PDT 24
Finished Apr 23 02:38:30 PM PDT 24
Peak memory 204028 kb
Host smart-ef209d2a-b4fb-44fd-b804-10240d4fdc0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29307
33530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.2930733530
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.75627374
Short name T176
Test name
Test status
Simulation time 8472811184 ps
CPU time 10.23 seconds
Started Apr 23 02:38:24 PM PDT 24
Finished Apr 23 02:38:35 PM PDT 24
Peak memory 204004 kb
Host smart-5a4ce91a-c794-4d51-a60a-790dbd830af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75627
374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.75627374
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.1580302313
Short name T748
Test name
Test status
Simulation time 8368455439 ps
CPU time 8.86 seconds
Started Apr 23 02:38:21 PM PDT 24
Finished Apr 23 02:38:30 PM PDT 24
Peak memory 203980 kb
Host smart-f02880fd-115d-40e4-9e5a-0b3891f7172e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15803
02313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.1580302313
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.1868151502
Short name T1043
Test name
Test status
Simulation time 32983750 ps
CPU time 0.61 seconds
Started Apr 23 02:38:23 PM PDT 24
Finished Apr 23 02:38:25 PM PDT 24
Peak memory 203940 kb
Host smart-c1c2f72c-fb4b-4666-b3f4-0671f0bd84c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18681
51502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.1868151502
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.2230874691
Short name T1255
Test name
Test status
Simulation time 20717455672 ps
CPU time 41.03 seconds
Started Apr 23 02:38:19 PM PDT 24
Finished Apr 23 02:39:01 PM PDT 24
Peak memory 204316 kb
Host smart-301c5c1a-b16e-4b19-930c-d6e4f180fa9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22308
74691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.2230874691
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.3708202426
Short name T48
Test name
Test status
Simulation time 8382682296 ps
CPU time 9.85 seconds
Started Apr 23 02:38:20 PM PDT 24
Finished Apr 23 02:38:30 PM PDT 24
Peak memory 204020 kb
Host smart-5a10ee5f-134a-4536-8180-95a719a73f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37082
02426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.3708202426
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3048752388
Short name T1269
Test name
Test status
Simulation time 8504837102 ps
CPU time 7.54 seconds
Started Apr 23 02:38:28 PM PDT 24
Finished Apr 23 02:38:36 PM PDT 24
Peak memory 203972 kb
Host smart-3e4df2c9-414a-43ff-a867-ea990e8e9f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30487
52388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3048752388
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.227145631
Short name T302
Test name
Test status
Simulation time 8423247080 ps
CPU time 8.36 seconds
Started Apr 23 02:38:25 PM PDT 24
Finished Apr 23 02:38:34 PM PDT 24
Peak memory 204056 kb
Host smart-7d541503-7ed9-4382-bc85-5a80a373eb25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22714
5631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.227145631
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.2473072689
Short name T797
Test name
Test status
Simulation time 8376679311 ps
CPU time 8.86 seconds
Started Apr 23 02:38:26 PM PDT 24
Finished Apr 23 02:38:35 PM PDT 24
Peak memory 203952 kb
Host smart-9860032d-fd58-401b-b660-6d4f163e67e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24730
72689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.2473072689
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.1992741481
Short name T782
Test name
Test status
Simulation time 8382426395 ps
CPU time 8.79 seconds
Started Apr 23 02:38:24 PM PDT 24
Finished Apr 23 02:38:34 PM PDT 24
Peak memory 204048 kb
Host smart-52bbcc40-3897-4e4f-9983-2150dca4a4b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19927
41481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.1992741481
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1662697624
Short name T145
Test name
Test status
Simulation time 8451562164 ps
CPU time 8 seconds
Started Apr 23 02:38:19 PM PDT 24
Finished Apr 23 02:38:27 PM PDT 24
Peak memory 204024 kb
Host smart-58a5f245-5cab-4549-a50a-44d25f485953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16626
97624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1662697624
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.200861398
Short name T991
Test name
Test status
Simulation time 8369231906 ps
CPU time 8.42 seconds
Started Apr 23 02:38:22 PM PDT 24
Finished Apr 23 02:38:31 PM PDT 24
Peak memory 204016 kb
Host smart-bb07367b-1168-489f-9a61-d9ddbe9d48f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20086
1398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.200861398
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.2340429536
Short name T1027
Test name
Test status
Simulation time 8391989794 ps
CPU time 9.23 seconds
Started Apr 23 02:38:21 PM PDT 24
Finished Apr 23 02:38:31 PM PDT 24
Peak memory 204004 kb
Host smart-3c40814e-156a-41cf-a4e3-cf78eb4a4c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23404
29536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.2340429536
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.749979270
Short name T491
Test name
Test status
Simulation time 8468122037 ps
CPU time 8.25 seconds
Started Apr 23 02:38:26 PM PDT 24
Finished Apr 23 02:38:35 PM PDT 24
Peak memory 204020 kb
Host smart-a46f214e-72be-460f-8e1a-09cbe3896f44
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=749979270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.749979270
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.2061973668
Short name T793
Test name
Test status
Simulation time 8380284782 ps
CPU time 8.23 seconds
Started Apr 23 02:38:27 PM PDT 24
Finished Apr 23 02:38:36 PM PDT 24
Peak memory 203256 kb
Host smart-0879c909-6df5-4ea7-bbeb-03d5b6012c09
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2061973668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.2061973668
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.2207842534
Short name T1237
Test name
Test status
Simulation time 8445758040 ps
CPU time 9.37 seconds
Started Apr 23 02:38:27 PM PDT 24
Finished Apr 23 02:38:37 PM PDT 24
Peak memory 204052 kb
Host smart-247c18b2-ff44-49eb-ba50-8cb2128e551d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22078
42534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.2207842534
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.3727931653
Short name T394
Test name
Test status
Simulation time 8377890486 ps
CPU time 8.02 seconds
Started Apr 23 02:38:24 PM PDT 24
Finished Apr 23 02:38:34 PM PDT 24
Peak memory 204024 kb
Host smart-8a60e78b-6fd0-4a70-81a9-0cf53d28d88f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37279
31653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.3727931653
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_enable.1941568969
Short name T967
Test name
Test status
Simulation time 8384135217 ps
CPU time 9.42 seconds
Started Apr 23 02:38:21 PM PDT 24
Finished Apr 23 02:38:31 PM PDT 24
Peak memory 204064 kb
Host smart-cce6aebe-53ff-4c94-b322-792d2e8ffc60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19415
68969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.1941568969
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.137073713
Short name T53
Test name
Test status
Simulation time 300590501 ps
CPU time 2.28 seconds
Started Apr 23 02:38:22 PM PDT 24
Finished Apr 23 02:38:25 PM PDT 24
Peak memory 204096 kb
Host smart-74bc76a6-b699-4254-b9db-f530463d670d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13707
3713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.137073713
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.3689773216
Short name T530
Test name
Test status
Simulation time 8424286212 ps
CPU time 7.56 seconds
Started Apr 23 02:38:25 PM PDT 24
Finished Apr 23 02:38:33 PM PDT 24
Peak memory 204040 kb
Host smart-938680e6-422a-4f05-8da2-328ad32e4882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36897
73216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.3689773216
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2213522527
Short name T196
Test name
Test status
Simulation time 8368230173 ps
CPU time 8.18 seconds
Started Apr 23 02:38:23 PM PDT 24
Finished Apr 23 02:38:33 PM PDT 24
Peak memory 204028 kb
Host smart-78b8ac8a-2f95-4198-87f9-8cc5f000a9d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22135
22527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2213522527
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3134587839
Short name T1327
Test name
Test status
Simulation time 8393757645 ps
CPU time 10.27 seconds
Started Apr 23 02:38:24 PM PDT 24
Finished Apr 23 02:38:35 PM PDT 24
Peak memory 204060 kb
Host smart-c2cfd17e-2968-456e-8a5a-654d8acc019b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31345
87839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3134587839
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1084730615
Short name T658
Test name
Test status
Simulation time 8413898556 ps
CPU time 7.59 seconds
Started Apr 23 02:38:21 PM PDT 24
Finished Apr 23 02:38:29 PM PDT 24
Peak memory 204044 kb
Host smart-421653f7-62d9-48ae-9c69-135005a44ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10847
30615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1084730615
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3087275132
Short name T295
Test name
Test status
Simulation time 8374700326 ps
CPU time 7.69 seconds
Started Apr 23 02:38:22 PM PDT 24
Finished Apr 23 02:38:30 PM PDT 24
Peak memory 204060 kb
Host smart-a73fc079-146d-45b2-bbec-41ef17c1504b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30872
75132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3087275132
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.4024222648
Short name T124
Test name
Test status
Simulation time 8401017597 ps
CPU time 8.5 seconds
Started Apr 23 02:38:25 PM PDT 24
Finished Apr 23 02:38:34 PM PDT 24
Peak memory 204064 kb
Host smart-02712fb5-bae4-4993-9df4-f290e2552bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40242
22648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.4024222648
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.3719536047
Short name T641
Test name
Test status
Simulation time 8397605470 ps
CPU time 7.77 seconds
Started Apr 23 02:38:23 PM PDT 24
Finished Apr 23 02:38:31 PM PDT 24
Peak memory 203972 kb
Host smart-cf90f465-c5a9-4f5f-8094-4613b3f3d93a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37195
36047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3719536047
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3681632248
Short name T1227
Test name
Test status
Simulation time 8402376414 ps
CPU time 10.31 seconds
Started Apr 23 02:38:23 PM PDT 24
Finished Apr 23 02:38:34 PM PDT 24
Peak memory 203992 kb
Host smart-34e41529-7150-4b88-a55e-8e905e6a28bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36816
32248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3681632248
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.863656492
Short name T54
Test name
Test status
Simulation time 8399381387 ps
CPU time 9.21 seconds
Started Apr 23 02:38:24 PM PDT 24
Finished Apr 23 02:38:34 PM PDT 24
Peak memory 204020 kb
Host smart-ad6ad8a7-661a-480b-b7e4-271c560a19f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86365
6492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.863656492
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.4157787341
Short name T367
Test name
Test status
Simulation time 8367263431 ps
CPU time 8.02 seconds
Started Apr 23 02:38:22 PM PDT 24
Finished Apr 23 02:38:31 PM PDT 24
Peak memory 204008 kb
Host smart-f4cc0235-5944-4aa2-9ca3-b5febc69dc9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41577
87341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.4157787341
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.3923199461
Short name T1345
Test name
Test status
Simulation time 37858032 ps
CPU time 0.64 seconds
Started Apr 23 02:38:28 PM PDT 24
Finished Apr 23 02:38:29 PM PDT 24
Peak memory 203904 kb
Host smart-0ad8348e-1439-41a8-9b76-3c75cfde44c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39231
99461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.3923199461
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.353217508
Short name T221
Test name
Test status
Simulation time 24121885800 ps
CPU time 44.3 seconds
Started Apr 23 02:38:26 PM PDT 24
Finished Apr 23 02:39:11 PM PDT 24
Peak memory 204332 kb
Host smart-aa842f33-c3b3-4729-881e-d7bdea6887ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35321
7508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.353217508
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.1785110937
Short name T680
Test name
Test status
Simulation time 8413903826 ps
CPU time 8.13 seconds
Started Apr 23 02:38:37 PM PDT 24
Finished Apr 23 02:38:45 PM PDT 24
Peak memory 204024 kb
Host smart-d78457f0-5b9d-4bc6-a9aa-889bffa55034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17851
10937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.1785110937
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.525508836
Short name T134
Test name
Test status
Simulation time 8423918789 ps
CPU time 7.64 seconds
Started Apr 23 02:38:28 PM PDT 24
Finished Apr 23 02:38:36 PM PDT 24
Peak memory 204052 kb
Host smart-3695f7f4-559f-46b8-a513-78ee9faa7c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52550
8836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.525508836
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.39577290
Short name T1359
Test name
Test status
Simulation time 8406690279 ps
CPU time 7.81 seconds
Started Apr 23 02:38:26 PM PDT 24
Finished Apr 23 02:38:34 PM PDT 24
Peak memory 204040 kb
Host smart-09f71c70-53d2-4e92-b49d-d770cbf14542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39577
290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.39577290
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.2003428451
Short name T1101
Test name
Test status
Simulation time 8371916888 ps
CPU time 9.01 seconds
Started Apr 23 02:38:27 PM PDT 24
Finished Apr 23 02:38:36 PM PDT 24
Peak memory 204016 kb
Host smart-2cae9443-95d7-429c-a859-3234b76ee97d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20034
28451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.2003428451
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.236761565
Short name T1178
Test name
Test status
Simulation time 8370627328 ps
CPU time 7.46 seconds
Started Apr 23 02:38:25 PM PDT 24
Finished Apr 23 02:38:33 PM PDT 24
Peak memory 204056 kb
Host smart-66e8f165-2196-4455-b58f-19a8f435ae8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23676
1565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.236761565
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.3164305515
Short name T1112
Test name
Test status
Simulation time 8424203651 ps
CPU time 7.75 seconds
Started Apr 23 02:38:24 PM PDT 24
Finished Apr 23 02:38:33 PM PDT 24
Peak memory 204048 kb
Host smart-6dfe672e-6b1a-47e5-8f1c-4a66428b1db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31643
05515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.3164305515
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2333357913
Short name T451
Test name
Test status
Simulation time 8395684774 ps
CPU time 7.62 seconds
Started Apr 23 02:38:24 PM PDT 24
Finished Apr 23 02:38:33 PM PDT 24
Peak memory 204032 kb
Host smart-0b42e8e0-9939-48e8-bb4e-409098da20ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23333
57913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.2333357913
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.3167451432
Short name T1346
Test name
Test status
Simulation time 8388823113 ps
CPU time 8.87 seconds
Started Apr 23 02:38:24 PM PDT 24
Finished Apr 23 02:38:34 PM PDT 24
Peak memory 203980 kb
Host smart-456dc886-e03d-49d0-a2db-f35be3654506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31674
51432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.3167451432
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.max_length_in_transaction.3131023391
Short name T915
Test name
Test status
Simulation time 8461899861 ps
CPU time 8.35 seconds
Started Apr 23 02:38:26 PM PDT 24
Finished Apr 23 02:38:35 PM PDT 24
Peak memory 204064 kb
Host smart-976984f0-8820-4cf0-943a-d4221084d489
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3131023391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.3131023391
Directory /workspace/45.max_length_in_transaction/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.1704904592
Short name T853
Test name
Test status
Simulation time 8382170594 ps
CPU time 8.13 seconds
Started Apr 23 02:38:26 PM PDT 24
Finished Apr 23 02:38:35 PM PDT 24
Peak memory 204024 kb
Host smart-6769b8ae-dce7-4bf8-8a4f-9291cf318961
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1704904592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.1704904592
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.random_length_in_trans.2711612064
Short name T843
Test name
Test status
Simulation time 8395709218 ps
CPU time 8.2 seconds
Started Apr 23 02:38:46 PM PDT 24
Finished Apr 23 02:38:55 PM PDT 24
Peak memory 204040 kb
Host smart-d21185d4-0748-42d0-a6ff-e7042f2f70a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27116
12064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.2711612064
Directory /workspace/45.random_length_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.961729327
Short name T689
Test name
Test status
Simulation time 8375509466 ps
CPU time 7.77 seconds
Started Apr 23 02:38:24 PM PDT 24
Finished Apr 23 02:38:33 PM PDT 24
Peak memory 204016 kb
Host smart-19befec6-5a91-4924-b3ac-651df328354d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96172
9327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.961729327
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_enable.1596707413
Short name T1278
Test name
Test status
Simulation time 8428507761 ps
CPU time 7.41 seconds
Started Apr 23 02:38:25 PM PDT 24
Finished Apr 23 02:38:33 PM PDT 24
Peak memory 204064 kb
Host smart-240dbae4-ecd4-4228-beb8-f012cbdf5961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15967
07413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.1596707413
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.3139495852
Short name T214
Test name
Test status
Simulation time 47651597 ps
CPU time 1.18 seconds
Started Apr 23 02:38:25 PM PDT 24
Finished Apr 23 02:38:27 PM PDT 24
Peak memory 203720 kb
Host smart-eb44b119-c632-4e0e-8cfa-97d92f7819d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31394
95852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.3139495852
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.3328529718
Short name T681
Test name
Test status
Simulation time 8443910498 ps
CPU time 8.23 seconds
Started Apr 23 02:38:36 PM PDT 24
Finished Apr 23 02:38:44 PM PDT 24
Peak memory 204012 kb
Host smart-94bc3703-189e-415f-9e2b-d59935e575ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33285
29718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.3328529718
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.2489100175
Short name T194
Test name
Test status
Simulation time 8365881622 ps
CPU time 9.36 seconds
Started Apr 23 02:38:25 PM PDT 24
Finished Apr 23 02:38:35 PM PDT 24
Peak memory 204032 kb
Host smart-4ab09944-6ace-4637-b1cd-07ff6d1bf69d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24891
00175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.2489100175
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.3272628525
Short name T761
Test name
Test status
Simulation time 8455451983 ps
CPU time 8.06 seconds
Started Apr 23 02:38:27 PM PDT 24
Finished Apr 23 02:38:35 PM PDT 24
Peak memory 204052 kb
Host smart-dda72e6f-f6af-4f52-82ef-0f457f8887f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32726
28525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3272628525
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.3789066052
Short name T375
Test name
Test status
Simulation time 8420525108 ps
CPU time 9.84 seconds
Started Apr 23 02:38:28 PM PDT 24
Finished Apr 23 02:38:39 PM PDT 24
Peak memory 204056 kb
Host smart-a7223640-98ec-4ef8-95af-e2777495e627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37890
66052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.3789066052
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.3526492242
Short name T1144
Test name
Test status
Simulation time 8372818551 ps
CPU time 9.51 seconds
Started Apr 23 02:38:34 PM PDT 24
Finished Apr 23 02:38:44 PM PDT 24
Peak memory 203992 kb
Host smart-99a2f676-9320-42cd-a013-c02eb49c8be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35264
92242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.3526492242
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.464751405
Short name T118
Test name
Test status
Simulation time 8419404258 ps
CPU time 9.05 seconds
Started Apr 23 02:38:25 PM PDT 24
Finished Apr 23 02:38:35 PM PDT 24
Peak memory 204056 kb
Host smart-ec5f1d47-532d-43ca-83dd-20675843b573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46475
1405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.464751405
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.2163664347
Short name T342
Test name
Test status
Simulation time 8395303895 ps
CPU time 9.41 seconds
Started Apr 23 02:38:27 PM PDT 24
Finished Apr 23 02:38:37 PM PDT 24
Peak memory 204012 kb
Host smart-62969ea3-3e90-4a1c-923b-4af1d5591060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21636
64347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.2163664347
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3507602106
Short name T877
Test name
Test status
Simulation time 8398572403 ps
CPU time 8.54 seconds
Started Apr 23 02:38:44 PM PDT 24
Finished Apr 23 02:38:54 PM PDT 24
Peak memory 204044 kb
Host smart-50ad74a2-edcb-4cd4-a494-222e803d7bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35076
02106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3507602106
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.3870388511
Short name T170
Test name
Test status
Simulation time 8400361022 ps
CPU time 7.81 seconds
Started Apr 23 02:38:36 PM PDT 24
Finished Apr 23 02:38:44 PM PDT 24
Peak memory 203992 kb
Host smart-98828546-0e4f-4f65-8974-ca0477253955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38703
88511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.3870388511
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.1800475014
Short name T1096
Test name
Test status
Simulation time 8372322874 ps
CPU time 7.86 seconds
Started Apr 23 02:38:27 PM PDT 24
Finished Apr 23 02:38:36 PM PDT 24
Peak memory 203428 kb
Host smart-33596c4e-57c7-4a63-aeb2-4b8a69669abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18004
75014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.1800475014
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.3506155521
Short name T45
Test name
Test status
Simulation time 36993261 ps
CPU time 0.63 seconds
Started Apr 23 02:38:26 PM PDT 24
Finished Apr 23 02:38:28 PM PDT 24
Peak memory 203900 kb
Host smart-5d02380c-a70b-49a6-a567-16383d80015c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35061
55521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.3506155521
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.4003530815
Short name T1058
Test name
Test status
Simulation time 29050781086 ps
CPU time 55.3 seconds
Started Apr 23 02:38:37 PM PDT 24
Finished Apr 23 02:39:32 PM PDT 24
Peak memory 204300 kb
Host smart-d4ac1e93-deb3-447f-9865-cc8942fce20b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40035
30815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.4003530815
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.1711277299
Short name T357
Test name
Test status
Simulation time 8385613015 ps
CPU time 7.9 seconds
Started Apr 23 02:38:45 PM PDT 24
Finished Apr 23 02:38:54 PM PDT 24
Peak memory 204008 kb
Host smart-01efcafc-d2c5-4bb6-8d56-6106837b759f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17112
77299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.1711277299
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.4004703599
Short name T729
Test name
Test status
Simulation time 8449465904 ps
CPU time 8.33 seconds
Started Apr 23 02:38:34 PM PDT 24
Finished Apr 23 02:38:42 PM PDT 24
Peak memory 204012 kb
Host smart-6098db19-205b-442d-8b9a-91f113392879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40047
03599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.4004703599
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.3565783799
Short name T1082
Test name
Test status
Simulation time 8445488215 ps
CPU time 9.49 seconds
Started Apr 23 02:38:40 PM PDT 24
Finished Apr 23 02:38:50 PM PDT 24
Peak memory 204044 kb
Host smart-ab32a440-8e08-4aa6-8413-ef9220baaabf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35657
83799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.3565783799
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.592547183
Short name T692
Test name
Test status
Simulation time 8375339038 ps
CPU time 9.96 seconds
Started Apr 23 02:38:27 PM PDT 24
Finished Apr 23 02:38:38 PM PDT 24
Peak memory 203956 kb
Host smart-3e7b7b1f-865c-4285-ac18-65d42868f397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59254
7183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.592547183
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.1175510678
Short name T540
Test name
Test status
Simulation time 8370759106 ps
CPU time 8.47 seconds
Started Apr 23 02:38:50 PM PDT 24
Finished Apr 23 02:38:59 PM PDT 24
Peak memory 204040 kb
Host smart-f042435a-b544-476b-a874-53111b0e134b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11755
10678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.1175510678
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.2840555157
Short name T86
Test name
Test status
Simulation time 8480275437 ps
CPU time 8.7 seconds
Started Apr 23 02:38:23 PM PDT 24
Finished Apr 23 02:38:32 PM PDT 24
Peak memory 204032 kb
Host smart-becb5d37-094f-4854-8deb-a6f325df2a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28405
55157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.2840555157
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.410300858
Short name T1371
Test name
Test status
Simulation time 8375140755 ps
CPU time 7.61 seconds
Started Apr 23 02:38:29 PM PDT 24
Finished Apr 23 02:38:37 PM PDT 24
Peak memory 204052 kb
Host smart-541e1b3c-ab1d-4f4f-bf69-488076b188b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41030
0858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.410300858
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.1470025570
Short name T1337
Test name
Test status
Simulation time 8389626976 ps
CPU time 8.09 seconds
Started Apr 23 02:38:35 PM PDT 24
Finished Apr 23 02:38:43 PM PDT 24
Peak memory 203988 kb
Host smart-40435132-e5a0-40db-b50a-7cb5649f7842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14700
25570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.1470025570
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.3313264014
Short name T543
Test name
Test status
Simulation time 8497554767 ps
CPU time 8.12 seconds
Started Apr 23 02:38:47 PM PDT 24
Finished Apr 23 02:38:56 PM PDT 24
Peak memory 203960 kb
Host smart-f61ab782-c946-478a-bbc1-9048a94829a9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3313264014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.3313264014
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.1009727615
Short name T1323
Test name
Test status
Simulation time 8386810964 ps
CPU time 7.82 seconds
Started Apr 23 02:38:37 PM PDT 24
Finished Apr 23 02:38:46 PM PDT 24
Peak memory 203996 kb
Host smart-bf047565-48f8-49fb-a273-6b74e95a426f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1009727615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.1009727615
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.3743016242
Short name T1042
Test name
Test status
Simulation time 8415675895 ps
CPU time 9.16 seconds
Started Apr 23 02:38:30 PM PDT 24
Finished Apr 23 02:38:40 PM PDT 24
Peak memory 204000 kb
Host smart-39aeec8c-c393-408a-a810-751bb5be26d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37430
16242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.3743016242
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.1757328069
Short name T694
Test name
Test status
Simulation time 8381076120 ps
CPU time 7.79 seconds
Started Apr 23 02:38:52 PM PDT 24
Finished Apr 23 02:39:00 PM PDT 24
Peak memory 203968 kb
Host smart-7211ac3d-0309-47dd-a8b6-04d97eb95f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17573
28069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.1757328069
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_enable.2861069510
Short name T1033
Test name
Test status
Simulation time 8392934269 ps
CPU time 7.67 seconds
Started Apr 23 02:38:35 PM PDT 24
Finished Apr 23 02:38:43 PM PDT 24
Peak memory 204016 kb
Host smart-57d76153-5201-4d42-be1a-66dfa759e242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28610
69510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2861069510
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.3631576448
Short name T813
Test name
Test status
Simulation time 251538733 ps
CPU time 1.94 seconds
Started Apr 23 02:38:40 PM PDT 24
Finished Apr 23 02:38:43 PM PDT 24
Peak memory 204148 kb
Host smart-fe18c094-0954-4a16-977f-cffe1a04124c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36315
76448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.3631576448
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.4147099185
Short name T411
Test name
Test status
Simulation time 8449597599 ps
CPU time 8.28 seconds
Started Apr 23 02:38:46 PM PDT 24
Finished Apr 23 02:38:55 PM PDT 24
Peak memory 203968 kb
Host smart-932af3b3-ebff-44d9-85b1-fda23e95ac38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41470
99185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.4147099185
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3573039756
Short name T1081
Test name
Test status
Simulation time 8367967185 ps
CPU time 8.82 seconds
Started Apr 23 02:38:29 PM PDT 24
Finished Apr 23 02:38:39 PM PDT 24
Peak memory 203992 kb
Host smart-9fa8bf5b-74bd-499a-bd89-dac3ed2e922c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35730
39756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3573039756
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.4241284925
Short name T1134
Test name
Test status
Simulation time 8447233927 ps
CPU time 8.21 seconds
Started Apr 23 02:38:46 PM PDT 24
Finished Apr 23 02:38:55 PM PDT 24
Peak memory 203968 kb
Host smart-2f7087b7-4569-488d-985e-26090648b158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42412
84925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.4241284925
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.1000515043
Short name T1315
Test name
Test status
Simulation time 8415001130 ps
CPU time 7.93 seconds
Started Apr 23 02:38:41 PM PDT 24
Finished Apr 23 02:38:50 PM PDT 24
Peak memory 204044 kb
Host smart-592615b7-77e9-4987-a442-a594743d7c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10005
15043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.1000515043
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.2663638056
Short name T815
Test name
Test status
Simulation time 8369983254 ps
CPU time 8.1 seconds
Started Apr 23 02:38:47 PM PDT 24
Finished Apr 23 02:38:56 PM PDT 24
Peak memory 204016 kb
Host smart-517d7e82-ba9f-4547-a755-219cdc0d5a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26636
38056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.2663638056
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.4235373095
Short name T992
Test name
Test status
Simulation time 8493615235 ps
CPU time 8.34 seconds
Started Apr 23 02:38:30 PM PDT 24
Finished Apr 23 02:38:39 PM PDT 24
Peak memory 203968 kb
Host smart-219bfc43-84d0-41b6-9710-cff6e6947ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42353
73095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.4235373095
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.3483911489
Short name T349
Test name
Test status
Simulation time 8434594324 ps
CPU time 9.63 seconds
Started Apr 23 02:38:50 PM PDT 24
Finished Apr 23 02:39:00 PM PDT 24
Peak memory 203964 kb
Host smart-b8a0d68e-d739-4961-ae24-ff50ab0fcbf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34839
11489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.3483911489
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.1057758347
Short name T564
Test name
Test status
Simulation time 8412830829 ps
CPU time 7.88 seconds
Started Apr 23 02:38:39 PM PDT 24
Finished Apr 23 02:38:47 PM PDT 24
Peak memory 204020 kb
Host smart-5243fa24-9259-4091-9622-5470604d2d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10577
58347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.1057758347
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.1475904742
Short name T181
Test name
Test status
Simulation time 8397927003 ps
CPU time 7.88 seconds
Started Apr 23 02:38:30 PM PDT 24
Finished Apr 23 02:38:39 PM PDT 24
Peak memory 204012 kb
Host smart-7a605138-9476-4122-a910-bb595aa84702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14759
04742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.1475904742
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.684719160
Short name T377
Test name
Test status
Simulation time 8374601210 ps
CPU time 7.66 seconds
Started Apr 23 02:38:32 PM PDT 24
Finished Apr 23 02:38:40 PM PDT 24
Peak memory 204040 kb
Host smart-1256fd93-fa73-4edc-96e6-360045e6b29d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68471
9160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.684719160
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.361545423
Short name T1143
Test name
Test status
Simulation time 42236742 ps
CPU time 0.65 seconds
Started Apr 23 02:38:46 PM PDT 24
Finished Apr 23 02:38:47 PM PDT 24
Peak memory 203832 kb
Host smart-9ecec481-dfca-4e55-aed4-1b757ea017c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36154
5423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.361545423
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.455472648
Short name T789
Test name
Test status
Simulation time 14710660139 ps
CPU time 26.62 seconds
Started Apr 23 02:38:32 PM PDT 24
Finished Apr 23 02:38:59 PM PDT 24
Peak memory 204332 kb
Host smart-3df4d90d-5cd4-4c24-a67d-a73ac2392cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45547
2648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.455472648
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.1518214276
Short name T398
Test name
Test status
Simulation time 8378248199 ps
CPU time 8.09 seconds
Started Apr 23 02:38:29 PM PDT 24
Finished Apr 23 02:38:37 PM PDT 24
Peak memory 203988 kb
Host smart-6775df55-2038-4933-9f39-54a68b2c971d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15182
14276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.1518214276
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.543649460
Short name T1088
Test name
Test status
Simulation time 8457094564 ps
CPU time 8.36 seconds
Started Apr 23 02:38:30 PM PDT 24
Finished Apr 23 02:38:39 PM PDT 24
Peak memory 204024 kb
Host smart-414556c4-90d1-4813-a53a-3989fe4a2d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54364
9460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.543649460
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.1095223598
Short name T36
Test name
Test status
Simulation time 8387860287 ps
CPU time 7.68 seconds
Started Apr 23 02:38:30 PM PDT 24
Finished Apr 23 02:38:38 PM PDT 24
Peak memory 204028 kb
Host smart-4f597e3b-3933-4b3b-a599-13dc0c354ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10952
23598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.1095223598
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.1842095177
Short name T1187
Test name
Test status
Simulation time 8375973019 ps
CPU time 8.01 seconds
Started Apr 23 02:38:31 PM PDT 24
Finished Apr 23 02:38:39 PM PDT 24
Peak memory 203952 kb
Host smart-a9c9d072-4eee-4008-a5bb-379fe4bd7dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18420
95177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.1842095177
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.3351959521
Short name T662
Test name
Test status
Simulation time 8371586391 ps
CPU time 9.17 seconds
Started Apr 23 02:38:43 PM PDT 24
Finished Apr 23 02:38:52 PM PDT 24
Peak memory 204012 kb
Host smart-6e11cfa7-451d-4f7f-ae53-25a3c02a2aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33519
59521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.3351959521
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.4142561865
Short name T135
Test name
Test status
Simulation time 8465158288 ps
CPU time 8.09 seconds
Started Apr 23 02:38:31 PM PDT 24
Finished Apr 23 02:38:39 PM PDT 24
Peak memory 203960 kb
Host smart-a911f0c2-24c4-4c24-9ca1-4b4dabf069f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41425
61865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.4142561865
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.2688049861
Short name T128
Test name
Test status
Simulation time 8418021291 ps
CPU time 7.65 seconds
Started Apr 23 02:38:32 PM PDT 24
Finished Apr 23 02:38:40 PM PDT 24
Peak memory 204020 kb
Host smart-70433ab9-4290-41ff-846a-b5f1df96930b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26880
49861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.2688049861
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.3967666947
Short name T1190
Test name
Test status
Simulation time 8406660032 ps
CPU time 7.78 seconds
Started Apr 23 02:38:31 PM PDT 24
Finished Apr 23 02:38:39 PM PDT 24
Peak memory 204000 kb
Host smart-e9187caa-a75e-426c-a2de-ea2003571506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39676
66947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.3967666947
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.449135316
Short name T601
Test name
Test status
Simulation time 8482283865 ps
CPU time 8.88 seconds
Started Apr 23 02:38:46 PM PDT 24
Finished Apr 23 02:38:55 PM PDT 24
Peak memory 203356 kb
Host smart-a8fd7534-6615-4081-9556-71de566150fd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=449135316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.449135316
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.2927014624
Short name T418
Test name
Test status
Simulation time 8386195140 ps
CPU time 8.95 seconds
Started Apr 23 02:38:42 PM PDT 24
Finished Apr 23 02:38:51 PM PDT 24
Peak memory 204012 kb
Host smart-d1a0a6fc-db8c-4ccd-b771-caeecbaaecf6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2927014624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.2927014624
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.2198349805
Short name T1148
Test name
Test status
Simulation time 8411420532 ps
CPU time 9.38 seconds
Started Apr 23 02:38:41 PM PDT 24
Finished Apr 23 02:38:51 PM PDT 24
Peak memory 204024 kb
Host smart-57a0eb14-7f7a-4bac-8932-2b5f3de71d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21983
49805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.2198349805
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2152796962
Short name T798
Test name
Test status
Simulation time 8383591175 ps
CPU time 7.86 seconds
Started Apr 23 02:38:33 PM PDT 24
Finished Apr 23 02:38:41 PM PDT 24
Peak memory 203956 kb
Host smart-f3664e6c-363b-42cb-a948-48dbd522ef1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21527
96962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2152796962
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_enable.2913458755
Short name T503
Test name
Test status
Simulation time 8374079192 ps
CPU time 9.05 seconds
Started Apr 23 02:38:35 PM PDT 24
Finished Apr 23 02:38:45 PM PDT 24
Peak memory 204020 kb
Host smart-345b7c04-9417-411b-bdff-8f3bb5f6ea1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29134
58755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2913458755
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3678802974
Short name T578
Test name
Test status
Simulation time 128024836 ps
CPU time 1.27 seconds
Started Apr 23 02:38:43 PM PDT 24
Finished Apr 23 02:38:45 PM PDT 24
Peak memory 204104 kb
Host smart-be950ae3-fc3f-4504-8092-5cabc9e004df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36788
02974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3678802974
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.2510676264
Short name T1034
Test name
Test status
Simulation time 8418803229 ps
CPU time 10.4 seconds
Started Apr 23 02:38:49 PM PDT 24
Finished Apr 23 02:39:00 PM PDT 24
Peak memory 204012 kb
Host smart-5756aeab-083d-4a05-8d84-a27985729752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25106
76264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.2510676264
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.1636224502
Short name T187
Test name
Test status
Simulation time 8364103739 ps
CPU time 8.15 seconds
Started Apr 23 02:38:41 PM PDT 24
Finished Apr 23 02:38:50 PM PDT 24
Peak memory 204036 kb
Host smart-25ad2796-240d-485a-8cdf-9253afcd217e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16362
24502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.1636224502
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.3182413722
Short name T1197
Test name
Test status
Simulation time 8430460080 ps
CPU time 9.85 seconds
Started Apr 23 02:38:37 PM PDT 24
Finished Apr 23 02:38:47 PM PDT 24
Peak memory 204004 kb
Host smart-e84d4fce-36c9-417a-a7a5-4f34c190aeb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31824
13722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.3182413722
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.2073568249
Short name T360
Test name
Test status
Simulation time 8444632086 ps
CPU time 7.79 seconds
Started Apr 23 02:38:44 PM PDT 24
Finished Apr 23 02:38:52 PM PDT 24
Peak memory 203996 kb
Host smart-5315cda6-23e1-4df9-a90e-4d3be820a566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20735
68249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.2073568249
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.1379307272
Short name T263
Test name
Test status
Simulation time 8374620394 ps
CPU time 7.81 seconds
Started Apr 23 02:38:42 PM PDT 24
Finished Apr 23 02:38:50 PM PDT 24
Peak memory 203984 kb
Host smart-ffc645e9-1b50-49e5-ade4-7b01b6ee6547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13793
07272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.1379307272
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.2042560594
Short name T105
Test name
Test status
Simulation time 8394431280 ps
CPU time 10.26 seconds
Started Apr 23 02:38:43 PM PDT 24
Finished Apr 23 02:38:54 PM PDT 24
Peak memory 204048 kb
Host smart-ba64bdaa-ab67-49a2-ae20-6f0bd3f10a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20425
60594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.2042560594
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.2213397636
Short name T730
Test name
Test status
Simulation time 8389879660 ps
CPU time 7.86 seconds
Started Apr 23 02:38:37 PM PDT 24
Finished Apr 23 02:38:45 PM PDT 24
Peak memory 203984 kb
Host smart-ef7f1e9f-53ce-4284-8991-f1c2cb10ccab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22133
97636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.2213397636
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.144266155
Short name T1247
Test name
Test status
Simulation time 8422545208 ps
CPU time 8.53 seconds
Started Apr 23 02:38:36 PM PDT 24
Finished Apr 23 02:38:45 PM PDT 24
Peak memory 204076 kb
Host smart-78a5c276-0b5c-4969-964e-6041eeefc542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14426
6155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.144266155
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.397849725
Short name T630
Test name
Test status
Simulation time 8404241688 ps
CPU time 10.44 seconds
Started Apr 23 02:38:49 PM PDT 24
Finished Apr 23 02:39:00 PM PDT 24
Peak memory 204044 kb
Host smart-e38a3bf1-4054-49ad-a536-c15f2496c4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39784
9725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.397849725
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.4110646040
Short name T493
Test name
Test status
Simulation time 8425860352 ps
CPU time 10.12 seconds
Started Apr 23 02:38:45 PM PDT 24
Finished Apr 23 02:38:55 PM PDT 24
Peak memory 204016 kb
Host smart-a908e3c1-9c8c-41b1-9c57-37f378659829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41106
46040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.4110646040
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.3779014877
Short name T756
Test name
Test status
Simulation time 48768743 ps
CPU time 0.67 seconds
Started Apr 23 02:38:39 PM PDT 24
Finished Apr 23 02:38:40 PM PDT 24
Peak memory 203900 kb
Host smart-3a9b1a9b-be94-449b-8066-6f8d947d2799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37790
14877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.3779014877
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.2473053883
Short name T1126
Test name
Test status
Simulation time 28859156609 ps
CPU time 60.28 seconds
Started Apr 23 02:38:49 PM PDT 24
Finished Apr 23 02:39:50 PM PDT 24
Peak memory 204308 kb
Host smart-82f68982-9fce-4da1-bd1d-5a9b8abb52df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24730
53883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.2473053883
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.2616562095
Short name T714
Test name
Test status
Simulation time 8392718334 ps
CPU time 9.51 seconds
Started Apr 23 02:38:50 PM PDT 24
Finished Apr 23 02:39:00 PM PDT 24
Peak memory 204044 kb
Host smart-a2f28045-845e-4b57-b0ad-b17503222e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26165
62095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.2616562095
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.3126784012
Short name T138
Test name
Test status
Simulation time 8441269143 ps
CPU time 10.45 seconds
Started Apr 23 02:38:37 PM PDT 24
Finished Apr 23 02:38:48 PM PDT 24
Peak memory 203980 kb
Host smart-8a0398f0-5a26-409c-b927-5cec6c5d8dd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31267
84012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3126784012
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.731985219
Short name T1241
Test name
Test status
Simulation time 8408748200 ps
CPU time 8.31 seconds
Started Apr 23 02:38:39 PM PDT 24
Finished Apr 23 02:38:47 PM PDT 24
Peak memory 204004 kb
Host smart-d1c3d58d-faf1-4cad-87d9-1cf331e34840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73198
5219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.731985219
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.2239453595
Short name T1098
Test name
Test status
Simulation time 8376572639 ps
CPU time 8.15 seconds
Started Apr 23 02:38:45 PM PDT 24
Finished Apr 23 02:38:53 PM PDT 24
Peak memory 203792 kb
Host smart-e1056bb4-6eea-47fa-9f10-dd9dd032f365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22394
53595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.2239453595
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.991888148
Short name T673
Test name
Test status
Simulation time 8374803417 ps
CPU time 8.16 seconds
Started Apr 23 02:38:43 PM PDT 24
Finished Apr 23 02:38:52 PM PDT 24
Peak memory 203984 kb
Host smart-682e6bca-ff5c-4f59-9c87-1f91150cb8bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99188
8148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.991888148
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.1520696819
Short name T514
Test name
Test status
Simulation time 8451993811 ps
CPU time 8.81 seconds
Started Apr 23 02:38:50 PM PDT 24
Finished Apr 23 02:39:00 PM PDT 24
Peak memory 204032 kb
Host smart-a3977bc5-5ddd-42af-b1fc-99b72e3e8bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15206
96819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1520696819
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.2910225312
Short name T428
Test name
Test status
Simulation time 8413525309 ps
CPU time 7.74 seconds
Started Apr 23 02:38:38 PM PDT 24
Finished Apr 23 02:38:47 PM PDT 24
Peak memory 203980 kb
Host smart-cde58e83-9cff-4356-bc40-d8865c2db6b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29102
25312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.2910225312
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.2388011837
Short name T774
Test name
Test status
Simulation time 8413287169 ps
CPU time 7.78 seconds
Started Apr 23 02:38:54 PM PDT 24
Finished Apr 23 02:39:02 PM PDT 24
Peak memory 204016 kb
Host smart-c06cd91a-3976-4d8b-b27d-452d7925b169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23880
11837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2388011837
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.3630782997
Short name T379
Test name
Test status
Simulation time 8465222586 ps
CPU time 8.6 seconds
Started Apr 23 02:38:47 PM PDT 24
Finished Apr 23 02:38:56 PM PDT 24
Peak memory 204024 kb
Host smart-40b63ffc-67af-44c7-883b-e5ef10bd129e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3630782997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.3630782997
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.873271309
Short name T721
Test name
Test status
Simulation time 8387562296 ps
CPU time 8.38 seconds
Started Apr 23 02:38:44 PM PDT 24
Finished Apr 23 02:38:53 PM PDT 24
Peak memory 203996 kb
Host smart-8e4ad382-81fd-4468-80f8-303c725ae7db
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=873271309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.873271309
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.2776791663
Short name T593
Test name
Test status
Simulation time 8414713719 ps
CPU time 7.41 seconds
Started Apr 23 02:38:40 PM PDT 24
Finished Apr 23 02:38:48 PM PDT 24
Peak memory 204092 kb
Host smart-48002e35-3d4d-4405-863d-8a7b2ac50996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27767
91663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.2776791663
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1887453988
Short name T668
Test name
Test status
Simulation time 8391055922 ps
CPU time 8.17 seconds
Started Apr 23 02:38:50 PM PDT 24
Finished Apr 23 02:38:59 PM PDT 24
Peak memory 204044 kb
Host smart-6ff57b6c-afd3-438d-afa8-71d694082ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18874
53988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1887453988
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_enable.2352279864
Short name T1232
Test name
Test status
Simulation time 8375937642 ps
CPU time 8.13 seconds
Started Apr 23 02:38:39 PM PDT 24
Finished Apr 23 02:38:47 PM PDT 24
Peak memory 204008 kb
Host smart-376a4322-2488-49e1-916d-0a1a57774f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23522
79864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.2352279864
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.1289883045
Short name T1284
Test name
Test status
Simulation time 154575895 ps
CPU time 1.41 seconds
Started Apr 23 02:38:51 PM PDT 24
Finished Apr 23 02:38:53 PM PDT 24
Peak memory 204140 kb
Host smart-935c4481-7cab-4cd7-9459-0e0ff73d4771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12898
83045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.1289883045
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.1978009937
Short name T150
Test name
Test status
Simulation time 8475327206 ps
CPU time 10.22 seconds
Started Apr 23 02:38:48 PM PDT 24
Finished Apr 23 02:38:58 PM PDT 24
Peak memory 204012 kb
Host smart-3a1fcc90-daa7-4c61-9220-392e49e2544a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19780
09937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.1978009937
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.715235025
Short name T199
Test name
Test status
Simulation time 8389192045 ps
CPU time 9.99 seconds
Started Apr 23 02:38:53 PM PDT 24
Finished Apr 23 02:39:04 PM PDT 24
Peak memory 204024 kb
Host smart-0b6ba06d-7ebd-4025-add8-c7e36d64299a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71523
5025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.715235025
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.311584656
Short name T1349
Test name
Test status
Simulation time 8420638606 ps
CPU time 8.24 seconds
Started Apr 23 02:38:45 PM PDT 24
Finished Apr 23 02:38:54 PM PDT 24
Peak memory 203360 kb
Host smart-cff0a22c-53ee-459a-860e-11969481422d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31158
4656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.311584656
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.240426079
Short name T1113
Test name
Test status
Simulation time 8416196971 ps
CPU time 9.66 seconds
Started Apr 23 02:38:56 PM PDT 24
Finished Apr 23 02:39:06 PM PDT 24
Peak memory 204056 kb
Host smart-5a275ca1-f2c7-4b0c-af5e-955bccdfd5a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24042
6079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.240426079
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.1011675929
Short name T373
Test name
Test status
Simulation time 8377530979 ps
CPU time 8.03 seconds
Started Apr 23 02:38:49 PM PDT 24
Finished Apr 23 02:38:58 PM PDT 24
Peak memory 204048 kb
Host smart-aa65fa02-88f2-4da6-b77c-35eb70b68fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10116
75929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.1011675929
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.304745869
Short name T107
Test name
Test status
Simulation time 8414208320 ps
CPU time 8.39 seconds
Started Apr 23 02:38:49 PM PDT 24
Finished Apr 23 02:38:59 PM PDT 24
Peak memory 204060 kb
Host smart-1c69a11c-f181-4454-846d-895867ac50a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30474
5869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.304745869
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3894651307
Short name T391
Test name
Test status
Simulation time 8379112951 ps
CPU time 8.35 seconds
Started Apr 23 02:38:45 PM PDT 24
Finished Apr 23 02:38:53 PM PDT 24
Peak memory 204100 kb
Host smart-76ffeaf1-7fcc-458c-9106-1fb3463a9305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38946
51307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3894651307
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.3179811638
Short name T677
Test name
Test status
Simulation time 8411419458 ps
CPU time 8.3 seconds
Started Apr 23 02:38:40 PM PDT 24
Finished Apr 23 02:38:48 PM PDT 24
Peak memory 203984 kb
Host smart-581b5b88-b0c1-4d67-b18e-c2125e208e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31798
11638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.3179811638
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.2829028355
Short name T165
Test name
Test status
Simulation time 8366992884 ps
CPU time 8 seconds
Started Apr 23 02:38:51 PM PDT 24
Finished Apr 23 02:39:00 PM PDT 24
Peak memory 204060 kb
Host smart-c1e0a37a-f1a0-442f-a9ab-0801012e97c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28290
28355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.2829028355
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.2361028558
Short name T666
Test name
Test status
Simulation time 8394875838 ps
CPU time 9.57 seconds
Started Apr 23 02:38:45 PM PDT 24
Finished Apr 23 02:38:55 PM PDT 24
Peak memory 204052 kb
Host smart-daf2a422-4c13-4153-bc90-e57d7ccf25e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23610
28558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.2361028558
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.3281859173
Short name T222
Test name
Test status
Simulation time 14681048213 ps
CPU time 25.99 seconds
Started Apr 23 02:38:43 PM PDT 24
Finished Apr 23 02:39:10 PM PDT 24
Peak memory 204348 kb
Host smart-7e40aa16-6a5d-404f-8cf0-4baa816c7747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32818
59173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.3281859173
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.2755701052
Short name T881
Test name
Test status
Simulation time 8389061886 ps
CPU time 7.4 seconds
Started Apr 23 02:38:45 PM PDT 24
Finished Apr 23 02:38:53 PM PDT 24
Peak memory 203732 kb
Host smart-27ee8ec2-ff40-4a06-9b51-fbe2e27303ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27557
01052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2755701052
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.2376095149
Short name T1195
Test name
Test status
Simulation time 8426943080 ps
CPU time 10.16 seconds
Started Apr 23 02:38:37 PM PDT 24
Finished Apr 23 02:38:48 PM PDT 24
Peak memory 204016 kb
Host smart-0d9336fa-693b-47b6-ad2b-b57886b7fb0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23760
95149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.2376095149
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.3011444897
Short name T724
Test name
Test status
Simulation time 8392202889 ps
CPU time 8.5 seconds
Started Apr 23 02:38:42 PM PDT 24
Finished Apr 23 02:38:51 PM PDT 24
Peak memory 204024 kb
Host smart-8bb90c8f-ae83-4982-8c41-5ae4b142bc75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30114
44897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.3011444897
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.281976658
Short name T661
Test name
Test status
Simulation time 8383599513 ps
CPU time 9.69 seconds
Started Apr 23 02:38:56 PM PDT 24
Finished Apr 23 02:39:07 PM PDT 24
Peak memory 203964 kb
Host smart-30c1c7d6-a14a-4f56-aae7-661503920588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28197
6658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.281976658
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.3859498285
Short name T720
Test name
Test status
Simulation time 8373538615 ps
CPU time 7.55 seconds
Started Apr 23 02:38:45 PM PDT 24
Finished Apr 23 02:38:53 PM PDT 24
Peak memory 203348 kb
Host smart-f94f5733-7b4d-4b3d-9b5f-7f72920c6d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38594
98285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.3859498285
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.117287482
Short name T1117
Test name
Test status
Simulation time 8440443597 ps
CPU time 9.95 seconds
Started Apr 23 02:38:44 PM PDT 24
Finished Apr 23 02:38:55 PM PDT 24
Peak memory 204044 kb
Host smart-2705004c-1561-4a6b-87ed-77a4752dbb89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11728
7482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.117287482
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.850979237
Short name T328
Test name
Test status
Simulation time 8379773485 ps
CPU time 8.2 seconds
Started Apr 23 02:38:49 PM PDT 24
Finished Apr 23 02:38:58 PM PDT 24
Peak memory 204040 kb
Host smart-69855944-10bc-43ec-a192-0f6f26c5c32a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85097
9237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.850979237
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.483641525
Short name T1311
Test name
Test status
Simulation time 8419537026 ps
CPU time 8.12 seconds
Started Apr 23 02:38:44 PM PDT 24
Finished Apr 23 02:38:53 PM PDT 24
Peak memory 204096 kb
Host smart-0faeea85-194e-49a1-86a5-90f2c62fe51f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48364
1525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.483641525
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.2127853845
Short name T1124
Test name
Test status
Simulation time 8482405581 ps
CPU time 8.6 seconds
Started Apr 23 02:38:47 PM PDT 24
Finished Apr 23 02:38:56 PM PDT 24
Peak memory 203976 kb
Host smart-59423768-689f-4cf9-8ec2-04433f56a1fc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2127853845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.2127853845
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.141086808
Short name T454
Test name
Test status
Simulation time 8398294534 ps
CPU time 7.83 seconds
Started Apr 23 02:38:51 PM PDT 24
Finished Apr 23 02:38:59 PM PDT 24
Peak memory 203996 kb
Host smart-f4c9ccfd-8d39-46d6-a11b-556fe0ab1861
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=141086808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.141086808
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.3939553768
Short name T152
Test name
Test status
Simulation time 8462516564 ps
CPU time 7.87 seconds
Started Apr 23 02:38:59 PM PDT 24
Finished Apr 23 02:39:08 PM PDT 24
Peak memory 204044 kb
Host smart-64eec3f8-4650-4422-8651-49928dac7fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39395
53768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.3939553768
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.1086561232
Short name T1348
Test name
Test status
Simulation time 8381347234 ps
CPU time 8.77 seconds
Started Apr 23 02:38:54 PM PDT 24
Finished Apr 23 02:39:03 PM PDT 24
Peak memory 203972 kb
Host smart-73c89924-166b-45da-9264-ea7edda080ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10865
61232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.1086561232
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_enable.338917650
Short name T476
Test name
Test status
Simulation time 8378402868 ps
CPU time 8.07 seconds
Started Apr 23 02:38:42 PM PDT 24
Finished Apr 23 02:38:51 PM PDT 24
Peak memory 204028 kb
Host smart-09ec9eee-a454-4286-9796-a66ff32a3387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33891
7650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.338917650
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.1250577606
Short name T453
Test name
Test status
Simulation time 40748798 ps
CPU time 1.06 seconds
Started Apr 23 02:38:48 PM PDT 24
Finished Apr 23 02:38:49 PM PDT 24
Peak memory 204152 kb
Host smart-daec6c5e-491d-41e7-b41a-f1768bdddde4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12505
77606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.1250577606
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.546896607
Short name T1142
Test name
Test status
Simulation time 8460456578 ps
CPU time 7.94 seconds
Started Apr 23 02:39:03 PM PDT 24
Finished Apr 23 02:39:11 PM PDT 24
Peak memory 204048 kb
Host smart-144ef206-79c2-4d04-8c2a-2b8234d906d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54689
6607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.546896607
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.4045622415
Short name T5
Test name
Test status
Simulation time 8364389968 ps
CPU time 7.74 seconds
Started Apr 23 02:38:57 PM PDT 24
Finished Apr 23 02:39:06 PM PDT 24
Peak memory 204028 kb
Host smart-fcd831b5-9a40-4b78-8b43-3c29eda05796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40456
22415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.4045622415
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.2880320894
Short name T1154
Test name
Test status
Simulation time 8436912289 ps
CPU time 7.87 seconds
Started Apr 23 02:38:43 PM PDT 24
Finished Apr 23 02:38:51 PM PDT 24
Peak memory 204064 kb
Host smart-124039a9-7a91-4c94-a5e4-df77c53dd5b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28803
20894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.2880320894
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2138760439
Short name T343
Test name
Test status
Simulation time 8414774165 ps
CPU time 7.6 seconds
Started Apr 23 02:38:48 PM PDT 24
Finished Apr 23 02:38:56 PM PDT 24
Peak memory 204008 kb
Host smart-548cb1c0-9a32-4250-93c2-8344ed5b751b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21387
60439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2138760439
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.2489718790
Short name T646
Test name
Test status
Simulation time 8429302568 ps
CPU time 8.16 seconds
Started Apr 23 02:38:46 PM PDT 24
Finished Apr 23 02:38:55 PM PDT 24
Peak memory 203988 kb
Host smart-a5076e8a-c11e-4667-82f6-d6bd695796d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24897
18790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.2489718790
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2692750362
Short name T971
Test name
Test status
Simulation time 8436066146 ps
CPU time 9.05 seconds
Started Apr 23 02:38:57 PM PDT 24
Finished Apr 23 02:39:07 PM PDT 24
Peak memory 203960 kb
Host smart-75dbbec2-4bf5-4740-9b47-a7b4cfd443d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26927
50362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2692750362
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.2666715867
Short name T889
Test name
Test status
Simulation time 8407079524 ps
CPU time 8.36 seconds
Started Apr 23 02:38:54 PM PDT 24
Finished Apr 23 02:39:03 PM PDT 24
Peak memory 204060 kb
Host smart-f160a69b-7c3d-4eaf-8be3-092be0c8640e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26667
15867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.2666715867
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.4134516645
Short name T497
Test name
Test status
Simulation time 8400882559 ps
CPU time 9.63 seconds
Started Apr 23 02:38:48 PM PDT 24
Finished Apr 23 02:38:58 PM PDT 24
Peak memory 204012 kb
Host smart-ec04b262-2229-473e-8c6a-f61a6ddaf60a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41345
16645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.4134516645
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.3276273770
Short name T74
Test name
Test status
Simulation time 8378274046 ps
CPU time 8.11 seconds
Started Apr 23 02:38:51 PM PDT 24
Finished Apr 23 02:39:00 PM PDT 24
Peak memory 204020 kb
Host smart-349ffe10-a857-4a70-871e-d2f211996367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32762
73770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.3276273770
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3887692491
Short name T686
Test name
Test status
Simulation time 8373527525 ps
CPU time 7.81 seconds
Started Apr 23 02:38:48 PM PDT 24
Finished Apr 23 02:38:56 PM PDT 24
Peak memory 204056 kb
Host smart-07755953-1ca6-4da1-88c6-56bb2e0f2c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38876
92491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3887692491
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.4127903345
Short name T303
Test name
Test status
Simulation time 205197588 ps
CPU time 0.85 seconds
Started Apr 23 02:38:55 PM PDT 24
Finished Apr 23 02:38:57 PM PDT 24
Peak memory 203852 kb
Host smart-68c71154-2334-4b36-a999-cd40ec29c783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41279
03345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.4127903345
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.2316355208
Short name T1291
Test name
Test status
Simulation time 21740225893 ps
CPU time 38.89 seconds
Started Apr 23 02:38:50 PM PDT 24
Finished Apr 23 02:39:29 PM PDT 24
Peak memory 204320 kb
Host smart-a8375370-f2c2-42c3-8ad3-684fa2a257bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23163
55208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.2316355208
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.1802281142
Short name T432
Test name
Test status
Simulation time 8427076908 ps
CPU time 9.74 seconds
Started Apr 23 02:38:54 PM PDT 24
Finished Apr 23 02:39:04 PM PDT 24
Peak memory 204012 kb
Host smart-e6ced4ce-ff62-4c01-addd-9763cbcbdf96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18022
81142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1802281142
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.4267007941
Short name T645
Test name
Test status
Simulation time 8423429394 ps
CPU time 8.79 seconds
Started Apr 23 02:38:53 PM PDT 24
Finished Apr 23 02:39:03 PM PDT 24
Peak memory 203960 kb
Host smart-9e4bd071-b2d7-40cc-b93e-9e7d38db71de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42670
07941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.4267007941
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.4211849582
Short name T1168
Test name
Test status
Simulation time 8376164150 ps
CPU time 8.65 seconds
Started Apr 23 02:38:53 PM PDT 24
Finished Apr 23 02:39:03 PM PDT 24
Peak memory 204048 kb
Host smart-145db028-6b7c-483c-a0b6-db9f3bc854df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42118
49582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.4211849582
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.3114823562
Short name T162
Test name
Test status
Simulation time 8375050135 ps
CPU time 7.84 seconds
Started Apr 23 02:38:49 PM PDT 24
Finished Apr 23 02:38:58 PM PDT 24
Peak memory 203980 kb
Host smart-2d3c1098-0ecb-41eb-ba99-dc16883b653b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31148
23562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.3114823562
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.1247802824
Short name T704
Test name
Test status
Simulation time 8363752578 ps
CPU time 8.08 seconds
Started Apr 23 02:38:49 PM PDT 24
Finished Apr 23 02:38:57 PM PDT 24
Peak memory 204008 kb
Host smart-556f6b81-b383-4f95-988b-32c07a54d881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12478
02824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.1247802824
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.2418128894
Short name T1104
Test name
Test status
Simulation time 8470812736 ps
CPU time 9.81 seconds
Started Apr 23 02:38:51 PM PDT 24
Finished Apr 23 02:39:02 PM PDT 24
Peak memory 204060 kb
Host smart-35677940-9a7c-426c-94be-2f9dd2a26142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24181
28894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.2418128894
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.4099833533
Short name T1061
Test name
Test status
Simulation time 8468039324 ps
CPU time 7.57 seconds
Started Apr 23 02:38:47 PM PDT 24
Finished Apr 23 02:38:55 PM PDT 24
Peak memory 204020 kb
Host smart-cc0b85e5-2f5d-4c66-a671-c179ab961caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40998
33533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.4099833533
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.3272065300
Short name T717
Test name
Test status
Simulation time 8416293333 ps
CPU time 7.63 seconds
Started Apr 23 02:38:49 PM PDT 24
Finished Apr 23 02:38:58 PM PDT 24
Peak memory 203980 kb
Host smart-d0262383-d7f6-419b-bf6e-61ce223a938d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32720
65300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.3272065300
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.768100426
Short name T238
Test name
Test status
Simulation time 8476616270 ps
CPU time 8.06 seconds
Started Apr 23 02:35:31 PM PDT 24
Finished Apr 23 02:35:40 PM PDT 24
Peak memory 204020 kb
Host smart-1d88362b-952a-4ac6-9079-8724e397c8cf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=768100426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.768100426
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.831609873
Short name T442
Test name
Test status
Simulation time 8383400202 ps
CPU time 7.83 seconds
Started Apr 23 02:35:32 PM PDT 24
Finished Apr 23 02:35:41 PM PDT 24
Peak memory 203980 kb
Host smart-daef8cf2-37a7-4c9e-b300-a1dba1b861ae
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=831609873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.831609873
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.781656429
Short name T466
Test name
Test status
Simulation time 8464964118 ps
CPU time 8.89 seconds
Started Apr 23 02:35:30 PM PDT 24
Finished Apr 23 02:35:40 PM PDT 24
Peak memory 204092 kb
Host smart-0ec0c4ec-7265-41e0-a355-7fbbf52f464c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78165
6429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.781656429
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.2349488846
Short name T819
Test name
Test status
Simulation time 8375221753 ps
CPU time 8.28 seconds
Started Apr 23 02:35:28 PM PDT 24
Finished Apr 23 02:35:37 PM PDT 24
Peak memory 204008 kb
Host smart-f1c0c078-a52f-4f25-9544-643b79cf7a16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23494
88846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.2349488846
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_enable.3841343485
Short name T1249
Test name
Test status
Simulation time 8372818054 ps
CPU time 10.14 seconds
Started Apr 23 02:35:28 PM PDT 24
Finished Apr 23 02:35:38 PM PDT 24
Peak memory 204016 kb
Host smart-dd03c4b4-03ec-4910-b1fb-f8d02452f7bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38413
43485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.3841343485
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.2387060760
Short name T691
Test name
Test status
Simulation time 187431040 ps
CPU time 1.75 seconds
Started Apr 23 02:35:35 PM PDT 24
Finished Apr 23 02:35:37 PM PDT 24
Peak memory 204188 kb
Host smart-72682191-9671-4a23-a910-f3aaeb84c7b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23870
60760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.2387060760
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.2033713166
Short name T403
Test name
Test status
Simulation time 8456637417 ps
CPU time 7.72 seconds
Started Apr 23 02:35:33 PM PDT 24
Finished Apr 23 02:35:41 PM PDT 24
Peak memory 204060 kb
Host smart-8bd55fab-7c1c-4448-85ed-20c9eced9e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20337
13166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.2033713166
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.1244143209
Short name T195
Test name
Test status
Simulation time 8365042264 ps
CPU time 7.45 seconds
Started Apr 23 02:35:31 PM PDT 24
Finished Apr 23 02:35:39 PM PDT 24
Peak memory 203980 kb
Host smart-981d814d-e158-424a-b26f-e98ba9030d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12441
43209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.1244143209
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.1978725914
Short name T140
Test name
Test status
Simulation time 8388267910 ps
CPU time 9.17 seconds
Started Apr 23 02:35:34 PM PDT 24
Finished Apr 23 02:35:44 PM PDT 24
Peak memory 204060 kb
Host smart-5a664b72-63f6-432e-8473-2cb592529887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19787
25914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1978725914
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.1195143479
Short name T725
Test name
Test status
Simulation time 8493685025 ps
CPU time 7.6 seconds
Started Apr 23 02:35:31 PM PDT 24
Finished Apr 23 02:35:39 PM PDT 24
Peak memory 204020 kb
Host smart-684df6e9-f4f8-43ec-a797-a5502ad8469e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11951
43479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.1195143479
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1798483351
Short name T434
Test name
Test status
Simulation time 8448270506 ps
CPU time 7.9 seconds
Started Apr 23 02:35:27 PM PDT 24
Finished Apr 23 02:35:35 PM PDT 24
Peak memory 204036 kb
Host smart-440bf648-a73a-4664-98f6-00af945038f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17984
83351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1798483351
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.2604164405
Short name T121
Test name
Test status
Simulation time 8470890172 ps
CPU time 8.39 seconds
Started Apr 23 02:35:34 PM PDT 24
Finished Apr 23 02:35:43 PM PDT 24
Peak memory 203976 kb
Host smart-2e98d6c6-1a17-41e4-a5e5-80e39bf46f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26041
64405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.2604164405
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.810700576
Short name T911
Test name
Test status
Simulation time 8414147833 ps
CPU time 8.41 seconds
Started Apr 23 02:35:35 PM PDT 24
Finished Apr 23 02:35:43 PM PDT 24
Peak memory 204056 kb
Host smart-be91943f-d38e-456a-84f8-afc98ee515ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81070
0576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.810700576
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.2982849063
Short name T599
Test name
Test status
Simulation time 8420108475 ps
CPU time 8.01 seconds
Started Apr 23 02:35:29 PM PDT 24
Finished Apr 23 02:35:38 PM PDT 24
Peak memory 204008 kb
Host smart-12f00bc9-f64a-4c82-8ef2-e321ec29ae4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29828
49063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2982849063
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.4224010815
Short name T764
Test name
Test status
Simulation time 8398534378 ps
CPU time 8.03 seconds
Started Apr 23 02:35:28 PM PDT 24
Finished Apr 23 02:35:37 PM PDT 24
Peak memory 203972 kb
Host smart-71e0b685-52a3-42ef-a8e3-1e3e15734567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42240
10815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.4224010815
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.3673223741
Short name T890
Test name
Test status
Simulation time 8442586649 ps
CPU time 8.58 seconds
Started Apr 23 02:35:28 PM PDT 24
Finished Apr 23 02:35:37 PM PDT 24
Peak memory 204016 kb
Host smart-8a825584-b8a9-4984-92f7-c73cac3757b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36732
23741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.3673223741
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.2199542353
Short name T242
Test name
Test status
Simulation time 37242681 ps
CPU time 0.62 seconds
Started Apr 23 02:35:25 PM PDT 24
Finished Apr 23 02:35:27 PM PDT 24
Peak memory 203928 kb
Host smart-3f4994ce-07d1-4fdc-a9b9-e6175dd17bb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21995
42353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.2199542353
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.1664802512
Short name T1029
Test name
Test status
Simulation time 29208771880 ps
CPU time 54.18 seconds
Started Apr 23 02:35:31 PM PDT 24
Finished Apr 23 02:36:26 PM PDT 24
Peak memory 204300 kb
Host smart-9d1037ff-11b3-4397-b9bc-2c7aec449884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16648
02512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.1664802512
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.2740200521
Short name T1068
Test name
Test status
Simulation time 8429887883 ps
CPU time 8.29 seconds
Started Apr 23 02:35:28 PM PDT 24
Finished Apr 23 02:35:37 PM PDT 24
Peak memory 204044 kb
Host smart-7d6d4953-0f94-4c4a-9eb4-14309e2e50fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27402
00521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2740200521
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.958142895
Short name T1175
Test name
Test status
Simulation time 8474503418 ps
CPU time 8.55 seconds
Started Apr 23 02:35:28 PM PDT 24
Finished Apr 23 02:35:37 PM PDT 24
Peak memory 203968 kb
Host smart-517f8c12-46ac-4301-944a-cbb51a4b3ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95814
2895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.958142895
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.2390997245
Short name T855
Test name
Test status
Simulation time 8396576464 ps
CPU time 7.97 seconds
Started Apr 23 02:35:36 PM PDT 24
Finished Apr 23 02:35:45 PM PDT 24
Peak memory 204056 kb
Host smart-9c9f286c-ac25-496d-aa71-f9f3a5c89b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23909
97245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.2390997245
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.2084332658
Short name T563
Test name
Test status
Simulation time 8371197080 ps
CPU time 9.43 seconds
Started Apr 23 02:35:28 PM PDT 24
Finished Apr 23 02:35:38 PM PDT 24
Peak memory 204076 kb
Host smart-f2fac2de-8cfd-4399-af75-fee57f9f5e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20843
32658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.2084332658
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.2315982460
Short name T932
Test name
Test status
Simulation time 8373005234 ps
CPU time 7.74 seconds
Started Apr 23 02:35:36 PM PDT 24
Finished Apr 23 02:35:44 PM PDT 24
Peak memory 204056 kb
Host smart-728e1c0c-a4ef-45ee-af05-dab53f9681b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23159
82460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.2315982460
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1066771290
Short name T1155
Test name
Test status
Simulation time 8520661604 ps
CPU time 8.32 seconds
Started Apr 23 02:35:28 PM PDT 24
Finished Apr 23 02:35:37 PM PDT 24
Peak memory 203972 kb
Host smart-3ce53597-0690-44f4-abe5-f590ef1ef2b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10667
71290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1066771290
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.1094426506
Short name T494
Test name
Test status
Simulation time 8438593622 ps
CPU time 8.29 seconds
Started Apr 23 02:35:26 PM PDT 24
Finished Apr 23 02:35:35 PM PDT 24
Peak memory 204000 kb
Host smart-86bafebc-c66a-4370-b8c3-cefec98a87a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10944
26506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.1094426506
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.1145673829
Short name T1204
Test name
Test status
Simulation time 8413481829 ps
CPU time 8.23 seconds
Started Apr 23 02:35:33 PM PDT 24
Finished Apr 23 02:35:42 PM PDT 24
Peak memory 203968 kb
Host smart-3e3dde60-4102-4d54-924f-67bf5d9a749e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11456
73829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.1145673829
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.3343664974
Short name T920
Test name
Test status
Simulation time 8459561089 ps
CPU time 7.82 seconds
Started Apr 23 02:35:36 PM PDT 24
Finished Apr 23 02:35:45 PM PDT 24
Peak memory 204024 kb
Host smart-a4978e8b-e9fa-494e-9949-6cc0d83e2920
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3343664974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.3343664974
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.2808155732
Short name T845
Test name
Test status
Simulation time 8381570729 ps
CPU time 8.94 seconds
Started Apr 23 02:35:40 PM PDT 24
Finished Apr 23 02:35:49 PM PDT 24
Peak memory 203996 kb
Host smart-5819be56-c71c-4f8c-a509-b3bb395af3a9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2808155732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.2808155732
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.3292675272
Short name T983
Test name
Test status
Simulation time 8393962777 ps
CPU time 7.7 seconds
Started Apr 23 02:35:38 PM PDT 24
Finished Apr 23 02:35:46 PM PDT 24
Peak memory 204008 kb
Host smart-fe824957-988b-497d-b00a-10f3f824afd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32926
75272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.3292675272
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.3621636488
Short name T899
Test name
Test status
Simulation time 8390589600 ps
CPU time 7.57 seconds
Started Apr 23 02:35:32 PM PDT 24
Finished Apr 23 02:35:41 PM PDT 24
Peak memory 204016 kb
Host smart-08109139-12bf-4ca1-8cab-d6bb25800459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36216
36488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.3621636488
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_enable.1180479741
Short name T1354
Test name
Test status
Simulation time 8394428642 ps
CPU time 7.57 seconds
Started Apr 23 02:35:31 PM PDT 24
Finished Apr 23 02:35:39 PM PDT 24
Peak memory 203972 kb
Host smart-57a169d4-e1fd-419c-8bde-a721732a15b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11804
79741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.1180479741
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.3890094771
Short name T318
Test name
Test status
Simulation time 92278445 ps
CPU time 2.02 seconds
Started Apr 23 02:35:29 PM PDT 24
Finished Apr 23 02:35:32 PM PDT 24
Peak memory 204036 kb
Host smart-d623bb63-938d-455b-abe2-97eca70df08e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38900
94771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.3890094771
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.2776982456
Short name T667
Test name
Test status
Simulation time 8388979532 ps
CPU time 7.48 seconds
Started Apr 23 02:35:38 PM PDT 24
Finished Apr 23 02:35:46 PM PDT 24
Peak memory 204060 kb
Host smart-e6cd859b-06c2-4557-85a0-a0f22f154369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27769
82456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.2776982456
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.459559991
Short name T200
Test name
Test status
Simulation time 8370004754 ps
CPU time 7.9 seconds
Started Apr 23 02:35:39 PM PDT 24
Finished Apr 23 02:35:47 PM PDT 24
Peak memory 204044 kb
Host smart-58868e5d-11b6-4559-89a3-e55bacc708dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45955
9991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.459559991
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.1276478155
Short name T728
Test name
Test status
Simulation time 8433715075 ps
CPU time 7.86 seconds
Started Apr 23 02:35:30 PM PDT 24
Finished Apr 23 02:35:38 PM PDT 24
Peak memory 204008 kb
Host smart-efb32eaa-1c70-45b5-a47e-f74262f82423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12764
78155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.1276478155
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.2368569147
Short name T618
Test name
Test status
Simulation time 8416888673 ps
CPU time 8.71 seconds
Started Apr 23 02:35:30 PM PDT 24
Finished Apr 23 02:35:40 PM PDT 24
Peak memory 204048 kb
Host smart-afbcbf67-57e9-4a72-8929-34a795dca554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23685
69147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.2368569147
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.3064478089
Short name T378
Test name
Test status
Simulation time 8370801512 ps
CPU time 8.78 seconds
Started Apr 23 02:35:29 PM PDT 24
Finished Apr 23 02:35:39 PM PDT 24
Peak memory 204032 kb
Host smart-6d5fbeaa-f41f-4cd7-9593-c15bda63d881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30644
78089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.3064478089
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.2757271453
Short name T103
Test name
Test status
Simulation time 8436013179 ps
CPU time 7.82 seconds
Started Apr 23 02:35:32 PM PDT 24
Finished Apr 23 02:35:41 PM PDT 24
Peak memory 204060 kb
Host smart-834fc077-efde-448c-a548-62b0b1961128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27572
71453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.2757271453
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.447575395
Short name T1235
Test name
Test status
Simulation time 8373289949 ps
CPU time 8.23 seconds
Started Apr 23 02:35:33 PM PDT 24
Finished Apr 23 02:35:42 PM PDT 24
Peak memory 203996 kb
Host smart-1a48bc84-693e-4f1d-9e42-e01b9e41a903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44757
5395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.447575395
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.2791523183
Short name T351
Test name
Test status
Simulation time 8404333235 ps
CPU time 7.87 seconds
Started Apr 23 02:35:35 PM PDT 24
Finished Apr 23 02:35:43 PM PDT 24
Peak memory 204056 kb
Host smart-cb4de1ed-dde6-41b5-8894-659486c445c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27915
23183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.2791523183
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.623725119
Short name T171
Test name
Test status
Simulation time 8374006125 ps
CPU time 7.45 seconds
Started Apr 23 02:35:39 PM PDT 24
Finished Apr 23 02:35:47 PM PDT 24
Peak memory 203968 kb
Host smart-9886645b-9b47-4fcb-b1ac-5307497d41f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62372
5119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.623725119
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.3503821131
Short name T422
Test name
Test status
Simulation time 8378554569 ps
CPU time 7.69 seconds
Started Apr 23 02:35:31 PM PDT 24
Finished Apr 23 02:35:40 PM PDT 24
Peak memory 204056 kb
Host smart-2740af14-f454-4edf-b7e2-7bf9896001cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35038
21131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.3503821131
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.3260237523
Short name T962
Test name
Test status
Simulation time 95091083 ps
CPU time 0.66 seconds
Started Apr 23 02:35:39 PM PDT 24
Finished Apr 23 02:35:40 PM PDT 24
Peak memory 203900 kb
Host smart-fed99a84-ae45-4667-9b9b-421639fdb0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32602
37523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.3260237523
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.2316125756
Short name T1018
Test name
Test status
Simulation time 18160550874 ps
CPU time 31.33 seconds
Started Apr 23 02:35:31 PM PDT 24
Finished Apr 23 02:36:04 PM PDT 24
Peak memory 204360 kb
Host smart-65408686-fb07-4af0-b90e-590b82150e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23161
25756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.2316125756
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.225338766
Short name T602
Test name
Test status
Simulation time 8414129581 ps
CPU time 9.83 seconds
Started Apr 23 02:35:29 PM PDT 24
Finished Apr 23 02:35:40 PM PDT 24
Peak memory 204032 kb
Host smart-520f7fb2-7f1a-4819-b42d-eb0b1222897b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22533
8766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.225338766
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.3903036126
Short name T783
Test name
Test status
Simulation time 8435850908 ps
CPU time 10.14 seconds
Started Apr 23 02:35:32 PM PDT 24
Finished Apr 23 02:35:44 PM PDT 24
Peak memory 203988 kb
Host smart-0ebc8ed3-10a6-40f8-9b4f-57e535c4610d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39030
36126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.3903036126
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.395220306
Short name T788
Test name
Test status
Simulation time 8370869477 ps
CPU time 7.63 seconds
Started Apr 23 02:35:32 PM PDT 24
Finished Apr 23 02:35:40 PM PDT 24
Peak memory 204072 kb
Host smart-234df85d-646b-414d-a2ec-4f1b8ba9d854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39522
0306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.395220306
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.239140712
Short name T85
Test name
Test status
Simulation time 8389327318 ps
CPU time 9.11 seconds
Started Apr 23 02:35:34 PM PDT 24
Finished Apr 23 02:35:44 PM PDT 24
Peak memory 203992 kb
Host smart-dd8ece0c-23d3-4cd8-93b5-813a91f1f027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23914
0712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.239140712
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.2721105738
Short name T1017
Test name
Test status
Simulation time 8372304702 ps
CPU time 8.02 seconds
Started Apr 23 02:35:30 PM PDT 24
Finished Apr 23 02:35:39 PM PDT 24
Peak memory 204024 kb
Host smart-7d37ee35-2b88-4438-9f72-c53e837c708d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27211
05738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.2721105738
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.3085177741
Short name T142
Test name
Test status
Simulation time 8509901577 ps
CPU time 7.84 seconds
Started Apr 23 02:35:29 PM PDT 24
Finished Apr 23 02:35:38 PM PDT 24
Peak memory 204024 kb
Host smart-3580a1f9-2e07-4d85-acfc-adbaea1df172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30851
77741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3085177741
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.2811628358
Short name T844
Test name
Test status
Simulation time 8370307417 ps
CPU time 8.06 seconds
Started Apr 23 02:35:31 PM PDT 24
Finished Apr 23 02:35:39 PM PDT 24
Peak memory 204008 kb
Host smart-53e55c71-d162-4a65-b206-c63465e229c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28116
28358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.2811628358
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.531057900
Short name T867
Test name
Test status
Simulation time 8402675409 ps
CPU time 8.2 seconds
Started Apr 23 02:35:33 PM PDT 24
Finished Apr 23 02:35:42 PM PDT 24
Peak memory 204016 kb
Host smart-e55ce39f-10e7-4eaa-a3f5-5863e97bb0c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53105
7900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.531057900
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.9529849
Short name T1051
Test name
Test status
Simulation time 8465176577 ps
CPU time 7.95 seconds
Started Apr 23 02:35:41 PM PDT 24
Finished Apr 23 02:35:49 PM PDT 24
Peak memory 203952 kb
Host smart-d4cbdb4a-a18b-4fd8-aa3b-7fad95862a3d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=9529849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.9529849
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.1456646701
Short name T1271
Test name
Test status
Simulation time 8434262763 ps
CPU time 8.84 seconds
Started Apr 23 02:35:43 PM PDT 24
Finished Apr 23 02:35:52 PM PDT 24
Peak memory 204032 kb
Host smart-1f585bef-acae-43bc-a663-9420f1a0722c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1456646701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.1456646701
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.3143265017
Short name T625
Test name
Test status
Simulation time 8485132441 ps
CPU time 8.1 seconds
Started Apr 23 02:35:52 PM PDT 24
Finished Apr 23 02:36:01 PM PDT 24
Peak memory 204056 kb
Host smart-1c35620c-6f38-48db-bfa3-5a14a2bc0d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31432
65017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.3143265017
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.692099391
Short name T344
Test name
Test status
Simulation time 8387077387 ps
CPU time 8.64 seconds
Started Apr 23 02:35:36 PM PDT 24
Finished Apr 23 02:35:46 PM PDT 24
Peak memory 204048 kb
Host smart-4f2a214c-fb83-42ad-beca-c25fd53a6454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69209
9391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.692099391
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_enable.2338707165
Short name T1328
Test name
Test status
Simulation time 8387923280 ps
CPU time 7.4 seconds
Started Apr 23 02:35:38 PM PDT 24
Finished Apr 23 02:35:46 PM PDT 24
Peak memory 204064 kb
Host smart-d7618c37-653d-4100-9862-55f1d49d5f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23387
07165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2338707165
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2796831178
Short name T950
Test name
Test status
Simulation time 120992754 ps
CPU time 1.41 seconds
Started Apr 23 02:35:52 PM PDT 24
Finished Apr 23 02:35:54 PM PDT 24
Peak memory 204192 kb
Host smart-d0df37af-1808-45c7-903b-acca7da398b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27968
31178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2796831178
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.3571503055
Short name T37
Test name
Test status
Simulation time 8445587003 ps
CPU time 8.13 seconds
Started Apr 23 02:35:42 PM PDT 24
Finished Apr 23 02:35:51 PM PDT 24
Peak memory 204036 kb
Host smart-9c9d9b25-07d1-4288-8e68-56fb3cebf735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35715
03055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.3571503055
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.490665810
Short name T734
Test name
Test status
Simulation time 8370587611 ps
CPU time 7.71 seconds
Started Apr 23 02:35:41 PM PDT 24
Finished Apr 23 02:35:49 PM PDT 24
Peak memory 203872 kb
Host smart-f44d0f16-7ba7-490f-906a-fe28b4eca995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49066
5810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.490665810
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3276757548
Short name T488
Test name
Test status
Simulation time 8447832436 ps
CPU time 9.71 seconds
Started Apr 23 02:35:42 PM PDT 24
Finished Apr 23 02:35:52 PM PDT 24
Peak memory 204024 kb
Host smart-3cbcd638-a0cf-4022-a09e-179fcd30cf3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32767
57548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3276757548
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3693867384
Short name T926
Test name
Test status
Simulation time 8420497311 ps
CPU time 7.69 seconds
Started Apr 23 02:35:41 PM PDT 24
Finished Apr 23 02:35:50 PM PDT 24
Peak memory 204032 kb
Host smart-bd2976ff-2f48-4a2c-a1fe-0192c1367a38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36938
67384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3693867384
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.1341906593
Short name T11
Test name
Test status
Simulation time 8404733459 ps
CPU time 7.81 seconds
Started Apr 23 02:35:40 PM PDT 24
Finished Apr 23 02:35:48 PM PDT 24
Peak memory 204036 kb
Host smart-0e5bdaac-19ae-4ffb-8f49-dde092592831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13419
06593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.1341906593
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.94514393
Short name T1360
Test name
Test status
Simulation time 8447573829 ps
CPU time 7.71 seconds
Started Apr 23 02:35:42 PM PDT 24
Finished Apr 23 02:35:50 PM PDT 24
Peak memory 204012 kb
Host smart-17aaf55e-8885-4446-9e0f-b5ed1f7d4591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94514
393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.94514393
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2276883776
Short name T423
Test name
Test status
Simulation time 8381398720 ps
CPU time 9.85 seconds
Started Apr 23 02:35:42 PM PDT 24
Finished Apr 23 02:35:53 PM PDT 24
Peak memory 204032 kb
Host smart-614d6ebd-dd74-47d1-aff1-494d7bffeb84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22768
83776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2276883776
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.1413428348
Short name T332
Test name
Test status
Simulation time 8374872479 ps
CPU time 8.01 seconds
Started Apr 23 02:35:41 PM PDT 24
Finished Apr 23 02:35:49 PM PDT 24
Peak memory 204012 kb
Host smart-e53f6c5c-c12e-4f0c-bb7d-d44e7e76273f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14134
28348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.1413428348
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.654418692
Short name T1032
Test name
Test status
Simulation time 8398792431 ps
CPU time 7.84 seconds
Started Apr 23 02:35:45 PM PDT 24
Finished Apr 23 02:35:53 PM PDT 24
Peak memory 204036 kb
Host smart-cf94c97d-71d6-466b-9ced-ca418038ea9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65441
8692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.654418692
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2305436742
Short name T743
Test name
Test status
Simulation time 31884938 ps
CPU time 0.7 seconds
Started Apr 23 02:35:43 PM PDT 24
Finished Apr 23 02:35:44 PM PDT 24
Peak memory 203896 kb
Host smart-f5319064-75fc-4ec9-ae7b-dd688ee64cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23054
36742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2305436742
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.837063852
Short name T247
Test name
Test status
Simulation time 19073044107 ps
CPU time 37.96 seconds
Started Apr 23 02:35:49 PM PDT 24
Finished Apr 23 02:36:28 PM PDT 24
Peak memory 204344 kb
Host smart-5b34202c-b2f5-481b-b5f9-7e6730645934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83706
3852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.837063852
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.3578783354
Short name T624
Test name
Test status
Simulation time 8395548540 ps
CPU time 9.94 seconds
Started Apr 23 02:35:43 PM PDT 24
Finished Apr 23 02:35:54 PM PDT 24
Peak memory 204024 kb
Host smart-b9253fe5-6809-4bf7-ae14-a0391e52e4b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35787
83354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.3578783354
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.935400713
Short name T141
Test name
Test status
Simulation time 8391238576 ps
CPU time 8.18 seconds
Started Apr 23 02:35:42 PM PDT 24
Finished Apr 23 02:35:50 PM PDT 24
Peak memory 204032 kb
Host smart-d925a3c8-2987-4c9f-be10-9d9fce1c0f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93540
0713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.935400713
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.4288234261
Short name T480
Test name
Test status
Simulation time 8403799991 ps
CPU time 9.03 seconds
Started Apr 23 02:35:52 PM PDT 24
Finished Apr 23 02:36:02 PM PDT 24
Peak memory 204060 kb
Host smart-f233e1e7-f1c8-4c44-80b3-561f3cf2e197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42882
34261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.4288234261
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.3717101416
Short name T678
Test name
Test status
Simulation time 8402295299 ps
CPU time 7.85 seconds
Started Apr 23 02:35:41 PM PDT 24
Finished Apr 23 02:35:49 PM PDT 24
Peak memory 203808 kb
Host smart-f16585a3-93bf-4fed-b43c-591c58242241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37171
01416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.3717101416
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.751231133
Short name T876
Test name
Test status
Simulation time 8370485872 ps
CPU time 8.04 seconds
Started Apr 23 02:35:45 PM PDT 24
Finished Apr 23 02:35:53 PM PDT 24
Peak memory 203964 kb
Host smart-6959097d-bab6-4918-b81e-4b8d764e891e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75123
1133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.751231133
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.3078483996
Short name T1055
Test name
Test status
Simulation time 8460414194 ps
CPU time 8.17 seconds
Started Apr 23 02:35:38 PM PDT 24
Finished Apr 23 02:35:47 PM PDT 24
Peak memory 204052 kb
Host smart-a6caf2a0-6ad4-4cf9-864b-e74466bfc660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30784
83996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.3078483996
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.1646101839
Short name T402
Test name
Test status
Simulation time 8386101025 ps
CPU time 7.88 seconds
Started Apr 23 02:35:44 PM PDT 24
Finished Apr 23 02:35:52 PM PDT 24
Peak memory 203952 kb
Host smart-b3ce2bd8-cdb2-416f-9b7b-7714041e6877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16461
01839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.1646101839
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.2417220278
Short name T330
Test name
Test status
Simulation time 8429230932 ps
CPU time 7.92 seconds
Started Apr 23 02:35:43 PM PDT 24
Finished Apr 23 02:35:52 PM PDT 24
Peak memory 204032 kb
Host smart-abac27aa-d5d6-4064-90da-f56aa20c73fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24172
20278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.2417220278
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.620528631
Short name T771
Test name
Test status
Simulation time 8468788765 ps
CPU time 9.39 seconds
Started Apr 23 02:35:52 PM PDT 24
Finished Apr 23 02:36:02 PM PDT 24
Peak memory 204064 kb
Host smart-69f5118e-8f66-406e-b752-3a7234354c64
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=620528631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.620528631
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.55978426
Short name T533
Test name
Test status
Simulation time 8413584807 ps
CPU time 7.52 seconds
Started Apr 23 02:35:48 PM PDT 24
Finished Apr 23 02:35:56 PM PDT 24
Peak memory 203988 kb
Host smart-90af3ad1-1b02-402b-a525-365798613021
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=55978426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.55978426
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.3826289087
Short name T158
Test name
Test status
Simulation time 8409827876 ps
CPU time 9.93 seconds
Started Apr 23 02:35:49 PM PDT 24
Finished Apr 23 02:36:00 PM PDT 24
Peak memory 204004 kb
Host smart-f8faf750-ce51-41d5-881f-38557b5b1748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38262
89087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.3826289087
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.974637527
Short name T1260
Test name
Test status
Simulation time 8427326670 ps
CPU time 7.64 seconds
Started Apr 23 02:35:45 PM PDT 24
Finished Apr 23 02:35:54 PM PDT 24
Peak memory 204020 kb
Host smart-d122d08e-2d41-4faf-97ec-1a000ff2e430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97463
7527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.974637527
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_enable.3604598579
Short name T762
Test name
Test status
Simulation time 8375666392 ps
CPU time 7.79 seconds
Started Apr 23 02:35:46 PM PDT 24
Finished Apr 23 02:35:54 PM PDT 24
Peak memory 204020 kb
Host smart-597da4c9-1c60-48b0-8a1e-f39f20e50e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36045
98579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3604598579
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.3527476146
Short name T936
Test name
Test status
Simulation time 52807211 ps
CPU time 1.09 seconds
Started Apr 23 02:35:48 PM PDT 24
Finished Apr 23 02:35:50 PM PDT 24
Peak memory 204064 kb
Host smart-e6a0e222-86fd-4854-9e85-948841032c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35274
76146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.3527476146
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.63141717
Short name T155
Test name
Test status
Simulation time 8437678435 ps
CPU time 10.68 seconds
Started Apr 23 02:35:48 PM PDT 24
Finished Apr 23 02:35:59 PM PDT 24
Peak memory 204032 kb
Host smart-6eba8baa-5744-4498-88f3-e006643b0eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63141
717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.63141717
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.3057194995
Short name T1119
Test name
Test status
Simulation time 8375984113 ps
CPU time 7.41 seconds
Started Apr 23 02:35:49 PM PDT 24
Finished Apr 23 02:35:57 PM PDT 24
Peak memory 204044 kb
Host smart-b70266d3-26d6-4efa-ae28-450132d536a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30571
94995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.3057194995
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.4280445103
Short name T509
Test name
Test status
Simulation time 8432593782 ps
CPU time 7.69 seconds
Started Apr 23 02:35:45 PM PDT 24
Finished Apr 23 02:35:54 PM PDT 24
Peak memory 203988 kb
Host smart-af0633ce-2809-49d6-bf94-1ca0d51b6433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42804
45103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.4280445103
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.3612024500
Short name T829
Test name
Test status
Simulation time 8439665241 ps
CPU time 9.1 seconds
Started Apr 23 02:35:45 PM PDT 24
Finished Apr 23 02:35:55 PM PDT 24
Peak memory 203968 kb
Host smart-b9075690-0ddf-4c21-8e7a-f95215b198e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36120
24500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.3612024500
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.117094096
Short name T988
Test name
Test status
Simulation time 8375678903 ps
CPU time 7.36 seconds
Started Apr 23 02:35:47 PM PDT 24
Finished Apr 23 02:35:55 PM PDT 24
Peak memory 204008 kb
Host smart-f2f464da-c63e-43ff-9e96-a13df9c14793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11709
4096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.117094096
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.1279868083
Short name T1111
Test name
Test status
Simulation time 8447618539 ps
CPU time 8.16 seconds
Started Apr 23 02:35:46 PM PDT 24
Finished Apr 23 02:35:54 PM PDT 24
Peak memory 204028 kb
Host smart-2fe342ee-c706-43e1-a39e-d1d9b671dea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12798
68083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.1279868083
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.2032561260
Short name T996
Test name
Test status
Simulation time 8410582814 ps
CPU time 8.28 seconds
Started Apr 23 02:35:49 PM PDT 24
Finished Apr 23 02:35:58 PM PDT 24
Peak memory 203996 kb
Host smart-6d76a237-3f0d-4183-83e5-721b64ab73a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20325
61260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.2032561260
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.2483618330
Short name T387
Test name
Test status
Simulation time 8391123975 ps
CPU time 9.54 seconds
Started Apr 23 02:35:47 PM PDT 24
Finished Apr 23 02:35:57 PM PDT 24
Peak memory 204008 kb
Host smart-0076ea6f-d44e-4212-a61c-1a85021256da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24836
18330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.2483618330
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.1512977592
Short name T1370
Test name
Test status
Simulation time 8388389460 ps
CPU time 10.39 seconds
Started Apr 23 02:35:51 PM PDT 24
Finished Apr 23 02:36:01 PM PDT 24
Peak memory 204008 kb
Host smart-c0869be5-e6b3-4283-a502-1a962affc1dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15129
77592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.1512977592
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.2349797731
Short name T1054
Test name
Test status
Simulation time 8396272433 ps
CPU time 8.22 seconds
Started Apr 23 02:35:48 PM PDT 24
Finished Apr 23 02:35:57 PM PDT 24
Peak memory 204000 kb
Host smart-5138ffd2-8e01-48b2-abf2-c07da3b80a38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23497
97731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.2349797731
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.4008986576
Short name T965
Test name
Test status
Simulation time 36678745 ps
CPU time 0.62 seconds
Started Apr 23 02:35:46 PM PDT 24
Finished Apr 23 02:35:47 PM PDT 24
Peak memory 203872 kb
Host smart-5678169e-774f-47f7-93ab-799c04bcfab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40089
86576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.4008986576
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.2899808019
Short name T219
Test name
Test status
Simulation time 20539247706 ps
CPU time 36.49 seconds
Started Apr 23 02:35:45 PM PDT 24
Finished Apr 23 02:36:22 PM PDT 24
Peak memory 204300 kb
Host smart-1d5e3501-d5c9-48f6-9bab-bc3fbfd421e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28998
08019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.2899808019
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.2160697274
Short name T300
Test name
Test status
Simulation time 8412083894 ps
CPU time 8.21 seconds
Started Apr 23 02:35:47 PM PDT 24
Finished Apr 23 02:35:56 PM PDT 24
Peak memory 204008 kb
Host smart-cc60fca2-1ab6-4752-8fc0-c5a73588b6dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21606
97274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.2160697274
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.4015069885
Short name T994
Test name
Test status
Simulation time 8423610442 ps
CPU time 8.15 seconds
Started Apr 23 02:35:44 PM PDT 24
Finished Apr 23 02:35:53 PM PDT 24
Peak memory 204064 kb
Host smart-cc177d18-9446-40d0-b761-4938595fe8b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40150
69885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.4015069885
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.3858299352
Short name T1270
Test name
Test status
Simulation time 8483980145 ps
CPU time 7.88 seconds
Started Apr 23 02:35:46 PM PDT 24
Finished Apr 23 02:35:54 PM PDT 24
Peak memory 204016 kb
Host smart-bd2bc0e1-bf27-42af-88d1-603190c86315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38582
99352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.3858299352
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.227037754
Short name T873
Test name
Test status
Simulation time 8375658484 ps
CPU time 7.87 seconds
Started Apr 23 02:35:49 PM PDT 24
Finished Apr 23 02:35:57 PM PDT 24
Peak memory 204048 kb
Host smart-5724045a-b362-4f80-915b-c8082d0fabd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22703
7754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.227037754
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.3881771645
Short name T773
Test name
Test status
Simulation time 8404596513 ps
CPU time 10.02 seconds
Started Apr 23 02:35:47 PM PDT 24
Finished Apr 23 02:35:57 PM PDT 24
Peak memory 204032 kb
Host smart-43221805-6701-4047-8f86-b68812623ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38817
71645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.3881771645
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.1074294295
Short name T866
Test name
Test status
Simulation time 8420416496 ps
CPU time 7.77 seconds
Started Apr 23 02:35:41 PM PDT 24
Finished Apr 23 02:35:49 PM PDT 24
Peak memory 204032 kb
Host smart-edc0e98c-e0bb-4122-916a-fcaf07fc8293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10742
94295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1074294295
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.4188594422
Short name T974
Test name
Test status
Simulation time 8375085151 ps
CPU time 7.99 seconds
Started Apr 23 02:35:46 PM PDT 24
Finished Apr 23 02:35:54 PM PDT 24
Peak memory 204016 kb
Host smart-78aa9a0c-3876-499e-b894-29be5ac04770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41885
94422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.4188594422
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.1109830566
Short name T334
Test name
Test status
Simulation time 8402335049 ps
CPU time 8.08 seconds
Started Apr 23 02:35:45 PM PDT 24
Finished Apr 23 02:35:53 PM PDT 24
Peak memory 204060 kb
Host smart-6c0e0233-654c-4cfd-a7a2-78e239b71b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11098
30566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.1109830566
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.max_length_in_transaction.2403472447
Short name T32
Test name
Test status
Simulation time 8466634904 ps
CPU time 9.17 seconds
Started Apr 23 02:35:52 PM PDT 24
Finished Apr 23 02:36:02 PM PDT 24
Peak memory 204020 kb
Host smart-5c282baf-70e1-4f06-a2a5-d2b747e74ebc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2403472447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.2403472447
Directory /workspace/9.max_length_in_transaction/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.2107527569
Short name T1224
Test name
Test status
Simulation time 8389008528 ps
CPU time 8.25 seconds
Started Apr 23 02:35:54 PM PDT 24
Finished Apr 23 02:36:03 PM PDT 24
Peak memory 204016 kb
Host smart-f0551b5d-e05d-4c54-abd0-b196a22738c6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2107527569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.2107527569
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.2553203124
Short name T264
Test name
Test status
Simulation time 8464532951 ps
CPU time 8.18 seconds
Started Apr 23 02:35:58 PM PDT 24
Finished Apr 23 02:36:08 PM PDT 24
Peak memory 204024 kb
Host smart-b3e58677-22f9-46c2-9522-7c2b29927884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25532
03124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.2553203124
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.1080143777
Short name T837
Test name
Test status
Simulation time 8376393759 ps
CPU time 7.45 seconds
Started Apr 23 02:35:48 PM PDT 24
Finished Apr 23 02:35:56 PM PDT 24
Peak memory 204064 kb
Host smart-4d5c3463-6da1-4502-8c23-785f09957172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10801
43777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.1080143777
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_enable.3585427534
Short name T956
Test name
Test status
Simulation time 8416879626 ps
CPU time 7.7 seconds
Started Apr 23 02:35:55 PM PDT 24
Finished Apr 23 02:36:03 PM PDT 24
Peak memory 204064 kb
Host smart-1804ab1c-ab6f-4f73-8f31-b8eb51212c8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35854
27534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.3585427534
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.910486018
Short name T523
Test name
Test status
Simulation time 62594370 ps
CPU time 1.63 seconds
Started Apr 23 02:35:52 PM PDT 24
Finished Apr 23 02:35:54 PM PDT 24
Peak memory 204140 kb
Host smart-e797a13c-0150-4f6d-9ad5-4b7702ce7bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91048
6018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.910486018
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.2031865396
Short name T154
Test name
Test status
Simulation time 8447859256 ps
CPU time 8.77 seconds
Started Apr 23 02:35:53 PM PDT 24
Finished Apr 23 02:36:03 PM PDT 24
Peak memory 203960 kb
Host smart-66fce8b9-1365-4db5-af07-58260acf53da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20318
65396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.2031865396
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.4072157946
Short name T682
Test name
Test status
Simulation time 8386617574 ps
CPU time 8.15 seconds
Started Apr 23 02:35:53 PM PDT 24
Finished Apr 23 02:36:02 PM PDT 24
Peak memory 204008 kb
Host smart-eb7a5308-a894-48b8-8047-306041300a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40721
57946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.4072157946
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.1714817915
Short name T976
Test name
Test status
Simulation time 8480606708 ps
CPU time 8.44 seconds
Started Apr 23 02:35:50 PM PDT 24
Finished Apr 23 02:35:59 PM PDT 24
Peak memory 204048 kb
Host smart-38c7d974-5b0b-4c5a-9130-611ab8779e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17148
17915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.1714817915
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.905220076
Short name T672
Test name
Test status
Simulation time 8419839314 ps
CPU time 8.34 seconds
Started Apr 23 02:35:51 PM PDT 24
Finished Apr 23 02:35:59 PM PDT 24
Peak memory 203984 kb
Host smart-b1164997-865e-4e92-b5e2-a6f2c88049c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90522
0076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.905220076
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.2004472829
Short name T439
Test name
Test status
Simulation time 8378233523 ps
CPU time 9.7 seconds
Started Apr 23 02:35:52 PM PDT 24
Finished Apr 23 02:36:02 PM PDT 24
Peak memory 204060 kb
Host smart-967a55e0-a183-4dc7-aaf4-741c54b3b78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20044
72829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.2004472829
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1999982531
Short name T101
Test name
Test status
Simulation time 8425377431 ps
CPU time 8.23 seconds
Started Apr 23 02:35:51 PM PDT 24
Finished Apr 23 02:35:59 PM PDT 24
Peak memory 204040 kb
Host smart-76353095-9c7b-4dc7-a37f-d28f0bb8f221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19999
82531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1999982531
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.3098167006
Short name T1209
Test name
Test status
Simulation time 8393187535 ps
CPU time 7.83 seconds
Started Apr 23 02:35:50 PM PDT 24
Finished Apr 23 02:35:59 PM PDT 24
Peak memory 204048 kb
Host smart-f5a4a6a6-60db-48d6-9781-787081b3f2ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30981
67006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.3098167006
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.1167752280
Short name T747
Test name
Test status
Simulation time 8395901628 ps
CPU time 8.68 seconds
Started Apr 23 02:35:53 PM PDT 24
Finished Apr 23 02:36:02 PM PDT 24
Peak memory 204012 kb
Host smart-9a89c19a-d04c-4e71-818c-289efd07a9b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11677
52280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.1167752280
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.1909850564
Short name T1366
Test name
Test status
Simulation time 8398458347 ps
CPU time 7.61 seconds
Started Apr 23 02:35:55 PM PDT 24
Finished Apr 23 02:36:03 PM PDT 24
Peak memory 204060 kb
Host smart-5bff2249-9b2a-45fb-97f2-adb30d173bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19098
50564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.1909850564
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.2807388052
Short name T575
Test name
Test status
Simulation time 8366036344 ps
CPU time 7.94 seconds
Started Apr 23 02:35:50 PM PDT 24
Finished Apr 23 02:35:59 PM PDT 24
Peak memory 204000 kb
Host smart-5a3fa350-0ab2-494e-b900-be36e439ee72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28073
88052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.2807388052
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.1792087183
Short name T1128
Test name
Test status
Simulation time 38829647 ps
CPU time 0.65 seconds
Started Apr 23 02:35:50 PM PDT 24
Finished Apr 23 02:35:51 PM PDT 24
Peak memory 203928 kb
Host smart-83f625f4-2806-4217-b6cf-36122b1319c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17920
87183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1792087183
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.2098601402
Short name T941
Test name
Test status
Simulation time 23415938401 ps
CPU time 43.39 seconds
Started Apr 23 02:35:50 PM PDT 24
Finished Apr 23 02:36:34 PM PDT 24
Peak memory 204348 kb
Host smart-61e3ec51-4516-466d-b8e6-62a4f799333f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20986
01402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.2098601402
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.747044222
Short name T1356
Test name
Test status
Simulation time 8376871228 ps
CPU time 9.03 seconds
Started Apr 23 02:35:55 PM PDT 24
Finished Apr 23 02:36:04 PM PDT 24
Peak memory 203988 kb
Host smart-85c84387-ba09-4f1a-94b1-af53419a954f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74704
4222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.747044222
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.1712957063
Short name T821
Test name
Test status
Simulation time 8409778445 ps
CPU time 8.44 seconds
Started Apr 23 02:35:54 PM PDT 24
Finished Apr 23 02:36:03 PM PDT 24
Peak memory 204064 kb
Host smart-2b24869f-d7bb-4c25-bfe2-f45cb7f53185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17129
57063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1712957063
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.1474706851
Short name T1261
Test name
Test status
Simulation time 8372627507 ps
CPU time 7.84 seconds
Started Apr 23 02:35:52 PM PDT 24
Finished Apr 23 02:36:00 PM PDT 24
Peak memory 203984 kb
Host smart-32636302-9b9f-4e50-a046-e05e3f4037e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14747
06851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.1474706851
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.687691655
Short name T182
Test name
Test status
Simulation time 8398345650 ps
CPU time 7.82 seconds
Started Apr 23 02:35:52 PM PDT 24
Finished Apr 23 02:36:01 PM PDT 24
Peak memory 204016 kb
Host smart-5518f765-74cb-40e9-8e00-7ba2691a6922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68769
1655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.687691655
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2100703568
Short name T370
Test name
Test status
Simulation time 8399153163 ps
CPU time 7.83 seconds
Started Apr 23 02:35:53 PM PDT 24
Finished Apr 23 02:36:01 PM PDT 24
Peak memory 203984 kb
Host smart-d09a4300-d5bf-4b00-b2d9-041d574cc71f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21007
03568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2100703568
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.4054424560
Short name T981
Test name
Test status
Simulation time 8461754067 ps
CPU time 8.63 seconds
Started Apr 23 02:35:48 PM PDT 24
Finished Apr 23 02:35:57 PM PDT 24
Peak memory 203988 kb
Host smart-99ddf834-e827-49c0-9a5a-d502b44dc321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40544
24560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.4054424560
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.246391033
Short name T419
Test name
Test status
Simulation time 8479035383 ps
CPU time 8.55 seconds
Started Apr 23 02:35:50 PM PDT 24
Finished Apr 23 02:35:59 PM PDT 24
Peak memory 204008 kb
Host smart-c129a712-742f-4be7-a1bf-31e48a1a2634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24639
1033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.246391033
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.1558373898
Short name T1306
Test name
Test status
Simulation time 8395704249 ps
CPU time 8.15 seconds
Started Apr 23 02:35:49 PM PDT 24
Finished Apr 23 02:35:58 PM PDT 24
Peak memory 204004 kb
Host smart-78a3f33a-eb95-4a21-afad-a5a571a5ad73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15583
73898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.1558373898
Directory /workspace/9.usbdev_stall_trans/latest
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