Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 22 0 22 100.00
Crosses 72 0 72 100.00


Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 18 0 18 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_cg_cc 72 0 72 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 18 0 18 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 25401 1 T2 3 T3 2 T4 3
all_values[1] 25401 1 T2 3 T3 2 T4 3
all_values[2] 25401 1 T2 3 T3 2 T4 3
all_values[3] 25401 1 T2 3 T3 2 T4 3
all_values[4] 25401 1 T2 3 T3 2 T4 3
all_values[5] 25401 1 T2 3 T3 2 T4 3
all_values[6] 25401 1 T2 3 T3 2 T4 3
all_values[7] 25401 1 T2 3 T3 2 T4 3
all_values[8] 25401 1 T2 3 T3 2 T4 3
all_values[9] 25401 1 T2 3 T3 2 T4 3
all_values[10] 25401 1 T2 3 T3 2 T4 3
all_values[11] 25401 1 T2 3 T3 2 T4 3
all_values[12] 25401 1 T2 3 T3 2 T4 3
all_values[13] 25401 1 T2 3 T3 2 T4 3
all_values[14] 25401 1 T2 3 T3 2 T4 3
all_values[15] 25401 1 T2 3 T3 2 T4 3
all_values[16] 25401 1 T2 3 T3 2 T4 3
all_values[17] 25401 1 T2 3 T3 2 T4 3



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 453340 1 T2 54 T3 36 T4 51
auto[1] 3878 1 T4 3 T10 4 T11 3



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 452413 1 T2 54 T3 36 T4 54
auto[1] 4805 1 T60 73 T61 77 T62 128



Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 72 0 72 100.00


Automatically Generated Cross Bins for intr_cg_cc

Bins
cp_intrcp_intr_encp_intr_stateCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] 24398 1 T2 3 T3 2 T11 3
all_values[0] auto[0] auto[1] 160 1 T60 4 T62 3 T63 5
all_values[0] auto[1] auto[0] 722 1 T4 3 T10 4 T17 4
all_values[0] auto[1] auto[1] 121 1 T60 1 T61 3 T62 2
all_values[1] auto[0] auto[0] 24804 1 T2 3 T3 2 T4 3
all_values[1] auto[0] auto[1] 131 1 T62 2 T63 6 T294 5
all_values[1] auto[1] auto[0] 335 1 T11 3 T37 3 T47 3
all_values[1] auto[1] auto[1] 131 1 T60 3 T61 5 T62 6
all_values[2] auto[0] auto[0] 25096 1 T2 3 T3 2 T4 3
all_values[2] auto[0] auto[1] 137 1 T60 1 T61 3 T62 2
all_values[2] auto[1] auto[0] 24 1 T60 1 T61 1 T64 2
all_values[2] auto[1] auto[1] 144 1 T60 3 T61 1 T62 6
all_values[3] auto[0] auto[0] 25107 1 T2 3 T3 2 T4 3
all_values[3] auto[0] auto[1] 137 1 T60 4 T61 1 T62 4
all_values[3] auto[1] auto[0] 26 1 T294 2 T291 1 T295 2
all_values[3] auto[1] auto[1] 131 1 T61 4 T62 4 T63 5
all_values[4] auto[0] auto[0] 25106 1 T2 3 T3 2 T4 3
all_values[4] auto[0] auto[1] 141 1 T60 3 T61 2 T62 5
all_values[4] auto[1] auto[0] 23 1 T62 1 T294 1 T291 2
all_values[4] auto[1] auto[1] 131 1 T60 2 T61 3 T62 1
all_values[5] auto[0] auto[0] 25101 1 T2 3 T3 2 T4 3
all_values[5] auto[0] auto[1] 144 1 T60 1 T62 3 T63 5
all_values[5] auto[1] auto[0] 24 1 T64 1 T294 3 T296 1
all_values[5] auto[1] auto[1] 132 1 T60 4 T61 4 T62 5
all_values[6] auto[0] auto[0] 25113 1 T2 3 T3 2 T4 3
all_values[6] auto[0] auto[1] 126 1 T60 1 T61 4 T62 3
all_values[6] auto[1] auto[0] 28 1 T62 1 T296 1 T297 1
all_values[6] auto[1] auto[1] 134 1 T60 4 T62 4 T63 5
all_values[7] auto[0] auto[0] 25112 1 T2 3 T3 2 T4 3
all_values[7] auto[0] auto[1] 119 1 T61 1 T62 6 T63 6
all_values[7] auto[1] auto[0] 28 1 T60 1 T63 1 T294 2
all_values[7] auto[1] auto[1] 142 1 T60 4 T61 4 T62 2
all_values[8] auto[0] auto[0] 25102 1 T2 3 T3 2 T4 3
all_values[8] auto[0] auto[1] 154 1 T60 3 T61 1 T62 2
all_values[8] auto[1] auto[0] 25 1 T60 2 T64 1 T294 1
all_values[8] auto[1] auto[1] 120 1 T61 3 T62 6 T63 5
all_values[9] auto[0] auto[0] 25112 1 T2 3 T3 2 T4 3
all_values[9] auto[0] auto[1] 110 1 T60 4 T62 2 T63 2
all_values[9] auto[1] auto[0] 49 1 T61 1 T62 1 T294 2
all_values[9] auto[1] auto[1] 130 1 T61 4 T62 5 T63 4
all_values[10] auto[0] auto[0] 25103 1 T2 3 T3 2 T4 3
all_values[10] auto[0] auto[1] 142 1 T60 4 T61 2 T62 3
all_values[10] auto[1] auto[0] 14 1 T294 1 T296 1 T297 1
all_values[10] auto[1] auto[1] 142 1 T60 1 T61 3 T62 4
all_values[11] auto[0] auto[0] 25114 1 T2 3 T3 2 T4 3
all_values[11] auto[0] auto[1] 129 1 T61 1 T62 3 T63 3
all_values[11] auto[1] auto[0] 19 1 T60 1 T61 1 T63 3
all_values[11] auto[1] auto[1] 139 1 T61 3 T62 5 T64 1
all_values[12] auto[0] auto[0] 25103 1 T2 3 T3 2 T4 3
all_values[12] auto[0] auto[1] 142 1 T60 1 T61 5 T62 5
all_values[12] auto[1] auto[0] 24 1 T64 2 T297 1 T295 4
all_values[12] auto[1] auto[1] 132 1 T60 4 T62 3 T63 4
all_values[13] auto[0] auto[0] 25100 1 T2 3 T3 2 T4 3
all_values[13] auto[0] auto[1] 111 1 T60 4 T61 2 T62 1
all_values[13] auto[1] auto[0] 31 1 T62 2 T290 2 T291 4
all_values[13] auto[1] auto[1] 159 1 T60 1 T61 3 T62 4
all_values[14] auto[0] auto[0] 25108 1 T2 3 T3 2 T4 3
all_values[14] auto[0] auto[1] 148 1 T60 3 T62 3 T63 7
all_values[14] auto[1] auto[0] 22 1 T294 1 T296 1 T292 1
all_values[14] auto[1] auto[1] 123 1 T60 1 T61 3 T62 5
all_values[15] auto[0] auto[0] 25110 1 T2 3 T3 2 T4 3
all_values[15] auto[0] auto[1] 148 1 T60 3 T61 3 T62 3
all_values[15] auto[1] auto[0] 40 1 T60 1 T291 1 T296 2
all_values[15] auto[1] auto[1] 103 1 T61 1 T62 5 T63 1
all_values[16] auto[0] auto[0] 25108 1 T2 3 T3 2 T4 3
all_values[16] auto[0] auto[1] 126 1 T60 3 T61 4 T62 5
all_values[16] auto[1] auto[0] 37 1 T60 1 T62 1 T64 1
all_values[16] auto[1] auto[1] 130 1 T60 1 T62 1 T63 5
all_values[17] auto[0] auto[0] 25114 1 T2 3 T3 2 T4 3
all_values[17] auto[0] auto[1] 124 1 T60 3 T61 4 T62 5
all_values[17] auto[1] auto[0] 31 1 T61 1 T62 1 T294 1
all_values[17] auto[1] auto[1] 132 1 T60 2 T63 3 T64 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%