Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	25401	1		T2	3		T3	2		T4	3
all_pins[1]	25401	1		T2	3		T3	2		T4	3
all_pins[2]	25401	1		T2	3		T3	2		T4	3
all_pins[3]	25401	1		T2	3		T3	2		T4	3
all_pins[4]	25401	1		T2	3		T3	2		T4	3
all_pins[5]	25401	1		T2	3		T3	2		T4	3
all_pins[6]	25401	1		T2	3		T3	2		T4	3
all_pins[7]	25401	1		T2	3		T3	2		T4	3
all_pins[8]	25401	1		T2	3		T3	2		T4	3
all_pins[9]	25401	1		T2	3		T3	2		T4	3
all_pins[10]	25401	1		T2	3		T3	2		T4	3
all_pins[11]	25401	1		T2	3		T3	2		T4	3
all_pins[12]	25401	1		T2	3		T3	2		T4	3
all_pins[13]	25401	1		T2	3		T3	2		T4	3
all_pins[14]	25401	1		T2	3		T3	2		T4	3
all_pins[15]	25401	1		T2	3		T3	2		T4	3
all_pins[16]	25401	1		T2	3		T3	2		T4	3
all_pins[17]	25401	1		T2	3		T3	2		T4	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	455917	1		T2	54		T3	36		T4	54
values[0x1]	1301	1		T10	1		T11	1		T17	1
transitions[0x0=>0x1]	1006	1		T10	1		T11	1		T17	1
transitions[0x1=>0x0]	1018	1		T10	1		T11	1		T17	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	25248	1		T2	3		T3	2		T4	3
all_pins[0]	values[0x1]	153	1		T10	1		T17	1		T46	1
all_pins[0]	transitions[0x0=>0x1]	135	1		T10	1		T17	1		T46	1
all_pins[0]	transitions[0x1=>0x0]	148	1		T11	1		T37	1		T47	1
all_pins[1]	values[0x0]	25235	1		T2	3		T3	2		T4	3
all_pins[1]	values[0x1]	166	1		T11	1		T37	1		T47	1
all_pins[1]	transitions[0x0=>0x1]	150	1		T11	1		T37	1		T47	1
all_pins[1]	transitions[0x1=>0x0]	49	1		T60	1		T62	1		T64	1
all_pins[2]	values[0x0]	25336	1		T2	3		T3	2		T4	3
all_pins[2]	values[0x1]	65	1		T60	2		T61	2		T62	2
all_pins[2]	transitions[0x0=>0x1]	47	1		T60	2		T61	1		T62	2
all_pins[2]	transitions[0x1=>0x0]	52	1		T63	4		T290	3		T291	2
all_pins[3]	values[0x0]	25331	1		T2	3		T3	2		T4	3
all_pins[3]	values[0x1]	70	1		T61	1		T63	4		T294	2
all_pins[3]	transitions[0x0=>0x1]	54	1		T61	1		T63	1		T294	2
all_pins[3]	transitions[0x1=>0x0]	45	1		T60	2		T61	2		T62	1
all_pins[4]	values[0x0]	25340	1		T2	3		T3	2		T4	3
all_pins[4]	values[0x1]	61	1		T60	2		T61	2		T62	1
all_pins[4]	transitions[0x0=>0x1]	45	1		T60	2		T62	1		T63	1
all_pins[4]	transitions[0x1=>0x0]	42	1		T62	2		T290	3		T292	1
all_pins[5]	values[0x0]	25343	1		T2	3		T3	2		T4	3
all_pins[5]	values[0x1]	58	1		T61	2		T62	2		T63	2
all_pins[5]	transitions[0x0=>0x1]	41	1		T61	2		T62	2		T290	4
all_pins[5]	transitions[0x1=>0x0]	55	1		T60	3		T64	3		T294	2
all_pins[6]	values[0x0]	25329	1		T2	3		T3	2		T4	3
all_pins[6]	values[0x1]	72	1		T60	3		T63	2		T64	3
all_pins[6]	transitions[0x0=>0x1]	50	1		T60	1		T63	2		T64	3
all_pins[6]	transitions[0x1=>0x0]	34	1		T61	1		T62	1		T294	2
all_pins[7]	values[0x0]	25345	1		T2	3		T3	2		T4	3
all_pins[7]	values[0x1]	56	1		T60	2		T61	1		T62	1
all_pins[7]	transitions[0x0=>0x1]	43	1		T60	2		T61	1		T62	1
all_pins[7]	transitions[0x1=>0x0]	41	1		T62	4		T63	1		T294	1
all_pins[8]	values[0x0]	25347	1		T2	3		T3	2		T4	3
all_pins[8]	values[0x1]	54	1		T62	4		T63	1		T294	2
all_pins[8]	transitions[0x0=>0x1]	45	1		T62	4		T63	1		T294	2
all_pins[8]	transitions[0x1=>0x0]	47	1		T61	3		T63	2		T64	3
all_pins[9]	values[0x0]	25345	1		T2	3		T3	2		T4	3
all_pins[9]	values[0x1]	56	1		T61	3		T63	2		T64	3
all_pins[9]	transitions[0x0=>0x1]	35	1		T61	1		T63	2		T64	1
all_pins[9]	transitions[0x1=>0x0]	47	1		T62	1		T63	1		T64	1
all_pins[10]	values[0x0]	25333	1		T2	3		T3	2		T4	3
all_pins[10]	values[0x1]	68	1		T61	2		T62	1		T63	1
all_pins[10]	transitions[0x0=>0x1]	50	1		T63	1		T64	3		T290	1
all_pins[10]	transitions[0x1=>0x0]	41	1		T62	1		T64	1		T294	1
all_pins[11]	values[0x0]	25342	1		T2	3		T3	2		T4	3
all_pins[11]	values[0x1]	59	1		T61	2		T62	2		T64	1
all_pins[11]	transitions[0x0=>0x1]	43	1		T61	2		T62	1		T64	1
all_pins[11]	transitions[0x1=>0x0]	48	1		T62	1		T63	3		T294	3
all_pins[12]	values[0x0]	25337	1		T2	3		T3	2		T4	3
all_pins[12]	values[0x1]	64	1		T62	2		T63	3		T294	3
all_pins[12]	transitions[0x0=>0x1]	40	1		T62	1		T63	2		T294	2
all_pins[12]	transitions[0x1=>0x0]	50	1		T60	1		T63	2		T64	1
all_pins[13]	values[0x0]	25327	1		T2	3		T3	2		T4	3
all_pins[13]	values[0x1]	74	1		T60	1		T62	1		T63	3
all_pins[13]	transitions[0x0=>0x1]	63	1		T60	1		T62	1		T63	3
all_pins[13]	transitions[0x1=>0x0]	47	1		T60	1		T61	2		T62	3
all_pins[14]	values[0x0]	25343	1		T2	3		T3	2		T4	3
all_pins[14]	values[0x1]	58	1		T60	1		T61	2		T62	3
all_pins[14]	transitions[0x0=>0x1]	45	1		T60	1		T61	2		T62	1
all_pins[14]	transitions[0x1=>0x0]	30	1		T62	2		T63	1		T290	2
all_pins[15]	values[0x0]	25358	1		T2	3		T3	2		T4	3
all_pins[15]	values[0x1]	43	1		T62	4		T63	1		T64	1
all_pins[15]	transitions[0x0=>0x1]	35	1		T62	3		T63	1		T290	3
all_pins[15]	transitions[0x1=>0x0]	59	1		T60	1		T63	2		T294	2
all_pins[16]	values[0x0]	25334	1		T2	3		T3	2		T4	3
all_pins[16]	values[0x1]	67	1		T60	1		T62	1		T63	2
all_pins[16]	transitions[0x0=>0x1]	48	1		T60	1		T62	1		T63	1
all_pins[16]	transitions[0x1=>0x0]	38	1		T60	1		T64	2		T294	1
all_pins[17]	values[0x0]	25344	1		T2	3		T3	2		T4	3
all_pins[17]	values[0x1]	57	1		T60	1		T63	1		T64	2
all_pins[17]	transitions[0x0=>0x1]	37	1		T63	1		T64	1		T294	2
all_pins[17]	transitions[0x1=>0x0]	145	1		T10	1		T17	1		T46	1