Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	272	1		T60	4		T61	4		T62	7
all_values[1]	272	1		T60	4		T61	4		T62	7
all_values[2]	272	1		T60	4		T61	4		T62	7
all_values[3]	272	1		T60	4		T61	4		T62	7
all_values[4]	272	1		T60	4		T61	4		T62	7
all_values[5]	272	1		T60	4		T61	4		T62	7
all_values[6]	272	1		T60	4		T61	4		T62	7
all_values[7]	272	1		T60	4		T61	4		T62	7
all_values[8]	272	1		T60	4		T61	4		T62	7
all_values[9]	272	1		T60	4		T61	4		T62	7
all_values[10]	272	1		T60	4		T61	4		T62	7
all_values[11]	272	1		T60	4		T61	4		T62	7
all_values[12]	272	1		T60	4		T61	4		T62	7
all_values[13]	272	1		T60	4		T61	4		T62	7
all_values[14]	272	1		T60	4		T61	4		T62	7
all_values[15]	272	1		T60	4		T61	4		T62	7
all_values[16]	272	1		T60	4		T61	4		T62	7
all_values[17]	272	1		T60	4		T61	4		T62	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2685	1		T60	33		T61	41		T62	72
auto[1]	2211	1		T60	39		T61	31		T62	54

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	922	1		T60	16		T61	13		T62	16
auto[1]	3974	1		T60	56		T61	59		T62	110

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2934	1		T60	47		T61	44		T62	74
auto[1]	1962	1		T60	25		T61	28		T62	52

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	26	1		T61	2		T62	2		T63	1
all_values[0]	auto[0]	auto[0]	auto[1]	60	1		T60	3		T62	2		T63	1
all_values[0]	auto[0]	auto[1]	auto[0]	13	1		T62	1		T291	1		T298	5
all_values[0]	auto[0]	auto[1]	auto[1]	50	1		T61	1		T62	1		T63	2
all_values[0]	auto[1]	auto[0]	auto[1]	73	1		T63	3		T64	2		T294	4
all_values[0]	auto[1]	auto[1]	auto[1]	50	1		T60	1		T61	1		T62	1
all_values[1]	auto[0]	auto[0]	auto[0]	30	1		T60	1		T64	1		T299	1
all_values[1]	auto[0]	auto[0]	auto[1]	49	1		T63	2		T294	3		T290	1
all_values[1]	auto[0]	auto[1]	auto[0]	27	1		T60	1		T63	1		T64	1
all_values[1]	auto[0]	auto[1]	auto[1]	47	1		T60	1		T61	1		T62	2
all_values[1]	auto[1]	auto[0]	auto[1]	62	1		T61	1		T62	2		T63	2
all_values[1]	auto[1]	auto[1]	auto[1]	57	1		T60	1		T61	2		T62	3
all_values[2]	auto[0]	auto[0]	auto[0]	24	1		T61	1		T294	3		T295	1
all_values[2]	auto[0]	auto[0]	auto[1]	67	1		T60	1		T61	2		T62	2
all_values[2]	auto[0]	auto[1]	auto[0]	16	1		T60	1		T64	2		T294	2
all_values[2]	auto[0]	auto[1]	auto[1]	59	1		T60	1		T62	2		T63	1
all_values[2]	auto[1]	auto[0]	auto[1]	57	1		T60	1		T62	1		T63	3
all_values[2]	auto[1]	auto[1]	auto[1]	49	1		T61	1		T62	2		T63	1
all_values[3]	auto[0]	auto[0]	auto[0]	34	1		T60	1		T63	1		T64	1
all_values[3]	auto[0]	auto[0]	auto[1]	57	1		T60	1		T62	2		T64	2
all_values[3]	auto[0]	auto[1]	auto[0]	18	1		T294	1		T291	1		T295	2
all_values[3]	auto[0]	auto[1]	auto[1]	55	1		T61	3		T62	2		T63	2
all_values[3]	auto[1]	auto[0]	auto[1]	63	1		T60	2		T61	1		T62	2
all_values[3]	auto[1]	auto[1]	auto[1]	45	1		T62	1		T63	2		T294	2
all_values[4]	auto[0]	auto[0]	auto[0]	26	1		T62	1		T64	2		T291	1
all_values[4]	auto[0]	auto[0]	auto[1]	57	1		T60	1		T61	1		T62	3
all_values[4]	auto[0]	auto[1]	auto[0]	21	1		T62	1		T294	1		T291	3
all_values[4]	auto[0]	auto[1]	auto[1]	52	1		T60	1		T61	1		T63	1
all_values[4]	auto[1]	auto[0]	auto[1]	69	1		T61	1		T62	2		T63	1
all_values[4]	auto[1]	auto[1]	auto[1]	47	1		T60	2		T61	1		T63	3
all_values[5]	auto[0]	auto[0]	auto[0]	25	1		T61	1		T64	3		T294	1
all_values[5]	auto[0]	auto[0]	auto[1]	69	1		T63	2		T291	1		T297	1
all_values[5]	auto[0]	auto[1]	auto[0]	17	1		T64	1		T294	4		T296	1
all_values[5]	auto[0]	auto[1]	auto[1]	57	1		T60	3		T61	1		T62	2
all_values[5]	auto[1]	auto[0]	auto[1]	69	1		T60	1		T62	3		T63	3
all_values[5]	auto[1]	auto[1]	auto[1]	35	1		T61	2		T62	2		T294	1
all_values[6]	auto[0]	auto[0]	auto[0]	35	1		T61	1		T62	1		T64	1
all_values[6]	auto[0]	auto[0]	auto[1]	56	1		T61	2		T62	1		T63	1
all_values[6]	auto[0]	auto[1]	auto[0]	24	1		T296	2		T300	1		T301	1
all_values[6]	auto[0]	auto[1]	auto[1]	57	1		T60	1		T62	3		T63	2
all_values[6]	auto[1]	auto[0]	auto[1]	47	1		T60	1		T61	1		T62	1
all_values[6]	auto[1]	auto[1]	auto[1]	53	1		T60	2		T62	1		T63	1
all_values[7]	auto[0]	auto[0]	auto[0]	34	1		T63	2		T291	1		T296	1
all_values[7]	auto[0]	auto[0]	auto[1]	54	1		T62	5		T63	2		T64	2
all_values[7]	auto[0]	auto[1]	auto[0]	22	1		T60	1		T294	2		T291	1
all_values[7]	auto[0]	auto[1]	auto[1]	55	1		T60	1		T61	2		T290	2
all_values[7]	auto[1]	auto[0]	auto[1]	55	1		T61	1		T62	1		T63	2
all_values[7]	auto[1]	auto[1]	auto[1]	52	1		T60	2		T61	1		T62	1
all_values[8]	auto[0]	auto[0]	auto[0]	27	1		T61	1		T64	1		T297	1
all_values[8]	auto[0]	auto[0]	auto[1]	69	1		T60	1		T63	1		T64	1
all_values[8]	auto[0]	auto[1]	auto[0]	18	1		T60	2		T64	1		T294	1
all_values[8]	auto[0]	auto[1]	auto[1]	54	1		T61	2		T62	1		T63	3
all_values[8]	auto[1]	auto[0]	auto[1]	53	1		T61	1		T62	2		T63	3
all_values[8]	auto[1]	auto[1]	auto[1]	51	1		T60	1		T62	4		T294	2
all_values[9]	auto[0]	auto[0]	auto[0]	44	1		T60	1		T61	1		T62	1
all_values[9]	auto[0]	auto[0]	auto[1]	48	1		T60	2		T62	2		T63	1
all_values[9]	auto[0]	auto[1]	auto[0]	27	1		T294	2		T296	1		T297	1
all_values[9]	auto[0]	auto[1]	auto[1]	57	1		T61	2		T62	3		T63	2
all_values[9]	auto[1]	auto[0]	auto[1]	49	1		T60	1		T63	1		T64	1
all_values[9]	auto[1]	auto[1]	auto[1]	47	1		T61	1		T62	1		T63	1
all_values[10]	auto[0]	auto[0]	auto[0]	24	1		T62	1		T294	2		T297	2
all_values[10]	auto[0]	auto[0]	auto[1]	66	1		T60	3		T62	2		T63	4
all_values[10]	auto[0]	auto[1]	auto[0]	12	1		T296	2		T295	2		T300	1
all_values[10]	auto[0]	auto[1]	auto[1]	55	1		T61	1		T62	2		T64	1
all_values[10]	auto[1]	auto[0]	auto[1]	63	1		T61	2		T62	2		T63	2
all_values[10]	auto[1]	auto[1]	auto[1]	52	1		T60	1		T61	1		T63	1
all_values[11]	auto[0]	auto[0]	auto[0]	40	1		T60	2		T61	1		T63	3
all_values[11]	auto[0]	auto[0]	auto[1]	51	1		T62	1		T63	1		T64	1
all_values[11]	auto[0]	auto[1]	auto[0]	12	1		T60	2		T63	2		T64	1
all_values[11]	auto[0]	auto[1]	auto[1]	61	1		T61	2		T62	3		T294	3
all_values[11]	auto[1]	auto[0]	auto[1]	59	1		T61	1		T62	3		T63	1
all_values[11]	auto[1]	auto[1]	auto[1]	49	1		T64	2		T290	1		T291	2
all_values[12]	auto[0]	auto[0]	auto[0]	27	1		T291	1		T296	2		T297	1
all_values[12]	auto[0]	auto[0]	auto[1]	52	1		T61	1		T62	3		T63	3
all_values[12]	auto[0]	auto[1]	auto[0]	17	1		T64	2		T295	2		T293	2
all_values[12]	auto[0]	auto[1]	auto[1]	58	1		T60	3		T63	1		T294	3
all_values[12]	auto[1]	auto[0]	auto[1]	70	1		T60	1		T61	3		T62	2
all_values[12]	auto[1]	auto[1]	auto[1]	48	1		T62	2		T63	3		T64	1
all_values[13]	auto[0]	auto[0]	auto[0]	29	1		T62	2		T290	1		T291	1
all_values[13]	auto[0]	auto[0]	auto[1]	46	1		T60	1		T61	1		T64	2
all_values[13]	auto[0]	auto[1]	auto[0]	19	1		T62	1		T290	1		T291	3
all_values[13]	auto[0]	auto[1]	auto[1]	63	1		T61	2		T62	2		T63	3
all_values[13]	auto[1]	auto[0]	auto[1]	58	1		T60	2		T61	1		T62	1
all_values[13]	auto[1]	auto[1]	auto[1]	57	1		T60	1		T62	1		T63	3
all_values[14]	auto[0]	auto[0]	auto[0]	34	1		T60	1		T61	2		T64	1
all_values[14]	auto[0]	auto[0]	auto[1]	56	1		T60	1		T62	1		T63	3
all_values[14]	auto[0]	auto[1]	auto[0]	14	1		T294	2		T296	1		T293	1
all_values[14]	auto[0]	auto[1]	auto[1]	52	1		T61	1		T62	3		T63	1
all_values[14]	auto[1]	auto[0]	auto[1]	71	1		T62	2		T63	2		T294	3
all_values[14]	auto[1]	auto[1]	auto[1]	45	1		T60	2		T61	1		T62	1
all_values[15]	auto[0]	auto[0]	auto[0]	36	1		T60	1		T61	1		T63	1
all_values[15]	auto[0]	auto[0]	auto[1]	61	1		T60	1		T61	2		T62	2
all_values[15]	auto[0]	auto[1]	auto[0]	30	1		T60	1		T291	2		T296	2
all_values[15]	auto[0]	auto[1]	auto[1]	46	1		T62	3		T294	2		T290	2
all_values[15]	auto[1]	auto[0]	auto[1]	61	1		T62	2		T63	3		T294	3
all_values[15]	auto[1]	auto[1]	auto[1]	38	1		T60	1		T61	1		T64	2
all_values[16]	auto[0]	auto[0]	auto[0]	29	1		T61	1		T62	1		T295	3
all_values[16]	auto[0]	auto[0]	auto[1]	54	1		T60	1		T61	2		T62	1
all_values[16]	auto[0]	auto[1]	auto[0]	30	1		T60	1		T62	1		T64	1
all_values[16]	auto[0]	auto[1]	auto[1]	54	1		T60	1		T63	3		T64	2
all_values[16]	auto[1]	auto[0]	auto[1]	59	1		T61	1		T62	4		T63	1
all_values[16]	auto[1]	auto[1]	auto[1]	46	1		T60	1		T63	2		T64	1
all_values[17]	auto[0]	auto[0]	auto[0]	39	1		T61	1		T62	2		T290	1
all_values[17]	auto[0]	auto[0]	auto[1]	55	1		T60	1		T61	1		T62	2
all_values[17]	auto[0]	auto[1]	auto[0]	22	1		T62	1		T294	2		T291	1
all_values[17]	auto[0]	auto[1]	auto[1]	53	1		T60	2		T63	1		T64	1
all_values[17]	auto[1]	auto[0]	auto[1]	57	1		T61	2		T62	2		T63	2
all_values[17]	auto[1]	auto[1]	auto[1]	46	1		T60	1		T63	1		T64	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal