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 LINE       9294
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T34,T35,T8
1	1	0	Covered	T53,T210,T237
1	1	1	Covered	T34,T35,T36

 LINE       9313
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T3,T8,T9
1	1	0	Covered	T53,T238,T247
1	1	1	Covered	T3,T8,T9

 LINE       9326
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T78,T13,T14
1	1	0	Covered	T53,T248,T244
1	1	1	Covered	T1,T58,T59

 LINE       9329
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T48,T49,T50
1	1	0	Covered	T237,T238,T245
1	1	1	Covered	T48,T49,T50

 LINE       9336
 EXPRESSION (addr_hit[39] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T9,T13,T14
1	1	0	Not Covered
1	1	1	Covered	T1,T58,T59

 LINE       9337
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T9,T13,T14
1	1	0	Covered	T210,T237,T241
1	1	1	Covered	T1,T58,T59

 LINE       9350
 EXPRESSION (addr_hit[40] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T87,T13,T14
1	1	0	Not Covered
1	1	1	Covered	T1,T58,T59

 LINE       9351
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T87,T13,T14
1	1	0	Covered	T53,T216,T237
1	1	1	Covered	T1,T58,T59

 LINE       9362
 EXPRESSION (addr_hit[41] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T13,T14,T219
1	1	0	Not Covered
1	1	1	Covered	T1,T58,T59

 LINE       9363
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T13,T14,T219
1	1	0	Covered	T53,T210,T237
1	1	1	Covered	T1,T58,T59

 LINE       9368
 EXPRESSION (addr_hit[42] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T87,T13,T14
1	1	0	Not Covered
1	1	1	Covered	T1,T58,T59

 LINE       9369
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T87,T13,T14
1	1	0	Covered	T53,T210,T237
1	1	1	Covered	T1,T58,T59

 LINE       9881
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Unreachable
1	0	Covered	T1,T58,T59