Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.61 96.24 88.96 96.90 50.00 94.22 97.35 96.58


Total test records in report: 1481
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T1331 /workspace/coverage/default/18.usbdev_in_iso.3686600850 Apr 25 02:32:41 PM PDT 24 Apr 25 02:32:50 PM PDT 24 8412926693 ps
T1332 /workspace/coverage/default/28.usbdev_min_length_out_transaction.656250006 Apr 25 02:34:00 PM PDT 24 Apr 25 02:34:10 PM PDT 24 8373095317 ps
T1333 /workspace/coverage/default/29.usbdev_min_length_out_transaction.4025438053 Apr 25 02:34:10 PM PDT 24 Apr 25 02:34:20 PM PDT 24 8385305033 ps
T1334 /workspace/coverage/default/16.usbdev_pkt_buffer.2303234427 Apr 25 02:32:25 PM PDT 24 Apr 25 02:33:24 PM PDT 24 28326618192 ps
T1335 /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.283027124 Apr 25 02:29:47 PM PDT 24 Apr 25 02:29:56 PM PDT 24 8376242791 ps
T1336 /workspace/coverage/default/10.usbdev_pending_in_trans.3342303944 Apr 25 02:31:22 PM PDT 24 Apr 25 02:31:32 PM PDT 24 8393606452 ps
T1337 /workspace/coverage/default/26.usbdev_stall_trans.30362966 Apr 25 02:33:47 PM PDT 24 Apr 25 02:33:55 PM PDT 24 8396930914 ps
T1338 /workspace/coverage/default/45.usbdev_max_length_out_transaction.1525600040 Apr 25 02:36:05 PM PDT 24 Apr 25 02:36:14 PM PDT 24 8425061856 ps
T1339 /workspace/coverage/default/2.usbdev_stall_priority_over_nak.2888161239 Apr 25 02:29:18 PM PDT 24 Apr 25 02:29:27 PM PDT 24 8384051185 ps
T1340 /workspace/coverage/default/8.usbdev_enable.1235398682 Apr 25 02:30:48 PM PDT 24 Apr 25 02:30:59 PM PDT 24 8377466029 ps
T1341 /workspace/coverage/default/43.usbdev_phy_pins_sense.60193060 Apr 25 02:35:53 PM PDT 24 Apr 25 02:35:54 PM PDT 24 43050191 ps
T1342 /workspace/coverage/default/8.usbdev_in_iso.1348291325 Apr 25 02:30:56 PM PDT 24 Apr 25 02:31:06 PM PDT 24 8381070652 ps
T1343 /workspace/coverage/default/39.usbdev_out_stall.1094378858 Apr 25 02:35:27 PM PDT 24 Apr 25 02:35:36 PM PDT 24 8403358500 ps
T1344 /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.3405114716 Apr 25 02:36:07 PM PDT 24 Apr 25 02:36:17 PM PDT 24 8371337730 ps
T1345 /workspace/coverage/default/13.usbdev_pkt_buffer.3468274370 Apr 25 02:31:50 PM PDT 24 Apr 25 02:32:47 PM PDT 24 26804941253 ps
T1346 /workspace/coverage/default/20.usbdev_enable.4112007521 Apr 25 02:32:54 PM PDT 24 Apr 25 02:33:03 PM PDT 24 8382292995 ps
T1347 /workspace/coverage/default/1.usbdev_phy_pins_sense.2871855178 Apr 25 02:29:01 PM PDT 24 Apr 25 02:29:03 PM PDT 24 48014466 ps
T1348 /workspace/coverage/default/35.usbdev_phy_pins_sense.2880362139 Apr 25 02:34:58 PM PDT 24 Apr 25 02:35:00 PM PDT 24 31700732 ps
T1349 /workspace/coverage/default/47.usbdev_pkt_received.3868700733 Apr 25 02:36:22 PM PDT 24 Apr 25 02:36:32 PM PDT 24 8374070715 ps
T1350 /workspace/coverage/default/40.usbdev_stall_priority_over_nak.2680246742 Apr 25 02:35:34 PM PDT 24 Apr 25 02:35:43 PM PDT 24 8406683135 ps
T1351 /workspace/coverage/default/21.usbdev_smoke.351474930 Apr 25 02:33:01 PM PDT 24 Apr 25 02:33:10 PM PDT 24 8445155813 ps
T1352 /workspace/coverage/default/30.min_length_in_transaction.2446850170 Apr 25 02:34:24 PM PDT 24 Apr 25 02:34:32 PM PDT 24 8373058111 ps
T1353 /workspace/coverage/default/24.usbdev_in_stall.4055595802 Apr 25 02:33:33 PM PDT 24 Apr 25 02:33:44 PM PDT 24 8388129310 ps
T1354 /workspace/coverage/default/4.usbdev_setup_trans_ignored.1997437495 Apr 25 02:29:48 PM PDT 24 Apr 25 02:29:58 PM PDT 24 8373128004 ps
T1355 /workspace/coverage/default/45.usbdev_pkt_received.1406799645 Apr 25 02:36:11 PM PDT 24 Apr 25 02:36:21 PM PDT 24 8410685255 ps
T1356 /workspace/coverage/default/24.usbdev_stall_trans.277763404 Apr 25 02:33:31 PM PDT 24 Apr 25 02:33:41 PM PDT 24 8400789696 ps
T1357 /workspace/coverage/default/31.usbdev_setup_stage.804434219 Apr 25 02:34:27 PM PDT 24 Apr 25 02:34:38 PM PDT 24 8376385981 ps
T1358 /workspace/coverage/default/48.usbdev_smoke.1532128299 Apr 25 02:36:22 PM PDT 24 Apr 25 02:36:31 PM PDT 24 8431169201 ps
T1359 /workspace/coverage/default/30.usbdev_pkt_sent.3538849718 Apr 25 02:34:21 PM PDT 24 Apr 25 02:34:30 PM PDT 24 8426539254 ps
T1360 /workspace/coverage/default/24.max_length_in_transaction.1103570964 Apr 25 02:33:34 PM PDT 24 Apr 25 02:33:45 PM PDT 24 8464645519 ps
T1361 /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.4014043097 Apr 25 02:30:40 PM PDT 24 Apr 25 02:30:51 PM PDT 24 8455255804 ps
T1362 /workspace/coverage/default/15.usbdev_stall_priority_over_nak.860812331 Apr 25 02:32:13 PM PDT 24 Apr 25 02:32:22 PM PDT 24 8398336143 ps
T1363 /workspace/coverage/default/48.usbdev_in_iso.2423280357 Apr 25 02:36:29 PM PDT 24 Apr 25 02:36:40 PM PDT 24 8437928302 ps
T1364 /workspace/coverage/default/21.usbdev_in_stall.495729414 Apr 25 02:33:07 PM PDT 24 Apr 25 02:33:16 PM PDT 24 8364275917 ps
T1365 /workspace/coverage/default/4.usbdev_pkt_received.1740416175 Apr 25 02:29:46 PM PDT 24 Apr 25 02:29:54 PM PDT 24 8405657416 ps
T1366 /workspace/coverage/default/12.max_length_in_transaction.1870621777 Apr 25 02:31:42 PM PDT 24 Apr 25 02:31:53 PM PDT 24 8477420563 ps
T1367 /workspace/coverage/default/42.usbdev_av_buffer.2183534915 Apr 25 02:35:44 PM PDT 24 Apr 25 02:35:53 PM PDT 24 8414928918 ps
T1368 /workspace/coverage/default/47.usbdev_stall_trans.1575420834 Apr 25 02:36:20 PM PDT 24 Apr 25 02:36:30 PM PDT 24 8418295141 ps
T1369 /workspace/coverage/default/20.max_length_in_transaction.3398892078 Apr 25 02:33:00 PM PDT 24 Apr 25 02:33:09 PM PDT 24 8461657859 ps
T1370 /workspace/coverage/default/26.usbdev_in_stall.1418036451 Apr 25 02:33:44 PM PDT 24 Apr 25 02:33:53 PM PDT 24 8365621872 ps
T1371 /workspace/coverage/default/10.usbdev_random_length_out_trans.3769449130 Apr 25 02:31:19 PM PDT 24 Apr 25 02:31:29 PM PDT 24 8413670578 ps
T1372 /workspace/coverage/default/20.usbdev_in_trans.1966598805 Apr 25 02:32:54 PM PDT 24 Apr 25 02:33:03 PM PDT 24 8426515787 ps
T1373 /workspace/coverage/default/29.max_length_in_transaction.4204666907 Apr 25 02:34:17 PM PDT 24 Apr 25 02:34:26 PM PDT 24 8505809994 ps
T1374 /workspace/coverage/default/42.usbdev_setup_trans_ignored.2961373631 Apr 25 02:35:45 PM PDT 24 Apr 25 02:35:55 PM PDT 24 8369327144 ps
T1375 /workspace/coverage/default/16.usbdev_pkt_received.2213348921 Apr 25 02:32:28 PM PDT 24 Apr 25 02:32:38 PM PDT 24 8378513252 ps
T1376 /workspace/coverage/default/9.usbdev_out_trans_nak.900189233 Apr 25 02:30:56 PM PDT 24 Apr 25 02:31:06 PM PDT 24 8420430921 ps
T1377 /workspace/coverage/default/49.usbdev_setup_trans_ignored.2981714098 Apr 25 02:36:26 PM PDT 24 Apr 25 02:36:35 PM PDT 24 8367569904 ps
T1378 /workspace/coverage/default/38.usbdev_enable.218241377 Apr 25 02:35:24 PM PDT 24 Apr 25 02:35:33 PM PDT 24 8374436383 ps
T1379 /workspace/coverage/default/27.usbdev_in_iso.1130548220 Apr 25 02:34:03 PM PDT 24 Apr 25 02:34:14 PM PDT 24 8389245608 ps
T1380 /workspace/coverage/default/33.usbdev_in_iso.898170657 Apr 25 02:34:46 PM PDT 24 Apr 25 02:34:55 PM PDT 24 8407422080 ps
T1381 /workspace/coverage/default/3.usbdev_pending_in_trans.3673595497 Apr 25 02:29:31 PM PDT 24 Apr 25 02:29:39 PM PDT 24 8385683143 ps
T1382 /workspace/coverage/default/41.usbdev_in_trans.1878933113 Apr 25 02:35:41 PM PDT 24 Apr 25 02:35:52 PM PDT 24 8436574359 ps
T1383 /workspace/coverage/default/28.usbdev_stall_trans.2866909885 Apr 25 02:34:10 PM PDT 24 Apr 25 02:34:20 PM PDT 24 8394000665 ps
T1384 /workspace/coverage/default/21.min_length_in_transaction.1571453657 Apr 25 02:33:13 PM PDT 24 Apr 25 02:33:22 PM PDT 24 8375211796 ps
T1385 /workspace/coverage/default/29.usbdev_pkt_buffer.4272339549 Apr 25 02:34:13 PM PDT 24 Apr 25 02:34:45 PM PDT 24 17812222706 ps
T1386 /workspace/coverage/default/48.usbdev_nak_trans.2217934702 Apr 25 02:36:22 PM PDT 24 Apr 25 02:36:32 PM PDT 24 8441113970 ps
T1 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.4257380407 Apr 25 12:34:36 PM PDT 24 Apr 25 12:34:41 PM PDT 24 89973381 ps
T58 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3068892895 Apr 25 12:34:42 PM PDT 24 Apr 25 12:34:47 PM PDT 24 226876825 ps
T59 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1858744172 Apr 25 12:34:34 PM PDT 24 Apr 25 12:34:42 PM PDT 24 1045264762 ps
T93 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.756592836 Apr 25 12:34:41 PM PDT 24 Apr 25 12:34:45 PM PDT 24 67073791 ps
T60 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2464270097 Apr 25 12:34:52 PM PDT 24 Apr 25 12:34:59 PM PDT 24 32260939 ps
T94 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3583545195 Apr 25 12:34:55 PM PDT 24 Apr 25 12:34:58 PM PDT 24 50574431 ps
T61 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.380461173 Apr 25 12:34:59 PM PDT 24 Apr 25 12:35:01 PM PDT 24 39141912 ps
T95 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.4078044069 Apr 25 12:34:36 PM PDT 24 Apr 25 12:34:41 PM PDT 24 96959555 ps
T51 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1258616600 Apr 25 12:34:50 PM PDT 24 Apr 25 12:34:53 PM PDT 24 72433850 ps
T96 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2952298097 Apr 25 12:34:57 PM PDT 24 Apr 25 12:35:00 PM PDT 24 89094549 ps
T97 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1201564367 Apr 25 12:35:05 PM PDT 24 Apr 25 12:35:08 PM PDT 24 84829504 ps
T98 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3157543998 Apr 25 12:34:41 PM PDT 24 Apr 25 12:34:47 PM PDT 24 458232233 ps
T52 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2618393721 Apr 25 12:35:05 PM PDT 24 Apr 25 12:35:10 PM PDT 24 545261586 ps
T279 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1863133753 Apr 25 12:34:56 PM PDT 24 Apr 25 12:34:59 PM PDT 24 54271267 ps
T53 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3414971233 Apr 25 12:34:55 PM PDT 24 Apr 25 12:35:00 PM PDT 24 226245185 ps
T280 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4204430787 Apr 25 12:34:49 PM PDT 24 Apr 25 12:34:52 PM PDT 24 43581995 ps
T211 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3709613863 Apr 25 12:34:54 PM PDT 24 Apr 25 12:35:00 PM PDT 24 561097109 ps
T62 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2933512023 Apr 25 12:35:09 PM PDT 24 Apr 25 12:35:13 PM PDT 24 26573496 ps
T210 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.515678035 Apr 25 12:34:51 PM PDT 24 Apr 25 12:34:55 PM PDT 24 173251558 ps
T212 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1872628295 Apr 25 12:35:13 PM PDT 24 Apr 25 12:35:20 PM PDT 24 187495102 ps
T63 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3711786257 Apr 25 12:34:59 PM PDT 24 Apr 25 12:35:01 PM PDT 24 52104464 ps
T249 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2305851663 Apr 25 12:34:51 PM PDT 24 Apr 25 12:34:54 PM PDT 24 95876240 ps
T64 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3861334612 Apr 25 12:34:54 PM PDT 24 Apr 25 12:34:56 PM PDT 24 30492238 ps
T250 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.405555909 Apr 25 12:34:38 PM PDT 24 Apr 25 12:34:44 PM PDT 24 86480593 ps
T216 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1778819258 Apr 25 12:34:53 PM PDT 24 Apr 25 12:34:56 PM PDT 24 94244598 ps
T294 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2552393993 Apr 25 12:35:02 PM PDT 24 Apr 25 12:35:04 PM PDT 24 38158857 ps
T1387 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2056066337 Apr 25 12:35:00 PM PDT 24 Apr 25 12:35:03 PM PDT 24 85655430 ps
T242 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.4236633441 Apr 25 12:34:48 PM PDT 24 Apr 25 12:34:50 PM PDT 24 75095094 ps
T215 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.996865322 Apr 25 12:34:44 PM PDT 24 Apr 25 12:34:50 PM PDT 24 324011768 ps
T290 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1428698867 Apr 25 12:34:35 PM PDT 24 Apr 25 12:34:40 PM PDT 24 32131471 ps
T291 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2303263980 Apr 25 12:34:58 PM PDT 24 Apr 25 12:35:00 PM PDT 24 43296661 ps
T1388 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.917877598 Apr 25 12:34:40 PM PDT 24 Apr 25 12:34:48 PM PDT 24 704664177 ps
T237 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1695456643 Apr 25 12:34:49 PM PDT 24 Apr 25 12:34:51 PM PDT 24 69712856 ps
T296 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.752898255 Apr 25 12:34:45 PM PDT 24 Apr 25 12:34:49 PM PDT 24 38996430 ps
T1389 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1424905129 Apr 25 12:34:35 PM PDT 24 Apr 25 12:34:43 PM PDT 24 167094729 ps
T1390 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.529417543 Apr 25 12:34:32 PM PDT 24 Apr 25 12:34:38 PM PDT 24 110193022 ps
T297 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.144095793 Apr 25 12:35:10 PM PDT 24 Apr 25 12:35:15 PM PDT 24 32623222 ps
T295 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3306176189 Apr 25 12:35:20 PM PDT 24 Apr 25 12:35:23 PM PDT 24 32729357 ps
T292 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3703695453 Apr 25 12:34:35 PM PDT 24 Apr 25 12:34:40 PM PDT 24 64434847 ps
T299 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2427779523 Apr 25 12:35:07 PM PDT 24 Apr 25 12:35:13 PM PDT 24 40843127 ps
T251 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1999569789 Apr 25 12:34:39 PM PDT 24 Apr 25 12:34:45 PM PDT 24 161318845 ps
T300 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2372315696 Apr 25 12:34:45 PM PDT 24 Apr 25 12:34:48 PM PDT 24 28590227 ps
T266 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1028943376 Apr 25 12:34:41 PM PDT 24 Apr 25 12:34:52 PM PDT 24 964474454 ps
T301 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2135630051 Apr 25 12:35:09 PM PDT 24 Apr 25 12:35:12 PM PDT 24 32869093 ps
T1391 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.582404499 Apr 25 12:35:05 PM PDT 24 Apr 25 12:35:06 PM PDT 24 31537514 ps
T1392 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2127327023 Apr 25 12:34:39 PM PDT 24 Apr 25 12:34:44 PM PDT 24 55731637 ps
T1393 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1566794417 Apr 25 12:34:38 PM PDT 24 Apr 25 12:34:43 PM PDT 24 63558247 ps
T1394 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.718562802 Apr 25 12:35:03 PM PDT 24 Apr 25 12:35:05 PM PDT 24 28986392 ps
T241 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.223691487 Apr 25 12:34:54 PM PDT 24 Apr 25 12:34:58 PM PDT 24 93179527 ps
T267 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1883863751 Apr 25 12:34:38 PM PDT 24 Apr 25 12:34:44 PM PDT 24 47582241 ps
T239 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2573276537 Apr 25 12:34:38 PM PDT 24 Apr 25 12:34:44 PM PDT 24 86532808 ps
T246 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.517361122 Apr 25 12:34:38 PM PDT 24 Apr 25 12:34:43 PM PDT 24 69667416 ps
T286 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3621342759 Apr 25 12:35:06 PM PDT 24 Apr 25 12:35:09 PM PDT 24 424344608 ps
T293 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1205484319 Apr 25 12:34:55 PM PDT 24 Apr 25 12:34:58 PM PDT 24 65440723 ps
T213 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3467435762 Apr 25 12:34:36 PM PDT 24 Apr 25 12:34:43 PM PDT 24 616287860 ps
T287 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2511149154 Apr 25 12:34:33 PM PDT 24 Apr 25 12:34:43 PM PDT 24 2182781928 ps
T288 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1806900572 Apr 25 12:34:51 PM PDT 24 Apr 25 12:34:58 PM PDT 24 717575890 ps
T1395 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.607208992 Apr 25 12:34:55 PM PDT 24 Apr 25 12:34:57 PM PDT 24 43555172 ps
T1396 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1216186874 Apr 25 12:34:47 PM PDT 24 Apr 25 12:34:50 PM PDT 24 51383479 ps
T214 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1798359294 Apr 25 12:34:37 PM PDT 24 Apr 25 12:34:46 PM PDT 24 582835459 ps
T308 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1175216487 Apr 25 12:34:40 PM PDT 24 Apr 25 12:34:46 PM PDT 24 363418227 ps
T306 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1926693177 Apr 25 12:34:50 PM PDT 24 Apr 25 12:34:54 PM PDT 24 226836983 ps
T289 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.584492399 Apr 25 12:34:49 PM PDT 24 Apr 25 12:34:51 PM PDT 24 82629426 ps
T268 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1368048547 Apr 25 12:34:35 PM PDT 24 Apr 25 12:34:48 PM PDT 24 2486715679 ps
T269 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.604959668 Apr 25 12:34:55 PM PDT 24 Apr 25 12:34:58 PM PDT 24 55272896 ps
T1397 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1765929799 Apr 25 12:35:08 PM PDT 24 Apr 25 12:35:10 PM PDT 24 50952028 ps
T240 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3528163308 Apr 25 12:34:55 PM PDT 24 Apr 25 12:35:00 PM PDT 24 80464942 ps
T1398 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.860435018 Apr 25 12:34:45 PM PDT 24 Apr 25 12:34:50 PM PDT 24 174914270 ps
T238 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.4098583293 Apr 25 12:34:56 PM PDT 24 Apr 25 12:35:02 PM PDT 24 304209593 ps
T1399 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3019186438 Apr 25 12:34:54 PM PDT 24 Apr 25 12:34:57 PM PDT 24 40006330 ps
T1400 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3771145183 Apr 25 12:34:58 PM PDT 24 Apr 25 12:35:01 PM PDT 24 97938562 ps
T270 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3898991289 Apr 25 12:34:38 PM PDT 24 Apr 25 12:34:47 PM PDT 24 1030309717 ps
T1401 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1633226304 Apr 25 12:34:38 PM PDT 24 Apr 25 12:34:44 PM PDT 24 189654447 ps
T307 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.409447328 Apr 25 12:34:48 PM PDT 24 Apr 25 12:34:54 PM PDT 24 968597819 ps
T1402 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1696977448 Apr 25 12:34:38 PM PDT 24 Apr 25 12:34:45 PM PDT 24 237015710 ps
T1403 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3359488149 Apr 25 12:34:34 PM PDT 24 Apr 25 12:34:39 PM PDT 24 70939593 ps
T1404 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.772159149 Apr 25 12:35:40 PM PDT 24 Apr 25 12:35:43 PM PDT 24 36956566 ps
T245 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2706615582 Apr 25 12:34:44 PM PDT 24 Apr 25 12:34:50 PM PDT 24 300026660 ps
T1405 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1057604394 Apr 25 12:34:42 PM PDT 24 Apr 25 12:34:46 PM PDT 24 143784430 ps
T1406 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.347186687 Apr 25 12:34:57 PM PDT 24 Apr 25 12:35:00 PM PDT 24 53452721 ps
T1407 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3513165 Apr 25 12:34:51 PM PDT 24 Apr 25 12:34:53 PM PDT 24 38755258 ps
T298 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.4062968277 Apr 25 12:35:04 PM PDT 24 Apr 25 12:35:06 PM PDT 24 91377984 ps
T1408 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.814464821 Apr 25 12:34:36 PM PDT 24 Apr 25 12:34:41 PM PDT 24 85570862 ps
T1409 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2135601679 Apr 25 12:34:51 PM PDT 24 Apr 25 12:34:54 PM PDT 24 91884903 ps
T1410 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1828065325 Apr 25 12:34:51 PM PDT 24 Apr 25 12:34:54 PM PDT 24 87049035 ps
T1411 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3548186565 Apr 25 12:34:37 PM PDT 24 Apr 25 12:34:42 PM PDT 24 39141048 ps
T1412 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2924501041 Apr 25 12:34:33 PM PDT 24 Apr 25 12:34:36 PM PDT 24 29067513 ps
T247 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1821619777 Apr 25 12:35:14 PM PDT 24 Apr 25 12:35:21 PM PDT 24 195376819 ps
T248 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.291488712 Apr 25 12:34:42 PM PDT 24 Apr 25 12:34:47 PM PDT 24 138911189 ps
T271 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2263121206 Apr 25 12:34:51 PM PDT 24 Apr 25 12:34:54 PM PDT 24 36300176 ps
T1413 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.79877038 Apr 25 12:34:40 PM PDT 24 Apr 25 12:34:45 PM PDT 24 42238140 ps
T1414 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.4269429172 Apr 25 12:34:54 PM PDT 24 Apr 25 12:34:58 PM PDT 24 73391316 ps
T302 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3365070360 Apr 25 12:34:38 PM PDT 24 Apr 25 12:34:46 PM PDT 24 322074503 ps
T244 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2858210615 Apr 25 12:34:33 PM PDT 24 Apr 25 12:34:38 PM PDT 24 244212441 ps
T1415 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.4261133064 Apr 25 12:34:35 PM PDT 24 Apr 25 12:34:40 PM PDT 24 98774625 ps
T309 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.116141212 Apr 25 12:35:07 PM PDT 24 Apr 25 12:35:18 PM PDT 24 484644351 ps
T272 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1580861864 Apr 25 12:34:35 PM PDT 24 Apr 25 12:34:39 PM PDT 24 63907060 ps
T1416 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.98148412 Apr 25 12:35:12 PM PDT 24 Apr 25 12:35:18 PM PDT 24 40103107 ps
T273 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.623958972 Apr 25 12:34:55 PM PDT 24 Apr 25 12:34:58 PM PDT 24 49541550 ps
T1417 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2971571984 Apr 25 12:34:42 PM PDT 24 Apr 25 12:34:46 PM PDT 24 42044528 ps
T1418 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.91542192 Apr 25 12:34:37 PM PDT 24 Apr 25 12:34:41 PM PDT 24 27844447 ps
T1419 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3310765260 Apr 25 12:34:57 PM PDT 24 Apr 25 12:35:00 PM PDT 24 30483935 ps
T1420 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.289795694 Apr 25 12:35:05 PM PDT 24 Apr 25 12:35:08 PM PDT 24 398638916 ps
T274 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3747710818 Apr 25 12:34:59 PM PDT 24 Apr 25 12:35:01 PM PDT 24 39788355 ps
T1421 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.741320419 Apr 25 12:35:02 PM PDT 24 Apr 25 12:35:04 PM PDT 24 38079166 ps
T1422 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3747120514 Apr 25 12:34:51 PM PDT 24 Apr 25 12:34:55 PM PDT 24 215233559 ps
T1423 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1675933617 Apr 25 12:34:54 PM PDT 24 Apr 25 12:34:56 PM PDT 24 35999348 ps
T1424 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2933381513 Apr 25 12:34:39 PM PDT 24 Apr 25 12:34:44 PM PDT 24 38110208 ps
T1425 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.4122219551 Apr 25 12:34:51 PM PDT 24 Apr 25 12:34:53 PM PDT 24 26292337 ps
T1426 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3034675337 Apr 25 12:34:46 PM PDT 24 Apr 25 12:34:50 PM PDT 24 130143809 ps
T1427 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3648399375 Apr 25 12:35:04 PM PDT 24 Apr 25 12:35:06 PM PDT 24 29739979 ps
T1428 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.263406648 Apr 25 12:34:44 PM PDT 24 Apr 25 12:34:48 PM PDT 24 107867087 ps
T1429 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3793457800 Apr 25 12:35:09 PM PDT 24 Apr 25 12:35:13 PM PDT 24 32762542 ps
T1430 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3173622796 Apr 25 12:34:54 PM PDT 24 Apr 25 12:34:57 PM PDT 24 183694003 ps
T275 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1614240220 Apr 25 12:34:35 PM PDT 24 Apr 25 12:34:41 PM PDT 24 181416301 ps
T276 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3383405533 Apr 25 12:35:06 PM PDT 24 Apr 25 12:35:09 PM PDT 24 72206574 ps
T1431 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2028393199 Apr 25 12:35:05 PM PDT 24 Apr 25 12:35:07 PM PDT 24 31050909 ps
T1432 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3120075364 Apr 25 12:34:52 PM PDT 24 Apr 25 12:34:57 PM PDT 24 252646062 ps
T57 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3297452342 Apr 25 12:34:47 PM PDT 24 Apr 25 12:34:50 PM PDT 24 94421159 ps
T1433 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2086210325 Apr 25 12:34:47 PM PDT 24 Apr 25 12:34:50 PM PDT 24 70369026 ps
T1434 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3688455852 Apr 25 12:34:54 PM PDT 24 Apr 25 12:34:57 PM PDT 24 55024477 ps
T1435 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2149513699 Apr 25 12:34:35 PM PDT 24 Apr 25 12:34:41 PM PDT 24 166570653 ps
T277 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2578787751 Apr 25 12:34:34 PM PDT 24 Apr 25 12:34:39 PM PDT 24 82541430 ps
T1436 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1764360093 Apr 25 12:35:05 PM PDT 24 Apr 25 12:35:07 PM PDT 24 47703506 ps
T278 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2299208657 Apr 25 12:34:38 PM PDT 24 Apr 25 12:34:44 PM PDT 24 49099733 ps
T1437 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.615102029 Apr 25 12:34:54 PM PDT 24 Apr 25 12:34:57 PM PDT 24 25125633 ps
T1438 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1579060523 Apr 25 12:35:01 PM PDT 24 Apr 25 12:35:03 PM PDT 24 22804974 ps
T1439 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3875326783 Apr 25 12:35:09 PM PDT 24 Apr 25 12:35:12 PM PDT 24 31763800 ps
T1440 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3611787622 Apr 25 12:36:10 PM PDT 24 Apr 25 12:36:14 PM PDT 24 69196442 ps
T1441 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1635420714 Apr 25 12:34:39 PM PDT 24 Apr 25 12:34:45 PM PDT 24 65734130 ps
T303 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2008540344 Apr 25 12:35:05 PM PDT 24 Apr 25 12:35:13 PM PDT 24 1486478761 ps
T1442 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.4037403761 Apr 25 12:34:55 PM PDT 24 Apr 25 12:34:59 PM PDT 24 150284877 ps
T305 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2985886621 Apr 25 12:35:06 PM PDT 24 Apr 25 12:35:10 PM PDT 24 338172940 ps
T1443 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3647677744 Apr 25 12:34:53 PM PDT 24 Apr 25 12:34:55 PM PDT 24 33167895 ps
T1444 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.127899071 Apr 25 12:34:51 PM PDT 24 Apr 25 12:34:55 PM PDT 24 86697898 ps
T1445 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3830809281 Apr 25 12:35:09 PM PDT 24 Apr 25 12:35:13 PM PDT 24 79238892 ps
T1446 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3573458886 Apr 25 12:34:51 PM PDT 24 Apr 25 12:34:54 PM PDT 24 77740208 ps
T1447 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3732505140 Apr 25 12:35:08 PM PDT 24 Apr 25 12:35:10 PM PDT 24 77130339 ps
T1448 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3284592389 Apr 25 12:34:36 PM PDT 24 Apr 25 12:34:42 PM PDT 24 189959240 ps
T1449 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3227733040 Apr 25 12:34:55 PM PDT 24 Apr 25 12:34:57 PM PDT 24 33654489 ps
T304 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3120073748 Apr 25 12:34:53 PM PDT 24 Apr 25 12:34:57 PM PDT 24 394902598 ps
T1450 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3409027589 Apr 25 12:34:39 PM PDT 24 Apr 25 12:34:47 PM PDT 24 616092710 ps
T1451 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2415327961 Apr 25 12:34:43 PM PDT 24 Apr 25 12:34:48 PM PDT 24 211974863 ps
T1452 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3650631654 Apr 25 12:34:53 PM PDT 24 Apr 25 12:34:56 PM PDT 24 35651852 ps
T1453 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.243547866 Apr 25 12:34:52 PM PDT 24 Apr 25 12:34:56 PM PDT 24 122420437 ps
T1454 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.823875950 Apr 25 12:34:56 PM PDT 24 Apr 25 12:34:59 PM PDT 24 36153286 ps
T1455 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2166846618 Apr 25 12:35:06 PM PDT 24 Apr 25 12:35:08 PM PDT 24 30419492 ps
T1456 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.4258865906 Apr 25 12:34:50 PM PDT 24 Apr 25 12:34:53 PM PDT 24 37293866 ps
T1457 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2549444315 Apr 25 12:34:57 PM PDT 24 Apr 25 12:34:59 PM PDT 24 27275521 ps
T1458 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.820796777 Apr 25 12:34:54 PM PDT 24 Apr 25 12:34:57 PM PDT 24 83676164 ps
T1459 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.85334214 Apr 25 12:34:42 PM PDT 24 Apr 25 12:34:45 PM PDT 24 34087904 ps
T1460 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3899659572 Apr 25 12:35:06 PM PDT 24 Apr 25 12:35:11 PM PDT 24 480346278 ps
T1461 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2380560270 Apr 25 12:34:37 PM PDT 24 Apr 25 12:34:46 PM PDT 24 705207551 ps
T310 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2430671391 Apr 25 12:34:47 PM PDT 24 Apr 25 12:34:54 PM PDT 24 773319388 ps
T1462 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2841762783 Apr 25 12:35:10 PM PDT 24 Apr 25 12:35:14 PM PDT 24 24415981 ps
T1463 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1141412666 Apr 25 12:34:53 PM PDT 24 Apr 25 12:34:56 PM PDT 24 60410817 ps
T1464 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.511930704 Apr 25 12:34:36 PM PDT 24 Apr 25 12:34:41 PM PDT 24 61825200 ps
T311 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2827103056 Apr 25 12:34:45 PM PDT 24 Apr 25 12:34:50 PM PDT 24 292253278 ps
T1465 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1661076417 Apr 25 12:34:37 PM PDT 24 Apr 25 12:34:43 PM PDT 24 156535449 ps
T1466 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3451679994 Apr 25 12:35:08 PM PDT 24 Apr 25 12:35:13 PM PDT 24 241375067 ps
T1467 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1399127250 Apr 25 12:34:45 PM PDT 24 Apr 25 12:34:48 PM PDT 24 40001327 ps
T1468 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1574210957 Apr 25 12:34:37 PM PDT 24 Apr 25 12:34:42 PM PDT 24 58140342 ps
T1469 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.489814189 Apr 25 12:34:55 PM PDT 24 Apr 25 12:34:58 PM PDT 24 51773750 ps
T1470 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2722848939 Apr 25 12:34:51 PM PDT 24 Apr 25 12:34:55 PM PDT 24 112165702 ps
T1471 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3415191905 Apr 25 12:34:56 PM PDT 24 Apr 25 12:34:59 PM PDT 24 44316392 ps
T1472 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2904293912 Apr 25 12:34:46 PM PDT 24 Apr 25 12:34:50 PM PDT 24 180704802 ps
T1473 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3092325221 Apr 25 12:34:35 PM PDT 24 Apr 25 12:34:42 PM PDT 24 109072626 ps
T1474 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3083662283 Apr 25 12:34:43 PM PDT 24 Apr 25 12:34:48 PM PDT 24 183267233 ps
T1475 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2379272924 Apr 25 12:34:34 PM PDT 24 Apr 25 12:34:40 PM PDT 24 83500156 ps
T1476 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1263945903 Apr 25 12:34:53 PM PDT 24 Apr 25 12:34:56 PM PDT 24 45442319 ps
T1477 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2858613573 Apr 25 12:35:09 PM PDT 24 Apr 25 12:35:12 PM PDT 24 29654359 ps
T1478 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1011589524 Apr 25 12:35:08 PM PDT 24 Apr 25 12:35:10 PM PDT 24 49545671 ps
T1479 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.367286805 Apr 25 12:34:51 PM PDT 24 Apr 25 12:34:54 PM PDT 24 101515397 ps
T1480 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1783212298 Apr 25 12:35:15 PM PDT 24 Apr 25 12:35:20 PM PDT 24 27131488 ps
T1481 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3821758884 Apr 25 12:34:48 PM PDT 24 Apr 25 12:34:52 PM PDT 24 95862098 ps

Test location /workspace/coverage/default/28.usbdev_in_trans.571693438
Short name T11
Test name
Test status
Simulation time 8450767875 ps
CPU time 7.79 seconds
Started Apr 25 02:34:04 PM PDT 24
Finished Apr 25 02:34:13 PM PDT 24
Peak memory 204096 kb
Host smart-8440afb6-c745-4da6-b3d7-d01ac7b6a858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57169
3438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.571693438
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.2551023249
Short name T13
Test name
Test status
Simulation time 18976363150 ps
CPU time 39.25 seconds
Started Apr 25 02:36:19 PM PDT 24
Finished Apr 25 02:36:59 PM PDT 24
Peak memory 204304 kb
Host smart-3cfa105b-3e8c-400b-b027-cd2596e51b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25510
23249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.2551023249
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2552393993
Short name T294
Test name
Test status
Simulation time 38158857 ps
CPU time 0.72 seconds
Started Apr 25 12:35:02 PM PDT 24
Finished Apr 25 12:35:04 PM PDT 24
Peak memory 203124 kb
Host smart-d5e5df48-cc42-4ff7-890a-8fe17343a9e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2552393993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2552393993
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1258616600
Short name T51
Test name
Test status
Simulation time 72433850 ps
CPU time 2.13 seconds
Started Apr 25 12:34:50 PM PDT 24
Finished Apr 25 12:34:53 PM PDT 24
Peak memory 212048 kb
Host smart-fc5e9786-1d88-47c0-b696-1660d63d2f51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258616600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.1258616600
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.1235080922
Short name T15
Test name
Test status
Simulation time 8370049364 ps
CPU time 7.79 seconds
Started Apr 25 02:34:11 PM PDT 24
Finished Apr 25 02:34:21 PM PDT 24
Peak memory 204072 kb
Host smart-f74a368a-885b-497b-813a-0cfbba036417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12350
80922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.1235080922
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.571301781
Short name T32
Test name
Test status
Simulation time 8482381564 ps
CPU time 8.48 seconds
Started Apr 25 02:29:29 PM PDT 24
Finished Apr 25 02:29:38 PM PDT 24
Peak memory 204128 kb
Host smart-ff8d380f-151f-4f78-a264-b17909b99a96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57130
1781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.571301781
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1428698867
Short name T290
Test name
Test status
Simulation time 32131471 ps
CPU time 0.67 seconds
Started Apr 25 12:34:35 PM PDT 24
Finished Apr 25 12:34:40 PM PDT 24
Peak memory 203016 kb
Host smart-a7b509c0-51d9-4f64-aaef-d39dfb43cf3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1428698867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.1428698867
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/default/35.usbdev_enable.2198327681
Short name T77
Test name
Test status
Simulation time 8387551041 ps
CPU time 7.86 seconds
Started Apr 25 02:34:52 PM PDT 24
Finished Apr 25 02:35:01 PM PDT 24
Peak memory 204112 kb
Host smart-bb91b8bc-2cdf-4617-b3f8-b0c76f35d8f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21983
27681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.2198327681
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.1578128901
Short name T54
Test name
Test status
Simulation time 254359194 ps
CPU time 1.16 seconds
Started Apr 25 02:28:38 PM PDT 24
Finished Apr 25 02:28:41 PM PDT 24
Peak memory 221524 kb
Host smart-ee15d436-a6db-49c1-b45a-a7f073982532
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1578128901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1578128901
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.3197590533
Short name T139
Test name
Test status
Simulation time 8431312532 ps
CPU time 7.72 seconds
Started Apr 25 02:36:05 PM PDT 24
Finished Apr 25 02:36:15 PM PDT 24
Peak memory 204144 kb
Host smart-42fc74eb-bb4c-4553-acda-9f1fa647e85d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31975
90533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.3197590533
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.758879100
Short name T22
Test name
Test status
Simulation time 8381286448 ps
CPU time 9.86 seconds
Started Apr 25 02:32:28 PM PDT 24
Finished Apr 25 02:32:39 PM PDT 24
Peak memory 204068 kb
Host smart-131d5704-1fca-41c1-9fbd-369a5f11321a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75887
9100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.758879100
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1806900572
Short name T288
Test name
Test status
Simulation time 717575890 ps
CPU time 5.02 seconds
Started Apr 25 12:34:51 PM PDT 24
Finished Apr 25 12:34:58 PM PDT 24
Peak memory 203836 kb
Host smart-ccfdf1dc-818d-4b5b-9c04-63962cf9bbb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1806900572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1806900572
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.2991581726
Short name T190
Test name
Test status
Simulation time 8379530636 ps
CPU time 8.28 seconds
Started Apr 25 02:31:43 PM PDT 24
Finished Apr 25 02:31:53 PM PDT 24
Peak memory 204116 kb
Host smart-6382e41e-949e-49ae-a5e8-0eece70e1aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29915
81726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.2991581726
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.4202545797
Short name T35
Test name
Test status
Simulation time 40331097 ps
CPU time 0.65 seconds
Started Apr 25 02:34:04 PM PDT 24
Finished Apr 25 02:34:06 PM PDT 24
Peak memory 204016 kb
Host smart-c9d67d0b-0c8e-42ae-b0b0-ae2a49fa8739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42025
45797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.4202545797
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.1856709231
Short name T48
Test name
Test status
Simulation time 271074641 ps
CPU time 2.22 seconds
Started Apr 25 02:35:30 PM PDT 24
Finished Apr 25 02:35:33 PM PDT 24
Peak memory 204236 kb
Host smart-2fe040a3-696f-4d68-81d5-687955438c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18567
09231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.1856709231
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2135630051
Short name T301
Test name
Test status
Simulation time 32869093 ps
CPU time 0.73 seconds
Started Apr 25 12:35:09 PM PDT 24
Finished Apr 25 12:35:12 PM PDT 24
Peak memory 203124 kb
Host smart-f70c6408-4e88-4903-bc34-5f2a37ff82af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2135630051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2135630051
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.4257380407
Short name T1
Test name
Test status
Simulation time 89973381 ps
CPU time 0.93 seconds
Started Apr 25 12:34:36 PM PDT 24
Finished Apr 25 12:34:41 PM PDT 24
Peak memory 203668 kb
Host smart-8921e2d6-812d-4cb5-99ff-dcf4135f150d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4257380407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.4257380407
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3414971233
Short name T53
Test name
Test status
Simulation time 226245185 ps
CPU time 2.78 seconds
Started Apr 25 12:34:55 PM PDT 24
Finished Apr 25 12:35:00 PM PDT 24
Peak memory 203896 kb
Host smart-04817888-c5f5-435d-8745-f8815f43f5cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3414971233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3414971233
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.517361122
Short name T246
Test name
Test status
Simulation time 69667416 ps
CPU time 0.96 seconds
Started Apr 25 12:34:38 PM PDT 24
Finished Apr 25 12:34:43 PM PDT 24
Peak memory 203576 kb
Host smart-66fad887-5d73-4e03-bfbf-e244794c9230
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=517361122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.517361122
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1182789454
Short name T21
Test name
Test status
Simulation time 8439292768 ps
CPU time 7.61 seconds
Started Apr 25 02:35:35 PM PDT 24
Finished Apr 25 02:35:44 PM PDT 24
Peak memory 204120 kb
Host smart-43bbaec6-8010-4457-843c-702e9aed56ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11827
89454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1182789454
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.116141212
Short name T309
Test name
Test status
Simulation time 484644351 ps
CPU time 4.16 seconds
Started Apr 25 12:35:07 PM PDT 24
Finished Apr 25 12:35:18 PM PDT 24
Peak memory 203872 kb
Host smart-10046051-6345-4abb-a8cc-29e5cc2c24d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=116141212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.116141212
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2464270097
Short name T60
Test name
Test status
Simulation time 32260939 ps
CPU time 0.64 seconds
Started Apr 25 12:34:52 PM PDT 24
Finished Apr 25 12:34:59 PM PDT 24
Peak memory 203048 kb
Host smart-ab9c0366-9483-47a8-8652-3ecb7b958a53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2464270097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.2464270097
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.1147198595
Short name T127
Test name
Test status
Simulation time 8414503578 ps
CPU time 10.01 seconds
Started Apr 25 02:28:23 PM PDT 24
Finished Apr 25 02:28:34 PM PDT 24
Peak memory 204112 kb
Host smart-4b24ce4c-4912-4566-87c4-305803bfa533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11471
98595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.1147198595
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.4062968277
Short name T298
Test name
Test status
Simulation time 91377984 ps
CPU time 0.7 seconds
Started Apr 25 12:35:04 PM PDT 24
Finished Apr 25 12:35:06 PM PDT 24
Peak memory 203120 kb
Host smart-6e4ffe62-0272-4d14-be18-441dfc65694b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4062968277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.4062968277
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2008540344
Short name T303
Test name
Test status
Simulation time 1486478761 ps
CPU time 5.9 seconds
Started Apr 25 12:35:05 PM PDT 24
Finished Apr 25 12:35:13 PM PDT 24
Peak memory 203768 kb
Host smart-e1d8e9d8-cc07-4953-bde5-25b669c5d155
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2008540344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2008540344
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2952298097
Short name T96
Test name
Test status
Simulation time 89094549 ps
CPU time 1.51 seconds
Started Apr 25 12:34:57 PM PDT 24
Finished Apr 25 12:35:00 PM PDT 24
Peak memory 203792 kb
Host smart-2fffba1f-76c8-4e22-b9f6-d7155bbcfb0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2952298097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2952298097
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.138763149
Short name T102
Test name
Test status
Simulation time 5131751329 ps
CPU time 30.55 seconds
Started Apr 25 02:28:15 PM PDT 24
Finished Apr 25 02:28:47 PM PDT 24
Peak memory 204340 kb
Host smart-cdf512d1-9094-45df-a9fb-ef186354d281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13876
3149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.138763149
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2971571984
Short name T1417
Test name
Test status
Simulation time 42044528 ps
CPU time 0.67 seconds
Started Apr 25 12:34:42 PM PDT 24
Finished Apr 25 12:34:46 PM PDT 24
Peak memory 203064 kb
Host smart-3ac94e55-90d4-4e57-b5d4-e325a3ff9654
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2971571984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2971571984
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3709613863
Short name T211
Test name
Test status
Simulation time 561097109 ps
CPU time 4.17 seconds
Started Apr 25 12:34:54 PM PDT 24
Finished Apr 25 12:35:00 PM PDT 24
Peak memory 203780 kb
Host smart-3f35d54a-e193-4ddb-8591-9c52d85e9106
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3709613863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3709613863
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2924501041
Short name T1412
Test name
Test status
Simulation time 29067513 ps
CPU time 0.67 seconds
Started Apr 25 12:34:33 PM PDT 24
Finished Apr 25 12:34:36 PM PDT 24
Peak memory 203032 kb
Host smart-84d7585c-65d7-4c69-b170-c6be9d24b635
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2924501041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2924501041
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.4098583293
Short name T238
Test name
Test status
Simulation time 304209593 ps
CPU time 3.2 seconds
Started Apr 25 12:34:56 PM PDT 24
Finished Apr 25 12:35:02 PM PDT 24
Peak memory 203888 kb
Host smart-a88f27c7-b5da-4304-9249-91f4adca4e79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4098583293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.4098583293
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.320793143
Short name T38
Test name
Test status
Simulation time 8465174593 ps
CPU time 8.44 seconds
Started Apr 25 02:33:26 PM PDT 24
Finished Apr 25 02:33:35 PM PDT 24
Peak memory 204148 kb
Host smart-ef8019e9-fcef-48a2-8c3d-96280f27cbcf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=320793143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.320793143
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_smoke.2873133962
Short name T44
Test name
Test status
Simulation time 8439034333 ps
CPU time 8.98 seconds
Started Apr 25 02:29:21 PM PDT 24
Finished Apr 25 02:29:30 PM PDT 24
Peak memory 204124 kb
Host smart-afa41c7f-a654-4c5b-b0df-73fd4acff648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28731
33962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2873133962
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.3298166763
Short name T171
Test name
Test status
Simulation time 8463702671 ps
CPU time 7.56 seconds
Started Apr 25 02:28:29 PM PDT 24
Finished Apr 25 02:28:38 PM PDT 24
Peak memory 204112 kb
Host smart-a7c5b598-0796-4653-bc4c-bc6dbeb67015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32981
66763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.3298166763
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.1729998164
Short name T208
Test name
Test status
Simulation time 8407528676 ps
CPU time 8.1 seconds
Started Apr 25 02:29:03 PM PDT 24
Finished Apr 25 02:29:12 PM PDT 24
Peak memory 204076 kb
Host smart-667ab3b0-6c4f-473d-ad9f-9f4499ff6e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17299
98164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.1729998164
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.3342303944
Short name T1336
Test name
Test status
Simulation time 8393606452 ps
CPU time 8.71 seconds
Started Apr 25 02:31:22 PM PDT 24
Finished Apr 25 02:31:32 PM PDT 24
Peak memory 204104 kb
Host smart-05d027a6-df95-41e3-a56f-6561e1172a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33423
03944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.3342303944
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.110639304
Short name T715
Test name
Test status
Simulation time 8398321083 ps
CPU time 8.03 seconds
Started Apr 25 02:31:50 PM PDT 24
Finished Apr 25 02:31:59 PM PDT 24
Peak memory 204144 kb
Host smart-32147e4e-d035-42e6-9c59-e998fbe356ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11063
9304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.110639304
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_smoke.156045699
Short name T875
Test name
Test status
Simulation time 8437709962 ps
CPU time 7.55 seconds
Started Apr 25 02:31:42 PM PDT 24
Finished Apr 25 02:31:50 PM PDT 24
Peak memory 204136 kb
Host smart-d7fbb97d-bb41-4cd1-ae20-f1c2abbc3e7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15604
5699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.156045699
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.2952217567
Short name T921
Test name
Test status
Simulation time 8400081377 ps
CPU time 7.59 seconds
Started Apr 25 02:32:31 PM PDT 24
Finished Apr 25 02:32:40 PM PDT 24
Peak memory 204136 kb
Host smart-ff8d29a5-bbc4-4daa-a7b4-aa2222a62725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29522
17567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.2952217567
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.499203153
Short name T380
Test name
Test status
Simulation time 61661468 ps
CPU time 0.66 seconds
Started Apr 25 02:33:05 PM PDT 24
Finished Apr 25 02:33:06 PM PDT 24
Peak memory 203980 kb
Host smart-226042bd-3cae-4fb2-87b8-3487cb895087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49920
3153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.499203153
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.666336637
Short name T180
Test name
Test status
Simulation time 8399864547 ps
CPU time 7.94 seconds
Started Apr 25 02:34:01 PM PDT 24
Finished Apr 25 02:34:11 PM PDT 24
Peak memory 204104 kb
Host smart-047f1263-d908-446e-92c5-72c1130cbfad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66633
6637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.666336637
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.3407958561
Short name T622
Test name
Test status
Simulation time 8375363663 ps
CPU time 9.22 seconds
Started Apr 25 02:34:06 PM PDT 24
Finished Apr 25 02:34:16 PM PDT 24
Peak memory 204016 kb
Host smart-90e7cc68-1884-44fa-8f40-763760fc66fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34079
58561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.3407958561
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.561423487
Short name T169
Test name
Test status
Simulation time 8395235445 ps
CPU time 8.06 seconds
Started Apr 25 02:34:56 PM PDT 24
Finished Apr 25 02:35:06 PM PDT 24
Peak memory 204112 kb
Host smart-e0e05121-5a4d-40f2-80de-aa9924e8465a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56142
3487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.561423487
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.963377409
Short name T14
Test name
Test status
Simulation time 31731537399 ps
CPU time 59.77 seconds
Started Apr 25 02:36:26 PM PDT 24
Finished Apr 25 02:37:27 PM PDT 24
Peak memory 204388 kb
Host smart-be4a0e32-7854-4a39-9897-b2f0133c9ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96337
7409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.963377409
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3821758884
Short name T1481
Test name
Test status
Simulation time 95862098 ps
CPU time 2.7 seconds
Started Apr 25 12:34:48 PM PDT 24
Finished Apr 25 12:34:52 PM PDT 24
Peak memory 212048 kb
Host smart-f73be9e3-94c8-4f1a-840d-2ff8064acec2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3821758884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3821758884
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1693995819
Short name T681
Test name
Test status
Simulation time 8424976864 ps
CPU time 8.43 seconds
Started Apr 25 02:28:20 PM PDT 24
Finished Apr 25 02:28:29 PM PDT 24
Peak memory 204100 kb
Host smart-45c2b951-62ee-4e7a-9f17-e0a834f3a720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16939
95819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1693995819
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.3283291124
Short name T154
Test name
Test status
Simulation time 8441302602 ps
CPU time 7.88 seconds
Started Apr 25 02:29:11 PM PDT 24
Finished Apr 25 02:29:20 PM PDT 24
Peak memory 204032 kb
Host smart-e9f0867b-36e9-4254-b367-cebd33cdfaf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32832
91124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.3283291124
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.2874773370
Short name T105
Test name
Test status
Simulation time 8434009739 ps
CPU time 8.29 seconds
Started Apr 25 02:28:49 PM PDT 24
Finished Apr 25 02:28:58 PM PDT 24
Peak memory 204148 kb
Host smart-b7c3f723-af87-4efa-8f46-33c903f58641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28747
73370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.2874773370
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.3057296195
Short name T45
Test name
Test status
Simulation time 8453572183 ps
CPU time 7.82 seconds
Started Apr 25 02:31:24 PM PDT 24
Finished Apr 25 02:31:33 PM PDT 24
Peak memory 204124 kb
Host smart-04e1a0fa-58c9-4bb6-b409-05e59ee141e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30572
96195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.3057296195
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.2596810304
Short name T132
Test name
Test status
Simulation time 8434726716 ps
CPU time 8.74 seconds
Started Apr 25 02:31:18 PM PDT 24
Finished Apr 25 02:31:28 PM PDT 24
Peak memory 204112 kb
Host smart-ecdddbc2-cc78-4c31-9644-f414f005b788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25968
10304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2596810304
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.2432902347
Short name T19
Test name
Test status
Simulation time 8438215442 ps
CPU time 8.93 seconds
Started Apr 25 02:31:34 PM PDT 24
Finished Apr 25 02:31:45 PM PDT 24
Peak memory 204112 kb
Host smart-02e6565f-1631-4f94-8754-0085c675b3bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24329
02347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.2432902347
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.1704758681
Short name T112
Test name
Test status
Simulation time 8406735316 ps
CPU time 9.64 seconds
Started Apr 25 02:31:30 PM PDT 24
Finished Apr 25 02:31:40 PM PDT 24
Peak memory 204112 kb
Host smart-5da9f6ee-5878-4cde-8788-8033f8feb0c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17047
58681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.1704758681
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_smoke.1486484935
Short name T164
Test name
Test status
Simulation time 8460546239 ps
CPU time 8.83 seconds
Started Apr 25 02:31:40 PM PDT 24
Finished Apr 25 02:31:50 PM PDT 24
Peak memory 204112 kb
Host smart-60b22faf-1ce1-4c59-8181-f6e653994b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14864
84935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.1486484935
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.1445192480
Short name T1045
Test name
Test status
Simulation time 8375789810 ps
CPU time 7.65 seconds
Started Apr 25 02:31:50 PM PDT 24
Finished Apr 25 02:31:59 PM PDT 24
Peak memory 204140 kb
Host smart-1a637a42-a02a-4450-826b-c41c0f506584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14451
92480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.1445192480
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.900052748
Short name T100
Test name
Test status
Simulation time 8425301622 ps
CPU time 7.87 seconds
Started Apr 25 02:31:42 PM PDT 24
Finished Apr 25 02:31:52 PM PDT 24
Peak memory 204184 kb
Host smart-beb58c01-693c-482e-a175-66a75e8251f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90005
2748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.900052748
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.3927465449
Short name T201
Test name
Test status
Simulation time 8370791279 ps
CPU time 8.23 seconds
Started Apr 25 02:32:04 PM PDT 24
Finished Apr 25 02:32:14 PM PDT 24
Peak memory 204124 kb
Host smart-056356db-deb9-4e60-a618-c92d6e2092d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39274
65449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3927465449
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_smoke.1282198940
Short name T894
Test name
Test status
Simulation time 8423011257 ps
CPU time 8.86 seconds
Started Apr 25 02:31:51 PM PDT 24
Finished Apr 25 02:32:01 PM PDT 24
Peak memory 204144 kb
Host smart-18cbce2f-fc06-428f-b67b-54dcc0907d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12821
98940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1282198940
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.919755442
Short name T120
Test name
Test status
Simulation time 8420062524 ps
CPU time 9.51 seconds
Started Apr 25 02:32:13 PM PDT 24
Finished Apr 25 02:32:23 PM PDT 24
Peak memory 204116 kb
Host smart-f551fda0-06e9-4622-b2c6-a03193259fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91975
5442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.919755442
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.191701370
Short name T575
Test name
Test status
Simulation time 8365976669 ps
CPU time 7.62 seconds
Started Apr 25 02:32:24 PM PDT 24
Finished Apr 25 02:32:33 PM PDT 24
Peak memory 204116 kb
Host smart-581b960f-031d-4095-9825-1d11ed49c397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19170
1370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.191701370
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.370964623
Short name T103
Test name
Test status
Simulation time 8446408089 ps
CPU time 8.93 seconds
Started Apr 25 02:32:24 PM PDT 24
Finished Apr 25 02:32:33 PM PDT 24
Peak memory 204088 kb
Host smart-1d327733-2d90-4103-9726-0268f10d7007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37096
4623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.370964623
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.2898330709
Short name T30
Test name
Test status
Simulation time 8452934562 ps
CPU time 8.02 seconds
Started Apr 25 02:29:10 PM PDT 24
Finished Apr 25 02:29:19 PM PDT 24
Peak memory 204104 kb
Host smart-89607d1e-5a47-440e-9b34-bb97fd38cb50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28983
30709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.2898330709
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1223308913
Short name T1269
Test name
Test status
Simulation time 8415735015 ps
CPU time 8.36 seconds
Started Apr 25 02:33:08 PM PDT 24
Finished Apr 25 02:33:18 PM PDT 24
Peak memory 204032 kb
Host smart-6fde3fd7-894a-46e5-b135-10595613d0e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12233
08913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1223308913
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.592783856
Short name T123
Test name
Test status
Simulation time 8450836919 ps
CPU time 9.16 seconds
Started Apr 25 02:33:11 PM PDT 24
Finished Apr 25 02:33:21 PM PDT 24
Peak memory 204148 kb
Host smart-1e0c638d-54eb-4334-b47b-702a11cf9178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59278
3856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.592783856
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.1557138489
Short name T111
Test name
Test status
Simulation time 8462796000 ps
CPU time 8.1 seconds
Started Apr 25 02:33:46 PM PDT 24
Finished Apr 25 02:33:55 PM PDT 24
Peak memory 204148 kb
Host smart-50c7bd57-f6a0-4907-9896-cbdc2a24925e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15571
38489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.1557138489
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.4221497510
Short name T126
Test name
Test status
Simulation time 8473977044 ps
CPU time 7.95 seconds
Started Apr 25 02:34:30 PM PDT 24
Finished Apr 25 02:34:40 PM PDT 24
Peak memory 204108 kb
Host smart-a72a00bb-8fb4-4a32-bd1f-c3c9f11dcf40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42214
97510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.4221497510
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3092325221
Short name T1473
Test name
Test status
Simulation time 109072626 ps
CPU time 3.19 seconds
Started Apr 25 12:34:35 PM PDT 24
Finished Apr 25 12:34:42 PM PDT 24
Peak memory 203676 kb
Host smart-f4dc3a1e-509d-4e81-be9c-6cb6a6ed3204
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3092325221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.3092325221
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1696977448
Short name T1402
Test name
Test status
Simulation time 237015710 ps
CPU time 3.68 seconds
Started Apr 25 12:34:38 PM PDT 24
Finished Apr 25 12:34:45 PM PDT 24
Peak memory 203684 kb
Host smart-9a93110b-7a7b-42c7-81fc-db4ddd6f0b02
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1696977448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1696977448
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3297452342
Short name T57
Test name
Test status
Simulation time 94421159 ps
CPU time 0.9 seconds
Started Apr 25 12:34:47 PM PDT 24
Finished Apr 25 12:34:50 PM PDT 24
Peak memory 203576 kb
Host smart-7d9b1a84-5090-4e7f-a7c3-f99e390bde52
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3297452342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3297452342
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.4261133064
Short name T1415
Test name
Test status
Simulation time 98774625 ps
CPU time 1.17 seconds
Started Apr 25 12:34:35 PM PDT 24
Finished Apr 25 12:34:40 PM PDT 24
Peak memory 213120 kb
Host smart-2d89d95c-4727-4a30-b978-ac58859181b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261133064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.4261133064
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2127327023
Short name T1392
Test name
Test status
Simulation time 55731637 ps
CPU time 0.87 seconds
Started Apr 25 12:34:39 PM PDT 24
Finished Apr 25 12:34:44 PM PDT 24
Peak memory 203576 kb
Host smart-9070d78d-ec20-4c74-b104-d940dd82105b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2127327023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2127327023
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3703695453
Short name T292
Test name
Test status
Simulation time 64434847 ps
CPU time 0.7 seconds
Started Apr 25 12:34:35 PM PDT 24
Finished Apr 25 12:34:40 PM PDT 24
Peak memory 203032 kb
Host smart-0fdcb096-c12b-4164-be6d-f99a8a550f56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3703695453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3703695453
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1614240220
Short name T275
Test name
Test status
Simulation time 181416301 ps
CPU time 2.3 seconds
Started Apr 25 12:34:35 PM PDT 24
Finished Apr 25 12:34:41 PM PDT 24
Peak memory 212044 kb
Host smart-9f7b3feb-7802-4877-b359-4577a2ea07e1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1614240220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1614240220
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.917877598
Short name T1388
Test name
Test status
Simulation time 704664177 ps
CPU time 4.73 seconds
Started Apr 25 12:34:40 PM PDT 24
Finished Apr 25 12:34:48 PM PDT 24
Peak memory 203688 kb
Host smart-7e6d5e30-1a98-403d-95f9-3dbf23573229
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=917877598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.917877598
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.511930704
Short name T1464
Test name
Test status
Simulation time 61825200 ps
CPU time 1.38 seconds
Started Apr 25 12:34:36 PM PDT 24
Finished Apr 25 12:34:41 PM PDT 24
Peak memory 203804 kb
Host smart-eee84a45-03d8-421d-afc1-789804b0630a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=511930704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.511930704
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2415327961
Short name T1451
Test name
Test status
Simulation time 211974863 ps
CPU time 2.11 seconds
Started Apr 25 12:34:43 PM PDT 24
Finished Apr 25 12:34:48 PM PDT 24
Peak memory 203952 kb
Host smart-06c9de7e-1e72-4611-9c7e-4039c4421ae4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2415327961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2415327961
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1798359294
Short name T214
Test name
Test status
Simulation time 582835459 ps
CPU time 4.51 seconds
Started Apr 25 12:34:37 PM PDT 24
Finished Apr 25 12:34:46 PM PDT 24
Peak memory 203836 kb
Host smart-d68e61fc-aa62-4660-a4a7-a15e754f4d3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1798359294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.1798359294
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1661076417
Short name T1465
Test name
Test status
Simulation time 156535449 ps
CPU time 2.17 seconds
Started Apr 25 12:34:37 PM PDT 24
Finished Apr 25 12:34:43 PM PDT 24
Peak memory 203732 kb
Host smart-4b69d3fd-9fb8-4d3b-bd88-ca6e6df1c00d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1661076417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1661076417
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1858744172
Short name T59
Test name
Test status
Simulation time 1045264762 ps
CPU time 4.53 seconds
Started Apr 25 12:34:34 PM PDT 24
Finished Apr 25 12:34:42 PM PDT 24
Peak memory 203612 kb
Host smart-063090ad-f3fd-49e1-98ef-387612c22fba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1858744172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1858744172
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.405555909
Short name T250
Test name
Test status
Simulation time 86480593 ps
CPU time 1.37 seconds
Started Apr 25 12:34:38 PM PDT 24
Finished Apr 25 12:34:44 PM PDT 24
Peak memory 212044 kb
Host smart-f306a2e4-5c3c-434d-bead-4841ebd58156
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405555909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev
_csr_mem_rw_with_rand_reset.405555909
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2933381513
Short name T1424
Test name
Test status
Simulation time 38110208 ps
CPU time 0.78 seconds
Started Apr 25 12:34:39 PM PDT 24
Finished Apr 25 12:34:44 PM PDT 24
Peak memory 203564 kb
Host smart-b1945213-832c-4cb5-9f3f-05bd7e7f3507
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2933381513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2933381513
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2578787751
Short name T277
Test name
Test status
Simulation time 82541430 ps
CPU time 2.05 seconds
Started Apr 25 12:34:34 PM PDT 24
Finished Apr 25 12:34:39 PM PDT 24
Peak memory 212044 kb
Host smart-b514ea5d-51d1-42a7-940e-0222de401ec0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2578787751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2578787751
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2380560270
Short name T1461
Test name
Test status
Simulation time 705207551 ps
CPU time 4.75 seconds
Started Apr 25 12:34:37 PM PDT 24
Finished Apr 25 12:34:46 PM PDT 24
Peak memory 203692 kb
Host smart-e6072415-d61e-49a6-acd0-4864683f2144
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2380560270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2380560270
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3359488149
Short name T1403
Test name
Test status
Simulation time 70939593 ps
CPU time 1.44 seconds
Started Apr 25 12:34:34 PM PDT 24
Finished Apr 25 12:34:39 PM PDT 24
Peak memory 203872 kb
Host smart-5172a962-b0c6-4c18-92c1-85f6af38da22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3359488149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.3359488149
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2706615582
Short name T245
Test name
Test status
Simulation time 300026660 ps
CPU time 3.2 seconds
Started Apr 25 12:34:44 PM PDT 24
Finished Apr 25 12:34:50 PM PDT 24
Peak memory 204000 kb
Host smart-a87b628e-305b-4f86-b921-8f598c698920
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2706615582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.2706615582
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3365070360
Short name T302
Test name
Test status
Simulation time 322074503 ps
CPU time 3.95 seconds
Started Apr 25 12:34:38 PM PDT 24
Finished Apr 25 12:34:46 PM PDT 24
Peak memory 203876 kb
Host smart-c5108c24-0629-436d-a87b-7560db03d6f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3365070360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3365070360
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.4037403761
Short name T1442
Test name
Test status
Simulation time 150284877 ps
CPU time 1.69 seconds
Started Apr 25 12:34:55 PM PDT 24
Finished Apr 25 12:34:59 PM PDT 24
Peak memory 212072 kb
Host smart-401e233f-88f6-476a-8cf0-f799f99f29aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037403761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.4037403761
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3647677744
Short name T1443
Test name
Test status
Simulation time 33167895 ps
CPU time 0.76 seconds
Started Apr 25 12:34:53 PM PDT 24
Finished Apr 25 12:34:55 PM PDT 24
Peak memory 203604 kb
Host smart-30280f57-1754-4666-aec4-31625fa4b723
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3647677744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3647677744
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1926693177
Short name T306
Test name
Test status
Simulation time 226836983 ps
CPU time 2.5 seconds
Started Apr 25 12:34:50 PM PDT 24
Finished Apr 25 12:34:54 PM PDT 24
Peak memory 203816 kb
Host smart-a416e66a-c438-4357-9d3c-6d2bfb9eba0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1926693177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1926693177
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.756592836
Short name T93
Test name
Test status
Simulation time 67073791 ps
CPU time 1.03 seconds
Started Apr 25 12:34:41 PM PDT 24
Finished Apr 25 12:34:45 PM PDT 24
Peak memory 203756 kb
Host smart-4c912253-f906-4db9-bf9d-313398e969d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=756592836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.756592836
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.4258865906
Short name T1456
Test name
Test status
Simulation time 37293866 ps
CPU time 0.63 seconds
Started Apr 25 12:34:50 PM PDT 24
Finished Apr 25 12:34:53 PM PDT 24
Peak memory 203044 kb
Host smart-434ac18b-352e-4d5d-94a9-915e6c7c01bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4258865906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.4258865906
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3034675337
Short name T1426
Test name
Test status
Simulation time 130143809 ps
CPU time 1.15 seconds
Started Apr 25 12:34:46 PM PDT 24
Finished Apr 25 12:34:50 PM PDT 24
Peak memory 203940 kb
Host smart-8a2e892a-a170-4282-a58c-9bbed6777425
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3034675337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3034675337
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.127899071
Short name T1444
Test name
Test status
Simulation time 86697898 ps
CPU time 2.69 seconds
Started Apr 25 12:34:51 PM PDT 24
Finished Apr 25 12:34:55 PM PDT 24
Peak memory 203896 kb
Host smart-5e9c5be5-f4a6-4754-a1a9-1f8c56649dd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=127899071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.127899071
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.409447328
Short name T307
Test name
Test status
Simulation time 968597819 ps
CPU time 4.64 seconds
Started Apr 25 12:34:48 PM PDT 24
Finished Apr 25 12:34:54 PM PDT 24
Peak memory 203848 kb
Host smart-ec51f2a7-d68e-4776-9932-794cff51590c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=409447328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.409447328
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.347186687
Short name T1406
Test name
Test status
Simulation time 53452721 ps
CPU time 1.26 seconds
Started Apr 25 12:34:57 PM PDT 24
Finished Apr 25 12:35:00 PM PDT 24
Peak memory 211988 kb
Host smart-1e317b30-8a2a-48c9-9c98-e8e1874592b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347186687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde
v_csr_mem_rw_with_rand_reset.347186687
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1399127250
Short name T1467
Test name
Test status
Simulation time 40001327 ps
CPU time 0.8 seconds
Started Apr 25 12:34:45 PM PDT 24
Finished Apr 25 12:34:48 PM PDT 24
Peak memory 203552 kb
Host smart-0625ec7b-a1e8-498d-abd6-37a499b049d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1399127250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1399127250
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.85334214
Short name T1459
Test name
Test status
Simulation time 34087904 ps
CPU time 0.64 seconds
Started Apr 25 12:34:42 PM PDT 24
Finished Apr 25 12:34:45 PM PDT 24
Peak memory 203020 kb
Host smart-9bd67cbf-c8ba-45c1-ac6b-1f9782baa17e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=85334214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.85334214
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2086210325
Short name T1433
Test name
Test status
Simulation time 70369026 ps
CPU time 1.04 seconds
Started Apr 25 12:34:47 PM PDT 24
Finished Apr 25 12:34:50 PM PDT 24
Peak memory 203760 kb
Host smart-ac6b6593-bee6-48c6-922d-7ed6f5de0242
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2086210325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.2086210325
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3120075364
Short name T1432
Test name
Test status
Simulation time 252646062 ps
CPU time 2.46 seconds
Started Apr 25 12:34:52 PM PDT 24
Finished Apr 25 12:34:57 PM PDT 24
Peak memory 212132 kb
Host smart-00d01266-ac0a-4669-9c3f-9c33d1d70efe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3120075364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.3120075364
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.996865322
Short name T215
Test name
Test status
Simulation time 324011768 ps
CPU time 2.52 seconds
Started Apr 25 12:34:44 PM PDT 24
Finished Apr 25 12:34:50 PM PDT 24
Peak memory 203828 kb
Host smart-14b7b0a1-0932-4e10-b38f-9a4a380b3264
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=996865322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.996865322
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3528163308
Short name T240
Test name
Test status
Simulation time 80464942 ps
CPU time 2.31 seconds
Started Apr 25 12:34:55 PM PDT 24
Finished Apr 25 12:35:00 PM PDT 24
Peak memory 212068 kb
Host smart-975d7771-6437-416e-aa45-da57240f65c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528163308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.3528163308
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3383405533
Short name T276
Test name
Test status
Simulation time 72206574 ps
CPU time 0.99 seconds
Started Apr 25 12:35:06 PM PDT 24
Finished Apr 25 12:35:09 PM PDT 24
Peak memory 203728 kb
Host smart-1660defb-6490-4a25-8680-c5ac0aa99892
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3383405533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3383405533
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1057604394
Short name T1405
Test name
Test status
Simulation time 143784430 ps
CPU time 1.46 seconds
Started Apr 25 12:34:42 PM PDT 24
Finished Apr 25 12:34:46 PM PDT 24
Peak memory 203756 kb
Host smart-84a756ac-1cde-454e-ace4-825346e6bd38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1057604394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1057604394
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.291488712
Short name T248
Test name
Test status
Simulation time 138911189 ps
CPU time 1.72 seconds
Started Apr 25 12:34:42 PM PDT 24
Finished Apr 25 12:34:47 PM PDT 24
Peak memory 203876 kb
Host smart-910e342b-44ac-4fe0-8c01-7946be82fd6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=291488712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.291488712
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1175216487
Short name T308
Test name
Test status
Simulation time 363418227 ps
CPU time 2.58 seconds
Started Apr 25 12:34:40 PM PDT 24
Finished Apr 25 12:34:46 PM PDT 24
Peak memory 203876 kb
Host smart-fe6fc848-dc82-4d34-b3f5-f35223684556
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1175216487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1175216487
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2135601679
Short name T1409
Test name
Test status
Simulation time 91884903 ps
CPU time 1.25 seconds
Started Apr 25 12:34:51 PM PDT 24
Finished Apr 25 12:34:54 PM PDT 24
Peak memory 212108 kb
Host smart-f581ff5a-221c-4728-bee0-26e8d63b252a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135601679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2135601679
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.604959668
Short name T269
Test name
Test status
Simulation time 55272896 ps
CPU time 0.86 seconds
Started Apr 25 12:34:55 PM PDT 24
Finished Apr 25 12:34:58 PM PDT 24
Peak memory 203552 kb
Host smart-3fec76c5-61d2-466c-b48f-fd87f41244fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=604959668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.604959668
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3711786257
Short name T63
Test name
Test status
Simulation time 52104464 ps
CPU time 0.69 seconds
Started Apr 25 12:34:59 PM PDT 24
Finished Apr 25 12:35:01 PM PDT 24
Peak memory 203176 kb
Host smart-708162c0-a8d5-4a2e-a364-61c9369e6b3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3711786257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3711786257
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1201564367
Short name T97
Test name
Test status
Simulation time 84829504 ps
CPU time 1.47 seconds
Started Apr 25 12:35:05 PM PDT 24
Finished Apr 25 12:35:08 PM PDT 24
Peak memory 203812 kb
Host smart-38050aa6-cb26-4a09-bab1-7c5948405afe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1201564367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.1201564367
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2985886621
Short name T305
Test name
Test status
Simulation time 338172940 ps
CPU time 2.81 seconds
Started Apr 25 12:35:06 PM PDT 24
Finished Apr 25 12:35:10 PM PDT 24
Peak memory 203808 kb
Host smart-03f84832-3d74-4620-b5b6-5afdc15bf39e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2985886621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.2985886621
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2305851663
Short name T249
Test name
Test status
Simulation time 95876240 ps
CPU time 1.2 seconds
Started Apr 25 12:34:51 PM PDT 24
Finished Apr 25 12:34:54 PM PDT 24
Peak memory 219884 kb
Host smart-8ac627bb-6cfd-4aa2-98ff-9d303c36e5f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305851663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.2305851663
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1863133753
Short name T279
Test name
Test status
Simulation time 54271267 ps
CPU time 0.99 seconds
Started Apr 25 12:34:56 PM PDT 24
Finished Apr 25 12:34:59 PM PDT 24
Peak memory 203828 kb
Host smart-baf210c8-7afe-4fc7-bd87-fbd08fce5baa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1863133753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.1863133753
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.823875950
Short name T1454
Test name
Test status
Simulation time 36153286 ps
CPU time 0.63 seconds
Started Apr 25 12:34:56 PM PDT 24
Finished Apr 25 12:34:59 PM PDT 24
Peak memory 202992 kb
Host smart-3ef58ec7-f3a4-4258-88c8-1bf571877058
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=823875950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.823875950
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3621342759
Short name T286
Test name
Test status
Simulation time 424344608 ps
CPU time 1.8 seconds
Started Apr 25 12:35:06 PM PDT 24
Finished Apr 25 12:35:09 PM PDT 24
Peak memory 203860 kb
Host smart-f2551019-123a-4532-b3e5-8cb97e9b5430
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3621342759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.3621342759
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3771145183
Short name T1400
Test name
Test status
Simulation time 97938562 ps
CPU time 1.38 seconds
Started Apr 25 12:34:58 PM PDT 24
Finished Apr 25 12:35:01 PM PDT 24
Peak memory 212092 kb
Host smart-91a202c2-2087-4a4a-a250-02de61f025ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771145183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.3771145183
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.623958972
Short name T273
Test name
Test status
Simulation time 49541550 ps
CPU time 0.95 seconds
Started Apr 25 12:34:55 PM PDT 24
Finished Apr 25 12:34:58 PM PDT 24
Peak memory 203804 kb
Host smart-f2abcec5-0ad3-4ff2-9901-3abda9d492b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=623958972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.623958972
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3173622796
Short name T1430
Test name
Test status
Simulation time 183694003 ps
CPU time 1.64 seconds
Started Apr 25 12:34:54 PM PDT 24
Finished Apr 25 12:34:57 PM PDT 24
Peak memory 203700 kb
Host smart-7923f84c-4cea-40ea-b836-118596aadc4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3173622796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3173622796
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1821619777
Short name T247
Test name
Test status
Simulation time 195376819 ps
CPU time 2.14 seconds
Started Apr 25 12:35:14 PM PDT 24
Finished Apr 25 12:35:21 PM PDT 24
Peak memory 203868 kb
Host smart-82db6ee1-11cb-4fe6-89ae-98c04b409ad1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1821619777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1821619777
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.289795694
Short name T1420
Test name
Test status
Simulation time 398638916 ps
CPU time 2.57 seconds
Started Apr 25 12:35:05 PM PDT 24
Finished Apr 25 12:35:08 PM PDT 24
Peak memory 203876 kb
Host smart-4024cce5-ccfe-45c0-ac2a-ada8e2bc51ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=289795694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.289795694
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.820796777
Short name T1458
Test name
Test status
Simulation time 83676164 ps
CPU time 1.41 seconds
Started Apr 25 12:34:54 PM PDT 24
Finished Apr 25 12:34:57 PM PDT 24
Peak memory 212060 kb
Host smart-c23f666c-fe42-45f2-ae92-9c97cd4eedea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820796777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbde
v_csr_mem_rw_with_rand_reset.820796777
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3415191905
Short name T1471
Test name
Test status
Simulation time 44316392 ps
CPU time 0.88 seconds
Started Apr 25 12:34:56 PM PDT 24
Finished Apr 25 12:34:59 PM PDT 24
Peak memory 203680 kb
Host smart-974ef65f-61bf-4929-86f0-b750143a6463
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3415191905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3415191905
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.615102029
Short name T1437
Test name
Test status
Simulation time 25125633 ps
CPU time 0.74 seconds
Started Apr 25 12:34:54 PM PDT 24
Finished Apr 25 12:34:57 PM PDT 24
Peak memory 203100 kb
Host smart-328da7d1-55dd-42b4-958e-d5d7d97c4859
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=615102029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.615102029
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2056066337
Short name T1387
Test name
Test status
Simulation time 85655430 ps
CPU time 1.13 seconds
Started Apr 25 12:35:00 PM PDT 24
Finished Apr 25 12:35:03 PM PDT 24
Peak memory 203852 kb
Host smart-4a07a1a9-b783-46bd-a272-252d6e3d2e2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2056066337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.2056066337
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.223691487
Short name T241
Test name
Test status
Simulation time 93179527 ps
CPU time 1.37 seconds
Started Apr 25 12:34:54 PM PDT 24
Finished Apr 25 12:34:58 PM PDT 24
Peak memory 203932 kb
Host smart-25145666-39f4-4116-a20b-20905357b220
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=223691487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.223691487
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2618393721
Short name T52
Test name
Test status
Simulation time 545261586 ps
CPU time 4.5 seconds
Started Apr 25 12:35:05 PM PDT 24
Finished Apr 25 12:35:10 PM PDT 24
Peak memory 203780 kb
Host smart-1a6304a0-7f0a-46ae-809d-aa179e7608c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2618393721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2618393721
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3573458886
Short name T1446
Test name
Test status
Simulation time 77740208 ps
CPU time 2.16 seconds
Started Apr 25 12:34:51 PM PDT 24
Finished Apr 25 12:34:54 PM PDT 24
Peak memory 212120 kb
Host smart-03fd0c8e-7f00-437c-af57-b1df41e2c568
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573458886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.3573458886
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3747710818
Short name T274
Test name
Test status
Simulation time 39788355 ps
CPU time 0.83 seconds
Started Apr 25 12:34:59 PM PDT 24
Finished Apr 25 12:35:01 PM PDT 24
Peak memory 203636 kb
Host smart-c57316c3-1068-4d79-8003-c24118a502a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3747710818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3747710818
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.741320419
Short name T1421
Test name
Test status
Simulation time 38079166 ps
CPU time 0.67 seconds
Started Apr 25 12:35:02 PM PDT 24
Finished Apr 25 12:35:04 PM PDT 24
Peak memory 203096 kb
Host smart-48f6ab37-8014-4b52-96dd-7de33b9a896d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=741320419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.741320419
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1872628295
Short name T212
Test name
Test status
Simulation time 187495102 ps
CPU time 1.64 seconds
Started Apr 25 12:35:13 PM PDT 24
Finished Apr 25 12:35:20 PM PDT 24
Peak memory 203812 kb
Host smart-1d459dbb-43a7-404f-93ad-cda812f6d4ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1872628295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.1872628295
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3451679994
Short name T1466
Test name
Test status
Simulation time 241375067 ps
CPU time 2.56 seconds
Started Apr 25 12:35:08 PM PDT 24
Finished Apr 25 12:35:13 PM PDT 24
Peak memory 203864 kb
Host smart-4978cbed-5217-490a-b518-6ee5930d7097
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3451679994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3451679994
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.4269429172
Short name T1414
Test name
Test status
Simulation time 73391316 ps
CPU time 1.24 seconds
Started Apr 25 12:34:54 PM PDT 24
Finished Apr 25 12:34:58 PM PDT 24
Peak memory 213132 kb
Host smart-d325176a-585a-4303-9829-86be366855e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269429172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.4269429172
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.489814189
Short name T1469
Test name
Test status
Simulation time 51773750 ps
CPU time 0.9 seconds
Started Apr 25 12:34:55 PM PDT 24
Finished Apr 25 12:34:58 PM PDT 24
Peak memory 203756 kb
Host smart-e01e03ff-e640-4d21-8b8d-f7dfab416c3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=489814189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.489814189
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.4122219551
Short name T1425
Test name
Test status
Simulation time 26292337 ps
CPU time 0.67 seconds
Started Apr 25 12:34:51 PM PDT 24
Finished Apr 25 12:34:53 PM PDT 24
Peak memory 203052 kb
Host smart-532c762a-1ec1-471e-9e5a-c1966cb22654
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4122219551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.4122219551
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3583545195
Short name T94
Test name
Test status
Simulation time 50574431 ps
CPU time 1 seconds
Started Apr 25 12:34:55 PM PDT 24
Finished Apr 25 12:34:58 PM PDT 24
Peak memory 203796 kb
Host smart-d2f69403-b002-4b48-8b27-302bd41c1953
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3583545195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.3583545195
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3747120514
Short name T1422
Test name
Test status
Simulation time 215233559 ps
CPU time 2.74 seconds
Started Apr 25 12:34:51 PM PDT 24
Finished Apr 25 12:34:55 PM PDT 24
Peak memory 203912 kb
Host smart-0cf9243a-b0cf-4009-ae8f-c01f0db0a163
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3747120514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3747120514
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.529417543
Short name T1390
Test name
Test status
Simulation time 110193022 ps
CPU time 3.23 seconds
Started Apr 25 12:34:32 PM PDT 24
Finished Apr 25 12:34:38 PM PDT 24
Peak memory 203736 kb
Host smart-90c27f03-bcba-4124-bebe-471072e0b3f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=529417543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.529417543
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1368048547
Short name T268
Test name
Test status
Simulation time 2486715679 ps
CPU time 9.65 seconds
Started Apr 25 12:34:35 PM PDT 24
Finished Apr 25 12:34:48 PM PDT 24
Peak memory 203748 kb
Host smart-a337503a-2ed6-4039-8801-373cca28ff04
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1368048547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1368048547
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1574210957
Short name T1468
Test name
Test status
Simulation time 58140342 ps
CPU time 0.95 seconds
Started Apr 25 12:34:37 PM PDT 24
Finished Apr 25 12:34:42 PM PDT 24
Peak memory 203668 kb
Host smart-5571c592-d7b6-4efc-a8f8-c3142e2e7b5c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1574210957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1574210957
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2573276537
Short name T239
Test name
Test status
Simulation time 86532808 ps
CPU time 2.1 seconds
Started Apr 25 12:34:38 PM PDT 24
Finished Apr 25 12:34:44 PM PDT 24
Peak memory 212068 kb
Host smart-f8a1f79a-dbd6-4323-a4fe-eb2f86499a1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573276537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.2573276537
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1580861864
Short name T272
Test name
Test status
Simulation time 63907060 ps
CPU time 0.92 seconds
Started Apr 25 12:34:35 PM PDT 24
Finished Apr 25 12:34:39 PM PDT 24
Peak memory 203816 kb
Host smart-eafa99a2-fd5c-403b-aa5e-6b79345a4042
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1580861864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1580861864
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3083662283
Short name T1474
Test name
Test status
Simulation time 183267233 ps
CPU time 2.32 seconds
Started Apr 25 12:34:43 PM PDT 24
Finished Apr 25 12:34:48 PM PDT 24
Peak memory 212012 kb
Host smart-67f583d0-c8c1-40ef-b021-44a7548aa753
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3083662283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3083662283
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2379272924
Short name T1475
Test name
Test status
Simulation time 83500156 ps
CPU time 2.36 seconds
Started Apr 25 12:34:34 PM PDT 24
Finished Apr 25 12:34:40 PM PDT 24
Peak memory 203772 kb
Host smart-0e016551-ccc3-4310-8c22-8470752c6c20
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2379272924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2379272924
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.4078044069
Short name T95
Test name
Test status
Simulation time 96959555 ps
CPU time 1.4 seconds
Started Apr 25 12:34:36 PM PDT 24
Finished Apr 25 12:34:41 PM PDT 24
Peak memory 203816 kb
Host smart-68bf5166-5a54-44ef-b199-b27a51bec35b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4078044069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.4078044069
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.263406648
Short name T1428
Test name
Test status
Simulation time 107867087 ps
CPU time 1.42 seconds
Started Apr 25 12:34:44 PM PDT 24
Finished Apr 25 12:34:48 PM PDT 24
Peak memory 203832 kb
Host smart-4931a0c9-c9cf-4118-a698-bacfab0a7e11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=263406648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.263406648
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3467435762
Short name T213
Test name
Test status
Simulation time 616287860 ps
CPU time 3.07 seconds
Started Apr 25 12:34:36 PM PDT 24
Finished Apr 25 12:34:43 PM PDT 24
Peak memory 203856 kb
Host smart-3c427311-8a9b-4aac-9645-9458d0b5dc1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3467435762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.3467435762
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3861334612
Short name T64
Test name
Test status
Simulation time 30492238 ps
CPU time 0.66 seconds
Started Apr 25 12:34:54 PM PDT 24
Finished Apr 25 12:34:56 PM PDT 24
Peak memory 203132 kb
Host smart-2c21f937-8252-4b87-b0cb-2cc679b83223
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3861334612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3861334612
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1675933617
Short name T1423
Test name
Test status
Simulation time 35999348 ps
CPU time 0.69 seconds
Started Apr 25 12:34:54 PM PDT 24
Finished Apr 25 12:34:56 PM PDT 24
Peak memory 203148 kb
Host smart-5b698bb1-fb4c-4fa6-af98-02d2027e972c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1675933617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.1675933617
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1205484319
Short name T293
Test name
Test status
Simulation time 65440723 ps
CPU time 0.68 seconds
Started Apr 25 12:34:55 PM PDT 24
Finished Apr 25 12:34:58 PM PDT 24
Peak memory 203104 kb
Host smart-cddc669f-8c26-4c7f-8d48-9f058782e2b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1205484319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1205484319
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3227733040
Short name T1449
Test name
Test status
Simulation time 33654489 ps
CPU time 0.64 seconds
Started Apr 25 12:34:55 PM PDT 24
Finished Apr 25 12:34:57 PM PDT 24
Peak memory 203112 kb
Host smart-a5a665d7-d4d3-4a79-8d83-3d25295b8e18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3227733040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3227733040
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.607208992
Short name T1395
Test name
Test status
Simulation time 43555172 ps
CPU time 0.65 seconds
Started Apr 25 12:34:55 PM PDT 24
Finished Apr 25 12:34:57 PM PDT 24
Peak memory 203128 kb
Host smart-67dce86c-d49c-475b-930b-01af41153869
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=607208992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.607208992
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2028393199
Short name T1431
Test name
Test status
Simulation time 31050909 ps
CPU time 0.64 seconds
Started Apr 25 12:35:05 PM PDT 24
Finished Apr 25 12:35:07 PM PDT 24
Peak memory 203068 kb
Host smart-d4b96335-3a5b-4181-ac24-44aca96c0a9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2028393199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2028393199
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3019186438
Short name T1399
Test name
Test status
Simulation time 40006330 ps
CPU time 0.66 seconds
Started Apr 25 12:34:54 PM PDT 24
Finished Apr 25 12:34:57 PM PDT 24
Peak memory 203132 kb
Host smart-4716cd21-e402-4440-937b-093d358f5f97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3019186438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.3019186438
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1783212298
Short name T1480
Test name
Test status
Simulation time 27131488 ps
CPU time 0.69 seconds
Started Apr 25 12:35:15 PM PDT 24
Finished Apr 25 12:35:20 PM PDT 24
Peak memory 203096 kb
Host smart-57af2b76-248c-4b4d-af4b-ffd00a6e8a8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1783212298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.1783212298
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3648399375
Short name T1427
Test name
Test status
Simulation time 29739979 ps
CPU time 0.68 seconds
Started Apr 25 12:35:04 PM PDT 24
Finished Apr 25 12:35:06 PM PDT 24
Peak memory 203100 kb
Host smart-d53fa2f5-cb58-4b89-b58b-8daafdfd2db6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3648399375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3648399375
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1579060523
Short name T1438
Test name
Test status
Simulation time 22804974 ps
CPU time 0.7 seconds
Started Apr 25 12:35:01 PM PDT 24
Finished Apr 25 12:35:03 PM PDT 24
Peak memory 203084 kb
Host smart-d5d9ea10-1946-4e86-a3ff-36f3b81e4902
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1579060523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1579060523
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3284592389
Short name T1448
Test name
Test status
Simulation time 189959240 ps
CPU time 2.01 seconds
Started Apr 25 12:34:36 PM PDT 24
Finished Apr 25 12:34:42 PM PDT 24
Peak memory 203904 kb
Host smart-35c183e7-2e7e-455b-89c3-f7582f0cdef2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3284592389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3284592389
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3898991289
Short name T270
Test name
Test status
Simulation time 1030309717 ps
CPU time 4.72 seconds
Started Apr 25 12:34:38 PM PDT 24
Finished Apr 25 12:34:47 PM PDT 24
Peak memory 203712 kb
Host smart-4e90ff19-eeec-439a-88ad-0df7c4eb7e13
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3898991289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3898991289
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1999569789
Short name T251
Test name
Test status
Simulation time 161318845 ps
CPU time 1.97 seconds
Started Apr 25 12:34:39 PM PDT 24
Finished Apr 25 12:34:45 PM PDT 24
Peak memory 212036 kb
Host smart-59370707-78bc-4264-a32c-22379fd5539a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999569789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.1999569789
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1566794417
Short name T1393
Test name
Test status
Simulation time 63558247 ps
CPU time 1.03 seconds
Started Apr 25 12:34:38 PM PDT 24
Finished Apr 25 12:34:43 PM PDT 24
Peak memory 203740 kb
Host smart-3ab9ae81-3eed-4edd-956d-43b74ce25427
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1566794417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1566794417
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.91542192
Short name T1418
Test name
Test status
Simulation time 27844447 ps
CPU time 0.63 seconds
Started Apr 25 12:34:37 PM PDT 24
Finished Apr 25 12:34:41 PM PDT 24
Peak memory 203012 kb
Host smart-bb26c946-58f6-4f07-bf59-02766f1d5801
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=91542192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.91542192
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2299208657
Short name T278
Test name
Test status
Simulation time 49099733 ps
CPU time 1.28 seconds
Started Apr 25 12:34:38 PM PDT 24
Finished Apr 25 12:34:44 PM PDT 24
Peak memory 212008 kb
Host smart-6ac11653-c509-48ca-8beb-109f0dab7fa9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2299208657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2299208657
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3409027589
Short name T1450
Test name
Test status
Simulation time 616092710 ps
CPU time 4.56 seconds
Started Apr 25 12:34:39 PM PDT 24
Finished Apr 25 12:34:47 PM PDT 24
Peak memory 203716 kb
Host smart-69910dc4-4365-4bdc-9354-b5c5e5bf5f79
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3409027589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3409027589
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.814464821
Short name T1408
Test name
Test status
Simulation time 85570862 ps
CPU time 1.15 seconds
Started Apr 25 12:34:36 PM PDT 24
Finished Apr 25 12:34:41 PM PDT 24
Peak memory 203860 kb
Host smart-9df7314b-5a18-493b-a4cb-43aa0ddbb0e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=814464821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.814464821
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2858210615
Short name T244
Test name
Test status
Simulation time 244212441 ps
CPU time 2.68 seconds
Started Apr 25 12:34:33 PM PDT 24
Finished Apr 25 12:34:38 PM PDT 24
Peak memory 204028 kb
Host smart-6dec664e-0499-4a4b-b183-d13d4c1b003e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2858210615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2858210615
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2511149154
Short name T287
Test name
Test status
Simulation time 2182781928 ps
CPU time 6.35 seconds
Started Apr 25 12:34:33 PM PDT 24
Finished Apr 25 12:34:43 PM PDT 24
Peak memory 203940 kb
Host smart-222b50d2-b10c-45a8-ad80-ea76c971bf39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2511149154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2511149154
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2303263980
Short name T291
Test name
Test status
Simulation time 43296661 ps
CPU time 0.66 seconds
Started Apr 25 12:34:58 PM PDT 24
Finished Apr 25 12:35:00 PM PDT 24
Peak memory 203036 kb
Host smart-6d4d7114-076a-4ab6-af7c-6bbd51075869
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2303263980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.2303263980
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.772159149
Short name T1404
Test name
Test status
Simulation time 36956566 ps
CPU time 0.6 seconds
Started Apr 25 12:35:40 PM PDT 24
Finished Apr 25 12:35:43 PM PDT 24
Peak memory 203064 kb
Host smart-0ebf6303-22b1-4a92-aef1-b9499f030853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=772159149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.772159149
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1011589524
Short name T1478
Test name
Test status
Simulation time 49545671 ps
CPU time 0.67 seconds
Started Apr 25 12:35:08 PM PDT 24
Finished Apr 25 12:35:10 PM PDT 24
Peak memory 203052 kb
Host smart-ab152716-7401-4699-9518-75da4ffb6a27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1011589524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.1011589524
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.380461173
Short name T61
Test name
Test status
Simulation time 39141912 ps
CPU time 0.67 seconds
Started Apr 25 12:34:59 PM PDT 24
Finished Apr 25 12:35:01 PM PDT 24
Peak memory 203056 kb
Host smart-36a26d0c-ddce-44df-8b10-42da53838c72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=380461173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.380461173
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2549444315
Short name T1457
Test name
Test status
Simulation time 27275521 ps
CPU time 0.62 seconds
Started Apr 25 12:34:57 PM PDT 24
Finished Apr 25 12:34:59 PM PDT 24
Peak memory 203052 kb
Host smart-78eecf37-a6e6-45cf-a5a5-1b3e83b9c378
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2549444315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.2549444315
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2858613573
Short name T1477
Test name
Test status
Simulation time 29654359 ps
CPU time 0.71 seconds
Started Apr 25 12:35:09 PM PDT 24
Finished Apr 25 12:35:12 PM PDT 24
Peak memory 203164 kb
Host smart-d5e68e59-8d74-46aa-9830-f114c6c9c931
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2858613573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2858613573
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2933512023
Short name T62
Test name
Test status
Simulation time 26573496 ps
CPU time 0.66 seconds
Started Apr 25 12:35:09 PM PDT 24
Finished Apr 25 12:35:13 PM PDT 24
Peak memory 203044 kb
Host smart-719f0eff-57be-4c72-a6f1-23649ddfd2b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2933512023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2933512023
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.98148412
Short name T1416
Test name
Test status
Simulation time 40103107 ps
CPU time 0.7 seconds
Started Apr 25 12:35:12 PM PDT 24
Finished Apr 25 12:35:18 PM PDT 24
Peak memory 203028 kb
Host smart-5d136ea6-5810-4033-8d9e-8686e8a06a70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=98148412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.98148412
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2841762783
Short name T1462
Test name
Test status
Simulation time 24415981 ps
CPU time 0.63 seconds
Started Apr 25 12:35:10 PM PDT 24
Finished Apr 25 12:35:14 PM PDT 24
Peak memory 203056 kb
Host smart-8042bd11-84d3-4699-9815-a800f9e0dd25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2841762783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2841762783
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1635420714
Short name T1441
Test name
Test status
Simulation time 65734130 ps
CPU time 1.92 seconds
Started Apr 25 12:34:39 PM PDT 24
Finished Apr 25 12:34:45 PM PDT 24
Peak memory 203732 kb
Host smart-e08a9871-d3e1-44dd-9dbe-73aba02d2403
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1635420714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.1635420714
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1028943376
Short name T266
Test name
Test status
Simulation time 964474454 ps
CPU time 7.57 seconds
Started Apr 25 12:34:41 PM PDT 24
Finished Apr 25 12:34:52 PM PDT 24
Peak memory 203812 kb
Host smart-b9e448e8-e22c-404d-9799-c60cacbd574e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1028943376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1028943376
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3611787622
Short name T1440
Test name
Test status
Simulation time 69196442 ps
CPU time 0.79 seconds
Started Apr 25 12:36:10 PM PDT 24
Finished Apr 25 12:36:14 PM PDT 24
Peak memory 203508 kb
Host smart-19c6d79a-79d1-44a2-ab19-6ddeffb994f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3611787622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3611787622
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3732505140
Short name T1447
Test name
Test status
Simulation time 77130339 ps
CPU time 1.16 seconds
Started Apr 25 12:35:08 PM PDT 24
Finished Apr 25 12:35:10 PM PDT 24
Peak memory 212052 kb
Host smart-d68be985-0bc8-4535-9c9a-e50b2f94e86d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732505140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.3732505140
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2263121206
Short name T271
Test name
Test status
Simulation time 36300176 ps
CPU time 0.75 seconds
Started Apr 25 12:34:51 PM PDT 24
Finished Apr 25 12:34:54 PM PDT 24
Peak memory 203572 kb
Host smart-7949ce5d-d116-4966-a084-81421d399cfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2263121206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2263121206
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3548186565
Short name T1411
Test name
Test status
Simulation time 39141048 ps
CPU time 0.69 seconds
Started Apr 25 12:34:37 PM PDT 24
Finished Apr 25 12:34:42 PM PDT 24
Peak memory 203120 kb
Host smart-44746c30-d8a5-49ff-b05c-331f94e646c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3548186565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3548186565
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1883863751
Short name T267
Test name
Test status
Simulation time 47582241 ps
CPU time 1.39 seconds
Started Apr 25 12:34:38 PM PDT 24
Finished Apr 25 12:34:44 PM PDT 24
Peak memory 212024 kb
Host smart-fe095e20-e878-42ae-8053-495c4abf1413
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1883863751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1883863751
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1424905129
Short name T1389
Test name
Test status
Simulation time 167094729 ps
CPU time 4.03 seconds
Started Apr 25 12:34:35 PM PDT 24
Finished Apr 25 12:34:43 PM PDT 24
Peak memory 203760 kb
Host smart-4fc39f71-a7d2-405a-9c55-193aa8fbabab
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1424905129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1424905129
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1633226304
Short name T1401
Test name
Test status
Simulation time 189654447 ps
CPU time 1.59 seconds
Started Apr 25 12:34:38 PM PDT 24
Finished Apr 25 12:34:44 PM PDT 24
Peak memory 203876 kb
Host smart-14806e46-b9c3-4e09-9967-d28cd83450ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1633226304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.1633226304
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3688455852
Short name T1434
Test name
Test status
Simulation time 55024477 ps
CPU time 1.46 seconds
Started Apr 25 12:34:54 PM PDT 24
Finished Apr 25 12:34:57 PM PDT 24
Peak memory 203908 kb
Host smart-8bb1616a-96a9-4fba-95be-2066a21a76a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3688455852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3688455852
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2149513699
Short name T1435
Test name
Test status
Simulation time 166570653 ps
CPU time 2.37 seconds
Started Apr 25 12:34:35 PM PDT 24
Finished Apr 25 12:34:41 PM PDT 24
Peak memory 203804 kb
Host smart-af614fdb-d68c-4ab6-90c6-34dcb954fa18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2149513699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2149513699
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3793457800
Short name T1429
Test name
Test status
Simulation time 32762542 ps
CPU time 0.72 seconds
Started Apr 25 12:35:09 PM PDT 24
Finished Apr 25 12:35:13 PM PDT 24
Peak memory 203160 kb
Host smart-2089debe-8f6a-4e6c-b620-6877f59a27fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3793457800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3793457800
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1764360093
Short name T1436
Test name
Test status
Simulation time 47703506 ps
CPU time 0.71 seconds
Started Apr 25 12:35:05 PM PDT 24
Finished Apr 25 12:35:07 PM PDT 24
Peak memory 203124 kb
Host smart-24d7c1b1-d264-476e-9141-c448dc074f39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1764360093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1764360093
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3875326783
Short name T1439
Test name
Test status
Simulation time 31763800 ps
CPU time 0.67 seconds
Started Apr 25 12:35:09 PM PDT 24
Finished Apr 25 12:35:12 PM PDT 24
Peak memory 203076 kb
Host smart-df2e2e81-d48c-4c2d-850f-419b6524e658
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3875326783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.3875326783
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3306176189
Short name T295
Test name
Test status
Simulation time 32729357 ps
CPU time 0.67 seconds
Started Apr 25 12:35:20 PM PDT 24
Finished Apr 25 12:35:23 PM PDT 24
Peak memory 203044 kb
Host smart-dfbf5b58-df03-4964-87e7-bf787ed51900
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3306176189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3306176189
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1765929799
Short name T1397
Test name
Test status
Simulation time 50952028 ps
CPU time 0.65 seconds
Started Apr 25 12:35:08 PM PDT 24
Finished Apr 25 12:35:10 PM PDT 24
Peak memory 203116 kb
Host smart-db37de05-1faa-421d-92b9-3dd75dd163a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1765929799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.1765929799
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3310765260
Short name T1419
Test name
Test status
Simulation time 30483935 ps
CPU time 0.71 seconds
Started Apr 25 12:34:57 PM PDT 24
Finished Apr 25 12:35:00 PM PDT 24
Peak memory 203052 kb
Host smart-48820ed2-3cfc-4c64-a174-1d425337dbd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3310765260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.3310765260
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.718562802
Short name T1394
Test name
Test status
Simulation time 28986392 ps
CPU time 0.67 seconds
Started Apr 25 12:35:03 PM PDT 24
Finished Apr 25 12:35:05 PM PDT 24
Peak memory 203116 kb
Host smart-88580536-0643-4dff-a109-d3c27ae2ddbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=718562802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.718562802
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.144095793
Short name T297
Test name
Test status
Simulation time 32623222 ps
CPU time 0.65 seconds
Started Apr 25 12:35:10 PM PDT 24
Finished Apr 25 12:35:15 PM PDT 24
Peak memory 203024 kb
Host smart-8db58ea4-f97e-43bd-9430-490af332795e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=144095793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.144095793
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.582404499
Short name T1391
Test name
Test status
Simulation time 31537514 ps
CPU time 0.65 seconds
Started Apr 25 12:35:05 PM PDT 24
Finished Apr 25 12:35:06 PM PDT 24
Peak memory 203112 kb
Host smart-f39eab5d-3ba6-4864-a2d7-c94cf83fc130
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=582404499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.582404499
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.243547866
Short name T1453
Test name
Test status
Simulation time 122420437 ps
CPU time 1.2 seconds
Started Apr 25 12:34:52 PM PDT 24
Finished Apr 25 12:34:56 PM PDT 24
Peak memory 213292 kb
Host smart-ad42f320-0b9f-4c49-bda3-9f4f7f685ae7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243547866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev
_csr_mem_rw_with_rand_reset.243547866
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2166846618
Short name T1455
Test name
Test status
Simulation time 30419492 ps
CPU time 0.81 seconds
Started Apr 25 12:35:06 PM PDT 24
Finished Apr 25 12:35:08 PM PDT 24
Peak memory 203572 kb
Host smart-c5d8b1d7-29eb-49cc-bcae-253b0de02582
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2166846618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.2166846618
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.752898255
Short name T296
Test name
Test status
Simulation time 38996430 ps
CPU time 0.69 seconds
Started Apr 25 12:34:45 PM PDT 24
Finished Apr 25 12:34:49 PM PDT 24
Peak memory 203104 kb
Host smart-82b343ac-6886-41fe-999d-d4ea9aa0e104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=752898255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.752898255
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.584492399
Short name T289
Test name
Test status
Simulation time 82629426 ps
CPU time 1.08 seconds
Started Apr 25 12:34:49 PM PDT 24
Finished Apr 25 12:34:51 PM PDT 24
Peak memory 203808 kb
Host smart-3e9d7606-cc02-46c9-8ee3-830ba36c32ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=584492399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.584492399
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2722848939
Short name T1470
Test name
Test status
Simulation time 112165702 ps
CPU time 1.58 seconds
Started Apr 25 12:34:51 PM PDT 24
Finished Apr 25 12:34:55 PM PDT 24
Peak memory 203880 kb
Host smart-b930b5d2-e2f2-44b3-8b30-b0f16ee4986f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2722848939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2722848939
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.860435018
Short name T1398
Test name
Test status
Simulation time 174914270 ps
CPU time 1.91 seconds
Started Apr 25 12:34:45 PM PDT 24
Finished Apr 25 12:34:50 PM PDT 24
Peak memory 212092 kb
Host smart-a8c0bc39-e887-4e11-b5e7-152b0b9dd609
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860435018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev
_csr_mem_rw_with_rand_reset.860435018
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3650631654
Short name T1452
Test name
Test status
Simulation time 35651852 ps
CPU time 0.81 seconds
Started Apr 25 12:34:53 PM PDT 24
Finished Apr 25 12:34:56 PM PDT 24
Peak memory 203540 kb
Host smart-77da8797-fcef-4d47-bf18-fc7abc818336
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3650631654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3650631654
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2372315696
Short name T300
Test name
Test status
Simulation time 28590227 ps
CPU time 0.67 seconds
Started Apr 25 12:34:45 PM PDT 24
Finished Apr 25 12:34:48 PM PDT 24
Peak memory 203164 kb
Host smart-2537f815-4e96-4d1a-b9d6-cf7eced7510f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2372315696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2372315696
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3157543998
Short name T98
Test name
Test status
Simulation time 458232233 ps
CPU time 2.06 seconds
Started Apr 25 12:34:41 PM PDT 24
Finished Apr 25 12:34:47 PM PDT 24
Peak memory 203852 kb
Host smart-839a2d9e-a943-483e-8ce9-74c4d654ea1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3157543998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.3157543998
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1778819258
Short name T216
Test name
Test status
Simulation time 94244598 ps
CPU time 1.32 seconds
Started Apr 25 12:34:53 PM PDT 24
Finished Apr 25 12:34:56 PM PDT 24
Peak memory 203912 kb
Host smart-0298e830-ad77-485b-a559-50b9d0e9ccf1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1778819258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1778819258
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2430671391
Short name T310
Test name
Test status
Simulation time 773319388 ps
CPU time 4.94 seconds
Started Apr 25 12:34:47 PM PDT 24
Finished Apr 25 12:34:54 PM PDT 24
Peak memory 203756 kb
Host smart-70884342-1c16-4e40-a833-e2a701b3af09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2430671391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2430671391
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1828065325
Short name T1410
Test name
Test status
Simulation time 87049035 ps
CPU time 1.18 seconds
Started Apr 25 12:34:51 PM PDT 24
Finished Apr 25 12:34:54 PM PDT 24
Peak memory 212056 kb
Host smart-0ef05cbd-6849-49ae-a498-e694a243a594
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828065325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.1828065325
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1141412666
Short name T1463
Test name
Test status
Simulation time 60410817 ps
CPU time 0.96 seconds
Started Apr 25 12:34:53 PM PDT 24
Finished Apr 25 12:34:56 PM PDT 24
Peak memory 203772 kb
Host smart-c318622a-7512-4d52-bd45-47610c18f985
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1141412666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1141412666
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2427779523
Short name T299
Test name
Test status
Simulation time 40843127 ps
CPU time 0.69 seconds
Started Apr 25 12:35:07 PM PDT 24
Finished Apr 25 12:35:13 PM PDT 24
Peak memory 203056 kb
Host smart-ea656ce7-feb9-4e51-8eef-635023f94524
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2427779523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2427779523
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3068892895
Short name T58
Test name
Test status
Simulation time 226876825 ps
CPU time 1.69 seconds
Started Apr 25 12:34:42 PM PDT 24
Finished Apr 25 12:34:47 PM PDT 24
Peak memory 203864 kb
Host smart-bfa20654-18ba-49df-b34d-9841b53aba2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3068892895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.3068892895
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2904293912
Short name T1472
Test name
Test status
Simulation time 180704802 ps
CPU time 2.14 seconds
Started Apr 25 12:34:46 PM PDT 24
Finished Apr 25 12:34:50 PM PDT 24
Peak memory 203848 kb
Host smart-e12219be-0d39-4f6a-b7e4-447a8f5ca4c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2904293912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2904293912
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3899659572
Short name T1460
Test name
Test status
Simulation time 480346278 ps
CPU time 3.15 seconds
Started Apr 25 12:35:06 PM PDT 24
Finished Apr 25 12:35:11 PM PDT 24
Peak memory 203868 kb
Host smart-cf2abf1a-45e3-4366-8abb-eaf23ad518a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3899659572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3899659572
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3830809281
Short name T1445
Test name
Test status
Simulation time 79238892 ps
CPU time 1.16 seconds
Started Apr 25 12:35:09 PM PDT 24
Finished Apr 25 12:35:13 PM PDT 24
Peak memory 212052 kb
Host smart-a28b9366-aa73-4520-9733-58a26b560e88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830809281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.3830809281
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1263945903
Short name T1476
Test name
Test status
Simulation time 45442319 ps
CPU time 0.84 seconds
Started Apr 25 12:34:53 PM PDT 24
Finished Apr 25 12:34:56 PM PDT 24
Peak memory 203536 kb
Host smart-1a8b2f43-0263-4935-b9c8-48901c05b76c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1263945903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1263945903
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3513165
Short name T1407
Test name
Test status
Simulation time 38755258 ps
CPU time 0.67 seconds
Started Apr 25 12:34:51 PM PDT 24
Finished Apr 25 12:34:53 PM PDT 24
Peak memory 203124 kb
Host smart-438a78d2-fb65-4c4e-9e37-ce3d9137e4a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3513165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.3513165
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.367286805
Short name T1479
Test name
Test status
Simulation time 101515397 ps
CPU time 1.14 seconds
Started Apr 25 12:34:51 PM PDT 24
Finished Apr 25 12:34:54 PM PDT 24
Peak memory 203852 kb
Host smart-ea77c3f5-af03-4b69-862b-2fbd6c52fbf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=367286805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.367286805
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1695456643
Short name T237
Test name
Test status
Simulation time 69712856 ps
CPU time 1.57 seconds
Started Apr 25 12:34:49 PM PDT 24
Finished Apr 25 12:34:51 PM PDT 24
Peak memory 203860 kb
Host smart-3c1c2472-c814-44f7-b5e3-ebaf62ce2b16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1695456643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1695456643
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3120073748
Short name T304
Test name
Test status
Simulation time 394902598 ps
CPU time 2.56 seconds
Started Apr 25 12:34:53 PM PDT 24
Finished Apr 25 12:34:57 PM PDT 24
Peak memory 203880 kb
Host smart-30c4c911-2310-4775-bd84-d82d21119f75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3120073748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3120073748
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.4236633441
Short name T242
Test name
Test status
Simulation time 75095094 ps
CPU time 1.2 seconds
Started Apr 25 12:34:48 PM PDT 24
Finished Apr 25 12:34:50 PM PDT 24
Peak memory 212128 kb
Host smart-f6caa4c0-2ef4-41d2-a1ce-11af43709d6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236633441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.4236633441
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4204430787
Short name T280
Test name
Test status
Simulation time 43581995 ps
CPU time 0.84 seconds
Started Apr 25 12:34:49 PM PDT 24
Finished Apr 25 12:34:52 PM PDT 24
Peak memory 203492 kb
Host smart-34bfa6c3-ba58-4446-9b0d-27b4ef835173
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4204430787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.4204430787
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1216186874
Short name T1396
Test name
Test status
Simulation time 51383479 ps
CPU time 0.68 seconds
Started Apr 25 12:34:47 PM PDT 24
Finished Apr 25 12:34:50 PM PDT 24
Peak memory 203080 kb
Host smart-6f579ea5-e858-4dab-8430-53cae42965c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1216186874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1216186874
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.79877038
Short name T1413
Test name
Test status
Simulation time 42238140 ps
CPU time 1.01 seconds
Started Apr 25 12:34:40 PM PDT 24
Finished Apr 25 12:34:45 PM PDT 24
Peak memory 203736 kb
Host smart-55b5e36f-27c4-41db-ace6-5bf4b98a76c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=79877038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.79877038
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.515678035
Short name T210
Test name
Test status
Simulation time 173251558 ps
CPU time 2.39 seconds
Started Apr 25 12:34:51 PM PDT 24
Finished Apr 25 12:34:55 PM PDT 24
Peak memory 203804 kb
Host smart-f26398e3-1f55-4796-8bb9-a57a4e2f944a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=515678035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.515678035
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2827103056
Short name T311
Test name
Test status
Simulation time 292253278 ps
CPU time 2.58 seconds
Started Apr 25 12:34:45 PM PDT 24
Finished Apr 25 12:34:50 PM PDT 24
Peak memory 203804 kb
Host smart-07460bab-a9f3-4261-aa94-d810f3fdb740
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2827103056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.2827103056
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.3152916645
Short name T1006
Test name
Test status
Simulation time 8464055036 ps
CPU time 7.69 seconds
Started Apr 25 02:28:39 PM PDT 24
Finished Apr 25 02:28:48 PM PDT 24
Peak memory 204136 kb
Host smart-cd67e219-3479-488e-8b30-a4640d11aeb8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3152916645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.3152916645
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.3411590541
Short name T378
Test name
Test status
Simulation time 8381396332 ps
CPU time 7.82 seconds
Started Apr 25 02:28:35 PM PDT 24
Finished Apr 25 02:28:43 PM PDT 24
Peak memory 204140 kb
Host smart-98c5d2a0-5ae8-439c-bd94-1909e09bf23f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3411590541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.3411590541
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.3765067287
Short name T410
Test name
Test status
Simulation time 8436918658 ps
CPU time 9.53 seconds
Started Apr 25 02:28:35 PM PDT 24
Finished Apr 25 02:28:45 PM PDT 24
Peak memory 204148 kb
Host smart-79fd8fe4-c016-4f9e-88d5-6fa084140c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37650
67287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.3765067287
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.1749464816
Short name T1206
Test name
Test status
Simulation time 8381003547 ps
CPU time 7.57 seconds
Started Apr 25 02:28:14 PM PDT 24
Finished Apr 25 02:28:22 PM PDT 24
Peak memory 204108 kb
Host smart-9d984f50-5e7e-4abc-9f35-0402c7d0b33f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17494
64816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.1749464816
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_enable.2355477503
Short name T665
Test name
Test status
Simulation time 8375902129 ps
CPU time 8.41 seconds
Started Apr 25 02:28:15 PM PDT 24
Finished Apr 25 02:28:24 PM PDT 24
Peak memory 204144 kb
Host smart-f5be8232-af24-4568-a225-6af75b77b085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23554
77503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.2355477503
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.445895001
Short name T1205
Test name
Test status
Simulation time 189980209 ps
CPU time 1.57 seconds
Started Apr 25 02:28:14 PM PDT 24
Finished Apr 25 02:28:16 PM PDT 24
Peak memory 204284 kb
Host smart-2e85dbd3-e406-4eca-9872-b245c3dcde2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44589
5001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.445895001
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.3130495151
Short name T673
Test name
Test status
Simulation time 8429027253 ps
CPU time 7.7 seconds
Started Apr 25 02:28:36 PM PDT 24
Finished Apr 25 02:28:44 PM PDT 24
Peak memory 204096 kb
Host smart-bf025477-957e-464b-9172-df4b69e4ba80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31304
95151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.3130495151
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.4137293245
Short name T191
Test name
Test status
Simulation time 8372283466 ps
CPU time 8.06 seconds
Started Apr 25 02:28:29 PM PDT 24
Finished Apr 25 02:28:38 PM PDT 24
Peak memory 204136 kb
Host smart-18983bf2-5c0d-4798-8a9f-f518c25d4164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41372
93245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.4137293245
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2725748901
Short name T916
Test name
Test status
Simulation time 8393446724 ps
CPU time 8.33 seconds
Started Apr 25 02:28:14 PM PDT 24
Finished Apr 25 02:28:23 PM PDT 24
Peak memory 204148 kb
Host smart-6b3aba05-1c60-460a-9fbf-0bb6e93311d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27257
48901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2725748901
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.2734740445
Short name T393
Test name
Test status
Simulation time 8409612257 ps
CPU time 7.73 seconds
Started Apr 25 02:28:23 PM PDT 24
Finished Apr 25 02:28:31 PM PDT 24
Peak memory 204108 kb
Host smart-d3e3e302-841e-4b53-b839-5372e2d80e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27347
40445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.2734740445
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.3887512238
Short name T882
Test name
Test status
Simulation time 8373688657 ps
CPU time 8.82 seconds
Started Apr 25 02:28:19 PM PDT 24
Finished Apr 25 02:28:28 PM PDT 24
Peak memory 204152 kb
Host smart-5512b0a2-580a-437e-b682-f61ce6263fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38875
12238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.3887512238
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.2064377049
Short name T438
Test name
Test status
Simulation time 8384725887 ps
CPU time 7.37 seconds
Started Apr 25 02:28:20 PM PDT 24
Finished Apr 25 02:28:29 PM PDT 24
Peak memory 204124 kb
Host smart-9de3e002-04bd-4de0-b403-62986ed048d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20643
77049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.2064377049
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.3519637126
Short name T836
Test name
Test status
Simulation time 8375878222 ps
CPU time 7.69 seconds
Started Apr 25 02:28:23 PM PDT 24
Finished Apr 25 02:28:31 PM PDT 24
Peak memory 204108 kb
Host smart-35f0778b-ef08-4363-8a4c-96ea0cc17d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35196
37126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.3519637126
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.2782349996
Short name T653
Test name
Test status
Simulation time 8361850879 ps
CPU time 7.66 seconds
Started Apr 25 02:28:28 PM PDT 24
Finished Apr 25 02:28:37 PM PDT 24
Peak memory 204128 kb
Host smart-317eb64f-3e56-4e61-af51-b40070fd605f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27823
49996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.2782349996
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.3171103072
Short name T41
Test name
Test status
Simulation time 94739116 ps
CPU time 0.72 seconds
Started Apr 25 02:28:28 PM PDT 24
Finished Apr 25 02:28:30 PM PDT 24
Peak memory 204020 kb
Host smart-552f3f72-92b8-4ebe-96cc-c0e0c58f701b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31711
03072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.3171103072
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.386080283
Short name T264
Test name
Test status
Simulation time 18815779627 ps
CPU time 32.8 seconds
Started Apr 25 02:28:21 PM PDT 24
Finished Apr 25 02:28:54 PM PDT 24
Peak memory 204432 kb
Host smart-effbbf82-abdc-4bd4-af3a-f8b3bb442ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38608
0283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.386080283
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.1130638111
Short name T892
Test name
Test status
Simulation time 8399957822 ps
CPU time 7.64 seconds
Started Apr 25 02:28:21 PM PDT 24
Finished Apr 25 02:28:29 PM PDT 24
Peak memory 204148 kb
Host smart-294912e9-d8c6-4511-af14-e1c6942fafb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11306
38111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.1130638111
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.1581822110
Short name T492
Test name
Test status
Simulation time 8438311401 ps
CPU time 7.62 seconds
Started Apr 25 02:28:28 PM PDT 24
Finished Apr 25 02:28:37 PM PDT 24
Peak memory 204112 kb
Host smart-779874d8-660f-4ba6-a822-441e28480fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15818
22110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.1581822110
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.2971987310
Short name T1036
Test name
Test status
Simulation time 8379629413 ps
CPU time 7.24 seconds
Started Apr 25 02:28:28 PM PDT 24
Finished Apr 25 02:28:37 PM PDT 24
Peak memory 204120 kb
Host smart-11893389-2232-4843-9c85-1219ae621473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29719
87310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2971987310
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.3562389178
Short name T735
Test name
Test status
Simulation time 8370011517 ps
CPU time 7.88 seconds
Started Apr 25 02:28:33 PM PDT 24
Finished Apr 25 02:28:41 PM PDT 24
Peak memory 204128 kb
Host smart-27417589-d5df-4057-bd3c-ff3c671dc028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35623
89178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.3562389178
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.3900034714
Short name T537
Test name
Test status
Simulation time 8430637513 ps
CPU time 8.07 seconds
Started Apr 25 02:28:13 PM PDT 24
Finished Apr 25 02:28:22 PM PDT 24
Peak memory 204120 kb
Host smart-a6fe4304-e13c-486d-9476-ddfd705dc2d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39000
34714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3900034714
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.2877370142
Short name T376
Test name
Test status
Simulation time 8380394833 ps
CPU time 7.66 seconds
Started Apr 25 02:28:28 PM PDT 24
Finished Apr 25 02:28:37 PM PDT 24
Peak memory 204120 kb
Host smart-50c7624f-ef00-4769-bd44-bc52e502b94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28773
70142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.2877370142
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.4146147652
Short name T252
Test name
Test status
Simulation time 8410033014 ps
CPU time 8.65 seconds
Started Apr 25 02:28:30 PM PDT 24
Finished Apr 25 02:28:39 PM PDT 24
Peak memory 204116 kb
Host smart-596b4aa1-19ec-406e-9e4a-6abc9285bddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41461
47652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.4146147652
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.1287619173
Short name T696
Test name
Test status
Simulation time 8463066859 ps
CPU time 8.05 seconds
Started Apr 25 02:29:02 PM PDT 24
Finished Apr 25 02:29:12 PM PDT 24
Peak memory 204124 kb
Host smart-04682feb-92fd-4f30-a322-260105acd51b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1287619173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.1287619173
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.3929152266
Short name T1101
Test name
Test status
Simulation time 8386688304 ps
CPU time 8.06 seconds
Started Apr 25 02:29:00 PM PDT 24
Finished Apr 25 02:29:09 PM PDT 24
Peak memory 204080 kb
Host smart-283adcc1-613c-498c-af88-34090ee6008c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3929152266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.3929152266
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.1909873258
Short name T834
Test name
Test status
Simulation time 8423891203 ps
CPU time 7.67 seconds
Started Apr 25 02:29:03 PM PDT 24
Finished Apr 25 02:29:11 PM PDT 24
Peak memory 204096 kb
Host smart-b6931c3e-f9e8-4c4a-b61c-a9be9d04f231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19098
73258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.1909873258
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.947926918
Short name T838
Test name
Test status
Simulation time 8379244100 ps
CPU time 7.47 seconds
Started Apr 25 02:28:45 PM PDT 24
Finished Apr 25 02:28:53 PM PDT 24
Peak memory 204088 kb
Host smart-379de298-aa8c-4538-bb80-e2852b02953c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94792
6918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.947926918
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_enable.1271671454
Short name T1126
Test name
Test status
Simulation time 8370459035 ps
CPU time 8.32 seconds
Started Apr 25 02:28:43 PM PDT 24
Finished Apr 25 02:28:52 PM PDT 24
Peak memory 204100 kb
Host smart-721464c7-681d-4866-8c66-13058246dd15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12716
71454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.1271671454
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1712919667
Short name T719
Test name
Test status
Simulation time 144883484 ps
CPU time 1.59 seconds
Started Apr 25 02:28:41 PM PDT 24
Finished Apr 25 02:28:43 PM PDT 24
Peak memory 204252 kb
Host smart-4367ee4c-d98e-46ba-a0ed-542a3270985e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17129
19667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1712919667
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.3459709151
Short name T935
Test name
Test status
Simulation time 8371707931 ps
CPU time 7.98 seconds
Started Apr 25 02:29:01 PM PDT 24
Finished Apr 25 02:29:11 PM PDT 24
Peak memory 204100 kb
Host smart-b0ed7b85-226f-43d4-b6a7-3dfb575efe7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34597
09151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3459709151
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.397782966
Short name T729
Test name
Test status
Simulation time 8484886729 ps
CPU time 7.86 seconds
Started Apr 25 02:28:42 PM PDT 24
Finished Apr 25 02:28:50 PM PDT 24
Peak memory 204044 kb
Host smart-08edefb4-4653-4192-ab76-d035b459bd34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39778
2966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.397782966
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.183193869
Short name T1279
Test name
Test status
Simulation time 8413742981 ps
CPU time 7.84 seconds
Started Apr 25 02:28:42 PM PDT 24
Finished Apr 25 02:28:51 PM PDT 24
Peak memory 204084 kb
Host smart-7667cbc1-d51b-4906-826b-e956f7fd446e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18319
3869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.183193869
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.1206879628
Short name T322
Test name
Test status
Simulation time 8373644798 ps
CPU time 8.53 seconds
Started Apr 25 02:28:41 PM PDT 24
Finished Apr 25 02:28:50 PM PDT 24
Peak memory 204140 kb
Host smart-6221fcde-deb2-4620-a3af-6a5feb8279b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12068
79628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.1206879628
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.4279519187
Short name T1273
Test name
Test status
Simulation time 8383621525 ps
CPU time 8.28 seconds
Started Apr 25 02:28:50 PM PDT 24
Finished Apr 25 02:28:59 PM PDT 24
Peak memory 204052 kb
Host smart-40610b5d-ce2b-4bfa-a420-621e56ebb4d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42795
19187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.4279519187
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.3252053299
Short name T451
Test name
Test status
Simulation time 8394014419 ps
CPU time 7.75 seconds
Started Apr 25 02:28:48 PM PDT 24
Finished Apr 25 02:28:56 PM PDT 24
Peak memory 204128 kb
Host smart-bbadb046-b570-4778-be78-2706838fcee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32520
53299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3252053299
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.2903988477
Short name T591
Test name
Test status
Simulation time 8379051623 ps
CPU time 8.16 seconds
Started Apr 25 02:28:57 PM PDT 24
Finished Apr 25 02:29:05 PM PDT 24
Peak memory 204112 kb
Host smart-94a92d55-3768-4028-bed9-c88b6966f883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29039
88477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.2903988477
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.2871855178
Short name T1347
Test name
Test status
Simulation time 48014466 ps
CPU time 0.71 seconds
Started Apr 25 02:29:01 PM PDT 24
Finished Apr 25 02:29:03 PM PDT 24
Peak memory 204020 kb
Host smart-59e459c9-3f47-4f7a-98da-743bdcba5fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28718
55178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.2871855178
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.1316626306
Short name T866
Test name
Test status
Simulation time 13617926823 ps
CPU time 21.78 seconds
Started Apr 25 02:28:49 PM PDT 24
Finished Apr 25 02:29:11 PM PDT 24
Peak memory 204408 kb
Host smart-dae938d5-55e4-4daa-9e11-89efbb75dfd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13166
26306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.1316626306
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.3199136942
Short name T495
Test name
Test status
Simulation time 8461204775 ps
CPU time 8.26 seconds
Started Apr 25 02:28:48 PM PDT 24
Finished Apr 25 02:28:56 PM PDT 24
Peak memory 204116 kb
Host smart-5917233d-3d9d-4c1f-ac9a-84fede504ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31991
36942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.3199136942
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.3255951529
Short name T718
Test name
Test status
Simulation time 8435727957 ps
CPU time 7.61 seconds
Started Apr 25 02:28:54 PM PDT 24
Finished Apr 25 02:29:03 PM PDT 24
Peak memory 204100 kb
Host smart-1e32b73b-dc2e-4fb1-96b3-93b1091ffa8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32559
51529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.3255951529
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.1040549213
Short name T485
Test name
Test status
Simulation time 8402573673 ps
CPU time 8.5 seconds
Started Apr 25 02:28:57 PM PDT 24
Finished Apr 25 02:29:06 PM PDT 24
Peak memory 204116 kb
Host smart-c5d3ad76-609f-44c5-bbe3-872829d3db71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10405
49213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.1040549213
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.2635717630
Short name T56
Test name
Test status
Simulation time 258601463 ps
CPU time 1.15 seconds
Started Apr 25 02:29:02 PM PDT 24
Finished Apr 25 02:29:04 PM PDT 24
Peak memory 221536 kb
Host smart-ae564d45-1480-461e-9478-015a8ead2372
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2635717630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2635717630
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.4234718418
Short name T172
Test name
Test status
Simulation time 8373412213 ps
CPU time 9.75 seconds
Started Apr 25 02:28:58 PM PDT 24
Finished Apr 25 02:29:08 PM PDT 24
Peak memory 204140 kb
Host smart-22ae99ad-6d82-42ec-8743-582ef3f0b922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42347
18418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.4234718418
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.74671581
Short name T528
Test name
Test status
Simulation time 8403104808 ps
CPU time 7.19 seconds
Started Apr 25 02:28:55 PM PDT 24
Finished Apr 25 02:29:02 PM PDT 24
Peak memory 204140 kb
Host smart-ab205e50-ca5c-4729-aeac-af4871151d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74671
581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.74671581
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.1771496607
Short name T1172
Test name
Test status
Simulation time 8409090977 ps
CPU time 8.9 seconds
Started Apr 25 02:28:46 PM PDT 24
Finished Apr 25 02:28:56 PM PDT 24
Peak memory 204144 kb
Host smart-b6c0c04a-0db3-440d-963b-297f5dcc8caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17714
96607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.1771496607
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1337989851
Short name T962
Test name
Test status
Simulation time 8411655079 ps
CPU time 7.96 seconds
Started Apr 25 02:28:55 PM PDT 24
Finished Apr 25 02:29:04 PM PDT 24
Peak memory 204052 kb
Host smart-e88b0dcb-b8c3-4156-854c-af879407588b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13379
89851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1337989851
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.1013694095
Short name T789
Test name
Test status
Simulation time 8404928735 ps
CPU time 7.92 seconds
Started Apr 25 02:28:54 PM PDT 24
Finished Apr 25 02:29:02 PM PDT 24
Peak memory 204116 kb
Host smart-619df2cb-372d-4051-8ac5-f4577bccc0e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10136
94095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.1013694095
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.2755672031
Short name T449
Test name
Test status
Simulation time 8500403902 ps
CPU time 8.07 seconds
Started Apr 25 02:31:42 PM PDT 24
Finished Apr 25 02:31:52 PM PDT 24
Peak memory 204052 kb
Host smart-5635477c-99ab-4445-b4c2-c079cbdb300f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2755672031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.2755672031
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.1853149216
Short name T1213
Test name
Test status
Simulation time 8383392114 ps
CPU time 7.54 seconds
Started Apr 25 02:31:29 PM PDT 24
Finished Apr 25 02:31:37 PM PDT 24
Peak memory 204076 kb
Host smart-000aefef-78d8-4311-adda-47b468f10ddc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1853149216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.1853149216
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.1511858927
Short name T1330
Test name
Test status
Simulation time 8471001104 ps
CPU time 7.88 seconds
Started Apr 25 02:31:24 PM PDT 24
Finished Apr 25 02:31:33 PM PDT 24
Peak memory 204136 kb
Host smart-598d9d4a-ebd0-4c2d-b4dd-a7724c092c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15118
58927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.1511858927
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.3867923556
Short name T1002
Test name
Test status
Simulation time 8388360948 ps
CPU time 8.54 seconds
Started Apr 25 02:31:15 PM PDT 24
Finished Apr 25 02:31:25 PM PDT 24
Peak memory 204132 kb
Host smart-6959ea44-bcc4-43e3-bde9-9034a661fccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38679
23556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3867923556
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_enable.2638142691
Short name T579
Test name
Test status
Simulation time 8382560796 ps
CPU time 7.98 seconds
Started Apr 25 02:31:10 PM PDT 24
Finished Apr 25 02:31:20 PM PDT 24
Peak memory 204032 kb
Host smart-96377fe3-0a00-436b-a2b6-da4eacad2f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26381
42691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.2638142691
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.2925074241
Short name T221
Test name
Test status
Simulation time 250388690 ps
CPU time 2.14 seconds
Started Apr 25 02:31:20 PM PDT 24
Finished Apr 25 02:31:23 PM PDT 24
Peak memory 204280 kb
Host smart-af414b30-2855-4c0b-a32b-9305d324ca29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29250
74241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.2925074241
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.1509501941
Short name T1159
Test name
Test status
Simulation time 8400026254 ps
CPU time 8.52 seconds
Started Apr 25 02:31:18 PM PDT 24
Finished Apr 25 02:31:27 PM PDT 24
Peak memory 204076 kb
Host smart-6b38f870-61d2-4430-be76-5e11415f88e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15095
01941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.1509501941
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.3671702116
Short name T160
Test name
Test status
Simulation time 8424171268 ps
CPU time 7.53 seconds
Started Apr 25 02:31:23 PM PDT 24
Finished Apr 25 02:31:31 PM PDT 24
Peak memory 204116 kb
Host smart-de3c9edc-6647-4f84-a743-d73989d462bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36717
02116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3671702116
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.3147232892
Short name T1295
Test name
Test status
Simulation time 8423202508 ps
CPU time 8.1 seconds
Started Apr 25 02:31:21 PM PDT 24
Finished Apr 25 02:31:30 PM PDT 24
Peak memory 204112 kb
Host smart-e1fee5d1-d4eb-406e-9796-c48c11592bc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31472
32892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.3147232892
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.2138031558
Short name T498
Test name
Test status
Simulation time 8374990231 ps
CPU time 8.71 seconds
Started Apr 25 02:31:17 PM PDT 24
Finished Apr 25 02:31:27 PM PDT 24
Peak memory 204092 kb
Host smart-933781da-acac-425a-9611-3bd34e1cc67b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21380
31558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2138031558
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.1435813380
Short name T226
Test name
Test status
Simulation time 8412165401 ps
CPU time 8.26 seconds
Started Apr 25 02:31:22 PM PDT 24
Finished Apr 25 02:31:31 PM PDT 24
Peak memory 204120 kb
Host smart-89855e32-4028-47eb-acb4-7acf81b3663f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14358
13380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.1435813380
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1393102978
Short name T1306
Test name
Test status
Simulation time 8386724805 ps
CPU time 7.88 seconds
Started Apr 25 02:31:17 PM PDT 24
Finished Apr 25 02:31:26 PM PDT 24
Peak memory 204096 kb
Host smart-898ce4d5-af0f-41fa-ac56-5ce57e948a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13931
02978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1393102978
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.285680733
Short name T508
Test name
Test status
Simulation time 8372977724 ps
CPU time 8.84 seconds
Started Apr 25 02:31:56 PM PDT 24
Finished Apr 25 02:32:06 PM PDT 24
Peak memory 204112 kb
Host smart-a197e668-4dbf-49f2-9dbc-3e697fff7d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28568
0733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.285680733
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.1333873133
Short name T43
Test name
Test status
Simulation time 44963277 ps
CPU time 0.64 seconds
Started Apr 25 02:31:17 PM PDT 24
Finished Apr 25 02:31:19 PM PDT 24
Peak memory 204028 kb
Host smart-abe39c4e-361e-429e-9bf5-9e673cebc925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13338
73133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.1333873133
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.3882370526
Short name T967
Test name
Test status
Simulation time 22774917927 ps
CPU time 43.35 seconds
Started Apr 25 02:31:22 PM PDT 24
Finished Apr 25 02:32:06 PM PDT 24
Peak memory 204416 kb
Host smart-27e93dd1-21df-4202-a967-ee8763b39e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38823
70526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.3882370526
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.3933458405
Short name T1042
Test name
Test status
Simulation time 8377003194 ps
CPU time 8.44 seconds
Started Apr 25 02:31:18 PM PDT 24
Finished Apr 25 02:31:28 PM PDT 24
Peak memory 204120 kb
Host smart-48e81ad6-7b3d-46ce-acb9-a337c85542ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39334
58405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.3933458405
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.4164033121
Short name T1085
Test name
Test status
Simulation time 8394316501 ps
CPU time 8.31 seconds
Started Apr 25 02:31:29 PM PDT 24
Finished Apr 25 02:31:38 PM PDT 24
Peak memory 204120 kb
Host smart-863e8ed7-c88b-4b6d-a515-8cd9e900daee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41640
33121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.4164033121
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.3769449130
Short name T1371
Test name
Test status
Simulation time 8413670578 ps
CPU time 8.51 seconds
Started Apr 25 02:31:19 PM PDT 24
Finished Apr 25 02:31:29 PM PDT 24
Peak memory 204072 kb
Host smart-40511102-1a7c-4d67-9666-0e05920dcb46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37694
49130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.3769449130
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.3939488234
Short name T167
Test name
Test status
Simulation time 8393478813 ps
CPU time 8.47 seconds
Started Apr 25 02:31:18 PM PDT 24
Finished Apr 25 02:31:28 PM PDT 24
Peak memory 204040 kb
Host smart-648eed32-7540-489e-bda0-f52bab4ca5e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39394
88234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.3939488234
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.2661775733
Short name T318
Test name
Test status
Simulation time 8380810557 ps
CPU time 9.88 seconds
Started Apr 25 02:31:20 PM PDT 24
Finished Apr 25 02:31:31 PM PDT 24
Peak memory 204016 kb
Host smart-d034ee77-c90b-47fe-817c-2dd354447a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26617
75733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.2661775733
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.2085355720
Short name T161
Test name
Test status
Simulation time 8426196782 ps
CPU time 8.22 seconds
Started Apr 25 02:31:10 PM PDT 24
Finished Apr 25 02:31:19 PM PDT 24
Peak memory 204084 kb
Host smart-f72f6ede-ac96-401a-8034-a18c728a32de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20853
55720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2085355720
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.3700049819
Short name T362
Test name
Test status
Simulation time 8410529470 ps
CPU time 8.45 seconds
Started Apr 25 02:31:17 PM PDT 24
Finished Apr 25 02:31:27 PM PDT 24
Peak memory 204148 kb
Host smart-d77735c0-5ed9-4d4e-9bc5-7ddb0c82bb85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37000
49819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.3700049819
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.667719301
Short name T69
Test name
Test status
Simulation time 8403689104 ps
CPU time 7.65 seconds
Started Apr 25 02:31:19 PM PDT 24
Finished Apr 25 02:31:28 PM PDT 24
Peak memory 204148 kb
Host smart-34f7842a-fd50-4b3b-b433-78c43fcfb94a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66771
9301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.667719301
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.3254660892
Short name T761
Test name
Test status
Simulation time 8465791676 ps
CPU time 8.75 seconds
Started Apr 25 02:31:34 PM PDT 24
Finished Apr 25 02:31:45 PM PDT 24
Peak memory 204108 kb
Host smart-26f4be48-2cde-43ce-a777-523937c24346
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3254660892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.3254660892
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.124379693
Short name T565
Test name
Test status
Simulation time 8387325107 ps
CPU time 8.88 seconds
Started Apr 25 02:31:32 PM PDT 24
Finished Apr 25 02:31:41 PM PDT 24
Peak memory 204108 kb
Host smart-e22e1a55-be5f-4a3a-a9f9-c849ce051ffb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=124379693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.124379693
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.3874697068
Short name T412
Test name
Test status
Simulation time 8384753854 ps
CPU time 7.35 seconds
Started Apr 25 02:31:33 PM PDT 24
Finished Apr 25 02:31:42 PM PDT 24
Peak memory 204092 kb
Host smart-87338a05-0a05-4b38-a146-783245705403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38746
97068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.3874697068
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.2215236148
Short name T1132
Test name
Test status
Simulation time 8383185371 ps
CPU time 7.87 seconds
Started Apr 25 02:31:25 PM PDT 24
Finished Apr 25 02:31:34 PM PDT 24
Peak memory 204112 kb
Host smart-9e180b62-8da3-4017-9c39-9745f9572c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22152
36148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.2215236148
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_enable.1337275726
Short name T627
Test name
Test status
Simulation time 8376302191 ps
CPU time 8.97 seconds
Started Apr 25 02:31:27 PM PDT 24
Finished Apr 25 02:31:37 PM PDT 24
Peak memory 204092 kb
Host smart-5cacfcc9-5d60-4e24-a46e-721702d76d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13372
75726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.1337275726
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.3023825359
Short name T703
Test name
Test status
Simulation time 72997860 ps
CPU time 1.17 seconds
Started Apr 25 02:31:25 PM PDT 24
Finished Apr 25 02:31:27 PM PDT 24
Peak memory 204228 kb
Host smart-dcf88e4e-34bd-4885-bea5-cb3dcfd8bb68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30238
25359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3023825359
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.2282078295
Short name T560
Test name
Test status
Simulation time 8365342548 ps
CPU time 8.29 seconds
Started Apr 25 02:31:34 PM PDT 24
Finished Apr 25 02:31:44 PM PDT 24
Peak memory 204152 kb
Host smart-a1fcc10c-2489-4124-be4d-66c1f717aa88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22820
78295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.2282078295
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.3220165584
Short name T959
Test name
Test status
Simulation time 8447695108 ps
CPU time 8.44 seconds
Started Apr 25 02:31:26 PM PDT 24
Finished Apr 25 02:31:35 PM PDT 24
Peak memory 204116 kb
Host smart-b6df5088-1232-4a25-b9c3-0ddae1686290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32201
65584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.3220165584
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.3068014340
Short name T1099
Test name
Test status
Simulation time 8496979343 ps
CPU time 8.19 seconds
Started Apr 25 02:31:30 PM PDT 24
Finished Apr 25 02:31:39 PM PDT 24
Peak memory 204108 kb
Host smart-fde499f9-0a76-4445-a900-75059578c467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30680
14340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.3068014340
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2262207039
Short name T1164
Test name
Test status
Simulation time 8380123847 ps
CPU time 8.06 seconds
Started Apr 25 02:31:24 PM PDT 24
Finished Apr 25 02:31:34 PM PDT 24
Peak memory 204056 kb
Host smart-78d1d25a-31a1-4236-8a1b-b5a6ab930b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22622
07039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2262207039
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.3188641399
Short name T1049
Test name
Test status
Simulation time 8401275948 ps
CPU time 7.9 seconds
Started Apr 25 02:31:31 PM PDT 24
Finished Apr 25 02:31:40 PM PDT 24
Peak memory 204148 kb
Host smart-94a2e92c-42b5-4f48-82df-67d5b3cbc8d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31886
41399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.3188641399
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1597997236
Short name T832
Test name
Test status
Simulation time 8424988671 ps
CPU time 8.53 seconds
Started Apr 25 02:31:26 PM PDT 24
Finished Apr 25 02:31:35 PM PDT 24
Peak memory 204156 kb
Host smart-ec7d9a9e-add6-4844-adf5-0af9807e7f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15979
97236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1597997236
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.3144954460
Short name T173
Test name
Test status
Simulation time 8382821647 ps
CPU time 7.3 seconds
Started Apr 25 02:31:34 PM PDT 24
Finished Apr 25 02:31:43 PM PDT 24
Peak memory 204136 kb
Host smart-30231c2d-356c-4c28-8970-2c9f95630b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31449
54460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.3144954460
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.554579097
Short name T338
Test name
Test status
Simulation time 8378351297 ps
CPU time 7.98 seconds
Started Apr 25 02:31:25 PM PDT 24
Finished Apr 25 02:31:34 PM PDT 24
Peak memory 204080 kb
Host smart-85ae4823-7574-49c4-bb08-b8701477ab49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55457
9097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.554579097
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.3375596215
Short name T530
Test name
Test status
Simulation time 29735268 ps
CPU time 0.63 seconds
Started Apr 25 02:31:35 PM PDT 24
Finished Apr 25 02:31:37 PM PDT 24
Peak memory 204016 kb
Host smart-42ee820d-5444-455d-abca-71ace5cd871a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33755
96215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.3375596215
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.3468320710
Short name T90
Test name
Test status
Simulation time 26719626441 ps
CPU time 51.89 seconds
Started Apr 25 02:31:27 PM PDT 24
Finished Apr 25 02:32:20 PM PDT 24
Peak memory 204400 kb
Host smart-879a3ae8-adc6-4520-833f-c185cdf6c813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34683
20710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.3468320710
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.183489512
Short name T1171
Test name
Test status
Simulation time 8402082127 ps
CPU time 10.36 seconds
Started Apr 25 02:31:39 PM PDT 24
Finished Apr 25 02:31:50 PM PDT 24
Peak memory 204140 kb
Host smart-43b2b139-d751-49a8-950b-183d55e950b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18348
9512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.183489512
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.816586661
Short name T441
Test name
Test status
Simulation time 8436979241 ps
CPU time 7.57 seconds
Started Apr 25 02:31:29 PM PDT 24
Finished Apr 25 02:31:37 PM PDT 24
Peak memory 204112 kb
Host smart-bf468d68-60a6-4286-8a34-cdd6ae0c9241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81658
6661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.816586661
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.2715925462
Short name T496
Test name
Test status
Simulation time 8391217725 ps
CPU time 8.2 seconds
Started Apr 25 02:31:26 PM PDT 24
Finished Apr 25 02:31:36 PM PDT 24
Peak memory 204044 kb
Host smart-044c410f-e4a7-4f10-b985-b3124cbe5680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27159
25462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.2715925462
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1170416730
Short name T585
Test name
Test status
Simulation time 8403018981 ps
CPU time 7.64 seconds
Started Apr 25 02:31:26 PM PDT 24
Finished Apr 25 02:31:34 PM PDT 24
Peak memory 204140 kb
Host smart-fb1bc2c8-394e-461a-b0dd-aeba2b5890ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11704
16730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1170416730
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.969993519
Short name T1154
Test name
Test status
Simulation time 8378517803 ps
CPU time 8.35 seconds
Started Apr 25 02:31:27 PM PDT 24
Finished Apr 25 02:31:36 PM PDT 24
Peak memory 204044 kb
Host smart-4b0d22b2-6637-4e05-ad20-275d69e6c34d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96999
3519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.969993519
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.1566590165
Short name T646
Test name
Test status
Simulation time 8488093380 ps
CPU time 8.09 seconds
Started Apr 25 02:31:26 PM PDT 24
Finished Apr 25 02:31:36 PM PDT 24
Peak memory 204144 kb
Host smart-1a103f6f-94a8-4b59-a835-728cde3d0c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15665
90165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.1566590165
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.602861749
Short name T554
Test name
Test status
Simulation time 8405502783 ps
CPU time 8.95 seconds
Started Apr 25 02:31:25 PM PDT 24
Finished Apr 25 02:31:34 PM PDT 24
Peak memory 203416 kb
Host smart-48aa11c3-567e-42d6-9d18-330bd1101fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60286
1749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.602861749
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.221128231
Short name T701
Test name
Test status
Simulation time 8433173865 ps
CPU time 7.9 seconds
Started Apr 25 02:31:27 PM PDT 24
Finished Apr 25 02:31:36 PM PDT 24
Peak memory 204028 kb
Host smart-eea33f25-ba1f-440b-8f12-6b1e82f4d38d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22112
8231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.221128231
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.1870621777
Short name T1366
Test name
Test status
Simulation time 8477420563 ps
CPU time 9.01 seconds
Started Apr 25 02:31:42 PM PDT 24
Finished Apr 25 02:31:53 PM PDT 24
Peak memory 204132 kb
Host smart-812d9b79-f4cc-4fd4-8928-e44dbf57a956
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1870621777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.1870621777
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/12.min_length_in_transaction.232228627
Short name T944
Test name
Test status
Simulation time 8434115844 ps
CPU time 7.69 seconds
Started Apr 25 02:31:40 PM PDT 24
Finished Apr 25 02:31:49 PM PDT 24
Peak memory 204136 kb
Host smart-c2db9556-57e6-41a7-afc7-d8804f266229
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=232228627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.232228627
Directory /workspace/12.min_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.4060820369
Short name T398
Test name
Test status
Simulation time 8440742114 ps
CPU time 8.13 seconds
Started Apr 25 02:31:41 PM PDT 24
Finished Apr 25 02:31:51 PM PDT 24
Peak memory 204064 kb
Host smart-a4dabbf2-390f-4e25-ab11-185e23d6d908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40608
20369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.4060820369
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2861772155
Short name T421
Test name
Test status
Simulation time 8379687842 ps
CPU time 7.98 seconds
Started Apr 25 02:31:35 PM PDT 24
Finished Apr 25 02:31:45 PM PDT 24
Peak memory 204056 kb
Host smart-77750ea6-f54f-4ca4-854a-237a86beb7b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28617
72155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2861772155
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_enable.1926582430
Short name T1191
Test name
Test status
Simulation time 8428449558 ps
CPU time 7.42 seconds
Started Apr 25 02:31:35 PM PDT 24
Finished Apr 25 02:31:44 PM PDT 24
Peak memory 204144 kb
Host smart-047635f4-91a5-4ef5-b41a-ae9a79fb87be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19265
82430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.1926582430
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.681428874
Short name T1198
Test name
Test status
Simulation time 82829445 ps
CPU time 1.93 seconds
Started Apr 25 02:31:33 PM PDT 24
Finished Apr 25 02:31:36 PM PDT 24
Peak memory 204272 kb
Host smart-3f4b41e3-80b8-4247-ad23-6d1a186060bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68142
8874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.681428874
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.3710188717
Short name T1314
Test name
Test status
Simulation time 8402226108 ps
CPU time 9.08 seconds
Started Apr 25 02:31:59 PM PDT 24
Finished Apr 25 02:32:10 PM PDT 24
Peak memory 204144 kb
Host smart-20529a5a-4b0b-41b1-9ad6-e248e3269cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37101
88717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.3710188717
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.1234627837
Short name T467
Test name
Test status
Simulation time 8442030986 ps
CPU time 10.5 seconds
Started Apr 25 02:31:33 PM PDT 24
Finished Apr 25 02:31:45 PM PDT 24
Peak memory 204148 kb
Host smart-4e583550-39c4-432c-b01f-9e8193673d2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12346
27837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.1234627837
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.2876635013
Short name T1082
Test name
Test status
Simulation time 8502006916 ps
CPU time 7.68 seconds
Started Apr 25 02:31:33 PM PDT 24
Finished Apr 25 02:31:42 PM PDT 24
Peak memory 204136 kb
Host smart-55357b31-4c49-459f-9478-acce8e89c163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28766
35013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.2876635013
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.3016930438
Short name T20
Test name
Test status
Simulation time 8393027683 ps
CPU time 7.72 seconds
Started Apr 25 02:31:34 PM PDT 24
Finished Apr 25 02:31:44 PM PDT 24
Peak memory 204128 kb
Host smart-121266af-4b14-46ac-9809-58a3f9203d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30169
30438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.3016930438
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3006736238
Short name T106
Test name
Test status
Simulation time 8416412059 ps
CPU time 7.96 seconds
Started Apr 25 02:31:35 PM PDT 24
Finished Apr 25 02:31:44 PM PDT 24
Peak memory 204124 kb
Host smart-79e6b3eb-8153-4e68-b939-c59febc088c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30067
36238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3006736238
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.2768778140
Short name T1081
Test name
Test status
Simulation time 8407815454 ps
CPU time 7.67 seconds
Started Apr 25 02:31:34 PM PDT 24
Finished Apr 25 02:31:43 PM PDT 24
Peak memory 204128 kb
Host smart-dfb03104-65d1-4b5e-9bcc-606a7b9fc085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27687
78140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.2768778140
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.475086387
Short name T466
Test name
Test status
Simulation time 8421156618 ps
CPU time 7.89 seconds
Started Apr 25 02:31:33 PM PDT 24
Finished Apr 25 02:31:43 PM PDT 24
Peak memory 204100 kb
Host smart-94b3cfca-5f46-4250-b464-84faf4d39c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47508
6387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.475086387
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1952093556
Short name T166
Test name
Test status
Simulation time 8405768574 ps
CPU time 8.5 seconds
Started Apr 25 02:31:42 PM PDT 24
Finished Apr 25 02:31:52 PM PDT 24
Peak memory 204136 kb
Host smart-2191179b-2922-4385-8ea6-a9d8c60f16b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19520
93556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1952093556
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.2316340702
Short name T9
Test name
Test status
Simulation time 8364725571 ps
CPU time 7.93 seconds
Started Apr 25 02:31:42 PM PDT 24
Finished Apr 25 02:31:51 PM PDT 24
Peak memory 204100 kb
Host smart-5f7f3864-ad2d-4a5d-8a77-19828a585097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23163
40702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.2316340702
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.4043841350
Short name T34
Test name
Test status
Simulation time 38317300 ps
CPU time 0.65 seconds
Started Apr 25 02:31:41 PM PDT 24
Finished Apr 25 02:31:43 PM PDT 24
Peak memory 203928 kb
Host smart-1f9acf29-1c6d-476c-ae93-40f2a3c1fbdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40438
41350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.4043841350
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.3910731066
Short name T1286
Test name
Test status
Simulation time 29985596429 ps
CPU time 59.59 seconds
Started Apr 25 02:31:36 PM PDT 24
Finished Apr 25 02:32:36 PM PDT 24
Peak memory 204424 kb
Host smart-70b3cdf0-5866-46b1-8420-7359a17e39c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39107
31066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.3910731066
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.4050335564
Short name T320
Test name
Test status
Simulation time 8384599399 ps
CPU time 7.69 seconds
Started Apr 25 02:31:34 PM PDT 24
Finished Apr 25 02:31:44 PM PDT 24
Peak memory 204144 kb
Host smart-bda70c9c-7d4e-457c-a9bb-8ce2f4c81f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40503
35564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.4050335564
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2051244445
Short name T769
Test name
Test status
Simulation time 8460861967 ps
CPU time 7.6 seconds
Started Apr 25 02:31:36 PM PDT 24
Finished Apr 25 02:31:45 PM PDT 24
Peak memory 204124 kb
Host smart-b95ae49b-f116-46c8-b439-41f909a6d285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20512
44445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2051244445
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.1889137038
Short name T818
Test name
Test status
Simulation time 8385578219 ps
CPU time 7.56 seconds
Started Apr 25 02:31:34 PM PDT 24
Finished Apr 25 02:31:43 PM PDT 24
Peak memory 204100 kb
Host smart-1df58f1c-b3db-4241-b1d4-3ce8871306e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18891
37038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.1889137038
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.2544284592
Short name T993
Test name
Test status
Simulation time 8377060638 ps
CPU time 8.15 seconds
Started Apr 25 02:31:42 PM PDT 24
Finished Apr 25 02:31:51 PM PDT 24
Peak memory 204128 kb
Host smart-982a3a19-c40c-4f16-935d-fe4f1e09e740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25442
84592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.2544284592
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.599580177
Short name T950
Test name
Test status
Simulation time 8370547931 ps
CPU time 8.3 seconds
Started Apr 25 02:31:34 PM PDT 24
Finished Apr 25 02:31:44 PM PDT 24
Peak memory 204140 kb
Host smart-0ce79259-2651-437d-be8b-5d1c71a98000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59958
0177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.599580177
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.3972658538
Short name T356
Test name
Test status
Simulation time 8412029747 ps
CPU time 10.35 seconds
Started Apr 25 02:31:41 PM PDT 24
Finished Apr 25 02:31:52 PM PDT 24
Peak memory 204072 kb
Host smart-15af8611-b50f-4692-9220-37ad8b424040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39726
58538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.3972658538
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.3022889648
Short name T536
Test name
Test status
Simulation time 8387773774 ps
CPU time 9.89 seconds
Started Apr 25 02:31:33 PM PDT 24
Finished Apr 25 02:31:44 PM PDT 24
Peak memory 204124 kb
Host smart-a9d3a0dc-82d5-4423-a677-ce1130072049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30228
89648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.3022889648
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.2530859508
Short name T1063
Test name
Test status
Simulation time 8471319914 ps
CPU time 7.72 seconds
Started Apr 25 02:31:51 PM PDT 24
Finished Apr 25 02:32:00 PM PDT 24
Peak memory 204032 kb
Host smart-0406bfd4-29a6-4e90-821e-104230994187
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2530859508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.2530859508
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.494744353
Short name T1111
Test name
Test status
Simulation time 8375463787 ps
CPU time 9.37 seconds
Started Apr 25 02:31:50 PM PDT 24
Finished Apr 25 02:32:00 PM PDT 24
Peak memory 204144 kb
Host smart-7d3cece2-2028-4d1a-85fb-2649de0d2ff8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=494744353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.494744353
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.2915678614
Short name T709
Test name
Test status
Simulation time 8408228693 ps
CPU time 10.19 seconds
Started Apr 25 02:31:49 PM PDT 24
Finished Apr 25 02:32:01 PM PDT 24
Peak memory 204052 kb
Host smart-050ac1b2-35dd-4cf8-a9cf-410745e90241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29156
78614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.2915678614
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.2767274968
Short name T903
Test name
Test status
Simulation time 8393599335 ps
CPU time 7.32 seconds
Started Apr 25 02:31:41 PM PDT 24
Finished Apr 25 02:31:49 PM PDT 24
Peak memory 204072 kb
Host smart-1d312e81-1af0-4c8a-a2b9-c3df1bb41cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27672
74968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.2767274968
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_enable.2181885277
Short name T1010
Test name
Test status
Simulation time 8397399870 ps
CPU time 7.41 seconds
Started Apr 25 02:31:40 PM PDT 24
Finished Apr 25 02:31:48 PM PDT 24
Peak memory 204084 kb
Host smart-8d10d1db-bbc0-4b7c-acff-207554443710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21818
85277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.2181885277
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.2070822843
Short name T1124
Test name
Test status
Simulation time 54038984 ps
CPU time 0.99 seconds
Started Apr 25 02:31:41 PM PDT 24
Finished Apr 25 02:31:43 PM PDT 24
Peak memory 204196 kb
Host smart-2e3acbe0-4056-4b39-849d-fa10649ddac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20708
22843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.2070822843
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.3350695181
Short name T140
Test name
Test status
Simulation time 8395455402 ps
CPU time 8.66 seconds
Started Apr 25 02:31:48 PM PDT 24
Finished Apr 25 02:31:58 PM PDT 24
Peak memory 204156 kb
Host smart-c3cab7d6-52c8-42ea-8b19-13710fb265dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33506
95181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.3350695181
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.3219562459
Short name T1261
Test name
Test status
Simulation time 8403193848 ps
CPU time 8.34 seconds
Started Apr 25 02:31:56 PM PDT 24
Finished Apr 25 02:32:06 PM PDT 24
Peak memory 204052 kb
Host smart-ee966b96-4ef0-4815-8bf0-eed53109bc19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32195
62459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.3219562459
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3205170407
Short name T583
Test name
Test status
Simulation time 8423742799 ps
CPU time 8.21 seconds
Started Apr 25 02:31:41 PM PDT 24
Finished Apr 25 02:31:51 PM PDT 24
Peak memory 204156 kb
Host smart-b10ff201-06e4-4a01-82c7-db21318c9fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32051
70407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3205170407
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.2198009474
Short name T1069
Test name
Test status
Simulation time 8394359912 ps
CPU time 10.23 seconds
Started Apr 25 02:31:42 PM PDT 24
Finished Apr 25 02:31:54 PM PDT 24
Peak memory 204112 kb
Host smart-e599c16f-b0fc-43e1-b91d-7950c4e107f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21980
09474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.2198009474
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.3985612561
Short name T970
Test name
Test status
Simulation time 8411917106 ps
CPU time 7.43 seconds
Started Apr 25 02:31:50 PM PDT 24
Finished Apr 25 02:31:59 PM PDT 24
Peak memory 204032 kb
Host smart-501dbad9-5d31-423f-bf39-56b1d0960593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39856
12561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3985612561
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1111022031
Short name T1227
Test name
Test status
Simulation time 8395845318 ps
CPU time 8.56 seconds
Started Apr 25 02:31:48 PM PDT 24
Finished Apr 25 02:31:58 PM PDT 24
Peak memory 204116 kb
Host smart-481ed54b-c03b-46e0-8844-e524fbb98d95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11110
22031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1111022031
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.2519184211
Short name T754
Test name
Test status
Simulation time 8371048211 ps
CPU time 7.81 seconds
Started Apr 25 02:31:50 PM PDT 24
Finished Apr 25 02:31:59 PM PDT 24
Peak memory 204116 kb
Host smart-8f449613-3aba-4a9d-b49a-3e32004e15b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25191
84211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.2519184211
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.3464146210
Short name T1326
Test name
Test status
Simulation time 63057547 ps
CPU time 0.66 seconds
Started Apr 25 02:31:48 PM PDT 24
Finished Apr 25 02:31:49 PM PDT 24
Peak memory 203980 kb
Host smart-eefd93ec-9107-4fd6-929d-6c8301ae82a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34641
46210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.3464146210
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.3468274370
Short name T1345
Test name
Test status
Simulation time 26804941253 ps
CPU time 56.04 seconds
Started Apr 25 02:31:50 PM PDT 24
Finished Apr 25 02:32:47 PM PDT 24
Peak memory 204444 kb
Host smart-d0a170fd-6855-4cb2-ba99-9f39d6ef0963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34682
74370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.3468274370
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.4151776570
Short name T847
Test name
Test status
Simulation time 8411289121 ps
CPU time 9.41 seconds
Started Apr 25 02:31:49 PM PDT 24
Finished Apr 25 02:31:59 PM PDT 24
Peak memory 204104 kb
Host smart-a8abe815-021b-4062-9705-4f1e9ed5b1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41517
76570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.4151776570
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.2235857767
Short name T1016
Test name
Test status
Simulation time 8418003988 ps
CPU time 7.59 seconds
Started Apr 25 02:31:49 PM PDT 24
Finished Apr 25 02:31:57 PM PDT 24
Peak memory 204108 kb
Host smart-b6e55e9d-1ebc-4faa-b982-70f89d5d0da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22358
57767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.2235857767
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.3201223543
Short name T599
Test name
Test status
Simulation time 8412354472 ps
CPU time 7.62 seconds
Started Apr 25 02:31:58 PM PDT 24
Finished Apr 25 02:32:07 PM PDT 24
Peak memory 204144 kb
Host smart-1165f8b6-19f1-45c7-b996-437750b8ed6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32012
23543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.3201223543
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.961310526
Short name T720
Test name
Test status
Simulation time 8385180749 ps
CPU time 7.67 seconds
Started Apr 25 02:31:52 PM PDT 24
Finished Apr 25 02:32:01 PM PDT 24
Peak memory 204140 kb
Host smart-6e53e40d-7c49-4532-b940-8a8612b4b207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96131
0526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.961310526
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.3415037397
Short name T924
Test name
Test status
Simulation time 8369664971 ps
CPU time 8.15 seconds
Started Apr 25 02:31:51 PM PDT 24
Finished Apr 25 02:32:01 PM PDT 24
Peak memory 204144 kb
Host smart-95f64d91-10be-4884-bed1-cfb968580f3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34150
37397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.3415037397
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1820822719
Short name T1284
Test name
Test status
Simulation time 8393518940 ps
CPU time 8.14 seconds
Started Apr 25 02:31:48 PM PDT 24
Finished Apr 25 02:31:57 PM PDT 24
Peak memory 204104 kb
Host smart-34e3ad63-bfe3-4937-8bbb-c454935ed4b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18208
22719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1820822719
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.3209261950
Short name T612
Test name
Test status
Simulation time 8413317869 ps
CPU time 7.71 seconds
Started Apr 25 02:31:49 PM PDT 24
Finished Apr 25 02:31:58 PM PDT 24
Peak memory 204116 kb
Host smart-0cf5ee9e-3fcf-4c9e-9f42-713f5c1b38cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32092
61950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.3209261950
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.max_length_in_transaction.1117288686
Short name T1174
Test name
Test status
Simulation time 8466395619 ps
CPU time 7.83 seconds
Started Apr 25 02:32:03 PM PDT 24
Finished Apr 25 02:32:13 PM PDT 24
Peak memory 204132 kb
Host smart-ade28fa0-3a66-4e4f-a342-ccf7219f794c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1117288686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.1117288686
Directory /workspace/14.max_length_in_transaction/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.2972578831
Short name T979
Test name
Test status
Simulation time 8440827893 ps
CPU time 7.66 seconds
Started Apr 25 02:32:02 PM PDT 24
Finished Apr 25 02:32:12 PM PDT 24
Peak memory 204104 kb
Host smart-fdabce38-7688-459e-96f7-ad318cefbfca
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2972578831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.2972578831
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.2760196968
Short name T738
Test name
Test status
Simulation time 8383133636 ps
CPU time 10.68 seconds
Started Apr 25 02:32:07 PM PDT 24
Finished Apr 25 02:32:18 PM PDT 24
Peak memory 204124 kb
Host smart-43fee6c8-1314-40c0-8342-f58a1a59fc19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27601
96968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.2760196968
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.3670302104
Short name T590
Test name
Test status
Simulation time 8443842642 ps
CPU time 9.05 seconds
Started Apr 25 02:31:50 PM PDT 24
Finished Apr 25 02:32:00 PM PDT 24
Peak memory 204140 kb
Host smart-2d37dff5-e56f-45eb-a4c2-0bc1b2676642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36703
02104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3670302104
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_enable.2749772797
Short name T1077
Test name
Test status
Simulation time 8397912398 ps
CPU time 7.4 seconds
Started Apr 25 02:31:50 PM PDT 24
Finished Apr 25 02:31:59 PM PDT 24
Peak memory 204020 kb
Host smart-14842d46-a5b8-45f0-bb63-c1e9d3d6ff52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27497
72797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.2749772797
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.510940272
Short name T1079
Test name
Test status
Simulation time 56402898 ps
CPU time 1.68 seconds
Started Apr 25 02:31:56 PM PDT 24
Finished Apr 25 02:31:59 PM PDT 24
Peak memory 204232 kb
Host smart-7d8c2a29-cedb-4bd0-861f-affe6af25caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51094
0272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.510940272
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.1282736129
Short name T1113
Test name
Test status
Simulation time 8414739156 ps
CPU time 8.86 seconds
Started Apr 25 02:32:05 PM PDT 24
Finished Apr 25 02:32:15 PM PDT 24
Peak memory 204132 kb
Host smart-fea997ef-24ff-41f6-b888-366b3f1e8b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12827
36129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.1282736129
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.3842470243
Short name T657
Test name
Test status
Simulation time 8447372687 ps
CPU time 7.73 seconds
Started Apr 25 02:31:56 PM PDT 24
Finished Apr 25 02:32:04 PM PDT 24
Peak memory 204116 kb
Host smart-9fd240ab-de44-49f4-bc92-6d502599fc95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38424
70243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.3842470243
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.2573473289
Short name T88
Test name
Test status
Simulation time 8415669941 ps
CPU time 7.84 seconds
Started Apr 25 02:31:56 PM PDT 24
Finished Apr 25 02:32:05 PM PDT 24
Peak memory 204140 kb
Host smart-82939c43-d210-497a-a594-d3e95e42c240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25734
73289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.2573473289
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.4261410266
Short name T83
Test name
Test status
Simulation time 8384991867 ps
CPU time 8.11 seconds
Started Apr 25 02:31:55 PM PDT 24
Finished Apr 25 02:32:04 PM PDT 24
Peak memory 204128 kb
Host smart-95878eb3-7dce-43fa-b2bb-a31cc8faacb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42614
10266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.4261410266
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.1018418836
Short name T772
Test name
Test status
Simulation time 8450087895 ps
CPU time 7.41 seconds
Started Apr 25 02:31:55 PM PDT 24
Finished Apr 25 02:32:04 PM PDT 24
Peak memory 204044 kb
Host smart-b30853c9-e911-4a78-a2c8-a38fc94a212f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10184
18836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.1018418836
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1400900730
Short name T436
Test name
Test status
Simulation time 8395613252 ps
CPU time 8.06 seconds
Started Apr 25 02:32:15 PM PDT 24
Finished Apr 25 02:32:23 PM PDT 24
Peak memory 204156 kb
Host smart-a958ddea-c106-4c77-8a4c-a1e4c1a5cc3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14009
00730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1400900730
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.843740990
Short name T348
Test name
Test status
Simulation time 8409627839 ps
CPU time 10.35 seconds
Started Apr 25 02:31:55 PM PDT 24
Finished Apr 25 02:32:06 PM PDT 24
Peak memory 204080 kb
Host smart-ce3eb1f6-37ff-4978-b373-89c75c4a588e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84374
0990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.843740990
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.3138804133
Short name T877
Test name
Test status
Simulation time 8379584696 ps
CPU time 7.92 seconds
Started Apr 25 02:32:21 PM PDT 24
Finished Apr 25 02:32:30 PM PDT 24
Peak memory 204064 kb
Host smart-80db89ab-e87e-4ae3-a7f4-b4b40afd80d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31388
04133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.3138804133
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.659547286
Short name T693
Test name
Test status
Simulation time 8363633470 ps
CPU time 7.85 seconds
Started Apr 25 02:32:04 PM PDT 24
Finished Apr 25 02:32:13 PM PDT 24
Peak memory 204116 kb
Host smart-b03ace24-9b11-4614-91d7-fe1c996c79ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65954
7286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.659547286
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2152006516
Short name T1166
Test name
Test status
Simulation time 44051678 ps
CPU time 0.62 seconds
Started Apr 25 02:32:30 PM PDT 24
Finished Apr 25 02:32:32 PM PDT 24
Peak memory 204012 kb
Host smart-50a065cb-491d-415a-932b-6d6ba68b2c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21520
06516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2152006516
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.1584435912
Short name T1268
Test name
Test status
Simulation time 22784583500 ps
CPU time 46.16 seconds
Started Apr 25 02:32:03 PM PDT 24
Finished Apr 25 02:32:51 PM PDT 24
Peak memory 204364 kb
Host smart-bf9c13f0-87af-491a-8d17-41d70aea5238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15844
35912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.1584435912
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.2900614627
Short name T820
Test name
Test status
Simulation time 8409719032 ps
CPU time 8.71 seconds
Started Apr 25 02:32:01 PM PDT 24
Finished Apr 25 02:32:12 PM PDT 24
Peak memory 204120 kb
Host smart-d67a4fb4-3aef-4fa0-afa5-7e6be7a4af73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29006
14627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.2900614627
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.2412531122
Short name T712
Test name
Test status
Simulation time 8428132434 ps
CPU time 8.26 seconds
Started Apr 25 02:32:03 PM PDT 24
Finished Apr 25 02:32:13 PM PDT 24
Peak memory 204148 kb
Host smart-d772daf0-a73f-4ce5-9792-941bca1cf451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24125
31122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.2412531122
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.382647236
Short name T84
Test name
Test status
Simulation time 8395461720 ps
CPU time 7.43 seconds
Started Apr 25 02:32:03 PM PDT 24
Finished Apr 25 02:32:13 PM PDT 24
Peak memory 204088 kb
Host smart-de664ad5-193c-4978-b1f8-97f4ef6560ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38264
7236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.382647236
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.1028260163
Short name T1043
Test name
Test status
Simulation time 8381841304 ps
CPU time 8.37 seconds
Started Apr 25 02:32:02 PM PDT 24
Finished Apr 25 02:32:13 PM PDT 24
Peak memory 204140 kb
Host smart-e74488fe-847a-48d7-8333-d5a61694236e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10282
60163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.1028260163
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.3598837588
Short name T480
Test name
Test status
Simulation time 8382045373 ps
CPU time 7.82 seconds
Started Apr 25 02:32:04 PM PDT 24
Finished Apr 25 02:32:14 PM PDT 24
Peak memory 204116 kb
Host smart-33d10a1d-e004-415b-9751-517e4e036947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35988
37588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.3598837588
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2769628080
Short name T687
Test name
Test status
Simulation time 8422162848 ps
CPU time 8.35 seconds
Started Apr 25 02:32:05 PM PDT 24
Finished Apr 25 02:32:15 PM PDT 24
Peak memory 204128 kb
Host smart-87c3d8ca-c8d3-432a-aceb-e2074a43ec8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27696
28080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2769628080
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.2248073600
Short name T952
Test name
Test status
Simulation time 8410168710 ps
CPU time 7.48 seconds
Started Apr 25 02:32:06 PM PDT 24
Finished Apr 25 02:32:15 PM PDT 24
Peak memory 204148 kb
Host smart-d8e9f9d2-1124-4c57-8ef2-9776ea9dc40f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22480
73600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.2248073600
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.25126941
Short name T1130
Test name
Test status
Simulation time 8463770770 ps
CPU time 8.22 seconds
Started Apr 25 02:32:22 PM PDT 24
Finished Apr 25 02:32:31 PM PDT 24
Peak memory 204104 kb
Host smart-51896c3f-1cd3-4088-a02b-068c089cdc6a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=25126941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.25126941
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.1755724929
Short name T1149
Test name
Test status
Simulation time 8373403155 ps
CPU time 8.89 seconds
Started Apr 25 02:32:17 PM PDT 24
Finished Apr 25 02:32:27 PM PDT 24
Peak memory 204032 kb
Host smart-c26ff8ba-5495-4643-a9fa-8e1f4f11120b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1755724929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.1755724929
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.1699256863
Short name T643
Test name
Test status
Simulation time 8459603401 ps
CPU time 7.61 seconds
Started Apr 25 02:32:17 PM PDT 24
Finished Apr 25 02:32:26 PM PDT 24
Peak memory 204124 kb
Host smart-243a8691-cdcc-4fad-9aca-bbda3e79a34c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16992
56863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.1699256863
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.3096033844
Short name T1155
Test name
Test status
Simulation time 8469948849 ps
CPU time 8.69 seconds
Started Apr 25 02:32:09 PM PDT 24
Finished Apr 25 02:32:19 PM PDT 24
Peak memory 204056 kb
Host smart-b82ef236-b738-44f6-b6e7-b9f3454cd6d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30960
33844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.3096033844
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_enable.1996917404
Short name T229
Test name
Test status
Simulation time 8375581457 ps
CPU time 9.27 seconds
Started Apr 25 02:32:08 PM PDT 24
Finished Apr 25 02:32:19 PM PDT 24
Peak memory 204104 kb
Host smart-b48a776f-d73e-4f29-8316-e329e6a707b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19969
17404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.1996917404
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2444379781
Short name T354
Test name
Test status
Simulation time 43871908 ps
CPU time 1.24 seconds
Started Apr 25 02:32:12 PM PDT 24
Finished Apr 25 02:32:15 PM PDT 24
Peak memory 203752 kb
Host smart-2cfb38f8-c4f7-42b2-b9cc-84042a5a4e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24443
79781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2444379781
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.3342719398
Short name T1317
Test name
Test status
Simulation time 8435410993 ps
CPU time 8.04 seconds
Started Apr 25 02:32:17 PM PDT 24
Finished Apr 25 02:32:26 PM PDT 24
Peak memory 204112 kb
Host smart-e7bec980-0d91-4f7c-ad0f-18c58f9d3a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33427
19398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.3342719398
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.505754130
Short name T626
Test name
Test status
Simulation time 8369808247 ps
CPU time 8.79 seconds
Started Apr 25 02:32:18 PM PDT 24
Finished Apr 25 02:32:28 PM PDT 24
Peak memory 204144 kb
Host smart-dfce05ba-a3ef-4993-adaf-6be8026f5a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50575
4130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.505754130
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.2795769610
Short name T158
Test name
Test status
Simulation time 8395274798 ps
CPU time 10.14 seconds
Started Apr 25 02:32:09 PM PDT 24
Finished Apr 25 02:32:21 PM PDT 24
Peak memory 204068 kb
Host smart-97c369fc-30f2-4aa0-a2c9-8a1848070778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27957
69610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.2795769610
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.879467171
Short name T801
Test name
Test status
Simulation time 8425646617 ps
CPU time 8.27 seconds
Started Apr 25 02:32:12 PM PDT 24
Finished Apr 25 02:32:22 PM PDT 24
Peak memory 203908 kb
Host smart-8c3a8ab4-c19b-4059-a29a-b596021b0dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87946
7171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.879467171
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.2478374817
Short name T699
Test name
Test status
Simulation time 8377423532 ps
CPU time 7.73 seconds
Started Apr 25 02:32:09 PM PDT 24
Finished Apr 25 02:32:18 PM PDT 24
Peak memory 204132 kb
Host smart-850cc90f-94f7-4258-84f1-51dd581e1310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24783
74817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.2478374817
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1311724791
Short name T16
Test name
Test status
Simulation time 8400099161 ps
CPU time 7.71 seconds
Started Apr 25 02:32:12 PM PDT 24
Finished Apr 25 02:32:21 PM PDT 24
Peak memory 204120 kb
Host smart-b6626fd5-0d7c-4557-b563-d8e542f71daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13117
24791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1311724791
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.2751139728
Short name T1030
Test name
Test status
Simulation time 8412962619 ps
CPU time 8.51 seconds
Started Apr 25 02:32:10 PM PDT 24
Finished Apr 25 02:32:19 PM PDT 24
Peak memory 204108 kb
Host smart-b1ee1512-efce-4a57-9cf9-37eabcaf0d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27511
39728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.2751139728
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.1916509461
Short name T1226
Test name
Test status
Simulation time 8391369794 ps
CPU time 10.1 seconds
Started Apr 25 02:32:10 PM PDT 24
Finished Apr 25 02:32:21 PM PDT 24
Peak memory 204136 kb
Host smart-54acc92e-e816-49fc-a508-b96a3b9a8aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19165
09461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.1916509461
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.190553968
Short name T860
Test name
Test status
Simulation time 8366866124 ps
CPU time 9.2 seconds
Started Apr 25 02:32:08 PM PDT 24
Finished Apr 25 02:32:19 PM PDT 24
Peak memory 204128 kb
Host smart-93d6250f-4280-491f-893f-33d9d725198e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19055
3968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.190553968
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3492143045
Short name T796
Test name
Test status
Simulation time 73052276 ps
CPU time 0.67 seconds
Started Apr 25 02:32:12 PM PDT 24
Finished Apr 25 02:32:14 PM PDT 24
Peak memory 203512 kb
Host smart-3f1204db-bed8-4fe0-8921-a318b6ace9ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34921
43045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3492143045
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.3534951370
Short name T1310
Test name
Test status
Simulation time 26058222955 ps
CPU time 52.9 seconds
Started Apr 25 02:32:11 PM PDT 24
Finished Apr 25 02:33:05 PM PDT 24
Peak memory 204384 kb
Host smart-97fcf8e3-06a0-4334-bd77-e9a1a71b0423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35349
51370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.3534951370
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.2113541930
Short name T75
Test name
Test status
Simulation time 8403945107 ps
CPU time 7.86 seconds
Started Apr 25 02:32:08 PM PDT 24
Finished Apr 25 02:32:18 PM PDT 24
Peak memory 204008 kb
Host smart-4c127831-12c0-4fa9-859b-e1e435e2429e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21135
41930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2113541930
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3344626940
Short name T1169
Test name
Test status
Simulation time 8406282601 ps
CPU time 7.89 seconds
Started Apr 25 02:32:08 PM PDT 24
Finished Apr 25 02:32:18 PM PDT 24
Peak memory 204060 kb
Host smart-235bf2ab-3bb0-4eb7-a617-1d7a802d6f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33446
26940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3344626940
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.606416705
Short name T443
Test name
Test status
Simulation time 8391536041 ps
CPU time 9.43 seconds
Started Apr 25 02:32:12 PM PDT 24
Finished Apr 25 02:32:23 PM PDT 24
Peak memory 204048 kb
Host smart-6f83baed-c81a-4b02-a90a-05fb0bad60db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60641
6705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.606416705
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.3701266152
Short name T802
Test name
Test status
Simulation time 8371355332 ps
CPU time 10.17 seconds
Started Apr 25 02:32:12 PM PDT 24
Finished Apr 25 02:32:24 PM PDT 24
Peak memory 203972 kb
Host smart-40c92ca2-001e-4f4e-88ed-58461e465d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37012
66152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.3701266152
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.2198184620
Short name T674
Test name
Test status
Simulation time 8373031321 ps
CPU time 7.92 seconds
Started Apr 25 02:32:09 PM PDT 24
Finished Apr 25 02:32:19 PM PDT 24
Peak memory 204120 kb
Host smart-b296761c-a791-4f43-982d-a54065f4b7c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21981
84620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.2198184620
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.1372124017
Short name T868
Test name
Test status
Simulation time 8452827751 ps
CPU time 7.47 seconds
Started Apr 25 02:32:10 PM PDT 24
Finished Apr 25 02:32:19 PM PDT 24
Peak memory 204132 kb
Host smart-bcc9e67c-20b3-4c21-9b9c-d5b6e4b9884f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13721
24017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.1372124017
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.860812331
Short name T1362
Test name
Test status
Simulation time 8398336143 ps
CPU time 7.69 seconds
Started Apr 25 02:32:13 PM PDT 24
Finished Apr 25 02:32:22 PM PDT 24
Peak memory 204140 kb
Host smart-42f1b8cb-8268-4943-88fc-ede2ee395dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86081
2331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.860812331
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.2188548039
Short name T748
Test name
Test status
Simulation time 8396897074 ps
CPU time 9.6 seconds
Started Apr 25 02:32:09 PM PDT 24
Finished Apr 25 02:32:20 PM PDT 24
Peak memory 204124 kb
Host smart-3e2fb5f4-f029-46c1-96c0-990d751d4461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21885
48039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.2188548039
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.347897416
Short name T1012
Test name
Test status
Simulation time 8470454622 ps
CPU time 7.69 seconds
Started Apr 25 02:32:27 PM PDT 24
Finished Apr 25 02:32:35 PM PDT 24
Peak memory 204116 kb
Host smart-1c8744d2-f166-4f9b-8dec-2ee5a64a72c0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=347897416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.347897416
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.min_length_in_transaction.2936265155
Short name T1118
Test name
Test status
Simulation time 8380037101 ps
CPU time 8.57 seconds
Started Apr 25 02:32:22 PM PDT 24
Finished Apr 25 02:32:31 PM PDT 24
Peak memory 204108 kb
Host smart-08fa9d61-f4bb-4f9f-9f7b-1af43a904dbd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2936265155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.2936265155
Directory /workspace/16.min_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.455217081
Short name T613
Test name
Test status
Simulation time 8381998179 ps
CPU time 7.82 seconds
Started Apr 25 02:32:25 PM PDT 24
Finished Apr 25 02:32:34 PM PDT 24
Peak memory 203796 kb
Host smart-50b079d6-44e0-4f77-800c-a1508484833d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45521
7081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.455217081
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.1426291651
Short name T596
Test name
Test status
Simulation time 8381342578 ps
CPU time 7.65 seconds
Started Apr 25 02:32:17 PM PDT 24
Finished Apr 25 02:32:26 PM PDT 24
Peak memory 204148 kb
Host smart-fe8f9742-32de-46a2-ae83-a4300b20826d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14262
91651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.1426291651
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_enable.958983663
Short name T589
Test name
Test status
Simulation time 8373076444 ps
CPU time 7.36 seconds
Started Apr 25 02:32:16 PM PDT 24
Finished Apr 25 02:32:24 PM PDT 24
Peak memory 204092 kb
Host smart-5d79c6ef-fbfd-441c-b63b-70a6d5b9f34a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95898
3663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.958983663
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.4288546043
Short name T815
Test name
Test status
Simulation time 181095755 ps
CPU time 1.91 seconds
Started Apr 25 02:32:17 PM PDT 24
Finished Apr 25 02:32:20 PM PDT 24
Peak memory 204220 kb
Host smart-329e8a22-b5c2-4c1e-a802-2b10627dafd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42885
46043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.4288546043
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.4161973450
Short name T592
Test name
Test status
Simulation time 8467068812 ps
CPU time 8.1 seconds
Started Apr 25 02:32:24 PM PDT 24
Finished Apr 25 02:32:33 PM PDT 24
Peak memory 204096 kb
Host smart-5c82d788-3dad-43f6-9f12-ce7d014e97f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41619
73450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.4161973450
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.3040067404
Short name T1182
Test name
Test status
Simulation time 8452841649 ps
CPU time 7.81 seconds
Started Apr 25 02:32:16 PM PDT 24
Finished Apr 25 02:32:25 PM PDT 24
Peak memory 204040 kb
Host smart-03a4e02a-b86b-49ea-b54a-d888f7feb554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30400
67404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.3040067404
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.4244816577
Short name T92
Test name
Test status
Simulation time 8448173804 ps
CPU time 7.25 seconds
Started Apr 25 02:32:16 PM PDT 24
Finished Apr 25 02:32:24 PM PDT 24
Peak memory 204068 kb
Host smart-86e54eaa-b0d9-48ae-942f-cc0e253d9453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42448
16577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.4244816577
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.1726917613
Short name T625
Test name
Test status
Simulation time 8374316067 ps
CPU time 8.87 seconds
Started Apr 25 02:32:16 PM PDT 24
Finished Apr 25 02:32:25 PM PDT 24
Peak memory 204112 kb
Host smart-4ca207e6-1efa-4a48-9803-e8fe53eba013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17269
17613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1726917613
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.2249119175
Short name T131
Test name
Test status
Simulation time 8440670536 ps
CPU time 9.01 seconds
Started Apr 25 02:32:15 PM PDT 24
Finished Apr 25 02:32:25 PM PDT 24
Peak memory 204048 kb
Host smart-57c96bba-035a-4359-9fc4-eea353541d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22491
19175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.2249119175
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.1846412018
Short name T833
Test name
Test status
Simulation time 8397058281 ps
CPU time 7.47 seconds
Started Apr 25 02:32:23 PM PDT 24
Finished Apr 25 02:32:32 PM PDT 24
Peak memory 204116 kb
Host smart-5f4b76ea-d209-4d32-9928-95de6b5596d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18464
12018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.1846412018
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.4137690506
Short name T588
Test name
Test status
Simulation time 8428396433 ps
CPU time 8.27 seconds
Started Apr 25 02:32:24 PM PDT 24
Finished Apr 25 02:32:33 PM PDT 24
Peak memory 204140 kb
Host smart-88f1f275-32f8-4b8c-af60-d67db8a132a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41376
90506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.4137690506
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.2284028997
Short name T883
Test name
Test status
Simulation time 8398678985 ps
CPU time 8.61 seconds
Started Apr 25 02:32:25 PM PDT 24
Finished Apr 25 02:32:35 PM PDT 24
Peak memory 203888 kb
Host smart-84a2d212-7483-4153-a9e2-60cee4748353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22840
28997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.2284028997
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.2953714868
Short name T881
Test name
Test status
Simulation time 8382493107 ps
CPU time 7.46 seconds
Started Apr 25 02:32:24 PM PDT 24
Finished Apr 25 02:32:33 PM PDT 24
Peak memory 204104 kb
Host smart-6c8eae13-97da-4d76-8aa5-8d24448a1094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29537
14868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.2953714868
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.2076949149
Short name T973
Test name
Test status
Simulation time 45337677 ps
CPU time 0.64 seconds
Started Apr 25 02:32:23 PM PDT 24
Finished Apr 25 02:32:24 PM PDT 24
Peak memory 204012 kb
Host smart-91a10bfe-74e7-4eeb-aab6-dd1461bf9ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20769
49149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.2076949149
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.2303234427
Short name T1334
Test name
Test status
Simulation time 28326618192 ps
CPU time 58.02 seconds
Started Apr 25 02:32:25 PM PDT 24
Finished Apr 25 02:33:24 PM PDT 24
Peak memory 204432 kb
Host smart-64edb2d9-a523-4647-9a72-7b6362622bd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23032
34427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.2303234427
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.2213348921
Short name T1375
Test name
Test status
Simulation time 8378513252 ps
CPU time 8.22 seconds
Started Apr 25 02:32:28 PM PDT 24
Finished Apr 25 02:32:38 PM PDT 24
Peak memory 204108 kb
Host smart-69dbce9a-16e1-47cd-80e2-7ad4b925ca9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22133
48921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.2213348921
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.3840826259
Short name T1316
Test name
Test status
Simulation time 8444783500 ps
CPU time 7.72 seconds
Started Apr 25 02:32:23 PM PDT 24
Finished Apr 25 02:32:32 PM PDT 24
Peak memory 204016 kb
Host smart-177667f4-1cd7-49bb-b24b-b9b9d3e12852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38408
26259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.3840826259
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.360245944
Short name T1005
Test name
Test status
Simulation time 8421739385 ps
CPU time 8.01 seconds
Started Apr 25 02:32:24 PM PDT 24
Finished Apr 25 02:32:33 PM PDT 24
Peak memory 204028 kb
Host smart-1879880b-1113-4532-8415-ac9912654d66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36024
5944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.360245944
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3801535293
Short name T86
Test name
Test status
Simulation time 8373258380 ps
CPU time 8.06 seconds
Started Apr 25 02:32:23 PM PDT 24
Finished Apr 25 02:32:32 PM PDT 24
Peak memory 204080 kb
Host smart-1f78149a-6497-4501-9e8e-88bc28e80dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38015
35293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3801535293
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.192698066
Short name T749
Test name
Test status
Simulation time 8367349373 ps
CPU time 8.34 seconds
Started Apr 25 02:32:25 PM PDT 24
Finished Apr 25 02:32:34 PM PDT 24
Peak memory 204140 kb
Host smart-6ddd1952-d2c8-4670-afb2-01d4ba7b890f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19269
8066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.192698066
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.3696545432
Short name T1320
Test name
Test status
Simulation time 8447659818 ps
CPU time 10.51 seconds
Started Apr 25 02:32:15 PM PDT 24
Finished Apr 25 02:32:26 PM PDT 24
Peak memory 204112 kb
Host smart-75882aaf-c818-4787-b591-6a6ce963a2b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36965
45432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.3696545432
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2054229253
Short name T217
Test name
Test status
Simulation time 8395017830 ps
CPU time 9.51 seconds
Started Apr 25 02:32:25 PM PDT 24
Finished Apr 25 02:32:36 PM PDT 24
Peak memory 204124 kb
Host smart-0c51d7a5-ffe0-4455-85f9-530e69fbe0b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20542
29253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2054229253
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.4029788123
Short name T379
Test name
Test status
Simulation time 8393582207 ps
CPU time 9.07 seconds
Started Apr 25 02:32:21 PM PDT 24
Finished Apr 25 02:32:31 PM PDT 24
Peak memory 204128 kb
Host smart-d191d852-0a7c-4843-bd83-f32ea508eae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40297
88123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.4029788123
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.max_length_in_transaction.3168318096
Short name T782
Test name
Test status
Simulation time 8471270062 ps
CPU time 7.94 seconds
Started Apr 25 02:32:29 PM PDT 24
Finished Apr 25 02:32:38 PM PDT 24
Peak memory 204132 kb
Host smart-e91b5684-cfd9-43d9-bb5d-566824eb47a7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3168318096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.3168318096
Directory /workspace/17.max_length_in_transaction/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.2507265119
Short name T1032
Test name
Test status
Simulation time 8382028522 ps
CPU time 8.73 seconds
Started Apr 25 02:32:31 PM PDT 24
Finished Apr 25 02:32:41 PM PDT 24
Peak memory 204148 kb
Host smart-49cac85e-8cf5-4ceb-b403-724fc41ebce4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2507265119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.2507265119
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.3629373672
Short name T416
Test name
Test status
Simulation time 8460581158 ps
CPU time 7.81 seconds
Started Apr 25 02:32:28 PM PDT 24
Finished Apr 25 02:32:36 PM PDT 24
Peak memory 204116 kb
Host smart-713abd31-29fb-4ee7-99dd-26ec1fd2de8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36293
73672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.3629373672
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.3575943448
Short name T461
Test name
Test status
Simulation time 8376569735 ps
CPU time 7.57 seconds
Started Apr 25 02:32:25 PM PDT 24
Finished Apr 25 02:32:34 PM PDT 24
Peak memory 204152 kb
Host smart-e2ceb8aa-ad24-4d17-8ea2-9ff47c39d5a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35759
43448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3575943448
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_enable.2260444271
Short name T71
Test name
Test status
Simulation time 8371706963 ps
CPU time 8.01 seconds
Started Apr 25 02:32:24 PM PDT 24
Finished Apr 25 02:32:34 PM PDT 24
Peak memory 204144 kb
Host smart-6bcb9297-8ab3-41f0-b7fb-39a737049d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22604
44271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.2260444271
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.623788805
Short name T966
Test name
Test status
Simulation time 89523764 ps
CPU time 1.17 seconds
Started Apr 25 02:32:21 PM PDT 24
Finished Apr 25 02:32:23 PM PDT 24
Peak memory 204148 kb
Host smart-9513a0e9-3e8d-4506-a781-476d3b2872fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62378
8805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.623788805
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.3447000876
Short name T616
Test name
Test status
Simulation time 8453056161 ps
CPU time 8.65 seconds
Started Apr 25 02:32:28 PM PDT 24
Finished Apr 25 02:32:38 PM PDT 24
Peak memory 204144 kb
Host smart-6e85fb0a-7894-43bc-88e2-d6b4c0c5da0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34470
00876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.3447000876
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3066870760
Short name T385
Test name
Test status
Simulation time 8363043181 ps
CPU time 7.85 seconds
Started Apr 25 02:32:30 PM PDT 24
Finished Apr 25 02:32:39 PM PDT 24
Peak memory 204164 kb
Host smart-d7efef09-5ff7-4a2e-8a9f-256984140f95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30668
70760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3066870760
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.143273967
Short name T580
Test name
Test status
Simulation time 8386773270 ps
CPU time 7.58 seconds
Started Apr 25 02:32:26 PM PDT 24
Finished Apr 25 02:32:35 PM PDT 24
Peak memory 204108 kb
Host smart-be739805-9018-4fda-97aa-25c716ce502f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14327
3967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.143273967
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.3733147711
Short name T369
Test name
Test status
Simulation time 8434332665 ps
CPU time 8.03 seconds
Started Apr 25 02:32:25 PM PDT 24
Finished Apr 25 02:32:34 PM PDT 24
Peak memory 204140 kb
Host smart-b1a58609-1e82-4f63-82c2-7d6c8b106363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37331
47711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.3733147711
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.2654290206
Short name T1061
Test name
Test status
Simulation time 8391734518 ps
CPU time 7.56 seconds
Started Apr 25 02:32:24 PM PDT 24
Finished Apr 25 02:32:33 PM PDT 24
Peak memory 204140 kb
Host smart-8a1c0c24-1373-4a22-821d-2916875d056c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26542
90206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.2654290206
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.3711225219
Short name T1323
Test name
Test status
Simulation time 8409033557 ps
CPU time 10.27 seconds
Started Apr 25 02:32:23 PM PDT 24
Finished Apr 25 02:32:34 PM PDT 24
Peak memory 204056 kb
Host smart-78ba4937-176b-422b-9f0e-2f87e2fc92d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37112
25219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.3711225219
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.2574830500
Short name T938
Test name
Test status
Simulation time 8396973395 ps
CPU time 10.39 seconds
Started Apr 25 02:32:29 PM PDT 24
Finished Apr 25 02:32:41 PM PDT 24
Peak memory 204084 kb
Host smart-c123e6ba-d958-4613-97a5-331262f6d794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25748
30500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.2574830500
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.163357366
Short name T471
Test name
Test status
Simulation time 60363534 ps
CPU time 0.68 seconds
Started Apr 25 02:32:31 PM PDT 24
Finished Apr 25 02:32:33 PM PDT 24
Peak memory 203980 kb
Host smart-45f34cca-03f0-4110-9d40-f69eecbba54a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16335
7366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.163357366
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3197216413
Short name T1062
Test name
Test status
Simulation time 28551335937 ps
CPU time 65.57 seconds
Started Apr 25 02:32:29 PM PDT 24
Finished Apr 25 02:33:36 PM PDT 24
Peak memory 204328 kb
Host smart-2ed10ac9-c855-4e99-944f-dc2d14f43285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31972
16413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3197216413
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.1019592763
Short name T368
Test name
Test status
Simulation time 8425286994 ps
CPU time 7.57 seconds
Started Apr 25 02:32:31 PM PDT 24
Finished Apr 25 02:32:39 PM PDT 24
Peak memory 204132 kb
Host smart-aced93e4-bf12-4abc-9d8d-663e39586907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10195
92763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1019592763
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.712163228
Short name T750
Test name
Test status
Simulation time 8468854820 ps
CPU time 8.82 seconds
Started Apr 25 02:32:29 PM PDT 24
Finished Apr 25 02:32:39 PM PDT 24
Peak memory 204132 kb
Host smart-1f3062db-a9a8-4d2f-b117-67e56f49ab9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71216
3228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.712163228
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.2223664516
Short name T1009
Test name
Test status
Simulation time 8409545786 ps
CPU time 7.69 seconds
Started Apr 25 02:32:30 PM PDT 24
Finished Apr 25 02:32:39 PM PDT 24
Peak memory 204100 kb
Host smart-f52acaf6-9ac7-4f43-9cbc-92c8e0c3f81c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22236
64516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.2223664516
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.1647308230
Short name T187
Test name
Test status
Simulation time 8390959219 ps
CPU time 10.21 seconds
Started Apr 25 02:32:31 PM PDT 24
Finished Apr 25 02:32:42 PM PDT 24
Peak memory 204144 kb
Host smart-f7a8ddc3-f260-4e6e-ab3e-787dd2bfb2bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16473
08230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.1647308230
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.2664431737
Short name T1007
Test name
Test status
Simulation time 8370752355 ps
CPU time 7.71 seconds
Started Apr 25 02:32:28 PM PDT 24
Finished Apr 25 02:32:36 PM PDT 24
Peak memory 204068 kb
Host smart-d1a4c037-2be2-4ca7-a1c6-93c7acdb06a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26644
31737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2664431737
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.393321248
Short name T910
Test name
Test status
Simulation time 8421747689 ps
CPU time 8.09 seconds
Started Apr 25 02:32:24 PM PDT 24
Finished Apr 25 02:32:33 PM PDT 24
Peak memory 204064 kb
Host smart-5d2f187f-d4ab-4974-b60d-abf7e72a5a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39332
1248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.393321248
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.464073364
Short name T316
Test name
Test status
Simulation time 8400915746 ps
CPU time 7.71 seconds
Started Apr 25 02:32:30 PM PDT 24
Finished Apr 25 02:32:39 PM PDT 24
Peak memory 204044 kb
Host smart-d6280b71-3f73-42aa-968a-5c19d581e097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46407
3364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.464073364
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.1829140231
Short name T504
Test name
Test status
Simulation time 8372524078 ps
CPU time 8.72 seconds
Started Apr 25 02:32:28 PM PDT 24
Finished Apr 25 02:32:38 PM PDT 24
Peak memory 204088 kb
Host smart-2e7ebcba-20f1-4408-818c-02152f76e1a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18291
40231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.1829140231
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.3245600974
Short name T1281
Test name
Test status
Simulation time 8462878356 ps
CPU time 9.45 seconds
Started Apr 25 02:32:48 PM PDT 24
Finished Apr 25 02:32:58 PM PDT 24
Peak memory 204152 kb
Host smart-c9f6f69c-85e4-4b45-b731-79310bb8b13e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3245600974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.3245600974
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.2231298082
Short name T546
Test name
Test status
Simulation time 8387272039 ps
CPU time 8.63 seconds
Started Apr 25 02:32:39 PM PDT 24
Finished Apr 25 02:32:48 PM PDT 24
Peak memory 204132 kb
Host smart-d27c37ca-17ec-4519-80bd-fb20882b4e2f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2231298082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.2231298082
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.1317260201
Short name T1119
Test name
Test status
Simulation time 8453086184 ps
CPU time 7.81 seconds
Started Apr 25 02:32:41 PM PDT 24
Finished Apr 25 02:32:50 PM PDT 24
Peak memory 204136 kb
Host smart-0753e456-d7e4-4204-8205-544a5d440deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13172
60201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.1317260201
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2530570740
Short name T323
Test name
Test status
Simulation time 8381262879 ps
CPU time 7.53 seconds
Started Apr 25 02:32:31 PM PDT 24
Finished Apr 25 02:32:39 PM PDT 24
Peak memory 204116 kb
Host smart-8db09802-8097-4ddd-9075-f9ab1ea24095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25305
70740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2530570740
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_enable.2397077551
Short name T454
Test name
Test status
Simulation time 8378171125 ps
CPU time 9.83 seconds
Started Apr 25 02:32:28 PM PDT 24
Finished Apr 25 02:32:39 PM PDT 24
Peak memory 204096 kb
Host smart-62196f0b-67e7-430e-b66d-10407ec6f82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23970
77551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.2397077551
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.663925646
Short name T955
Test name
Test status
Simulation time 133413159 ps
CPU time 1.44 seconds
Started Apr 25 02:32:40 PM PDT 24
Finished Apr 25 02:32:42 PM PDT 24
Peak memory 204224 kb
Host smart-e5da7d30-5613-4d0c-b985-3fcecaab3d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66392
5646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.663925646
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.3686600850
Short name T1331
Test name
Test status
Simulation time 8412926693 ps
CPU time 8.06 seconds
Started Apr 25 02:32:41 PM PDT 24
Finished Apr 25 02:32:50 PM PDT 24
Peak memory 204160 kb
Host smart-fd90daa9-45d8-4ae5-91ea-6c1c6b867e17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36866
00850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.3686600850
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.2317338810
Short name T207
Test name
Test status
Simulation time 8385590419 ps
CPU time 7.38 seconds
Started Apr 25 02:32:46 PM PDT 24
Finished Apr 25 02:32:55 PM PDT 24
Peak memory 204152 kb
Host smart-9a860ce2-8928-46d4-b1de-af241927228a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23173
38810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.2317338810
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.2992198616
Short name T567
Test name
Test status
Simulation time 8496686930 ps
CPU time 9.4 seconds
Started Apr 25 02:32:40 PM PDT 24
Finished Apr 25 02:32:51 PM PDT 24
Peak memory 204112 kb
Host smart-b7740f19-b7b9-40b0-bf3b-d8c96cf1ac17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29921
98616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.2992198616
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.1577413583
Short name T711
Test name
Test status
Simulation time 8423129903 ps
CPU time 7.9 seconds
Started Apr 25 02:32:41 PM PDT 24
Finished Apr 25 02:32:50 PM PDT 24
Peak memory 204140 kb
Host smart-96e6d39d-2eac-4787-9bda-2fc8a888b531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15774
13583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1577413583
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.1102963988
Short name T922
Test name
Test status
Simulation time 8384645139 ps
CPU time 8.43 seconds
Started Apr 25 02:32:42 PM PDT 24
Finished Apr 25 02:32:51 PM PDT 24
Peak memory 204140 kb
Host smart-1b44e710-25a1-4ce6-9485-f84ef987d491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11029
63988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.1102963988
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.807777754
Short name T756
Test name
Test status
Simulation time 8421653761 ps
CPU time 9.04 seconds
Started Apr 25 02:32:43 PM PDT 24
Finished Apr 25 02:32:53 PM PDT 24
Peak memory 204116 kb
Host smart-351a9066-cc76-4256-b415-0cba78bc6480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80777
7754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.807777754
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1352503193
Short name T72
Test name
Test status
Simulation time 8418592485 ps
CPU time 7.69 seconds
Started Apr 25 02:32:41 PM PDT 24
Finished Apr 25 02:32:50 PM PDT 24
Peak memory 204140 kb
Host smart-b0d5ac3b-65cf-4fc3-96f9-e0a4c5c0f827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13525
03193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1352503193
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.2506093671
Short name T609
Test name
Test status
Simulation time 8405814099 ps
CPU time 9.32 seconds
Started Apr 25 02:32:40 PM PDT 24
Finished Apr 25 02:32:50 PM PDT 24
Peak memory 204156 kb
Host smart-d5529f40-3289-4bbc-bcb3-93a97b50a971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25060
93671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.2506093671
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.2748693388
Short name T1271
Test name
Test status
Simulation time 8395793511 ps
CPU time 8.17 seconds
Started Apr 25 02:32:41 PM PDT 24
Finished Apr 25 02:32:50 PM PDT 24
Peak memory 204108 kb
Host smart-3f07490e-e47c-4691-a4a1-11d87f06a55c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27486
93388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.2748693388
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3775993729
Short name T1146
Test name
Test status
Simulation time 8434809977 ps
CPU time 10.59 seconds
Started Apr 25 02:32:41 PM PDT 24
Finished Apr 25 02:32:53 PM PDT 24
Peak memory 204132 kb
Host smart-4cd9712b-a768-4d7a-88aa-dbb46dbbacfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37759
93729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3775993729
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.1477819700
Short name T1254
Test name
Test status
Simulation time 75076854 ps
CPU time 0.68 seconds
Started Apr 25 02:32:41 PM PDT 24
Finished Apr 25 02:32:43 PM PDT 24
Peak memory 203972 kb
Host smart-e7ec4e5e-06fe-45c3-9b24-cacd937d40c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14778
19700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.1477819700
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.3844779003
Short name T510
Test name
Test status
Simulation time 16308323968 ps
CPU time 28.48 seconds
Started Apr 25 02:32:41 PM PDT 24
Finished Apr 25 02:33:11 PM PDT 24
Peak memory 204424 kb
Host smart-6ed194ce-b72b-4e83-8f24-e9cdfa5ab593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38447
79003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.3844779003
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.1711191934
Short name T809
Test name
Test status
Simulation time 8405742763 ps
CPU time 9.32 seconds
Started Apr 25 02:32:39 PM PDT 24
Finished Apr 25 02:32:49 PM PDT 24
Peak memory 204108 kb
Host smart-46889d04-7ba5-4e71-b9d6-18c6af2a81e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17111
91934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.1711191934
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.665866322
Short name T1037
Test name
Test status
Simulation time 8443907007 ps
CPU time 10.18 seconds
Started Apr 25 02:32:39 PM PDT 24
Finished Apr 25 02:32:50 PM PDT 24
Peak memory 204116 kb
Host smart-725af6c2-44a4-4d33-9cd2-85f9fa1e14c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66586
6322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.665866322
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.4259218984
Short name T1270
Test name
Test status
Simulation time 8430876991 ps
CPU time 7.53 seconds
Started Apr 25 02:32:40 PM PDT 24
Finished Apr 25 02:32:48 PM PDT 24
Peak memory 204128 kb
Host smart-1c50ad90-6d3c-457f-b958-d44e74646e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42592
18984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.4259218984
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.537512341
Short name T615
Test name
Test status
Simulation time 8371320130 ps
CPU time 9.88 seconds
Started Apr 25 02:32:41 PM PDT 24
Finished Apr 25 02:32:52 PM PDT 24
Peak memory 204044 kb
Host smart-8c9fa10d-8651-4e4d-b5a1-03b3bc06de17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53751
2341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.537512341
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.3144016430
Short name T597
Test name
Test status
Simulation time 8369357340 ps
CPU time 7.56 seconds
Started Apr 25 02:32:38 PM PDT 24
Finished Apr 25 02:32:47 PM PDT 24
Peak memory 204124 kb
Host smart-539241bb-9402-426d-af33-453fe642aa24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31440
16430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.3144016430
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.1806732483
Short name T1112
Test name
Test status
Simulation time 8438911256 ps
CPU time 8.51 seconds
Started Apr 25 02:32:28 PM PDT 24
Finished Apr 25 02:32:38 PM PDT 24
Peak memory 204112 kb
Host smart-32e98b7f-45b4-49a2-a120-066ffeb055b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18067
32483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.1806732483
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.2509436347
Short name T623
Test name
Test status
Simulation time 8398536993 ps
CPU time 9.68 seconds
Started Apr 25 02:32:40 PM PDT 24
Finished Apr 25 02:32:51 PM PDT 24
Peak memory 204116 kb
Host smart-c19305b8-9d24-4c8f-a344-723916cc554b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25094
36347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.2509436347
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.1666639690
Short name T1084
Test name
Test status
Simulation time 8396255710 ps
CPU time 7.93 seconds
Started Apr 25 02:32:41 PM PDT 24
Finished Apr 25 02:32:50 PM PDT 24
Peak memory 204116 kb
Host smart-e332ba1f-c8f2-4715-854e-ed3209c8349e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16666
39690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.1666639690
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.3515780636
Short name T686
Test name
Test status
Simulation time 8462674436 ps
CPU time 8.53 seconds
Started Apr 25 02:32:54 PM PDT 24
Finished Apr 25 02:33:04 PM PDT 24
Peak memory 204056 kb
Host smart-7860aef1-ec52-4129-86c1-941d1583ff59
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3515780636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.3515780636
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.255575752
Short name T897
Test name
Test status
Simulation time 8374688002 ps
CPU time 8.1 seconds
Started Apr 25 02:32:51 PM PDT 24
Finished Apr 25 02:33:00 PM PDT 24
Peak memory 204128 kb
Host smart-2633ed0c-274b-4b6f-918a-9edf2184c45d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=255575752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.255575752
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.3322407101
Short name T425
Test name
Test status
Simulation time 8407598045 ps
CPU time 7.84 seconds
Started Apr 25 02:32:51 PM PDT 24
Finished Apr 25 02:33:00 PM PDT 24
Peak memory 204040 kb
Host smart-c1506785-3766-449d-a6cf-928241edcbe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33224
07101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.3322407101
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.785478789
Short name T509
Test name
Test status
Simulation time 8391826786 ps
CPU time 7.57 seconds
Started Apr 25 02:32:47 PM PDT 24
Finished Apr 25 02:32:56 PM PDT 24
Peak memory 204052 kb
Host smart-f5bbeb31-8d96-4a4a-b1cb-322fdbf291f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78547
8789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.785478789
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_enable.2788842128
Short name T1020
Test name
Test status
Simulation time 8412997327 ps
CPU time 7.95 seconds
Started Apr 25 02:32:46 PM PDT 24
Finished Apr 25 02:32:54 PM PDT 24
Peak memory 204080 kb
Host smart-b841c9f9-46f2-4568-897f-646f99f16708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27888
42128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.2788842128
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.427263354
Short name T353
Test name
Test status
Simulation time 198056269 ps
CPU time 2.04 seconds
Started Apr 25 02:32:49 PM PDT 24
Finished Apr 25 02:32:52 PM PDT 24
Peak memory 204180 kb
Host smart-ad9614e5-17bf-4dac-a13a-ffe1b5c14d9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42726
3354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.427263354
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.1320654948
Short name T460
Test name
Test status
Simulation time 8445769534 ps
CPU time 8 seconds
Started Apr 25 02:32:51 PM PDT 24
Finished Apr 25 02:33:00 PM PDT 24
Peak memory 204032 kb
Host smart-d8bd2c25-0bd1-4ced-94b6-fc2b30ce44ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13206
54948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.1320654948
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.1695768522
Short name T1329
Test name
Test status
Simulation time 8370746502 ps
CPU time 7.73 seconds
Started Apr 25 02:32:52 PM PDT 24
Finished Apr 25 02:33:01 PM PDT 24
Peak memory 204136 kb
Host smart-9249d401-0866-4660-b3f4-a2f82d9db904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16957
68522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.1695768522
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.2053912606
Short name T462
Test name
Test status
Simulation time 8434241454 ps
CPU time 7.83 seconds
Started Apr 25 02:32:45 PM PDT 24
Finished Apr 25 02:32:54 PM PDT 24
Peak memory 204120 kb
Host smart-d77f80e2-5ee1-4305-baac-2a0fdf10f119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20539
12606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.2053912606
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.2840484996
Short name T1242
Test name
Test status
Simulation time 8414467190 ps
CPU time 8.58 seconds
Started Apr 25 02:32:48 PM PDT 24
Finished Apr 25 02:32:57 PM PDT 24
Peak memory 204036 kb
Host smart-cd074f49-83ba-47dc-bc26-7fb09891b144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28404
84996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.2840484996
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3869425234
Short name T1272
Test name
Test status
Simulation time 8365826369 ps
CPU time 7.44 seconds
Started Apr 25 02:32:46 PM PDT 24
Finished Apr 25 02:32:54 PM PDT 24
Peak memory 204132 kb
Host smart-08e3b229-18db-46ee-935a-987e1a9affd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38694
25234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3869425234
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2331653506
Short name T101
Test name
Test status
Simulation time 8425759951 ps
CPU time 8.15 seconds
Started Apr 25 02:32:47 PM PDT 24
Finished Apr 25 02:32:56 PM PDT 24
Peak memory 204052 kb
Host smart-6f95d2d0-d40d-4c75-82a7-5c9e943dad2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23316
53506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2331653506
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.1689451745
Short name T491
Test name
Test status
Simulation time 8399794518 ps
CPU time 8.76 seconds
Started Apr 25 02:32:47 PM PDT 24
Finished Apr 25 02:32:57 PM PDT 24
Peak memory 204032 kb
Host smart-02c3a700-ce6e-41c4-8b3f-0716337f10c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16894
51745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.1689451745
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.374107110
Short name T29
Test name
Test status
Simulation time 8384977034 ps
CPU time 10.02 seconds
Started Apr 25 02:32:50 PM PDT 24
Finished Apr 25 02:33:01 PM PDT 24
Peak memory 204116 kb
Host smart-cfc964d8-efa6-409e-b82b-bc4b3dc197a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37410
7110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.374107110
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.1939282049
Short name T1041
Test name
Test status
Simulation time 8398009393 ps
CPU time 8.14 seconds
Started Apr 25 02:32:53 PM PDT 24
Finished Apr 25 02:33:03 PM PDT 24
Peak memory 204128 kb
Host smart-9cae42b3-e35b-45c1-849d-4be13a1fd0fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19392
82049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.1939282049
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.3136821697
Short name T1262
Test name
Test status
Simulation time 8429320940 ps
CPU time 8.44 seconds
Started Apr 25 02:32:53 PM PDT 24
Finished Apr 25 02:33:02 PM PDT 24
Peak memory 204092 kb
Host smart-134bb44e-7cb1-472b-90c7-09314731e170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31368
21697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.3136821697
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.3168310930
Short name T621
Test name
Test status
Simulation time 107231971 ps
CPU time 0.73 seconds
Started Apr 25 02:32:54 PM PDT 24
Finished Apr 25 02:32:56 PM PDT 24
Peak memory 204016 kb
Host smart-74c91843-c920-4cf2-8399-a3c7baa03605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31683
10930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.3168310930
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.1432640903
Short name T918
Test name
Test status
Simulation time 30751769379 ps
CPU time 71.11 seconds
Started Apr 25 02:32:46 PM PDT 24
Finished Apr 25 02:33:58 PM PDT 24
Peak memory 204416 kb
Host smart-5fc5d44a-c4b0-42b5-b0a5-79a066e1d03a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14326
40903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.1432640903
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.2773404761
Short name T542
Test name
Test status
Simulation time 8381695883 ps
CPU time 7.63 seconds
Started Apr 25 02:32:53 PM PDT 24
Finished Apr 25 02:33:02 PM PDT 24
Peak memory 204100 kb
Host smart-fa6b199d-1ca9-4fdb-bc7b-9643ad171934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27734
04761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.2773404761
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1548106212
Short name T1228
Test name
Test status
Simulation time 8435592198 ps
CPU time 7.79 seconds
Started Apr 25 02:32:53 PM PDT 24
Finished Apr 25 02:33:02 PM PDT 24
Peak memory 204092 kb
Host smart-19e23c74-a88c-40e1-9958-05f914411cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15481
06212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1548106212
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.832378590
Short name T779
Test name
Test status
Simulation time 8416307770 ps
CPU time 9.62 seconds
Started Apr 25 02:32:53 PM PDT 24
Finished Apr 25 02:33:04 PM PDT 24
Peak memory 204108 kb
Host smart-31f01f50-222a-42be-9006-bf1ae9b45583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83237
8590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.832378590
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.1449513144
Short name T1178
Test name
Test status
Simulation time 8388588245 ps
CPU time 8.95 seconds
Started Apr 25 02:32:52 PM PDT 24
Finished Apr 25 02:33:02 PM PDT 24
Peak memory 204096 kb
Host smart-bfbce695-c0f2-49d4-9b37-fb1e86c11566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14495
13144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.1449513144
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.2616807030
Short name T27
Test name
Test status
Simulation time 8372428440 ps
CPU time 7.37 seconds
Started Apr 25 02:32:55 PM PDT 24
Finished Apr 25 02:33:03 PM PDT 24
Peak memory 204140 kb
Host smart-a9529b94-e49f-4ea3-9bc9-a65e2f5b41c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26168
07030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.2616807030
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.4211951308
Short name T1015
Test name
Test status
Simulation time 8432235929 ps
CPU time 7.8 seconds
Started Apr 25 02:32:48 PM PDT 24
Finished Apr 25 02:32:57 PM PDT 24
Peak memory 204116 kb
Host smart-63ac6aca-6d75-4b8b-a896-c8cccd70ea55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42119
51308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.4211951308
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.3110921417
Short name T494
Test name
Test status
Simulation time 8384645087 ps
CPU time 8.15 seconds
Started Apr 25 02:32:52 PM PDT 24
Finished Apr 25 02:33:01 PM PDT 24
Peak memory 204148 kb
Host smart-929dac32-4e65-4770-92d5-409bfc886c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31109
21417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.3110921417
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3368635253
Short name T427
Test name
Test status
Simulation time 8409473787 ps
CPU time 7.97 seconds
Started Apr 25 02:32:54 PM PDT 24
Finished Apr 25 02:33:03 PM PDT 24
Peak memory 204044 kb
Host smart-a5ce64c0-5ece-4071-b2b3-87caeebd8197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33686
35253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3368635253
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.2284972899
Short name T915
Test name
Test status
Simulation time 8509723328 ps
CPU time 7.75 seconds
Started Apr 25 02:29:19 PM PDT 24
Finished Apr 25 02:29:28 PM PDT 24
Peak memory 204124 kb
Host smart-a2d38f99-41be-4e74-bb42-14b614bad9c9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2284972899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.2284972899
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.791622075
Short name T632
Test name
Test status
Simulation time 8379977234 ps
CPU time 8.84 seconds
Started Apr 25 02:29:19 PM PDT 24
Finished Apr 25 02:29:29 PM PDT 24
Peak memory 204104 kb
Host smart-bf1c8386-e70f-4ef0-817e-a7b7e07a279e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=791622075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.791622075
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.942057856
Short name T764
Test name
Test status
Simulation time 8419396013 ps
CPU time 7.45 seconds
Started Apr 25 02:29:15 PM PDT 24
Finished Apr 25 02:29:23 PM PDT 24
Peak memory 204184 kb
Host smart-027206e0-6149-4cea-bdac-24450cb9a419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94205
7856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.942057856
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.3857880064
Short name T690
Test name
Test status
Simulation time 8404852485 ps
CPU time 7.46 seconds
Started Apr 25 02:29:04 PM PDT 24
Finished Apr 25 02:29:13 PM PDT 24
Peak memory 204140 kb
Host smart-8ea24eda-5551-4b96-8c2a-1081ab7a636e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38578
80064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.3857880064
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_enable.2700171200
Short name T594
Test name
Test status
Simulation time 8415150255 ps
CPU time 9.69 seconds
Started Apr 25 02:29:02 PM PDT 24
Finished Apr 25 02:29:13 PM PDT 24
Peak memory 204144 kb
Host smart-f67e6096-a9e7-46ea-8a41-7dde841f3056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27001
71200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.2700171200
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.846712646
Short name T900
Test name
Test status
Simulation time 137014103 ps
CPU time 1.54 seconds
Started Apr 25 02:29:09 PM PDT 24
Finished Apr 25 02:29:12 PM PDT 24
Peak memory 204244 kb
Host smart-029f0f3f-d374-4390-9b93-1b1cf5853ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84671
2646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.846712646
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.3941099670
Short name T914
Test name
Test status
Simulation time 8387780235 ps
CPU time 7.65 seconds
Started Apr 25 02:29:19 PM PDT 24
Finished Apr 25 02:29:28 PM PDT 24
Peak memory 204104 kb
Host smart-c5e439b8-e281-42f1-9cb5-e66220219415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39410
99670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.3941099670
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.4271595581
Short name T1153
Test name
Test status
Simulation time 8369706924 ps
CPU time 8.51 seconds
Started Apr 25 02:29:19 PM PDT 24
Finished Apr 25 02:29:28 PM PDT 24
Peak memory 204104 kb
Host smart-25d31df8-df0d-49ff-8a6a-cff84e0b4e17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42715
95581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.4271595581
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.2132550489
Short name T464
Test name
Test status
Simulation time 8407493732 ps
CPU time 7.85 seconds
Started Apr 25 02:29:11 PM PDT 24
Finished Apr 25 02:29:21 PM PDT 24
Peak memory 203648 kb
Host smart-12eada9a-2221-4550-a58b-f76ea150b57e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21325
50489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.2132550489
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.584626490
Short name T819
Test name
Test status
Simulation time 8418210486 ps
CPU time 8.82 seconds
Started Apr 25 02:29:11 PM PDT 24
Finished Apr 25 02:29:21 PM PDT 24
Peak memory 204160 kb
Host smart-53390c73-246f-4cdb-ba86-514c801eab4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58462
6490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.584626490
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.2014036359
Short name T1161
Test name
Test status
Simulation time 8368969052 ps
CPU time 8.88 seconds
Started Apr 25 02:29:11 PM PDT 24
Finished Apr 25 02:29:22 PM PDT 24
Peak memory 203704 kb
Host smart-54310d85-4e47-4b8d-8c36-7edf135c74f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20140
36359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.2014036359
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.834786656
Short name T1122
Test name
Test status
Simulation time 8406981408 ps
CPU time 9.82 seconds
Started Apr 25 02:29:10 PM PDT 24
Finished Apr 25 02:29:21 PM PDT 24
Peak memory 204112 kb
Host smart-a79414c8-bfb6-4d59-a1f6-21db59e99d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83478
6656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.834786656
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1055021190
Short name T920
Test name
Test status
Simulation time 8377051278 ps
CPU time 9.15 seconds
Started Apr 25 02:29:10 PM PDT 24
Finished Apr 25 02:29:21 PM PDT 24
Peak memory 204140 kb
Host smart-d31ab1ca-99bf-4032-a363-66d5d35261c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10550
21190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1055021190
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.267616531
Short name T192
Test name
Test status
Simulation time 8372723684 ps
CPU time 7.63 seconds
Started Apr 25 02:29:16 PM PDT 24
Finished Apr 25 02:29:24 PM PDT 24
Peak memory 204124 kb
Host smart-dc77fedd-ae73-4838-a31a-9f52c00100fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26761
6531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.267616531
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.601227964
Short name T707
Test name
Test status
Simulation time 8383155678 ps
CPU time 7.86 seconds
Started Apr 25 02:29:18 PM PDT 24
Finished Apr 25 02:29:27 PM PDT 24
Peak memory 204100 kb
Host smart-340b20f0-8670-4e9b-971b-26f95aad63d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60122
7964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.601227964
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2975211236
Short name T36
Test name
Test status
Simulation time 36014299 ps
CPU time 0.66 seconds
Started Apr 25 02:29:16 PM PDT 24
Finished Apr 25 02:29:17 PM PDT 24
Peak memory 204008 kb
Host smart-a0430cbf-9df7-44e3-a53f-123202eb3338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29752
11236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2975211236
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.3303512433
Short name T1218
Test name
Test status
Simulation time 15393106923 ps
CPU time 26.11 seconds
Started Apr 25 02:29:10 PM PDT 24
Finished Apr 25 02:29:37 PM PDT 24
Peak memory 204312 kb
Host smart-3a767264-3ea2-4f9d-bb2f-d809a8aa5bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33035
12433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.3303512433
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.655248153
Short name T740
Test name
Test status
Simulation time 8379453277 ps
CPU time 8.53 seconds
Started Apr 25 02:29:10 PM PDT 24
Finished Apr 25 02:29:20 PM PDT 24
Peak memory 204148 kb
Host smart-2f8201ff-c0c3-4f38-946f-dfe8bcc5932e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65524
8153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.655248153
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.2812777218
Short name T1176
Test name
Test status
Simulation time 8491911897 ps
CPU time 8.66 seconds
Started Apr 25 02:29:11 PM PDT 24
Finished Apr 25 02:29:21 PM PDT 24
Peak memory 204024 kb
Host smart-678311dc-736b-4fdf-8aad-c8e777d65633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28127
77218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2812777218
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.1120312290
Short name T887
Test name
Test status
Simulation time 8409902976 ps
CPU time 7.99 seconds
Started Apr 25 02:29:15 PM PDT 24
Finished Apr 25 02:29:23 PM PDT 24
Peak memory 204120 kb
Host smart-8009ad35-9962-4994-9402-d889601a6b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11203
12290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.1120312290
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.1778227722
Short name T66
Test name
Test status
Simulation time 186472680 ps
CPU time 1.05 seconds
Started Apr 25 02:29:20 PM PDT 24
Finished Apr 25 02:29:22 PM PDT 24
Peak memory 220420 kb
Host smart-f9cd3fef-afd7-4a84-b58c-6312de9d4762
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1778227722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1778227722
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.2483603650
Short name T25
Test name
Test status
Simulation time 8400037953 ps
CPU time 8.86 seconds
Started Apr 25 02:29:16 PM PDT 24
Finished Apr 25 02:29:26 PM PDT 24
Peak memory 204120 kb
Host smart-ce5cfd8f-e27d-4c24-ab5f-0c1f5e873303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24836
03650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.2483603650
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3193094160
Short name T1129
Test name
Test status
Simulation time 8374874578 ps
CPU time 9.38 seconds
Started Apr 25 02:29:16 PM PDT 24
Finished Apr 25 02:29:26 PM PDT 24
Peak memory 204108 kb
Host smart-87d1a6bf-6e81-40d6-8ecb-4e30ece7386e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31930
94160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3193094160
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.1396124519
Short name T524
Test name
Test status
Simulation time 8438004490 ps
CPU time 9.67 seconds
Started Apr 25 02:29:02 PM PDT 24
Finished Apr 25 02:29:13 PM PDT 24
Peak memory 204120 kb
Host smart-fb8e8b9e-e08b-4443-84f3-ddc07b76a264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13961
24519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.1396124519
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.2888161239
Short name T1339
Test name
Test status
Simulation time 8384051185 ps
CPU time 7.74 seconds
Started Apr 25 02:29:18 PM PDT 24
Finished Apr 25 02:29:27 PM PDT 24
Peak memory 204116 kb
Host smart-0c417c6b-53cb-4537-b491-fe546fa714f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28881
61239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.2888161239
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.4138044207
Short name T1230
Test name
Test status
Simulation time 8425869668 ps
CPU time 8.1 seconds
Started Apr 25 02:29:19 PM PDT 24
Finished Apr 25 02:29:28 PM PDT 24
Peak memory 204116 kb
Host smart-ab959a53-a68e-44e6-9732-abb352d40c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41380
44207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.4138044207
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.3398892078
Short name T1369
Test name
Test status
Simulation time 8461657859 ps
CPU time 7.73 seconds
Started Apr 25 02:33:00 PM PDT 24
Finished Apr 25 02:33:09 PM PDT 24
Peak memory 204092 kb
Host smart-61be5819-c14f-446b-a0e1-876495ccc5f1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3398892078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.3398892078
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.1518510
Short name T783
Test name
Test status
Simulation time 8427145043 ps
CPU time 8.4 seconds
Started Apr 25 02:33:01 PM PDT 24
Finished Apr 25 02:33:11 PM PDT 24
Peak memory 204132 kb
Host smart-d9af7696-f788-4f81-a0e1-62b8b09a569f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1518510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.1518510
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.461343689
Short name T854
Test name
Test status
Simulation time 8448741964 ps
CPU time 7.79 seconds
Started Apr 25 02:32:59 PM PDT 24
Finished Apr 25 02:33:08 PM PDT 24
Peak memory 204136 kb
Host smart-5c9a5960-54dd-4a58-a175-5b09467feeaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46134
3689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.461343689
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3560222815
Short name T475
Test name
Test status
Simulation time 8384661623 ps
CPU time 8.14 seconds
Started Apr 25 02:32:52 PM PDT 24
Finished Apr 25 02:33:00 PM PDT 24
Peak memory 204124 kb
Host smart-febd9ab5-5805-4a69-84aa-468e795fc09c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35602
22815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3560222815
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_enable.4112007521
Short name T1346
Test name
Test status
Simulation time 8382292995 ps
CPU time 7.55 seconds
Started Apr 25 02:32:54 PM PDT 24
Finished Apr 25 02:33:03 PM PDT 24
Peak memory 204108 kb
Host smart-d493b4cb-5f43-4496-b602-367aa85e9102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41120
07521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.4112007521
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.228999421
Short name T1167
Test name
Test status
Simulation time 48077036 ps
CPU time 1.18 seconds
Started Apr 25 02:32:52 PM PDT 24
Finished Apr 25 02:32:54 PM PDT 24
Peak memory 204132 kb
Host smart-f8673cc2-d93d-4481-9cbe-12089fbb1142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22899
9421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.228999421
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.2727643242
Short name T73
Test name
Test status
Simulation time 8390856737 ps
CPU time 8.07 seconds
Started Apr 25 02:33:00 PM PDT 24
Finished Apr 25 02:33:10 PM PDT 24
Peak memory 204148 kb
Host smart-42a6e996-255b-419a-bcc3-8cdf7b22b7d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27276
43242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.2727643242
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.2495180864
Short name T1255
Test name
Test status
Simulation time 8402253645 ps
CPU time 8.36 seconds
Started Apr 25 02:33:01 PM PDT 24
Finished Apr 25 02:33:10 PM PDT 24
Peak memory 204016 kb
Host smart-c6b28eb8-8c13-4247-b4ef-b57059dbb82c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24951
80864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.2495180864
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.1966598805
Short name T1372
Test name
Test status
Simulation time 8426515787 ps
CPU time 7.48 seconds
Started Apr 25 02:32:54 PM PDT 24
Finished Apr 25 02:33:03 PM PDT 24
Peak memory 204116 kb
Host smart-d6295226-4434-42fe-942b-41aab8b02acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19665
98805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.1966598805
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.2257810312
Short name T791
Test name
Test status
Simulation time 8418678951 ps
CPU time 7.78 seconds
Started Apr 25 02:32:59 PM PDT 24
Finished Apr 25 02:33:08 PM PDT 24
Peak memory 204136 kb
Host smart-d07d3914-530b-4348-a7ac-dce796484798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22578
10312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.2257810312
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.2771923305
Short name T987
Test name
Test status
Simulation time 8369244158 ps
CPU time 7.78 seconds
Started Apr 25 02:32:59 PM PDT 24
Finished Apr 25 02:33:07 PM PDT 24
Peak memory 204116 kb
Host smart-b0569385-b621-4903-93a9-0a3b8ea9a630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27719
23305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.2771923305
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.3142683581
Short name T728
Test name
Test status
Simulation time 8437224093 ps
CPU time 8.76 seconds
Started Apr 25 02:32:59 PM PDT 24
Finished Apr 25 02:33:08 PM PDT 24
Peak memory 204092 kb
Host smart-635c0520-ad6e-449c-b149-a7c751e2210d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31426
83581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.3142683581
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.3995016715
Short name T1236
Test name
Test status
Simulation time 8370997991 ps
CPU time 7.91 seconds
Started Apr 25 02:32:58 PM PDT 24
Finished Apr 25 02:33:07 PM PDT 24
Peak memory 204128 kb
Host smart-3c91fc4c-2519-4801-b4fa-f1c48f0fbd39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39950
16715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.3995016715
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.1774263998
Short name T557
Test name
Test status
Simulation time 8405305930 ps
CPU time 8.61 seconds
Started Apr 25 02:33:00 PM PDT 24
Finished Apr 25 02:33:10 PM PDT 24
Peak memory 204108 kb
Host smart-c2cd763e-1b97-4b7e-b12f-fab2f9a43e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17742
63998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.1774263998
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.1971394991
Short name T628
Test name
Test status
Simulation time 8389192054 ps
CPU time 7.92 seconds
Started Apr 25 02:33:03 PM PDT 24
Finished Apr 25 02:33:11 PM PDT 24
Peak memory 204040 kb
Host smart-c185e57c-bebf-4b29-a486-6e4aeeeb55bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19713
94991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.1971394991
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.2771004091
Short name T515
Test name
Test status
Simulation time 8365869226 ps
CPU time 8.2 seconds
Started Apr 25 02:33:00 PM PDT 24
Finished Apr 25 02:33:09 PM PDT 24
Peak memory 204060 kb
Host smart-ddc0e417-9b04-459a-8996-00470d7d7d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27710
04091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.2771004091
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.2997162585
Short name T1157
Test name
Test status
Simulation time 178342244 ps
CPU time 0.77 seconds
Started Apr 25 02:33:01 PM PDT 24
Finished Apr 25 02:33:03 PM PDT 24
Peak memory 203988 kb
Host smart-4b53899f-7aa2-44fd-bf91-104c71f66337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29971
62585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.2997162585
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.2906626967
Short name T1259
Test name
Test status
Simulation time 23728856137 ps
CPU time 47.58 seconds
Started Apr 25 02:32:59 PM PDT 24
Finished Apr 25 02:33:48 PM PDT 24
Peak memory 204360 kb
Host smart-f79e2d1f-13bd-4fbb-8bbb-a23cdf7cfa8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29066
26967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.2906626967
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.2405618282
Short name T911
Test name
Test status
Simulation time 8409564984 ps
CPU time 8.82 seconds
Started Apr 25 02:32:59 PM PDT 24
Finished Apr 25 02:33:09 PM PDT 24
Peak memory 204068 kb
Host smart-39c3551e-830e-42e2-8142-97e6d2cbb138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24056
18282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.2405618282
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.4147805522
Short name T1097
Test name
Test status
Simulation time 8376575573 ps
CPU time 8.3 seconds
Started Apr 25 02:32:59 PM PDT 24
Finished Apr 25 02:33:08 PM PDT 24
Peak memory 204116 kb
Host smart-dec0407c-da2a-4df2-96cb-9adf41b07d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41478
05522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.4147805522
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.1603604081
Short name T473
Test name
Test status
Simulation time 8420088339 ps
CPU time 7.85 seconds
Started Apr 25 02:33:01 PM PDT 24
Finished Apr 25 02:33:10 PM PDT 24
Peak memory 204132 kb
Host smart-63d2ebbc-97b3-454d-bba4-499dc5f7c95e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16036
04081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.1603604081
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.3599518951
Short name T1183
Test name
Test status
Simulation time 8411149702 ps
CPU time 8.19 seconds
Started Apr 25 02:33:01 PM PDT 24
Finished Apr 25 02:33:10 PM PDT 24
Peak memory 204116 kb
Host smart-352f1f2f-dbf2-46fa-9fcc-8e5a1acbeef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35995
18951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.3599518951
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1346603203
Short name T225
Test name
Test status
Simulation time 8365059252 ps
CPU time 9.46 seconds
Started Apr 25 02:33:01 PM PDT 24
Finished Apr 25 02:33:12 PM PDT 24
Peak memory 204128 kb
Host smart-0428d6bd-e804-47a1-855c-bbce3b0ca0a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13466
03203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1346603203
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1075568577
Short name T1140
Test name
Test status
Simulation time 8434540974 ps
CPU time 7.62 seconds
Started Apr 25 02:32:54 PM PDT 24
Finished Apr 25 02:33:03 PM PDT 24
Peak memory 204048 kb
Host smart-076cddc0-94bc-405b-a94d-93cedfd753e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10755
68577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1075568577
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.2137796808
Short name T1222
Test name
Test status
Simulation time 8389113710 ps
CPU time 7.53 seconds
Started Apr 25 02:33:00 PM PDT 24
Finished Apr 25 02:33:09 PM PDT 24
Peak memory 204140 kb
Host smart-5e73045a-c99b-4cc5-9ff8-c67723df62b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21377
96808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.2137796808
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.33336407
Short name T825
Test name
Test status
Simulation time 8391422333 ps
CPU time 7.89 seconds
Started Apr 25 02:32:58 PM PDT 24
Finished Apr 25 02:33:07 PM PDT 24
Peak memory 204148 kb
Host smart-9db16256-f91e-40d3-aab5-33e673a9811e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33336
407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.33336407
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.117230707
Short name T917
Test name
Test status
Simulation time 8476539568 ps
CPU time 8.7 seconds
Started Apr 25 02:33:11 PM PDT 24
Finished Apr 25 02:33:22 PM PDT 24
Peak memory 204132 kb
Host smart-a89cb3a3-522c-4edf-a824-27ae9a04098a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=117230707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.117230707
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.1571453657
Short name T1384
Test name
Test status
Simulation time 8375211796 ps
CPU time 7.56 seconds
Started Apr 25 02:33:13 PM PDT 24
Finished Apr 25 02:33:22 PM PDT 24
Peak memory 204032 kb
Host smart-482beb37-332e-4a68-a38c-d552f8779d25
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1571453657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.1571453657
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.562643284
Short name T1027
Test name
Test status
Simulation time 8453930382 ps
CPU time 7.75 seconds
Started Apr 25 02:33:06 PM PDT 24
Finished Apr 25 02:33:15 PM PDT 24
Peak memory 204052 kb
Host smart-cd84846e-185a-408f-b102-63040b9d525d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56264
3284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.562643284
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.778088169
Short name T76
Test name
Test status
Simulation time 8380386635 ps
CPU time 8.14 seconds
Started Apr 25 02:33:02 PM PDT 24
Finished Apr 25 02:33:11 PM PDT 24
Peak memory 204152 kb
Host smart-33316a4d-e277-4c21-a9e5-e49bbfffd1e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77808
8169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.778088169
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_enable.3314072971
Short name T78
Test name
Test status
Simulation time 8384477751 ps
CPU time 8.11 seconds
Started Apr 25 02:33:00 PM PDT 24
Finished Apr 25 02:33:09 PM PDT 24
Peak memory 204072 kb
Host smart-57771daa-f55d-4677-b3a3-924fd683e55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33140
72971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.3314072971
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.347997819
Short name T255
Test name
Test status
Simulation time 180606251 ps
CPU time 1.62 seconds
Started Apr 25 02:33:02 PM PDT 24
Finished Apr 25 02:33:05 PM PDT 24
Peak memory 204244 kb
Host smart-b3201e30-abf5-4530-acce-ef88cd387f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34799
7819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.347997819
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.2899061550
Short name T870
Test name
Test status
Simulation time 8465554694 ps
CPU time 7.62 seconds
Started Apr 25 02:33:05 PM PDT 24
Finished Apr 25 02:33:13 PM PDT 24
Peak memory 204144 kb
Host smart-27dc8300-f2d5-4f14-aec2-01a0e51aace3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28990
61550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.2899061550
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.495729414
Short name T1364
Test name
Test status
Simulation time 8364275917 ps
CPU time 7.94 seconds
Started Apr 25 02:33:07 PM PDT 24
Finished Apr 25 02:33:16 PM PDT 24
Peak memory 204136 kb
Host smart-8fd26e5e-23b6-4228-8299-55f7baf8f3b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49572
9414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.495729414
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.3090046227
Short name T159
Test name
Test status
Simulation time 8395373755 ps
CPU time 8.81 seconds
Started Apr 25 02:33:02 PM PDT 24
Finished Apr 25 02:33:12 PM PDT 24
Peak memory 204116 kb
Host smart-70184540-7f10-45f3-b2b8-b9b255b4d1f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30900
46227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.3090046227
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.2245689357
Short name T1327
Test name
Test status
Simulation time 8412697890 ps
CPU time 7.98 seconds
Started Apr 25 02:33:06 PM PDT 24
Finished Apr 25 02:33:15 PM PDT 24
Peak memory 204124 kb
Host smart-da38e420-8dcb-4ac5-91dd-37d3ad67a595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22456
89357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.2245689357
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.802761645
Short name T812
Test name
Test status
Simulation time 8378042788 ps
CPU time 7.46 seconds
Started Apr 25 02:33:06 PM PDT 24
Finished Apr 25 02:33:15 PM PDT 24
Peak memory 204116 kb
Host smart-546356bd-7e3b-4709-b7c1-0a67f97c8d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80276
1645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.802761645
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.3150661243
Short name T923
Test name
Test status
Simulation time 8377736059 ps
CPU time 8.96 seconds
Started Apr 25 02:33:06 PM PDT 24
Finished Apr 25 02:33:16 PM PDT 24
Peak memory 204056 kb
Host smart-ea1cff07-e1f5-4211-9dae-c8214e626fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31506
61243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.3150661243
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.797619933
Short name T631
Test name
Test status
Simulation time 8387752625 ps
CPU time 9.76 seconds
Started Apr 25 02:33:08 PM PDT 24
Finished Apr 25 02:33:19 PM PDT 24
Peak memory 204020 kb
Host smart-90ac79ed-5553-4886-8dbf-adba6bdd4ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79761
9933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.797619933
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.2271530406
Short name T1194
Test name
Test status
Simulation time 8378088616 ps
CPU time 8.5 seconds
Started Apr 25 02:33:05 PM PDT 24
Finished Apr 25 02:33:15 PM PDT 24
Peak memory 204112 kb
Host smart-b32a4402-4769-424c-8388-74aa5bfe4c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22715
30406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.2271530406
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.1092140336
Short name T1263
Test name
Test status
Simulation time 8367739793 ps
CPU time 10.03 seconds
Started Apr 25 02:33:05 PM PDT 24
Finished Apr 25 02:33:16 PM PDT 24
Peak memory 204108 kb
Host smart-1d4702fe-3306-45d6-9073-77a59f78ff0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10921
40336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.1092140336
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.383817493
Short name T236
Test name
Test status
Simulation time 28412970381 ps
CPU time 51.03 seconds
Started Apr 25 02:33:03 PM PDT 24
Finished Apr 25 02:33:55 PM PDT 24
Peak memory 204472 kb
Host smart-0dce635e-30b5-42b1-875a-f1bc9b7652a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38381
7493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.383817493
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.38544089
Short name T374
Test name
Test status
Simulation time 8401864273 ps
CPU time 8.16 seconds
Started Apr 25 02:33:08 PM PDT 24
Finished Apr 25 02:33:17 PM PDT 24
Peak memory 204032 kb
Host smart-5f113b20-79d1-4574-8125-af64be0901cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38544
089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.38544089
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.1765441147
Short name T143
Test name
Test status
Simulation time 8489049404 ps
CPU time 8.3 seconds
Started Apr 25 02:33:04 PM PDT 24
Finished Apr 25 02:33:13 PM PDT 24
Peak memory 204076 kb
Host smart-2dfe6d4b-0cec-4032-a7ed-cff9d58340f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17654
41147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1765441147
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.1881538736
Short name T677
Test name
Test status
Simulation time 8388190940 ps
CPU time 8.11 seconds
Started Apr 25 02:33:07 PM PDT 24
Finished Apr 25 02:33:16 PM PDT 24
Peak memory 204116 kb
Host smart-9ecf8813-449a-40fa-9701-7fd17479c50b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18815
38736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.1881538736
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.1501505536
Short name T1004
Test name
Test status
Simulation time 8374073265 ps
CPU time 7.88 seconds
Started Apr 25 02:33:08 PM PDT 24
Finished Apr 25 02:33:17 PM PDT 24
Peak memory 204028 kb
Host smart-bdc99b92-cc68-4e60-bc04-289a6237a651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15015
05536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.1501505536
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.3014626333
Short name T1141
Test name
Test status
Simulation time 8373851219 ps
CPU time 8.09 seconds
Started Apr 25 02:33:07 PM PDT 24
Finished Apr 25 02:33:16 PM PDT 24
Peak memory 204100 kb
Host smart-41801039-94e5-43aa-8030-f01aa3e42898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30146
26333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.3014626333
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.351474930
Short name T1351
Test name
Test status
Simulation time 8445155813 ps
CPU time 8.26 seconds
Started Apr 25 02:33:01 PM PDT 24
Finished Apr 25 02:33:10 PM PDT 24
Peak memory 204044 kb
Host smart-2ba43958-ec3f-4db0-9cc9-19ed4c677f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35147
4930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.351474930
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.734053781
Short name T390
Test name
Test status
Simulation time 8470298104 ps
CPU time 7.88 seconds
Started Apr 25 02:33:07 PM PDT 24
Finished Apr 25 02:33:16 PM PDT 24
Peak memory 204100 kb
Host smart-06936ec2-595e-4b9c-9dd5-efc779252329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73405
3781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.734053781
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.8345250
Short name T1200
Test name
Test status
Simulation time 8421049539 ps
CPU time 8.15 seconds
Started Apr 25 02:33:06 PM PDT 24
Finished Apr 25 02:33:16 PM PDT 24
Peak memory 204144 kb
Host smart-861a5442-b566-4f54-afc9-9990e203ea61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83452
50 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.8345250
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.500181040
Short name T1193
Test name
Test status
Simulation time 8377591818 ps
CPU time 7.75 seconds
Started Apr 25 02:33:12 PM PDT 24
Finished Apr 25 02:33:21 PM PDT 24
Peak memory 204088 kb
Host smart-eaeee16c-360d-477c-ace0-d1e69d902531
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=500181040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.500181040
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.4226459685
Short name T964
Test name
Test status
Simulation time 8475723261 ps
CPU time 7.65 seconds
Started Apr 25 02:33:12 PM PDT 24
Finished Apr 25 02:33:21 PM PDT 24
Peak memory 204152 kb
Host smart-e88ac4bb-eeda-4e05-bcc7-d80b1ec83c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42264
59685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.4226459685
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.4176285366
Short name T328
Test name
Test status
Simulation time 8460350092 ps
CPU time 7.53 seconds
Started Apr 25 02:33:11 PM PDT 24
Finished Apr 25 02:33:20 PM PDT 24
Peak memory 204152 kb
Host smart-bbfc9bd1-198d-4b57-90fa-1ee0e400147b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41762
85366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.4176285366
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_enable.54306738
Short name T337
Test name
Test status
Simulation time 8390333701 ps
CPU time 8.84 seconds
Started Apr 25 02:33:15 PM PDT 24
Finished Apr 25 02:33:25 PM PDT 24
Peak memory 204144 kb
Host smart-5995c815-69f0-43ef-8e84-2de89a85502f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54306
738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.54306738
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.4269415606
Short name T907
Test name
Test status
Simulation time 228405561 ps
CPU time 1.85 seconds
Started Apr 25 02:33:14 PM PDT 24
Finished Apr 25 02:33:17 PM PDT 24
Peak memory 204188 kb
Host smart-144dc37f-7f5b-4d5b-9665-8771a588df3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42694
15606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.4269415606
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.2820081266
Short name T839
Test name
Test status
Simulation time 8405794316 ps
CPU time 8.85 seconds
Started Apr 25 02:33:11 PM PDT 24
Finished Apr 25 02:33:21 PM PDT 24
Peak memory 204096 kb
Host smart-9349626e-0dc8-44df-bb1e-52a07753bac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28200
81266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.2820081266
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.824948077
Short name T6
Test name
Test status
Simulation time 8370273928 ps
CPU time 7.67 seconds
Started Apr 25 02:33:10 PM PDT 24
Finished Apr 25 02:33:19 PM PDT 24
Peak memory 204112 kb
Host smart-119c8e22-b236-42d8-af81-5252043ab6c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82494
8077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.824948077
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.3038327079
Short name T153
Test name
Test status
Simulation time 8394338522 ps
CPU time 7.59 seconds
Started Apr 25 02:33:10 PM PDT 24
Finished Apr 25 02:33:19 PM PDT 24
Peak memory 204080 kb
Host smart-36ae8ba7-77c5-46b7-963f-841e2810a791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30383
27079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.3038327079
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.1873297123
Short name T411
Test name
Test status
Simulation time 8469034888 ps
CPU time 8.61 seconds
Started Apr 25 02:33:17 PM PDT 24
Finished Apr 25 02:33:27 PM PDT 24
Peak memory 204112 kb
Host smart-4ce99841-ff9f-4a13-84f1-fc643e2b8eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18732
97123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.1873297123
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3111127922
Short name T433
Test name
Test status
Simulation time 8368400385 ps
CPU time 8.29 seconds
Started Apr 25 02:33:15 PM PDT 24
Finished Apr 25 02:33:25 PM PDT 24
Peak memory 204140 kb
Host smart-6bbbd8b1-525e-4adf-b3a7-0f0e9c3bcd43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31111
27922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3111127922
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2645023763
Short name T726
Test name
Test status
Simulation time 8386725837 ps
CPU time 8.13 seconds
Started Apr 25 02:33:11 PM PDT 24
Finished Apr 25 02:33:21 PM PDT 24
Peak memory 204136 kb
Host smart-8b7fa053-e990-4e07-aac9-5d96607b3111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26450
23763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2645023763
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.3880951662
Short name T814
Test name
Test status
Simulation time 8410998507 ps
CPU time 7.95 seconds
Started Apr 25 02:33:12 PM PDT 24
Finished Apr 25 02:33:22 PM PDT 24
Peak memory 204112 kb
Host smart-961f32b3-15dd-44de-9bff-20fe78f23dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38809
51662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.3880951662
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1089012860
Short name T808
Test name
Test status
Simulation time 8416517507 ps
CPU time 8.57 seconds
Started Apr 25 02:33:13 PM PDT 24
Finished Apr 25 02:33:23 PM PDT 24
Peak memory 204136 kb
Host smart-863b02e7-90b4-443d-94a6-2d5b66f8ad55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10890
12860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1089012860
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.749866386
Short name T24
Test name
Test status
Simulation time 8374882149 ps
CPU time 8.05 seconds
Started Apr 25 02:33:11 PM PDT 24
Finished Apr 25 02:33:20 PM PDT 24
Peak memory 204068 kb
Host smart-6e3749b6-4174-4b26-a414-ce76ccbeeecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74986
6386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.749866386
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.1084418201
Short name T40
Test name
Test status
Simulation time 59976249 ps
CPU time 0.73 seconds
Started Apr 25 02:33:13 PM PDT 24
Finished Apr 25 02:33:15 PM PDT 24
Peak memory 204032 kb
Host smart-0d63fa14-93b4-42af-93ec-a57adb71bb20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10844
18201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.1084418201
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.1156880858
Short name T678
Test name
Test status
Simulation time 27570555814 ps
CPU time 50.84 seconds
Started Apr 25 02:33:12 PM PDT 24
Finished Apr 25 02:34:05 PM PDT 24
Peak memory 204360 kb
Host smart-d76a2a64-6ace-438a-9f3e-8bac2ba31ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11568
80858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.1156880858
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.2843505242
Short name T822
Test name
Test status
Simulation time 8393054506 ps
CPU time 8.58 seconds
Started Apr 25 02:33:16 PM PDT 24
Finished Apr 25 02:33:26 PM PDT 24
Peak memory 204108 kb
Host smart-66bcf203-dd53-4911-a4f6-2aaa9056eccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28435
05242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.2843505242
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.1887596386
Short name T999
Test name
Test status
Simulation time 8420518768 ps
CPU time 8.15 seconds
Started Apr 25 02:33:12 PM PDT 24
Finished Apr 25 02:33:22 PM PDT 24
Peak memory 204116 kb
Host smart-5d6ad926-4fed-4cbd-bc92-0bd59b047496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18875
96386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1887596386
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.1644099298
Short name T684
Test name
Test status
Simulation time 8407923232 ps
CPU time 9.21 seconds
Started Apr 25 02:33:12 PM PDT 24
Finished Apr 25 02:33:23 PM PDT 24
Peak memory 204060 kb
Host smart-aac3c892-aeeb-43d7-b339-92bbb679e9d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16440
99298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.1644099298
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.509528238
Short name T968
Test name
Test status
Simulation time 8383159079 ps
CPU time 7.52 seconds
Started Apr 25 02:33:12 PM PDT 24
Finished Apr 25 02:33:21 PM PDT 24
Peak memory 204148 kb
Host smart-671b6e32-d29e-4cd0-a84b-01131446c637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50952
8238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.509528238
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.2877452410
Short name T426
Test name
Test status
Simulation time 8370506728 ps
CPU time 10.38 seconds
Started Apr 25 02:33:11 PM PDT 24
Finished Apr 25 02:33:23 PM PDT 24
Peak memory 204024 kb
Host smart-aa514cef-33c5-481a-90c5-a45da5441131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28774
52410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.2877452410
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.2129385092
Short name T1233
Test name
Test status
Simulation time 8469860810 ps
CPU time 8.91 seconds
Started Apr 25 02:33:10 PM PDT 24
Finished Apr 25 02:33:20 PM PDT 24
Peak memory 204116 kb
Host smart-7fa3ecc6-8898-4d81-b515-c474f83eabb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21293
85092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.2129385092
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.4075122737
Short name T951
Test name
Test status
Simulation time 8413478360 ps
CPU time 7.63 seconds
Started Apr 25 02:33:12 PM PDT 24
Finished Apr 25 02:33:21 PM PDT 24
Peak memory 204140 kb
Host smart-5f5cfa36-2944-4804-8b9a-0a9b64dfc31d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40751
22737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.4075122737
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2200422531
Short name T539
Test name
Test status
Simulation time 8412778235 ps
CPU time 8.49 seconds
Started Apr 25 02:33:13 PM PDT 24
Finished Apr 25 02:33:23 PM PDT 24
Peak memory 204140 kb
Host smart-e6e021be-a96f-463c-84b1-7cdda07206c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22004
22531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2200422531
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.620424203
Short name T732
Test name
Test status
Simulation time 8470142857 ps
CPU time 7.69 seconds
Started Apr 25 02:33:25 PM PDT 24
Finished Apr 25 02:33:34 PM PDT 24
Peak memory 204148 kb
Host smart-9a9cd397-f6d3-434a-8d2d-05913eb43454
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=620424203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.620424203
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.3578504023
Short name T360
Test name
Test status
Simulation time 8378787158 ps
CPU time 7.59 seconds
Started Apr 25 02:33:25 PM PDT 24
Finished Apr 25 02:33:33 PM PDT 24
Peak memory 204128 kb
Host smart-cabccc29-94e9-40f0-b748-b6f51c6257b6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3578504023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.3578504023
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.1682077505
Short name T455
Test name
Test status
Simulation time 8460067924 ps
CPU time 8.15 seconds
Started Apr 25 02:33:31 PM PDT 24
Finished Apr 25 02:33:40 PM PDT 24
Peak memory 204140 kb
Host smart-2e513dd1-41bc-44f9-910d-b7737a27f655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16820
77505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.1682077505
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.1066064538
Short name T682
Test name
Test status
Simulation time 8383172950 ps
CPU time 8.04 seconds
Started Apr 25 02:33:20 PM PDT 24
Finished Apr 25 02:33:29 PM PDT 24
Peak memory 204076 kb
Host smart-7a6e1221-6aef-4094-8976-dc1511f23a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10660
64538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.1066064538
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_enable.2748836137
Short name T1246
Test name
Test status
Simulation time 8419640853 ps
CPU time 7.7 seconds
Started Apr 25 02:33:18 PM PDT 24
Finished Apr 25 02:33:27 PM PDT 24
Peak memory 204132 kb
Host smart-7a381ff7-8f56-487b-84cd-fd5e9fb37528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27488
36137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2748836137
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2041903783
Short name T313
Test name
Test status
Simulation time 57808652 ps
CPU time 1.31 seconds
Started Apr 25 02:33:33 PM PDT 24
Finished Apr 25 02:33:35 PM PDT 24
Peak memory 204276 kb
Host smart-65db9779-6fb8-4d20-a2d3-af92e39f4f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20419
03783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2041903783
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.3296653010
Short name T753
Test name
Test status
Simulation time 8450200137 ps
CPU time 8.52 seconds
Started Apr 25 02:33:30 PM PDT 24
Finished Apr 25 02:33:39 PM PDT 24
Peak memory 204144 kb
Host smart-31d5be89-8f70-414a-af31-85dec25643ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32966
53010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.3296653010
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.219616628
Short name T1066
Test name
Test status
Simulation time 8364734367 ps
CPU time 8.42 seconds
Started Apr 25 02:33:25 PM PDT 24
Finished Apr 25 02:33:35 PM PDT 24
Peak memory 204116 kb
Host smart-7f0beae2-a378-4d46-a8ff-882dfcbcb587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21961
6628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.219616628
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.175977950
Short name T660
Test name
Test status
Simulation time 8442679392 ps
CPU time 10.53 seconds
Started Apr 25 02:33:18 PM PDT 24
Finished Apr 25 02:33:30 PM PDT 24
Peak memory 204148 kb
Host smart-36d2f87a-2687-4fa3-a471-d7ebe51f2ab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17597
7950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.175977950
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.1943264978
Short name T803
Test name
Test status
Simulation time 8412570377 ps
CPU time 7.91 seconds
Started Apr 25 02:33:17 PM PDT 24
Finished Apr 25 02:33:26 PM PDT 24
Peak memory 204136 kb
Host smart-81f199c9-0481-427c-97a6-cf73a2f72510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19432
64978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.1943264978
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.1879430870
Short name T784
Test name
Test status
Simulation time 8390137663 ps
CPU time 7.39 seconds
Started Apr 25 02:33:22 PM PDT 24
Finished Apr 25 02:33:30 PM PDT 24
Peak memory 204144 kb
Host smart-74e3633e-1613-4876-aa5e-9a1e0f43bf95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18794
30870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.1879430870
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.2668752629
Short name T128
Test name
Test status
Simulation time 8409985982 ps
CPU time 8.52 seconds
Started Apr 25 02:33:18 PM PDT 24
Finished Apr 25 02:33:28 PM PDT 24
Peak memory 204088 kb
Host smart-2b193edd-ce06-422d-ad09-2658b9757983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26687
52629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2668752629
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2116179088
Short name T898
Test name
Test status
Simulation time 8439526434 ps
CPU time 8.25 seconds
Started Apr 25 02:33:20 PM PDT 24
Finished Apr 25 02:33:29 PM PDT 24
Peak memory 204140 kb
Host smart-a1778d63-d752-4ea6-a935-502ae7053b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21161
79088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2116179088
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.61972780
Short name T506
Test name
Test status
Simulation time 8438215415 ps
CPU time 7.67 seconds
Started Apr 25 02:33:17 PM PDT 24
Finished Apr 25 02:33:26 PM PDT 24
Peak memory 204156 kb
Host smart-b700cbee-e27e-4fd4-9138-51014723aa99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61972
780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.61972780
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.335973529
Short name T184
Test name
Test status
Simulation time 8401127693 ps
CPU time 7.78 seconds
Started Apr 25 02:33:25 PM PDT 24
Finished Apr 25 02:33:34 PM PDT 24
Peak memory 204132 kb
Host smart-47b5976e-30ad-43f7-ba3d-4eeb691b863f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33597
3529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.335973529
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.420111888
Short name T1123
Test name
Test status
Simulation time 8381522139 ps
CPU time 8.1 seconds
Started Apr 25 02:33:30 PM PDT 24
Finished Apr 25 02:33:39 PM PDT 24
Peak memory 203424 kb
Host smart-ca70e092-062f-4a32-ad5a-b9d8b311e382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42011
1888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.420111888
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2830379650
Short name T42
Test name
Test status
Simulation time 40104083 ps
CPU time 0.66 seconds
Started Apr 25 02:33:25 PM PDT 24
Finished Apr 25 02:33:27 PM PDT 24
Peak memory 204028 kb
Host smart-bce5207a-92b4-4557-b855-a705cd618070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28303
79650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2830379650
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.1759379208
Short name T89
Test name
Test status
Simulation time 30573735571 ps
CPU time 59.29 seconds
Started Apr 25 02:33:17 PM PDT 24
Finished Apr 25 02:34:17 PM PDT 24
Peak memory 204424 kb
Host smart-094fa871-19ff-4b69-806b-4e09540cdbfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17593
79208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.1759379208
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.1438486043
Short name T810
Test name
Test status
Simulation time 8396017441 ps
CPU time 7.86 seconds
Started Apr 25 02:33:21 PM PDT 24
Finished Apr 25 02:33:30 PM PDT 24
Peak memory 204108 kb
Host smart-ac74b23a-8367-45bb-bb8a-82abf33dd44e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14384
86043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.1438486043
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2347677448
Short name T948
Test name
Test status
Simulation time 8410206292 ps
CPU time 7.39 seconds
Started Apr 25 02:33:20 PM PDT 24
Finished Apr 25 02:33:28 PM PDT 24
Peak memory 204124 kb
Host smart-b365891a-e45f-45b6-a217-57082b161fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23476
77448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2347677448
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.2908578762
Short name T1275
Test name
Test status
Simulation time 8369911794 ps
CPU time 8.51 seconds
Started Apr 25 02:33:18 PM PDT 24
Finished Apr 25 02:33:27 PM PDT 24
Peak memory 204088 kb
Host smart-cdc3188a-10ac-4fe9-9419-1ccbc50f300e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29085
78762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.2908578762
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.178859362
Short name T727
Test name
Test status
Simulation time 8425097503 ps
CPU time 8.32 seconds
Started Apr 25 02:33:30 PM PDT 24
Finished Apr 25 02:33:39 PM PDT 24
Peak memory 203420 kb
Host smart-08387d86-8f22-4535-8245-69bb6d65b953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17885
9362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.178859362
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.3116928353
Short name T1108
Test name
Test status
Simulation time 8368683069 ps
CPU time 7.41 seconds
Started Apr 25 02:33:20 PM PDT 24
Finished Apr 25 02:33:28 PM PDT 24
Peak memory 204100 kb
Host smart-b0ae0a06-4e72-44f8-a464-aaa0284c3d9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31169
28353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.3116928353
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.243531834
Short name T176
Test name
Test status
Simulation time 8425981137 ps
CPU time 8.43 seconds
Started Apr 25 02:33:20 PM PDT 24
Finished Apr 25 02:33:30 PM PDT 24
Peak memory 204160 kb
Host smart-35d5c53d-b6a7-4495-b4b1-2a0108b51550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24353
1834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.243531834
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.2716149562
Short name T680
Test name
Test status
Simulation time 8373798954 ps
CPU time 7.91 seconds
Started Apr 25 02:33:20 PM PDT 24
Finished Apr 25 02:33:30 PM PDT 24
Peak memory 204140 kb
Host smart-ec272721-d5d4-4204-9782-34c8f9d4693b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27161
49562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.2716149562
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.922417335
Short name T1216
Test name
Test status
Simulation time 8432454769 ps
CPU time 8.73 seconds
Started Apr 25 02:33:18 PM PDT 24
Finished Apr 25 02:33:28 PM PDT 24
Peak memory 204116 kb
Host smart-ef350798-78ad-4a4e-9458-d7a166fe4f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92241
7335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.922417335
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.max_length_in_transaction.1103570964
Short name T1360
Test name
Test status
Simulation time 8464645519 ps
CPU time 9.4 seconds
Started Apr 25 02:33:34 PM PDT 24
Finished Apr 25 02:33:45 PM PDT 24
Peak memory 204152 kb
Host smart-d022da19-00f2-463d-b299-dd1fccf19b08
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1103570964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.1103570964
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.1838424967
Short name T778
Test name
Test status
Simulation time 8387007273 ps
CPU time 7.79 seconds
Started Apr 25 02:33:34 PM PDT 24
Finished Apr 25 02:33:43 PM PDT 24
Peak memory 204120 kb
Host smart-0d886c96-c1c3-4fbe-a630-49dc7dcaad46
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1838424967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.1838424967
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.3250216281
Short name T1017
Test name
Test status
Simulation time 8466801720 ps
CPU time 8.97 seconds
Started Apr 25 02:33:32 PM PDT 24
Finished Apr 25 02:33:43 PM PDT 24
Peak memory 204144 kb
Host smart-d1538574-26b5-43aa-8905-a6b012f58a38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32502
16281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.3250216281
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.1719609121
Short name T490
Test name
Test status
Simulation time 8375839473 ps
CPU time 8.27 seconds
Started Apr 25 02:33:27 PM PDT 24
Finished Apr 25 02:33:36 PM PDT 24
Peak memory 204124 kb
Host smart-bcaab57f-3684-4f90-ac32-2ac124333909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17196
09121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.1719609121
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_enable.2633320343
Short name T890
Test name
Test status
Simulation time 8381088580 ps
CPU time 8.08 seconds
Started Apr 25 02:33:24 PM PDT 24
Finished Apr 25 02:33:32 PM PDT 24
Peak memory 204108 kb
Host smart-17147515-11d3-497c-81a7-d0491f6081c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26333
20343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.2633320343
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.899825535
Short name T731
Test name
Test status
Simulation time 51529025 ps
CPU time 1.31 seconds
Started Apr 25 02:33:25 PM PDT 24
Finished Apr 25 02:33:27 PM PDT 24
Peak memory 204240 kb
Host smart-a8f385f2-82a6-4f83-bc4e-a204d117a09e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89982
5535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.899825535
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.2210533508
Short name T1031
Test name
Test status
Simulation time 8387671529 ps
CPU time 7.52 seconds
Started Apr 25 02:33:34 PM PDT 24
Finished Apr 25 02:33:43 PM PDT 24
Peak memory 204104 kb
Host smart-18bb5058-be9a-4a6f-9d8c-e13613b82478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22105
33508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.2210533508
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.4055595802
Short name T1353
Test name
Test status
Simulation time 8388129310 ps
CPU time 9.35 seconds
Started Apr 25 02:33:33 PM PDT 24
Finished Apr 25 02:33:44 PM PDT 24
Peak memory 204164 kb
Host smart-78f5040f-bd5b-4065-a57e-4b2a730860b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40555
95802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.4055595802
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.1767277760
Short name T607
Test name
Test status
Simulation time 8426162080 ps
CPU time 7.78 seconds
Started Apr 25 02:33:26 PM PDT 24
Finished Apr 25 02:33:35 PM PDT 24
Peak memory 204072 kb
Host smart-73a8e0f0-9857-46d4-98ea-031996074808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17672
77760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.1767277760
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.3952341558
Short name T1291
Test name
Test status
Simulation time 8414934250 ps
CPU time 9.25 seconds
Started Apr 25 02:33:24 PM PDT 24
Finished Apr 25 02:33:34 PM PDT 24
Peak memory 204108 kb
Host smart-b17b93b9-267f-488c-94a4-0443e6f91070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39523
41558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.3952341558
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3076175707
Short name T531
Test name
Test status
Simulation time 8375509717 ps
CPU time 8.58 seconds
Started Apr 25 02:33:30 PM PDT 24
Finished Apr 25 02:33:40 PM PDT 24
Peak memory 204140 kb
Host smart-8d3370d5-c062-4631-88e6-21256a0f03d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30761
75707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3076175707
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.1374588554
Short name T116
Test name
Test status
Simulation time 8432362712 ps
CPU time 7.97 seconds
Started Apr 25 02:33:30 PM PDT 24
Finished Apr 25 02:33:39 PM PDT 24
Peak memory 204148 kb
Host smart-eff3ae8b-9539-437d-a640-4665776a11a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13745
88554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.1374588554
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.698605776
Short name T629
Test name
Test status
Simulation time 8426734942 ps
CPU time 7.97 seconds
Started Apr 25 02:33:30 PM PDT 24
Finished Apr 25 02:33:39 PM PDT 24
Peak memory 203424 kb
Host smart-38df577f-6f92-48b2-bf1f-35f44d649e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69860
5776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.698605776
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.1874783699
Short name T1247
Test name
Test status
Simulation time 8386272224 ps
CPU time 9.17 seconds
Started Apr 25 02:33:26 PM PDT 24
Finished Apr 25 02:33:36 PM PDT 24
Peak memory 204156 kb
Host smart-f0d97aef-8171-4f19-bae5-916dbd86b09f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18747
83699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.1874783699
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.646929801
Short name T1110
Test name
Test status
Simulation time 8401857577 ps
CPU time 8.75 seconds
Started Apr 25 02:33:30 PM PDT 24
Finished Apr 25 02:33:39 PM PDT 24
Peak memory 204048 kb
Host smart-7bae5ef2-da6d-4407-adfe-0662cd7807bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64692
9801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.646929801
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.58463459
Short name T371
Test name
Test status
Simulation time 8365844951 ps
CPU time 8.06 seconds
Started Apr 25 02:33:32 PM PDT 24
Finished Apr 25 02:33:42 PM PDT 24
Peak memory 204088 kb
Host smart-ed21fd9e-7ce6-4b4f-a663-e7fad8623fe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58463
459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.58463459
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.2774316673
Short name T1047
Test name
Test status
Simulation time 38262332 ps
CPU time 0.65 seconds
Started Apr 25 02:33:32 PM PDT 24
Finished Apr 25 02:33:34 PM PDT 24
Peak memory 203916 kb
Host smart-bbf4f86a-ead7-4559-ba57-e1e66bcf5913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27743
16673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.2774316673
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.1373452957
Short name T1013
Test name
Test status
Simulation time 15721460862 ps
CPU time 27.65 seconds
Started Apr 25 02:33:33 PM PDT 24
Finished Apr 25 02:34:02 PM PDT 24
Peak memory 204404 kb
Host smart-81071c85-1a6c-4c45-977c-75b1708b9287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13734
52957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.1373452957
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.2692349713
Short name T386
Test name
Test status
Simulation time 8409530168 ps
CPU time 8.31 seconds
Started Apr 25 02:33:33 PM PDT 24
Finished Apr 25 02:33:42 PM PDT 24
Peak memory 204104 kb
Host smart-4377a7df-da95-471a-b0e0-c97f4ba9fbcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26923
49713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.2692349713
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.4008790872
Short name T835
Test name
Test status
Simulation time 8450430176 ps
CPU time 9.74 seconds
Started Apr 25 02:33:31 PM PDT 24
Finished Apr 25 02:33:42 PM PDT 24
Peak memory 204148 kb
Host smart-03f044f4-cf76-4254-8ab2-dc549af40288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40087
90872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.4008790872
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.1719008763
Short name T573
Test name
Test status
Simulation time 8402152465 ps
CPU time 9.38 seconds
Started Apr 25 02:33:33 PM PDT 24
Finished Apr 25 02:33:44 PM PDT 24
Peak memory 204140 kb
Host smart-6f739fe9-b54c-4ced-b873-68c89529a8ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17190
08763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.1719008763
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.3537032697
Short name T1162
Test name
Test status
Simulation time 8387385530 ps
CPU time 7.65 seconds
Started Apr 25 02:33:32 PM PDT 24
Finished Apr 25 02:33:40 PM PDT 24
Peak memory 204072 kb
Host smart-a4e735a7-406a-4a22-90c6-f809266a3824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35370
32697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.3537032697
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.1782264160
Short name T664
Test name
Test status
Simulation time 8369405779 ps
CPU time 7.89 seconds
Started Apr 25 02:33:34 PM PDT 24
Finished Apr 25 02:33:43 PM PDT 24
Peak memory 204140 kb
Host smart-5a0640d5-24d5-4fa1-8ab1-b135fadf24ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17822
64160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.1782264160
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.81741762
Short name T175
Test name
Test status
Simulation time 8442975794 ps
CPU time 7.53 seconds
Started Apr 25 02:33:31 PM PDT 24
Finished Apr 25 02:33:39 PM PDT 24
Peak memory 204148 kb
Host smart-706ea883-73d4-46c9-9a6b-b3f744ddafd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81741
762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.81741762
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.2867760378
Short name T983
Test name
Test status
Simulation time 8366777386 ps
CPU time 8.24 seconds
Started Apr 25 02:33:33 PM PDT 24
Finished Apr 25 02:33:43 PM PDT 24
Peak memory 204108 kb
Host smart-56700b63-6ac5-4c46-b0c7-58fb71f3cd0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28677
60378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.2867760378
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.277763404
Short name T1356
Test name
Test status
Simulation time 8400789696 ps
CPU time 9.22 seconds
Started Apr 25 02:33:31 PM PDT 24
Finished Apr 25 02:33:41 PM PDT 24
Peak memory 204132 kb
Host smart-458eff94-8fa0-480e-8a49-a2435d9ffd4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27776
3404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.277763404
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.max_length_in_transaction.3479386659
Short name T807
Test name
Test status
Simulation time 8467531648 ps
CPU time 8.73 seconds
Started Apr 25 02:33:44 PM PDT 24
Finished Apr 25 02:33:54 PM PDT 24
Peak memory 204128 kb
Host smart-39951274-5a82-4eea-97e8-d1126dc584a4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3479386659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.3479386659
Directory /workspace/25.max_length_in_transaction/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.2882769266
Short name T549
Test name
Test status
Simulation time 8384229174 ps
CPU time 8.72 seconds
Started Apr 25 02:33:40 PM PDT 24
Finished Apr 25 02:33:50 PM PDT 24
Peak memory 204132 kb
Host smart-8dd47caa-1322-4399-912b-ceee4627db1e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2882769266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.2882769266
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.1434419078
Short name T1095
Test name
Test status
Simulation time 8389276784 ps
CPU time 9.69 seconds
Started Apr 25 02:33:39 PM PDT 24
Finished Apr 25 02:33:51 PM PDT 24
Peak memory 204064 kb
Host smart-8c0efd2e-2110-4feb-89db-8015d3ca6c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14344
19078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.1434419078
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.4092427940
Short name T1022
Test name
Test status
Simulation time 8389306511 ps
CPU time 7.76 seconds
Started Apr 25 02:33:39 PM PDT 24
Finished Apr 25 02:33:49 PM PDT 24
Peak memory 204108 kb
Host smart-60ea63e2-5b91-49a1-95b0-ffbaccb861ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40924
27940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.4092427940
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_enable.3947362384
Short name T502
Test name
Test status
Simulation time 8439183992 ps
CPU time 8.18 seconds
Started Apr 25 02:33:40 PM PDT 24
Finished Apr 25 02:33:50 PM PDT 24
Peak memory 204120 kb
Host smart-07f494f8-be24-416b-8333-5f6d1185584f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39473
62384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3947362384
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1490263463
Short name T963
Test name
Test status
Simulation time 136105733 ps
CPU time 1.52 seconds
Started Apr 25 02:33:38 PM PDT 24
Finished Apr 25 02:33:40 PM PDT 24
Peak memory 204156 kb
Host smart-687c6c32-7914-40cf-a233-45c58ba215de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14902
63463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1490263463
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.1038588408
Short name T655
Test name
Test status
Simulation time 8442630588 ps
CPU time 7.99 seconds
Started Apr 25 02:33:42 PM PDT 24
Finished Apr 25 02:33:52 PM PDT 24
Peak memory 204136 kb
Host smart-be433da9-7ce1-45a2-94d9-9e6b7a1ebca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10385
88408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.1038588408
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.3859331780
Short name T989
Test name
Test status
Simulation time 8400891379 ps
CPU time 7.75 seconds
Started Apr 25 02:33:39 PM PDT 24
Finished Apr 25 02:33:48 PM PDT 24
Peak memory 204004 kb
Host smart-f3ed54ce-4889-4939-aee4-841c1ee7aecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38593
31780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.3859331780
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3074776666
Short name T136
Test name
Test status
Simulation time 8428774695 ps
CPU time 7.51 seconds
Started Apr 25 02:33:38 PM PDT 24
Finished Apr 25 02:33:46 PM PDT 24
Peak memory 204128 kb
Host smart-557519c6-d87e-4c35-b5c5-a48d88534e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30747
76666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3074776666
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.4089157263
Short name T901
Test name
Test status
Simulation time 8420311549 ps
CPU time 7.92 seconds
Started Apr 25 02:33:39 PM PDT 24
Finished Apr 25 02:33:49 PM PDT 24
Peak memory 204148 kb
Host smart-2ca0683a-659d-4d60-bc23-a61d509ffb9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40891
57263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.4089157263
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.2989711080
Short name T336
Test name
Test status
Simulation time 8367578551 ps
CPU time 8.39 seconds
Started Apr 25 02:33:41 PM PDT 24
Finished Apr 25 02:33:51 PM PDT 24
Peak memory 204124 kb
Host smart-4e0f6a7f-343e-48ef-b1f1-66736de7ee7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29897
11080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.2989711080
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1889756039
Short name T99
Test name
Test status
Simulation time 8407823264 ps
CPU time 7.53 seconds
Started Apr 25 02:33:41 PM PDT 24
Finished Apr 25 02:33:50 PM PDT 24
Peak memory 204124 kb
Host smart-ecfe1a0a-1427-4fb7-b8f1-6e8045f0ec50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18897
56039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1889756039
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.4108381825
Short name T1319
Test name
Test status
Simulation time 8377188877 ps
CPU time 7.53 seconds
Started Apr 25 02:33:39 PM PDT 24
Finished Apr 25 02:33:48 PM PDT 24
Peak memory 204108 kb
Host smart-7866c969-0e23-40fe-8767-9200ea1ff502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41083
81825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.4108381825
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3029521787
Short name T969
Test name
Test status
Simulation time 8416300992 ps
CPU time 7.8 seconds
Started Apr 25 02:33:39 PM PDT 24
Finished Apr 25 02:33:49 PM PDT 24
Peak memory 204128 kb
Host smart-c7f01763-0368-4df6-bf85-57b69da6e8be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30295
21787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3029521787
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.1883076404
Short name T188
Test name
Test status
Simulation time 8409754531 ps
CPU time 7.73 seconds
Started Apr 25 02:33:41 PM PDT 24
Finished Apr 25 02:33:51 PM PDT 24
Peak memory 204016 kb
Host smart-1f26b0da-655f-4485-8c5b-4ccc26cab41d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18830
76404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.1883076404
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.3371163773
Short name T851
Test name
Test status
Simulation time 8424794039 ps
CPU time 8.81 seconds
Started Apr 25 02:33:39 PM PDT 24
Finished Apr 25 02:33:50 PM PDT 24
Peak memory 204132 kb
Host smart-bc9849bb-a248-4fe0-b2e2-5ce93b87e405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33711
63773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.3371163773
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.1131960492
Short name T733
Test name
Test status
Simulation time 41111533 ps
CPU time 0.66 seconds
Started Apr 25 02:33:53 PM PDT 24
Finished Apr 25 02:33:55 PM PDT 24
Peak memory 203984 kb
Host smart-7bbcbab7-f169-4127-a5c1-32e6f5b2f74b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11319
60492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.1131960492
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.1676700513
Short name T258
Test name
Test status
Simulation time 25540219814 ps
CPU time 47.67 seconds
Started Apr 25 02:33:40 PM PDT 24
Finished Apr 25 02:34:30 PM PDT 24
Peak memory 204408 kb
Host smart-37fae090-a8ba-4808-ba4c-8fc495eca473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16767
00513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.1676700513
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.1284730687
Short name T792
Test name
Test status
Simulation time 8388321446 ps
CPU time 8.16 seconds
Started Apr 25 02:33:38 PM PDT 24
Finished Apr 25 02:33:47 PM PDT 24
Peak memory 204120 kb
Host smart-f5edd5cf-9353-4c64-bdd1-8e3d544f9f0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12847
30687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.1284730687
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.741983218
Short name T620
Test name
Test status
Simulation time 8465912279 ps
CPU time 8.45 seconds
Started Apr 25 02:33:42 PM PDT 24
Finished Apr 25 02:33:52 PM PDT 24
Peak memory 204136 kb
Host smart-68a845a9-e224-4eac-b2c8-21eabdff5777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74198
3218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.741983218
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.744062647
Short name T505
Test name
Test status
Simulation time 8395058216 ps
CPU time 9.9 seconds
Started Apr 25 02:33:41 PM PDT 24
Finished Apr 25 02:33:53 PM PDT 24
Peak memory 204144 kb
Host smart-93fc518d-8f33-4eb9-a0db-3a1beb31c90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74406
2647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.744062647
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.3043651450
Short name T978
Test name
Test status
Simulation time 8370246494 ps
CPU time 7.21 seconds
Started Apr 25 02:33:41 PM PDT 24
Finished Apr 25 02:33:50 PM PDT 24
Peak memory 204116 kb
Host smart-3201333f-7d9a-4b3a-80ae-b292c7bc20a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30436
51450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.3043651450
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.638085142
Short name T1048
Test name
Test status
Simulation time 8378600349 ps
CPU time 8.21 seconds
Started Apr 25 02:33:39 PM PDT 24
Finished Apr 25 02:33:48 PM PDT 24
Peak memory 204140 kb
Host smart-5d3a4898-d7ad-49c3-b56e-1cbd22dd4314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63808
5142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.638085142
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.167944737
Short name T1128
Test name
Test status
Simulation time 8408514638 ps
CPU time 7.62 seconds
Started Apr 25 02:33:39 PM PDT 24
Finished Apr 25 02:33:48 PM PDT 24
Peak memory 204120 kb
Host smart-f0c3e27a-7d70-4198-892a-2499c2ac883b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16794
4737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.167944737
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.2899906979
Short name T739
Test name
Test status
Simulation time 8416838804 ps
CPU time 9.77 seconds
Started Apr 25 02:33:39 PM PDT 24
Finished Apr 25 02:33:51 PM PDT 24
Peak memory 204144 kb
Host smart-ad4c9b21-b167-4c7f-8d4a-3bdcad24c2c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28999
06979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.2899906979
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.2233448927
Short name T644
Test name
Test status
Simulation time 8400907051 ps
CPU time 8.5 seconds
Started Apr 25 02:33:38 PM PDT 24
Finished Apr 25 02:33:48 PM PDT 24
Peak memory 204092 kb
Host smart-b23cde6e-3de9-410f-8252-f5152e566dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22334
48927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.2233448927
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.max_length_in_transaction.3245770429
Short name T358
Test name
Test status
Simulation time 8478104612 ps
CPU time 7.81 seconds
Started Apr 25 02:33:52 PM PDT 24
Finished Apr 25 02:34:02 PM PDT 24
Peak memory 204076 kb
Host smart-e128b404-bd10-4c25-bf14-243f93cea7c9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3245770429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.3245770429
Directory /workspace/26.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.3715027843
Short name T345
Test name
Test status
Simulation time 8380127264 ps
CPU time 8.09 seconds
Started Apr 25 02:33:52 PM PDT 24
Finished Apr 25 02:34:02 PM PDT 24
Peak memory 204112 kb
Host smart-2b54d576-11fb-4245-ac58-8f17ebe55349
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3715027843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.3715027843
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.4179716728
Short name T389
Test name
Test status
Simulation time 8531839577 ps
CPU time 8.17 seconds
Started Apr 25 02:33:53 PM PDT 24
Finished Apr 25 02:34:02 PM PDT 24
Peak memory 204128 kb
Host smart-ac5beb08-35f3-4a0a-a063-be4b2bdbc585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41797
16728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.4179716728
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.3873998017
Short name T532
Test name
Test status
Simulation time 8379553626 ps
CPU time 7.87 seconds
Started Apr 25 02:33:49 PM PDT 24
Finished Apr 25 02:33:58 PM PDT 24
Peak memory 204092 kb
Host smart-845a117b-aef3-4a22-8a2e-27f23c8307ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38739
98017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.3873998017
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_enable.619852320
Short name T384
Test name
Test status
Simulation time 8373788121 ps
CPU time 7.86 seconds
Started Apr 25 02:33:46 PM PDT 24
Finished Apr 25 02:33:55 PM PDT 24
Peak memory 204048 kb
Host smart-54e22cef-ec85-43bd-8159-0eb3af2ab1aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61985
2320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.619852320
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.2072988846
Short name T453
Test name
Test status
Simulation time 151047840 ps
CPU time 1.7 seconds
Started Apr 25 02:33:48 PM PDT 24
Finished Apr 25 02:33:50 PM PDT 24
Peak memory 204268 kb
Host smart-f2b6b0d8-5a00-45ae-8cbd-77e81c36dbc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20729
88846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.2072988846
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.146108343
Short name T163
Test name
Test status
Simulation time 8401472352 ps
CPU time 9.28 seconds
Started Apr 25 02:33:52 PM PDT 24
Finished Apr 25 02:34:03 PM PDT 24
Peak memory 204020 kb
Host smart-7b44b3b5-7181-4749-8efd-fb3cc979a8f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14610
8343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.146108343
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.1418036451
Short name T1370
Test name
Test status
Simulation time 8365621872 ps
CPU time 7.68 seconds
Started Apr 25 02:33:44 PM PDT 24
Finished Apr 25 02:33:53 PM PDT 24
Peak memory 204040 kb
Host smart-9cc56677-e583-4d94-9cdb-e001404a141f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14180
36451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1418036451
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3398189149
Short name T827
Test name
Test status
Simulation time 8437002940 ps
CPU time 7.63 seconds
Started Apr 25 02:33:46 PM PDT 24
Finished Apr 25 02:33:55 PM PDT 24
Peak memory 204016 kb
Host smart-c7ffd019-fd9c-4b8e-9cf8-5415a3da8e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33981
89149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3398189149
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.995428928
Short name T816
Test name
Test status
Simulation time 8410976585 ps
CPU time 7.72 seconds
Started Apr 25 02:33:46 PM PDT 24
Finished Apr 25 02:33:55 PM PDT 24
Peak memory 204116 kb
Host smart-9d99adcb-87ac-4e02-a84b-a1d2d356ad10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99542
8928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.995428928
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1589773259
Short name T702
Test name
Test status
Simulation time 8373018468 ps
CPU time 8.24 seconds
Started Apr 25 02:33:52 PM PDT 24
Finished Apr 25 02:34:01 PM PDT 24
Peak memory 204088 kb
Host smart-1c75122d-9628-48c8-a4be-9e58ccdd5cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15897
73259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1589773259
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.723338334
Short name T845
Test name
Test status
Simulation time 8434868472 ps
CPU time 8.59 seconds
Started Apr 25 02:33:47 PM PDT 24
Finished Apr 25 02:33:57 PM PDT 24
Peak memory 204116 kb
Host smart-9a2af3a2-7302-4035-8445-71c3da173f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72333
8334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.723338334
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1624559504
Short name T456
Test name
Test status
Simulation time 8422583827 ps
CPU time 7.95 seconds
Started Apr 25 02:33:51 PM PDT 24
Finished Apr 25 02:34:00 PM PDT 24
Peak memory 204088 kb
Host smart-87447903-14d1-44f4-a954-b423f112851e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16245
59504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1624559504
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.2159861502
Short name T1234
Test name
Test status
Simulation time 8385972773 ps
CPU time 7.65 seconds
Started Apr 25 02:33:46 PM PDT 24
Finished Apr 25 02:33:54 PM PDT 24
Peak memory 204104 kb
Host smart-1714ae79-6107-478d-8948-7a361d42d711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21598
61502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.2159861502
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.1217709028
Short name T343
Test name
Test status
Simulation time 8370208367 ps
CPU time 10.04 seconds
Started Apr 25 02:33:44 PM PDT 24
Finished Apr 25 02:33:55 PM PDT 24
Peak memory 204088 kb
Host smart-a4c94d5d-73e4-4b03-9191-e455542b6b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12177
09028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.1217709028
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1540568482
Short name T913
Test name
Test status
Simulation time 42888999 ps
CPU time 0.68 seconds
Started Apr 25 02:33:45 PM PDT 24
Finished Apr 25 02:33:47 PM PDT 24
Peak memory 204004 kb
Host smart-665f4e83-afa9-4f45-ab89-6516b1279de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15405
68482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1540568482
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3373627853
Short name T793
Test name
Test status
Simulation time 23673398375 ps
CPU time 50.42 seconds
Started Apr 25 02:33:52 PM PDT 24
Finished Apr 25 02:34:44 PM PDT 24
Peak memory 204380 kb
Host smart-7024c362-8f61-4d84-af5a-d50fe39f3a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33736
27853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3373627853
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.3149705007
Short name T543
Test name
Test status
Simulation time 8397049780 ps
CPU time 10.3 seconds
Started Apr 25 02:33:51 PM PDT 24
Finished Apr 25 02:34:02 PM PDT 24
Peak memory 204088 kb
Host smart-99cac6bb-953a-4102-b054-29b2b73af0e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31497
05007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.3149705007
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2915088884
Short name T431
Test name
Test status
Simulation time 8435131127 ps
CPU time 7.78 seconds
Started Apr 25 02:33:45 PM PDT 24
Finished Apr 25 02:33:54 PM PDT 24
Peak memory 204156 kb
Host smart-73f52255-d46c-43dc-9007-00e881242deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29150
88884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2915088884
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.717325042
Short name T661
Test name
Test status
Simulation time 8413963155 ps
CPU time 7.73 seconds
Started Apr 25 02:33:52 PM PDT 24
Finished Apr 25 02:34:00 PM PDT 24
Peak memory 204092 kb
Host smart-f3d1bd68-80c5-41c6-bc21-ad72ddb20ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71732
5042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.717325042
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.3324187470
Short name T902
Test name
Test status
Simulation time 8379261370 ps
CPU time 8.37 seconds
Started Apr 25 02:33:56 PM PDT 24
Finished Apr 25 02:34:05 PM PDT 24
Peak memory 204112 kb
Host smart-97d6884d-3aaf-4322-b6c6-98f4d4c2b888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33241
87470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3324187470
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.3814941613
Short name T1179
Test name
Test status
Simulation time 8369706887 ps
CPU time 9.77 seconds
Started Apr 25 02:33:52 PM PDT 24
Finished Apr 25 02:34:03 PM PDT 24
Peak memory 204088 kb
Host smart-a8d5ac34-696f-4181-ba48-19aa65872a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38149
41613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.3814941613
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.132897613
Short name T170
Test name
Test status
Simulation time 8434384156 ps
CPU time 7.94 seconds
Started Apr 25 02:33:45 PM PDT 24
Finished Apr 25 02:33:54 PM PDT 24
Peak memory 204120 kb
Host smart-0ed68ffc-cffe-458b-a2af-441bb32fef3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13289
7613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.132897613
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.530191624
Short name T1189
Test name
Test status
Simulation time 8389722646 ps
CPU time 8.02 seconds
Started Apr 25 02:33:45 PM PDT 24
Finished Apr 25 02:33:54 PM PDT 24
Peak memory 204140 kb
Host smart-2d3d1623-391e-4b49-886a-865c1515d1b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53019
1624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.530191624
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.30362966
Short name T1337
Test name
Test status
Simulation time 8396930914 ps
CPU time 7.52 seconds
Started Apr 25 02:33:47 PM PDT 24
Finished Apr 25 02:33:55 PM PDT 24
Peak memory 204032 kb
Host smart-578d9333-34c9-4f41-bd07-db72a6d1afcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30362
966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.30362966
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.1773698509
Short name T499
Test name
Test status
Simulation time 8516764404 ps
CPU time 8.81 seconds
Started Apr 25 02:34:00 PM PDT 24
Finished Apr 25 02:34:10 PM PDT 24
Peak memory 204056 kb
Host smart-cc58684f-025f-44b4-a5ab-debefc537b30
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1773698509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.1773698509
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.2111761337
Short name T1322
Test name
Test status
Simulation time 8409704492 ps
CPU time 7.67 seconds
Started Apr 25 02:34:01 PM PDT 24
Finished Apr 25 02:34:11 PM PDT 24
Peak memory 204112 kb
Host smart-f3c96b29-fafb-46c5-b940-217a58b8c87c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2111761337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.2111761337
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.4046735804
Short name T1210
Test name
Test status
Simulation time 8412108179 ps
CPU time 8 seconds
Started Apr 25 02:34:01 PM PDT 24
Finished Apr 25 02:34:11 PM PDT 24
Peak memory 204136 kb
Host smart-40258e16-6090-4674-80cb-814ca54f4282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40467
35804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.4046735804
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.3183209708
Short name T841
Test name
Test status
Simulation time 8371184201 ps
CPU time 7.62 seconds
Started Apr 25 02:33:51 PM PDT 24
Finished Apr 25 02:33:59 PM PDT 24
Peak memory 204140 kb
Host smart-bc804aec-485f-411f-9067-c86ee42ad879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31832
09708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.3183209708
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_enable.88106690
Short name T1324
Test name
Test status
Simulation time 8374282245 ps
CPU time 8.71 seconds
Started Apr 25 02:33:52 PM PDT 24
Finished Apr 25 02:34:03 PM PDT 24
Peak memory 204104 kb
Host smart-3933fe2b-9de7-44b4-91c4-4b9eadd41bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88106
690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.88106690
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.2889256608
Short name T908
Test name
Test status
Simulation time 226834529 ps
CPU time 1.97 seconds
Started Apr 25 02:33:53 PM PDT 24
Finished Apr 25 02:33:56 PM PDT 24
Peak memory 204168 kb
Host smart-80659327-f226-4742-adc9-2d0340754832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28892
56608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2889256608
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.1130548220
Short name T1379
Test name
Test status
Simulation time 8389245608 ps
CPU time 8.32 seconds
Started Apr 25 02:34:03 PM PDT 24
Finished Apr 25 02:34:14 PM PDT 24
Peak memory 204044 kb
Host smart-1c9a1503-214e-473e-b243-fef4ed0f961c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11305
48220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.1130548220
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.583783368
Short name T70
Test name
Test status
Simulation time 8436708155 ps
CPU time 7.93 seconds
Started Apr 25 02:34:01 PM PDT 24
Finished Apr 25 02:34:12 PM PDT 24
Peak memory 204028 kb
Host smart-3d5e6f15-0f12-4bfe-944b-c2a314c4a0ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58378
3368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.583783368
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.3200296979
Short name T736
Test name
Test status
Simulation time 8525638805 ps
CPU time 7.85 seconds
Started Apr 25 02:33:54 PM PDT 24
Finished Apr 25 02:34:03 PM PDT 24
Peak memory 204152 kb
Host smart-5e5aa44b-ca06-40d6-8de2-232240765098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32002
96979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.3200296979
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.190982533
Short name T409
Test name
Test status
Simulation time 8425076043 ps
CPU time 8.41 seconds
Started Apr 25 02:33:52 PM PDT 24
Finished Apr 25 02:34:01 PM PDT 24
Peak memory 204140 kb
Host smart-1e657367-0257-4bac-9a21-889ef27c9a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19098
2533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.190982533
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.2944817948
Short name T406
Test name
Test status
Simulation time 8382757483 ps
CPU time 7.54 seconds
Started Apr 25 02:33:51 PM PDT 24
Finished Apr 25 02:33:59 PM PDT 24
Peak memory 204128 kb
Host smart-5d988298-29c9-4dfb-8894-bf1a8d6b3d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29448
17948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.2944817948
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.2830931773
Short name T1304
Test name
Test status
Simulation time 8405671307 ps
CPU time 7.38 seconds
Started Apr 25 02:33:54 PM PDT 24
Finished Apr 25 02:34:02 PM PDT 24
Peak memory 204104 kb
Host smart-1ef45769-f92e-468d-b33c-89dda15a5ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28309
31773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2830931773
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.2714006963
Short name T891
Test name
Test status
Simulation time 8371927181 ps
CPU time 8.11 seconds
Started Apr 25 02:33:52 PM PDT 24
Finished Apr 25 02:34:02 PM PDT 24
Peak memory 204052 kb
Host smart-a644e73e-ee05-4a12-92ae-8d491f78a9b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27140
06963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2714006963
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.4212558541
Short name T1212
Test name
Test status
Simulation time 8404355083 ps
CPU time 8.03 seconds
Started Apr 25 02:33:53 PM PDT 24
Finished Apr 25 02:34:02 PM PDT 24
Peak memory 204116 kb
Host smart-1bbad2f5-7c85-4095-8c39-423ec9a3a249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42125
58541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.4212558541
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.2617344016
Short name T605
Test name
Test status
Simulation time 8370025158 ps
CPU time 9.11 seconds
Started Apr 25 02:34:03 PM PDT 24
Finished Apr 25 02:34:14 PM PDT 24
Peak memory 204112 kb
Host smart-0b2d1d97-d66b-4871-b8d5-665b91bcb00a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26173
44016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.2617344016
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3664996991
Short name T1309
Test name
Test status
Simulation time 59495947 ps
CPU time 0.69 seconds
Started Apr 25 02:34:02 PM PDT 24
Finished Apr 25 02:34:05 PM PDT 24
Peak memory 203984 kb
Host smart-ccf87ae3-fd3c-4e58-82ab-5a94bcd57ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36649
96991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3664996991
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.306531108
Short name T12
Test name
Test status
Simulation time 21438761951 ps
CPU time 41.51 seconds
Started Apr 25 02:33:52 PM PDT 24
Finished Apr 25 02:34:35 PM PDT 24
Peak memory 204396 kb
Host smart-d0557df1-cf6d-484a-901e-bf40ea8f99e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30653
1108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.306531108
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.2393354313
Short name T81
Test name
Test status
Simulation time 8394221167 ps
CPU time 8.12 seconds
Started Apr 25 02:33:52 PM PDT 24
Finished Apr 25 02:34:02 PM PDT 24
Peak memory 204020 kb
Host smart-27086af7-97bc-4a73-a975-920455f1141d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23933
54313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.2393354313
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3513064493
Short name T1311
Test name
Test status
Simulation time 8386449443 ps
CPU time 8.39 seconds
Started Apr 25 02:33:52 PM PDT 24
Finished Apr 25 02:34:01 PM PDT 24
Peak memory 204040 kb
Host smart-26dc1cc0-80ad-445c-a750-d5729814854d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35130
64493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3513064493
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.482014417
Short name T896
Test name
Test status
Simulation time 8385048295 ps
CPU time 7.51 seconds
Started Apr 25 02:34:01 PM PDT 24
Finished Apr 25 02:34:10 PM PDT 24
Peak memory 204032 kb
Host smart-e43a88f3-bf3c-41b6-974a-9dd59203de99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48201
4417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.482014417
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.3628175973
Short name T168
Test name
Test status
Simulation time 8380033166 ps
CPU time 9.45 seconds
Started Apr 25 02:34:06 PM PDT 24
Finished Apr 25 02:34:16 PM PDT 24
Peak memory 204108 kb
Host smart-f92bebb0-3372-4514-aa39-3fc0b1fdd7aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36281
75973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.3628175973
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.3996045902
Short name T1092
Test name
Test status
Simulation time 8379039216 ps
CPU time 8.06 seconds
Started Apr 25 02:33:59 PM PDT 24
Finished Apr 25 02:34:09 PM PDT 24
Peak memory 204092 kb
Host smart-7e6ddcf1-0b13-40d0-a330-f991ea6ca0b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39960
45902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.3996045902
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2164998685
Short name T648
Test name
Test status
Simulation time 8489951198 ps
CPU time 8.06 seconds
Started Apr 25 02:33:52 PM PDT 24
Finished Apr 25 02:34:00 PM PDT 24
Peak memory 204120 kb
Host smart-ec2ad1f5-ee38-47b6-8d98-2425155baaf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21649
98685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2164998685
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3938376061
Short name T366
Test name
Test status
Simulation time 8401963582 ps
CPU time 7.99 seconds
Started Apr 25 02:34:01 PM PDT 24
Finished Apr 25 02:34:11 PM PDT 24
Peak memory 204152 kb
Host smart-9f752fe6-649e-40e8-bd84-acfed4e10800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39383
76061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3938376061
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.1629420981
Short name T1139
Test name
Test status
Simulation time 8407498171 ps
CPU time 7.61 seconds
Started Apr 25 02:34:02 PM PDT 24
Finished Apr 25 02:34:12 PM PDT 24
Peak memory 204128 kb
Host smart-19dbda36-fd70-4b69-93af-47e4a836520a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16294
20981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.1629420981
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.1184740837
Short name T1148
Test name
Test status
Simulation time 8459116169 ps
CPU time 8.99 seconds
Started Apr 25 02:34:01 PM PDT 24
Finished Apr 25 02:34:12 PM PDT 24
Peak memory 204096 kb
Host smart-587e3d1d-d142-43b4-874e-1a336e661e75
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1184740837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.1184740837
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.46678680
Short name T518
Test name
Test status
Simulation time 8381401145 ps
CPU time 7.54 seconds
Started Apr 25 02:34:06 PM PDT 24
Finished Apr 25 02:34:14 PM PDT 24
Peak memory 204112 kb
Host smart-c0f03e07-362f-4fdb-bf49-2ff72a51f547
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=46678680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.46678680
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.236379024
Short name T942
Test name
Test status
Simulation time 8422726405 ps
CPU time 8.17 seconds
Started Apr 25 02:34:04 PM PDT 24
Finished Apr 25 02:34:14 PM PDT 24
Peak memory 204136 kb
Host smart-68cfb175-0b72-4450-b49e-286df73f61b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23637
9024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.236379024
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.4150681496
Short name T571
Test name
Test status
Simulation time 8377997786 ps
CPU time 8.45 seconds
Started Apr 25 02:34:02 PM PDT 24
Finished Apr 25 02:34:13 PM PDT 24
Peak memory 204116 kb
Host smart-e9b30e2b-c881-4770-bb91-f7d6512b4d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41506
81496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.4150681496
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_enable.2307867729
Short name T408
Test name
Test status
Simulation time 8423149580 ps
CPU time 8.44 seconds
Started Apr 25 02:34:03 PM PDT 24
Finished Apr 25 02:34:13 PM PDT 24
Peak memory 204148 kb
Host smart-847dfe3c-eee2-420a-948a-eeec3ce71353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23078
67729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.2307867729
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.3730146004
Short name T497
Test name
Test status
Simulation time 120836726 ps
CPU time 1.82 seconds
Started Apr 25 02:34:02 PM PDT 24
Finished Apr 25 02:34:06 PM PDT 24
Peak memory 204016 kb
Host smart-0973a377-3c59-4300-890a-63ba36c16a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37301
46004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.3730146004
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.2114302428
Short name T691
Test name
Test status
Simulation time 8448386040 ps
CPU time 7.63 seconds
Started Apr 25 02:34:03 PM PDT 24
Finished Apr 25 02:34:13 PM PDT 24
Peak memory 204112 kb
Host smart-ac0a7dd3-33de-49f6-90c5-6f6e0598fadb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21143
02428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.2114302428
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.3906740144
Short name T766
Test name
Test status
Simulation time 8367076040 ps
CPU time 8.32 seconds
Started Apr 25 02:34:07 PM PDT 24
Finished Apr 25 02:34:16 PM PDT 24
Peak memory 204112 kb
Host smart-43f6f49b-88e9-4674-8932-3aeb26228ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39067
40144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.3906740144
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.1021017385
Short name T364
Test name
Test status
Simulation time 8427744537 ps
CPU time 7.9 seconds
Started Apr 25 02:33:59 PM PDT 24
Finished Apr 25 02:34:09 PM PDT 24
Peak memory 204132 kb
Host smart-d80bb0e3-461e-4f54-8604-7d9e4aa57860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10210
17385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.1021017385
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.656250006
Short name T1332
Test name
Test status
Simulation time 8373095317 ps
CPU time 8.41 seconds
Started Apr 25 02:34:00 PM PDT 24
Finished Apr 25 02:34:10 PM PDT 24
Peak memory 204128 kb
Host smart-1c039d05-bae6-418d-9700-4196cdf3e78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65625
0006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.656250006
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.827525607
Short name T115
Test name
Test status
Simulation time 8427405005 ps
CPU time 8.76 seconds
Started Apr 25 02:34:01 PM PDT 24
Finished Apr 25 02:34:12 PM PDT 24
Peak memory 204092 kb
Host smart-f6ed074e-8af0-48d4-ae4f-932d182f80e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82752
5607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.827525607
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3850263216
Short name T1266
Test name
Test status
Simulation time 8397350388 ps
CPU time 8.6 seconds
Started Apr 25 02:34:02 PM PDT 24
Finished Apr 25 02:34:13 PM PDT 24
Peak memory 203960 kb
Host smart-c5196e3b-1829-4093-95a2-f1dc2cde7a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38502
63216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3850263216
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.1453228138
Short name T777
Test name
Test status
Simulation time 8408414447 ps
CPU time 7.58 seconds
Started Apr 25 02:33:59 PM PDT 24
Finished Apr 25 02:34:08 PM PDT 24
Peak memory 204156 kb
Host smart-95e0ee22-94ea-4255-8bb3-771ab4296409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14532
28138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.1453228138
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.2104983672
Short name T1235
Test name
Test status
Simulation time 8364414756 ps
CPU time 8.59 seconds
Started Apr 25 02:34:06 PM PDT 24
Finished Apr 25 02:34:16 PM PDT 24
Peak memory 204036 kb
Host smart-bfd752a8-25b0-4a91-936e-c7f06f778487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21049
83672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.2104983672
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.1764546822
Short name T991
Test name
Test status
Simulation time 26108357537 ps
CPU time 47.05 seconds
Started Apr 25 02:34:02 PM PDT 24
Finished Apr 25 02:34:51 PM PDT 24
Peak memory 204368 kb
Host smart-fb20f629-79ec-4c2e-8d1f-8eaef9062437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17645
46822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.1764546822
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.1972788186
Short name T905
Test name
Test status
Simulation time 8399966352 ps
CPU time 10.12 seconds
Started Apr 25 02:34:03 PM PDT 24
Finished Apr 25 02:34:15 PM PDT 24
Peak memory 204044 kb
Host smart-f3d4da5c-01c7-4d17-a9db-3f538f6e2ed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19727
88186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.1972788186
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.768183020
Short name T135
Test name
Test status
Simulation time 8412351512 ps
CPU time 8.74 seconds
Started Apr 25 02:34:08 PM PDT 24
Finished Apr 25 02:34:17 PM PDT 24
Peak memory 204112 kb
Host smart-2f16b7b9-bd3c-4d6f-97e6-1065aa59894b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76818
3020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.768183020
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.2206559791
Short name T351
Test name
Test status
Simulation time 8424278351 ps
CPU time 7.74 seconds
Started Apr 25 02:34:01 PM PDT 24
Finished Apr 25 02:34:11 PM PDT 24
Peak memory 204136 kb
Host smart-cc3a8f6c-4ea0-49fa-b45d-7d0dbf54eedc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22065
59791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.2206559791
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.118063165
Short name T725
Test name
Test status
Simulation time 8427370766 ps
CPU time 9.2 seconds
Started Apr 25 02:34:06 PM PDT 24
Finished Apr 25 02:34:16 PM PDT 24
Peak memory 204032 kb
Host smart-9a9a2702-6158-4f44-b6a1-2e838cb9a0dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11806
3165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.118063165
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1727315322
Short name T334
Test name
Test status
Simulation time 8372626997 ps
CPU time 7.89 seconds
Started Apr 25 02:34:03 PM PDT 24
Finished Apr 25 02:34:13 PM PDT 24
Peak memory 204128 kb
Host smart-60b02396-9d21-4703-8bd1-5ca20cd47a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17273
15322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1727315322
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.1596484265
Short name T1277
Test name
Test status
Simulation time 8436905573 ps
CPU time 9.41 seconds
Started Apr 25 02:33:59 PM PDT 24
Finished Apr 25 02:34:10 PM PDT 24
Peak memory 204064 kb
Host smart-d1ae538d-e6fd-4725-bda3-792e6f5c5739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15964
84265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.1596484265
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.753496470
Short name T463
Test name
Test status
Simulation time 8404423658 ps
CPU time 10.02 seconds
Started Apr 25 02:34:03 PM PDT 24
Finished Apr 25 02:34:15 PM PDT 24
Peak memory 204084 kb
Host smart-df8c1d13-5473-44f9-9bcd-7c88c116dca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75349
6470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.753496470
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.2866909885
Short name T1383
Test name
Test status
Simulation time 8394000665 ps
CPU time 8.62 seconds
Started Apr 25 02:34:10 PM PDT 24
Finished Apr 25 02:34:20 PM PDT 24
Peak memory 204156 kb
Host smart-723b0bc7-cd64-4cd7-adc1-a77fe0ca140c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28669
09885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.2866909885
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.4204666907
Short name T1373
Test name
Test status
Simulation time 8505809994 ps
CPU time 8.26 seconds
Started Apr 25 02:34:17 PM PDT 24
Finished Apr 25 02:34:26 PM PDT 24
Peak memory 204148 kb
Host smart-763e1f3b-a222-48a5-86db-afc68a2c8280
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4204666907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.4204666907
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.1634008108
Short name T888
Test name
Test status
Simulation time 8381056954 ps
CPU time 8.44 seconds
Started Apr 25 02:34:14 PM PDT 24
Finished Apr 25 02:34:24 PM PDT 24
Peak memory 204052 kb
Host smart-4e8fd44a-cbd4-42d0-98be-20fdd178a916
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1634008108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.1634008108
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.826236568
Short name T1023
Test name
Test status
Simulation time 8466695942 ps
CPU time 8.89 seconds
Started Apr 25 02:34:14 PM PDT 24
Finished Apr 25 02:34:24 PM PDT 24
Peak memory 204108 kb
Host smart-365278a9-a21e-45a4-ae5a-d1e30e631cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82623
6568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.826236568
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.2706809389
Short name T730
Test name
Test status
Simulation time 8437960954 ps
CPU time 9.44 seconds
Started Apr 25 02:34:04 PM PDT 24
Finished Apr 25 02:34:15 PM PDT 24
Peak memory 204148 kb
Host smart-07b79f57-d25a-46c3-bb69-63533048e3f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27068
09389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.2706809389
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_enable.289470228
Short name T315
Test name
Test status
Simulation time 8378507517 ps
CPU time 8.04 seconds
Started Apr 25 02:34:08 PM PDT 24
Finished Apr 25 02:34:17 PM PDT 24
Peak memory 204116 kb
Host smart-f7731890-0eaf-4a28-ae9b-314ecfe45494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28947
0228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.289470228
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.2029795362
Short name T965
Test name
Test status
Simulation time 145062760 ps
CPU time 1.39 seconds
Started Apr 25 02:34:08 PM PDT 24
Finished Apr 25 02:34:10 PM PDT 24
Peak memory 204184 kb
Host smart-89a022ec-774e-49f0-80aa-c1fe8e9d5881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20297
95362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.2029795362
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.1052309047
Short name T152
Test name
Test status
Simulation time 8421754747 ps
CPU time 8.96 seconds
Started Apr 25 02:34:14 PM PDT 24
Finished Apr 25 02:34:25 PM PDT 24
Peak memory 204028 kb
Host smart-1ab5e5fc-9b57-44f5-a127-4b0a7f94f83d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10523
09047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.1052309047
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.1813108799
Short name T717
Test name
Test status
Simulation time 8368615563 ps
CPU time 8.08 seconds
Started Apr 25 02:34:19 PM PDT 24
Finished Apr 25 02:34:28 PM PDT 24
Peak memory 204120 kb
Host smart-ab5eddec-7a85-4855-9466-3e7290720de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18131
08799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.1813108799
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.2015585511
Short name T1217
Test name
Test status
Simulation time 8429583573 ps
CPU time 9.99 seconds
Started Apr 25 02:34:10 PM PDT 24
Finished Apr 25 02:34:22 PM PDT 24
Peak memory 204116 kb
Host smart-d1ddb470-db69-42e8-8fcf-2ad892f5cd86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20155
85511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.2015585511
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.1599913963
Short name T752
Test name
Test status
Simulation time 8413609848 ps
CPU time 7.97 seconds
Started Apr 25 02:34:12 PM PDT 24
Finished Apr 25 02:34:22 PM PDT 24
Peak memory 204140 kb
Host smart-b416c151-d47a-4fb3-9214-3fc2f4a47f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15999
13963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.1599913963
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.4025438053
Short name T1333
Test name
Test status
Simulation time 8385305033 ps
CPU time 8.8 seconds
Started Apr 25 02:34:10 PM PDT 24
Finished Apr 25 02:34:20 PM PDT 24
Peak memory 204140 kb
Host smart-f37153f4-78fc-4fee-8ccb-ab0955f7fa61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40254
38053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.4025438053
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.1612053029
Short name T130
Test name
Test status
Simulation time 8433764397 ps
CPU time 8.56 seconds
Started Apr 25 02:34:08 PM PDT 24
Finished Apr 25 02:34:18 PM PDT 24
Peak memory 204152 kb
Host smart-430a6fa7-1717-4eab-89f4-85c29d0a1697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16120
53029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.1612053029
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.1700238782
Short name T1094
Test name
Test status
Simulation time 8416140564 ps
CPU time 8.37 seconds
Started Apr 25 02:34:10 PM PDT 24
Finished Apr 25 02:34:20 PM PDT 24
Peak memory 204156 kb
Host smart-2c6d7551-c34e-41c5-9ef6-0b1377c4f008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17002
38782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.1700238782
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.4204336963
Short name T1078
Test name
Test status
Simulation time 8374593725 ps
CPU time 8.21 seconds
Started Apr 25 02:34:10 PM PDT 24
Finished Apr 25 02:34:20 PM PDT 24
Peak memory 204140 kb
Host smart-56615aed-0d1e-4fd5-b30b-68f1f81bab08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42043
36963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.4204336963
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.2087033742
Short name T185
Test name
Test status
Simulation time 8391732498 ps
CPU time 8.68 seconds
Started Apr 25 02:34:12 PM PDT 24
Finished Apr 25 02:34:22 PM PDT 24
Peak memory 204152 kb
Host smart-270a5cc0-587b-467d-8b1a-973c0cf6daec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20870
33742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.2087033742
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.2961471717
Short name T420
Test name
Test status
Simulation time 8371486838 ps
CPU time 10.08 seconds
Started Apr 25 02:34:09 PM PDT 24
Finished Apr 25 02:34:20 PM PDT 24
Peak memory 204132 kb
Host smart-1a767a3d-a0af-492c-979a-2d4eddd18111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29614
71717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.2961471717
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.534644533
Short name T501
Test name
Test status
Simulation time 33743260 ps
CPU time 0.68 seconds
Started Apr 25 02:34:09 PM PDT 24
Finished Apr 25 02:34:11 PM PDT 24
Peak memory 204008 kb
Host smart-c036e8aa-5b9e-4009-bbf3-392b92fcef33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53464
4533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.534644533
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.4272339549
Short name T1385
Test name
Test status
Simulation time 17812222706 ps
CPU time 30.89 seconds
Started Apr 25 02:34:13 PM PDT 24
Finished Apr 25 02:34:45 PM PDT 24
Peak memory 204400 kb
Host smart-b64f4448-a72e-4e46-a231-45fff960e618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42723
39549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.4272339549
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1607605872
Short name T1086
Test name
Test status
Simulation time 8424604442 ps
CPU time 9.1 seconds
Started Apr 25 02:34:12 PM PDT 24
Finished Apr 25 02:34:22 PM PDT 24
Peak memory 204112 kb
Host smart-38de7a5b-fc3e-45e4-bf2c-986bc13be84b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16076
05872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1607605872
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.1660661628
Short name T516
Test name
Test status
Simulation time 8475663270 ps
CPU time 8.19 seconds
Started Apr 25 02:34:10 PM PDT 24
Finished Apr 25 02:34:20 PM PDT 24
Peak memory 204104 kb
Host smart-4be985b5-5205-435a-851a-0ee618729886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16606
61628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.1660661628
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.770497475
Short name T708
Test name
Test status
Simulation time 8399969052 ps
CPU time 7.77 seconds
Started Apr 25 02:34:12 PM PDT 24
Finished Apr 25 02:34:21 PM PDT 24
Peak memory 204116 kb
Host smart-251009b8-c607-4309-afb3-ddedb2383493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77049
7475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.770497475
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.241350567
Short name T1117
Test name
Test status
Simulation time 8397976765 ps
CPU time 8.51 seconds
Started Apr 25 02:34:11 PM PDT 24
Finished Apr 25 02:34:21 PM PDT 24
Peak memory 204132 kb
Host smart-6405e49d-02c3-4734-9654-5120467a6b0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24135
0567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.241350567
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_smoke.2487205462
Short name T787
Test name
Test status
Simulation time 8436551931 ps
CPU time 8.87 seconds
Started Apr 25 02:34:06 PM PDT 24
Finished Apr 25 02:34:16 PM PDT 24
Peak memory 204112 kb
Host smart-e45408de-bb24-4aec-b284-59e51b42ca52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24872
05462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2487205462
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.104330458
Short name T133
Test name
Test status
Simulation time 8397347606 ps
CPU time 7.93 seconds
Started Apr 25 02:34:10 PM PDT 24
Finished Apr 25 02:34:19 PM PDT 24
Peak memory 204072 kb
Host smart-adba4d3c-b775-4df7-877c-f2ffb195f793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10433
0458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.104330458
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.497187443
Short name T325
Test name
Test status
Simulation time 8371979818 ps
CPU time 7.72 seconds
Started Apr 25 02:34:10 PM PDT 24
Finished Apr 25 02:34:19 PM PDT 24
Peak memory 204104 kb
Host smart-7683338f-7ac9-47fc-a3b7-7799dd85d4ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49718
7443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.497187443
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.4068274744
Short name T794
Test name
Test status
Simulation time 8469755155 ps
CPU time 8.51 seconds
Started Apr 25 02:29:36 PM PDT 24
Finished Apr 25 02:29:45 PM PDT 24
Peak memory 204124 kb
Host smart-c063c898-559b-4599-be14-d1d76afbafa7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4068274744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.4068274744
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.3949216620
Short name T813
Test name
Test status
Simulation time 8382029534 ps
CPU time 8.65 seconds
Started Apr 25 02:29:34 PM PDT 24
Finished Apr 25 02:29:43 PM PDT 24
Peak memory 204148 kb
Host smart-3f31fe26-717f-4009-bd38-af3dba0290dd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3949216620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.3949216620
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.3003355214
Short name T1072
Test name
Test status
Simulation time 8383296298 ps
CPU time 8.57 seconds
Started Apr 25 02:29:37 PM PDT 24
Finished Apr 25 02:29:46 PM PDT 24
Peak memory 204056 kb
Host smart-8e9ad0cb-0193-422f-a2e1-08a653cf7f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30033
55214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.3003355214
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1623830656
Short name T721
Test name
Test status
Simulation time 8378465943 ps
CPU time 7.8 seconds
Started Apr 25 02:29:23 PM PDT 24
Finished Apr 25 02:29:33 PM PDT 24
Peak memory 204116 kb
Host smart-c03beccc-f673-49bf-ab61-ae14e348f57c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16238
30656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1623830656
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_enable.201186669
Short name T375
Test name
Test status
Simulation time 8378594526 ps
CPU time 7.37 seconds
Started Apr 25 02:29:21 PM PDT 24
Finished Apr 25 02:29:30 PM PDT 24
Peak memory 204100 kb
Host smart-049a33bf-5520-4cb9-827e-42b815182d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20118
6669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.201186669
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3797815974
Short name T555
Test name
Test status
Simulation time 166906776 ps
CPU time 1.69 seconds
Started Apr 25 02:29:22 PM PDT 24
Finished Apr 25 02:29:25 PM PDT 24
Peak memory 204164 kb
Host smart-72f03d19-c1d5-49e1-ae02-d6549dd3e568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37978
15974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3797815974
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.485374208
Short name T1021
Test name
Test status
Simulation time 8401576391 ps
CPU time 8.28 seconds
Started Apr 25 02:29:35 PM PDT 24
Finished Apr 25 02:29:44 PM PDT 24
Peak memory 204144 kb
Host smart-468d513d-70ab-44ea-b321-75a4b48bcd31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48537
4208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.485374208
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.340476764
Short name T198
Test name
Test status
Simulation time 8383669228 ps
CPU time 7.67 seconds
Started Apr 25 02:29:36 PM PDT 24
Finished Apr 25 02:29:44 PM PDT 24
Peak memory 204116 kb
Host smart-0242ca70-7785-45eb-b55e-5191219f4b0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34047
6764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.340476764
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.839750043
Short name T595
Test name
Test status
Simulation time 8441379462 ps
CPU time 9.34 seconds
Started Apr 25 02:29:23 PM PDT 24
Finished Apr 25 02:29:34 PM PDT 24
Peak memory 204144 kb
Host smart-ef04ef08-6c0c-4b26-8b0f-ed2da06657f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83975
0043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.839750043
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.2464044993
Short name T828
Test name
Test status
Simulation time 8413058561 ps
CPU time 8.07 seconds
Started Apr 25 02:29:22 PM PDT 24
Finished Apr 25 02:29:31 PM PDT 24
Peak memory 204092 kb
Host smart-9fd03c85-dff1-42f8-b397-93a00e2af89f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24640
44993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.2464044993
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2281161170
Short name T428
Test name
Test status
Simulation time 8376133976 ps
CPU time 7.92 seconds
Started Apr 25 02:29:24 PM PDT 24
Finished Apr 25 02:29:33 PM PDT 24
Peak memory 204144 kb
Host smart-098cca54-d7fc-48b4-aa3e-09fbfef0b2b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22811
61170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2281161170
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.3499663029
Short name T1318
Test name
Test status
Simulation time 8391292289 ps
CPU time 7.57 seconds
Started Apr 25 02:29:22 PM PDT 24
Finished Apr 25 02:29:31 PM PDT 24
Peak memory 204144 kb
Host smart-9211cd18-c65d-4314-b681-acbf3948434f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34996
63029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.3499663029
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.1722040818
Short name T1103
Test name
Test status
Simulation time 8404266761 ps
CPU time 8.15 seconds
Started Apr 25 02:29:22 PM PDT 24
Finished Apr 25 02:29:32 PM PDT 24
Peak memory 204128 kb
Host smart-c2788ed2-d90c-4c85-aca5-64cdf903b894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17220
40818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.1722040818
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.918408147
Short name T28
Test name
Test status
Simulation time 8414613554 ps
CPU time 9.53 seconds
Started Apr 25 02:29:21 PM PDT 24
Finished Apr 25 02:29:32 PM PDT 24
Peak memory 204140 kb
Host smart-344e8bfb-7155-4ccd-a206-3f65ed7427b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91840
8147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.918408147
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.3673595497
Short name T1381
Test name
Test status
Simulation time 8385683143 ps
CPU time 7.56 seconds
Started Apr 25 02:29:31 PM PDT 24
Finished Apr 25 02:29:39 PM PDT 24
Peak memory 204068 kb
Host smart-44f039d2-d21a-4f77-aaf3-70a280aada13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36735
95497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.3673595497
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.822186106
Short name T893
Test name
Test status
Simulation time 8369267342 ps
CPU time 7.26 seconds
Started Apr 25 02:29:29 PM PDT 24
Finished Apr 25 02:29:37 PM PDT 24
Peak memory 204052 kb
Host smart-d8faf423-14b5-4c32-b59c-645b8fb1c4bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82218
6106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.822186106
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.1217552131
Short name T1243
Test name
Test status
Simulation time 40295896 ps
CPU time 0.62 seconds
Started Apr 25 02:29:36 PM PDT 24
Finished Apr 25 02:29:38 PM PDT 24
Peak memory 204004 kb
Host smart-d8bd8c81-b982-4537-8a16-61c71cbcecd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12175
52131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1217552131
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.805182099
Short name T1249
Test name
Test status
Simulation time 27580608315 ps
CPU time 53.68 seconds
Started Apr 25 02:29:31 PM PDT 24
Finished Apr 25 02:30:26 PM PDT 24
Peak memory 204432 kb
Host smart-e405bbbc-df2a-4da1-bbe1-e4cdd006eaf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80518
2099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.805182099
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1377037930
Short name T716
Test name
Test status
Simulation time 8426373424 ps
CPU time 10.39 seconds
Started Apr 25 02:29:28 PM PDT 24
Finished Apr 25 02:29:39 PM PDT 24
Peak memory 204104 kb
Host smart-d8256294-8c84-497c-a47a-c39a967634de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13770
37930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1377037930
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.110265933
Short name T855
Test name
Test status
Simulation time 8382601100 ps
CPU time 7.56 seconds
Started Apr 25 02:29:29 PM PDT 24
Finished Apr 25 02:29:37 PM PDT 24
Peak memory 204148 kb
Host smart-4a3f0ec3-7b74-4f55-9ecf-8bef1dc7a4b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11026
5933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.110265933
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.1879672951
Short name T704
Test name
Test status
Simulation time 8390942144 ps
CPU time 8.47 seconds
Started Apr 25 02:29:30 PM PDT 24
Finished Apr 25 02:29:39 PM PDT 24
Peak memory 204116 kb
Host smart-0cf55dbe-34f7-44e5-94f1-cc448e0968a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18796
72951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.1879672951
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.623645461
Short name T55
Test name
Test status
Simulation time 236837076 ps
CPU time 1.04 seconds
Started Apr 25 02:29:42 PM PDT 24
Finished Apr 25 02:29:44 PM PDT 24
Peak memory 220408 kb
Host smart-cc24e013-2682-47ac-97a3-9a93e594f8f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=623645461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.623645461
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.2065643527
Short name T746
Test name
Test status
Simulation time 8372483258 ps
CPU time 7.77 seconds
Started Apr 25 02:29:28 PM PDT 24
Finished Apr 25 02:29:36 PM PDT 24
Peak memory 204104 kb
Host smart-50029805-4e1a-4d2c-a4b5-c005cd92cef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20656
43527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.2065643527
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2543568704
Short name T939
Test name
Test status
Simulation time 8370513701 ps
CPU time 8.45 seconds
Started Apr 25 02:29:32 PM PDT 24
Finished Apr 25 02:29:41 PM PDT 24
Peak memory 204132 kb
Host smart-5a7e37d5-2117-46b7-b975-5acadbb6f058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25435
68704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2543568704
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.3392457965
Short name T1241
Test name
Test status
Simulation time 8407989039 ps
CPU time 7.81 seconds
Started Apr 25 02:29:27 PM PDT 24
Finished Apr 25 02:29:35 PM PDT 24
Peak memory 204132 kb
Host smart-6127909a-c6a1-48a2-b600-34d00797ee2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33924
57965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.3392457965
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.767465486
Short name T986
Test name
Test status
Simulation time 8466039636 ps
CPU time 9.73 seconds
Started Apr 25 02:34:19 PM PDT 24
Finished Apr 25 02:34:30 PM PDT 24
Peak memory 204148 kb
Host smart-26a76436-e115-4d25-9340-660c76f59963
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=767465486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.767465486
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.2446850170
Short name T1352
Test name
Test status
Simulation time 8373058111 ps
CPU time 7.47 seconds
Started Apr 25 02:34:24 PM PDT 24
Finished Apr 25 02:34:32 PM PDT 24
Peak memory 204112 kb
Host smart-8e8cd12c-1970-4a8e-bdf8-a331f08bd97d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2446850170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.2446850170
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.3327447248
Short name T547
Test name
Test status
Simulation time 8517433160 ps
CPU time 7.64 seconds
Started Apr 25 02:34:28 PM PDT 24
Finished Apr 25 02:34:36 PM PDT 24
Peak memory 204108 kb
Host smart-f247fa6a-39d6-4e3e-bd79-984396e4d6ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33274
47248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.3327447248
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.2142661541
Short name T365
Test name
Test status
Simulation time 8383411260 ps
CPU time 8.15 seconds
Started Apr 25 02:34:14 PM PDT 24
Finished Apr 25 02:34:23 PM PDT 24
Peak memory 204124 kb
Host smart-27066ae9-8c24-4ba1-951e-4f70e6a4114f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21426
61541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.2142661541
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_enable.25404482
Short name T370
Test name
Test status
Simulation time 8372091361 ps
CPU time 9.92 seconds
Started Apr 25 02:34:16 PM PDT 24
Finished Apr 25 02:34:27 PM PDT 24
Peak memory 204132 kb
Host smart-7189f2e0-813b-427f-9c23-34d8cac445fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25404
482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.25404482
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.4250152557
Short name T220
Test name
Test status
Simulation time 38826457 ps
CPU time 0.97 seconds
Started Apr 25 02:34:16 PM PDT 24
Finished Apr 25 02:34:18 PM PDT 24
Peak memory 204204 kb
Host smart-7f507739-f7d0-44d7-889e-96ee09e3ed2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42501
52557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.4250152557
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.415752845
Short name T1252
Test name
Test status
Simulation time 8395088172 ps
CPU time 9.19 seconds
Started Apr 25 02:34:24 PM PDT 24
Finished Apr 25 02:34:34 PM PDT 24
Peak memory 204160 kb
Host smart-cf97f4ce-080a-413a-9464-fd5de9e30371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41575
2845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.415752845
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.3004515782
Short name T5
Test name
Test status
Simulation time 8360702493 ps
CPU time 9.08 seconds
Started Apr 25 02:34:32 PM PDT 24
Finished Apr 25 02:34:44 PM PDT 24
Peak memory 204100 kb
Host smart-ed64b8d0-c841-470c-8245-4940fa1479c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30045
15782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.3004515782
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.4060318884
Short name T669
Test name
Test status
Simulation time 8426993605 ps
CPU time 8.95 seconds
Started Apr 25 02:34:18 PM PDT 24
Finished Apr 25 02:34:27 PM PDT 24
Peak memory 204108 kb
Host smart-0238e8ed-ef55-42e8-8932-526253ba93ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40603
18884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.4060318884
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.2098506464
Short name T954
Test name
Test status
Simulation time 8423203121 ps
CPU time 7.46 seconds
Started Apr 25 02:34:18 PM PDT 24
Finished Apr 25 02:34:26 PM PDT 24
Peak memory 204100 kb
Host smart-472996eb-8f84-426d-81d4-a58b2dcf3622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20985
06464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.2098506464
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.3946610383
Short name T1050
Test name
Test status
Simulation time 8369061573 ps
CPU time 7.63 seconds
Started Apr 25 02:34:18 PM PDT 24
Finished Apr 25 02:34:26 PM PDT 24
Peak memory 204100 kb
Host smart-aa7fcc0f-e0a7-4ff1-bebc-fd2b6c7cb6b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39466
10383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.3946610383
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.705539604
Short name T110
Test name
Test status
Simulation time 8410635584 ps
CPU time 9.8 seconds
Started Apr 25 02:34:14 PM PDT 24
Finished Apr 25 02:34:25 PM PDT 24
Peak memory 204160 kb
Host smart-7d51a673-00f1-4f45-bf46-37280672b13f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70553
9604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.705539604
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.1744959491
Short name T683
Test name
Test status
Simulation time 8408596778 ps
CPU time 8.52 seconds
Started Apr 25 02:34:17 PM PDT 24
Finished Apr 25 02:34:26 PM PDT 24
Peak memory 204140 kb
Host smart-07e97857-b4f5-429d-955c-36998aa531a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17449
59491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.1744959491
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.2795287858
Short name T1000
Test name
Test status
Simulation time 8413914590 ps
CPU time 10.1 seconds
Started Apr 25 02:34:17 PM PDT 24
Finished Apr 25 02:34:28 PM PDT 24
Peak memory 204140 kb
Host smart-282b0d67-bdd1-493a-8ad8-1d1e278846f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27952
87858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.2795287858
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.2010799386
Short name T747
Test name
Test status
Simulation time 8404510268 ps
CPU time 9.12 seconds
Started Apr 25 02:34:19 PM PDT 24
Finished Apr 25 02:34:30 PM PDT 24
Peak memory 204108 kb
Host smart-86c10360-a4fd-41e1-8c4c-eb5ee13fa159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20107
99386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.2010799386
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.1276143572
Short name T695
Test name
Test status
Simulation time 8372343895 ps
CPU time 9.7 seconds
Started Apr 25 02:34:21 PM PDT 24
Finished Apr 25 02:34:32 PM PDT 24
Peak memory 204068 kb
Host smart-647d5c7c-8ddd-4eec-9eaa-41b46048e861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12761
43572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.1276143572
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.3182440454
Short name T874
Test name
Test status
Simulation time 36642615 ps
CPU time 0.68 seconds
Started Apr 25 02:34:22 PM PDT 24
Finished Apr 25 02:34:23 PM PDT 24
Peak memory 204008 kb
Host smart-f44977cc-9f53-46e8-b4b4-5900c78a8ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31824
40454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.3182440454
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.2390823976
Short name T755
Test name
Test status
Simulation time 26318273518 ps
CPU time 53.55 seconds
Started Apr 25 02:34:22 PM PDT 24
Finished Apr 25 02:35:17 PM PDT 24
Peak memory 204436 kb
Host smart-68004d31-3840-49f8-bdab-2498d9c65c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23908
23976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.2390823976
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.1845739435
Short name T946
Test name
Test status
Simulation time 8369132871 ps
CPU time 8.76 seconds
Started Apr 25 02:34:19 PM PDT 24
Finished Apr 25 02:34:28 PM PDT 24
Peak memory 204072 kb
Host smart-4125797e-b809-41e9-ae23-a995db03a3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18457
39435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1845739435
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.3538849718
Short name T1359
Test name
Test status
Simulation time 8426539254 ps
CPU time 7.96 seconds
Started Apr 25 02:34:21 PM PDT 24
Finished Apr 25 02:34:30 PM PDT 24
Peak memory 204148 kb
Host smart-cccf4c79-f4ac-4225-ac15-109a387d4a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35388
49718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.3538849718
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.1850090249
Short name T1074
Test name
Test status
Simulation time 8436119947 ps
CPU time 8.41 seconds
Started Apr 25 02:34:19 PM PDT 24
Finished Apr 25 02:34:28 PM PDT 24
Peak memory 204136 kb
Host smart-76acceb8-5b63-4a5f-95ec-7f992473ba5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18500
90249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.1850090249
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.4041795472
Short name T570
Test name
Test status
Simulation time 8426706743 ps
CPU time 7.62 seconds
Started Apr 25 02:34:24 PM PDT 24
Finished Apr 25 02:34:32 PM PDT 24
Peak memory 204104 kb
Host smart-b6f5aecb-319a-4b9b-86b1-f24674170770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40417
95472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.4041795472
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.1304440039
Short name T347
Test name
Test status
Simulation time 8371526652 ps
CPU time 8.36 seconds
Started Apr 25 02:34:21 PM PDT 24
Finished Apr 25 02:34:31 PM PDT 24
Peak memory 204140 kb
Host smart-6920cc71-64a6-43a7-af2b-1ac278bae205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13044
40039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.1304440039
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.1883729809
Short name T1073
Test name
Test status
Simulation time 8469830669 ps
CPU time 7.74 seconds
Started Apr 25 02:34:16 PM PDT 24
Finished Apr 25 02:34:25 PM PDT 24
Peak memory 204112 kb
Host smart-774c54fb-8dd7-465c-9d43-b8b3c091ffda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18837
29809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.1883729809
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.1818355372
Short name T312
Test name
Test status
Simulation time 8419444253 ps
CPU time 9.51 seconds
Started Apr 25 02:34:23 PM PDT 24
Finished Apr 25 02:34:33 PM PDT 24
Peak memory 204116 kb
Host smart-4528feb5-6dbb-4607-a085-1472641da6d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18183
55372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.1818355372
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.3970123333
Short name T33
Test name
Test status
Simulation time 8413127888 ps
CPU time 8.49 seconds
Started Apr 25 02:34:23 PM PDT 24
Finished Apr 25 02:34:32 PM PDT 24
Peak memory 204140 kb
Host smart-0d17e288-104a-4434-8896-a9436f11df9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39701
23333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.3970123333
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.3253258511
Short name T1289
Test name
Test status
Simulation time 8463538414 ps
CPU time 8.13 seconds
Started Apr 25 02:34:44 PM PDT 24
Finished Apr 25 02:34:53 PM PDT 24
Peak memory 204140 kb
Host smart-64c2daa9-9f9a-48e9-bbf4-d79a1e35d114
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3253258511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.3253258511
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.min_length_in_transaction.2803395021
Short name T388
Test name
Test status
Simulation time 8377378930 ps
CPU time 7.73 seconds
Started Apr 25 02:34:31 PM PDT 24
Finished Apr 25 02:34:40 PM PDT 24
Peak memory 204120 kb
Host smart-3ea199d6-f43a-4f94-ae08-df57a99a96dc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2803395021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.2803395021
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.2384293658
Short name T1135
Test name
Test status
Simulation time 8402756577 ps
CPU time 7.58 seconds
Started Apr 25 02:34:32 PM PDT 24
Finished Apr 25 02:34:42 PM PDT 24
Peak memory 204136 kb
Host smart-7c193548-6c76-4df3-b9f9-0e85136cafa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23842
93658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.2384293658
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.3885467277
Short name T283
Test name
Test status
Simulation time 8384326805 ps
CPU time 9.44 seconds
Started Apr 25 02:34:27 PM PDT 24
Finished Apr 25 02:34:38 PM PDT 24
Peak memory 204156 kb
Host smart-63f3353c-518a-4f3a-b913-22a7701b7caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38854
67277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.3885467277
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_enable.362876062
Short name T503
Test name
Test status
Simulation time 8374658699 ps
CPU time 8.68 seconds
Started Apr 25 02:34:31 PM PDT 24
Finished Apr 25 02:34:41 PM PDT 24
Peak memory 204092 kb
Host smart-2e9db516-d6de-4e6b-a141-aca49239d921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36287
6062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.362876062
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.2501821817
Short name T564
Test name
Test status
Simulation time 139714601 ps
CPU time 1.27 seconds
Started Apr 25 02:34:25 PM PDT 24
Finished Apr 25 02:34:27 PM PDT 24
Peak memory 204132 kb
Host smart-6ea83133-344b-44ca-b103-5bd0446770b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25018
21817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.2501821817
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.1128472098
Short name T151
Test name
Test status
Simulation time 8403444486 ps
CPU time 9.75 seconds
Started Apr 25 02:34:29 PM PDT 24
Finished Apr 25 02:34:40 PM PDT 24
Peak memory 204112 kb
Host smart-f4779bbc-343d-4e8b-895d-28618f38c4bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11284
72098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.1128472098
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.3301041379
Short name T209
Test name
Test status
Simulation time 8395582420 ps
CPU time 8.28 seconds
Started Apr 25 02:34:33 PM PDT 24
Finished Apr 25 02:34:43 PM PDT 24
Peak memory 204096 kb
Host smart-a42efc30-184a-435a-89a8-7ca8d568abd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33010
41379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.3301041379
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.2216977920
Short name T714
Test name
Test status
Simulation time 8447070119 ps
CPU time 7.65 seconds
Started Apr 25 02:34:30 PM PDT 24
Finished Apr 25 02:34:39 PM PDT 24
Peak memory 204140 kb
Host smart-47a28f28-7df2-4755-99f5-9c893610ddef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22169
77920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.2216977920
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.3449618604
Short name T634
Test name
Test status
Simulation time 8426829495 ps
CPU time 7.91 seconds
Started Apr 25 02:34:27 PM PDT 24
Finished Apr 25 02:34:36 PM PDT 24
Peak memory 204136 kb
Host smart-4c16dc72-b666-41f5-bd8d-9955aa52fb00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34496
18604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.3449618604
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1648240007
Short name T1257
Test name
Test status
Simulation time 8389174264 ps
CPU time 8.79 seconds
Started Apr 25 02:34:26 PM PDT 24
Finished Apr 25 02:34:36 PM PDT 24
Peak memory 204120 kb
Host smart-338b7a21-9bfb-40bb-8bdb-be79d351a0e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16482
40007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1648240007
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.874571565
Short name T984
Test name
Test status
Simulation time 8419320750 ps
CPU time 7.88 seconds
Started Apr 25 02:34:31 PM PDT 24
Finished Apr 25 02:34:40 PM PDT 24
Peak memory 204124 kb
Host smart-e2d4b758-3537-4a6e-9923-89a8f24b6075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87457
1565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.874571565
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.4093089468
Short name T776
Test name
Test status
Simulation time 8434272110 ps
CPU time 8.32 seconds
Started Apr 25 02:34:30 PM PDT 24
Finished Apr 25 02:34:40 PM PDT 24
Peak memory 204140 kb
Host smart-0b504abd-2fcd-4ebb-b7ef-79a78579dd2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40930
89468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.4093089468
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.151098971
Short name T372
Test name
Test status
Simulation time 8413605541 ps
CPU time 7.49 seconds
Started Apr 25 02:34:28 PM PDT 24
Finished Apr 25 02:34:36 PM PDT 24
Peak memory 204132 kb
Host smart-ff2b510a-aa6b-4dd9-b06e-fddb5539cf08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15109
8971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.151098971
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.4207438543
Short name T178
Test name
Test status
Simulation time 8373322171 ps
CPU time 8.04 seconds
Started Apr 25 02:34:31 PM PDT 24
Finished Apr 25 02:34:40 PM PDT 24
Peak memory 204124 kb
Host smart-a21b673a-aaea-40c6-9c69-4d23b9e50837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42074
38543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.4207438543
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.3572990937
Short name T1282
Test name
Test status
Simulation time 8370304266 ps
CPU time 8.07 seconds
Started Apr 25 02:34:26 PM PDT 24
Finished Apr 25 02:34:36 PM PDT 24
Peak memory 204136 kb
Host smart-81f72d4e-b3fd-4a0d-abb0-f5428cae2610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35729
90937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.3572990937
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.2310822558
Short name T1250
Test name
Test status
Simulation time 77168891 ps
CPU time 0.68 seconds
Started Apr 25 02:34:26 PM PDT 24
Finished Apr 25 02:34:27 PM PDT 24
Peak memory 203972 kb
Host smart-c7fbcb81-08ad-4b6f-b363-e58d71e07b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23108
22558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.2310822558
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.2567227
Short name T1202
Test name
Test status
Simulation time 26092349496 ps
CPU time 48.48 seconds
Started Apr 25 02:34:27 PM PDT 24
Finished Apr 25 02:35:17 PM PDT 24
Peak memory 204356 kb
Host smart-2f3c6d73-566d-410c-b40c-bcd8b5652e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25672
27 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.2567227
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.340557107
Short name T540
Test name
Test status
Simulation time 8396318631 ps
CPU time 10.06 seconds
Started Apr 25 02:34:30 PM PDT 24
Finished Apr 25 02:34:41 PM PDT 24
Peak memory 204128 kb
Host smart-228bf0b8-73f5-45e7-b7bb-06563efb266e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34055
7107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.340557107
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.4136580527
Short name T37
Test name
Test status
Simulation time 8407489311 ps
CPU time 10.22 seconds
Started Apr 25 02:34:30 PM PDT 24
Finished Apr 25 02:34:42 PM PDT 24
Peak memory 204140 kb
Host smart-df569505-6aa6-42dd-8f9f-e34b079a2011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41365
80527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.4136580527
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.1761133610
Short name T600
Test name
Test status
Simulation time 8376330264 ps
CPU time 9.01 seconds
Started Apr 25 02:34:31 PM PDT 24
Finished Apr 25 02:34:42 PM PDT 24
Peak memory 204056 kb
Host smart-1b4ec8bf-55b0-41cf-8eec-15cd5b824d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17611
33610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.1761133610
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.804434219
Short name T1357
Test name
Test status
Simulation time 8376385981 ps
CPU time 9.46 seconds
Started Apr 25 02:34:27 PM PDT 24
Finished Apr 25 02:34:38 PM PDT 24
Peak memory 204132 kb
Host smart-5712a2e1-64f0-447b-b1a5-f9c30b5fd345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80443
4219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.804434219
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3708044911
Short name T1096
Test name
Test status
Simulation time 8395105610 ps
CPU time 8.37 seconds
Started Apr 25 02:34:26 PM PDT 24
Finished Apr 25 02:34:35 PM PDT 24
Peak memory 204140 kb
Host smart-bedd78f8-0ae5-4ee0-a464-457803d766c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37080
44911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3708044911
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.3248197392
Short name T831
Test name
Test status
Simulation time 8448234296 ps
CPU time 9.53 seconds
Started Apr 25 02:34:26 PM PDT 24
Finished Apr 25 02:34:36 PM PDT 24
Peak memory 204120 kb
Host smart-2c37d554-4727-43f4-a22f-6c07d19ae60a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32481
97392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.3248197392
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.817533420
Short name T985
Test name
Test status
Simulation time 8390411844 ps
CPU time 9.93 seconds
Started Apr 25 02:34:28 PM PDT 24
Finished Apr 25 02:34:39 PM PDT 24
Peak memory 204132 kb
Host smart-898387b2-31bb-4d17-a798-969200f81687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81753
3420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.817533420
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.3330476176
Short name T675
Test name
Test status
Simulation time 8410471225 ps
CPU time 7.53 seconds
Started Apr 25 02:34:26 PM PDT 24
Finished Apr 25 02:34:35 PM PDT 24
Peak memory 204028 kb
Host smart-dfdec361-136c-4a49-ba0e-f5f93e324950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33304
76176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.3330476176
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.max_length_in_transaction.4261347762
Short name T676
Test name
Test status
Simulation time 8517358446 ps
CPU time 7.81 seconds
Started Apr 25 02:34:40 PM PDT 24
Finished Apr 25 02:34:50 PM PDT 24
Peak memory 204124 kb
Host smart-1514836a-b799-4940-8614-35097bb798cf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4261347762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.4261347762
Directory /workspace/32.max_length_in_transaction/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.865037411
Short name T1059
Test name
Test status
Simulation time 8391714591 ps
CPU time 8.14 seconds
Started Apr 25 02:34:41 PM PDT 24
Finished Apr 25 02:34:51 PM PDT 24
Peak memory 204076 kb
Host smart-ad9cfaa1-aca9-4b95-8b30-4ccb45f79708
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=865037411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.865037411
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.random_length_in_trans.1977258202
Short name T705
Test name
Test status
Simulation time 8397131562 ps
CPU time 7.95 seconds
Started Apr 25 02:34:39 PM PDT 24
Finished Apr 25 02:34:49 PM PDT 24
Peak memory 204140 kb
Host smart-db5d07fa-1ff1-42fc-baf2-1272169ef4a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19772
58202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.1977258202
Directory /workspace/32.random_length_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2034996451
Short name T798
Test name
Test status
Simulation time 8394959486 ps
CPU time 7.97 seconds
Started Apr 25 02:34:30 PM PDT 24
Finished Apr 25 02:34:39 PM PDT 24
Peak memory 204044 kb
Host smart-f55339a7-5819-455d-9d31-0126c622cb98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20349
96451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2034996451
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_enable.610422210
Short name T811
Test name
Test status
Simulation time 8414489490 ps
CPU time 7.79 seconds
Started Apr 25 02:34:31 PM PDT 24
Finished Apr 25 02:34:41 PM PDT 24
Peak memory 204144 kb
Host smart-e1391320-e6f0-4b25-852f-52b5d80a6724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61042
2210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.610422210
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.456894358
Short name T50
Test name
Test status
Simulation time 62133762 ps
CPU time 1.6 seconds
Started Apr 25 02:34:34 PM PDT 24
Finished Apr 25 02:34:37 PM PDT 24
Peak memory 204144 kb
Host smart-1d63a712-7c66-4381-affd-963812e9f618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45689
4358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.456894358
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.778346641
Short name T424
Test name
Test status
Simulation time 8437176002 ps
CPU time 7.42 seconds
Started Apr 25 02:34:40 PM PDT 24
Finished Apr 25 02:34:50 PM PDT 24
Peak memory 204040 kb
Host smart-799d1c32-db25-4aa6-9c6c-c329eb5d4098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77834
6641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.778346641
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.3027515301
Short name T1312
Test name
Test status
Simulation time 8417406432 ps
CPU time 8.27 seconds
Started Apr 25 02:34:40 PM PDT 24
Finished Apr 25 02:34:52 PM PDT 24
Peak memory 204152 kb
Host smart-8a593e85-55b7-462e-8b0e-c8ef34518171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30275
15301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.3027515301
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.1991818097
Short name T694
Test name
Test status
Simulation time 8420120506 ps
CPU time 7.6 seconds
Started Apr 25 02:34:32 PM PDT 24
Finished Apr 25 02:34:42 PM PDT 24
Peak memory 204052 kb
Host smart-9ad671e3-9d91-4c62-a3c6-20d9199e100c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19918
18097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.1991818097
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.4294847574
Short name T1260
Test name
Test status
Simulation time 8417745379 ps
CPU time 8.58 seconds
Started Apr 25 02:34:30 PM PDT 24
Finished Apr 25 02:34:40 PM PDT 24
Peak memory 204112 kb
Host smart-92628d66-e05f-4350-a202-2a6be8458589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42948
47574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.4294847574
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.2067189514
Short name T604
Test name
Test status
Simulation time 8372223254 ps
CPU time 8.29 seconds
Started Apr 25 02:34:29 PM PDT 24
Finished Apr 25 02:34:39 PM PDT 24
Peak memory 204056 kb
Host smart-faa3a956-7954-44e5-9622-54e0df373acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20671
89514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.2067189514
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.453167794
Short name T1180
Test name
Test status
Simulation time 8448640365 ps
CPU time 7.58 seconds
Started Apr 25 02:34:31 PM PDT 24
Finished Apr 25 02:34:40 PM PDT 24
Peak memory 204116 kb
Host smart-7f9c1419-8a96-473c-b469-03bfc20f990e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45316
7794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.453167794
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.2735541587
Short name T688
Test name
Test status
Simulation time 8401679223 ps
CPU time 7.59 seconds
Started Apr 25 02:34:33 PM PDT 24
Finished Apr 25 02:34:43 PM PDT 24
Peak memory 204056 kb
Host smart-4413083c-dff4-4ae3-b0b1-09f775c9ccf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27355
41587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.2735541587
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.343631934
Short name T181
Test name
Test status
Simulation time 8411359106 ps
CPU time 7.56 seconds
Started Apr 25 02:34:50 PM PDT 24
Finished Apr 25 02:34:59 PM PDT 24
Peak memory 204060 kb
Host smart-50433d91-020f-47bd-9c1f-c1f41524dd87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34363
1934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.343631934
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.3171535894
Short name T799
Test name
Test status
Simulation time 8369884463 ps
CPU time 9.38 seconds
Started Apr 25 02:34:31 PM PDT 24
Finished Apr 25 02:34:41 PM PDT 24
Peak memory 204088 kb
Host smart-13969db5-cc2e-4350-baa4-514e7d2ba45f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31715
35894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.3171535894
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.681166011
Short name T1209
Test name
Test status
Simulation time 71168031 ps
CPU time 0.69 seconds
Started Apr 25 02:34:41 PM PDT 24
Finished Apr 25 02:34:44 PM PDT 24
Peak memory 204016 kb
Host smart-46f571ab-7c15-4f74-9758-a4aca0602f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68116
6011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.681166011
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.4182359573
Short name T231
Test name
Test status
Simulation time 27151118070 ps
CPU time 59.95 seconds
Started Apr 25 02:34:31 PM PDT 24
Finished Apr 25 02:35:32 PM PDT 24
Peak memory 204436 kb
Host smart-68899e4b-84e9-4f88-95f0-c1096b32d6d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41823
59573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.4182359573
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.3014602909
Short name T909
Test name
Test status
Simulation time 8408976648 ps
CPU time 8.23 seconds
Started Apr 25 02:34:31 PM PDT 24
Finished Apr 25 02:34:41 PM PDT 24
Peak memory 204064 kb
Host smart-f55578db-502d-49ee-875c-98bfaa0e365c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30146
02909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3014602909
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.2036521683
Short name T574
Test name
Test status
Simulation time 8421241096 ps
CPU time 8.18 seconds
Started Apr 25 02:34:32 PM PDT 24
Finished Apr 25 02:34:42 PM PDT 24
Peak memory 204128 kb
Host smart-92823ab5-c1db-4227-8ce6-e354e1ba54fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20365
21683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.2036521683
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.860610965
Short name T1165
Test name
Test status
Simulation time 8410013026 ps
CPU time 8.18 seconds
Started Apr 25 02:34:32 PM PDT 24
Finished Apr 25 02:34:43 PM PDT 24
Peak memory 204152 kb
Host smart-35c6364c-7b0e-45c4-abaf-5a91589265ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86061
0965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.860610965
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.3974082814
Short name T1201
Test name
Test status
Simulation time 8386285144 ps
CPU time 7.6 seconds
Started Apr 25 02:34:40 PM PDT 24
Finished Apr 25 02:34:50 PM PDT 24
Peak memory 204044 kb
Host smart-46ffacaf-f257-48f4-8c53-91b93d33d48f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39740
82814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.3974082814
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2766593606
Short name T762
Test name
Test status
Simulation time 8368219363 ps
CPU time 7.94 seconds
Started Apr 25 02:34:32 PM PDT 24
Finished Apr 25 02:34:42 PM PDT 24
Peak memory 204184 kb
Host smart-00300a84-320f-4681-9ecf-939ce62cdaa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27665
93606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2766593606
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.3036700179
Short name T659
Test name
Test status
Simulation time 8461789431 ps
CPU time 8.03 seconds
Started Apr 25 02:34:33 PM PDT 24
Finished Apr 25 02:34:43 PM PDT 24
Peak memory 204144 kb
Host smart-43c9f671-a630-43d4-85da-2fb5facb0184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30367
00179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.3036700179
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.3186135575
Short name T940
Test name
Test status
Simulation time 8387271156 ps
CPU time 9.33 seconds
Started Apr 25 02:34:32 PM PDT 24
Finished Apr 25 02:34:43 PM PDT 24
Peak memory 204140 kb
Host smart-a42141a2-e80b-4455-a2e0-ff357c6d04a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31861
35575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.3186135575
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.1846608632
Short name T1136
Test name
Test status
Simulation time 8416143285 ps
CPU time 10.22 seconds
Started Apr 25 02:34:32 PM PDT 24
Finished Apr 25 02:34:45 PM PDT 24
Peak memory 204080 kb
Host smart-b40bc96b-e8f8-4a3f-8b02-e8380caf44ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18466
08632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.1846608632
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.3761631802
Short name T138
Test name
Test status
Simulation time 8470068438 ps
CPU time 7.95 seconds
Started Apr 25 02:34:45 PM PDT 24
Finished Apr 25 02:34:54 PM PDT 24
Peak memory 204056 kb
Host smart-7bd9477a-40ab-4584-90f8-3b41864b60b5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3761631802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.3761631802
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.1139110822
Short name T399
Test name
Test status
Simulation time 8380477804 ps
CPU time 7.82 seconds
Started Apr 25 02:34:43 PM PDT 24
Finished Apr 25 02:34:53 PM PDT 24
Peak memory 204096 kb
Host smart-3d3bba4e-fa60-4e0c-85b3-5b8f70e4c36e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1139110822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.1139110822
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.2053125746
Short name T423
Test name
Test status
Simulation time 8427953087 ps
CPU time 7.79 seconds
Started Apr 25 02:34:48 PM PDT 24
Finished Apr 25 02:34:57 PM PDT 24
Peak memory 204140 kb
Host smart-e1eab5dd-016d-4158-b0af-a6dddb017e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20531
25746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.2053125746
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.4026909306
Short name T640
Test name
Test status
Simulation time 8404707933 ps
CPU time 7.6 seconds
Started Apr 25 02:34:41 PM PDT 24
Finished Apr 25 02:34:51 PM PDT 24
Peak memory 204116 kb
Host smart-58e5b523-e16c-41f8-af50-2166bf67ec39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40269
09306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.4026909306
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_enable.3422633300
Short name T1143
Test name
Test status
Simulation time 8387258242 ps
CPU time 7.65 seconds
Started Apr 25 02:34:39 PM PDT 24
Finished Apr 25 02:34:49 PM PDT 24
Peak memory 204120 kb
Host smart-15b3d56f-0dfa-4ced-84c3-322baceb6542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34226
33300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.3422633300
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.2768347730
Short name T87
Test name
Test status
Simulation time 90102035 ps
CPU time 1.19 seconds
Started Apr 25 02:34:40 PM PDT 24
Finished Apr 25 02:34:44 PM PDT 24
Peak memory 204240 kb
Host smart-19ee4274-0485-411c-9ad8-451d831e81e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27683
47730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2768347730
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.898170657
Short name T1380
Test name
Test status
Simulation time 8407422080 ps
CPU time 7.73 seconds
Started Apr 25 02:34:46 PM PDT 24
Finished Apr 25 02:34:55 PM PDT 24
Peak memory 204104 kb
Host smart-0245dbab-5d98-449a-b67e-f8fed7d72cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89817
0657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.898170657
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.805870272
Short name T197
Test name
Test status
Simulation time 8369975190 ps
CPU time 7.49 seconds
Started Apr 25 02:34:45 PM PDT 24
Finished Apr 25 02:34:54 PM PDT 24
Peak memory 204144 kb
Host smart-f9188c83-10db-4d7e-a9e6-f130e053c7ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80587
0272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.805870272
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.2758007440
Short name T551
Test name
Test status
Simulation time 8394517363 ps
CPU time 7.74 seconds
Started Apr 25 02:34:44 PM PDT 24
Finished Apr 25 02:34:54 PM PDT 24
Peak memory 204156 kb
Host smart-6eaa48ec-ba75-4252-bdf1-84f25cf20198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27580
07440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.2758007440
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1324030465
Short name T926
Test name
Test status
Simulation time 8418675584 ps
CPU time 10.34 seconds
Started Apr 25 02:34:40 PM PDT 24
Finished Apr 25 02:34:53 PM PDT 24
Peak memory 204100 kb
Host smart-d469a2cc-af7c-454c-80f6-2033bcf3f1c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13240
30465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1324030465
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.3703369473
Short name T377
Test name
Test status
Simulation time 8382218941 ps
CPU time 9.64 seconds
Started Apr 25 02:34:39 PM PDT 24
Finished Apr 25 02:34:52 PM PDT 24
Peak memory 204132 kb
Host smart-dd09e323-92f6-4479-b7dd-5617eb643372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37033
69473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.3703369473
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.1998322608
Short name T1044
Test name
Test status
Simulation time 8430654648 ps
CPU time 7.76 seconds
Started Apr 25 02:34:39 PM PDT 24
Finished Apr 25 02:34:50 PM PDT 24
Peak memory 204120 kb
Host smart-eedea896-b2a3-4cd4-9faa-389f131ab4e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19983
22608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.1998322608
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.4195958171
Short name T350
Test name
Test status
Simulation time 8418191671 ps
CPU time 8.25 seconds
Started Apr 25 02:34:39 PM PDT 24
Finished Apr 25 02:34:50 PM PDT 24
Peak memory 204132 kb
Host smart-8aacd9e0-c596-4c3c-aaa3-c7dabf33d97f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41959
58171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.4195958171
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.1413959017
Short name T1033
Test name
Test status
Simulation time 8451472338 ps
CPU time 8.38 seconds
Started Apr 25 02:34:39 PM PDT 24
Finished Apr 25 02:34:51 PM PDT 24
Peak memory 204140 kb
Host smart-8dc3d347-79ad-4661-a847-42b76d9d86a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14139
59017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.1413959017
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.1760741764
Short name T1292
Test name
Test status
Simulation time 8403475139 ps
CPU time 8.45 seconds
Started Apr 25 02:34:43 PM PDT 24
Finished Apr 25 02:34:54 PM PDT 24
Peak memory 204056 kb
Host smart-d8d1f88e-88eb-4bf2-9309-0d1bc4f3c310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17607
41764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.1760741764
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.2420698291
Short name T330
Test name
Test status
Simulation time 8392742589 ps
CPU time 7.7 seconds
Started Apr 25 02:34:45 PM PDT 24
Finished Apr 25 02:34:55 PM PDT 24
Peak memory 204108 kb
Host smart-68d79b25-fe69-45fe-8923-444ed3790165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24206
98291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.2420698291
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.2937942530
Short name T652
Test name
Test status
Simulation time 39624990 ps
CPU time 0.65 seconds
Started Apr 25 02:34:56 PM PDT 24
Finished Apr 25 02:34:57 PM PDT 24
Peak memory 203960 kb
Host smart-0539b3dc-a347-49ca-a113-114b8e934302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29379
42530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.2937942530
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.189937413
Short name T770
Test name
Test status
Simulation time 23221994066 ps
CPU time 45.14 seconds
Started Apr 25 02:34:39 PM PDT 24
Finished Apr 25 02:35:25 PM PDT 24
Peak memory 204444 kb
Host smart-e48f4a1b-9232-41a7-8de7-7613bc23015a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18993
7413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.189937413
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.2644394495
Short name T445
Test name
Test status
Simulation time 8433687525 ps
CPU time 8.28 seconds
Started Apr 25 02:34:44 PM PDT 24
Finished Apr 25 02:34:54 PM PDT 24
Peak memory 204148 kb
Host smart-403d34ad-e17f-4329-9bac-4318b8fb094f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26443
94495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.2644394495
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2803921444
Short name T624
Test name
Test status
Simulation time 8436358809 ps
CPU time 8.93 seconds
Started Apr 25 02:34:37 PM PDT 24
Finished Apr 25 02:34:47 PM PDT 24
Peak memory 204116 kb
Host smart-4f3a1782-6517-43ca-8c70-fe62983a39e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28039
21444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2803921444
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.409516815
Short name T227
Test name
Test status
Simulation time 8406354324 ps
CPU time 8.5 seconds
Started Apr 25 02:34:40 PM PDT 24
Finished Apr 25 02:34:51 PM PDT 24
Peak memory 204140 kb
Host smart-cf16291e-2009-4f1a-a5b3-6c796731e083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40951
6815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.409516815
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.2655236460
Short name T493
Test name
Test status
Simulation time 8392585262 ps
CPU time 8.5 seconds
Started Apr 25 02:34:50 PM PDT 24
Finished Apr 25 02:35:00 PM PDT 24
Peak memory 204100 kb
Host smart-d3cb283c-3e9d-42e1-a971-f46390c4a269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26552
36460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.2655236460
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.3993377289
Short name T4
Test name
Test status
Simulation time 8365694444 ps
CPU time 8.02 seconds
Started Apr 25 02:34:48 PM PDT 24
Finished Apr 25 02:34:58 PM PDT 24
Peak memory 204144 kb
Host smart-386a4ee2-0ee3-4468-a233-e6c3a8a2bc8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39933
77289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3993377289
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.3917624920
Short name T1138
Test name
Test status
Simulation time 8510949930 ps
CPU time 7.95 seconds
Started Apr 25 02:34:42 PM PDT 24
Finished Apr 25 02:34:52 PM PDT 24
Peak memory 204144 kb
Host smart-ada95c0a-01f4-4498-81fd-7bd8eaa87708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39176
24920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.3917624920
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.3298295143
Short name T373
Test name
Test status
Simulation time 8375952920 ps
CPU time 8.98 seconds
Started Apr 25 02:34:45 PM PDT 24
Finished Apr 25 02:34:56 PM PDT 24
Peak memory 204124 kb
Host smart-e378cbcd-a412-4c41-a1cd-ff803f4af74a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32982
95143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.3298295143
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.897440888
Short name T956
Test name
Test status
Simulation time 8378488344 ps
CPU time 8.33 seconds
Started Apr 25 02:34:56 PM PDT 24
Finished Apr 25 02:35:05 PM PDT 24
Peak memory 204092 kb
Host smart-e4cbf6d2-be5c-44bc-a7d7-97fbb874196c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89744
0888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.897440888
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.3616140292
Short name T39
Test name
Test status
Simulation time 8466693414 ps
CPU time 7.49 seconds
Started Apr 25 02:34:50 PM PDT 24
Finished Apr 25 02:34:59 PM PDT 24
Peak memory 204096 kb
Host smart-46cc1992-124f-4698-851f-88f1bc55e4d9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3616140292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.3616140292
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.578923879
Short name T1046
Test name
Test status
Simulation time 8398938987 ps
CPU time 7.71 seconds
Started Apr 25 02:34:52 PM PDT 24
Finished Apr 25 02:35:01 PM PDT 24
Peak memory 204116 kb
Host smart-e4f19d53-c285-4a90-8471-d69acf4f289f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=578923879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.578923879
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.1690088375
Short name T500
Test name
Test status
Simulation time 8397237845 ps
CPU time 8.15 seconds
Started Apr 25 02:34:50 PM PDT 24
Finished Apr 25 02:35:00 PM PDT 24
Peak memory 204040 kb
Host smart-64caf7b0-c836-450a-bc9f-9a0e51ed01a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16900
88375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.1690088375
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.1585851694
Short name T1244
Test name
Test status
Simulation time 8404355971 ps
CPU time 7.68 seconds
Started Apr 25 02:34:46 PM PDT 24
Finished Apr 25 02:34:55 PM PDT 24
Peak memory 204088 kb
Host smart-57528c95-001b-4a9d-8efb-5676c452ee77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15858
51694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.1585851694
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_enable.1360073617
Short name T1301
Test name
Test status
Simulation time 8374885730 ps
CPU time 7.29 seconds
Started Apr 25 02:34:47 PM PDT 24
Finished Apr 25 02:34:56 PM PDT 24
Peak memory 204020 kb
Host smart-8f584fc8-b411-49bf-abb6-672aefcd9c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13600
73617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.1360073617
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.3033585854
Short name T927
Test name
Test status
Simulation time 132522809 ps
CPU time 1.22 seconds
Started Apr 25 02:34:56 PM PDT 24
Finished Apr 25 02:34:58 PM PDT 24
Peak memory 204232 kb
Host smart-d7bd69ab-82ad-4237-b461-5fd3a7e9bd1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30335
85854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.3033585854
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.836948975
Short name T458
Test name
Test status
Simulation time 8397632497 ps
CPU time 7.68 seconds
Started Apr 25 02:34:51 PM PDT 24
Finished Apr 25 02:35:00 PM PDT 24
Peak memory 204148 kb
Host smart-f29fa93c-be32-4423-add6-b667a73ca047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83694
8975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.836948975
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.1564815266
Short name T204
Test name
Test status
Simulation time 8389614324 ps
CPU time 8.66 seconds
Started Apr 25 02:34:50 PM PDT 24
Finished Apr 25 02:35:00 PM PDT 24
Peak memory 204136 kb
Host smart-eae6861b-cb94-4da9-b959-218c636d1394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15648
15266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.1564815266
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.4116954462
Short name T1181
Test name
Test status
Simulation time 8454475315 ps
CPU time 7.94 seconds
Started Apr 25 02:34:45 PM PDT 24
Finished Apr 25 02:34:55 PM PDT 24
Peak memory 204140 kb
Host smart-e3076889-ac7f-4034-86f7-ad28e0c01ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41169
54462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.4116954462
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.4114597821
Short name T1087
Test name
Test status
Simulation time 8420367863 ps
CPU time 8.24 seconds
Started Apr 25 02:34:46 PM PDT 24
Finished Apr 25 02:34:56 PM PDT 24
Peak memory 204120 kb
Host smart-f79dd458-7607-4db4-833d-8415cba0fb8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41145
97821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.4114597821
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.2709792392
Short name T577
Test name
Test status
Simulation time 8370336712 ps
CPU time 9.61 seconds
Started Apr 25 02:34:56 PM PDT 24
Finished Apr 25 02:35:07 PM PDT 24
Peak memory 204088 kb
Host smart-71bfa256-7798-4e10-82c6-f292b0362fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27097
92392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.2709792392
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.2812162865
Short name T118
Test name
Test status
Simulation time 8426366741 ps
CPU time 7.92 seconds
Started Apr 25 02:34:56 PM PDT 24
Finished Apr 25 02:35:05 PM PDT 24
Peak memory 204092 kb
Host smart-b2e9aab1-1f56-490f-875a-b17d469910a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28121
62865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2812162865
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2433322821
Short name T232
Test name
Test status
Simulation time 8375752625 ps
CPU time 9.16 seconds
Started Apr 25 02:34:49 PM PDT 24
Finished Apr 25 02:34:59 PM PDT 24
Peak memory 204152 kb
Host smart-2cc3ff0b-c181-4b72-9f68-c348651aadcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24333
22821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2433322821
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.271489597
Short name T745
Test name
Test status
Simulation time 8495900598 ps
CPU time 8.01 seconds
Started Apr 25 02:34:56 PM PDT 24
Finished Apr 25 02:35:05 PM PDT 24
Peak memory 204088 kb
Host smart-c005baa6-ca03-4de2-96b8-365107b99f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27148
9597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.271489597
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.3807387452
Short name T933
Test name
Test status
Simulation time 8406892391 ps
CPU time 8.46 seconds
Started Apr 25 02:34:51 PM PDT 24
Finished Apr 25 02:35:02 PM PDT 24
Peak memory 204100 kb
Host smart-10a43a8e-1efd-4121-9c9a-dc1de2bf5183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38073
87452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.3807387452
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.3261458528
Short name T340
Test name
Test status
Simulation time 8367219188 ps
CPU time 7.39 seconds
Started Apr 25 02:34:50 PM PDT 24
Finished Apr 25 02:35:00 PM PDT 24
Peak memory 204140 kb
Host smart-d6f509d1-b8a4-4782-8115-f3cc30613260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32614
58528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.3261458528
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3556858675
Short name T1220
Test name
Test status
Simulation time 44706999 ps
CPU time 0.68 seconds
Started Apr 25 02:34:51 PM PDT 24
Finished Apr 25 02:34:53 PM PDT 24
Peak memory 203980 kb
Host smart-b4a7c90d-3b9b-479f-bbc7-3d5ac1f6181f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35568
58675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3556858675
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.2786040371
Short name T977
Test name
Test status
Simulation time 24121599708 ps
CPU time 43.62 seconds
Started Apr 25 02:34:48 PM PDT 24
Finished Apr 25 02:35:33 PM PDT 24
Peak memory 204400 kb
Host smart-8a0154b4-46de-4166-a8b5-940b422e65fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27860
40371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.2786040371
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.3423592261
Short name T1173
Test name
Test status
Simulation time 8371196124 ps
CPU time 7.89 seconds
Started Apr 25 02:34:44 PM PDT 24
Finished Apr 25 02:34:54 PM PDT 24
Peak memory 204148 kb
Host smart-4c48abb7-8048-414c-9665-4b5cb85ae6f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34235
92261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.3423592261
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.59418627
Short name T700
Test name
Test status
Simulation time 8450364802 ps
CPU time 9.53 seconds
Started Apr 25 02:34:51 PM PDT 24
Finished Apr 25 02:35:03 PM PDT 24
Peak memory 204068 kb
Host smart-ef090528-0640-4548-ad04-1802de5754c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59418
627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.59418627
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.418310544
Short name T429
Test name
Test status
Simulation time 8403946070 ps
CPU time 9.06 seconds
Started Apr 25 02:34:50 PM PDT 24
Finished Apr 25 02:35:01 PM PDT 24
Peak memory 204028 kb
Host smart-bbf4b068-96a9-48f9-a80a-b792c891b253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41831
0544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.418310544
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.4076546770
Short name T763
Test name
Test status
Simulation time 8429595075 ps
CPU time 7.7 seconds
Started Apr 25 02:34:50 PM PDT 24
Finished Apr 25 02:35:00 PM PDT 24
Peak memory 204052 kb
Host smart-436f2534-7ebc-4436-a911-99e0e5d56c73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40765
46770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.4076546770
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.3576919838
Short name T817
Test name
Test status
Simulation time 8409492947 ps
CPU time 7.44 seconds
Started Apr 25 02:34:51 PM PDT 24
Finished Apr 25 02:35:01 PM PDT 24
Peak memory 204140 kb
Host smart-da6be7a2-c78a-4923-870b-e8f17026b881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35769
19838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.3576919838
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.2102212575
Short name T470
Test name
Test status
Simulation time 8451956009 ps
CPU time 7.94 seconds
Started Apr 25 02:34:45 PM PDT 24
Finished Apr 25 02:34:54 PM PDT 24
Peak memory 204144 kb
Host smart-39989073-4c3d-47bb-a7ba-124d709bd443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21022
12575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2102212575
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.3373923933
Short name T452
Test name
Test status
Simulation time 8375377769 ps
CPU time 7.61 seconds
Started Apr 25 02:34:51 PM PDT 24
Finished Apr 25 02:35:01 PM PDT 24
Peak memory 204128 kb
Host smart-2d8b35b4-5d16-4baa-a75c-bd189107aed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33739
23933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.3373923933
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.1916177872
Short name T864
Test name
Test status
Simulation time 8390367378 ps
CPU time 7.4 seconds
Started Apr 25 02:34:50 PM PDT 24
Finished Apr 25 02:35:00 PM PDT 24
Peak memory 204140 kb
Host smart-90d26bc5-7c53-4b84-85fc-0582aa198170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19161
77872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.1916177872
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.3902851872
Short name T1231
Test name
Test status
Simulation time 8488571876 ps
CPU time 8.28 seconds
Started Apr 25 02:34:56 PM PDT 24
Finished Apr 25 02:35:05 PM PDT 24
Peak memory 204128 kb
Host smart-b5797256-1d1f-4745-8899-973f45a81fc9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3902851872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.3902851872
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.1460755323
Short name T346
Test name
Test status
Simulation time 8388808928 ps
CPU time 8.57 seconds
Started Apr 25 02:34:56 PM PDT 24
Finished Apr 25 02:35:05 PM PDT 24
Peak memory 204148 kb
Host smart-a5c4f03a-7fac-4eba-b7cb-952f3f1aa21d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1460755323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.1460755323
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.1559871607
Short name T1328
Test name
Test status
Simulation time 8427899129 ps
CPU time 9.23 seconds
Started Apr 25 02:35:01 PM PDT 24
Finished Apr 25 02:35:11 PM PDT 24
Peak memory 204136 kb
Host smart-750a683e-61c6-4c28-8eef-73d0dbe1a629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15598
71607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.1559871607
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.3236785568
Short name T710
Test name
Test status
Simulation time 8382220763 ps
CPU time 7.9 seconds
Started Apr 25 02:34:51 PM PDT 24
Finished Apr 25 02:35:00 PM PDT 24
Peak memory 204108 kb
Host smart-59c4f081-c9b2-4b59-81a5-9397b6d2df15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32367
85568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.3236785568
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1068546380
Short name T218
Test name
Test status
Simulation time 54620933 ps
CPU time 1.11 seconds
Started Apr 25 02:34:51 PM PDT 24
Finished Apr 25 02:34:54 PM PDT 24
Peak memory 204088 kb
Host smart-7c46679f-c4d7-4b2e-ae2e-0247f849eb6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10685
46380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1068546380
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.321470737
Short name T155
Test name
Test status
Simulation time 8398957303 ps
CPU time 7.84 seconds
Started Apr 25 02:35:03 PM PDT 24
Finished Apr 25 02:35:11 PM PDT 24
Peak memory 204060 kb
Host smart-56d50bb8-2949-4c33-b33f-c4d1e7d167ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32147
0737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.321470737
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.1367100562
Short name T205
Test name
Test status
Simulation time 8368182393 ps
CPU time 7.81 seconds
Started Apr 25 02:34:57 PM PDT 24
Finished Apr 25 02:35:06 PM PDT 24
Peak memory 204120 kb
Host smart-ed97f5bb-215c-4044-8461-3af92fee8d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13671
00562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.1367100562
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.2928072090
Short name T235
Test name
Test status
Simulation time 8425587462 ps
CPU time 8.88 seconds
Started Apr 25 02:34:52 PM PDT 24
Finished Apr 25 02:35:03 PM PDT 24
Peak memory 204096 kb
Host smart-703cd781-ad01-4c69-bc88-35a2ffbb4e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29280
72090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2928072090
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.4136856081
Short name T442
Test name
Test status
Simulation time 8416533568 ps
CPU time 8 seconds
Started Apr 25 02:34:50 PM PDT 24
Finished Apr 25 02:35:00 PM PDT 24
Peak memory 204156 kb
Host smart-8b056210-c344-41ca-bb9d-6c94108afe58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41368
56081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.4136856081
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2376171432
Short name T582
Test name
Test status
Simulation time 8371673786 ps
CPU time 8.34 seconds
Started Apr 25 02:34:49 PM PDT 24
Finished Apr 25 02:34:59 PM PDT 24
Peak memory 204156 kb
Host smart-e0a2bedd-e224-4b12-b1dd-bee0d469633a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23761
71432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2376171432
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2759551352
Short name T121
Test name
Test status
Simulation time 8415988156 ps
CPU time 8.35 seconds
Started Apr 25 02:34:51 PM PDT 24
Finished Apr 25 02:35:01 PM PDT 24
Peak memory 204128 kb
Host smart-d7b38966-f211-4db8-9a8b-144209d5cebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27595
51352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2759551352
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.1143715052
Short name T848
Test name
Test status
Simulation time 8506218037 ps
CPU time 7.63 seconds
Started Apr 25 02:34:49 PM PDT 24
Finished Apr 25 02:34:58 PM PDT 24
Peak memory 204044 kb
Host smart-0974137c-87ce-4001-ae9f-0c0c40b785ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11437
15052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.1143715052
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.3517563553
Short name T469
Test name
Test status
Simulation time 8372743857 ps
CPU time 7.88 seconds
Started Apr 25 02:34:49 PM PDT 24
Finished Apr 25 02:34:59 PM PDT 24
Peak memory 204156 kb
Host smart-31f6c0c8-26fe-45b7-a288-d4c3b5fb54c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35175
63553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.3517563553
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.3546354139
Short name T1303
Test name
Test status
Simulation time 8377458728 ps
CPU time 8.88 seconds
Started Apr 25 02:34:57 PM PDT 24
Finished Apr 25 02:35:07 PM PDT 24
Peak memory 204044 kb
Host smart-ee22f2a0-7a5f-43b6-b579-a007df8268fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35463
54139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.3546354139
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2880362139
Short name T1348
Test name
Test status
Simulation time 31700732 ps
CPU time 0.65 seconds
Started Apr 25 02:34:58 PM PDT 24
Finished Apr 25 02:35:00 PM PDT 24
Peak memory 204032 kb
Host smart-0af143e7-360b-458f-b49a-db436c4f5cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28803
62139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2880362139
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.237278149
Short name T880
Test name
Test status
Simulation time 16146429853 ps
CPU time 29.45 seconds
Started Apr 25 02:34:51 PM PDT 24
Finished Apr 25 02:35:22 PM PDT 24
Peak memory 204392 kb
Host smart-9a788258-eb6b-49ae-a8b0-f267f815b67c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23727
8149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.237278149
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.1285546466
Short name T572
Test name
Test status
Simulation time 8377664305 ps
CPU time 8.99 seconds
Started Apr 25 02:34:57 PM PDT 24
Finished Apr 25 02:35:07 PM PDT 24
Peak memory 204092 kb
Host smart-c9510fc5-96aa-4bb1-b759-41a75bc2b437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12855
46466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.1285546466
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.3767484010
Short name T797
Test name
Test status
Simulation time 8388842105 ps
CPU time 7.51 seconds
Started Apr 25 02:35:12 PM PDT 24
Finished Apr 25 02:35:21 PM PDT 24
Peak memory 204108 kb
Host smart-40700b57-e6c5-4c69-a58a-0c7e4b4a21d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37674
84010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3767484010
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.321637695
Short name T858
Test name
Test status
Simulation time 8417800135 ps
CPU time 7.87 seconds
Started Apr 25 02:34:58 PM PDT 24
Finished Apr 25 02:35:08 PM PDT 24
Peak memory 204148 kb
Host smart-acbd3b3a-040a-4e40-9d79-21bbf0eb8df8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32163
7695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.321637695
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.1079112332
Short name T1011
Test name
Test status
Simulation time 8378451110 ps
CPU time 7.86 seconds
Started Apr 25 02:34:58 PM PDT 24
Finished Apr 25 02:35:07 PM PDT 24
Peak memory 204052 kb
Host smart-d0736966-7284-4f3f-8ac3-baefde823fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10791
12332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.1079112332
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.3374698577
Short name T552
Test name
Test status
Simulation time 8376980665 ps
CPU time 10.43 seconds
Started Apr 25 02:34:56 PM PDT 24
Finished Apr 25 02:35:08 PM PDT 24
Peak memory 204116 kb
Host smart-04cac83c-60f9-4be9-9bfd-e28bec5961a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33746
98577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3374698577
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.1769692502
Short name T432
Test name
Test status
Simulation time 8462986517 ps
CPU time 9.26 seconds
Started Apr 25 02:34:51 PM PDT 24
Finished Apr 25 02:35:02 PM PDT 24
Peak memory 204024 kb
Host smart-ac41df9f-f1f2-4c79-8d2b-2bf7fe5468cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17696
92502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.1769692502
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.4252217083
Short name T402
Test name
Test status
Simulation time 8428375458 ps
CPU time 7.82 seconds
Started Apr 25 02:34:57 PM PDT 24
Finished Apr 25 02:35:06 PM PDT 24
Peak memory 204140 kb
Host smart-d2542f03-96c0-4851-afc1-33261bb96daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42522
17083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.4252217083
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.3658125689
Short name T1199
Test name
Test status
Simulation time 8378229456 ps
CPU time 7.32 seconds
Started Apr 25 02:34:57 PM PDT 24
Finished Apr 25 02:35:05 PM PDT 24
Peak memory 204124 kb
Host smart-3c2b19d6-35b0-425a-9786-272856d2b9c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36581
25689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.3658125689
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.1807837289
Short name T961
Test name
Test status
Simulation time 8492044174 ps
CPU time 7.79 seconds
Started Apr 25 02:35:05 PM PDT 24
Finished Apr 25 02:35:14 PM PDT 24
Peak memory 204120 kb
Host smart-c095ae36-d5e2-49a3-a600-a141086ba59d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1807837289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.1807837289
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.2218235929
Short name T1267
Test name
Test status
Simulation time 8377345307 ps
CPU time 7.73 seconds
Started Apr 25 02:35:03 PM PDT 24
Finished Apr 25 02:35:12 PM PDT 24
Peak memory 204148 kb
Host smart-771bd57c-cfc4-4ad9-a162-8e2a567695c0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2218235929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.2218235929
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.4139188250
Short name T610
Test name
Test status
Simulation time 8462015444 ps
CPU time 8.53 seconds
Started Apr 25 02:35:07 PM PDT 24
Finished Apr 25 02:35:17 PM PDT 24
Peak memory 204160 kb
Host smart-1d3be8d8-9bd1-47aa-b73a-f13d4fc0521c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41391
88250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.4139188250
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.1904774390
Short name T387
Test name
Test status
Simulation time 8387976261 ps
CPU time 8.49 seconds
Started Apr 25 02:35:01 PM PDT 24
Finished Apr 25 02:35:10 PM PDT 24
Peak memory 204148 kb
Host smart-a0833ea4-ce4d-4b2e-a136-b7a221c64757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19047
74390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1904774390
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_enable.2821359379
Short name T417
Test name
Test status
Simulation time 8428731985 ps
CPU time 7.98 seconds
Started Apr 25 02:34:58 PM PDT 24
Finished Apr 25 02:35:07 PM PDT 24
Peak memory 204160 kb
Host smart-8aed77ef-20bc-4944-973a-d52743788790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28213
59379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.2821359379
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1968600686
Short name T68
Test name
Test status
Simulation time 167382624 ps
CPU time 1.87 seconds
Started Apr 25 02:34:55 PM PDT 24
Finished Apr 25 02:34:57 PM PDT 24
Peak memory 204180 kb
Host smart-726fee65-801b-42d6-a337-d8f295352925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19686
00686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1968600686
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.2283542462
Short name T521
Test name
Test status
Simulation time 8420712486 ps
CPU time 8.6 seconds
Started Apr 25 02:35:05 PM PDT 24
Finished Apr 25 02:35:14 PM PDT 24
Peak memory 204048 kb
Host smart-d65fa91e-33ea-4510-8ea2-2f0d3c4b0fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22835
42462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.2283542462
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.4033136073
Short name T7
Test name
Test status
Simulation time 8391526278 ps
CPU time 7.77 seconds
Started Apr 25 02:35:06 PM PDT 24
Finished Apr 25 02:35:15 PM PDT 24
Peak memory 204124 kb
Host smart-bb189711-beed-4d0f-8559-81660a88696c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40331
36073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.4033136073
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.1088623926
Short name T1025
Test name
Test status
Simulation time 8407656273 ps
CPU time 9.17 seconds
Started Apr 25 02:34:59 PM PDT 24
Finished Apr 25 02:35:09 PM PDT 24
Peak memory 204016 kb
Host smart-9fb1c718-a701-4b74-9410-9b9251785c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10886
23926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.1088623926
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.2470693280
Short name T647
Test name
Test status
Simulation time 8411813886 ps
CPU time 7.93 seconds
Started Apr 25 02:34:59 PM PDT 24
Finished Apr 25 02:35:08 PM PDT 24
Peak memory 204080 kb
Host smart-11479018-a7b6-439f-bb72-4dcc396e7232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24706
93280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2470693280
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.3272854733
Short name T1024
Test name
Test status
Simulation time 8374459622 ps
CPU time 8.72 seconds
Started Apr 25 02:34:59 PM PDT 24
Finished Apr 25 02:35:09 PM PDT 24
Peak memory 204032 kb
Host smart-7949def8-c095-4815-a63d-d579159a71b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32728
54733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.3272854733
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.957964000
Short name T114
Test name
Test status
Simulation time 8442238749 ps
CPU time 8 seconds
Started Apr 25 02:35:05 PM PDT 24
Finished Apr 25 02:35:15 PM PDT 24
Peak memory 204116 kb
Host smart-4792f369-46c7-4f8e-8809-a788c7b080b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95796
4000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.957964000
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3773263339
Short name T382
Test name
Test status
Simulation time 8389524149 ps
CPU time 7.5 seconds
Started Apr 25 02:35:03 PM PDT 24
Finished Apr 25 02:35:11 PM PDT 24
Peak memory 204104 kb
Host smart-62f209c5-c457-44d0-a162-88bdabbe1ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37732
63339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3773263339
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.497020743
Short name T1147
Test name
Test status
Simulation time 8402058274 ps
CPU time 10.13 seconds
Started Apr 25 02:35:05 PM PDT 24
Finished Apr 25 02:35:17 PM PDT 24
Peak memory 204112 kb
Host smart-3e45943c-f296-4d52-8135-2de28e6fd5a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49702
0743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.497020743
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.2726364735
Short name T895
Test name
Test status
Simulation time 8417253161 ps
CPU time 8.03 seconds
Started Apr 25 02:35:05 PM PDT 24
Finished Apr 25 02:35:14 PM PDT 24
Peak memory 204100 kb
Host smart-2d2a08d8-a8f2-49e2-a3d1-806597a49451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27263
64735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.2726364735
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.3997528393
Short name T865
Test name
Test status
Simulation time 8388686140 ps
CPU time 9.97 seconds
Started Apr 25 02:35:07 PM PDT 24
Finished Apr 25 02:35:18 PM PDT 24
Peak memory 204092 kb
Host smart-1a02d7ff-ea36-4868-a948-50d9e022a641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39975
28393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.3997528393
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.410885933
Short name T1090
Test name
Test status
Simulation time 32807425 ps
CPU time 0.64 seconds
Started Apr 25 02:35:05 PM PDT 24
Finished Apr 25 02:35:07 PM PDT 24
Peak memory 204016 kb
Host smart-ea037fee-faa4-491b-8bcc-b3d05d375144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41088
5933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.410885933
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3842732973
Short name T260
Test name
Test status
Simulation time 29480274630 ps
CPU time 57.06 seconds
Started Apr 25 02:35:03 PM PDT 24
Finished Apr 25 02:36:01 PM PDT 24
Peak memory 204328 kb
Host smart-6dbfa42b-8502-4801-81e1-2f03097d29bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38427
32973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3842732973
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3480023055
Short name T1163
Test name
Test status
Simulation time 8408235526 ps
CPU time 7.71 seconds
Started Apr 25 02:35:11 PM PDT 24
Finished Apr 25 02:35:19 PM PDT 24
Peak memory 204088 kb
Host smart-053219a1-29ea-47df-9410-3b6bff208bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34800
23055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3480023055
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.2534367660
Short name T666
Test name
Test status
Simulation time 8409777303 ps
CPU time 9.38 seconds
Started Apr 25 02:35:06 PM PDT 24
Finished Apr 25 02:35:17 PM PDT 24
Peak memory 204072 kb
Host smart-922ba07a-db5e-401c-a414-ae2df0a30850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25343
67660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.2534367660
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.911654422
Short name T562
Test name
Test status
Simulation time 8380107696 ps
CPU time 7.59 seconds
Started Apr 25 02:35:03 PM PDT 24
Finished Apr 25 02:35:11 PM PDT 24
Peak memory 204132 kb
Host smart-48dd6e10-95d6-4f7d-80d0-800a4df112e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91165
4422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.911654422
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.3937046054
Short name T513
Test name
Test status
Simulation time 8376820842 ps
CPU time 8.09 seconds
Started Apr 25 02:35:10 PM PDT 24
Finished Apr 25 02:35:19 PM PDT 24
Peak memory 204088 kb
Host smart-b8e35f45-cf0a-4dcc-b73c-6cdb2f4193be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39370
46054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.3937046054
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1580306376
Short name T606
Test name
Test status
Simulation time 8393364861 ps
CPU time 9.55 seconds
Started Apr 25 02:35:05 PM PDT 24
Finished Apr 25 02:35:16 PM PDT 24
Peak memory 204108 kb
Host smart-3c437b74-6a1b-432c-a1c3-4269064cf8f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15803
06376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1580306376
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.498296810
Short name T663
Test name
Test status
Simulation time 8467117016 ps
CPU time 7.95 seconds
Started Apr 25 02:34:59 PM PDT 24
Finished Apr 25 02:35:09 PM PDT 24
Peak memory 204020 kb
Host smart-5b1bab5c-5950-4587-ab35-69ee5ef1293b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49829
6810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.498296810
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.2716964752
Short name T1083
Test name
Test status
Simulation time 8404524756 ps
CPU time 7.94 seconds
Started Apr 25 02:35:04 PM PDT 24
Finished Apr 25 02:35:12 PM PDT 24
Peak memory 204128 kb
Host smart-c4a24901-4a1a-446f-b6fd-05aca2167da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27169
64752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.2716964752
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.2356046534
Short name T976
Test name
Test status
Simulation time 8408332829 ps
CPU time 9.52 seconds
Started Apr 25 02:35:04 PM PDT 24
Finished Apr 25 02:35:14 PM PDT 24
Peak memory 204016 kb
Host smart-483de32f-e20a-4fbf-a24c-ceabd21d0b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23560
46534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.2356046534
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.2498147270
Short name T751
Test name
Test status
Simulation time 8479847272 ps
CPU time 8.61 seconds
Started Apr 25 02:35:20 PM PDT 24
Finished Apr 25 02:35:30 PM PDT 24
Peak memory 204076 kb
Host smart-39374354-9b52-4b89-abea-9ce8cf3e29fa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2498147270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.2498147270
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.2465043578
Short name T790
Test name
Test status
Simulation time 8387662444 ps
CPU time 8.81 seconds
Started Apr 25 02:35:19 PM PDT 24
Finished Apr 25 02:35:29 PM PDT 24
Peak memory 204056 kb
Host smart-83215bff-80be-436a-91ef-6f90e2c2dd34
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2465043578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.2465043578
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.random_length_in_trans.1868874310
Short name T636
Test name
Test status
Simulation time 8449684667 ps
CPU time 10.09 seconds
Started Apr 25 02:35:20 PM PDT 24
Finished Apr 25 02:35:31 PM PDT 24
Peak memory 204040 kb
Host smart-0eb7cd8e-d120-49a2-abf0-91ff83443e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18688
74310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.1868874310
Directory /workspace/37.random_length_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3570263807
Short name T525
Test name
Test status
Simulation time 8434254805 ps
CPU time 7.78 seconds
Started Apr 25 02:35:11 PM PDT 24
Finished Apr 25 02:35:20 PM PDT 24
Peak memory 204124 kb
Host smart-fc4fd83d-a9ad-4172-b799-486b2c03ecee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35702
63807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3570263807
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_enable.1202505570
Short name T430
Test name
Test status
Simulation time 8370035065 ps
CPU time 7.63 seconds
Started Apr 25 02:35:10 PM PDT 24
Finished Apr 25 02:35:19 PM PDT 24
Peak memory 204128 kb
Host smart-309ad557-502f-45b2-a727-09efda95071e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12025
05570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.1202505570
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.451591278
Short name T233
Test name
Test status
Simulation time 167386190 ps
CPU time 1.81 seconds
Started Apr 25 02:35:13 PM PDT 24
Finished Apr 25 02:35:16 PM PDT 24
Peak memory 204264 kb
Host smart-c1562dfe-e25f-49ec-9831-8959744d2ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45159
1278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.451591278
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3234102052
Short name T149
Test name
Test status
Simulation time 8393338237 ps
CPU time 7.79 seconds
Started Apr 25 02:35:19 PM PDT 24
Finished Apr 25 02:35:28 PM PDT 24
Peak memory 204120 kb
Host smart-ab8d0c3a-78a0-4c58-85e0-55437fe3a7eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32341
02052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3234102052
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.3894671695
Short name T1127
Test name
Test status
Simulation time 8370817440 ps
CPU time 9.35 seconds
Started Apr 25 02:35:21 PM PDT 24
Finished Apr 25 02:35:32 PM PDT 24
Peak memory 204120 kb
Host smart-bdb532b1-c8d0-428e-a670-4bf3cc21d96c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38946
71695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.3894671695
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.1703110269
Short name T861
Test name
Test status
Simulation time 8421560854 ps
CPU time 7.69 seconds
Started Apr 25 02:35:19 PM PDT 24
Finished Apr 25 02:35:27 PM PDT 24
Peak memory 204140 kb
Host smart-928ad4b9-3206-4dda-8590-5a29bfc87fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17031
10269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.1703110269
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1247054805
Short name T843
Test name
Test status
Simulation time 8427785648 ps
CPU time 8.79 seconds
Started Apr 25 02:35:10 PM PDT 24
Finished Apr 25 02:35:20 PM PDT 24
Peak memory 204140 kb
Host smart-81e214b7-5f7d-44ef-913e-204876055f0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12470
54805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1247054805
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.525263440
Short name T395
Test name
Test status
Simulation time 8368646420 ps
CPU time 7.62 seconds
Started Apr 25 02:35:13 PM PDT 24
Finished Apr 25 02:35:22 PM PDT 24
Peak memory 204140 kb
Host smart-d3444656-0963-4817-b340-158f614d308a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52526
3440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.525263440
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.615358472
Short name T1039
Test name
Test status
Simulation time 8451997489 ps
CPU time 7.49 seconds
Started Apr 25 02:35:13 PM PDT 24
Finished Apr 25 02:35:22 PM PDT 24
Peak memory 204120 kb
Host smart-62615854-06d7-4efc-855b-d0b624b64925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61535
8472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.615358472
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.3781353541
Short name T651
Test name
Test status
Simulation time 8397923736 ps
CPU time 8.52 seconds
Started Apr 25 02:35:10 PM PDT 24
Finished Apr 25 02:35:19 PM PDT 24
Peak memory 204056 kb
Host smart-a752b05a-f596-4822-b21e-0d9aa14aed77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37813
53541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.3781353541
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.2096538380
Short name T608
Test name
Test status
Simulation time 8385742127 ps
CPU time 8.48 seconds
Started Apr 25 02:35:15 PM PDT 24
Finished Apr 25 02:35:24 PM PDT 24
Peak memory 204120 kb
Host smart-bff0dff6-c7c9-418c-b6c0-797001133dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20965
38380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2096538380
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.3001528109
Short name T1018
Test name
Test status
Simulation time 8438984379 ps
CPU time 7.91 seconds
Started Apr 25 02:35:19 PM PDT 24
Finished Apr 25 02:35:27 PM PDT 24
Peak memory 204112 kb
Host smart-25471511-2521-4fb3-8013-fb86b8fcb477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30015
28109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.3001528109
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3015715365
Short name T23
Test name
Test status
Simulation time 8368912961 ps
CPU time 8.16 seconds
Started Apr 25 02:35:14 PM PDT 24
Finished Apr 25 02:35:23 PM PDT 24
Peak memory 204140 kb
Host smart-e8e77523-4bec-472f-aff4-9a56470890c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30157
15365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.3015715365
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.1890170092
Short name T1125
Test name
Test status
Simulation time 38707792 ps
CPU time 0.65 seconds
Started Apr 25 02:35:20 PM PDT 24
Finished Apr 25 02:35:22 PM PDT 24
Peak memory 204056 kb
Host smart-36bc562c-9c73-4a2a-b0cb-980d4cf08e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18901
70092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.1890170092
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.2461192243
Short name T641
Test name
Test status
Simulation time 21058287247 ps
CPU time 41.31 seconds
Started Apr 25 02:35:12 PM PDT 24
Finished Apr 25 02:35:55 PM PDT 24
Peak memory 204408 kb
Host smart-72f97e25-dfe8-41cc-af6f-3b7d19d3f345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24611
92243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.2461192243
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.2380846287
Short name T46
Test name
Test status
Simulation time 8392856253 ps
CPU time 7.71 seconds
Started Apr 25 02:35:15 PM PDT 24
Finished Apr 25 02:35:24 PM PDT 24
Peak memory 204104 kb
Host smart-11d1b6da-d0a5-4e16-acd3-eadec5a1f7ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23808
46287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2380846287
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.771854940
Short name T47
Test name
Test status
Simulation time 8444210683 ps
CPU time 7.66 seconds
Started Apr 25 02:35:11 PM PDT 24
Finished Apr 25 02:35:20 PM PDT 24
Peak memory 204144 kb
Host smart-f563dbf7-0d9e-48de-897d-452835ad5b02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77185
4940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.771854940
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.4106791326
Short name T401
Test name
Test status
Simulation time 8435288547 ps
CPU time 8.01 seconds
Started Apr 25 02:35:15 PM PDT 24
Finished Apr 25 02:35:24 PM PDT 24
Peak memory 204100 kb
Host smart-485327e6-2af8-4144-8680-32f55546aa77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41067
91326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.4106791326
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.3064546901
Short name T1150
Test name
Test status
Simulation time 8389042755 ps
CPU time 7.55 seconds
Started Apr 25 02:35:19 PM PDT 24
Finished Apr 25 02:35:27 PM PDT 24
Peak memory 204052 kb
Host smart-69a90512-5aef-494c-897f-a4f6a9025984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30645
46901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.3064546901
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.3039563375
Short name T1156
Test name
Test status
Simulation time 8365935184 ps
CPU time 10.26 seconds
Started Apr 25 02:35:11 PM PDT 24
Finished Apr 25 02:35:22 PM PDT 24
Peak memory 204068 kb
Host smart-a00e3b07-0f96-41ac-8811-c893309d9676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30395
63375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.3039563375
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.2614672584
Short name T1219
Test name
Test status
Simulation time 8497999054 ps
CPU time 9.48 seconds
Started Apr 25 02:35:04 PM PDT 24
Finished Apr 25 02:35:14 PM PDT 24
Peak memory 204084 kb
Host smart-f6734cdf-1a77-433e-a196-1c1c77251325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26146
72584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.2614672584
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.2158973424
Short name T363
Test name
Test status
Simulation time 8411033786 ps
CPU time 7.42 seconds
Started Apr 25 02:35:10 PM PDT 24
Finished Apr 25 02:35:18 PM PDT 24
Peak memory 204128 kb
Host smart-65f35549-e1c9-4091-a9a8-e0b1942fc28f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21589
73424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.2158973424
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.251672600
Short name T414
Test name
Test status
Simulation time 8400914787 ps
CPU time 7.75 seconds
Started Apr 25 02:35:11 PM PDT 24
Finished Apr 25 02:35:20 PM PDT 24
Peak memory 204128 kb
Host smart-c2587ad0-f669-495c-8ce7-6a471ba0256e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25167
2600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.251672600
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.497982731
Short name T342
Test name
Test status
Simulation time 8529507039 ps
CPU time 9.47 seconds
Started Apr 25 02:35:19 PM PDT 24
Finished Apr 25 02:35:29 PM PDT 24
Peak memory 204112 kb
Host smart-dffad830-231a-4a5c-bc08-8b7308bdf2ce
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=497982731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.497982731
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.1697389921
Short name T477
Test name
Test status
Simulation time 8379036111 ps
CPU time 8.49 seconds
Started Apr 25 02:35:27 PM PDT 24
Finished Apr 25 02:35:37 PM PDT 24
Peak memory 204088 kb
Host smart-ddc5eb0b-59ce-4bbb-99ad-e1a1d49573ee
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1697389921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.1697389921
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.3757457371
Short name T440
Test name
Test status
Simulation time 8394511666 ps
CPU time 8.66 seconds
Started Apr 25 02:35:18 PM PDT 24
Finished Apr 25 02:35:27 PM PDT 24
Peak memory 204148 kb
Host smart-d63799a8-64ae-4eed-8bc0-876642438dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37574
57371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.3757457371
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.3839973839
Short name T321
Test name
Test status
Simulation time 8427900276 ps
CPU time 8.91 seconds
Started Apr 25 02:35:21 PM PDT 24
Finished Apr 25 02:35:31 PM PDT 24
Peak memory 204032 kb
Host smart-f40a0c5f-cc4f-43cc-bc67-245e7dfe5f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38399
73839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3839973839
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_enable.218241377
Short name T1378
Test name
Test status
Simulation time 8374436383 ps
CPU time 8.19 seconds
Started Apr 25 02:35:24 PM PDT 24
Finished Apr 25 02:35:33 PM PDT 24
Peak memory 204136 kb
Host smart-a9028c47-5197-4c51-9af8-4a747dbc6613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21824
1377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.218241377
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.3607481660
Short name T1232
Test name
Test status
Simulation time 8417292946 ps
CPU time 7.54 seconds
Started Apr 25 02:35:30 PM PDT 24
Finished Apr 25 02:35:39 PM PDT 24
Peak memory 204112 kb
Host smart-df7977bb-5a65-44ed-ba65-a1051f8ccff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36074
81660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.3607481660
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.1681311445
Short name T194
Test name
Test status
Simulation time 8360773745 ps
CPU time 9.18 seconds
Started Apr 25 02:35:19 PM PDT 24
Finished Apr 25 02:35:29 PM PDT 24
Peak memory 204092 kb
Host smart-4b70b22c-aae7-4325-a363-a67d3a77d6e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16813
11445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.1681311445
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.3538562169
Short name T1028
Test name
Test status
Simulation time 8391320823 ps
CPU time 7.44 seconds
Started Apr 25 02:35:18 PM PDT 24
Finished Apr 25 02:35:27 PM PDT 24
Peak memory 204076 kb
Host smart-28d7d349-d624-4be4-904f-4f422736413f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35385
62169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.3538562169
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.363983055
Short name T885
Test name
Test status
Simulation time 8460551070 ps
CPU time 7.75 seconds
Started Apr 25 02:35:22 PM PDT 24
Finished Apr 25 02:35:31 PM PDT 24
Peak memory 204140 kb
Host smart-bdfc44b4-b663-4e5f-8a40-80e5cae0cf2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36398
3055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.363983055
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.1833624719
Short name T937
Test name
Test status
Simulation time 8370849415 ps
CPU time 8.21 seconds
Started Apr 25 02:35:23 PM PDT 24
Finished Apr 25 02:35:32 PM PDT 24
Peak memory 204032 kb
Host smart-a85f18c2-217e-4fbd-85f5-83af51476c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18336
24719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.1833624719
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.2030269717
Short name T587
Test name
Test status
Simulation time 8433063377 ps
CPU time 9.68 seconds
Started Apr 25 02:35:20 PM PDT 24
Finished Apr 25 02:35:31 PM PDT 24
Peak memory 204084 kb
Host smart-4431e82d-0dff-490c-879a-05d36d856a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20302
69717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.2030269717
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.1816152295
Short name T1294
Test name
Test status
Simulation time 8402603354 ps
CPU time 7.81 seconds
Started Apr 25 02:35:24 PM PDT 24
Finished Apr 25 02:35:32 PM PDT 24
Peak memory 204140 kb
Host smart-cfbd5556-0b73-41a7-bd75-2edfdff92d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18161
52295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.1816152295
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.974602183
Short name T668
Test name
Test status
Simulation time 8397475382 ps
CPU time 7.53 seconds
Started Apr 25 02:35:22 PM PDT 24
Finished Apr 25 02:35:30 PM PDT 24
Peak memory 204140 kb
Host smart-e8e0f146-36ee-4776-8376-b2d815123f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97460
2183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.974602183
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.3260997948
Short name T1008
Test name
Test status
Simulation time 8402727629 ps
CPU time 7.47 seconds
Started Apr 25 02:35:17 PM PDT 24
Finished Apr 25 02:35:25 PM PDT 24
Peak memory 204068 kb
Host smart-7b2c836a-e3ed-4b1f-bd1e-d14f24be6f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32609
97948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.3260997948
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.1593665705
Short name T642
Test name
Test status
Simulation time 8373816634 ps
CPU time 10.51 seconds
Started Apr 25 02:35:21 PM PDT 24
Finished Apr 25 02:35:33 PM PDT 24
Peak memory 204104 kb
Host smart-1340cde1-0f5e-4995-872c-4825922f72fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15936
65705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.1593665705
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.3148649222
Short name T767
Test name
Test status
Simulation time 31426410 ps
CPU time 0.66 seconds
Started Apr 25 02:35:22 PM PDT 24
Finished Apr 25 02:35:24 PM PDT 24
Peak memory 203980 kb
Host smart-e844f6e5-b381-4261-9416-397b944910e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31486
49222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.3148649222
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.2897989401
Short name T1105
Test name
Test status
Simulation time 18286058691 ps
CPU time 31.98 seconds
Started Apr 25 02:35:20 PM PDT 24
Finished Apr 25 02:35:53 PM PDT 24
Peak memory 204416 kb
Host smart-b40a1c79-df04-43a9-8214-efa241780818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28979
89401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.2897989401
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.1423255721
Short name T685
Test name
Test status
Simulation time 8373654323 ps
CPU time 7.71 seconds
Started Apr 25 02:35:20 PM PDT 24
Finished Apr 25 02:35:29 PM PDT 24
Peak memory 204140 kb
Host smart-67eca49c-c393-441c-8640-8ac65fa191f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14232
55721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.1423255721
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.451713945
Short name T141
Test name
Test status
Simulation time 8466623037 ps
CPU time 8.25 seconds
Started Apr 25 02:35:20 PM PDT 24
Finished Apr 25 02:35:30 PM PDT 24
Peak memory 204100 kb
Host smart-8be35fb6-5b8e-4d59-915c-09b99b2129fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45171
3945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.451713945
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.3280852301
Short name T759
Test name
Test status
Simulation time 8383862811 ps
CPU time 7.79 seconds
Started Apr 25 02:35:19 PM PDT 24
Finished Apr 25 02:35:28 PM PDT 24
Peak memory 204128 kb
Host smart-a4b2481d-0f7d-482d-b7a2-6be4679dc6d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32808
52301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.3280852301
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.1106022666
Short name T1034
Test name
Test status
Simulation time 8388651167 ps
CPU time 9.55 seconds
Started Apr 25 02:35:21 PM PDT 24
Finished Apr 25 02:35:32 PM PDT 24
Peak memory 204116 kb
Host smart-41b2ac16-fbb1-4912-bd99-2d78ffdc2b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11060
22666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.1106022666
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.1336169386
Short name T990
Test name
Test status
Simulation time 8373473273 ps
CPU time 7.62 seconds
Started Apr 25 02:35:22 PM PDT 24
Finished Apr 25 02:35:30 PM PDT 24
Peak memory 204136 kb
Host smart-5b2f9aa7-2460-42f1-a08e-eb995ffa3a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13361
69386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.1336169386
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3370569309
Short name T156
Test name
Test status
Simulation time 8445807581 ps
CPU time 7.76 seconds
Started Apr 25 02:35:20 PM PDT 24
Finished Apr 25 02:35:29 PM PDT 24
Peak memory 204148 kb
Host smart-1c1faaad-cc12-4b9a-a2ea-aab448a28f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33705
69309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3370569309
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.2648545524
Short name T134
Test name
Test status
Simulation time 8410670041 ps
CPU time 7.62 seconds
Started Apr 25 02:35:19 PM PDT 24
Finished Apr 25 02:35:28 PM PDT 24
Peak memory 204040 kb
Host smart-f46d91c9-362a-4331-aa32-fb71f7167d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26485
45524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.2648545524
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.3653953378
Short name T326
Test name
Test status
Simulation time 8377083898 ps
CPU time 9.24 seconds
Started Apr 25 02:35:19 PM PDT 24
Finished Apr 25 02:35:29 PM PDT 24
Peak memory 204044 kb
Host smart-76cc235a-6353-419d-a13b-c1e51aca4ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36539
53378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.3653953378
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.2952168568
Short name T823
Test name
Test status
Simulation time 8465456530 ps
CPU time 8.71 seconds
Started Apr 25 02:35:27 PM PDT 24
Finished Apr 25 02:35:37 PM PDT 24
Peak memory 204156 kb
Host smart-ae7791b0-415c-4b25-b969-166e49aa2a3e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2952168568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.2952168568
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.528675313
Short name T472
Test name
Test status
Simulation time 8378191840 ps
CPU time 10.04 seconds
Started Apr 25 02:35:27 PM PDT 24
Finished Apr 25 02:35:39 PM PDT 24
Peak memory 204136 kb
Host smart-cda99e6b-a265-4c5b-8f84-7a469bdca29f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=528675313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.528675313
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.2431540472
Short name T1052
Test name
Test status
Simulation time 8422400493 ps
CPU time 7.65 seconds
Started Apr 25 02:35:26 PM PDT 24
Finished Apr 25 02:35:34 PM PDT 24
Peak memory 204140 kb
Host smart-65375874-4465-4b31-8259-5a003dc3a7db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24315
40472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.2431540472
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.3176727244
Short name T397
Test name
Test status
Simulation time 8396525871 ps
CPU time 9.96 seconds
Started Apr 25 02:35:26 PM PDT 24
Finished Apr 25 02:35:36 PM PDT 24
Peak memory 204120 kb
Host smart-73e5d17c-b204-47cc-8cdd-b92052ae5c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31767
27244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.3176727244
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_enable.2529029751
Short name T1288
Test name
Test status
Simulation time 8411268758 ps
CPU time 8.34 seconds
Started Apr 25 02:35:25 PM PDT 24
Finished Apr 25 02:35:34 PM PDT 24
Peak memory 204104 kb
Host smart-05570a24-9fec-4d16-90a4-a474eecf1857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25290
29751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.2529029751
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3910307770
Short name T1280
Test name
Test status
Simulation time 185426253 ps
CPU time 1.56 seconds
Started Apr 25 02:35:29 PM PDT 24
Finished Apr 25 02:35:31 PM PDT 24
Peak memory 204268 kb
Host smart-3264bb59-e913-4eb1-b1d4-241e8c2469ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39103
07770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3910307770
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.321203038
Short name T800
Test name
Test status
Simulation time 8424020237 ps
CPU time 8.15 seconds
Started Apr 25 02:35:32 PM PDT 24
Finished Apr 25 02:35:42 PM PDT 24
Peak memory 204108 kb
Host smart-b23190d9-ffdf-43dd-bbc6-c2b345686dc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32120
3038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.321203038
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.2442445586
Short name T202
Test name
Test status
Simulation time 8367345140 ps
CPU time 7.35 seconds
Started Apr 25 02:35:27 PM PDT 24
Finished Apr 25 02:35:35 PM PDT 24
Peak memory 204116 kb
Host smart-3f3e7034-b0ff-490c-a7c4-e313e3b090ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24424
45586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.2442445586
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.3881052925
Short name T1151
Test name
Test status
Simulation time 8426456601 ps
CPU time 9.35 seconds
Started Apr 25 02:35:24 PM PDT 24
Finished Apr 25 02:35:34 PM PDT 24
Peak memory 204164 kb
Host smart-852c7790-5555-4fcd-9ed0-8c98f82a1623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38810
52925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3881052925
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2432853249
Short name T1325
Test name
Test status
Simulation time 8460196619 ps
CPU time 7.69 seconds
Started Apr 25 02:35:26 PM PDT 24
Finished Apr 25 02:35:34 PM PDT 24
Peak memory 204036 kb
Host smart-3b0ecb3e-fa70-4655-b0e4-642bfbf74cb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24328
53249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2432853249
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3530657243
Short name T1035
Test name
Test status
Simulation time 8384402662 ps
CPU time 7.43 seconds
Started Apr 25 02:35:26 PM PDT 24
Finished Apr 25 02:35:34 PM PDT 24
Peak memory 204140 kb
Host smart-af1718ec-0093-4acd-b197-00f210085734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35306
57243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3530657243
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.2219552731
Short name T124
Test name
Test status
Simulation time 8411983735 ps
CPU time 8.05 seconds
Started Apr 25 02:35:25 PM PDT 24
Finished Apr 25 02:35:34 PM PDT 24
Peak memory 204148 kb
Host smart-eab9b8ef-d198-45f8-a5e6-05357a29b3d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22195
52731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.2219552731
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1094378858
Short name T1343
Test name
Test status
Simulation time 8403358500 ps
CPU time 7.93 seconds
Started Apr 25 02:35:27 PM PDT 24
Finished Apr 25 02:35:36 PM PDT 24
Peak memory 204148 kb
Host smart-5e33276b-7c84-45d2-aa6e-59a0d9c8bf6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10943
78858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1094378858
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.86811807
Short name T1229
Test name
Test status
Simulation time 8383593626 ps
CPU time 8 seconds
Started Apr 25 02:35:27 PM PDT 24
Finished Apr 25 02:35:36 PM PDT 24
Peak memory 204108 kb
Host smart-c3e1f175-e3fd-4ec5-b831-2bdca337b0bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86811
807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.86811807
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.99235137
Short name T1190
Test name
Test status
Simulation time 8382862043 ps
CPU time 7.22 seconds
Started Apr 25 02:35:26 PM PDT 24
Finished Apr 25 02:35:34 PM PDT 24
Peak memory 204104 kb
Host smart-4dfacdba-db28-4305-a7e9-7e8db9e3cd93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99235
137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.99235137
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.3296070206
Short name T743
Test name
Test status
Simulation time 8368653211 ps
CPU time 7.48 seconds
Started Apr 25 02:35:32 PM PDT 24
Finished Apr 25 02:35:41 PM PDT 24
Peak memory 204124 kb
Host smart-8d7e206a-7b3d-4acc-83a6-96acf692cf02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32960
70206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.3296070206
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3257735091
Short name T561
Test name
Test status
Simulation time 54626668 ps
CPU time 0.67 seconds
Started Apr 25 02:35:29 PM PDT 24
Finished Apr 25 02:35:31 PM PDT 24
Peak memory 204008 kb
Host smart-36909f31-f38b-450e-87b5-0c44fb8872a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32577
35091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3257735091
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.218801994
Short name T1114
Test name
Test status
Simulation time 17911052118 ps
CPU time 31.98 seconds
Started Apr 25 02:35:29 PM PDT 24
Finished Apr 25 02:36:02 PM PDT 24
Peak memory 204432 kb
Host smart-dbde3ed6-b6dd-499a-bb68-61de1a4174df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21880
1994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.218801994
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.2646893460
Short name T446
Test name
Test status
Simulation time 8380758632 ps
CPU time 7.91 seconds
Started Apr 25 02:35:27 PM PDT 24
Finished Apr 25 02:35:37 PM PDT 24
Peak memory 204148 kb
Host smart-106d27dc-4eca-4c0f-bf68-d7e8f620a2a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26468
93460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.2646893460
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2716712457
Short name T142
Test name
Test status
Simulation time 8457358979 ps
CPU time 7.99 seconds
Started Apr 25 02:35:28 PM PDT 24
Finished Apr 25 02:35:37 PM PDT 24
Peak memory 204124 kb
Host smart-9421e0d0-21da-4eba-8a73-96478215c0ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27167
12457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2716712457
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.110910767
Short name T1057
Test name
Test status
Simulation time 8378511738 ps
CPU time 8.32 seconds
Started Apr 25 02:35:27 PM PDT 24
Finished Apr 25 02:35:36 PM PDT 24
Peak memory 204132 kb
Host smart-6c242b4c-7cf8-48cb-84dc-3eb9537a948e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11091
0767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.110910767
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.1662705959
Short name T517
Test name
Test status
Simulation time 8370582266 ps
CPU time 7.57 seconds
Started Apr 25 02:35:30 PM PDT 24
Finished Apr 25 02:35:39 PM PDT 24
Peak memory 203868 kb
Host smart-a2085a7a-f040-4aa8-98bb-b5ca522b81f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16627
05959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.1662705959
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.4051903675
Short name T656
Test name
Test status
Simulation time 8371855534 ps
CPU time 7.73 seconds
Started Apr 25 02:35:30 PM PDT 24
Finished Apr 25 02:35:39 PM PDT 24
Peak memory 203908 kb
Host smart-5bf17fe2-fd16-43a3-b10f-47c9a3902c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40519
03675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.4051903675
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.2233977005
Short name T1144
Test name
Test status
Simulation time 8427593125 ps
CPU time 8.27 seconds
Started Apr 25 02:35:27 PM PDT 24
Finished Apr 25 02:35:37 PM PDT 24
Peak memory 204048 kb
Host smart-2fa64882-b054-4937-9099-eb42d6624366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22339
77005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.2233977005
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.4161358518
Short name T1283
Test name
Test status
Simulation time 8461864624 ps
CPU time 9.49 seconds
Started Apr 25 02:35:27 PM PDT 24
Finished Apr 25 02:35:38 PM PDT 24
Peak memory 204088 kb
Host smart-b12b8de1-8c45-423b-beae-6e339eaaf357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41613
58518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.4161358518
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.3039784634
Short name T603
Test name
Test status
Simulation time 8396431429 ps
CPU time 8.98 seconds
Started Apr 25 02:35:32 PM PDT 24
Finished Apr 25 02:35:43 PM PDT 24
Peak memory 204116 kb
Host smart-24d4a1c5-bfb1-4e42-a5be-24a1f4799507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30397
84634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.3039784634
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.1992953533
Short name T1116
Test name
Test status
Simulation time 8464511083 ps
CPU time 8.26 seconds
Started Apr 25 02:29:53 PM PDT 24
Finished Apr 25 02:30:02 PM PDT 24
Peak memory 204108 kb
Host smart-ef23d50b-c2d6-4cd6-b6a6-ebd1a54955e3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1992953533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.1992953533
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.1020230782
Short name T439
Test name
Test status
Simulation time 8372608351 ps
CPU time 10.13 seconds
Started Apr 25 02:29:52 PM PDT 24
Finished Apr 25 02:30:03 PM PDT 24
Peak memory 204076 kb
Host smart-b1b59e8e-77fe-48a0-b644-619a6fcd13b5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1020230782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.1020230782
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.3449155778
Short name T352
Test name
Test status
Simulation time 8393871233 ps
CPU time 7.85 seconds
Started Apr 25 02:29:47 PM PDT 24
Finished Apr 25 02:29:55 PM PDT 24
Peak memory 204072 kb
Host smart-4ad43662-f864-47f4-9215-0c579b627cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34491
55778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.3449155778
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.3310172479
Short name T1071
Test name
Test status
Simulation time 8381436746 ps
CPU time 7.5 seconds
Started Apr 25 02:29:39 PM PDT 24
Finished Apr 25 02:29:48 PM PDT 24
Peak memory 204148 kb
Host smart-275e9124-3a24-4eb2-b350-6751bfa05fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33101
72479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.3310172479
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_enable.3453608838
Short name T842
Test name
Test status
Simulation time 8469438694 ps
CPU time 8.46 seconds
Started Apr 25 02:29:42 PM PDT 24
Finished Apr 25 02:29:51 PM PDT 24
Peak memory 204044 kb
Host smart-e7e70751-177b-4a28-bca6-df15dd704d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34536
08838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.3453608838
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.78081975
Short name T1239
Test name
Test status
Simulation time 48417908 ps
CPU time 1.19 seconds
Started Apr 25 02:29:42 PM PDT 24
Finished Apr 25 02:29:43 PM PDT 24
Peak memory 204176 kb
Host smart-7a698a0d-2cfb-4137-ad66-ab63b62308b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78081
975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.78081975
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.1411297664
Short name T533
Test name
Test status
Simulation time 8393283696 ps
CPU time 7.43 seconds
Started Apr 25 02:29:48 PM PDT 24
Finished Apr 25 02:29:56 PM PDT 24
Peak memory 204152 kb
Host smart-28b04735-7440-4a17-a4d2-e9818a0f3264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14112
97664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1411297664
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.1032984177
Short name T925
Test name
Test status
Simulation time 8368976183 ps
CPU time 7.53 seconds
Started Apr 25 02:29:44 PM PDT 24
Finished Apr 25 02:29:52 PM PDT 24
Peak memory 204024 kb
Host smart-d3281434-5077-45bc-99d1-8e7dc6318a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10329
84177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.1032984177
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.992798814
Short name T601
Test name
Test status
Simulation time 8477167750 ps
CPU time 7.69 seconds
Started Apr 25 02:29:43 PM PDT 24
Finished Apr 25 02:29:51 PM PDT 24
Peak memory 204116 kb
Host smart-dfa05044-2ac5-44f0-b3e7-72a7d2a1b359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99279
8814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.992798814
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.2289086833
Short name T650
Test name
Test status
Simulation time 8428323276 ps
CPU time 8.49 seconds
Started Apr 25 02:29:41 PM PDT 24
Finished Apr 25 02:29:50 PM PDT 24
Peak memory 204132 kb
Host smart-e2017c9f-493c-4e75-89ce-44747dc0d0a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22890
86833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.2289086833
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.149602374
Short name T437
Test name
Test status
Simulation time 8373300181 ps
CPU time 7.96 seconds
Started Apr 25 02:29:45 PM PDT 24
Finished Apr 25 02:29:53 PM PDT 24
Peak memory 204148 kb
Host smart-6963f46d-4abb-42b1-b359-79e255304006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14960
2374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.149602374
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.1658203209
Short name T129
Test name
Test status
Simulation time 8443159269 ps
CPU time 8.11 seconds
Started Apr 25 02:29:40 PM PDT 24
Finished Apr 25 02:29:48 PM PDT 24
Peak memory 204112 kb
Host smart-2da724ab-65f9-4ee8-b212-a374854281c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16582
03209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.1658203209
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.992102389
Short name T332
Test name
Test status
Simulation time 8369781909 ps
CPU time 8.09 seconds
Started Apr 25 02:29:41 PM PDT 24
Finished Apr 25 02:29:49 PM PDT 24
Peak memory 204108 kb
Host smart-295a65da-b72f-4a7f-b4b5-bf8b62f0783c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99210
2389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.992102389
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.850307290
Short name T1160
Test name
Test status
Simulation time 8431357026 ps
CPU time 8.54 seconds
Started Apr 25 02:29:48 PM PDT 24
Finished Apr 25 02:29:58 PM PDT 24
Peak memory 204044 kb
Host smart-25537fdb-562c-48e6-b65c-faa21710d3e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85030
7290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.850307290
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.3310017783
Short name T1055
Test name
Test status
Simulation time 8397425719 ps
CPU time 7.53 seconds
Started Apr 25 02:29:47 PM PDT 24
Finished Apr 25 02:29:55 PM PDT 24
Peak memory 204116 kb
Host smart-41291ba6-cfe9-4fec-bcc2-7f04f774c386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33100
17783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.3310017783
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.283027124
Short name T1335
Test name
Test status
Simulation time 8376242791 ps
CPU time 8.07 seconds
Started Apr 25 02:29:47 PM PDT 24
Finished Apr 25 02:29:56 PM PDT 24
Peak memory 204116 kb
Host smart-a0e37491-e94d-49cf-b322-383af6e42c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28302
7124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.283027124
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3999709919
Short name T635
Test name
Test status
Simulation time 63807414 ps
CPU time 0.69 seconds
Started Apr 25 02:29:46 PM PDT 24
Finished Apr 25 02:29:48 PM PDT 24
Peak memory 203988 kb
Host smart-3737bc29-a735-498d-a66b-0b8fd4608aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39997
09919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3999709919
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.765380227
Short name T261
Test name
Test status
Simulation time 29231824712 ps
CPU time 55.26 seconds
Started Apr 25 02:29:48 PM PDT 24
Finished Apr 25 02:30:44 PM PDT 24
Peak memory 204332 kb
Host smart-4c712c89-0edd-4a2a-9882-53017e1e52fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76538
0227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.765380227
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.1740416175
Short name T1365
Test name
Test status
Simulation time 8405657416 ps
CPU time 8.27 seconds
Started Apr 25 02:29:46 PM PDT 24
Finished Apr 25 02:29:54 PM PDT 24
Peak memory 204060 kb
Host smart-2a33cbf3-587a-4e70-a313-e71a36836fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17404
16175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.1740416175
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.886887357
Short name T1207
Test name
Test status
Simulation time 8378992425 ps
CPU time 7.6 seconds
Started Apr 25 02:29:48 PM PDT 24
Finished Apr 25 02:29:56 PM PDT 24
Peak memory 204148 kb
Host smart-27387863-a2dd-476c-848e-47349e8fecf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88688
7357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.886887357
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.3063871184
Short name T459
Test name
Test status
Simulation time 8410469822 ps
CPU time 9.75 seconds
Started Apr 25 02:29:46 PM PDT 24
Finished Apr 25 02:29:56 PM PDT 24
Peak memory 204132 kb
Host smart-72db96c2-5fb2-4aac-8ebb-3bc332a0fded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30638
71184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.3063871184
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.22877176
Short name T65
Test name
Test status
Simulation time 545206282 ps
CPU time 1.41 seconds
Started Apr 25 02:29:52 PM PDT 24
Finished Apr 25 02:29:54 PM PDT 24
Peak memory 220364 kb
Host smart-96fb6192-fc2e-4fcf-84cf-8065b3d89927
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=22877176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.22877176
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.1805757425
Short name T189
Test name
Test status
Simulation time 8381451400 ps
CPU time 7.57 seconds
Started Apr 25 02:29:47 PM PDT 24
Finished Apr 25 02:29:56 PM PDT 24
Peak memory 204124 kb
Host smart-01709c11-7ee6-40f6-be4d-e7b0c1c71295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18057
57425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.1805757425
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.1997437495
Short name T1354
Test name
Test status
Simulation time 8373128004 ps
CPU time 8.7 seconds
Started Apr 25 02:29:48 PM PDT 24
Finished Apr 25 02:29:58 PM PDT 24
Peak memory 204136 kb
Host smart-62a86599-800b-4116-b616-4c137229018d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19974
37495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.1997437495
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.3716361547
Short name T544
Test name
Test status
Simulation time 8410503235 ps
CPU time 8.71 seconds
Started Apr 25 02:29:45 PM PDT 24
Finished Apr 25 02:29:54 PM PDT 24
Peak memory 204148 kb
Host smart-ae16c9a0-cf0c-4988-9333-acf1868bfeeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37163
61547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.3716361547
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.1871685861
Short name T1104
Test name
Test status
Simulation time 8413043187 ps
CPU time 9.66 seconds
Started Apr 25 02:29:48 PM PDT 24
Finished Apr 25 02:29:58 PM PDT 24
Peak memory 204088 kb
Host smart-9fd9a19b-0eaa-42fe-ace9-84bc242119f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18716
85861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.1871685861
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.3611469965
Short name T383
Test name
Test status
Simulation time 8435752379 ps
CPU time 8.05 seconds
Started Apr 25 02:29:48 PM PDT 24
Finished Apr 25 02:29:57 PM PDT 24
Peak memory 204140 kb
Host smart-690db094-c44f-4f91-b381-a872bf5f4cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36114
69965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.3611469965
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.3922205228
Short name T996
Test name
Test status
Simulation time 8471177891 ps
CPU time 8.44 seconds
Started Apr 25 02:35:33 PM PDT 24
Finished Apr 25 02:35:44 PM PDT 24
Peak memory 204124 kb
Host smart-d2c33dc5-7464-4c2e-ab36-de57168343d3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3922205228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.3922205228
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.2602822174
Short name T785
Test name
Test status
Simulation time 8378993758 ps
CPU time 8.43 seconds
Started Apr 25 02:35:31 PM PDT 24
Finished Apr 25 02:35:40 PM PDT 24
Peak memory 204044 kb
Host smart-efe87946-ed7f-40bb-b1d1-fae7f5a05e25
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2602822174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.2602822174
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.655362388
Short name T1058
Test name
Test status
Simulation time 8503623737 ps
CPU time 10.17 seconds
Started Apr 25 02:35:34 PM PDT 24
Finished Apr 25 02:35:46 PM PDT 24
Peak memory 204040 kb
Host smart-28729051-e467-4458-8ec1-751940341893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65536
2388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.655362388
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.3665157526
Short name T243
Test name
Test status
Simulation time 8377814353 ps
CPU time 7.46 seconds
Started Apr 25 02:35:33 PM PDT 24
Finished Apr 25 02:35:42 PM PDT 24
Peak memory 204084 kb
Host smart-d102fd16-4a11-4b61-87c6-2abcde5f9a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36651
57526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.3665157526
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_enable.2212645297
Short name T713
Test name
Test status
Simulation time 8384614796 ps
CPU time 7.73 seconds
Started Apr 25 02:35:34 PM PDT 24
Finished Apr 25 02:35:43 PM PDT 24
Peak memory 204076 kb
Host smart-12c300db-aa18-482d-a0ac-e51590811824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22126
45297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.2212645297
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.1910715771
Short name T234
Test name
Test status
Simulation time 89820263 ps
CPU time 1.68 seconds
Started Apr 25 02:35:36 PM PDT 24
Finished Apr 25 02:35:39 PM PDT 24
Peak memory 204168 kb
Host smart-a29d1d86-3ec2-434b-aa47-960c20853a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19107
15771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.1910715771
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.3116972076
Short name T919
Test name
Test status
Simulation time 8401604877 ps
CPU time 7.69 seconds
Started Apr 25 02:35:35 PM PDT 24
Finished Apr 25 02:35:45 PM PDT 24
Peak memory 204100 kb
Host smart-1db45087-b524-4ccc-886b-72fef25e47c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31169
72076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.3116972076
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.2537096797
Short name T193
Test name
Test status
Simulation time 8369108043 ps
CPU time 10.1 seconds
Started Apr 25 02:35:32 PM PDT 24
Finished Apr 25 02:35:44 PM PDT 24
Peak memory 204056 kb
Host smart-4a24567b-14b5-40cc-9ea4-b0bafb498e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25370
96797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.2537096797
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.1437862695
Short name T146
Test name
Test status
Simulation time 8418084099 ps
CPU time 8.49 seconds
Started Apr 25 02:35:32 PM PDT 24
Finished Apr 25 02:35:42 PM PDT 24
Peak memory 204076 kb
Host smart-1c398e6e-0f16-4d4a-a2eb-8d5ba7fc4766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14378
62695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1437862695
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.940513554
Short name T873
Test name
Test status
Simulation time 8433261621 ps
CPU time 7.82 seconds
Started Apr 25 02:35:35 PM PDT 24
Finished Apr 25 02:35:45 PM PDT 24
Peak memory 204092 kb
Host smart-2f231649-20aa-4675-9968-0861f78d3e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94051
3554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.940513554
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2320891520
Short name T568
Test name
Test status
Simulation time 8430452401 ps
CPU time 8.25 seconds
Started Apr 25 02:35:33 PM PDT 24
Finished Apr 25 02:35:43 PM PDT 24
Peak memory 204060 kb
Host smart-d68934d0-52e8-4b65-898f-3691c6c36700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23208
91520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2320891520
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.2350973643
Short name T107
Test name
Test status
Simulation time 8403483732 ps
CPU time 8.67 seconds
Started Apr 25 02:35:35 PM PDT 24
Finished Apr 25 02:35:45 PM PDT 24
Peak memory 204128 kb
Host smart-58c30d4a-96de-4156-96bc-5ebbc818da87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23509
73643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.2350973643
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.4022220798
Short name T1080
Test name
Test status
Simulation time 8383245356 ps
CPU time 9.3 seconds
Started Apr 25 02:35:33 PM PDT 24
Finished Apr 25 02:35:44 PM PDT 24
Peak memory 204148 kb
Host smart-3d30a90a-83bb-4cc9-8000-c846d6a23c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40222
20798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.4022220798
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.127288594
Short name T541
Test name
Test status
Simulation time 8388664470 ps
CPU time 7.5 seconds
Started Apr 25 02:35:36 PM PDT 24
Finished Apr 25 02:35:45 PM PDT 24
Peak memory 204132 kb
Host smart-d09b1eef-4af2-4450-840c-7601c057256c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12728
8594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.127288594
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.3871390317
Short name T744
Test name
Test status
Simulation time 8406217485 ps
CPU time 8.65 seconds
Started Apr 25 02:35:36 PM PDT 24
Finished Apr 25 02:35:46 PM PDT 24
Peak memory 204112 kb
Host smart-209f48c7-efb4-4011-8835-0704a3b50b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38713
90317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.3871390317
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.3502642054
Short name T3
Test name
Test status
Simulation time 8365478324 ps
CPU time 7.98 seconds
Started Apr 25 02:35:35 PM PDT 24
Finished Apr 25 02:35:45 PM PDT 24
Peak memory 204132 kb
Host smart-2fdab746-a3a6-47aa-aea6-f294cf15ef17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35026
42054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.3502642054
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.77507053
Short name T435
Test name
Test status
Simulation time 42923658 ps
CPU time 0.66 seconds
Started Apr 25 02:35:35 PM PDT 24
Finished Apr 25 02:35:38 PM PDT 24
Peak memory 203976 kb
Host smart-21158f19-ce04-4161-a1f0-676d9a16f397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77507
053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.77507053
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.2167341357
Short name T265
Test name
Test status
Simulation time 15664310938 ps
CPU time 29.32 seconds
Started Apr 25 02:35:34 PM PDT 24
Finished Apr 25 02:36:05 PM PDT 24
Peak memory 204400 kb
Host smart-0786e07d-b594-4774-a9e2-947e5811408c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21673
41357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.2167341357
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.3955321096
Short name T1003
Test name
Test status
Simulation time 8434991242 ps
CPU time 8.24 seconds
Started Apr 25 02:35:34 PM PDT 24
Finished Apr 25 02:35:45 PM PDT 24
Peak memory 204076 kb
Host smart-a53cacea-cfb6-44a7-ad0a-7a3587ab430f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39553
21096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.3955321096
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.2486582800
Short name T906
Test name
Test status
Simulation time 8430460512 ps
CPU time 7.64 seconds
Started Apr 25 02:35:34 PM PDT 24
Finished Apr 25 02:35:44 PM PDT 24
Peak memory 204124 kb
Host smart-14fa1f85-6aa2-44a5-8cde-f7df397aad56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24865
82800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.2486582800
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.1991913508
Short name T859
Test name
Test status
Simulation time 8403152183 ps
CPU time 8.24 seconds
Started Apr 25 02:35:33 PM PDT 24
Finished Apr 25 02:35:43 PM PDT 24
Peak memory 204100 kb
Host smart-430031bf-e5de-4a89-8f0e-f2356a0e8b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19919
13508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.1991913508
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.1867246470
Short name T617
Test name
Test status
Simulation time 8379060888 ps
CPU time 7.57 seconds
Started Apr 25 02:35:36 PM PDT 24
Finished Apr 25 02:35:45 PM PDT 24
Peak memory 204148 kb
Host smart-c793fa3d-b5fa-4240-9ef6-a97b81a2f5ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18672
46470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.1867246470
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.2904913631
Short name T468
Test name
Test status
Simulation time 8391210812 ps
CPU time 7.97 seconds
Started Apr 25 02:35:32 PM PDT 24
Finished Apr 25 02:35:41 PM PDT 24
Peak memory 204136 kb
Host smart-8197eb47-f12e-4e31-8dcb-4d7cafb61c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29049
13631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.2904913631
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.4257624135
Short name T559
Test name
Test status
Simulation time 8460626528 ps
CPU time 8.18 seconds
Started Apr 25 02:35:35 PM PDT 24
Finished Apr 25 02:35:45 PM PDT 24
Peak memory 204024 kb
Host smart-011b9177-a262-4c90-9451-8f557236f2dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42576
24135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.4257624135
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.2680246742
Short name T1350
Test name
Test status
Simulation time 8406683135 ps
CPU time 7.83 seconds
Started Apr 25 02:35:34 PM PDT 24
Finished Apr 25 02:35:43 PM PDT 24
Peak memory 204140 kb
Host smart-51532413-ed50-4e1a-b43a-facf3121bbaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26802
46742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.2680246742
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.2039166719
Short name T282
Test name
Test status
Simulation time 8379540997 ps
CPU time 7.99 seconds
Started Apr 25 02:35:33 PM PDT 24
Finished Apr 25 02:35:44 PM PDT 24
Peak memory 204028 kb
Host smart-1a004b2a-64a7-4b44-ad73-db44140f4300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20391
66719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.2039166719
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.2985994510
Short name T1197
Test name
Test status
Simulation time 8518803540 ps
CPU time 9.09 seconds
Started Apr 25 02:35:39 PM PDT 24
Finished Apr 25 02:35:49 PM PDT 24
Peak memory 204132 kb
Host smart-43fb9ec4-542a-4025-ba96-822765ba8a83
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2985994510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.2985994510
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.3448433422
Short name T479
Test name
Test status
Simulation time 8391170756 ps
CPU time 7.75 seconds
Started Apr 25 02:35:40 PM PDT 24
Finished Apr 25 02:35:50 PM PDT 24
Peak memory 204116 kb
Host smart-6aefc44f-37e6-4d7c-886e-5a56ce28d028
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3448433422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.3448433422
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.random_length_in_trans.162331230
Short name T849
Test name
Test status
Simulation time 8463162586 ps
CPU time 8.12 seconds
Started Apr 25 02:35:40 PM PDT 24
Finished Apr 25 02:35:50 PM PDT 24
Peak memory 204136 kb
Host smart-15ffbe12-99a0-461d-b344-7dbfaa6e46b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16233
1230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.162331230
Directory /workspace/41.random_length_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.1586764644
Short name T988
Test name
Test status
Simulation time 8374162754 ps
CPU time 9.26 seconds
Started Apr 25 02:35:35 PM PDT 24
Finished Apr 25 02:35:46 PM PDT 24
Peak memory 204076 kb
Host smart-8dbd07ec-aaf6-4afa-a906-be5664002761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15867
64644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.1586764644
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_enable.3444331768
Short name T10
Test name
Test status
Simulation time 8370867573 ps
CPU time 7.89 seconds
Started Apr 25 02:35:41 PM PDT 24
Finished Apr 25 02:35:50 PM PDT 24
Peak memory 204100 kb
Host smart-7e0e83b8-2257-419d-a650-68520b99a91f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34443
31768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3444331768
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.227317265
Short name T400
Test name
Test status
Simulation time 276430897 ps
CPU time 2.12 seconds
Started Apr 25 02:35:40 PM PDT 24
Finished Apr 25 02:35:43 PM PDT 24
Peak memory 204280 kb
Host smart-b9670895-7954-4d49-9dce-e738294e8b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22731
7265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.227317265
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.1027431175
Short name T981
Test name
Test status
Simulation time 8430217715 ps
CPU time 7.94 seconds
Started Apr 25 02:36:08 PM PDT 24
Finished Apr 25 02:36:18 PM PDT 24
Peak memory 204144 kb
Host smart-0bec8773-d515-4d03-91d6-4a54148e99e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10274
31175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.1027431175
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2939112775
Short name T1026
Test name
Test status
Simulation time 8372968076 ps
CPU time 8.23 seconds
Started Apr 25 02:35:41 PM PDT 24
Finished Apr 25 02:35:51 PM PDT 24
Peak memory 204032 kb
Host smart-109a0c04-e934-44b8-ada9-8a49bc15738b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29391
12775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2939112775
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.1878933113
Short name T1382
Test name
Test status
Simulation time 8436574359 ps
CPU time 8.9 seconds
Started Apr 25 02:35:41 PM PDT 24
Finished Apr 25 02:35:52 PM PDT 24
Peak memory 204152 kb
Host smart-bb99c1e6-2c43-4b55-b12c-1d7c8416b026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18789
33113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.1878933113
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.4269411484
Short name T545
Test name
Test status
Simulation time 8432163754 ps
CPU time 8.1 seconds
Started Apr 25 02:35:50 PM PDT 24
Finished Apr 25 02:35:59 PM PDT 24
Peak memory 204112 kb
Host smart-b05a642b-bb52-48b7-818e-3077bf97007f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42694
11484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.4269411484
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.526634155
Short name T331
Test name
Test status
Simulation time 8377138187 ps
CPU time 8.02 seconds
Started Apr 25 02:35:44 PM PDT 24
Finished Apr 25 02:35:53 PM PDT 24
Peak memory 204072 kb
Host smart-32ae7729-b912-4235-9264-e40202907088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52663
4155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.526634155
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.1578878806
Short name T104
Test name
Test status
Simulation time 8412095955 ps
CPU time 9.05 seconds
Started Apr 25 02:35:40 PM PDT 24
Finished Apr 25 02:35:50 PM PDT 24
Peak memory 204136 kb
Host smart-67567f8c-8571-46df-aa80-b5ac29187a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15788
78806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.1578878806
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.3623233817
Short name T558
Test name
Test status
Simulation time 8408339231 ps
CPU time 10.13 seconds
Started Apr 25 02:35:39 PM PDT 24
Finished Apr 25 02:35:50 PM PDT 24
Peak memory 204096 kb
Host smart-65ca0127-7473-4f71-a041-bdca1808e29d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36232
33817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.3623233817
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3194112209
Short name T958
Test name
Test status
Simulation time 8421600228 ps
CPU time 8.07 seconds
Started Apr 25 02:35:41 PM PDT 24
Finished Apr 25 02:35:51 PM PDT 24
Peak memory 204116 kb
Host smart-647a511e-13c9-4910-9d9f-a564dec7d5bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31941
12209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3194112209
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.3795724980
Short name T867
Test name
Test status
Simulation time 8373886954 ps
CPU time 9.11 seconds
Started Apr 25 02:35:40 PM PDT 24
Finished Apr 25 02:35:51 PM PDT 24
Peak memory 204124 kb
Host smart-1f35b8de-6ce0-48df-8a4b-22c9ce899d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37957
24980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.3795724980
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.3273989515
Short name T219
Test name
Test status
Simulation time 8375385589 ps
CPU time 9.41 seconds
Started Apr 25 02:35:39 PM PDT 24
Finished Apr 25 02:35:50 PM PDT 24
Peak memory 204136 kb
Host smart-ded9c3b5-bb65-46e6-a207-85dd1c6dc5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32739
89515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.3273989515
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2959380126
Short name T795
Test name
Test status
Simulation time 58646727 ps
CPU time 0.67 seconds
Started Apr 25 02:35:40 PM PDT 24
Finished Apr 25 02:35:42 PM PDT 24
Peak memory 203948 kb
Host smart-7685fa89-ba45-4cac-b1bc-f28028aa2271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29593
80126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2959380126
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.3164836319
Short name T1264
Test name
Test status
Simulation time 23915123741 ps
CPU time 48.1 seconds
Started Apr 25 02:35:49 PM PDT 24
Finished Apr 25 02:36:39 PM PDT 24
Peak memory 204400 kb
Host smart-560ce246-a218-462d-b1de-d402347b96cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31648
36319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3164836319
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.3509740707
Short name T850
Test name
Test status
Simulation time 8410262317 ps
CPU time 7.38 seconds
Started Apr 25 02:35:39 PM PDT 24
Finished Apr 25 02:35:48 PM PDT 24
Peak memory 204116 kb
Host smart-b561ae28-7e81-488e-8466-b11ea329a6e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35097
40707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.3509740707
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.2013022214
Short name T1076
Test name
Test status
Simulation time 8378204201 ps
CPU time 10.04 seconds
Started Apr 25 02:35:40 PM PDT 24
Finished Apr 25 02:35:51 PM PDT 24
Peak memory 204148 kb
Host smart-02f88b9d-3f12-4cfd-bc7f-9f59032411fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20130
22214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2013022214
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.1731292178
Short name T781
Test name
Test status
Simulation time 8403110159 ps
CPU time 10.04 seconds
Started Apr 25 02:35:39 PM PDT 24
Finished Apr 25 02:35:50 PM PDT 24
Peak memory 204072 kb
Host smart-48daf816-31c2-45e9-bc61-26034c2761ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17312
92178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.1731292178
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.3770868133
Short name T586
Test name
Test status
Simulation time 8374704454 ps
CPU time 7.54 seconds
Started Apr 25 02:35:40 PM PDT 24
Finished Apr 25 02:35:49 PM PDT 24
Peak memory 204028 kb
Host smart-753cc148-a9f9-4157-bf1e-5fa6298f07dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37708
68133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.3770868133
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.1364016818
Short name T228
Test name
Test status
Simulation time 8360913452 ps
CPU time 7.43 seconds
Started Apr 25 02:35:40 PM PDT 24
Finished Apr 25 02:35:49 PM PDT 24
Peak memory 204108 kb
Host smart-884ded3a-55ab-436c-a542-10715b8c920f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13640
16818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.1364016818
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.1463644970
Short name T381
Test name
Test status
Simulation time 8390446740 ps
CPU time 7.53 seconds
Started Apr 25 02:35:50 PM PDT 24
Finished Apr 25 02:35:58 PM PDT 24
Peak memory 204116 kb
Host smart-17290097-36c7-47d8-8fea-8198cb5f7a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14636
44970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.1463644970
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.1650055323
Short name T405
Test name
Test status
Simulation time 8399490590 ps
CPU time 8.03 seconds
Started Apr 25 02:35:41 PM PDT 24
Finished Apr 25 02:35:50 PM PDT 24
Peak memory 204068 kb
Host smart-e53363ff-b73e-4714-b09d-d3bf3486e151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16500
55323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.1650055323
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.2064786962
Short name T18
Test name
Test status
Simulation time 8504519904 ps
CPU time 7.69 seconds
Started Apr 25 02:35:46 PM PDT 24
Finished Apr 25 02:35:55 PM PDT 24
Peak memory 204104 kb
Host smart-786ef123-85af-4a73-a6d1-ff064ea7c0b3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2064786962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.2064786962
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.3987317165
Short name T523
Test name
Test status
Simulation time 8480993564 ps
CPU time 8.16 seconds
Started Apr 25 02:35:48 PM PDT 24
Finished Apr 25 02:35:58 PM PDT 24
Peak memory 204032 kb
Host smart-ec666c92-93ca-4c59-8958-b02384ad1cca
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3987317165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.3987317165
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.4063983624
Short name T391
Test name
Test status
Simulation time 8468048665 ps
CPU time 7.89 seconds
Started Apr 25 02:35:48 PM PDT 24
Finished Apr 25 02:35:57 PM PDT 24
Peak memory 204152 kb
Host smart-81e3ba31-ac1d-43d7-970e-269442d5a50b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40639
83624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.4063983624
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2183534915
Short name T1367
Test name
Test status
Simulation time 8414928918 ps
CPU time 7.73 seconds
Started Apr 25 02:35:44 PM PDT 24
Finished Apr 25 02:35:53 PM PDT 24
Peak memory 204072 kb
Host smart-f1f3aefe-2b28-4c24-8a87-b4a90709628b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21835
34915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2183534915
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_enable.1878666027
Short name T662
Test name
Test status
Simulation time 8373857724 ps
CPU time 7.44 seconds
Started Apr 25 02:35:41 PM PDT 24
Finished Apr 25 02:35:50 PM PDT 24
Peak memory 204044 kb
Host smart-7ced43b7-fe40-4e3e-84e6-5c629ba314ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18786
66027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.1878666027
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.2237814586
Short name T1188
Test name
Test status
Simulation time 59453190 ps
CPU time 1.32 seconds
Started Apr 25 02:35:50 PM PDT 24
Finished Apr 25 02:35:52 PM PDT 24
Peak memory 204156 kb
Host smart-d2068401-32a4-445a-92b9-0c9971f17fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22378
14586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.2237814586
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.117946677
Short name T1195
Test name
Test status
Simulation time 8411476826 ps
CPU time 7.97 seconds
Started Apr 25 02:35:56 PM PDT 24
Finished Apr 25 02:36:04 PM PDT 24
Peak memory 204080 kb
Host smart-5b0f89c2-ca85-4552-a62b-a89d9415db46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11794
6677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.117946677
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.3191748453
Short name T195
Test name
Test status
Simulation time 8371300594 ps
CPU time 7.44 seconds
Started Apr 25 02:35:46 PM PDT 24
Finished Apr 25 02:35:55 PM PDT 24
Peak memory 204040 kb
Host smart-cadd1f45-1aa8-4b88-b029-3fe36e87d036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31917
48453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.3191748453
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.414413065
Short name T484
Test name
Test status
Simulation time 8451680052 ps
CPU time 8.38 seconds
Started Apr 25 02:35:40 PM PDT 24
Finished Apr 25 02:35:49 PM PDT 24
Peak memory 204116 kb
Host smart-e7acbc20-d362-4349-8189-3edb241f1c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41441
3065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.414413065
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.3123816813
Short name T912
Test name
Test status
Simulation time 8419708093 ps
CPU time 7.76 seconds
Started Apr 25 02:35:39 PM PDT 24
Finished Apr 25 02:35:48 PM PDT 24
Peak memory 204108 kb
Host smart-2b303e8f-4a28-4467-8ef2-865a40db771d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31238
16813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.3123816813
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.3035833982
Short name T355
Test name
Test status
Simulation time 8381335902 ps
CPU time 7.66 seconds
Started Apr 25 02:35:42 PM PDT 24
Finished Apr 25 02:35:51 PM PDT 24
Peak memory 204108 kb
Host smart-da72c557-dcdb-4767-950e-3acbbc7bbb3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30358
33982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.3035833982
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.2357908667
Short name T1237
Test name
Test status
Simulation time 8401595793 ps
CPU time 8.2 seconds
Started Apr 25 02:35:42 PM PDT 24
Finished Apr 25 02:35:51 PM PDT 24
Peak memory 204156 kb
Host smart-e3970724-c11e-4bd7-a28a-77757b4bc6db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23579
08667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.2357908667
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.1988112526
Short name T82
Test name
Test status
Simulation time 8428280319 ps
CPU time 9.54 seconds
Started Apr 25 02:35:48 PM PDT 24
Finished Apr 25 02:35:59 PM PDT 24
Peak memory 204032 kb
Host smart-ae2abd30-8f55-4f77-85ce-542878aa7bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19881
12526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.1988112526
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.3582205870
Short name T487
Test name
Test status
Simulation time 8387981764 ps
CPU time 7.91 seconds
Started Apr 25 02:35:45 PM PDT 24
Finished Apr 25 02:35:54 PM PDT 24
Peak memory 204112 kb
Host smart-1873cdb3-a59f-4b07-b947-3ce060d35b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35822
05870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.3582205870
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.1660195984
Short name T1298
Test name
Test status
Simulation time 8396887154 ps
CPU time 8.25 seconds
Started Apr 25 02:35:46 PM PDT 24
Finished Apr 25 02:35:55 PM PDT 24
Peak memory 204092 kb
Host smart-f8efe0c7-9310-43b8-a431-293e61976820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16601
95984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.1660195984
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.1914018491
Short name T638
Test name
Test status
Simulation time 8374113401 ps
CPU time 8.25 seconds
Started Apr 25 02:35:47 PM PDT 24
Finished Apr 25 02:35:57 PM PDT 24
Peak memory 204044 kb
Host smart-2bb9900b-e8fb-4808-8762-f04fddf53575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19140
18491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.1914018491
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.209007185
Short name T972
Test name
Test status
Simulation time 65537520 ps
CPU time 0.67 seconds
Started Apr 25 02:35:47 PM PDT 24
Finished Apr 25 02:35:49 PM PDT 24
Peak memory 203972 kb
Host smart-023b7a71-6890-4481-9130-6aa6f6ef9369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20900
7185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.209007185
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.637942725
Short name T262
Test name
Test status
Simulation time 32205719588 ps
CPU time 63.88 seconds
Started Apr 25 02:35:47 PM PDT 24
Finished Apr 25 02:36:52 PM PDT 24
Peak memory 204412 kb
Host smart-52861dbb-47ed-4511-b814-207ebed28d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63794
2725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.637942725
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.230250210
Short name T869
Test name
Test status
Simulation time 8396025848 ps
CPU time 7.81 seconds
Started Apr 25 02:35:46 PM PDT 24
Finished Apr 25 02:35:55 PM PDT 24
Peak memory 204108 kb
Host smart-4085a5d4-d891-4ab0-bde9-5406a8f0759b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23025
0210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.230250210
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.2768406074
Short name T1238
Test name
Test status
Simulation time 8437317188 ps
CPU time 7.69 seconds
Started Apr 25 02:35:56 PM PDT 24
Finished Apr 25 02:36:04 PM PDT 24
Peak memory 204076 kb
Host smart-a9806fc5-d5e0-4bd9-8043-f9ee5b367e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27684
06074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2768406074
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.4124025604
Short name T548
Test name
Test status
Simulation time 8428057911 ps
CPU time 7.72 seconds
Started Apr 25 02:35:48 PM PDT 24
Finished Apr 25 02:35:57 PM PDT 24
Peak memory 204028 kb
Host smart-a31799e2-d8ac-46b1-a28f-f7e62259e9b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41240
25604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.4124025604
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.2423646026
Short name T1133
Test name
Test status
Simulation time 8388334800 ps
CPU time 8.11 seconds
Started Apr 25 02:35:48 PM PDT 24
Finished Apr 25 02:35:57 PM PDT 24
Peak memory 204140 kb
Host smart-7fab70d6-989c-4e76-8b09-37f2031302b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24236
46026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.2423646026
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2961373631
Short name T1374
Test name
Test status
Simulation time 8369327144 ps
CPU time 9.1 seconds
Started Apr 25 02:35:45 PM PDT 24
Finished Apr 25 02:35:55 PM PDT 24
Peak memory 204028 kb
Host smart-c853153c-2737-4dea-b710-1d7a32e4e871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29613
73631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2961373631
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2209227208
Short name T1067
Test name
Test status
Simulation time 8426774290 ps
CPU time 8.72 seconds
Started Apr 25 02:35:41 PM PDT 24
Finished Apr 25 02:35:51 PM PDT 24
Peak memory 204144 kb
Host smart-f1686031-b6a1-42ef-b933-c1b1593a95f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22092
27208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2209227208
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2700227394
Short name T256
Test name
Test status
Simulation time 8381672241 ps
CPU time 8.85 seconds
Started Apr 25 02:35:50 PM PDT 24
Finished Apr 25 02:36:00 PM PDT 24
Peak memory 204124 kb
Host smart-a243a848-69ff-41c9-9673-4c1b2dbc0b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27002
27394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2700227394
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.2073056521
Short name T1240
Test name
Test status
Simulation time 8382723606 ps
CPU time 9.18 seconds
Started Apr 25 02:35:48 PM PDT 24
Finished Apr 25 02:35:58 PM PDT 24
Peak memory 204140 kb
Host smart-4785fa5e-be51-4f6c-80b6-3018d7f52d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20730
56521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.2073056521
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.2846284389
Short name T1109
Test name
Test status
Simulation time 8525936936 ps
CPU time 8.25 seconds
Started Apr 25 02:36:00 PM PDT 24
Finished Apr 25 02:36:09 PM PDT 24
Peak memory 204092 kb
Host smart-c29a093a-e24c-4bc9-8d67-8d01cbbe84c2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2846284389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.2846284389
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.4137024017
Short name T1056
Test name
Test status
Simulation time 8382004718 ps
CPU time 8.25 seconds
Started Apr 25 02:35:54 PM PDT 24
Finished Apr 25 02:36:04 PM PDT 24
Peak memory 204140 kb
Host smart-21520c5c-790c-47b9-96dc-c71edabc7e34
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4137024017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.4137024017
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.4273023914
Short name T511
Test name
Test status
Simulation time 8423403692 ps
CPU time 8.49 seconds
Started Apr 25 02:35:52 PM PDT 24
Finished Apr 25 02:36:02 PM PDT 24
Peak memory 204152 kb
Host smart-1afaba91-dec2-448d-85cd-9d1d51735de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42730
23914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.4273023914
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.1089398565
Short name T361
Test name
Test status
Simulation time 8378336273 ps
CPU time 8.55 seconds
Started Apr 25 02:35:48 PM PDT 24
Finished Apr 25 02:35:58 PM PDT 24
Peak memory 204164 kb
Host smart-33b2b347-e533-4f52-9d48-a7527ea98c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10893
98565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1089398565
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_enable.1750125060
Short name T649
Test name
Test status
Simulation time 8373911158 ps
CPU time 8.42 seconds
Started Apr 25 02:35:46 PM PDT 24
Finished Apr 25 02:35:55 PM PDT 24
Peak memory 204144 kb
Host smart-1e2c044e-327e-49a7-9c2c-31b0c88db9e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17501
25060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1750125060
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.2893703921
Short name T1051
Test name
Test status
Simulation time 81197693 ps
CPU time 2.03 seconds
Started Apr 25 02:35:45 PM PDT 24
Finished Apr 25 02:35:48 PM PDT 24
Peak memory 204276 kb
Host smart-3e82e52a-6757-4ea4-b43d-e374761fbc24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28937
03921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.2893703921
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.2408533078
Short name T162
Test name
Test status
Simulation time 8417908223 ps
CPU time 10.18 seconds
Started Apr 25 02:35:53 PM PDT 24
Finished Apr 25 02:36:05 PM PDT 24
Peak memory 204064 kb
Host smart-c78e99f8-edc3-4867-90f2-e45295f409de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24085
33078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.2408533078
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.267543258
Short name T203
Test name
Test status
Simulation time 8362246126 ps
CPU time 8.01 seconds
Started Apr 25 02:35:59 PM PDT 24
Finished Apr 25 02:36:08 PM PDT 24
Peak memory 204076 kb
Host smart-9265990f-7d61-4b7e-aaf2-0eb3979b6be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26754
3258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.267543258
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1702036867
Short name T614
Test name
Test status
Simulation time 8406776164 ps
CPU time 8.81 seconds
Started Apr 25 02:35:47 PM PDT 24
Finished Apr 25 02:35:57 PM PDT 24
Peak memory 204148 kb
Host smart-5321a956-3be5-46f6-9f01-bdcbe9139344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17020
36867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1702036867
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2635260312
Short name T538
Test name
Test status
Simulation time 8411216930 ps
CPU time 8.69 seconds
Started Apr 25 02:35:47 PM PDT 24
Finished Apr 25 02:35:57 PM PDT 24
Peak memory 204144 kb
Host smart-00b4f1e9-60ca-468e-aab6-367d179f8ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26352
60312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2635260312
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.2227429957
Short name T257
Test name
Test status
Simulation time 8370300047 ps
CPU time 7.66 seconds
Started Apr 25 02:35:49 PM PDT 24
Finished Apr 25 02:35:57 PM PDT 24
Peak memory 204156 kb
Host smart-41291e3d-aaa9-4b50-bfe0-b4e5a1df6f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22274
29957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.2227429957
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.2798892471
Short name T122
Test name
Test status
Simulation time 8422572341 ps
CPU time 8.65 seconds
Started Apr 25 02:35:54 PM PDT 24
Finished Apr 25 02:36:05 PM PDT 24
Peak memory 204140 kb
Host smart-443f5252-1433-409e-bf4b-086b007832ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27988
92471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2798892471
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.3245985767
Short name T581
Test name
Test status
Simulation time 8406083134 ps
CPU time 9.67 seconds
Started Apr 25 02:35:54 PM PDT 24
Finished Apr 25 02:36:04 PM PDT 24
Peak memory 204052 kb
Host smart-45939935-0e30-4cab-91e7-efccf431774d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32459
85767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.3245985767
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3788864334
Short name T444
Test name
Test status
Simulation time 8391598612 ps
CPU time 7.99 seconds
Started Apr 25 02:35:52 PM PDT 24
Finished Apr 25 02:36:01 PM PDT 24
Peak memory 204116 kb
Host smart-a6314c9d-aae7-4661-b5ac-7042e103dd8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37888
64334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3788864334
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.1239183855
Short name T889
Test name
Test status
Simulation time 8401286954 ps
CPU time 7.74 seconds
Started Apr 25 02:35:54 PM PDT 24
Finished Apr 25 02:36:03 PM PDT 24
Peak memory 204104 kb
Host smart-2eb287c5-d384-4eb8-bdc9-8eaa175967a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12391
83855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.1239183855
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.4133356278
Short name T553
Test name
Test status
Simulation time 8374689154 ps
CPU time 7.46 seconds
Started Apr 25 02:35:59 PM PDT 24
Finished Apr 25 02:36:07 PM PDT 24
Peak memory 204096 kb
Host smart-83554d2e-0f24-4870-9001-a521093839f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41333
56278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.4133356278
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.60193060
Short name T1341
Test name
Test status
Simulation time 43050191 ps
CPU time 0.65 seconds
Started Apr 25 02:35:53 PM PDT 24
Finished Apr 25 02:35:54 PM PDT 24
Peak memory 204012 kb
Host smart-e7a0a736-5113-4d33-ba8c-aa157d537bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60193
060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.60193060
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.437789497
Short name T263
Test name
Test status
Simulation time 27482815350 ps
CPU time 59.46 seconds
Started Apr 25 02:35:52 PM PDT 24
Finished Apr 25 02:36:52 PM PDT 24
Peak memory 204424 kb
Host smart-fab50c79-ce3e-4955-8bde-877e5c06b850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43778
9497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.437789497
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.3465567135
Short name T482
Test name
Test status
Simulation time 8396946428 ps
CPU time 8.15 seconds
Started Apr 25 02:35:54 PM PDT 24
Finished Apr 25 02:36:03 PM PDT 24
Peak memory 204140 kb
Host smart-6b791a3d-7088-4627-a702-29049c17a96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34655
67135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.3465567135
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.199786328
Short name T692
Test name
Test status
Simulation time 8377239500 ps
CPU time 7.89 seconds
Started Apr 25 02:35:52 PM PDT 24
Finished Apr 25 02:36:00 PM PDT 24
Peak memory 204120 kb
Host smart-9dc3bcc3-5324-40ec-bfc5-c08200374ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19978
6328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.199786328
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.3295682769
Short name T584
Test name
Test status
Simulation time 8438121573 ps
CPU time 8.04 seconds
Started Apr 25 02:35:52 PM PDT 24
Finished Apr 25 02:36:00 PM PDT 24
Peak memory 204088 kb
Host smart-8655ac4f-fbe1-4999-9b49-601ae04a2091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32956
82769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.3295682769
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.772348817
Short name T804
Test name
Test status
Simulation time 8376696512 ps
CPU time 7.88 seconds
Started Apr 25 02:36:00 PM PDT 24
Finished Apr 25 02:36:08 PM PDT 24
Peak memory 204092 kb
Host smart-796413cf-6f0f-4173-90be-017a173d1fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77234
8817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.772348817
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3679565047
Short name T957
Test name
Test status
Simulation time 8409178962 ps
CPU time 7.54 seconds
Started Apr 25 02:35:51 PM PDT 24
Finished Apr 25 02:35:59 PM PDT 24
Peak memory 204016 kb
Host smart-fca8bb3f-bbe7-4d55-915f-961cdf349887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36795
65047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3679565047
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.3550920742
Short name T578
Test name
Test status
Simulation time 8441014224 ps
CPU time 8.26 seconds
Started Apr 25 02:35:46 PM PDT 24
Finished Apr 25 02:35:55 PM PDT 24
Peak memory 204120 kb
Host smart-d023e495-6ed1-4c9d-bfe1-9981955f46f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35509
20742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.3550920742
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.4067254111
Short name T324
Test name
Test status
Simulation time 8448075373 ps
CPU time 8.92 seconds
Started Apr 25 02:35:54 PM PDT 24
Finished Apr 25 02:36:04 PM PDT 24
Peak memory 204112 kb
Host smart-fee429db-8de3-4d60-b2a2-2aa59a66dca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40672
54111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.4067254111
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.3279842592
Short name T1170
Test name
Test status
Simulation time 8383886426 ps
CPU time 7.93 seconds
Started Apr 25 02:35:53 PM PDT 24
Finished Apr 25 02:36:01 PM PDT 24
Peak memory 204116 kb
Host smart-bf79d3da-e209-4dd9-9b52-10e2bf77e725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32798
42592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.3279842592
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.1616308217
Short name T1302
Test name
Test status
Simulation time 8541067784 ps
CPU time 7.89 seconds
Started Apr 25 02:36:05 PM PDT 24
Finished Apr 25 02:36:15 PM PDT 24
Peak memory 204188 kb
Host smart-5355f5e6-6fd7-4810-83b7-db5c411bf365
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1616308217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.1616308217
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.1069810960
Short name T422
Test name
Test status
Simulation time 8389171993 ps
CPU time 8.5 seconds
Started Apr 25 02:36:07 PM PDT 24
Finished Apr 25 02:36:18 PM PDT 24
Peak memory 204144 kb
Host smart-58434c4c-dccc-46d6-a1c3-470ac6a9bc20
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1069810960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.1069810960
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.713574208
Short name T1265
Test name
Test status
Simulation time 8448412380 ps
CPU time 8.38 seconds
Started Apr 25 02:36:05 PM PDT 24
Finished Apr 25 02:36:15 PM PDT 24
Peak memory 204152 kb
Host smart-34ee6f65-7415-4831-9c77-b2e1f8d3d69a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71357
4208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.713574208
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.605431437
Short name T1256
Test name
Test status
Simulation time 8383752378 ps
CPU time 8.64 seconds
Started Apr 25 02:36:00 PM PDT 24
Finished Apr 25 02:36:10 PM PDT 24
Peak memory 204136 kb
Host smart-a16e4e16-7627-4aae-9332-d8d88fea494d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60543
1437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.605431437
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_enable.754899256
Short name T396
Test name
Test status
Simulation time 8369880534 ps
CPU time 8.02 seconds
Started Apr 25 02:36:01 PM PDT 24
Finished Apr 25 02:36:10 PM PDT 24
Peak memory 204144 kb
Host smart-0020ad36-5299-48a5-8a06-28a5a7fd3763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75489
9256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.754899256
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.342665207
Short name T853
Test name
Test status
Simulation time 127199624 ps
CPU time 1.55 seconds
Started Apr 25 02:36:00 PM PDT 24
Finished Apr 25 02:36:02 PM PDT 24
Peak memory 204240 kb
Host smart-60768410-9bdd-40c8-8984-f0e54c734aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34266
5207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.342665207
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.3822965960
Short name T448
Test name
Test status
Simulation time 8407003985 ps
CPU time 7.86 seconds
Started Apr 25 02:36:06 PM PDT 24
Finished Apr 25 02:36:16 PM PDT 24
Peak memory 204072 kb
Host smart-c6482475-bc1c-49be-8684-d7c5ab0136af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38229
65960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.3822965960
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.3239694717
Short name T1106
Test name
Test status
Simulation time 8370237120 ps
CPU time 7.98 seconds
Started Apr 25 02:36:07 PM PDT 24
Finished Apr 25 02:36:17 PM PDT 24
Peak memory 204052 kb
Host smart-19dbf5ec-e501-4c9d-9095-ae6b530c3317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32396
94717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.3239694717
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3701577796
Short name T768
Test name
Test status
Simulation time 8451928500 ps
CPU time 7.99 seconds
Started Apr 25 02:36:08 PM PDT 24
Finished Apr 25 02:36:18 PM PDT 24
Peak memory 204076 kb
Host smart-0a9ba636-3a54-4ce3-9be7-a07226abb5b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37015
77796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3701577796
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.450257862
Short name T863
Test name
Test status
Simulation time 8414234255 ps
CPU time 9.54 seconds
Started Apr 25 02:35:58 PM PDT 24
Finished Apr 25 02:36:08 PM PDT 24
Peak memory 204128 kb
Host smart-dc2bd836-8b99-498d-9f79-80499464bf12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45025
7862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.450257862
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3755423279
Short name T1158
Test name
Test status
Simulation time 8372625681 ps
CPU time 10.2 seconds
Started Apr 25 02:35:59 PM PDT 24
Finished Apr 25 02:36:10 PM PDT 24
Peak memory 204116 kb
Host smart-8d67784e-81c0-433a-bd3d-386e52d47975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37554
23279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3755423279
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.64262186
Short name T108
Test name
Test status
Simulation time 8469337845 ps
CPU time 7.8 seconds
Started Apr 25 02:36:09 PM PDT 24
Finished Apr 25 02:36:18 PM PDT 24
Peak memory 204072 kb
Host smart-9ab4643e-c97a-42a8-9d47-7018d5ef42d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64262
186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.64262186
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.2007610426
Short name T253
Test name
Test status
Simulation time 8423232908 ps
CPU time 9.56 seconds
Started Apr 25 02:36:01 PM PDT 24
Finished Apr 25 02:36:12 PM PDT 24
Peak memory 204148 kb
Host smart-f2395090-47bf-4b6b-b2e2-057475f9286a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20076
10426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.2007610426
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.1492286045
Short name T734
Test name
Test status
Simulation time 8421603253 ps
CPU time 9.97 seconds
Started Apr 25 02:36:10 PM PDT 24
Finished Apr 25 02:36:21 PM PDT 24
Peak memory 204092 kb
Host smart-74c8bf6f-d237-4a26-9b13-77cb4c1729e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14922
86045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.1492286045
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.2372407055
Short name T85
Test name
Test status
Simulation time 8407845032 ps
CPU time 7.97 seconds
Started Apr 25 02:36:01 PM PDT 24
Finished Apr 25 02:36:11 PM PDT 24
Peak memory 204060 kb
Host smart-81bc1465-5637-4277-9fe8-d9d37cd514a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23724
07055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.2372407055
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.633035081
Short name T8
Test name
Test status
Simulation time 8376955968 ps
CPU time 8.39 seconds
Started Apr 25 02:35:59 PM PDT 24
Finished Apr 25 02:36:08 PM PDT 24
Peak memory 204084 kb
Host smart-2f152262-0fdb-48f5-8d5f-fc90efd08526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63303
5081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.633035081
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.1647202563
Short name T1208
Test name
Test status
Simulation time 54856340 ps
CPU time 0.72 seconds
Started Apr 25 02:36:05 PM PDT 24
Finished Apr 25 02:36:06 PM PDT 24
Peak memory 203972 kb
Host smart-ccff5b98-c6c9-457d-bf9c-5cf41e1e9f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16472
02563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.1647202563
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.2507500056
Short name T284
Test name
Test status
Simulation time 22409706080 ps
CPU time 44.62 seconds
Started Apr 25 02:36:04 PM PDT 24
Finished Apr 25 02:36:49 PM PDT 24
Peak memory 204372 kb
Host smart-fa7489f2-c36c-4e43-916b-89f6e5d25d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25075
00056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.2507500056
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.2577362523
Short name T489
Test name
Test status
Simulation time 8394053555 ps
CPU time 7.97 seconds
Started Apr 25 02:36:01 PM PDT 24
Finished Apr 25 02:36:10 PM PDT 24
Peak memory 204068 kb
Host smart-2479002f-7446-479c-99aa-78a63988a188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25773
62523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.2577362523
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1404757107
Short name T737
Test name
Test status
Simulation time 8414860937 ps
CPU time 9.23 seconds
Started Apr 25 02:36:10 PM PDT 24
Finished Apr 25 02:36:20 PM PDT 24
Peak memory 204076 kb
Host smart-672631fc-7b72-4012-87df-451873484b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14047
57107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1404757107
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.2226054178
Short name T788
Test name
Test status
Simulation time 8431580788 ps
CPU time 8.26 seconds
Started Apr 25 02:35:59 PM PDT 24
Finished Apr 25 02:36:09 PM PDT 24
Peak memory 204140 kb
Host smart-c7611fa8-929d-44fc-8ddc-814c33efaeee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22260
54178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.2226054178
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.1676954478
Short name T645
Test name
Test status
Simulation time 8375165071 ps
CPU time 8.38 seconds
Started Apr 25 02:36:00 PM PDT 24
Finished Apr 25 02:36:10 PM PDT 24
Peak memory 204096 kb
Host smart-24255ab8-aaa3-453d-9d53-ab06e2b57bf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16769
54478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.1676954478
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.619465737
Short name T341
Test name
Test status
Simulation time 8374423173 ps
CPU time 7.73 seconds
Started Apr 25 02:36:00 PM PDT 24
Finished Apr 25 02:36:09 PM PDT 24
Peak memory 204116 kb
Host smart-837c0ab1-5330-4325-b9a9-96319953784a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61946
5737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.619465737
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.2566309404
Short name T741
Test name
Test status
Simulation time 8448951322 ps
CPU time 8.02 seconds
Started Apr 25 02:36:01 PM PDT 24
Finished Apr 25 02:36:10 PM PDT 24
Peak memory 204048 kb
Host smart-e308f962-6f51-4177-820c-66707a851635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25663
09404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.2566309404
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2937190762
Short name T281
Test name
Test status
Simulation time 8391666454 ps
CPU time 7.74 seconds
Started Apr 25 02:36:00 PM PDT 24
Finished Apr 25 02:36:10 PM PDT 24
Peak memory 204144 kb
Host smart-c806525c-687a-4f8b-bcf7-bed984c54020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29371
90762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.2937190762
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.570487491
Short name T742
Test name
Test status
Simulation time 8425428668 ps
CPU time 7.54 seconds
Started Apr 25 02:35:59 PM PDT 24
Finished Apr 25 02:36:08 PM PDT 24
Peak memory 204124 kb
Host smart-9eb1d8db-076d-453e-a33a-fc52d8400b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57048
7491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.570487491
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.max_length_in_transaction.3642873319
Short name T404
Test name
Test status
Simulation time 8465053577 ps
CPU time 8.61 seconds
Started Apr 25 02:36:13 PM PDT 24
Finished Apr 25 02:36:23 PM PDT 24
Peak memory 204132 kb
Host smart-eb310b91-c29c-45ff-baf1-cdd29e1ea435
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3642873319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.3642873319
Directory /workspace/45.max_length_in_transaction/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.2958138812
Short name T1278
Test name
Test status
Simulation time 8384515620 ps
CPU time 7.66 seconds
Started Apr 25 02:36:06 PM PDT 24
Finished Apr 25 02:36:15 PM PDT 24
Peak memory 204152 kb
Host smart-cf4b7154-5316-425e-8af3-735ce0ed2d5d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2958138812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.2958138812
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.random_length_in_trans.509857021
Short name T457
Test name
Test status
Simulation time 8457804914 ps
CPU time 8.92 seconds
Started Apr 25 02:36:06 PM PDT 24
Finished Apr 25 02:36:17 PM PDT 24
Peak memory 204104 kb
Host smart-008686b2-0e1f-4dfe-ab74-51a31014c941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50985
7021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.509857021
Directory /workspace/45.random_length_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.1006849759
Short name T1305
Test name
Test status
Simulation time 8388818580 ps
CPU time 8.47 seconds
Started Apr 25 02:36:09 PM PDT 24
Finished Apr 25 02:36:19 PM PDT 24
Peak memory 204148 kb
Host smart-c2fca444-6f22-46ea-bf1b-b4c2b1e669a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10068
49759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.1006849759
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_enable.162714462
Short name T394
Test name
Test status
Simulation time 8373849063 ps
CPU time 7.38 seconds
Started Apr 25 02:36:06 PM PDT 24
Finished Apr 25 02:36:16 PM PDT 24
Peak memory 204100 kb
Host smart-013a0f0f-2da4-494e-9d4d-632449779cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16271
4462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.162714462
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.1996067839
Short name T758
Test name
Test status
Simulation time 240444975 ps
CPU time 2.09 seconds
Started Apr 25 02:36:07 PM PDT 24
Finished Apr 25 02:36:11 PM PDT 24
Peak memory 204164 kb
Host smart-f059721d-7f7a-4297-b372-0d0cf367222b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19960
67839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1996067839
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.754589504
Short name T1245
Test name
Test status
Simulation time 8363904686 ps
CPU time 7.56 seconds
Started Apr 25 02:36:11 PM PDT 24
Finished Apr 25 02:36:20 PM PDT 24
Peak memory 204112 kb
Host smart-180bf115-2a4c-463d-bea0-c3df8e0e3df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75458
9504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.754589504
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.3566069895
Short name T74
Test name
Test status
Simulation time 8458657874 ps
CPU time 7.88 seconds
Started Apr 25 02:36:07 PM PDT 24
Finished Apr 25 02:36:17 PM PDT 24
Peak memory 204148 kb
Host smart-5c0c7ba4-eacb-4cd9-9598-9ae7b1c68129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35660
69895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3566069895
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.1525600040
Short name T1338
Test name
Test status
Simulation time 8425061856 ps
CPU time 8.23 seconds
Started Apr 25 02:36:05 PM PDT 24
Finished Apr 25 02:36:14 PM PDT 24
Peak memory 204136 kb
Host smart-049f85f9-d630-4ea3-821b-6e865f2cb334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15256
00040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.1525600040
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2353975196
Short name T1215
Test name
Test status
Simulation time 8393421610 ps
CPU time 7.97 seconds
Started Apr 25 02:36:09 PM PDT 24
Finished Apr 25 02:36:18 PM PDT 24
Peak memory 204140 kb
Host smart-2748af8d-8378-4614-b2a8-c40196b90e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23539
75196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2353975196
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2139803552
Short name T109
Test name
Test status
Simulation time 8429478544 ps
CPU time 8.96 seconds
Started Apr 25 02:36:06 PM PDT 24
Finished Apr 25 02:36:17 PM PDT 24
Peak memory 204128 kb
Host smart-592d8ac6-85b6-44ee-870f-973c1973ba3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21398
03552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2139803552
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.728692189
Short name T760
Test name
Test status
Simulation time 8426836899 ps
CPU time 7.45 seconds
Started Apr 25 02:36:09 PM PDT 24
Finished Apr 25 02:36:18 PM PDT 24
Peak memory 204140 kb
Host smart-efc40432-a676-40d6-93f0-bc96c261a725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72869
2189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.728692189
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.994873754
Short name T67
Test name
Test status
Simulation time 8403725782 ps
CPU time 8.49 seconds
Started Apr 25 02:36:11 PM PDT 24
Finished Apr 25 02:36:20 PM PDT 24
Peak memory 204104 kb
Host smart-cd2eb073-41f7-4de5-921e-d999a52feeed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99487
3754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.994873754
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.3098367035
Short name T223
Test name
Test status
Simulation time 8397074404 ps
CPU time 7.8 seconds
Started Apr 25 02:36:07 PM PDT 24
Finished Apr 25 02:36:17 PM PDT 24
Peak memory 204136 kb
Host smart-d883ddc9-262c-4faf-ac3b-069a77fc6357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30983
67035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.3098367035
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.3405114716
Short name T1344
Test name
Test status
Simulation time 8371337730 ps
CPU time 7.7 seconds
Started Apr 25 02:36:07 PM PDT 24
Finished Apr 25 02:36:17 PM PDT 24
Peak memory 204112 kb
Host smart-72748f67-9ea1-4d75-a46a-2935a9f174a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34051
14716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.3405114716
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.4063506448
Short name T514
Test name
Test status
Simulation time 35291519 ps
CPU time 0.64 seconds
Started Apr 25 02:36:05 PM PDT 24
Finished Apr 25 02:36:07 PM PDT 24
Peak memory 203988 kb
Host smart-548b24e4-d83e-4a31-8b64-8d7a4b265ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40635
06448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.4063506448
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.1406799645
Short name T1355
Test name
Test status
Simulation time 8410685255 ps
CPU time 8.4 seconds
Started Apr 25 02:36:11 PM PDT 24
Finished Apr 25 02:36:21 PM PDT 24
Peak memory 204104 kb
Host smart-b8b15303-5725-4536-ad75-47ab7a8f00ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14067
99645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.1406799645
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.2842794849
Short name T1102
Test name
Test status
Simulation time 8465199548 ps
CPU time 10.17 seconds
Started Apr 25 02:36:08 PM PDT 24
Finished Apr 25 02:36:20 PM PDT 24
Peak memory 204072 kb
Host smart-a72f6de2-dfc5-43b7-ab2b-0f30d4f3b3a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28427
94849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.2842794849
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.237815589
Short name T960
Test name
Test status
Simulation time 8420552145 ps
CPU time 8.2 seconds
Started Apr 25 02:36:05 PM PDT 24
Finished Apr 25 02:36:15 PM PDT 24
Peak memory 204044 kb
Host smart-797fae6d-7776-40d7-a514-28e5566f5e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23781
5589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.237815589
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.3009600644
Short name T1276
Test name
Test status
Simulation time 8380014012 ps
CPU time 9.63 seconds
Started Apr 25 02:36:06 PM PDT 24
Finished Apr 25 02:36:17 PM PDT 24
Peak memory 204112 kb
Host smart-73731133-5362-4a28-ade8-69c9c63d6072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30096
00644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.3009600644
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.3221503317
Short name T1185
Test name
Test status
Simulation time 8367894723 ps
CPU time 8.59 seconds
Started Apr 25 02:36:08 PM PDT 24
Finished Apr 25 02:36:19 PM PDT 24
Peak memory 204124 kb
Host smart-b2c2bdb9-d2b9-4178-a53e-2819b1cfc7e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32215
03317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.3221503317
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.2826271648
Short name T1175
Test name
Test status
Simulation time 8447759438 ps
CPU time 8.03 seconds
Started Apr 25 02:36:12 PM PDT 24
Finished Apr 25 02:36:21 PM PDT 24
Peak memory 204124 kb
Host smart-a7d122e9-c8b4-46b7-84f9-16c4d4a70022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28262
71648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.2826271648
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.1665509278
Short name T1297
Test name
Test status
Simulation time 8406941392 ps
CPU time 7.38 seconds
Started Apr 25 02:36:05 PM PDT 24
Finished Apr 25 02:36:15 PM PDT 24
Peak memory 204052 kb
Host smart-65cba1a7-ab09-4e43-a870-a0592414ba19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16655
09278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.1665509278
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.1970781382
Short name T550
Test name
Test status
Simulation time 8376945491 ps
CPU time 7.97 seconds
Started Apr 25 02:36:06 PM PDT 24
Finished Apr 25 02:36:16 PM PDT 24
Peak memory 204088 kb
Host smart-493ac668-6608-4af7-97ba-c21f46c72423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19707
81382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.1970781382
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.587999566
Short name T1060
Test name
Test status
Simulation time 8475038478 ps
CPU time 8.02 seconds
Started Apr 25 02:36:15 PM PDT 24
Finished Apr 25 02:36:24 PM PDT 24
Peak memory 204140 kb
Host smart-48685317-2004-44bd-83b0-60dbac5879da
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=587999566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.587999566
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.2227671209
Short name T932
Test name
Test status
Simulation time 8378370945 ps
CPU time 10.31 seconds
Started Apr 25 02:36:11 PM PDT 24
Finished Apr 25 02:36:23 PM PDT 24
Peak memory 204148 kb
Host smart-a8de0f7a-e360-4601-96b7-3c15834161be
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2227671209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.2227671209
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.1310886830
Short name T534
Test name
Test status
Simulation time 8397935390 ps
CPU time 8.09 seconds
Started Apr 25 02:36:12 PM PDT 24
Finished Apr 25 02:36:21 PM PDT 24
Peak memory 204136 kb
Host smart-df55d116-b3e6-49a7-9e93-c3da4e425b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13108
86830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.1310886830
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.4243415142
Short name T698
Test name
Test status
Simulation time 8373445539 ps
CPU time 7.54 seconds
Started Apr 25 02:36:14 PM PDT 24
Finished Apr 25 02:36:23 PM PDT 24
Peak memory 204132 kb
Host smart-8b15db9f-2d05-489b-aab4-89f1b8e22527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42434
15142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.4243415142
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_enable.4014127486
Short name T79
Test name
Test status
Simulation time 8385529317 ps
CPU time 9.49 seconds
Started Apr 25 02:36:18 PM PDT 24
Finished Apr 25 02:36:29 PM PDT 24
Peak memory 204112 kb
Host smart-1dc4134d-061a-4eae-b03c-9ef70c6ecbff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40141
27486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.4014127486
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.1485675587
Short name T1258
Test name
Test status
Simulation time 213248840 ps
CPU time 2.24 seconds
Started Apr 25 02:36:16 PM PDT 24
Finished Apr 25 02:36:20 PM PDT 24
Peak memory 204232 kb
Host smart-6dcb456b-710c-435c-bfde-a526e4edf74c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14856
75587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.1485675587
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.2260383946
Short name T1187
Test name
Test status
Simulation time 8411436399 ps
CPU time 8.68 seconds
Started Apr 25 02:36:15 PM PDT 24
Finished Apr 25 02:36:25 PM PDT 24
Peak memory 204108 kb
Host smart-c9cd54c4-d70e-482a-945d-ffcb1e29785a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22603
83946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.2260383946
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.4480928
Short name T566
Test name
Test status
Simulation time 8376287230 ps
CPU time 7.87 seconds
Started Apr 25 02:36:14 PM PDT 24
Finished Apr 25 02:36:24 PM PDT 24
Peak memory 204112 kb
Host smart-df5dc4d7-fc87-4137-a41f-80f4cf9caa8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44809
28 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.4480928
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.680370088
Short name T1177
Test name
Test status
Simulation time 8433561536 ps
CPU time 7.85 seconds
Started Apr 25 02:36:12 PM PDT 24
Finished Apr 25 02:36:22 PM PDT 24
Peak memory 204028 kb
Host smart-0be419e1-daf5-4c34-b8c0-03fb22fb6273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68037
0088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.680370088
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2799191708
Short name T407
Test name
Test status
Simulation time 8418927447 ps
CPU time 8.91 seconds
Started Apr 25 02:36:12 PM PDT 24
Finished Apr 25 02:36:23 PM PDT 24
Peak memory 204060 kb
Host smart-bb69f1dc-ed27-44c9-91c8-0787677ff87b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27991
91708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2799191708
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.3021713261
Short name T837
Test name
Test status
Simulation time 8394895683 ps
CPU time 8.15 seconds
Started Apr 25 02:36:13 PM PDT 24
Finished Apr 25 02:36:23 PM PDT 24
Peak memory 204184 kb
Host smart-676cf5b0-3022-41b7-8e95-eb5fdbc628e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30217
13261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.3021713261
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1982208027
Short name T119
Test name
Test status
Simulation time 8448743037 ps
CPU time 7.81 seconds
Started Apr 25 02:36:13 PM PDT 24
Finished Apr 25 02:36:22 PM PDT 24
Peak memory 204112 kb
Host smart-06474e44-4c0f-4081-8705-4acdf9492906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19822
08027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1982208027
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.422405555
Short name T953
Test name
Test status
Simulation time 8438336916 ps
CPU time 7.57 seconds
Started Apr 25 02:36:12 PM PDT 24
Finished Apr 25 02:36:22 PM PDT 24
Peak memory 204092 kb
Host smart-08274a73-d4c0-40ad-a8c6-583d6a699961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42240
5555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.422405555
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2476116609
Short name T319
Test name
Test status
Simulation time 8407363240 ps
CPU time 8.04 seconds
Started Apr 25 02:36:15 PM PDT 24
Finished Apr 25 02:36:25 PM PDT 24
Peak memory 204132 kb
Host smart-d72e3723-5e6f-4223-97d8-72662cdeed17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24761
16609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2476116609
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.3274007872
Short name T179
Test name
Test status
Simulation time 8456835698 ps
CPU time 8.27 seconds
Started Apr 25 02:36:16 PM PDT 24
Finished Apr 25 02:36:26 PM PDT 24
Peak memory 204116 kb
Host smart-1573382c-de23-4d29-a9ea-4f32cbfde0d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32740
07872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.3274007872
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3412375604
Short name T1137
Test name
Test status
Simulation time 8364820411 ps
CPU time 8.28 seconds
Started Apr 25 02:36:12 PM PDT 24
Finished Apr 25 02:36:22 PM PDT 24
Peak memory 204140 kb
Host smart-ebed589b-4e19-4df8-be96-9531f18f14b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34123
75604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3412375604
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.2435124588
Short name T619
Test name
Test status
Simulation time 70959966 ps
CPU time 0.68 seconds
Started Apr 25 02:36:13 PM PDT 24
Finished Apr 25 02:36:15 PM PDT 24
Peak memory 203972 kb
Host smart-e6da83db-be80-447e-a135-7aa7fda3e9e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24351
24588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.2435124588
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.3797123069
Short name T1192
Test name
Test status
Simulation time 19666992545 ps
CPU time 41.91 seconds
Started Apr 25 02:36:12 PM PDT 24
Finished Apr 25 02:36:56 PM PDT 24
Peak memory 204448 kb
Host smart-0aacaa42-91da-4ff5-9fd2-4fd16cc0a584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37971
23069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.3797123069
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.3833419716
Short name T1134
Test name
Test status
Simulation time 8435246769 ps
CPU time 8.21 seconds
Started Apr 25 02:36:14 PM PDT 24
Finished Apr 25 02:36:24 PM PDT 24
Peak memory 204140 kb
Host smart-d052eeaf-d394-464c-a6c7-4226fb717be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38334
19716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.3833419716
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.666575969
Short name T611
Test name
Test status
Simulation time 8447291067 ps
CPU time 8.15 seconds
Started Apr 25 02:36:14 PM PDT 24
Finished Apr 25 02:36:24 PM PDT 24
Peak memory 204100 kb
Host smart-02f03878-d7c4-4cad-ba10-597de3bd064c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66657
5969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.666575969
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.3064973549
Short name T1253
Test name
Test status
Simulation time 8401927234 ps
CPU time 10.08 seconds
Started Apr 25 02:36:13 PM PDT 24
Finished Apr 25 02:36:25 PM PDT 24
Peak memory 204112 kb
Host smart-21eeecee-cd61-4e3f-bf63-027b793ad02c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30649
73549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.3064973549
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.342808958
Short name T174
Test name
Test status
Simulation time 8416148271 ps
CPU time 9.47 seconds
Started Apr 25 02:36:16 PM PDT 24
Finished Apr 25 02:36:27 PM PDT 24
Peak memory 204156 kb
Host smart-9739b44e-f9fe-42c3-b34a-6c1ca5241697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34280
8958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.342808958
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.2237431122
Short name T724
Test name
Test status
Simulation time 8374208711 ps
CPU time 8.28 seconds
Started Apr 25 02:36:18 PM PDT 24
Finished Apr 25 02:36:27 PM PDT 24
Peak memory 204100 kb
Host smart-deccfcd2-bc2c-4229-8814-d14daa34fbaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22374
31122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.2237431122
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.2634641994
Short name T147
Test name
Test status
Simulation time 8441438348 ps
CPU time 8.42 seconds
Started Apr 25 02:36:14 PM PDT 24
Finished Apr 25 02:36:24 PM PDT 24
Peak memory 204120 kb
Host smart-2aaf7cc5-f59b-42d7-b7c7-e3fc9582e955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26346
41994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.2634641994
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.606144002
Short name T403
Test name
Test status
Simulation time 8392499098 ps
CPU time 8.89 seconds
Started Apr 25 02:36:12 PM PDT 24
Finished Apr 25 02:36:23 PM PDT 24
Peak memory 204108 kb
Host smart-b97fc867-673e-4a5a-bc73-f738f60daba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60614
4002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.606144002
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.21533039
Short name T1223
Test name
Test status
Simulation time 8442120854 ps
CPU time 8.13 seconds
Started Apr 25 02:36:13 PM PDT 24
Finished Apr 25 02:36:23 PM PDT 24
Peak memory 204116 kb
Host smart-930a6b28-d4bc-4519-af43-3e3b1d9d1c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21533
039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.21533039
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.2140521438
Short name T157
Test name
Test status
Simulation time 8466246600 ps
CPU time 7.79 seconds
Started Apr 25 02:36:19 PM PDT 24
Finished Apr 25 02:36:28 PM PDT 24
Peak memory 204132 kb
Host smart-53b6b8f0-8cd9-4ba4-bc4c-16f17f2e204c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2140521438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.2140521438
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.1231566342
Short name T876
Test name
Test status
Simulation time 8373531801 ps
CPU time 8.11 seconds
Started Apr 25 02:36:23 PM PDT 24
Finished Apr 25 02:36:32 PM PDT 24
Peak memory 204120 kb
Host smart-29a5f8f5-c5df-40ea-88b2-97de650274d1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1231566342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.1231566342
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.3237357868
Short name T824
Test name
Test status
Simulation time 8437256901 ps
CPU time 7.37 seconds
Started Apr 25 02:36:21 PM PDT 24
Finished Apr 25 02:36:29 PM PDT 24
Peak memory 204112 kb
Host smart-833abeb1-3eb7-4933-b49a-508b83905598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32373
57868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.3237357868
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.3093569273
Short name T1019
Test name
Test status
Simulation time 8374264436 ps
CPU time 7.87 seconds
Started Apr 25 02:36:14 PM PDT 24
Finished Apr 25 02:36:23 PM PDT 24
Peak memory 203904 kb
Host smart-f51eeb7e-9dbb-4da7-a5f8-b23913b4098d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30935
69273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.3093569273
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_enable.3944155866
Short name T1204
Test name
Test status
Simulation time 8388773094 ps
CPU time 8.9 seconds
Started Apr 25 02:36:19 PM PDT 24
Finished Apr 25 02:36:29 PM PDT 24
Peak memory 204072 kb
Host smart-19283aff-7b4b-4039-9ead-668de159a637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39441
55866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.3944155866
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3149217319
Short name T630
Test name
Test status
Simulation time 86803829 ps
CPU time 2.08 seconds
Started Apr 25 02:36:18 PM PDT 24
Finished Apr 25 02:36:21 PM PDT 24
Peak memory 204204 kb
Host smart-55f1170a-2baa-4b0a-be64-457efd42842d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31492
17319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3149217319
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.393842855
Short name T654
Test name
Test status
Simulation time 8435407051 ps
CPU time 9.65 seconds
Started Apr 25 02:36:24 PM PDT 24
Finished Apr 25 02:36:35 PM PDT 24
Peak memory 204156 kb
Host smart-f3c4739f-519a-4bb7-b8d9-eedddb29b10e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39384
2855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.393842855
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.668226020
Short name T879
Test name
Test status
Simulation time 8362952563 ps
CPU time 9.16 seconds
Started Apr 25 02:36:18 PM PDT 24
Finished Apr 25 02:36:28 PM PDT 24
Peak memory 204128 kb
Host smart-39462b3a-b521-41e0-9c29-1552759a2066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66822
6020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.668226020
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.3796956355
Short name T995
Test name
Test status
Simulation time 8442835165 ps
CPU time 10.01 seconds
Started Apr 25 02:36:22 PM PDT 24
Finished Apr 25 02:36:34 PM PDT 24
Peak memory 204152 kb
Host smart-c39755ca-e586-4e96-af1e-ebb15baebeca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37969
56355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.3796956355
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.1320277313
Short name T91
Test name
Test status
Simulation time 8419186862 ps
CPU time 10.34 seconds
Started Apr 25 02:36:19 PM PDT 24
Finished Apr 25 02:36:30 PM PDT 24
Peak memory 204108 kb
Host smart-31729dfc-5002-480f-b74a-cb3c84c1c216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13202
77313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.1320277313
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.1401155235
Short name T314
Test name
Test status
Simulation time 8414721604 ps
CPU time 9.18 seconds
Started Apr 25 02:36:23 PM PDT 24
Finished Apr 25 02:36:34 PM PDT 24
Peak memory 204124 kb
Host smart-9f4fa90a-411f-482a-9176-cb4396fb785e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14011
55235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.1401155235
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.2263167101
Short name T1089
Test name
Test status
Simulation time 8435265467 ps
CPU time 7.74 seconds
Started Apr 25 02:36:23 PM PDT 24
Finished Apr 25 02:36:32 PM PDT 24
Peak memory 204136 kb
Host smart-dd724b28-5f07-4624-95a3-eb6d0afcca78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22631
67101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.2263167101
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1350131027
Short name T679
Test name
Test status
Simulation time 8388994803 ps
CPU time 7.89 seconds
Started Apr 25 02:36:19 PM PDT 24
Finished Apr 25 02:36:28 PM PDT 24
Peak memory 204056 kb
Host smart-7dbf6e76-be8e-442a-a9d9-5e86e0e877ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13501
31027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1350131027
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.754169891
Short name T222
Test name
Test status
Simulation time 8391108402 ps
CPU time 9.57 seconds
Started Apr 25 02:36:24 PM PDT 24
Finished Apr 25 02:36:35 PM PDT 24
Peak memory 204148 kb
Host smart-d23d0369-6216-4cb7-bdab-a5130af7c147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75416
9891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.754169891
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.3232732384
Short name T196
Test name
Test status
Simulation time 8431655671 ps
CPU time 9.65 seconds
Started Apr 25 02:36:21 PM PDT 24
Finished Apr 25 02:36:32 PM PDT 24
Peak memory 204072 kb
Host smart-b12664e5-7541-4225-83a9-881850b5d969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32327
32384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.3232732384
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.1963164324
Short name T1121
Test name
Test status
Simulation time 8414860379 ps
CPU time 7.56 seconds
Started Apr 25 02:36:20 PM PDT 24
Finished Apr 25 02:36:29 PM PDT 24
Peak memory 204140 kb
Host smart-435ebcfc-86d5-4d61-9977-62cde55771ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19631
64324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.1963164324
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.62459961
Short name T1299
Test name
Test status
Simulation time 38550111 ps
CPU time 0.68 seconds
Started Apr 25 02:36:23 PM PDT 24
Finished Apr 25 02:36:25 PM PDT 24
Peak memory 203972 kb
Host smart-f639b149-f9de-476d-b27f-d53e0079c45d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62459
961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.62459961
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.4280518756
Short name T1038
Test name
Test status
Simulation time 23535070143 ps
CPU time 44.65 seconds
Started Apr 25 02:36:19 PM PDT 24
Finished Apr 25 02:37:04 PM PDT 24
Peak memory 204412 kb
Host smart-cad4377d-eb8d-48a6-92d4-8f0f2d27dc8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42805
18756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.4280518756
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.3868700733
Short name T1349
Test name
Test status
Simulation time 8374070715 ps
CPU time 8.04 seconds
Started Apr 25 02:36:22 PM PDT 24
Finished Apr 25 02:36:32 PM PDT 24
Peak memory 204140 kb
Host smart-c46034cb-c655-4013-b163-68c51c77ddb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38687
00733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.3868700733
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.3012519639
Short name T706
Test name
Test status
Simulation time 8396832527 ps
CPU time 9.68 seconds
Started Apr 25 02:36:18 PM PDT 24
Finished Apr 25 02:36:29 PM PDT 24
Peak memory 204040 kb
Host smart-235ce0a3-9e5d-41c2-ad5f-61b4bc27ebdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30125
19639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3012519639
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.2820508690
Short name T975
Test name
Test status
Simulation time 8415346449 ps
CPU time 8.07 seconds
Started Apr 25 02:36:20 PM PDT 24
Finished Apr 25 02:36:30 PM PDT 24
Peak memory 204120 kb
Host smart-0a0a8b62-29ac-43c8-8ea5-941900655560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28205
08690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.2820508690
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.1965918530
Short name T1088
Test name
Test status
Simulation time 8371199176 ps
CPU time 7.25 seconds
Started Apr 25 02:36:22 PM PDT 24
Finished Apr 25 02:36:31 PM PDT 24
Peak memory 204096 kb
Host smart-d22f3b64-be56-4120-9563-dcdb4c6d3cb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19659
18530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1965918530
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2639300163
Short name T1307
Test name
Test status
Simulation time 8393419824 ps
CPU time 8.47 seconds
Started Apr 25 02:36:25 PM PDT 24
Finished Apr 25 02:36:35 PM PDT 24
Peak memory 204156 kb
Host smart-56dbc149-e8c2-4776-a6f9-8313b6e32e7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26393
00163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2639300163
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.2044581214
Short name T148
Test name
Test status
Simulation time 8468224823 ps
CPU time 7.88 seconds
Started Apr 25 02:36:17 PM PDT 24
Finished Apr 25 02:36:26 PM PDT 24
Peak memory 204116 kb
Host smart-be56665b-58f3-4b51-ad84-8a4124dcc975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20445
81214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.2044581214
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.4273145156
Short name T576
Test name
Test status
Simulation time 8389391074 ps
CPU time 8.16 seconds
Started Apr 25 02:36:20 PM PDT 24
Finished Apr 25 02:36:30 PM PDT 24
Peak memory 204144 kb
Host smart-cb52491c-4465-49eb-916a-2196c0413c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42731
45156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.4273145156
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.1575420834
Short name T1368
Test name
Test status
Simulation time 8418295141 ps
CPU time 8.78 seconds
Started Apr 25 02:36:20 PM PDT 24
Finished Apr 25 02:36:30 PM PDT 24
Peak memory 204140 kb
Host smart-e184905d-f55b-44f6-afa2-bf6dedeb9261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15754
20834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.1575420834
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.892501221
Short name T671
Test name
Test status
Simulation time 8469735360 ps
CPU time 9.77 seconds
Started Apr 25 02:36:29 PM PDT 24
Finished Apr 25 02:36:40 PM PDT 24
Peak memory 204148 kb
Host smart-5ecd4c86-8858-4254-81e1-0c6e2cf7bc3b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=892501221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.892501221
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.402279168
Short name T618
Test name
Test status
Simulation time 8375351278 ps
CPU time 7.72 seconds
Started Apr 25 02:36:28 PM PDT 24
Finished Apr 25 02:36:37 PM PDT 24
Peak memory 204120 kb
Host smart-760cd556-c87b-4504-a9b6-652f5386ffad
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=402279168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.402279168
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.854541137
Short name T852
Test name
Test status
Simulation time 8423561971 ps
CPU time 7.67 seconds
Started Apr 25 02:36:30 PM PDT 24
Finished Apr 25 02:36:39 PM PDT 24
Peak memory 204152 kb
Host smart-0294c9d5-77ac-43a0-8c5a-d0cb9262cfe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85454
1137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.854541137
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1064758890
Short name T447
Test name
Test status
Simulation time 8399555925 ps
CPU time 8.27 seconds
Started Apr 25 02:36:23 PM PDT 24
Finished Apr 25 02:36:33 PM PDT 24
Peak memory 204120 kb
Host smart-a4756923-f053-4c6d-b6dd-391406a6c05e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10647
58890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1064758890
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_enable.2139288028
Short name T1251
Test name
Test status
Simulation time 8381458747 ps
CPU time 7.39 seconds
Started Apr 25 02:36:23 PM PDT 24
Finished Apr 25 02:36:32 PM PDT 24
Peak memory 204160 kb
Host smart-2a8ee808-21f2-45d9-883c-d38864a96ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21392
88028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.2139288028
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.586310667
Short name T481
Test name
Test status
Simulation time 60827835 ps
CPU time 1.12 seconds
Started Apr 25 02:36:20 PM PDT 24
Finished Apr 25 02:36:22 PM PDT 24
Peak memory 204184 kb
Host smart-aa24c9a0-cb84-4e3e-8b67-ef5f770398e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58631
0667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.586310667
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.2423280357
Short name T1363
Test name
Test status
Simulation time 8437928302 ps
CPU time 9.47 seconds
Started Apr 25 02:36:29 PM PDT 24
Finished Apr 25 02:36:40 PM PDT 24
Peak memory 204160 kb
Host smart-20b2c722-a2a0-4003-b783-0e48a284b5d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24232
80357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.2423280357
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.1987806065
Short name T522
Test name
Test status
Simulation time 8362624176 ps
CPU time 8.32 seconds
Started Apr 25 02:36:29 PM PDT 24
Finished Apr 25 02:36:38 PM PDT 24
Peak memory 204148 kb
Host smart-d0949ec7-defe-4e6f-908d-193fd7600012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19878
06065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1987806065
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.3439011832
Short name T137
Test name
Test status
Simulation time 8425981105 ps
CPU time 7.95 seconds
Started Apr 25 02:36:20 PM PDT 24
Finished Apr 25 02:36:29 PM PDT 24
Peak memory 204016 kb
Host smart-585efb90-0c2a-4f2a-87dc-59c6444ca82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34390
11832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.3439011832
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.4053404537
Short name T658
Test name
Test status
Simulation time 8413434918 ps
CPU time 8.01 seconds
Started Apr 25 02:36:22 PM PDT 24
Finished Apr 25 02:36:32 PM PDT 24
Peak memory 204132 kb
Host smart-5d9f16c2-57fd-41b6-9e14-880beb00c6db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40534
04537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.4053404537
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.1144625714
Short name T904
Test name
Test status
Simulation time 8371534289 ps
CPU time 7.8 seconds
Started Apr 25 02:36:20 PM PDT 24
Finished Apr 25 02:36:29 PM PDT 24
Peak memory 204076 kb
Host smart-6df7460e-02f7-4d04-8f6a-b5fd7bb0e233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11446
25714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.1144625714
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.2217934702
Short name T1386
Test name
Test status
Simulation time 8441113970 ps
CPU time 8.62 seconds
Started Apr 25 02:36:22 PM PDT 24
Finished Apr 25 02:36:32 PM PDT 24
Peak memory 204152 kb
Host smart-b1aa7646-e1ee-494f-8504-ea20a2bc47f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22179
34702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.2217934702
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3089870027
Short name T1001
Test name
Test status
Simulation time 8413512693 ps
CPU time 7.68 seconds
Started Apr 25 02:36:20 PM PDT 24
Finished Apr 25 02:36:29 PM PDT 24
Peak memory 204148 kb
Host smart-2cd0e756-46b5-443c-8c01-e348a7108d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30898
70027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3089870027
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.1966598424
Short name T1145
Test name
Test status
Simulation time 8424960225 ps
CPU time 7.94 seconds
Started Apr 25 02:36:18 PM PDT 24
Finished Apr 25 02:36:27 PM PDT 24
Peak memory 204044 kb
Host smart-9bf4e2c1-8b44-48d1-be55-4e6e41be5f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19665
98424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.1966598424
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.4255524657
Short name T971
Test name
Test status
Simulation time 8394143489 ps
CPU time 7.73 seconds
Started Apr 25 02:36:26 PM PDT 24
Finished Apr 25 02:36:35 PM PDT 24
Peak memory 204068 kb
Host smart-dde2344d-5d09-438b-8bb8-a955a985b637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42555
24657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.4255524657
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.253159668
Short name T483
Test name
Test status
Simulation time 8373210969 ps
CPU time 8.83 seconds
Started Apr 25 02:36:30 PM PDT 24
Finished Apr 25 02:36:40 PM PDT 24
Peak memory 204148 kb
Host smart-6d6cafec-f9b5-4389-ad11-a39a524122d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25315
9668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.253159668
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1586496187
Short name T878
Test name
Test status
Simulation time 69947842 ps
CPU time 0.65 seconds
Started Apr 25 02:36:25 PM PDT 24
Finished Apr 25 02:36:27 PM PDT 24
Peak memory 204004 kb
Host smart-8cd61777-4cc5-4d60-9713-0ecb76232b02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15864
96187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1586496187
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.827490818
Short name T1068
Test name
Test status
Simulation time 8398293325 ps
CPU time 7.71 seconds
Started Apr 25 02:36:28 PM PDT 24
Finished Apr 25 02:36:37 PM PDT 24
Peak memory 204072 kb
Host smart-048337e7-a608-4011-8f40-787cac8b0b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82749
0818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.827490818
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.704180976
Short name T1115
Test name
Test status
Simulation time 8420673038 ps
CPU time 7.55 seconds
Started Apr 25 02:36:28 PM PDT 24
Finished Apr 25 02:36:37 PM PDT 24
Peak memory 204116 kb
Host smart-833cb61b-57de-4b35-97a9-74da231a75fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70418
0976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.704180976
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.231639121
Short name T941
Test name
Test status
Simulation time 8397823195 ps
CPU time 8.09 seconds
Started Apr 25 02:36:26 PM PDT 24
Finished Apr 25 02:36:35 PM PDT 24
Peak memory 204068 kb
Host smart-413aa309-c4de-4323-bfde-6a554d53f4d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23163
9121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.231639121
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.3126521049
Short name T476
Test name
Test status
Simulation time 8378900563 ps
CPU time 8.94 seconds
Started Apr 25 02:36:26 PM PDT 24
Finished Apr 25 02:36:36 PM PDT 24
Peak memory 204024 kb
Host smart-e60fe3c8-9a68-44f6-bab0-93d48e21795e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31265
21049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3126521049
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.3864224449
Short name T805
Test name
Test status
Simulation time 8375887129 ps
CPU time 7.9 seconds
Started Apr 25 02:36:25 PM PDT 24
Finished Apr 25 02:36:34 PM PDT 24
Peak memory 204128 kb
Host smart-67dfc08f-4267-4235-abd2-c2395709c37b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38642
24449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.3864224449
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1532128299
Short name T1358
Test name
Test status
Simulation time 8431169201 ps
CPU time 7.85 seconds
Started Apr 25 02:36:22 PM PDT 24
Finished Apr 25 02:36:31 PM PDT 24
Peak memory 204136 kb
Host smart-6bd8e8d7-4126-47f7-a5c4-950e3270baae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15321
28299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1532128299
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.2064650161
Short name T357
Test name
Test status
Simulation time 8382834238 ps
CPU time 7.53 seconds
Started Apr 25 02:36:25 PM PDT 24
Finished Apr 25 02:36:34 PM PDT 24
Peak memory 204088 kb
Host smart-3c12d0ac-4246-4830-8b16-d9e3f7b0a3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20646
50161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.2064650161
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.975263863
Short name T1186
Test name
Test status
Simulation time 8374399015 ps
CPU time 8.41 seconds
Started Apr 25 02:36:27 PM PDT 24
Finished Apr 25 02:36:37 PM PDT 24
Peak memory 204128 kb
Host smart-57961b1f-09e0-4b93-89cf-5585dea3b33a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97526
3863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.975263863
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.1770235079
Short name T1029
Test name
Test status
Simulation time 8472257029 ps
CPU time 9.14 seconds
Started Apr 25 02:36:32 PM PDT 24
Finished Apr 25 02:36:44 PM PDT 24
Peak memory 204148 kb
Host smart-13e8e6bc-1660-4d16-a7c7-4ab43b198dd5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1770235079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.1770235079
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.357215325
Short name T413
Test name
Test status
Simulation time 8381596233 ps
CPU time 7.66 seconds
Started Apr 25 02:36:32 PM PDT 24
Finished Apr 25 02:36:42 PM PDT 24
Peak memory 204052 kb
Host smart-d7f37cda-abc0-4ded-bb90-abe1207d71ac
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=357215325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.357215325
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.554340638
Short name T780
Test name
Test status
Simulation time 8468945240 ps
CPU time 9.87 seconds
Started Apr 25 02:36:31 PM PDT 24
Finished Apr 25 02:36:42 PM PDT 24
Peak memory 204148 kb
Host smart-6ae6ffd2-3537-4635-aa45-1374df2a4cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55434
0638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.554340638
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3558565056
Short name T936
Test name
Test status
Simulation time 8384190780 ps
CPU time 7.36 seconds
Started Apr 25 02:36:27 PM PDT 24
Finished Apr 25 02:36:36 PM PDT 24
Peak memory 204128 kb
Host smart-60b809ae-3979-4ff1-8eee-37cb07eb72ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35585
65056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3558565056
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_enable.1872738093
Short name T1184
Test name
Test status
Simulation time 8371676028 ps
CPU time 8.33 seconds
Started Apr 25 02:36:31 PM PDT 24
Finished Apr 25 02:36:40 PM PDT 24
Peak memory 204076 kb
Host smart-459b4944-7a6e-4ebc-a836-d76c41d58410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18727
38093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.1872738093
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.1136904723
Short name T526
Test name
Test status
Simulation time 210988322 ps
CPU time 2.29 seconds
Started Apr 25 02:36:42 PM PDT 24
Finished Apr 25 02:36:45 PM PDT 24
Peak memory 204196 kb
Host smart-6ed0a96e-d945-408d-8648-72558392f8e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11369
04723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.1136904723
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.3448233062
Short name T1131
Test name
Test status
Simulation time 8446526008 ps
CPU time 7.65 seconds
Started Apr 25 02:36:32 PM PDT 24
Finished Apr 25 02:36:42 PM PDT 24
Peak memory 204120 kb
Host smart-a8650ca4-fc84-4b90-8c87-9eb98a29d01d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34482
33062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.3448233062
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.4122157713
Short name T199
Test name
Test status
Simulation time 8381124247 ps
CPU time 8.8 seconds
Started Apr 25 02:36:33 PM PDT 24
Finished Apr 25 02:36:44 PM PDT 24
Peak memory 204096 kb
Host smart-db40c766-a610-4907-8cfa-9ccdf2219b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41221
57713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.4122157713
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.85024263
Short name T535
Test name
Test status
Simulation time 8430519362 ps
CPU time 8.09 seconds
Started Apr 25 02:36:27 PM PDT 24
Finished Apr 25 02:36:37 PM PDT 24
Peak memory 204112 kb
Host smart-c7c7c868-7c75-461a-992f-eb5d4417ea84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85024
263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.85024263
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.1781069276
Short name T771
Test name
Test status
Simulation time 8410662681 ps
CPU time 8.14 seconds
Started Apr 25 02:36:30 PM PDT 24
Finished Apr 25 02:36:40 PM PDT 24
Peak memory 204148 kb
Host smart-d56aec83-6987-43cf-8aa4-c24fb1f1efd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17810
69276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.1781069276
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1010945319
Short name T507
Test name
Test status
Simulation time 8363239438 ps
CPU time 7.45 seconds
Started Apr 25 02:36:30 PM PDT 24
Finished Apr 25 02:36:38 PM PDT 24
Peak memory 204148 kb
Host smart-0b334032-a0ef-41ab-9e83-5e1779da6a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10109
45319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1010945319
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2801320194
Short name T125
Test name
Test status
Simulation time 8424932750 ps
CPU time 9.94 seconds
Started Apr 25 02:36:28 PM PDT 24
Finished Apr 25 02:36:39 PM PDT 24
Peak memory 204116 kb
Host smart-824d16c0-0725-4162-a83e-d7e595d196a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28013
20194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2801320194
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.2370601073
Short name T1040
Test name
Test status
Simulation time 8378261702 ps
CPU time 8.06 seconds
Started Apr 25 02:36:26 PM PDT 24
Finished Apr 25 02:36:35 PM PDT 24
Peak memory 204096 kb
Host smart-f51bbcda-a184-4c0b-9955-37c11c879ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23706
01073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.2370601073
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2465239648
Short name T1098
Test name
Test status
Simulation time 8381313741 ps
CPU time 7.4 seconds
Started Apr 25 02:36:28 PM PDT 24
Finished Apr 25 02:36:37 PM PDT 24
Peak memory 204128 kb
Host smart-3c7cd88f-dbc8-4d51-99b1-fc2ef0b1e040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24652
39648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2465239648
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.661896752
Short name T997
Test name
Test status
Simulation time 8377637711 ps
CPU time 8.09 seconds
Started Apr 25 02:36:31 PM PDT 24
Finished Apr 25 02:36:40 PM PDT 24
Peak memory 204024 kb
Host smart-50d8ec68-80fa-4fa3-aaa3-a318142a1538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66189
6752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.661896752
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3871992422
Short name T992
Test name
Test status
Simulation time 8369643836 ps
CPU time 7.59 seconds
Started Apr 25 02:36:36 PM PDT 24
Finished Apr 25 02:36:45 PM PDT 24
Peak memory 204124 kb
Host smart-6176c2d8-b97a-48bf-8830-dbdd9ec37ccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38719
92422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3871992422
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.4012558641
Short name T563
Test name
Test status
Simulation time 38402642 ps
CPU time 0.64 seconds
Started Apr 25 02:36:32 PM PDT 24
Finished Apr 25 02:36:35 PM PDT 24
Peak memory 203984 kb
Host smart-5cb61d2b-29b5-41c3-8c76-45cf0d104534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40125
58641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.4012558641
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.1537273077
Short name T230
Test name
Test status
Simulation time 14783714874 ps
CPU time 27.13 seconds
Started Apr 25 02:36:27 PM PDT 24
Finished Apr 25 02:36:55 PM PDT 24
Peak memory 204416 kb
Host smart-dbdaf8a4-109a-4a8c-9dbd-1f97246b38e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15372
73077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.1537273077
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3724358091
Short name T349
Test name
Test status
Simulation time 8409768686 ps
CPU time 7.52 seconds
Started Apr 25 02:36:27 PM PDT 24
Finished Apr 25 02:36:36 PM PDT 24
Peak memory 204132 kb
Host smart-2cf903bc-4de4-4d6a-bb95-aa4af6d5b410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37243
58091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3724358091
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1100168045
Short name T1064
Test name
Test status
Simulation time 8483508665 ps
CPU time 8.31 seconds
Started Apr 25 02:36:27 PM PDT 24
Finished Apr 25 02:36:37 PM PDT 24
Peak memory 204040 kb
Host smart-c756e2a0-9ab1-4943-b281-b395e87f74a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11001
68045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1100168045
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.2873218754
Short name T846
Test name
Test status
Simulation time 8381679126 ps
CPU time 8.47 seconds
Started Apr 25 02:36:29 PM PDT 24
Finished Apr 25 02:36:39 PM PDT 24
Peak memory 204156 kb
Host smart-d48d4133-4555-48c0-9d64-dd1093c0ed1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28732
18754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.2873218754
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.2196981170
Short name T182
Test name
Test status
Simulation time 8373763460 ps
CPU time 7.7 seconds
Started Apr 25 02:36:31 PM PDT 24
Finished Apr 25 02:36:40 PM PDT 24
Peak memory 204052 kb
Host smart-c3143d55-49be-4c73-8e7f-401666c996b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21969
81170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.2196981170
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.2981714098
Short name T1377
Test name
Test status
Simulation time 8367569904 ps
CPU time 7.64 seconds
Started Apr 25 02:36:26 PM PDT 24
Finished Apr 25 02:36:35 PM PDT 24
Peak memory 204104 kb
Host smart-0ac30a33-5f0e-4ace-a1c4-ef17959f19f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29817
14098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.2981714098
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.159606940
Short name T183
Test name
Test status
Simulation time 8548735982 ps
CPU time 8.26 seconds
Started Apr 25 02:36:28 PM PDT 24
Finished Apr 25 02:36:38 PM PDT 24
Peak memory 204132 kb
Host smart-d931eea5-3cf1-43c9-9786-b83018013cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15960
6940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.159606940
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.4244269902
Short name T31
Test name
Test status
Simulation time 8416369354 ps
CPU time 8.11 seconds
Started Apr 25 02:36:35 PM PDT 24
Finished Apr 25 02:36:45 PM PDT 24
Peak memory 204156 kb
Host smart-37713655-6a81-4155-9edb-8e923e33485d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42442
69902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.4244269902
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.2752776844
Short name T1321
Test name
Test status
Simulation time 8407291269 ps
CPU time 10.13 seconds
Started Apr 25 02:36:25 PM PDT 24
Finished Apr 25 02:36:36 PM PDT 24
Peak memory 204128 kb
Host smart-257cd75b-fc85-4b76-8f48-39986a3e3296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27527
76844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.2752776844
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.166529680
Short name T1285
Test name
Test status
Simulation time 8470097353 ps
CPU time 7.54 seconds
Started Apr 25 02:30:32 PM PDT 24
Finished Apr 25 02:30:40 PM PDT 24
Peak memory 204088 kb
Host smart-aa5485f6-05e3-461d-8c2c-4c34abd4003b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=166529680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.166529680
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.190142987
Short name T1070
Test name
Test status
Simulation time 8385404102 ps
CPU time 8.55 seconds
Started Apr 25 02:30:33 PM PDT 24
Finished Apr 25 02:30:42 PM PDT 24
Peak memory 204048 kb
Host smart-1dff9c51-345e-4f2f-948e-b55d952a0650
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=190142987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.190142987
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.3298677805
Short name T593
Test name
Test status
Simulation time 8417092747 ps
CPU time 7.83 seconds
Started Apr 25 02:30:03 PM PDT 24
Finished Apr 25 02:30:12 PM PDT 24
Peak memory 204044 kb
Host smart-7035ff48-3903-4c2c-989a-a59b95ec717a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32986
77805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.3298677805
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.615858302
Short name T254
Test name
Test status
Simulation time 8377884385 ps
CPU time 7.34 seconds
Started Apr 25 02:29:53 PM PDT 24
Finished Apr 25 02:30:01 PM PDT 24
Peak memory 204148 kb
Host smart-0da1b64b-d658-4e7f-94cf-2b4c8826b7e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61585
8302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.615858302
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_enable.1407312057
Short name T344
Test name
Test status
Simulation time 8371054350 ps
CPU time 7.54 seconds
Started Apr 25 02:29:54 PM PDT 24
Finished Apr 25 02:30:02 PM PDT 24
Peak memory 204144 kb
Host smart-208c541d-ffc4-4133-a75c-fbe14dac6d60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14073
12057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.1407312057
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.2892210071
Short name T949
Test name
Test status
Simulation time 200865485 ps
CPU time 2.08 seconds
Started Apr 25 02:29:55 PM PDT 24
Finished Apr 25 02:29:58 PM PDT 24
Peak memory 204264 kb
Host smart-4765efab-7146-4bba-b206-d56f4f350e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28922
10071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.2892210071
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.236444690
Short name T2
Test name
Test status
Simulation time 8398003525 ps
CPU time 7.88 seconds
Started Apr 25 02:30:04 PM PDT 24
Finished Apr 25 02:30:14 PM PDT 24
Peak memory 204124 kb
Host smart-35d1bac9-65f9-4e3f-a90e-59ecd0c2be3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23644
4690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.236444690
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.4178129943
Short name T974
Test name
Test status
Simulation time 8378751175 ps
CPU time 8.02 seconds
Started Apr 25 02:30:02 PM PDT 24
Finished Apr 25 02:30:12 PM PDT 24
Peak memory 204076 kb
Host smart-ae02168c-1402-4a21-b55b-cf68fbba3e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41781
29943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.4178129943
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.1682186772
Short name T773
Test name
Test status
Simulation time 8401777352 ps
CPU time 8.21 seconds
Started Apr 25 02:29:55 PM PDT 24
Finished Apr 25 02:30:04 PM PDT 24
Peak memory 204136 kb
Host smart-66b04da5-2585-4821-93df-842291340c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16821
86772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1682186772
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.9794845
Short name T672
Test name
Test status
Simulation time 8418546168 ps
CPU time 7.63 seconds
Started Apr 25 02:30:05 PM PDT 24
Finished Apr 25 02:30:14 PM PDT 24
Peak memory 204152 kb
Host smart-49bad15e-377b-48b2-9e75-722671c493c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97948
45 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.9794845
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.3148629341
Short name T1221
Test name
Test status
Simulation time 8368834359 ps
CPU time 8.14 seconds
Started Apr 25 02:30:03 PM PDT 24
Finished Apr 25 02:30:12 PM PDT 24
Peak memory 204128 kb
Host smart-89d411e1-17b9-4e59-929d-591d758230d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31486
29341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.3148629341
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1697140434
Short name T1296
Test name
Test status
Simulation time 8433198743 ps
CPU time 8.41 seconds
Started Apr 25 02:30:03 PM PDT 24
Finished Apr 25 02:30:12 PM PDT 24
Peak memory 204116 kb
Host smart-230a3163-0b51-47e2-a8d2-a92fe7d04aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16971
40434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1697140434
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.3192922077
Short name T697
Test name
Test status
Simulation time 8391765187 ps
CPU time 8.99 seconds
Started Apr 25 02:30:04 PM PDT 24
Finished Apr 25 02:30:14 PM PDT 24
Peak memory 204052 kb
Host smart-422aee26-07fc-43d5-93f9-0e66832f0124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31929
22077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.3192922077
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.983878394
Short name T871
Test name
Test status
Simulation time 8408402486 ps
CPU time 8.79 seconds
Started Apr 25 02:30:03 PM PDT 24
Finished Apr 25 02:30:13 PM PDT 24
Peak memory 204156 kb
Host smart-43a589f6-020a-4449-ab59-689a6cea51f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98387
8394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.983878394
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.343816598
Short name T774
Test name
Test status
Simulation time 8377206460 ps
CPU time 7.71 seconds
Started Apr 25 02:30:04 PM PDT 24
Finished Apr 25 02:30:13 PM PDT 24
Peak memory 204112 kb
Host smart-7febab03-4d68-46f0-b854-733a66351564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34381
6598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.343816598
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.2952741874
Short name T765
Test name
Test status
Simulation time 8374398611 ps
CPU time 7.49 seconds
Started Apr 25 02:30:02 PM PDT 24
Finished Apr 25 02:30:11 PM PDT 24
Peak memory 204096 kb
Host smart-7311e44b-9bd3-4fed-b004-55861dc5afd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29527
41874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.2952741874
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.283931343
Short name T556
Test name
Test status
Simulation time 129524617 ps
CPU time 0.72 seconds
Started Apr 25 02:30:03 PM PDT 24
Finished Apr 25 02:30:04 PM PDT 24
Peak memory 204016 kb
Host smart-e3bb55be-efcd-49cc-93e0-2a000727a911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28393
1343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.283931343
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.873220843
Short name T519
Test name
Test status
Simulation time 28126793553 ps
CPU time 63.41 seconds
Started Apr 25 02:30:03 PM PDT 24
Finished Apr 25 02:31:07 PM PDT 24
Peak memory 204420 kb
Host smart-3515b9f1-ce0a-47e9-8d99-3e4c35f4f425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87322
0843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.873220843
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.752375682
Short name T1091
Test name
Test status
Simulation time 8448725178 ps
CPU time 7.86 seconds
Started Apr 25 02:30:03 PM PDT 24
Finished Apr 25 02:30:12 PM PDT 24
Peak memory 204120 kb
Host smart-c6832394-fef3-46a5-b01a-965119aea4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75237
5682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.752375682
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.2784748859
Short name T602
Test name
Test status
Simulation time 8451246625 ps
CPU time 8.59 seconds
Started Apr 25 02:30:04 PM PDT 24
Finished Apr 25 02:30:14 PM PDT 24
Peak memory 204188 kb
Host smart-77e1f514-fa54-4dee-8bef-d00bcaea9af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27847
48859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.2784748859
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.2295047786
Short name T1203
Test name
Test status
Simulation time 8408195727 ps
CPU time 7.98 seconds
Started Apr 25 02:30:04 PM PDT 24
Finished Apr 25 02:30:14 PM PDT 24
Peak memory 204144 kb
Host smart-d586e05c-5064-4b0e-9168-4029c545fa74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22950
47786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.2295047786
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.1774633678
Short name T844
Test name
Test status
Simulation time 8398337889 ps
CPU time 9.93 seconds
Started Apr 25 02:30:05 PM PDT 24
Finished Apr 25 02:30:16 PM PDT 24
Peak memory 204100 kb
Host smart-cb3c44a3-e57d-40dc-8238-b445050abaab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17746
33678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.1774633678
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.751212355
Short name T1225
Test name
Test status
Simulation time 8365284858 ps
CPU time 8.26 seconds
Started Apr 25 02:30:03 PM PDT 24
Finished Apr 25 02:30:12 PM PDT 24
Peak memory 204136 kb
Host smart-f0664e22-a9ed-496a-a2d8-c4567add0fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75121
2355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.751212355
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1330555873
Short name T598
Test name
Test status
Simulation time 8445690057 ps
CPU time 9.96 seconds
Started Apr 25 02:29:55 PM PDT 24
Finished Apr 25 02:30:06 PM PDT 24
Peak memory 204152 kb
Host smart-d373c04e-025b-4f4b-b04f-0d6883648ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13305
55873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1330555873
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.3991834471
Short name T945
Test name
Test status
Simulation time 8391104201 ps
CPU time 8.91 seconds
Started Apr 25 02:30:04 PM PDT 24
Finished Apr 25 02:30:15 PM PDT 24
Peak memory 204144 kb
Host smart-bbe53ec2-db59-4749-8469-4ebe27b0c5e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39918
34471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.3991834471
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.3025810988
Short name T317
Test name
Test status
Simulation time 8450176385 ps
CPU time 8.1 seconds
Started Apr 25 02:30:04 PM PDT 24
Finished Apr 25 02:30:14 PM PDT 24
Peak memory 204160 kb
Host smart-468bd929-f597-4d23-8c8f-bf202fe3a99e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30258
10988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.3025810988
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.2080371540
Short name T723
Test name
Test status
Simulation time 8464662542 ps
CPU time 8.23 seconds
Started Apr 25 02:30:38 PM PDT 24
Finished Apr 25 02:30:48 PM PDT 24
Peak memory 204136 kb
Host smart-ed14ca84-5f4e-4078-a09a-3ca7fdf31325
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2080371540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.2080371540
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.368319363
Short name T150
Test name
Test status
Simulation time 8392992178 ps
CPU time 8.12 seconds
Started Apr 25 02:30:38 PM PDT 24
Finished Apr 25 02:30:47 PM PDT 24
Peak memory 204108 kb
Host smart-003125c8-1190-4c9f-8a7f-452e74316b03
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=368319363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.368319363
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.4163491844
Short name T1065
Test name
Test status
Simulation time 8423666756 ps
CPU time 7.8 seconds
Started Apr 25 02:30:38 PM PDT 24
Finished Apr 25 02:30:48 PM PDT 24
Peak memory 204112 kb
Host smart-f3a78ef2-3e1a-4d69-a363-83136a175aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41634
91844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.4163491844
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.3306737282
Short name T486
Test name
Test status
Simulation time 8379787718 ps
CPU time 7.75 seconds
Started Apr 25 02:30:30 PM PDT 24
Finished Apr 25 02:30:39 PM PDT 24
Peak memory 204128 kb
Host smart-e9472855-4b16-44fd-a321-0eab5eca3f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33067
37282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.3306737282
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_enable.4183720932
Short name T1214
Test name
Test status
Simulation time 8385125007 ps
CPU time 8.06 seconds
Started Apr 25 02:30:32 PM PDT 24
Finished Apr 25 02:30:41 PM PDT 24
Peak memory 204152 kb
Host smart-16697ef4-4a3e-4f13-8e9e-191e070c4872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41837
20932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.4183720932
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.2943108479
Short name T529
Test name
Test status
Simulation time 106013569 ps
CPU time 1.32 seconds
Started Apr 25 02:30:32 PM PDT 24
Finished Apr 25 02:30:34 PM PDT 24
Peak memory 204204 kb
Host smart-59b5abf0-e864-4a07-bdb7-cdfd921c4fff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29431
08479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2943108479
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.3486699443
Short name T934
Test name
Test status
Simulation time 8459874956 ps
CPU time 8.04 seconds
Started Apr 25 02:30:38 PM PDT 24
Finished Apr 25 02:30:46 PM PDT 24
Peak memory 204112 kb
Host smart-4d7a6942-d624-4cf3-8649-aa6f4fef5f0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34866
99443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.3486699443
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.2182501074
Short name T637
Test name
Test status
Simulation time 8371105144 ps
CPU time 8.62 seconds
Started Apr 25 02:30:38 PM PDT 24
Finished Apr 25 02:30:48 PM PDT 24
Peak memory 204100 kb
Host smart-81e6fcea-4222-48f0-a9a9-fd97f384497d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21825
01074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.2182501074
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.1027145140
Short name T633
Test name
Test status
Simulation time 8426634442 ps
CPU time 8.14 seconds
Started Apr 25 02:30:34 PM PDT 24
Finished Apr 25 02:30:43 PM PDT 24
Peak memory 204068 kb
Host smart-2b0ef3e1-f901-4e55-91ad-4596d3c85e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10271
45140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.1027145140
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1541441620
Short name T367
Test name
Test status
Simulation time 8441348276 ps
CPU time 7.85 seconds
Started Apr 25 02:30:33 PM PDT 24
Finished Apr 25 02:30:42 PM PDT 24
Peak memory 204032 kb
Host smart-50437029-c784-499b-aa38-b3e395ffdd16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15414
41620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1541441620
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.457417626
Short name T829
Test name
Test status
Simulation time 8377457208 ps
CPU time 10.25 seconds
Started Apr 25 02:30:31 PM PDT 24
Finished Apr 25 02:30:42 PM PDT 24
Peak memory 204100 kb
Host smart-09475539-69a9-4322-a71a-75890b2ad6b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45741
7626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.457417626
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3355866488
Short name T117
Test name
Test status
Simulation time 8442269217 ps
CPU time 8.13 seconds
Started Apr 25 02:30:33 PM PDT 24
Finished Apr 25 02:30:42 PM PDT 24
Peak memory 204028 kb
Host smart-d94351eb-e1ac-4dd6-be69-53d30e9afee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33558
66488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3355866488
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.2063632505
Short name T512
Test name
Test status
Simulation time 8383817425 ps
CPU time 8.69 seconds
Started Apr 25 02:30:33 PM PDT 24
Finished Apr 25 02:30:43 PM PDT 24
Peak memory 204084 kb
Host smart-69470149-2c17-4c41-968e-30d923678223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20636
32505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.2063632505
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.148702777
Short name T757
Test name
Test status
Simulation time 8417552833 ps
CPU time 7.48 seconds
Started Apr 25 02:30:30 PM PDT 24
Finished Apr 25 02:30:38 PM PDT 24
Peak memory 204120 kb
Host smart-fc98cd2f-d6fb-4f28-9198-45431660b06d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14870
2777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.148702777
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.3327096262
Short name T1287
Test name
Test status
Simulation time 8376350762 ps
CPU time 7.27 seconds
Started Apr 25 02:30:41 PM PDT 24
Finished Apr 25 02:30:50 PM PDT 24
Peak memory 204136 kb
Host smart-4d0eab23-f755-465a-a17c-cdda5503ada4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33270
96262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.3327096262
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.4014043097
Short name T1361
Test name
Test status
Simulation time 8455255804 ps
CPU time 9.1 seconds
Started Apr 25 02:30:40 PM PDT 24
Finished Apr 25 02:30:51 PM PDT 24
Peak memory 204140 kb
Host smart-7efa63ee-7728-48c4-ace7-7004a9ce8686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40140
43097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.4014043097
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.4269257345
Short name T899
Test name
Test status
Simulation time 38215696 ps
CPU time 0.65 seconds
Started Apr 25 02:30:40 PM PDT 24
Finished Apr 25 02:30:42 PM PDT 24
Peak memory 203968 kb
Host smart-e86f069a-eedf-4233-acfc-e549672e2b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42692
57345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.4269257345
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.3066489175
Short name T826
Test name
Test status
Simulation time 29880170563 ps
CPU time 69.58 seconds
Started Apr 25 02:30:33 PM PDT 24
Finished Apr 25 02:31:43 PM PDT 24
Peak memory 204316 kb
Host smart-f4e6553c-b5eb-40c6-b580-7f575815e8be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30664
89175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.3066489175
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.907602537
Short name T17
Test name
Test status
Simulation time 8382796639 ps
CPU time 7.85 seconds
Started Apr 25 02:30:37 PM PDT 24
Finished Apr 25 02:30:46 PM PDT 24
Peak memory 204128 kb
Host smart-169736b2-4c89-4148-934f-e8b0b3734215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90760
2537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.907602537
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.3309658049
Short name T1196
Test name
Test status
Simulation time 8399351594 ps
CPU time 7.66 seconds
Started Apr 25 02:30:38 PM PDT 24
Finished Apr 25 02:30:47 PM PDT 24
Peak memory 204120 kb
Host smart-268a3de9-2b93-4f70-a1e0-c96071922799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33096
58049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.3309658049
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.2042892891
Short name T419
Test name
Test status
Simulation time 8397218549 ps
CPU time 7.7 seconds
Started Apr 25 02:30:24 PM PDT 24
Finished Apr 25 02:30:32 PM PDT 24
Peak memory 204072 kb
Host smart-862b6085-b007-4c14-8d5b-9b44f184afc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20428
92891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.2042892891
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.627582384
Short name T947
Test name
Test status
Simulation time 8384514145 ps
CPU time 8.34 seconds
Started Apr 25 02:30:39 PM PDT 24
Finished Apr 25 02:30:49 PM PDT 24
Peak memory 204104 kb
Host smart-7a112ac1-fd92-409a-bb6f-bea6be50d723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62758
2384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.627582384
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.4052525742
Short name T1075
Test name
Test status
Simulation time 8385407800 ps
CPU time 8.78 seconds
Started Apr 25 02:30:40 PM PDT 24
Finished Apr 25 02:30:50 PM PDT 24
Peak memory 204132 kb
Host smart-df9edec8-858b-4bde-85c9-27b284b6d441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40525
25742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.4052525742
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.2626428792
Short name T872
Test name
Test status
Simulation time 8445203435 ps
CPU time 7.99 seconds
Started Apr 25 02:30:31 PM PDT 24
Finished Apr 25 02:30:40 PM PDT 24
Peak memory 204108 kb
Host smart-5d18d58e-6b4c-4bab-8a52-107451113f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26264
28792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.2626428792
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.2735214427
Short name T478
Test name
Test status
Simulation time 8417699764 ps
CPU time 9.34 seconds
Started Apr 25 02:30:36 PM PDT 24
Finished Apr 25 02:30:46 PM PDT 24
Peak memory 204120 kb
Host smart-ebec2922-425d-48b1-ae9d-56d173bf91f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27352
14427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.2735214427
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.3158254571
Short name T569
Test name
Test status
Simulation time 8381907132 ps
CPU time 8.36 seconds
Started Apr 25 02:30:40 PM PDT 24
Finished Apr 25 02:30:49 PM PDT 24
Peak memory 204052 kb
Host smart-150a4a45-136e-49ec-9528-0e1b903f6053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31582
54571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.3158254571
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.1903699940
Short name T415
Test name
Test status
Simulation time 8496328250 ps
CPU time 7.69 seconds
Started Apr 25 02:30:47 PM PDT 24
Finished Apr 25 02:30:56 PM PDT 24
Peak memory 204036 kb
Host smart-a14b4bd2-f435-4865-a8a6-60fba9ae5adc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1903699940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.1903699940
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.2920514383
Short name T830
Test name
Test status
Simulation time 8405242262 ps
CPU time 8.36 seconds
Started Apr 25 02:30:46 PM PDT 24
Finished Apr 25 02:30:55 PM PDT 24
Peak memory 204140 kb
Host smart-f5b4c2ed-190e-4741-a21a-5df1ca35abc5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2920514383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.2920514383
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.3602660779
Short name T1142
Test name
Test status
Simulation time 8459054704 ps
CPU time 7.67 seconds
Started Apr 25 02:30:47 PM PDT 24
Finished Apr 25 02:30:56 PM PDT 24
Peak memory 204140 kb
Host smart-f824aff5-3caa-48e4-ab47-57ca6511827f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36026
60779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.3602660779
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2209221505
Short name T359
Test name
Test status
Simulation time 8435840853 ps
CPU time 8.1 seconds
Started Apr 25 02:30:44 PM PDT 24
Finished Apr 25 02:30:54 PM PDT 24
Peak memory 204152 kb
Host smart-f9e0dc6b-9c81-4107-8273-f93673f860ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22092
21505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2209221505
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_enable.3649527043
Short name T327
Test name
Test status
Simulation time 8376402444 ps
CPU time 7.59 seconds
Started Apr 25 02:30:41 PM PDT 24
Finished Apr 25 02:30:50 PM PDT 24
Peak memory 204120 kb
Host smart-471e6988-62dc-44dd-9d0c-eb829a6e234d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36495
27043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.3649527043
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.4045853863
Short name T49
Test name
Test status
Simulation time 253620505 ps
CPU time 2.16 seconds
Started Apr 25 02:30:41 PM PDT 24
Finished Apr 25 02:30:44 PM PDT 24
Peak memory 204144 kb
Host smart-0729d624-a4d0-4805-bd8d-fd3de0870181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40458
53863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.4045853863
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.4033068385
Short name T1014
Test name
Test status
Simulation time 8400147399 ps
CPU time 8.05 seconds
Started Apr 25 02:30:34 PM PDT 24
Finished Apr 25 02:30:43 PM PDT 24
Peak memory 204040 kb
Host smart-5ff8e70a-7305-490e-ad9d-2b9d3f6d2115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40330
68385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.4033068385
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.1846997663
Short name T639
Test name
Test status
Simulation time 8366514867 ps
CPU time 8.2 seconds
Started Apr 25 02:30:47 PM PDT 24
Finished Apr 25 02:30:57 PM PDT 24
Peak memory 204100 kb
Host smart-163ff6c3-3f88-45b0-90da-934782f9175b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18469
97663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.1846997663
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.596645789
Short name T520
Test name
Test status
Simulation time 8445769965 ps
CPU time 8.05 seconds
Started Apr 25 02:30:39 PM PDT 24
Finished Apr 25 02:30:48 PM PDT 24
Peak memory 204144 kb
Host smart-6ab79b68-dd16-4da1-a715-6f9abf820078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59664
5789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.596645789
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.266838327
Short name T821
Test name
Test status
Simulation time 8447287832 ps
CPU time 8.36 seconds
Started Apr 25 02:30:42 PM PDT 24
Finished Apr 25 02:30:52 PM PDT 24
Peak memory 204132 kb
Host smart-68d54096-e8e1-451c-ba8e-96ea3dfb6661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26683
8327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.266838327
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.1675887179
Short name T450
Test name
Test status
Simulation time 8375470837 ps
CPU time 7.57 seconds
Started Apr 25 02:30:43 PM PDT 24
Finished Apr 25 02:30:52 PM PDT 24
Peak memory 204140 kb
Host smart-434473c2-2eea-4bce-bb87-37431f7f78c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16758
87179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.1675887179
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3338862624
Short name T113
Test name
Test status
Simulation time 8446009359 ps
CPU time 9.09 seconds
Started Apr 25 02:30:31 PM PDT 24
Finished Apr 25 02:30:41 PM PDT 24
Peak memory 204128 kb
Host smart-8f942ada-ca0f-47cb-8b1d-0880ae93bf07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33388
62624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3338862624
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2325838256
Short name T1290
Test name
Test status
Simulation time 8414305072 ps
CPU time 7.86 seconds
Started Apr 25 02:30:40 PM PDT 24
Finished Apr 25 02:30:50 PM PDT 24
Peak memory 204108 kb
Host smart-d6ba3f88-80e6-41a2-832d-a3686236564a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23258
38256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2325838256
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.1368749850
Short name T333
Test name
Test status
Simulation time 8376575275 ps
CPU time 8.52 seconds
Started Apr 25 02:30:44 PM PDT 24
Finished Apr 25 02:30:54 PM PDT 24
Peak memory 204144 kb
Host smart-63378af9-ceef-44f0-b8ee-1f2e8e211ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13687
49850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.1368749850
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.308588885
Short name T186
Test name
Test status
Simulation time 8377585946 ps
CPU time 8.29 seconds
Started Apr 25 02:30:47 PM PDT 24
Finished Apr 25 02:30:57 PM PDT 24
Peak memory 204136 kb
Host smart-9a1e4968-c11c-47d0-b464-ffb7843a02ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30858
8885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.308588885
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.2031115668
Short name T670
Test name
Test status
Simulation time 8372377013 ps
CPU time 8.11 seconds
Started Apr 25 02:30:45 PM PDT 24
Finished Apr 25 02:30:54 PM PDT 24
Peak memory 204120 kb
Host smart-ce3d2624-6523-47ec-9097-64c846c85b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20311
15668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.2031115668
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2832340386
Short name T418
Test name
Test status
Simulation time 42860280 ps
CPU time 0.63 seconds
Started Apr 25 02:30:44 PM PDT 24
Finished Apr 25 02:30:46 PM PDT 24
Peak memory 204032 kb
Host smart-53698d3a-9001-4e4b-a280-480c67ed347c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28323
40386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2832340386
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.1384752831
Short name T259
Test name
Test status
Simulation time 17182837487 ps
CPU time 32.43 seconds
Started Apr 25 02:30:42 PM PDT 24
Finished Apr 25 02:31:16 PM PDT 24
Peak memory 204432 kb
Host smart-e9f2fd0f-2ce7-45c0-adfa-7ec69828d7c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13847
52831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.1384752831
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.113697491
Short name T722
Test name
Test status
Simulation time 8424248730 ps
CPU time 7.51 seconds
Started Apr 25 02:30:43 PM PDT 24
Finished Apr 25 02:30:52 PM PDT 24
Peak memory 204120 kb
Host smart-2418b849-6cd2-490f-b200-529a0ad38b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11369
7491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.113697491
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.1287132807
Short name T1168
Test name
Test status
Simulation time 8389508662 ps
CPU time 9.8 seconds
Started Apr 25 02:30:43 PM PDT 24
Finished Apr 25 02:30:54 PM PDT 24
Peak memory 204152 kb
Host smart-0ce9b41b-6ddd-430d-88fa-11fd8b14fabc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12871
32807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.1287132807
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.2988857671
Short name T1274
Test name
Test status
Simulation time 8372327938 ps
CPU time 8.76 seconds
Started Apr 25 02:30:46 PM PDT 24
Finished Apr 25 02:30:56 PM PDT 24
Peak memory 204120 kb
Host smart-70d01d84-60b1-4345-a95b-92ea52a9286f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29888
57671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.2988857671
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.570690353
Short name T177
Test name
Test status
Simulation time 8375680825 ps
CPU time 7.1 seconds
Started Apr 25 02:30:47 PM PDT 24
Finished Apr 25 02:30:56 PM PDT 24
Peak memory 204028 kb
Host smart-04f915f0-e0d7-4722-b3ee-bfd6458172d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57069
0353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.570690353
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.3265364326
Short name T856
Test name
Test status
Simulation time 8374510293 ps
CPU time 7.94 seconds
Started Apr 25 02:30:46 PM PDT 24
Finished Apr 25 02:30:56 PM PDT 24
Peak memory 204120 kb
Host smart-521adbae-ef32-43cc-8a58-2d825cbb67e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32653
64326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3265364326
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2599734211
Short name T145
Test name
Test status
Simulation time 8425409793 ps
CPU time 8.35 seconds
Started Apr 25 02:30:39 PM PDT 24
Finished Apr 25 02:30:49 PM PDT 24
Peak memory 204112 kb
Host smart-5efb3014-d24d-4df7-965f-34cdf0687f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25997
34211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2599734211
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.1295688608
Short name T329
Test name
Test status
Simulation time 8400901091 ps
CPU time 8.94 seconds
Started Apr 25 02:30:45 PM PDT 24
Finished Apr 25 02:30:55 PM PDT 24
Peak memory 204120 kb
Host smart-da95b454-3ff5-4eb7-8c18-517134cf8771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12956
88608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.1295688608
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.2582368915
Short name T1300
Test name
Test status
Simulation time 8386494217 ps
CPU time 8.03 seconds
Started Apr 25 02:30:42 PM PDT 24
Finished Apr 25 02:30:52 PM PDT 24
Peak memory 204148 kb
Host smart-eb9669a2-9f95-4146-9f6f-b400f8fb5bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25823
68915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.2582368915
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.1239841055
Short name T335
Test name
Test status
Simulation time 8501126193 ps
CPU time 10.01 seconds
Started Apr 25 02:31:00 PM PDT 24
Finished Apr 25 02:31:12 PM PDT 24
Peak memory 204104 kb
Host smart-ea2c76a1-d321-4a71-afb1-2b9b8998798f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1239841055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.1239841055
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.2767561863
Short name T144
Test name
Test status
Simulation time 8380731071 ps
CPU time 8.85 seconds
Started Apr 25 02:31:00 PM PDT 24
Finished Apr 25 02:31:11 PM PDT 24
Peak memory 204104 kb
Host smart-ce8607fc-f7eb-4af7-b736-99eb16216ab9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2767561863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.2767561863
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.579474565
Short name T786
Test name
Test status
Simulation time 8401677570 ps
CPU time 9.8 seconds
Started Apr 25 02:30:54 PM PDT 24
Finished Apr 25 02:31:05 PM PDT 24
Peak memory 204156 kb
Host smart-0f01ab44-d0df-45fc-bb88-22d53fe6d380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57947
4565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.579474565
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.298238076
Short name T667
Test name
Test status
Simulation time 8378227550 ps
CPU time 7.64 seconds
Started Apr 25 02:30:48 PM PDT 24
Finished Apr 25 02:30:57 PM PDT 24
Peak memory 204092 kb
Host smart-54c1c998-2bb8-4ae5-add2-637664c04094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29823
8076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.298238076
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_enable.1235398682
Short name T1340
Test name
Test status
Simulation time 8377466029 ps
CPU time 9.73 seconds
Started Apr 25 02:30:48 PM PDT 24
Finished Apr 25 02:30:59 PM PDT 24
Peak memory 204096 kb
Host smart-0ecec3f2-f5c2-47fe-9942-21883bb2c5a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12353
98682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.1235398682
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.185649582
Short name T1107
Test name
Test status
Simulation time 82140716 ps
CPU time 2.04 seconds
Started Apr 25 02:30:47 PM PDT 24
Finished Apr 25 02:30:50 PM PDT 24
Peak memory 204112 kb
Host smart-ce9aa0ae-3c92-4c33-85c6-5334ed8d8f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18564
9582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.185649582
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.1348291325
Short name T1342
Test name
Test status
Simulation time 8381070652 ps
CPU time 9.65 seconds
Started Apr 25 02:30:56 PM PDT 24
Finished Apr 25 02:31:06 PM PDT 24
Peak memory 204116 kb
Host smart-9e8ddec1-14af-47b4-b559-9cc8eda87872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13482
91325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.1348291325
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1786420303
Short name T206
Test name
Test status
Simulation time 8383079802 ps
CPU time 8.16 seconds
Started Apr 25 02:30:51 PM PDT 24
Finished Apr 25 02:31:00 PM PDT 24
Peak memory 204188 kb
Host smart-8c3c1553-aeca-4df0-a8dd-0b9292faa4c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17864
20303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1786420303
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3698872332
Short name T930
Test name
Test status
Simulation time 8452422959 ps
CPU time 7.79 seconds
Started Apr 25 02:30:47 PM PDT 24
Finished Apr 25 02:30:57 PM PDT 24
Peak memory 204024 kb
Host smart-982c2082-effd-46b9-b587-57c8c95223b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36988
72332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3698872332
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.3436754237
Short name T1152
Test name
Test status
Simulation time 8437054074 ps
CPU time 7.6 seconds
Started Apr 25 02:30:47 PM PDT 24
Finished Apr 25 02:30:56 PM PDT 24
Peak memory 204056 kb
Host smart-d27e5d13-de31-4768-96c3-d7677cb7c76c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34367
54237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.3436754237
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.2806444315
Short name T465
Test name
Test status
Simulation time 8371175879 ps
CPU time 9.96 seconds
Started Apr 25 02:30:48 PM PDT 24
Finished Apr 25 02:30:59 PM PDT 24
Peak memory 204072 kb
Host smart-3f8888e5-ad0d-4402-bf53-2cca6bc3cd42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28064
44315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.2806444315
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.487985685
Short name T1093
Test name
Test status
Simulation time 8431943468 ps
CPU time 9.74 seconds
Started Apr 25 02:30:49 PM PDT 24
Finished Apr 25 02:31:00 PM PDT 24
Peak memory 204116 kb
Host smart-e8dc766d-b6c8-4a8c-a212-83d23ff6f30a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48798
5685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.487985685
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.363377416
Short name T931
Test name
Test status
Simulation time 8396119906 ps
CPU time 9.25 seconds
Started Apr 25 02:30:50 PM PDT 24
Finished Apr 25 02:31:01 PM PDT 24
Peak memory 204144 kb
Host smart-bfa13f8b-b9a9-4669-ae3f-86c869da9298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36337
7416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.363377416
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.89473512
Short name T1315
Test name
Test status
Simulation time 8443760215 ps
CPU time 7.74 seconds
Started Apr 25 02:30:50 PM PDT 24
Finished Apr 25 02:30:59 PM PDT 24
Peak memory 204120 kb
Host smart-192e3a9e-af4f-4ae0-a874-913eef11b577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89473
512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.89473512
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.3949518293
Short name T857
Test name
Test status
Simulation time 8470910821 ps
CPU time 9.71 seconds
Started Apr 25 02:31:00 PM PDT 24
Finished Apr 25 02:31:12 PM PDT 24
Peak memory 204108 kb
Host smart-71cd1761-f22b-4b19-a15c-9c494402569b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39495
18293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.3949518293
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.345256591
Short name T806
Test name
Test status
Simulation time 8364549277 ps
CPU time 8.21 seconds
Started Apr 25 02:30:53 PM PDT 24
Finished Apr 25 02:31:02 PM PDT 24
Peak memory 204044 kb
Host smart-f912eb8a-8476-4293-aa3e-59387deee11f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34525
6591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.345256591
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.1646982833
Short name T1211
Test name
Test status
Simulation time 139976252 ps
CPU time 0.77 seconds
Started Apr 25 02:30:54 PM PDT 24
Finished Apr 25 02:30:56 PM PDT 24
Peak memory 204024 kb
Host smart-9c646ef6-85f1-4620-a335-6d01b6651267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16469
82833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.1646982833
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.788520770
Short name T1248
Test name
Test status
Simulation time 31015439323 ps
CPU time 63.23 seconds
Started Apr 25 02:30:49 PM PDT 24
Finished Apr 25 02:31:54 PM PDT 24
Peak memory 204444 kb
Host smart-7d894e5d-0761-418f-95a8-e024c79d098b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78852
0770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.788520770
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.1864258792
Short name T80
Test name
Test status
Simulation time 8471115493 ps
CPU time 9.95 seconds
Started Apr 25 02:30:49 PM PDT 24
Finished Apr 25 02:31:01 PM PDT 24
Peak memory 204156 kb
Host smart-619e453b-c464-4f89-9e8a-cedf1655f29e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18642
58792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.1864258792
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.1624700762
Short name T929
Test name
Test status
Simulation time 8407944546 ps
CPU time 10.28 seconds
Started Apr 25 02:30:49 PM PDT 24
Finished Apr 25 02:31:01 PM PDT 24
Peak memory 204132 kb
Host smart-908cb0d5-2e3f-401c-8048-1e4d20fb483e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16247
00762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1624700762
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.2916948059
Short name T1053
Test name
Test status
Simulation time 8373070806 ps
CPU time 7.86 seconds
Started Apr 25 02:30:48 PM PDT 24
Finished Apr 25 02:30:57 PM PDT 24
Peak memory 204116 kb
Host smart-e9c8c2e4-612b-4419-b677-2a3502a7b983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29169
48059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.2916948059
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.1242494711
Short name T775
Test name
Test status
Simulation time 8381394279 ps
CPU time 9.36 seconds
Started Apr 25 02:31:13 PM PDT 24
Finished Apr 25 02:31:25 PM PDT 24
Peak memory 204140 kb
Host smart-84ded014-59fd-468d-b1ca-96b3684300de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12424
94711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.1242494711
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2965005650
Short name T474
Test name
Test status
Simulation time 8380797838 ps
CPU time 7.83 seconds
Started Apr 25 02:30:51 PM PDT 24
Finished Apr 25 02:31:00 PM PDT 24
Peak memory 204064 kb
Host smart-b8f18608-6fdc-41f0-ba8f-90fe55870a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29650
05650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2965005650
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.2916063204
Short name T998
Test name
Test status
Simulation time 8433400848 ps
CPU time 9.11 seconds
Started Apr 25 02:30:47 PM PDT 24
Finished Apr 25 02:30:58 PM PDT 24
Peak memory 204144 kb
Host smart-0a702d0a-b433-47ee-a493-acd93b323fe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29160
63204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.2916063204
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.795148293
Short name T488
Test name
Test status
Simulation time 8444652465 ps
CPU time 8.03 seconds
Started Apr 25 02:30:54 PM PDT 24
Finished Apr 25 02:31:03 PM PDT 24
Peak memory 204140 kb
Host smart-6bc64923-e1fd-41aa-8404-ce4d6cd53a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79514
8293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.795148293
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.3972477300
Short name T689
Test name
Test status
Simulation time 8399406894 ps
CPU time 9.1 seconds
Started Apr 25 02:30:49 PM PDT 24
Finished Apr 25 02:30:59 PM PDT 24
Peak memory 204096 kb
Host smart-aa220dc1-60d3-4edd-b97d-66e0c8cb8349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39724
77300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.3972477300
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.max_length_in_transaction.164165395
Short name T1293
Test name
Test status
Simulation time 8464537949 ps
CPU time 7.98 seconds
Started Apr 25 02:31:13 PM PDT 24
Finished Apr 25 02:31:23 PM PDT 24
Peak memory 204152 kb
Host smart-e12a7941-0f73-4ca9-bb36-86fc95573432
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=164165395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.164165395
Directory /workspace/9.max_length_in_transaction/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.3236253135
Short name T943
Test name
Test status
Simulation time 8413377674 ps
CPU time 8.61 seconds
Started Apr 25 02:31:11 PM PDT 24
Finished Apr 25 02:31:22 PM PDT 24
Peak memory 204128 kb
Host smart-fd7fe9d9-cca5-461b-842c-6ff64da14b4a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3236253135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.3236253135
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.327949412
Short name T840
Test name
Test status
Simulation time 8440395547 ps
CPU time 7.63 seconds
Started Apr 25 02:31:13 PM PDT 24
Finished Apr 25 02:31:22 PM PDT 24
Peak memory 204144 kb
Host smart-47944554-1c0d-4830-8ab0-e060e40169b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32794
9412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.327949412
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.1844480155
Short name T980
Test name
Test status
Simulation time 8394314786 ps
CPU time 7.28 seconds
Started Apr 25 02:30:59 PM PDT 24
Finished Apr 25 02:31:08 PM PDT 24
Peak memory 204152 kb
Host smart-ef9795cd-9e20-4d9e-bf05-6b4d2d5e4d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18444
80155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.1844480155
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_enable.3574186485
Short name T1120
Test name
Test status
Simulation time 8386149974 ps
CPU time 7.99 seconds
Started Apr 25 02:31:01 PM PDT 24
Finished Apr 25 02:31:11 PM PDT 24
Peak memory 204148 kb
Host smart-6e80dff5-e2a9-45ca-97bf-f465816073e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35741
86485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.3574186485
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1718243022
Short name T928
Test name
Test status
Simulation time 68464416 ps
CPU time 1.37 seconds
Started Apr 25 02:30:54 PM PDT 24
Finished Apr 25 02:30:56 PM PDT 24
Peak memory 204184 kb
Host smart-1ec7d9c9-73c1-4f1e-a152-da747baa60d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17182
43022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1718243022
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.1905954130
Short name T1100
Test name
Test status
Simulation time 8409770713 ps
CPU time 8.04 seconds
Started Apr 25 02:31:11 PM PDT 24
Finished Apr 25 02:31:21 PM PDT 24
Peak memory 204076 kb
Host smart-7690f280-2a0c-4d00-b5bf-36709256fb32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19059
54130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.1905954130
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.995085745
Short name T200
Test name
Test status
Simulation time 8424764872 ps
CPU time 9.57 seconds
Started Apr 25 02:31:13 PM PDT 24
Finished Apr 25 02:31:24 PM PDT 24
Peak memory 204148 kb
Host smart-bfbdcc71-59f7-4052-a2c8-ef731691c4ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99508
5745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.995085745
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.144794778
Short name T886
Test name
Test status
Simulation time 8420495814 ps
CPU time 8.13 seconds
Started Apr 25 02:30:56 PM PDT 24
Finished Apr 25 02:31:05 PM PDT 24
Peak memory 204072 kb
Host smart-08b37ba0-ac6d-42d0-802e-bd0b9bb97eda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14479
4778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.144794778
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3210440791
Short name T434
Test name
Test status
Simulation time 8423410147 ps
CPU time 8.56 seconds
Started Apr 25 02:30:59 PM PDT 24
Finished Apr 25 02:31:09 PM PDT 24
Peak memory 204104 kb
Host smart-49f9abce-f579-4d69-8b33-9fe344f92996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32104
40791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3210440791
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.2228022015
Short name T224
Test name
Test status
Simulation time 8379552704 ps
CPU time 7.48 seconds
Started Apr 25 02:31:04 PM PDT 24
Finished Apr 25 02:31:12 PM PDT 24
Peak memory 204132 kb
Host smart-9687f99c-b20e-4f0c-9de7-ae4a5cd75bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22280
22015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.2228022015
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.4039444142
Short name T1313
Test name
Test status
Simulation time 8495885181 ps
CPU time 8.18 seconds
Started Apr 25 02:30:56 PM PDT 24
Finished Apr 25 02:31:05 PM PDT 24
Peak memory 204108 kb
Host smart-ad4b1415-fc5e-4eff-907f-755faf3f3249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40394
44142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.4039444142
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.2996187563
Short name T339
Test name
Test status
Simulation time 8409829691 ps
CPU time 7.85 seconds
Started Apr 25 02:30:54 PM PDT 24
Finished Apr 25 02:31:03 PM PDT 24
Peak memory 204116 kb
Host smart-dcc0b8e9-b745-47d5-9132-437f0a380f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29961
87563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2996187563
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.900189233
Short name T1376
Test name
Test status
Simulation time 8420430921 ps
CPU time 8.37 seconds
Started Apr 25 02:30:56 PM PDT 24
Finished Apr 25 02:31:06 PM PDT 24
Peak memory 204112 kb
Host smart-8b69f369-0565-4565-892e-2ec18027bf89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90018
9233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.900189233
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.3612999637
Short name T26
Test name
Test status
Simulation time 8410684364 ps
CPU time 7.91 seconds
Started Apr 25 02:31:03 PM PDT 24
Finished Apr 25 02:31:12 PM PDT 24
Peak memory 204132 kb
Host smart-a8214a1f-4bec-4e99-b651-d1a959e5b981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36129
99637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.3612999637
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.4018461065
Short name T884
Test name
Test status
Simulation time 8372458280 ps
CPU time 8.35 seconds
Started Apr 25 02:31:03 PM PDT 24
Finished Apr 25 02:31:12 PM PDT 24
Peak memory 204032 kb
Host smart-7cd2cd80-349e-4bf9-9264-05b737b915cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40184
61065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.4018461065
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.3052531463
Short name T1054
Test name
Test status
Simulation time 36141497 ps
CPU time 0.67 seconds
Started Apr 25 02:31:12 PM PDT 24
Finished Apr 25 02:31:15 PM PDT 24
Peak memory 204012 kb
Host smart-4fddcd2b-8c42-4980-ada1-651fce50ae7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30525
31463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.3052531463
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.745133088
Short name T285
Test name
Test status
Simulation time 23368382823 ps
CPU time 46.65 seconds
Started Apr 25 02:30:58 PM PDT 24
Finished Apr 25 02:31:46 PM PDT 24
Peak memory 204440 kb
Host smart-c3e821c5-918f-48e9-a2bc-d331ab2f49bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74513
3088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.745133088
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.3572471417
Short name T392
Test name
Test status
Simulation time 8405831963 ps
CPU time 7.81 seconds
Started Apr 25 02:31:02 PM PDT 24
Finished Apr 25 02:31:11 PM PDT 24
Peak memory 204128 kb
Host smart-05c63d21-f5a6-4620-9a9b-802faaaa5897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35724
71417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.3572471417
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.2245842103
Short name T994
Test name
Test status
Simulation time 8422987826 ps
CPU time 8.04 seconds
Started Apr 25 02:30:57 PM PDT 24
Finished Apr 25 02:31:07 PM PDT 24
Peak memory 204136 kb
Host smart-eed772b3-e7cf-4e00-8c74-77d2dfc0101e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22458
42103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.2245842103
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.1236325010
Short name T1224
Test name
Test status
Simulation time 8413694934 ps
CPU time 8.77 seconds
Started Apr 25 02:30:58 PM PDT 24
Finished Apr 25 02:31:08 PM PDT 24
Peak memory 204160 kb
Host smart-ee9a6014-d25f-4869-b2bb-2b1450b1b021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12363
25010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.1236325010
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.272821277
Short name T165
Test name
Test status
Simulation time 8389510956 ps
CPU time 8.93 seconds
Started Apr 25 02:31:07 PM PDT 24
Finished Apr 25 02:31:17 PM PDT 24
Peak memory 204148 kb
Host smart-c17cbad6-cfe7-4c0d-90c0-0fd22010987e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27282
1277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.272821277
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.1236441052
Short name T527
Test name
Test status
Simulation time 8377778817 ps
CPU time 8.1 seconds
Started Apr 25 02:31:00 PM PDT 24
Finished Apr 25 02:31:10 PM PDT 24
Peak memory 204120 kb
Host smart-e3a09f2e-606f-4155-8869-734c5d8b07c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12364
41052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.1236441052
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.667170587
Short name T982
Test name
Test status
Simulation time 8439957331 ps
CPU time 9.5 seconds
Started Apr 25 02:30:56 PM PDT 24
Finished Apr 25 02:31:06 PM PDT 24
Peak memory 204064 kb
Host smart-3fe11e0a-34ac-4c3d-99ac-3bc7f2d91fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66717
0587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.667170587
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.3303169748
Short name T1308
Test name
Test status
Simulation time 8379153175 ps
CPU time 7.95 seconds
Started Apr 25 02:31:01 PM PDT 24
Finished Apr 25 02:31:10 PM PDT 24
Peak memory 204124 kb
Host smart-36e9c42e-47fd-42bf-a6c3-9ee8c896762b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33031
69748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.3303169748
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.4172716594
Short name T862
Test name
Test status
Simulation time 8405523998 ps
CPU time 9.96 seconds
Started Apr 25 02:31:00 PM PDT 24
Finished Apr 25 02:31:12 PM PDT 24
Peak memory 204104 kb
Host smart-3cfe1f56-e107-4863-96f8-ee67d233d62e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41727
16594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.4172716594
Directory /workspace/9.usbdev_stall_trans/latest
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