Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	115522	1		T1	2		T2	2		T3	3
all_values[1]	115522	1		T1	2		T2	2		T3	3
all_values[2]	115522	1		T1	2		T2	2		T3	3
all_values[3]	115522	1		T1	2		T2	2		T3	3
all_values[4]	115522	1		T1	2		T2	2		T3	3
all_values[5]	115522	1		T1	2		T2	2		T3	3
all_values[6]	115522	1		T1	2		T2	2		T3	3
all_values[7]	115522	1		T1	2		T2	2		T3	3
all_values[8]	115522	1		T1	2		T2	2		T3	3
all_values[9]	115522	1		T1	2		T2	2		T3	3
all_values[10]	115522	1		T1	2		T2	2		T3	3
all_values[11]	115522	1		T1	2		T2	2		T3	3
all_values[12]	115522	1		T1	2		T2	2		T3	3
all_values[13]	115522	1		T1	2		T2	2		T3	3
all_values[14]	115522	1		T1	2		T2	2		T3	3
all_values[15]	115522	1		T1	2		T2	2		T3	3
all_values[16]	115522	1		T1	2		T2	2		T3	3
all_values[17]	115522	1		T1	2		T2	2		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2075318	1		T1	36		T2	36		T3	54
auto[1]	4078	1		T16	4		T17	4		T18	4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2074264	1		T1	36		T2	36		T3	54
auto[1]	5132	1		T65	63		T66	122		T67	132

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	114507	1		T1	2		T2	2		T3	3
all_values[0]	auto[0]	auto[1]	120	1		T66	1		T67	5		T68	4
all_values[0]	auto[1]	auto[0]	730	1		T16	4		T17	4		T18	4
all_values[0]	auto[1]	auto[1]	165	1		T65	3		T66	7		T67	3
all_values[1]	auto[0]	auto[0]	114912	1		T1	2		T2	2		T3	3
all_values[1]	auto[0]	auto[1]	136	1		T66	3		T67	1		T69	5
all_values[1]	auto[1]	auto[0]	332	1		T21	3		T36	3		T40	3
all_values[1]	auto[1]	auto[1]	142	1		T65	3		T66	5		T67	7
all_values[2]	auto[0]	auto[0]	115212	1		T1	2		T2	2		T3	3
all_values[2]	auto[0]	auto[1]	138	1		T66	6		T67	4		T69	3
all_values[2]	auto[1]	auto[0]	30	1		T65	1		T67	3		T68	1
all_values[2]	auto[1]	auto[1]	142	1		T65	4		T66	2		T67	1
all_values[3]	auto[0]	auto[0]	115217	1		T1	2		T2	2		T3	3
all_values[3]	auto[0]	auto[1]	147	1		T66	4		T67	5		T68	3
all_values[3]	auto[1]	auto[0]	25	1		T65	1		T66	1		T69	1
all_values[3]	auto[1]	auto[1]	133	1		T65	3		T66	2		T67	2
all_values[4]	auto[0]	auto[0]	115213	1		T1	2		T2	2		T3	3
all_values[4]	auto[0]	auto[1]	135	1		T65	4		T66	4		T67	5
all_values[4]	auto[1]	auto[0]	33	1		T66	1		T67	1		T68	1
all_values[4]	auto[1]	auto[1]	141	1		T65	1		T66	1		T67	2
all_values[5]	auto[0]	auto[0]	115206	1		T1	2		T2	2		T3	3
all_values[5]	auto[0]	auto[1]	144	1		T65	5		T66	6		T67	1
all_values[5]	auto[1]	auto[0]	25	1		T67	1		T268	1		T269	2
all_values[5]	auto[1]	auto[1]	147	1		T66	2		T67	6		T68	1
all_values[6]	auto[0]	auto[0]	115199	1		T1	2		T2	2		T3	3
all_values[6]	auto[0]	auto[1]	155	1		T66	5		T67	2		T68	4
all_values[6]	auto[1]	auto[0]	26	1		T65	1		T68	1		T69	1
all_values[6]	auto[1]	auto[1]	142	1		T65	4		T66	3		T67	6
all_values[7]	auto[0]	auto[0]	115223	1		T1	2		T2	2		T3	3
all_values[7]	auto[0]	auto[1]	140	1		T66	3		T67	5		T270	4
all_values[7]	auto[1]	auto[0]	32	1		T65	1		T66	2		T68	1
all_values[7]	auto[1]	auto[1]	127	1		T65	3		T67	3		T69	5
all_values[8]	auto[0]	auto[0]	115206	1		T1	2		T2	2		T3	3
all_values[8]	auto[0]	auto[1]	126	1		T65	4		T67	7		T68	3
all_values[8]	auto[1]	auto[0]	17	1		T271	1		T268	1		T265	1
all_values[8]	auto[1]	auto[1]	173	1		T65	1		T66	7		T67	1
all_values[9]	auto[0]	auto[0]	115201	1		T1	2		T2	2		T3	3
all_values[9]	auto[0]	auto[1]	147	1		T66	2		T67	6		T68	3
all_values[9]	auto[1]	auto[0]	35	1		T65	4		T67	1		T68	1
all_values[9]	auto[1]	auto[1]	139	1		T66	5		T67	1		T68	1
all_values[10]	auto[0]	auto[0]	115216	1		T1	2		T2	2		T3	3
all_values[10]	auto[0]	auto[1]	144	1		T66	4		T67	2		T69	3
all_values[10]	auto[1]	auto[0]	28	1		T65	3		T67	1		T68	3
all_values[10]	auto[1]	auto[1]	134	1		T66	4		T67	5		T270	6
all_values[11]	auto[0]	auto[0]	115199	1		T1	2		T2	2		T3	3
all_values[11]	auto[0]	auto[1]	164	1		T65	1		T66	5		T67	3
all_values[11]	auto[1]	auto[0]	17	1		T66	3		T268	1		T265	1
all_values[11]	auto[1]	auto[1]	142	1		T65	4		T67	5		T68	1
all_values[12]	auto[0]	auto[0]	115213	1		T1	2		T2	2		T3	3
all_values[12]	auto[0]	auto[1]	120	1		T66	3		T67	2		T69	3
all_values[12]	auto[1]	auto[0]	33	1		T68	5		T69	1		T265	1
all_values[12]	auto[1]	auto[1]	156	1		T65	5		T66	4		T67	5
all_values[13]	auto[0]	auto[0]	115214	1		T1	2		T2	2		T3	3
all_values[13]	auto[0]	auto[1]	160	1		T65	3		T66	7		T67	6
all_values[13]	auto[1]	auto[0]	26	1		T271	1		T272	1		T265	5
all_values[13]	auto[1]	auto[1]	122	1		T65	1		T66	1		T67	2
all_values[14]	auto[0]	auto[0]	115203	1		T1	2		T2	2		T3	3
all_values[14]	auto[0]	auto[1]	158	1		T66	4		T67	5		T68	1
all_values[14]	auto[1]	auto[0]	29	1		T65	1		T66	3		T270	7
all_values[14]	auto[1]	auto[1]	132	1		T66	1		T67	3		T68	4
all_values[15]	auto[0]	auto[0]	115210	1		T1	2		T2	2		T3	3
all_values[15]	auto[0]	auto[1]	148	1		T65	1		T66	3		T67	2
all_values[15]	auto[1]	auto[0]	21	1		T67	1		T271	3		T269	1
all_values[15]	auto[1]	auto[1]	143	1		T65	4		T66	3		T67	5
all_values[16]	auto[0]	auto[0]	115205	1		T1	2		T2	2		T3	3
all_values[16]	auto[0]	auto[1]	149	1		T65	3		T66	6		T67	4
all_values[16]	auto[1]	auto[0]	20	1		T68	1		T273	3		T274	1
all_values[16]	auto[1]	auto[1]	148	1		T65	2		T66	2		T67	4
all_values[17]	auto[0]	auto[0]	115210	1		T1	2		T2	2		T3	3
all_values[17]	auto[0]	auto[1]	121	1		T65	1		T66	5		T67	4
all_values[17]	auto[1]	auto[0]	39	1		T65	1		T67	1		T68	3
all_values[17]	auto[1]	auto[1]	152	1		T65	3		T66	2		T67	2