Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	115522	1		T1	2		T2	2		T3	3
all_pins[1]	115522	1		T1	2		T2	2		T3	3
all_pins[2]	115522	1		T1	2		T2	2		T3	3
all_pins[3]	115522	1		T1	2		T2	2		T3	3
all_pins[4]	115522	1		T1	2		T2	2		T3	3
all_pins[5]	115522	1		T1	2		T2	2		T3	3
all_pins[6]	115522	1		T1	2		T2	2		T3	3
all_pins[7]	115522	1		T1	2		T2	2		T3	3
all_pins[8]	115522	1		T1	2		T2	2		T3	3
all_pins[9]	115522	1		T1	2		T2	2		T3	3
all_pins[10]	115522	1		T1	2		T2	2		T3	3
all_pins[11]	115522	1		T1	2		T2	2		T3	3
all_pins[12]	115522	1		T1	2		T2	2		T3	3
all_pins[13]	115522	1		T1	2		T2	2		T3	3
all_pins[14]	115522	1		T1	2		T2	2		T3	3
all_pins[15]	115522	1		T1	2		T2	2		T3	3
all_pins[16]	115522	1		T1	2		T2	2		T3	3
all_pins[17]	115522	1		T1	2		T2	2		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2077969	1		T1	36		T2	36		T3	54
values[0x1]	1427	1		T16	1		T17	1		T18	1
transitions[0x0=>0x1]	1109	1		T16	1		T17	1		T18	1
transitions[0x1=>0x0]	1121	1		T16	1		T17	1		T18	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	115353	1		T1	2		T2	2		T3	3
all_pins[0]	values[0x1]	169	1		T16	1		T17	1		T18	1
all_pins[0]	transitions[0x0=>0x1]	152	1		T16	1		T17	1		T18	1
all_pins[0]	transitions[0x1=>0x0]	138	1		T21	1		T36	1		T40	1
all_pins[1]	values[0x0]	115367	1		T1	2		T2	2		T3	3
all_pins[1]	values[0x1]	155	1		T21	1		T36	1		T40	1
all_pins[1]	transitions[0x0=>0x1]	137	1		T21	1		T36	1		T40	1
all_pins[1]	transitions[0x1=>0x0]	82	1		T65	1		T67	1		T68	2
all_pins[2]	values[0x0]	115422	1		T1	2		T2	2		T3	3
all_pins[2]	values[0x1]	100	1		T65	2		T67	2		T68	2
all_pins[2]	transitions[0x0=>0x1]	76	1		T67	1		T68	2		T69	2
all_pins[2]	transitions[0x1=>0x0]	52	1		T66	2		T68	1		T271	3
all_pins[3]	values[0x0]	115446	1		T1	2		T2	2		T3	3
all_pins[3]	values[0x1]	76	1		T65	2		T66	2		T67	1
all_pins[3]	transitions[0x0=>0x1]	58	1		T65	2		T66	1		T67	1
all_pins[3]	transitions[0x1=>0x0]	53	1		T65	1		T67	1		T68	2
all_pins[4]	values[0x0]	115451	1		T1	2		T2	2		T3	3
all_pins[4]	values[0x1]	71	1		T65	1		T66	1		T67	1
all_pins[4]	transitions[0x0=>0x1]	55	1		T65	1		T66	1		T68	2
all_pins[4]	transitions[0x1=>0x0]	43	1		T66	1		T67	4		T68	1
all_pins[5]	values[0x0]	115463	1		T1	2		T2	2		T3	3
all_pins[5]	values[0x1]	59	1		T66	1		T67	5		T68	1
all_pins[5]	transitions[0x0=>0x1]	46	1		T66	1		T67	5		T68	1
all_pins[5]	transitions[0x1=>0x0]	55	1		T65	3		T66	1		T69	1
all_pins[6]	values[0x0]	115454	1		T1	2		T2	2		T3	3
all_pins[6]	values[0x1]	68	1		T65	3		T66	1		T69	1
all_pins[6]	transitions[0x0=>0x1]	58	1		T65	2		T66	1		T69	1
all_pins[6]	transitions[0x1=>0x0]	45	1		T67	3		T69	1		T270	1
all_pins[7]	values[0x0]	115467	1		T1	2		T2	2		T3	3
all_pins[7]	values[0x1]	55	1		T65	1		T67	3		T69	1
all_pins[7]	transitions[0x0=>0x1]	35	1		T65	1		T67	3		T270	1
all_pins[7]	transitions[0x1=>0x0]	58	1		T65	1		T66	4		T68	1
all_pins[8]	values[0x0]	115444	1		T1	2		T2	2		T3	3
all_pins[8]	values[0x1]	78	1		T65	1		T66	4		T68	1
all_pins[8]	transitions[0x0=>0x1]	57	1		T65	1		T66	2		T69	3
all_pins[8]	transitions[0x1=>0x0]	46	1		T66	2		T67	1		T268	1
all_pins[9]	values[0x0]	115455	1		T1	2		T2	2		T3	3
all_pins[9]	values[0x1]	67	1		T66	4		T67	1		T68	1
all_pins[9]	transitions[0x0=>0x1]	50	1		T66	2		T67	1		T68	1
all_pins[9]	transitions[0x1=>0x0]	50	1		T67	2		T270	1		T271	1
all_pins[10]	values[0x0]	115455	1		T1	2		T2	2		T3	3
all_pins[10]	values[0x1]	67	1		T66	2		T67	2		T270	2
all_pins[10]	transitions[0x0=>0x1]	51	1		T66	2		T67	2		T270	1
all_pins[10]	transitions[0x1=>0x0]	51	1		T65	2		T67	1		T68	1
all_pins[11]	values[0x0]	115455	1		T1	2		T2	2		T3	3
all_pins[11]	values[0x1]	67	1		T65	2		T67	1		T68	1
all_pins[11]	transitions[0x0=>0x1]	45	1		T68	1		T69	2		T268	2
all_pins[11]	transitions[0x1=>0x0]	44	1		T65	1		T66	2		T271	4
all_pins[12]	values[0x0]	115456	1		T1	2		T2	2		T3	3
all_pins[12]	values[0x1]	66	1		T65	3		T66	2		T67	1
all_pins[12]	transitions[0x0=>0x1]	49	1		T65	2		T66	2		T67	1
all_pins[12]	transitions[0x1=>0x0]	41	1		T68	3		T270	3		T271	2
all_pins[13]	values[0x0]	115464	1		T1	2		T2	2		T3	3
all_pins[13]	values[0x1]	58	1		T65	1		T68	3		T270	4
all_pins[13]	transitions[0x0=>0x1]	40	1		T65	1		T68	1		T270	4
all_pins[13]	transitions[0x1=>0x0]	52	1		T66	1		T67	3		T68	1
all_pins[14]	values[0x0]	115452	1		T1	2		T2	2		T3	3
all_pins[14]	values[0x1]	70	1		T66	1		T67	3		T68	3
all_pins[14]	transitions[0x0=>0x1]	59	1		T66	1		T67	2		T68	2
all_pins[14]	transitions[0x1=>0x0]	62	1		T65	3		T68	1		T270	3
all_pins[15]	values[0x0]	115449	1		T1	2		T2	2		T3	3
all_pins[15]	values[0x1]	73	1		T65	3		T67	1		T68	2
all_pins[15]	transitions[0x0=>0x1]	55	1		T65	2		T67	1		T68	2
all_pins[15]	transitions[0x1=>0x0]	47	1		T66	1		T67	2		T69	2
all_pins[16]	values[0x0]	115457	1		T1	2		T2	2		T3	3
all_pins[16]	values[0x1]	65	1		T65	1		T66	1		T67	2
all_pins[16]	transitions[0x0=>0x1]	49	1		T65	1		T66	1		T67	2
all_pins[16]	transitions[0x1=>0x0]	47	1		T66	2		T67	2		T271	1
all_pins[17]	values[0x0]	115459	1		T1	2		T2	2		T3	3
all_pins[17]	values[0x1]	63	1		T66	2		T67	2		T271	2
all_pins[17]	transitions[0x0=>0x1]	37	1		T66	1		T67	2		T271	1
all_pins[17]	transitions[0x1=>0x0]	155	1		T16	1		T17	1		T18	1